diff --git a/bsp/essemi/es32f0271/.config b/bsp/essemi/es32f0271/.config new file mode 100644 index 0000000000000000000000000000000000000000..15ed9fadcdeec8cb13ace64af79a459d4f28e721 --- /dev/null +++ b/bsp/essemi/es32f0271/.config @@ -0,0 +1,439 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_ES32F0271LT=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# + +# +# PIN Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C2 is not set + +# +# HWtimer Drivers +# +# CONFIG_BSP_USING_HWTIMER1 is not set + +# +# PWM Drivers +# +# CONFIG_BSP_USING_PWM_GP16C2T1 is not set +# CONFIG_BSP_USING_PWM_GP16C2T4 is not set + +# +# RTC Drivers +# +# CONFIG_BSP_USING_RTC is not set + +# +# ADC Drivers +# +# CONFIG_BSP_USING_ADC is not set + +# +# Onboard Peripheral Drivers +# + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/essemi/es32f0271/Kconfig b/bsp/essemi/es32f0271/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..20657830420ecf9c45d5ba7615ce9dbae0837d2e --- /dev/null +++ b/bsp/essemi/es32f0271/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES32F0271LT + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/essemi/es32f0271/README.md b/bsp/essemi/es32f0271/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c50443466b595e0d80c7bb507e4b36ed50dc2d1e --- /dev/null +++ b/bsp/essemi/es32f0271/README.md @@ -0,0 +1,95 @@ +# ES-PDS-ES32F0271 开发板 BSP 说明 +标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。 + +ES-PDS-ES32F0271-V1.1 + +该开发板常用 **板载资源** 如下： + +- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH +- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) +- 常用外设 + - 可调电阻：1个，(PC03) + - LED：2个，(PD03/PB08) + - 五轴按键： +- 常用接口：GPIO、UART、SPI、I2C +- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :---------------- | :----------: | :------------------------------------| +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | GPIOs | +| UART | 支持 | UART1/2/3 | +| SPI | 支持 | SPI1/2 | +| I2C | 支持 | I2C1/2 | +| PWM | 支持 | PWM1/2 | +| TIMER | 支持 | TIMER1 | +| RTC | 支持 | RTC | +| ADC | 支持 | ADC | + +### 1.2 注意事项 + +- 本BSP中，SPI2和PWM2不能同时使用 + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +### 硬件连接 + +使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。 + +ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1 + +### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 31 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [yuzr](https://github.com/essemi-yuzr) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/essemi/es32f0271/SConscript b/bsp/essemi/es32f0271/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..468297b6a99ab9c400a87ed01dcdedc3d60da45d --- /dev/null +++ b/bsp/essemi/es32f0271/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/essemi/es32f0271/SConstruct b/bsp/essemi/es32f0271/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..164265293da6f0f0240d637f812532529b46881b --- /dev/null +++ b/bsp/essemi/es32f0271/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es32f0271/applications/SConscript b/bsp/essemi/es32f0271/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e0c84e8f1426ab2abb2c870cea377371a7c752f3 --- /dev/null +++ b/bsp/essemi/es32f0271/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32f0271/applications/main.c b/bsp/essemi/es32f0271/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..31e31d355d224ddbbb20a84752b06d6733581492 --- /dev/null +++ b/bsp/essemi/es32f0271/applications/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include + +#define LED_PIN 61 + +int main(void) +{ + /* LED pin configuration */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(1000); + } +} diff --git a/bsp/essemi/es32f0271/drivers/Kconfig b/bsp/essemi/es32f0271/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..37265a5ba811e1cec537e98bc0efb68e4b3ef250 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/Kconfig @@ -0,0 +1,102 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + menu "PIN Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + endmenu + + menu "UART Drivers" + config BSP_USING_UART1 + bool "Enable UART1 PB06/PB07(T/R)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART2 + bool "Enable UART2 PA02/PA03(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Enable UART3 PC06/PC07(T/R)" + select RT_USING_SERIAL + default n + endmenu + + menu "SPI Drivers" + config BSP_USING_SPI1 + bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + depends on !BSP_USING_PWM_GP16C2T4 + endmenu + + menu "I2C Drivers" + config BSP_USING_I2C1 + bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)" + select RT_USING_I2C + default n + + config BSP_USING_I2C2 + bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)" + select RT_USING_I2C + default n + endmenu + + menu "HWtimer Drivers" + + config BSP_USING_HWTIMER1 + bool "Using timer1" + select RT_USING_HWTIMER + default n + endmenu + + menu "PWM Drivers" + + config BSP_USING_PWM_GP16C2T1 + bool "Using PWM_1(GP16C2T1) PB01/PB02" + select RT_USING_PWM + default n + + config BSP_USING_PWM_GP16C2T4 + bool "Using PWM2(GP16C2T4) PB12/PB14" + select RT_USING_PWM + default n + depends on !BSP_USING_SPI2 + + endmenu + + menu "RTC Drivers" + config BSP_USING_RTC + bool "Using RTC" + select RT_USING_RTC + default n + endmenu + + menu "ADC Drivers" + config BSP_USING_ADC + bool "Using ADC" + select RT_USING_ADC + default n + endmenu + + endmenu + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/essemi/es32f0271/drivers/SConscript b/bsp/essemi/es32f0271/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..3be3df80c59c61bd23f3d02f367d0a9463b598c9 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/SConscript @@ -0,0 +1,45 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +board.c +''') + +# add gpio code +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): + src += ['drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'): + src += ['drv_spi.c'] + +# add i2c driver code +if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'): + src += ['drv_i2c.c'] + +# add pwm driver code +if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'): + src += ['drv_pwm.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_HWTIMER1'): + src += ['drv_hwtimer.c'] + +# add rtc driver code +if GetDepend(['BSP_USING_RTC']): + src += ['drv_rtc.c'] + +# add adc driver code +if GetDepend(['BSP_USING_ADC']): + src += ['drv_adc.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32f0271/drivers/board.c b/bsp/essemi/es32f0271/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..8ebc351ff1922c195befbd24629a557c95a098f1 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/board.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" +#include "md_gpio.h" + +/** + * @addtogroup es32f0 + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +} + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + /*-------------------------Clock Config-------------------------/ + * Config system clock to 48MHz of which the clock source + * is PLL0. + */ + + // + // Open PLL0/HRC then wait it ready. + // + SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK); + SET_BIT(RCU->CON, RCU_CON_HRCON_MSK); + + /* Wait HRC clock steady. */ + while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK)); + + // + // Change system clock source,PLL0,48MHz. + // + /* Chose PLL0 as system clock. */ + MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS)); + /* Config mul of PLL0. */ + MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS)); + + // + // Start to change system clock and wait it ready. + // + /* Config flash read wait time. */ + MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS)); + /* Start to change. */ + SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK); + + /* Wait system clock ready. */ + while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK)); + + // + // Remember the system clock. + // + SystemCoreClock = 48000000; +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + /* ticks = sysclk / RT_TICK_PER_SECOND */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/*@}*/ +/** + * This function will initial ES32F0 board. + */ +void rt_hw_board_init(void) +{ + /* NVIC Configuration */ + NVIC_Configuration(); + + /*System Clock Configuration */ + SystemClock_Config(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + diff --git a/bsp/essemi/es32f0271/drivers/board.h b/bsp/essemi/es32f0271/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..b1cb44890d2d77bc21a950af016385f833d90a96 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "es32f0271.h" + +#define ES32F0_SRAM_SIZE 0x2000 +#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END ES32F0_SRAM_END + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_adc.c b/bsp/essemi/es32f0271/drivers/drv_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..d111b54f22bbdd263b3fe2df08c7300e91f758df --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_adc.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_adc.h" +#include "md_gpio.h" +#include "md_adc.h" +#include "md_rcu.h" +#include "md_syscfg.h" + +#ifdef RT_USING_ADC + +#define BSP_ADC_CHANNEL_NUM 8 + +/* define adc instance */ +static struct rt_adc_device _device_adc0; + +/* enable or disable adc */ +static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + RT_ASSERT(device != RT_NULL); + + if (enabled) + { + md_adc_enable_ssen_ss0en(ADC); + } + else + { + md_adc_disable_ssen_ss0en(ADC); + } + + return RT_EOK; +} + +static void _adc_channel_config(rt_uint32_t channel) +{ + /* select gpio pin as adc function */ + switch (channel) + { + case 0: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG); + break; + case 1: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG); + break; + case 2: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG); + break; + case 3: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG); + break; + case 4: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG); + break; + case 5: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG); + break; + case 6: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG); + break; + case 7: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG); + break; + default: + break; + } +} + +static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM]; + rt_uint32_t i; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + /* config adc channel */ + _adc_channel_config(channel); + + md_adc_set_swtri_ss0(ADC); + + while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0); + + for (i=0; i +#include +#include "board.h" +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, gpio_index} +#define __ES32F0_PIN_DEFAULT {-1, 0, 0} + +/* ES32F0 GPIO driver */ +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(2, C, 13), + __ES32F0_PIN(3, C, 14), + __ES32F0_PIN(4, C, 15), + __ES32F0_PIN(5, D, 14), + __ES32F0_PIN(6, D, 15), + __ES32F0_PIN(7, D, 13), + __ES32F0_PIN(8, C, 0), + __ES32F0_PIN(9, C, 1), + __ES32F0_PIN(10, C, 2), + __ES32F0_PIN(11, C, 3), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(14, A, 0), + __ES32F0_PIN(15, A, 1), + __ES32F0_PIN(16, A, 2), + __ES32F0_PIN(17, A, 3), + __ES32F0_PIN(18, D, 0), + __ES32F0_PIN(19, D, 1), + __ES32F0_PIN(20, A, 4), + __ES32F0_PIN(21, A, 5), + __ES32F0_PIN(22, A, 6), + __ES32F0_PIN(23, A, 7), + __ES32F0_PIN(24, C, 4), + __ES32F0_PIN(25, C, 5), + __ES32F0_PIN(26, B, 0), + __ES32F0_PIN(27, B, 1), + __ES32F0_PIN(28, B, 2), + __ES32F0_PIN(29, B, 10), + __ES32F0_PIN(30, B, 11), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(33, B, 12), + __ES32F0_PIN(34, B, 13), + __ES32F0_PIN(35, B, 14), + __ES32F0_PIN(36, B, 15), + __ES32F0_PIN(37, C, 6), + __ES32F0_PIN(38, C, 7), + __ES32F0_PIN(39, C, 8), + __ES32F0_PIN(40, C, 9), + __ES32F0_PIN(41, A, 8), + __ES32F0_PIN(42, A, 9), + __ES32F0_PIN(43, A, 10), + __ES32F0_PIN(44, A, 11), + __ES32F0_PIN(45, A, 12), + __ES32F0_PIN(46, A, 13), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(49, A, 14), + __ES32F0_PIN(50, A, 15), + __ES32F0_PIN(51, C, 10), + __ES32F0_PIN(52, C, 11), + __ES32F0_PIN(53, C, 12), + __ES32F0_PIN(54, D, 2), + __ES32F0_PIN(55, B, 3), + __ES32F0_PIN(56, B, 4), + __ES32F0_PIN(57, B, 5), + __ES32F0_PIN(58, B, 6), + __ES32F0_PIN(59, B, 7), + __ES32F0_PIN(60, D, 3), + __ES32F0_PIN(61, B, 8), + __ES32F0_PIN(62, B, 9), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {0, EXTI_0to1_IRQn}, + {1, EXTI_0to1_IRQn}, + {2, EXTI_2to3_IRQn}, + {3, EXTI_2to3_IRQn}, + {4, EXTI_4to15_IRQn}, + {5, EXTI_4to15_IRQn}, + {6, EXTI_4to15_IRQn}, + {7, EXTI_4to15_IRQn}, + {8, EXTI_4to15_IRQn}, + {9, EXTI_4to15_IRQn}, + {10, EXTI_4to15_IRQn}, + {11, EXTI_4to15_IRQn}, + {12, EXTI_4to15_IRQn}, + {13, EXTI_4to15_IRQn}, + {14, EXTI_4to15_IRQn}, + {15, EXTI_4to15_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Write GPIO */ + if (value == 0) + SET_BIT(index->gpio->BSBR, 0x1<<(index->pin+16)); + else + SET_BIT(index->gpio->BSBR, 0x1<pin); +} + +int es32f0_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + /* Read the GPIO value with the spcified index */ + value = (index->gpio->IDATA & (0x1<pin)) != 0; + + return value; +} + +void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_TypeDef *gpiox; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Get the IO port */ + gpiox = index->gpio; + + /* Config GPIO */ + switch(mode) + { + case PIN_MODE_OUTPUT: + { + /* pushpull & output & 16mA */ + MODIFY_REG(gpiox->MOD, (0x3<<(index->pin*2)), (0x1<<(index->pin*2))); + CLEAR_BIT(gpiox->OT, (0x1<pin)); + CLEAR_BIT(gpiox->DS, (0x1<pin)); + break; + } + case PIN_MODE_OUTPUT_OD: + { + /* opendrain & output & 16mA */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x1<pin)); + SET_BIT(gpiox->OT, (0x1<pin)); + CLEAR_BIT(gpiox->DS, (0x1<pin)); + break; + } + case PIN_MODE_INPUT: + { + /* input & no pull & CMOS & filter */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x0<pin)); + SET_BIT(gpiox->IST, (0x1<pin)); + SET_BIT(gpiox->FIR, (0x1<pin)); + break; + } + case PIN_MODE_INPUT_PULLUP: + { + /* input & pull up & CMOS & filter */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); + SET_BIT(gpiox->IST, (0x1<pin)); + SET_BIT(gpiox->FIR, (0x1<pin)); + break; + } + case PIN_MODE_INPUT_PULLDOWN: + { + /* input & pull down & CMOS & filter */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x2<pin)); + SET_BIT(gpiox->IST, (0x1<pin)); + SET_BIT(gpiox->FIR, (0x1<pin)); + break; + } + default: + { + /* output */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x1<pin)); + } + } +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) +{ + rt_int32_t mapindex = gpio_pin & 0x00FF; + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = index->pin & 0x00FF; + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + GPIO_TypeDef *gpiox; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + /* Get the IO port */ + gpiox = index->gpio; + + if (enabled == PIN_IRQ_ENABLE) + { + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + + /* Config EXTI */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + SET_BIT(gpiox->FIR, index->pin); + SET_BIT(gpiox->IST, index->pin); + MODIFY_REG(((uint32_t *)(&EXTI->ICFG1))[index->pin/8], + 0xF<<(index->pin%8), + (((uint32_t)(index->gpio) - AHB2_BASE)/0x400)<<(index->pin%8)); + SET_BIT(EXTI->DB, 0x1<pin); + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + { + /* pull down the pin */ + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x2<pin)); + /* Enable EXTI rising interrupt and disable falling interrupt */ + SET_BIT(EXTI->RTS, (0x1<pin)); + CLEAR_BIT(EXTI->FTS, (0x1<pin)); + break; + } + case PIN_IRQ_MODE_FALLING: + { + /* pull up the pin */ + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); + /* Enable EXTI falling interrupt and disable rising interrupt */ + CLEAR_BIT(EXTI->RTS, (0x1<pin)); + SET_BIT(EXTI->FTS, (0x1<pin)); + break; + } + case PIN_IRQ_MODE_RISING_FALLING: + { + /* pull up the pin */ + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); + /* Enable EXTI falling interrupt and enable rising interrupt */ + SET_BIT(EXTI->RTS, (0x1<pin)); + SET_BIT(EXTI->FTS, (0x1<pin)); + break; + } + } + + /* Enable EXTI interrupt */ + SET_BIT(EXTI->IER, (0x1<pin)); + NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _es32f0_pin_ops = +{ + es32f0_pin_mode, + es32f0_pin_write, + es32f0_pin_read, + es32f0_pin_attach_irq, + es32f0_pin_detach_irq, + es32f0_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + + /* Open IO clock */ + SET_BIT(RCU->AHBEN, RCU_AHBEN_GPDEN_MSK|RCU_AHBEN_GPCEN_MSK \ + |RCU_AHBEN_GPBEN_MSK|RCU_AHBEN_GPAEN_MSK); + + /* register IO device */ + result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) +{ + uint16_t irqno; + /* pin no. convert to dec no. */ + for (irqno = 0; irqno < 16; irqno++) + { + if ((0x01 << irqno) == GPIO_Pin) + { + break; + } + } + if (irqno == 16) + return; + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Read the exti interrupt then clear the flag */ + if ((EXTI->RIF & (0x1<ICR, 0x1< +#include +#include +#include +#include +#include "md_ad16c4t.h" +#include "md_rcu.h" + +#ifdef RT_USING_HWTIMER + +/* Defien the hardware timer control struct */ +struct es32f0_hwtimer_dev +{ + rt_hwtimer_t parent; + AD16C4T_TypeDef *hwtimer_periph; + IRQn_Type IRQn; +}; + +#ifdef BSP_USING_HWTIMER1 +static struct es32f0_hwtimer_dev hwtimer1; + +void BS16T1_IRQHandler(void) +{ + /* if BS16T1 IT */ + if (BS16T1->IFM & AD16C4T_RIF_UI_MSK) + { + SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK); + rt_device_hwtimer_isr(&hwtimer1.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) + { + CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK); + } + } +} +#endif + +static struct rt_hwtimer_info es32f0_hwtimer_info = +{ + 48000000, /* maximum count frequency */ + 1, /* minimum count frequency */ + 65535, /* counter maximum value */ + HWTIMER_CNTMODE_UP +}; + +static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + if (1 == state) + { + /* Set frequency */ + WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1)); + /* Enable timer IT */ + SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK); + NVIC_EnableIRQ(hwtimer->IRQn); + } + else + { + /* Dsiable timer IT */ + SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK); + } +} + +static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, + rt_uint32_t cnt, + rt_hwtimer_mode_t mode) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + WRITE_REG(hwtimer->hwtimer_periph->AR, cnt); + SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); + + return RT_EOK; +} + +static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); +} + +static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + uint32_t hwtimer_count = 0; + + RT_ASSERT(hwtimer != RT_NULL); + + hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT); + + return hwtimer_count; +} + +static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, + rt_uint32_t cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t freq = 0; + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + freq = *(rt_uint32_t *)args; + if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq)) + { + ret = RT_EINVAL; + } + /* Set frequency */ + WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1)); + break; + + case HWTIMER_CTRL_STOP: + CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); + break; + + default: + ret = RT_EINVAL; + break; + } + + return ret; +} + +static struct rt_hwtimer_ops es32f0_hwtimer_ops = +{ + es32f0_hwtimer_init, + es32f0_hwtimer_start, + es32f0_hwtimer_stop, + es32f0_hwtimer_count_get, + es32f0_hwtimer_control +}; + +int rt_hw_hwtimer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_HWTIMER1 + /*Open clock*/ + SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK); + + hwtimer1.hwtimer_periph = BS16T1; + hwtimer1.IRQn = BS16T1_IRQn; + hwtimer1.parent.info = &es32f0_hwtimer_info; + hwtimer1.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#endif + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_hwtimer.h b/bsp/essemi/es32f0271/drivers/drv_hwtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..576671e73537d41c6b8b000b7434e2bbe48fbe68 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_hwtimer.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_HWTIMER_H__ +#define DRV_HWTIMER_H__ + +int rt_hw_hwtimer_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_i2c.c b/bsp/essemi/es32f0271/drivers/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..5d863fc447617652b6e93716375231c992cf8d6d --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_i2c.c @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_i2c.h" +#include "md_i2c.h" +#include "md_gpio.h" + +#ifdef RT_USING_I2C + +#define TIMEOUT 0xF +/* Define I2C hardware SCL timeout */ +#define I2C_TIMING_48MHZ_CLK100KHZ ((0xBU<<28)|(4<<20)|(2<<16)|(0xF<<8)|(0x13)) + +/** + * @brief: I2C receive. + * @param: i2cx, pointer to the I2Cx + * @param: addr, address + * @param: buf, send data buffer + * @param: len, the length of buf + * @param: timout, timeout + * @retval: rt_err_t + */ +static rt_err_t __i2c_master_recv(I2C_TypeDef *i2cx, rt_uint16_t addr, + rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout) +{ + rt_uint32_t rt_timout; + + // + // Config I2C transfer mode + // + md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT); + /* Config slaver address */ + md_i2c_set_con2_sadd(i2cx, addr); + /* Config data size */ + md_i2c_set_con2_nbytes(i2cx, len); + /* Reset TX FIFO */ + md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET); + /* Config mode */ + md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_READ); + /* Config auto-reload */ + md_i2c_set_con2_reload(i2cx, MD_I2C_NORELOAD_MODE); + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE); + /* Start the I2C communication */ + md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION); + + while (len > 0) + { + /* Wait Rx FIFO non-empty */ + rt_timout = timout; + while (md_i2c_is_active_stat_rxe(i2cx) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + *buf++ = md_i2c_recv(i2cx); + len--; + } + + return RT_EOK; +} + +/** + * @brief: I2C send. + * @param: i2cx, pointer to the I2Cx + * @param: addr, address + * @param: buf, send data buffer + * @param: len, the length of buf + * @param: timout, timeout + * @retval: rt_err_t + */ +static rt_err_t __i2c_master_send(I2C_TypeDef *i2cx, rt_uint16_t addr, + rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout) +{ + rt_uint32_t rt_timout; + rt_uint8_t index; + + // + // Config I2C transfer mode + // + md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT); + /* Config slaver address */ + md_i2c_set_con2_sadd(i2cx, addr); + /* Config data size */ + md_i2c_set_con2_nbytes(i2cx, len); + /* Reset TX FIFO */ + md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET); + /* Config mode */ + md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_WRITE); + /* Enable auto-end */ + md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE); + + // + // Check if the bus is busy + // + /* Wait bus to be ready */ + rt_timout = timout; + while ((READ_BIT(i2cx->STAT, I2C_STAT_BUSY_MSK) == I2C_STAT_BUSY_MSK) && (--rt_timout)); + if (rt_timout == 0) + return RT_EBUSY; + + // + // Start to send + // + if (len <= 8) + { + for (index = 0; index < len; index++) + md_i2c_send(i2cx, *buf++); + + len = 0; + } + else + { + for (index = 0; index < 8; index++) + md_i2c_send(i2cx, *buf++); + + len -= 8; + } + + /* Start the I2C communication */ + md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION); + + while (len > 0) + { + rt_timout = timout; + while (md_i2c_is_active_stat_txf(i2cx) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + md_i2c_send(i2cx, *buf++); + len--; + } + + return RT_EOK; +} + +static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + if (msg->flags & RT_I2C_RD) + { + if (__i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + else + { + if (__i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + } + + ret = i; + +out: + i2c_dbg("send stop condition\n"); + + return ret; +} + +const struct rt_i2c_bus_device_ops es32f0_i2c_ops = +{ + es32f0_master_xfer, + RT_NULL, + RT_NULL, +}; + +static void _i2c_init(void) +{ + md_i2c_inittypedef I2C_Init = + { + .Timing = CLK100kHz48M, + .Address1 = 0x55 << 1, + .AddrSize = MD_I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = MD_I2C_DUALADDRESS_DISABLE, + .Address2 = 0xAA, + .Address2Masks = MD_I2C_ADDR2_NOMASK + }; + +#ifdef BSP_USING_I2C1 + /* Open I2C clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C1EN_MSK); + + /* GPIO configuration */ + md_gpio_set_pull (GPIOC, MD_GPIO_PIN_12, MD_GPIO_PULL_UP); + md_gpio_set_pull (GPIOD, MD_GPIO_PIN_2, MD_GPIO_PULL_UP); + md_gpio_set_output_type (GPIOC, MD_GPIO_PIN_12, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_output_type (GPIOD, MD_GPIO_PIN_2, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_mode (GPIOC, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOD, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15(GPIOC, MD_GPIO_PIN_12, MD_GPIO_AF1); + md_gpio_set_function0_7 (GPIOD, MD_GPIO_PIN_2, MD_GPIO_AF1); + + // + // Config I2C + // + md_i2c_init(I2C1, &I2C_Init); +#endif + +#ifdef BSP_USING_I2C2 + /* Open I2C clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C2EN_MSK); + + /* GPIO configuration */ + md_gpio_set_pull (GPIOB, MD_GPIO_PIN_10, MD_GPIO_PULL_UP); + md_gpio_set_pull (GPIOB, MD_GPIO_PIN_11, MD_GPIO_PULL_UP); + md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_10, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_11, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_10, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_11, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_10, MD_GPIO_AF1); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_11, MD_GPIO_AF1); + + // + // Config I2C + // + md_i2c_init(I2C2, &I2C_Init); +#endif +} + +#ifdef BSP_USING_I2C2 +static struct rt_i2c_bus_device i2c_device2; +#endif + +#ifdef BSP_USING_I2C1 +static struct rt_i2c_bus_device i2c_device1; +#endif +int rt_hw_i2c_init(void) +{ + _i2c_init(); + +#ifdef BSP_USING_I2C2 + /* define i2c Instance */ + rt_memset((void *)&i2c_device2, 0, sizeof(struct rt_i2c_bus_device)); + i2c_device2.ops = &es32f0_i2c_ops; + i2c_device2.priv = I2C2; + rt_i2c_bus_device_register(&i2c_device2, "i2c2"); +#endif + +#ifdef BSP_USING_I2C1 + /* define i2c Instance */ + rt_memset((void *)&i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); + i2c_device1.ops = &es32f0_i2c_ops; + i2c_device1.priv = I2C1; + rt_i2c_bus_device_register(&i2c_device1, "i2c1"); +#endif + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_i2c.h b/bsp/essemi/es32f0271/drivers/drv_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..7af06805f70c18188f37725c999eadf1715585cb --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_i2c.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_pwm.c b/bsp/essemi/es32f0271/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..768fcd04cd6b943c5e285e0a87368a202dbd18ed --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_pwm.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include +#include "md_gpio.h" + +/* PWM device control struct */ +struct pwm_dev_ctrl { + AD16C4T_TypeDef *timx; + rt_uint8_t chnm; /* Cannel number */ + struct rt_pwm_configuration *cfg; +}; + +#ifdef BSP_USING_PWM_GP16C2T1 + +/* Remember channel configuration */ +static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t1[2] = { + [0] = { + .channel = 1, + .period = 0, + .pulse = 0 + }, + [1] = { + .channel = 2, + .period = 0, + .pulse = 0 + } +}; + +/* Define static device */ +static struct rt_device_pwm pwm_dev_gp16c2t1; +static struct pwm_dev_ctrl pwm_dev_gp16c2t1_ctrl; +#endif +#ifdef BSP_USING_PWM_GP16C2T4 + +/* Remember channel configuration */ +static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t4[2] = { + [0] = { + .channel = 1, + .period = 0, + .pulse = 0 + }, + [1] = { + .channel = 2, + .period = 0, + .pulse = 0 + } +}; + +/* Define static device */ +static struct rt_device_pwm pwm_dev_gp16c2t4; +static struct pwm_dev_ctrl pwm_dev_gp16c2t4_ctrl; +#endif + +static void pwm_auto_config_freq(AD16C4T_TypeDef *timerx, uint32_t ns) +{ + uint32_t temp_ar; + uint32_t temp_pres = timerx->PRES & 0xFFFF; + uint32_t err_cnt = 0; + + /* Automatic setting frequency division ratio */ + while (err_cnt++ < 65536) + { + temp_ar = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1); + if (temp_ar <= 0xFFFF) + break; + temp_pres++; + } + + /* Write back to PRES */ + timerx->PRES = (uint16_t)(temp_pres & 0xFFFF); + timerx->AR = temp_ar; +} + +static void pwm_set_duty(AD16C4T_TypeDef *timerx, uint8_t ch, uint32_t ns) +{ + uint32_t temp_pres = timerx->PRES & 0xFFFF; + uint64_t tmp = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1); + + if (ch == 1) + WRITE_REG(timerx->CCVAL1, (uint32_t)tmp); + else if (ch == 2) + WRITE_REG(timerx->CCVAL2, (uint32_t)tmp); +} + +static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + rt_err_t ret = RT_EOK; + struct pwm_dev_ctrl *dev_ctrl + = (struct pwm_dev_ctrl *)device->parent.user_data; + struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + AD16C4T_TypeDef *timerx = (AD16C4T_TypeDef *)dev_ctrl->timx; + + switch (cmd) + { + case PWM_CMD_ENABLE: + { + if (cfg->channel == 1) + SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK); + else if (cfg->channel == 2) + SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK); + break; + } + case PWM_CMD_DISABLE: + { + if (cfg->channel == 1) + CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK); + else if (cfg->channel == 2) + CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK); + break; + } + case PWM_CMD_SET: + { + /* count registers max 0xFFFF, auto adjust prescaler */ + pwm_auto_config_freq(timerx, cfg->period); + pwm_set_duty(timerx, cfg->channel, cfg->pulse); + /* Remember configuration */ + dev_ctrl->cfg[cfg->channel-1].period = cfg->period; + dev_ctrl->cfg[cfg->channel-1].pulse = cfg->pulse; + break; + } + case PWM_CMD_GET: + { + cfg->period = dev_ctrl->cfg[cfg->channel-1].period; + cfg->pulse = dev_ctrl->cfg[cfg->channel-1].pulse; + break; + } + + default: + break; + } + return ret; +} + +const static struct rt_pwm_ops es32f0_pwm_ops = +{ + es32f0_pwm_control +}; + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_PWM_GP16C2T1 /* 2 channels */ + /* Open clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); + + /* GPIO configuration */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_1, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_1, MD_GPIO_AF5); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_2, MD_GPIO_AF5); + + /* Timer configuration */ + MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); + MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); + SET_BIT(GP16C2T1->BDCFG, AD16C4T_BDCFG_GOEN_MSK); + SET_BIT(GP16C2T1->CON1, AD16C4T_CON1_CNTEN_MSK); + + pwm_dev_gp16c2t1_ctrl.chnm = 2; + pwm_dev_gp16c2t1_ctrl.timx = GP16C2T1; + pwm_dev_gp16c2t1_ctrl.cfg = pwm_ch_cfg_gp16c2t1; + /* Register PWM device */ + ret = rt_device_pwm_register(&pwm_dev_gp16c2t1, + "pwm1", &es32f0_pwm_ops, &pwm_dev_gp16c2t1_ctrl); +#endif + +#ifdef BSP_USING_PWM_GP16C2T4 /* 2 channels */ + /* Open clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); + + /* GPIO configuration */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_12, MD_GPIO_AF5); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF5); + + /* Timer configuration */ + MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); + MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); + SET_BIT(GP16C2T4->BDCFG, AD16C4T_BDCFG_GOEN_MSK); + SET_BIT(GP16C2T4->CON1, AD16C4T_CON1_CNTEN_MSK); + + pwm_dev_gp16c2t4_ctrl.chnm = 2; + pwm_dev_gp16c2t4_ctrl.timx = GP16C2T4; + pwm_dev_gp16c2t4_ctrl.cfg = pwm_ch_cfg_gp16c2t4; + /* Register PWM device */ + ret = rt_device_pwm_register(&pwm_dev_gp16c2t4, + "pwm2", &es32f0_pwm_ops, &pwm_dev_gp16c2t4_ctrl); +#endif + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/essemi/es32f0271/drivers/drv_pwm.h b/bsp/essemi/es32f0271/drivers/drv_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..12c0364563a16688e71def91ca1c7b89cc8d903d --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.c b/bsp/essemi/es32f0271/drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..23bab4dc16bb58e5e64720118c9adb4c99c41769 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_rtc.c @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_rtc.h" + +#ifdef RT_USING_RTC + +/** + * @brief Time structure + */ +typedef struct +{ + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ +} rtc_time_t; + +/** + * @brief Date structure + */ +typedef struct +{ + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ +} rtc_date_t; + +static rt_uint32_t bcd_to_dec(rt_uint32_t bcd) +{ + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); +} + +static void rtc_get_time(rtc_time_t *time) +{ + rt_uint32_t tmp = RTC->TIME; + + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + + return; +} + +static void rtc_get_date(rtc_date_t *date) +{ + uint32_t tmp = RTC->CAL; + + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((RTC->TIME >> 24) & 0x7); + + return; +} + +static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + struct tm time_temp; + struct tm *pNow; + rt_uint16_t timout = 0xFFF; + rtc_time_t *time = rt_malloc(sizeof(rtc_time_t)); + rtc_date_t *date = rt_malloc(sizeof(rtc_date_t)); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + { + /* Wait RTC data ready then read */ + while ((--timout)&&((RTC->STAT & RTC_STAT_SYNDONE_MSK) != RTC_STAT_SYNDONE_MSK)); + if (timout == 0) + result = RT_ERROR; + /* Read */ + rtc_get_time(time); + rtc_get_date(date); + + time_temp.tm_sec = time->second; + time_temp.tm_min = time->minute; + time_temp.tm_hour = time->hour; + time_temp.tm_wday = date->week - 1; + time_temp.tm_mday = date->day; + time_temp.tm_mon = date->month - 1; + time_temp.tm_year = date->year - 1900 + 2000; + *((time_t *)args) = mktime(&time_temp); + break; + } + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + rt_enter_critical(); + /* converts calendar time time into local time. */ + pNow = localtime((const time_t *)args); + /* copy the statically located variable */ + memcpy(&time_temp, pNow, sizeof(struct tm)); + /* unlock scheduler. */ + rt_exit_critical(); + + time->hour = time_temp.tm_hour; + time->minute = time_temp.tm_min; + time->second = time_temp.tm_sec; + date->year = time_temp.tm_year + 1900 - 2000; + date->month = time_temp.tm_mon + 1; + date->day = time_temp.tm_mday; + /* Stop RTC */ + CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK); + WRITE_REG(RTC->TIME, ((time->hour/10)<hour%10)<minute/10)<minute%10)<second/10)<second%10)<CAL, ((date->year/10)<year%10)<month/10)<month%10)<day/10)<day%10)<CON, RTC_CON_RTCEN_MSK); + break; + } + case RT_DEVICE_CTRL_RTC_GET_ALARM: + break; + + case RT_DEVICE_CTRL_RTC_SET_ALARM: + break; + + default: + break; + } + + rt_free(time); + rt_free(date); + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops es32f0_rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + es32f0_rtc_control +}; +#endif + +static struct rt_device rtc_dev; +#define RTC_SOURCE_LOSC 0x1 +#define RTC_SOURCE_LRC 0x2 +int rt_hw_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + rt_uint16_t timout = 0xFFFF; + rt_uint32_t rtc_clk = 32768-1; + rt_uint8_t rtc_src = RTC_SOURCE_LOSC; + + /* + * Config RTC clock + * We config the external 32.768K crystal as RTC clock source for the first + * choice. If external 32.768K crystal is not ready, we will choose LRC. + */ + /* Enable LOSC then wait it ready */ + if ((RCU->CON & RCU_CON_LOSCON_MSK) != RCU_CON_LOSCON_MSK) + SET_BIT(RCU->CON, RCU_CON_LOSCON_MSK); + + /* Wait external 32.768K crystal ready */ + while (((RCU->CON & RCU_CON_LOSCRDY_MSK) != RCU_CON_LOSCRDY_MSK)&&(--timout)); + if (timout == 0) + { + /* We use LRC if external 32.768K crystal is not ready */ + if ((RCU->CON & RCU_CON_LRCON_MSK) != RCU_CON_LRCON_MSK) + SET_BIT(RCU->CON, RCU_CON_LRCON_MSK); + /* Wait LRC ready */ + timout = 0xFF; + while (((RCU->CON & RCU_CON_LRCRDY_MSK) != RCU_CON_LRCRDY_MSK)&&(--timout)); + rtc_clk = 32000-1; + rtc_src = RTC_SOURCE_LRC; + } + + /* Open RTC clock */ + SET_BIT(RCU->AHBEN, RCU_AHBEN_RTCEN_MSK); + + /* Reset RTC */ + SET_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK); + CLEAR_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK); + CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK); + + /* Config RTC clock source */ + MODIFY_REG(RTC->CON, RTC_CON_CKSEL_MSK, rtc_src<CON, RTC_CON_PSCALE_MSK|RTC_CON_SCALE_MSK, + ((rtc_clk&0x7F)<>7)&0xFF)<TIME, (0x3<CAL, (0x1<CON, RTC_CON_RTCEN_MSK); + + rtc_dev.type = RT_Device_Class_RTC; + rtc_dev.rx_indicate = RT_NULL; + rtc_dev.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + rtc_dev.ops = &es32f0_rtc_ops; +#else + rtc_dev.init = RT_NULL; + rtc_dev.open = RT_NULL; + rtc_dev.close = RT_NULL; + rtc_dev.read = RT_NULL; + rtc_dev.write = RT_NULL; + rtc_dev.control = es32f0_rtc_control; +#endif + + rtc_dev.user_data = RTC; + + ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.h b/bsp/essemi/es32f0271/drivers/drv_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..0fd0661026b7974e3d680cf30965912a7803421b --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_rtc.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_RTC_H__ +#define DRV_RTC_H__ + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_spi.c b/bsp/essemi/es32f0271/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..9a7fc3ab7064fc4462b3a0ac01cb1e33448bb600 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_spi.c @@ -0,0 +1,439 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_spi.h" +#include "md_spi.h" +#include "md_gpio.h" + +#ifdef RT_USING_SPI + +#define SPITIMEOUT 0x0FFF + +static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout); +static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout); +static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf, + rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout); + +/** + * @brief: SPI single line send. + * @param: device, pointer to the SPI device + * @param: buf, send data buffer + * @param: len, the length of buf + * @param: tmout, timeout + * @retval: rt_err_t + */ +static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout) +{ + SPI_TypeDef *hspi; + rt_uint32_t rt_timout; + rt_uint8_t temp_data; + + /* Get the SPI port */ + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Open SPI if it is disabled */ + if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) + SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); + + while (len > 0) + { + /* Confirm that no data is being transmitted */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + hspi->DATA = *(rt_uint8_t *)buf; + buf++; + len--; + } + else if (device->config.data_width == 16) + { + hspi->DATA = *(rt_uint16_t *)buf; + buf += 2; + len -= 2; + } + else + return RT_EINVAL; + } + + /* At here, we have transmitted all the data. + * The next step is to clear the IT flag. + */ + for (rt_uint8_t i = 0; i < md_spi_get_stat_rxflv(hspi); i++) + temp_data = hspi->DATA; + UNUSED(temp_data); + hspi->ICR = hspi->RIF; + + return RT_EOK; +} + +/** + * @brief: SPI single line receive. + * @param: device, pointer to the SPI device + * @param: buf, receive data buffer + * @param: len, the length of buf + * @param: tmout, timeout + * @retval: rt_err_t + */ +static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout) +{ + SPI_TypeDef *hspi; + rt_uint32_t rt_timout; + + /* Get the SPI port */ + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Open SPI if it is disabled */ + if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) + SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); + + /* Handle data in __spi_send_recv() function */ + if (((device->config.mode & RT_SPI_SLAVE) == 0) + && ((device->config.mode & RT_SPI_3WIRE) == 0)) + __spi_send_recv(device, buf, buf, len, tmout); + + while (len > 0) + { + /* Waiting for data */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + *(rt_uint8_t *)buf = hspi->DATA; + buf++; + len--; + } + else if (device->config.data_width == 16) + { + *(rt_uint16_t *)buf = hspi->DATA; + buf += 2; + len -= 2; + } + else + return RT_EINVAL; + } + + /* At here, we have transmitted all the data. + * The next step is to clear the IT flag. + */ + hspi->ICR = hspi->RIF; + + return RT_EOK; +} + +/** + * @brief: SPI two line transmission. + * @param: device, pointer to the SPI device + * @param: tbuf, send data buffer + * @param: rbuf, receive data buffer + * @param: len, the length of buf + * @param: tmout, timeout + * @retval: rt_err_t + */ +static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf, + rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout) +{ + SPI_TypeDef *hspi; + rt_uint32_t rt_timout; + + /* Get the SPI port */ + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Open SPI if it is disabled */ + if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) + SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); + + /* return error if SPI is in 1-line mode */ + if ((device->config.mode & RT_SPI_3WIRE) == RT_SPI_3WIRE) + return RT_ERROR; + + while (len > 0) + { + /* Confirm that no data is being transmitted */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + hspi->DATA = *(rt_uint8_t *)tbuf; + tbuf++; + len--; + } + else if (device->config.data_width == 16) + { + hspi->DATA = *(rt_uint16_t *)tbuf; + tbuf += 2; + len -= 2; + } + else + return RT_EINVAL; + + /* Waiting for data */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + *(rt_uint8_t *)rbuf = hspi->DATA; + rbuf++; + } + else if (device->config.data_width == 16) + { + *(rt_uint16_t *)rbuf = hspi->DATA; + rbuf += 2; + } + } + + /* At here, we have transmitted all the data. + * The next step is to clear the IT flag. + */ + hspi->ICR = hspi->RIF; + + return RT_EOK; +} + +rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *cfg) +{ + SPI_TypeDef *hspi; + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Close SPI temporarily */ + md_spi_disable_con1_spien(hspi); + + /* config spi mode */ + if (cfg->mode & RT_SPI_SLAVE) + md_spi_set_con1_mstren(hspi, MD_SPI_MODE_SLAVE); + else + md_spi_set_con1_mstren(hspi, MD_SPI_MODE_MASTER); + + /* Config data mode */ + if (cfg->mode & RT_SPI_3WIRE) + md_spi_set_con1_bidimode(hspi, MD_SPI_HALF_DUPLEX); + else + md_spi_set_con1_bidimode(hspi, MD_SPI_FULL_DUPLEX); + + /* Config data width */ + if (cfg->data_width == 8) + md_spi_set_con1_flen(hspi, MD_SPI_FRAME_FORMAT_8BIT); + else if (cfg->data_width == 16) + md_spi_set_con1_flen(hspi, SPI_CON1_FLEN_MSK); + + /* Config phase */ + if (cfg->mode & RT_SPI_CPHA) + md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_2EDGE); + else + md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_1EDGE); + + /* Config polarity */ + if (cfg->mode & RT_SPI_CPOL) + md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_HIGH); + else + md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_LOW); + + /* Config if NSS pin is managed by software */ + md_spi_disable_con1_ssen(hspi); + + /* config spi clock */ + if (cfg->max_hz >= SystemCoreClock / 2) + { + /* pclk1 max speed 48MHz, spi master max speed 10MHz */ + if (SystemCoreClock / 2 <= 10000000) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV2); + else if (SystemCoreClock / 4 <= 10000000) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4); + else + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); + } + else if (cfg->max_hz >= SystemCoreClock / 4) + { + /* pclk1 max speed 48MHz, spi master max speed 10MHz */ + if (SystemCoreClock / 4 <= 10000000) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4); + else + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); + } + else if (cfg->max_hz >= SystemCoreClock / 8) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); + else if (cfg->max_hz >= SystemCoreClock / 16) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV16); + else if (cfg->max_hz >= SystemCoreClock / 32) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV32); + else if (cfg->max_hz >= SystemCoreClock / 64) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV64); + else if (cfg->max_hz >= SystemCoreClock / 128) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV128); + else + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV256); + + /* Enable SPI */ + md_spi_enable_con1_spien(hspi); + + return RT_EOK; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + rt_uint32_t *cs; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + cs = (rt_uint32_t *)device->parent.user_data; + + /* only send data */ + if (message->recv_buf == RT_NULL) + { + if (message->cs_take) + { + rt_pin_write(*cs, 0); + } + res = __spi_send(device, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(*cs, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + /* only receive data */ + if (message->send_buf == RT_NULL) + { + if (message->cs_take) + { + rt_pin_write(*cs, 0); + } + res = __spi_recv(device, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(*cs, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + /* send & receive */ + else + { + if (message->cs_take) + { + rt_pin_write(*cs, 0); + } + res = __spi_send_recv(device, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(*cs, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + return message->length; +} + +const struct rt_spi_ops es32f0_spi_ops = +{ + spi_configure, + spixfer, +}; + +static struct rt_spi_bus _spi_bus1, _spi_bus2; +int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) +{ + struct rt_spi_bus *spi_bus; + + if (SPIx == SPI2) + { + /* Open GPIO and SPI clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_SPI2EN_MSK); + SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK); + + /* Config SPI2 GPIO */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_13, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_15, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_13, MD_GPIO_AF0); + md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF0); + md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_15, MD_GPIO_AF0); + + /* Remember SPI bus2 */ + spi_bus = &_spi_bus2; + } + else if (SPIx == SPI1) + { + /* Open GPIO and SPI clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_SPI1EN_MSK); + SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK); + + /* Config SPI1 GPIO */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_4, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_5, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_3, MD_GPIO_AF0); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_4, MD_GPIO_AF0); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_5, MD_GPIO_AF0); + + /* Remember SPI bus1 */ + spi_bus = &_spi_bus1; + } + else + { + return -1; + } + spi_bus->parent.user_data = SPIx; + + return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops); +} + +int rt_hw_spi_init(void) +{ + int result = 0; + +#ifdef BSP_USING_SPI2 + result = es32f0_spi_register_bus(SPI2, "spi2"); +#endif + +#ifdef BSP_USING_SPI1 + result = es32f0_spi_register_bus(SPI1, "spi1"); +#endif + + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_spi.h b/bsp/essemi/es32f0271/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..c7c8a13b4ad287e69804fa81dff9b7565a714e78 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_spi.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include +#include +#include + +///* cannot be used before completion init */ +//rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_uart.c b/bsp/essemi/es32f0271/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..f860c2df91e2c0200212e13c7613fb40e8167f38 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_uart.c @@ -0,0 +1,296 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "md_gpio.h" +#include "md_uart.h" + +#ifdef RT_USING_SERIAL + +/* es32 uart driver */ +struct es32_uart +{ + UART_TypeDef *huart; + IRQn_Type irq; +}; + +static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Close TX/RX temporarily */ + md_uart_disable_lcon_txen(uart->huart); + md_uart_disable_lcon_rxen(uart->huart); + +#ifdef BSP_USING_UART1 + /* Open UART1 clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_UART1EN_MSK); + + /* Config UART1 GPIO pin */ + md_gpio_set_pull (GPIOB, MD_GPIO_PIN_7, MD_GPIO_PULL_UP); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_6, MD_GPIO_AF2); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_7, MD_GPIO_AF2); +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART2 + /* Open UART2 clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_UART2EN_MSK); + + /* Config UART2 GPIO pin */ + md_gpio_set_pull (GPIOA, MD_GPIO_PIN_3, MD_GPIO_PULL_UP); + md_gpio_set_mode (GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_2, MD_GPIO_AF2); + md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_3, MD_GPIO_AF2); +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART3 + /* Open UART3 clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_UART3EN_MSK); + + /* Config UART3 GPIO pin */ + md_gpio_set_pull (GPIOC, MD_GPIO_PIN_7, MD_GPIO_PULL_UP); + md_gpio_set_mode (GPIOC, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOC, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_6, MD_GPIO_AF2); + md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_7, MD_GPIO_AF2); +#endif /* uart3 gpio init */ + + if (cfg->bit_order == BIT_ORDER_MSB) + { + md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_MSB_FIRST); + } + else + { + md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_LSB_FIRST); + } + + if (cfg->invert == NRZ_INVERTED) + { + md_uart_enable_lcon_datainv(uart->huart); + } + else + { + md_uart_disable_lcon_datainv(uart->huart); + } + + /* Config buadrate */ + md_uart_set_brr(uart->huart, SystemCoreClock/cfg->baud_rate); + /* Config data width */ + md_uart_set_lcon_dls(uart->huart, 8-cfg->data_bits); + /* Config stop bits */ + md_uart_set_lcon_stop(uart->huart, cfg->stop_bits); + /* Config parity */ + if (cfg->parity > PARITY_NONE) + { + md_uart_set_lcon_ps(uart->huart, cfg->parity-1); + md_uart_enable_lcon_pe(uart->huart); + } + else + md_uart_disable_lcon_pe(uart->huart); + + /* enable rx int */ + md_uart_set_fcon_rxth(uart->huart, MD_UART_FCON_RXTH_1); + md_uart_enable_ier_rfth(uart->huart); + md_uart_enable_lcon_txen(uart->huart); + md_uart_enable_lcon_rxen(uart->huart); + + return RT_EOK; +} + +static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + md_uart_disable_idr_rfth(uart->huart); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + md_uart_enable_ier_rfth(uart->huart); + break; + } + + return RT_EOK; +} + +static int es32f0x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (uart->huart->STAT & UART_STAT_TSBUSY_MSK); + WRITE_REG(uart->huart->TXBUF, c); + + return 1; +} + +static int es32f0x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (uart->huart->STAT & UART_STAT_RFTH_MSK) + { + ch = (uint8_t)(uart->huart->RXBUF & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f0x_uart_ops = +{ + es32f0x_configure, + es32f0x_control, + es32f0x_putc, + es32f0x_getc, +}; + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +struct es32_uart uart1 = +{ + UART1, + UART1_IRQn +}; + +struct rt_serial_device serial1; + +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (md_uart_is_active_flag_rif_rfth(UART1) == 1) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + md_uart_clear_flag_rfth(UART1); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +/* UART2 device driver structure */ +struct es32_uart uart2 = +{ + UART2, + UART2_IRQn +}; + +struct rt_serial_device serial2; + +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (md_uart_is_active_flag_rif_rfth(UART2) == 1) + { + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + md_uart_clear_flag_rfth(UART2); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +/* UART3 device driver structure */ +struct es32_uart uart3 = +{ + UART3, + UART3_IRQn +}; + +struct rt_serial_device serial3; + +void UART3_AES_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (md_uart_is_active_flag_rif_rfth(UART3) == 1) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + md_uart_clear_flag_rfth(UART3); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct es32_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART1 + uart = &uart1; + serial1.ops = &es32f0x_uart_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + uart = &uart2; + serial2.ops = &es32f0x_uart_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 + uart = &uart3; + serial3.ops = &es32f0x_uart_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_uart.h b/bsp/essemi/es32f0271/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..7d3755d0a6db211c8f28cee324a5dbfb168ec97f --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct b/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..4ee8d1e3fc8b0d721151fcb3200a6732c50f765d --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct @@ -0,0 +1,14 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x10000 { ; load region size_region + ER_IROM1 0x00000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x2000{ ; RW data + .ANY (+RW +ZI) + } +} diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..b374366930b2d1b5689ff5044caba49eace6aa68 Binary files /dev/null and b/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf differ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf b/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf new file mode 100644 index 0000000000000000000000000000000000000000..fb44cda0cafec3f672b94d74a765212a63b39e2b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf @@ -0,0 +1,793 @@ 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}{\listlevel +\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 +\fi-1440\li1440\lin1440 }{\listname ;}\listid1335182434}{\list\listtemplateid-1861725538\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 +\fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel 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}{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2 +\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0 +\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0 +\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 +\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 } +{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid1801338294} +{\list\listtemplateid-1056679890\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1429 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\af1 +\ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 \cell \cell }\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 +\trowd \irow0\irowband0\lastrow \ltrrow\ts11\trgaph108\trrh240\trleft-108\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind0\tblindtype3 \clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl +\cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx4405\clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl \cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx8918\row }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1 +\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 +\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang {\pntxta )}} +{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl8 +\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}\pard\plain \ltrpar\qj \li0\ri0\sa240\widctlpar +\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 END USER LICENCE AGREEMENT FOR THE }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS) DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 +SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 . ARM IS ONLY WILLING TO LICENSE THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93 +CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-CORE +\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores. +\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid11754636 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 +\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-DSP\'94 + means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid11754636\charrsid13240697 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML schema file}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid11754636\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-RTOS API\'94 means the + real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 +Notwithstanding the foregoing, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 the CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 shall not}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 include}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (i) the implementation of other published specification +\hich\af1\dbch\af37\loch\f1 s }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 referenced }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 in th}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 +; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof that }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 complies with the }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 , but are not themselves expressly set forth in the }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 (e.\hich\af1\dbch\af37\loch\f1 +g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; processor microarchitecture) +\hich\af1\dbch\af37\loch\f1 ;\hich\af1\dbch\af37\loch\f1 (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 +\hich\af1\dbch\af37\loch\f1 level representations of integrated circuit designs.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-SVD\'94 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 means }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636 schema}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 files. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93Separate Files\'94 means the components in }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid10227990 the CMSIS reference implementation identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 + in the Schedule that demonstrate the usage of the CMSIS-CORE, CMSIS-DRIVER, CMSIS-DSP, CMSIS-PACK and CMSIS-RTOS API, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid3618484 for microprocessors +or device specific software applications that are for use with microprocessors.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 1. LICENCE GRANTS. +\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES +\par +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar +\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ; and +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 unmodified, with the products}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Clause 1.1 (i) }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 . +\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 +If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant to Clauses 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 +}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM\hich\f1 \rquote \loch\f1 s name\hich\af1\dbch\af37\loch\f1 +, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 to }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 +\hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 +\hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and authorised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 2}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 + CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 :}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 i}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you. +\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 + are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 + or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . SUPPORT. +\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 may do so entirely at ARM's discretion. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 + LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARR +ANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE CMSIS DELIVERABLES MAY CONTAIN ERRORS. }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . LIMITATION OF LIABILITY. +\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +THE TOTAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICEN +CE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW. +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 6 +}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13830602 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 +The Separate Files are delivered subject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and the\hich\af1\dbch\af37\loch\f1 \hich\f1 y are not included in the term \'93}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 +\loch\af1\dbch\af37\hich\f1 \'94\loch\f1 \hich\f1 under this Licence. You agree to comply with all terms and conditions imposed on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms +\'94\loch\f1 ). +\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLA\hich\af1\dbch\af37\loch\f1 \hich\f1 +IMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 +OTHER CODE\'94\loch\f1 ), AND THE USE OF\hich\af1\dbch\af37\loch\f1 \hich\af1\dbch\af37\loch\f1 +ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE. +\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, \hich\af1\dbch\af37\loch\f1 +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EX +\hich\af1\dbch\af37\loch\f1 E\hich\af1\dbch\af37\loch\f1 RCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . U.S. GOVERNMENT END USERS. +\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . TERM AND TERMINATION. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 . You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 +8.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence fro\hich\af1\dbch\af37\loch\f1 +m ARM for the CMSIS Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) patent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 +\hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 +\hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 (i) "affiliate" means any entity controlling, contr\hich\af1\dbch\af37\loch\f1 +olled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, o +\hich\af1\dbch\af37\loch\f1 r\hich\af1\dbch\af37\loch\f1 proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1 + means with respect to any claims of any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when imp\hich\af1\dbch\af37\loch\f1 lementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 +because no alternative, commercially reasonable, non-infringing way of implementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid5900444 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 Upon termination of this Licence,}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 +using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 + and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . GENERAL. +\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 + and it may only be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence may not be modified by purchase orders, ad +vertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this Licence shall not be affected thereby. The failure by ARM to enforce any o +f the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 This Licence may not be assigned without the prior written consent of ARM. +\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \page SCHEDULE +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Separate Files +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 The }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 contained in the following directories}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar +\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 +\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 +DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 +\hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - Header files; +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 +\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 +DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 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+000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000105000000000000}} \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h new file mode 100644 index 0000000000000000000000000000000000000000..f70a10e35c1b006af73d87098ae17e362f310b6c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h @@ -0,0 +1,683 @@ +/** + ************************************************************************************** + * @file reg_AD16C4T.h + * @brief AD16C4T Head File + * + * @version V0.01 + * @date 3/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_AD16C4T_H__ +#define __REG_AD16C4T_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for AD16C4T_CON1 register ************************/ + +#define AD16C4T_CON1_DBGSEL_POS 15U +#define AD16C4T_CON1_DBGSEL_MSK BIT(AD16C4T_CON1_DBGSEL_POS) + +#define AD16C4T_CON1_CMPSEL_POSS 11U +#define AD16C4T_CON1_CMPSEL_POSE 13U +#define AD16C4T_CON1_CMPSEL_MSK BITS(AD16C4T_CON1_CMPSEL_POSS,AD16C4T_CON1_CMPSEL_POSE) + +#define AD16C4T_CON1_CMPSELP_POS 10U +#define AD16C4T_CON1_CMPSELP_MSK BIT(AD16C4T_CON1_CMPSELP_POS) + +#define AD16C4T_CON1_DFCKSEL_POSS 8U +#define AD16C4T_CON1_DFCKSEL_POSE 9U +#define AD16C4T_CON1_DFCKSEL_MSK BITS(AD16C4T_CON1_DFCKSEL_POSS,AD16C4T_CON1_DFCKSEL_POSE) + +#define AD16C4T_CON1_ARPEN_POS 7U +#define AD16C4T_CON1_ARPEN_MSK BIT(AD16C4T_CON1_ARPEN_POS) + +#define AD16C4T_CON1_CMSEL_POSS 5U +#define AD16C4T_CON1_CMSEL_POSE 6U +#define AD16C4T_CON1_CMSEL_MSK BITS(AD16C4T_CON1_CMSEL_POSS,AD16C4T_CON1_CMSEL_POSE) + +#define AD16C4T_CON1_DIRSEL_POS 4U +#define AD16C4T_CON1_DIRSEL_MSK BIT(AD16C4T_CON1_DIRSEL_POS) + +#define AD16C4T_CON1_SPMEN_POS 3U +#define AD16C4T_CON1_SPMEN_MSK BIT(AD16C4T_CON1_SPMEN_POS) + +#define AD16C4T_CON1_UERSEL_POS 2U +#define AD16C4T_CON1_UERSEL_MSK BIT(AD16C4T_CON1_UERSEL_POS) + +#define AD16C4T_CON1_DISUE_POS 1U +#define AD16C4T_CON1_DISUE_MSK BIT(AD16C4T_CON1_DISUE_POS) + +#define AD16C4T_CON1_CNTEN_POS 0U +#define AD16C4T_CON1_CNTEN_MSK BIT(AD16C4T_CON1_CNTEN_POS) + +/****************** Bit definition for AD16C4T_CON2 register ************************/ + +#define AD16C4T_CON2_OISS4_POS 14U +#define AD16C4T_CON2_OISS4_MSK BIT(AD16C4T_CON2_OISS4_POS) + +#define AD16C4T_CON2_OISS3N_POS 13U +#define AD16C4T_CON2_OISS3N_MSK BIT(AD16C4T_CON2_OISS3N_POS) + +#define AD16C4T_CON2_OISS3_POS 12U +#define AD16C4T_CON2_OISS3_MSK BIT(AD16C4T_CON2_OISS3_POS) + +#define AD16C4T_CON2_OISS2N_POS 11U +#define AD16C4T_CON2_OISS2N_MSK BIT(AD16C4T_CON2_OISS2N_POS) + +#define AD16C4T_CON2_OISS2_POS 10U +#define AD16C4T_CON2_OISS2_MSK BIT(AD16C4T_CON2_OISS2_POS) + +#define AD16C4T_CON2_OISS1N_POS 9U +#define AD16C4T_CON2_OISS1N_MSK BIT(AD16C4T_CON2_OISS1N_POS) + +#define AD16C4T_CON2_OISS1_POS 8U +#define AD16C4T_CON2_OISS1_MSK BIT(AD16C4T_CON2_OISS1_POS) + +#define AD16C4T_CON2_I1SEL_POS 7U +#define AD16C4T_CON2_I1SEL_MSK BIT(AD16C4T_CON2_I1SEL_POS) + +#define AD16C4T_CON2_MMSEL_POSS 4U +#define AD16C4T_CON2_MMSEL_POSE 6U +#define AD16C4T_CON2_MMSEL_MSK BITS(AD16C4T_CON2_MMSEL_POSS,AD16C4T_CON2_MMSEL_POSE) + +#define AD16C4T_CON2_CCDMASEL_POS 3U +#define AD16C4T_CON2_CCDMASEL_MSK BIT(AD16C4T_CON2_CCDMASEL_POS) + +#define AD16C4T_CON2_CCUSEL_POS 2U +#define AD16C4T_CON2_CCUSEL_MSK BIT(AD16C4T_CON2_CCUSEL_POS) + +#define AD16C4T_CON2_CCPCEN_POS 0U +#define AD16C4T_CON2_CCPCEN_MSK BIT(AD16C4T_CON2_CCPCEN_POS) + +/****************** Bit definition for AD16C4T_SMCON register ************************/ + +#define AD16C4T_SMCON_ETPOL_POS 15U +#define AD16C4T_SMCON_ETPOL_MSK BIT(AD16C4T_SMCON_ETPOL_POS) + +#define AD16C4T_SMCON_ECM2EN_POS 14U +#define AD16C4T_SMCON_ECM2EN_MSK BIT(AD16C4T_SMCON_ECM2EN_POS) + +#define AD16C4T_SMCON_ETFLT_POSS 8U +#define AD16C4T_SMCON_ETFLT_POSE 11U +#define AD16C4T_SMCON_ETFLT_MSK BITS(AD16C4T_SMCON_ETFLT_POSS,AD16C4T_SMCON_ETFLT_POSE) + +#define AD16C4T_SMCON_MSCFG_POS 7U +#define AD16C4T_SMCON_MSCFG_MSK BIT(AD16C4T_SMCON_MSCFG_POS) + +#define AD16C4T_SMCON_TSSEL_POSS 4U +#define AD16C4T_SMCON_TSSEL_POSE 6U +#define AD16C4T_SMCON_TSSEL_MSK BITS(AD16C4T_SMCON_TSSEL_POSS,AD16C4T_SMCON_TSSEL_POSE) + +#define AD16C4T_SMCON_CHCSEL_POS 3U +#define AD16C4T_SMCON_CHCSEL_MSK BIT(AD16C4T_SMCON_CHCSEL_POS) + +#define AD16C4T_SMCON_SMODS_POSS 0U +#define AD16C4T_SMCON_SMODS_POSE 2U +#define AD16C4T_SMCON_SMODS_MSK BITS(AD16C4T_SMCON_SMODS_POSS,AD16C4T_SMCON_SMODS_POSE) + +/****************** Bit definition for AD16C4T_IER register ************************/ + +#define AD16C4T_IER_CH4OVI_POS 12U +#define AD16C4T_IER_CH4OVI_MSK BIT(AD16C4T_IER_CH4OVI_POS) + +#define AD16C4T_IER_CH3OVI_POS 11U +#define AD16C4T_IER_CH3OVI_MSK BIT(AD16C4T_IER_CH3OVI_POS) + +#define AD16C4T_IER_CH2OVI_POS 10U +#define AD16C4T_IER_CH2OVI_MSK BIT(AD16C4T_IER_CH2OVI_POS) + +#define AD16C4T_IER_CH1OVI_POS 9U +#define AD16C4T_IER_CH1OVI_MSK BIT(AD16C4T_IER_CH1OVI_POS) + +#define AD16C4T_IER_BRKI_POS 7U +#define AD16C4T_IER_BRKI_MSK BIT(AD16C4T_IER_BRKI_POS) + +#define AD16C4T_IER_TRGI_POS 6U +#define AD16C4T_IER_TRGI_MSK BIT(AD16C4T_IER_TRGI_POS) + +#define AD16C4T_IER_COMI_POS 5U +#define AD16C4T_IER_COMI_MSK BIT(AD16C4T_IER_COMI_POS) + +#define AD16C4T_IER_CH4I_POS 4U +#define AD16C4T_IER_CH4I_MSK BIT(AD16C4T_IER_CH4I_POS) + +#define AD16C4T_IER_CH3I_POS 3U +#define AD16C4T_IER_CH3I_MSK BIT(AD16C4T_IER_CH3I_POS) + +#define AD16C4T_IER_CH2I_POS 2U +#define AD16C4T_IER_CH2I_MSK BIT(AD16C4T_IER_CH2I_POS) + +#define AD16C4T_IER_CH1I_POS 1U +#define AD16C4T_IER_CH1I_MSK BIT(AD16C4T_IER_CH1I_POS) + +#define AD16C4T_IER_UI_POS 0U +#define AD16C4T_IER_UI_MSK BIT(AD16C4T_IER_UI_POS) + +/****************** Bit definition for AD16C4T_IDR register ************************/ + +#define AD16C4T_IDR_CH4OVI_POS 12U +#define AD16C4T_IDR_CH4OVI_MSK BIT(AD16C4T_IDR_CH4OVI_POS) + +#define AD16C4T_IDR_CH3OVI_POS 11U +#define AD16C4T_IDR_CH3OVI_MSK BIT(AD16C4T_IDR_CH3OVI_POS) + +#define AD16C4T_IDR_CH2OVI_POS 10U +#define AD16C4T_IDR_CH2OVI_MSK BIT(AD16C4T_IDR_CH2OVI_POS) + +#define AD16C4T_IDR_CH1OVI_POS 9U +#define AD16C4T_IDR_CH1OVI_MSK BIT(AD16C4T_IDR_CH1OVI_POS) + +#define AD16C4T_IDR_BRKI_POS 7U +#define AD16C4T_IDR_BRKI_MSK BIT(AD16C4T_IDR_BRKI_POS) + +#define AD16C4T_IDR_TRGI_POS 6U +#define AD16C4T_IDR_TRGI_MSK BIT(AD16C4T_IDR_TRGI_POS) + +#define AD16C4T_IDR_COMI_POS 5U +#define AD16C4T_IDR_COMI_MSK BIT(AD16C4T_IDR_COMI_POS) + +#define AD16C4T_IDR_CH4I_POS 4U +#define AD16C4T_IDR_CH4I_MSK BIT(AD16C4T_IDR_CH4I_POS) + +#define AD16C4T_IDR_CH3I_POS 3U +#define AD16C4T_IDR_CH3I_MSK BIT(AD16C4T_IDR_CH3I_POS) + +#define AD16C4T_IDR_CH2I_POS 2U +#define AD16C4T_IDR_CH2I_MSK BIT(AD16C4T_IDR_CH2I_POS) + +#define AD16C4T_IDR_CH1I_POS 1U +#define AD16C4T_IDR_CH1I_MSK BIT(AD16C4T_IDR_CH1I_POS) + +#define AD16C4T_IDR_UI_POS 0U +#define AD16C4T_IDR_UI_MSK BIT(AD16C4T_IDR_UI_POS) + +/****************** Bit definition for AD16C4T_IVS register ************************/ + +#define AD16C4T_IVS_CH4OVI_POS 12U +#define AD16C4T_IVS_CH4OVI_MSK BIT(AD16C4T_IVS_CH4OVI_POS) + +#define AD16C4T_IVS_CH3OVI_POS 11U +#define AD16C4T_IVS_CH3OVI_MSK BIT(AD16C4T_IVS_CH3OVI_POS) + +#define AD16C4T_IVS_CH2OVI_POS 10U +#define AD16C4T_IVS_CH2OVI_MSK BIT(AD16C4T_IVS_CH2OVI_POS) + +#define AD16C4T_IVS_CH1OVI_POS 9U +#define AD16C4T_IVS_CH1OVI_MSK BIT(AD16C4T_IVS_CH1OVI_POS) + +#define AD16C4T_IVS_BRKI_POS 7U +#define AD16C4T_IVS_BRKI_MSK BIT(AD16C4T_IVS_BRKI_POS) + +#define AD16C4T_IVS_TRGI_POS 6U +#define AD16C4T_IVS_TRGI_MSK BIT(AD16C4T_IVS_TRGI_POS) + +#define AD16C4T_IVS_COMI_POS 5U +#define AD16C4T_IVS_COMI_MSK BIT(AD16C4T_IVS_COMI_POS) + +#define AD16C4T_IVS_CH4I_POS 4U +#define AD16C4T_IVS_CH4I_MSK BIT(AD16C4T_IVS_CH4I_POS) + +#define AD16C4T_IVS_CH3I_POS 3U +#define AD16C4T_IVS_CH3I_MSK BIT(AD16C4T_IVS_CH3I_POS) + +#define AD16C4T_IVS_CH2I_POS 2U +#define AD16C4T_IVS_CH2I_MSK BIT(AD16C4T_IVS_CH2I_POS) + +#define AD16C4T_IVS_CH1I_POS 1U +#define AD16C4T_IVS_CH1I_MSK BIT(AD16C4T_IVS_CH1I_POS) + +#define AD16C4T_IVS_UI_POS 0U +#define AD16C4T_IVS_UI_MSK BIT(AD16C4T_IVS_UI_POS) + +/****************** Bit definition for AD16C4T_RIF register ************************/ + +#define AD16C4T_RIF_CH4OVI_POS 12U +#define AD16C4T_RIF_CH4OVI_MSK BIT(AD16C4T_RIF_CH4OVI_POS) + +#define AD16C4T_RIF_CH3OVI_POS 11U +#define AD16C4T_RIF_CH3OVI_MSK BIT(AD16C4T_RIF_CH3OVI_POS) + +#define AD16C4T_RIF_CH2OVI_POS 10U +#define AD16C4T_RIF_CH2OVI_MSK BIT(AD16C4T_RIF_CH2OVI_POS) + +#define AD16C4T_RIF_CH1OVI_POS 9U +#define AD16C4T_RIF_CH1OVI_MSK BIT(AD16C4T_RIF_CH1OVI_POS) + +#define AD16C4T_RIF_BRKI_POS 7U +#define AD16C4T_RIF_BRKI_MSK BIT(AD16C4T_RIF_BRKI_POS) + +#define AD16C4T_RIF_TRGI_POS 6U +#define AD16C4T_RIF_TRGI_MSK BIT(AD16C4T_RIF_TRGI_POS) + +#define AD16C4T_RIF_COMI_POS 5U +#define AD16C4T_RIF_COMI_MSK BIT(AD16C4T_RIF_COMI_POS) + +#define AD16C4T_RIF_CH4I_POS 4U +#define AD16C4T_RIF_CH4I_MSK BIT(AD16C4T_RIF_CH4I_POS) + +#define AD16C4T_RIF_CH3I_POS 3U +#define AD16C4T_RIF_CH3I_MSK BIT(AD16C4T_RIF_CH3I_POS) + +#define AD16C4T_RIF_CH2I_POS 2U +#define AD16C4T_RIF_CH2I_MSK BIT(AD16C4T_RIF_CH2I_POS) + +#define AD16C4T_RIF_CH1I_POS 1U +#define AD16C4T_RIF_CH1I_MSK BIT(AD16C4T_RIF_CH1I_POS) + +#define AD16C4T_RIF_UI_POS 0U +#define AD16C4T_RIF_UI_MSK BIT(AD16C4T_RIF_UI_POS) + +/****************** Bit definition for AD16C4T_IFM register ************************/ + +#define AD16C4T_IFM_CH4OVI_POS 12U +#define AD16C4T_IFM_CH4OVI_MSK BIT(AD16C4T_IFM_CH4OVI_POS) + +#define AD16C4T_IFM_CH3OVI_POS 11U +#define AD16C4T_IFM_CH3OVI_MSK BIT(AD16C4T_IFM_CH3OVI_POS) + +#define AD16C4T_IFM_CH2OVI_POS 10U +#define AD16C4T_IFM_CH2OVI_MSK BIT(AD16C4T_IFM_CH2OVI_POS) + +#define AD16C4T_IFM_CH1OVI_POS 9U +#define AD16C4T_IFM_CH1OVI_MSK BIT(AD16C4T_IFM_CH1OVI_POS) + +#define AD16C4T_IFM_BRKI_POS 7U +#define AD16C4T_IFM_BRKI_MSK BIT(AD16C4T_IFM_BRKI_POS) + +#define AD16C4T_IFM_TRGI_POS 6U +#define AD16C4T_IFM_TRGI_MSK BIT(AD16C4T_IFM_TRGI_POS) + +#define AD16C4T_IFM_COMI_POS 5U +#define AD16C4T_IFM_COMI_MSK BIT(AD16C4T_IFM_COMI_POS) + +#define AD16C4T_IFM_CH4I_POS 4U +#define AD16C4T_IFM_CH4I_MSK BIT(AD16C4T_IFM_CH4I_POS) + +#define AD16C4T_IFM_CH3I_POS 3U +#define AD16C4T_IFM_CH3I_MSK BIT(AD16C4T_IFM_CH3I_POS) + +#define AD16C4T_IFM_CH2I_POS 2U +#define AD16C4T_IFM_CH2I_MSK BIT(AD16C4T_IFM_CH2I_POS) + +#define AD16C4T_IFM_CH1I_POS 1U +#define AD16C4T_IFM_CH1I_MSK BIT(AD16C4T_IFM_CH1I_POS) + +#define AD16C4T_IFM_UI_POS 0U +#define AD16C4T_IFM_UI_MSK BIT(AD16C4T_IFM_UI_POS) + +/****************** Bit definition for AD16C4T_ICR register ************************/ + +#define AD16C4T_ICR_CH4OVI_POS 12U +#define AD16C4T_ICR_CH4OVI_MSK BIT(AD16C4T_ICR_CH4OVI_POS) + +#define AD16C4T_ICR_CH3OVI_POS 11U +#define AD16C4T_ICR_CH3OVI_MSK BIT(AD16C4T_ICR_CH3OVI_POS) + +#define AD16C4T_ICR_CH2OVI_POS 10U +#define AD16C4T_ICR_CH2OVI_MSK BIT(AD16C4T_ICR_CH2OVI_POS) + +#define AD16C4T_ICR_CH1OVI_POS 9U +#define AD16C4T_ICR_CH1OVI_MSK BIT(AD16C4T_ICR_CH1OVI_POS) + +#define AD16C4T_ICR_BRKI_POS 7U +#define AD16C4T_ICR_BRKI_MSK BIT(AD16C4T_ICR_BRKI_POS) + +#define AD16C4T_ICR_TRGI_POS 6U +#define AD16C4T_ICR_TRGI_MSK BIT(AD16C4T_ICR_TRGI_POS) + +#define AD16C4T_ICR_COMI_POS 5U +#define AD16C4T_ICR_COMI_MSK BIT(AD16C4T_ICR_COMI_POS) + +#define AD16C4T_ICR_CH4I_POS 4U +#define AD16C4T_ICR_CH4I_MSK BIT(AD16C4T_ICR_CH4I_POS) + +#define AD16C4T_ICR_CH3I_POS 3U +#define AD16C4T_ICR_CH3I_MSK BIT(AD16C4T_ICR_CH3I_POS) + +#define AD16C4T_ICR_CH2I_POS 2U +#define AD16C4T_ICR_CH2I_MSK BIT(AD16C4T_ICR_CH2I_POS) + +#define AD16C4T_ICR_CH1I_POS 1U +#define AD16C4T_ICR_CH1I_MSK BIT(AD16C4T_ICR_CH1I_POS) + +#define AD16C4T_ICR_UI_POS 0U +#define AD16C4T_ICR_UI_MSK BIT(AD16C4T_ICR_UI_POS) + +/****************** Bit definition for AD16C4T_SGE register ************************/ + +#define AD16C4T_SGE_SGBRK_POS 7U +#define AD16C4T_SGE_SGBRK_MSK BIT(AD16C4T_SGE_SGBRK_POS) + +#define AD16C4T_SGE_SGTRG_POS 6U +#define AD16C4T_SGE_SGTRG_MSK BIT(AD16C4T_SGE_SGTRG_POS) + +#define AD16C4T_SGE_SGCOM_POS 5U +#define AD16C4T_SGE_SGCOM_MSK BIT(AD16C4T_SGE_SGCOM_POS) + +#define AD16C4T_SGE_SGCH4_POS 4U +#define AD16C4T_SGE_SGCH4_MSK BIT(AD16C4T_SGE_SGCH4_POS) + +#define AD16C4T_SGE_SGCH3_POS 3U +#define AD16C4T_SGE_SGCH3_MSK BIT(AD16C4T_SGE_SGCH3_POS) + +#define AD16C4T_SGE_SGCH2_POS 2U +#define AD16C4T_SGE_SGCH2_MSK BIT(AD16C4T_SGE_SGCH2_POS) + +#define AD16C4T_SGE_SGCH1_POS 1U +#define AD16C4T_SGE_SGCH1_MSK BIT(AD16C4T_SGE_SGCH1_POS) + +#define AD16C4T_SGE_SGU_POS 0U +#define AD16C4T_SGE_SGU_MSK BIT(AD16C4T_SGE_SGU_POS) + +/****************** Bit definition for AD16C4T_CHMR1_OUTPUT register ************************/ + +#define AD16C4T_CHMR1_OUTPUT_CH2OCLREN_POS 15U +#define AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2OCLREN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS 12U +#define AD16C4T_CHMR1_OUTPUT_CH2MOD_POSE 14U +#define AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK BITS(AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS,AD16C4T_CHMR1_OUTPUT_CH2MOD_POSE) + +#define AD16C4T_CHMR1_OUTPUT_CH2PEN_POS 11U +#define AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2PEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH2FEN_POS 10U +#define AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2FEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS 8U +#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSE 9U +#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK BITS(AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS,AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSE) + +#define AD16C4T_CHMR1_OUTPUT_CH1OCLREN_POS 7U +#define AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1OCLREN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS 4U +#define AD16C4T_CHMR1_OUTPUT_CH1MOD_POSE 6U +#define AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK BITS(AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS,AD16C4T_CHMR1_OUTPUT_CH1MOD_POSE) + +#define AD16C4T_CHMR1_OUTPUT_CH1PEN_POS 3U +#define AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1PEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH1FEN_POS 2U +#define AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1FEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS 0U +#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSE 1U +#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK BITS(AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS,AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSE) + +/****************** Bit definition for AD16C4T_CHMR1_INPUT register ************************/ + +#define AD16C4T_CHMR1_INPUT_I2FLT_POSS 12U +#define AD16C4T_CHMR1_INPUT_I2FLT_POSE 15U +#define AD16C4T_CHMR1_INPUT_I2FLT_MSK BITS(AD16C4T_CHMR1_INPUT_I2FLT_POSS,AD16C4T_CHMR1_INPUT_I2FLT_POSE) + +#define AD16C4T_CHMR1_INPUT_I2PRES_POSS 10U +#define AD16C4T_CHMR1_INPUT_I2PRES_POSE 11U +#define AD16C4T_CHMR1_INPUT_I2PRES_MSK BITS(AD16C4T_CHMR1_INPUT_I2PRES_POSS,AD16C4T_CHMR1_INPUT_I2PRES_POSE) + +#define AD16C4T_CHMR1_INPUT_CC2SSEL_POSS 8U +#define AD16C4T_CHMR1_INPUT_CC2SSEL_POSE 9U +#define AD16C4T_CHMR1_INPUT_CC2SSEL_MSK BITS(AD16C4T_CHMR1_INPUT_CC2SSEL_POSS,AD16C4T_CHMR1_INPUT_CC2SSEL_POSE) + +#define AD16C4T_CHMR1_INPUT_I1FLT_POSS 4U +#define AD16C4T_CHMR1_INPUT_I1FLT_POSE 7U +#define AD16C4T_CHMR1_INPUT_I1FLT_MSK BITS(AD16C4T_CHMR1_INPUT_I1FLT_POSS,AD16C4T_CHMR1_INPUT_I1FLT_POSE) + +#define AD16C4T_CHMR1_INPUT_I1PRES_POSS 2U +#define AD16C4T_CHMR1_INPUT_I1PRES_POSE 3U +#define AD16C4T_CHMR1_INPUT_I1PRES_MSK BITS(AD16C4T_CHMR1_INPUT_I1PRES_POSS,AD16C4T_CHMR1_INPUT_I1PRES_POSE) + +#define AD16C4T_CHMR1_INPUT_CC1SSEL_POSS 0U +#define AD16C4T_CHMR1_INPUT_CC1SSEL_POSE 1U +#define AD16C4T_CHMR1_INPUT_CC1SSEL_MSK BITS(AD16C4T_CHMR1_INPUT_CC1SSEL_POSS,AD16C4T_CHMR1_INPUT_CC1SSEL_POSE) + +/****************** Bit definition for AD16C4T_CHMR2_OUTPUT register ************************/ + +#define AD16C4T_CHMR2_OUTPUT_CH4OCLREN_POS 15U +#define AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4OCLREN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS 12U +#define AD16C4T_CHMR2_OUTPUT_CH4MOD_POSE 14U +#define AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK BITS(AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS,AD16C4T_CHMR2_OUTPUT_CH4MOD_POSE) + +#define AD16C4T_CHMR2_OUTPUT_CH4PEN_POS 11U +#define AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4PEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH4FEN_POS 10U +#define AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4FEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS 8U +#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSE 9U +#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK BITS(AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS,AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSE) + +#define AD16C4T_CHMR2_OUTPUT_CH3OCLREN_POS 7U +#define AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3OCLREN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS 4U +#define AD16C4T_CHMR2_OUTPUT_CH3MOD_POSE 6U +#define AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK BITS(AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS,AD16C4T_CHMR2_OUTPUT_CH3MOD_POSE) + +#define AD16C4T_CHMR2_OUTPUT_CH3PEN_POS 3U +#define AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3PEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH3FEN_POS 2U +#define AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3FEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS 0U +#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSE 1U +#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK BITS(AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS,AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSE) + +/****************** Bit definition for AD16C4T_CHMR2_INPUT register ************************/ + +#define AD16C4T_CHMR2_INPUT_I4FLT_POSS 12U +#define AD16C4T_CHMR2_INPUT_I4FLT_POSE 15U +#define AD16C4T_CHMR2_INPUT_I4FLT_MSK BITS(AD16C4T_CHMR2_INPUT_I4FLT_POSS,AD16C4T_CHMR2_INPUT_I4FLT_POSE) + +#define AD16C4T_CHMR2_INPUT_I4PRES_POSS 10U +#define AD16C4T_CHMR2_INPUT_I4PRES_POSE 11U +#define AD16C4T_CHMR2_INPUT_I4PRES_MSK BITS(AD16C4T_CHMR2_INPUT_I4PRES_POSS,AD16C4T_CHMR2_INPUT_I4PRES_POSE) + +#define AD16C4T_CHMR2_INPUT_CC4SSEL_POSS 8U +#define AD16C4T_CHMR2_INPUT_CC4SSEL_POSE 9U +#define AD16C4T_CHMR2_INPUT_CC4SSEL_MSK BITS(AD16C4T_CHMR2_INPUT_CC4SSEL_POSS,AD16C4T_CHMR2_INPUT_CC4SSEL_POSE) + +#define AD16C4T_CHMR2_INPUT_I3FLT_POSS 4U +#define AD16C4T_CHMR2_INPUT_I3FLT_POSE 7U +#define AD16C4T_CHMR2_INPUT_I3FLT_MSK BITS(AD16C4T_CHMR2_INPUT_I3FLT_POSS,AD16C4T_CHMR2_INPUT_I3FLT_POSE) + +#define AD16C4T_CHMR2_INPUT_I3PRES_POSS 2U +#define AD16C4T_CHMR2_INPUT_I3PRES_POSE 3U +#define AD16C4T_CHMR2_INPUT_I3PRES_MSK BITS(AD16C4T_CHMR2_INPUT_I3PRES_POSS,AD16C4T_CHMR2_INPUT_I3PRES_POSE) + +#define AD16C4T_CHMR2_INPUT_CC3SSEL_POSS 0U +#define AD16C4T_CHMR2_INPUT_CC3SSEL_POSE 1U +#define AD16C4T_CHMR2_INPUT_CC3SSEL_MSK BITS(AD16C4T_CHMR2_INPUT_CC3SSEL_POSS,AD16C4T_CHMR2_INPUT_CC3SSEL_POSE) + +/****************** Bit definition for AD16C4T_CCEP register ************************/ + +#define AD16C4T_CCEP_CC4NPOL_POS 15U +#define AD16C4T_CCEP_CC4NPOL_MSK BIT(AD16C4T_CCEP_CC4NPOL_POS) + +#define AD16C4T_CCEP_CC4POL_POS 13U +#define AD16C4T_CCEP_CC4POL_MSK BIT(AD16C4T_CCEP_CC4POL_POS) + +#define AD16C4T_CCEP_CC4EN_POS 12U +#define AD16C4T_CCEP_CC4EN_MSK BIT(AD16C4T_CCEP_CC4EN_POS) + +#define AD16C4T_CCEP_CC3NPOL_POS 11U +#define AD16C4T_CCEP_CC3NPOL_MSK BIT(AD16C4T_CCEP_CC3NPOL_POS) + +#define AD16C4T_CCEP_CC3NEN_POS 10U +#define AD16C4T_CCEP_CC3NEN_MSK BIT(AD16C4T_CCEP_CC3NEN_POS) + +#define AD16C4T_CCEP_CC3POL_POS 9U +#define AD16C4T_CCEP_CC3POL_MSK BIT(AD16C4T_CCEP_CC3POL_POS) + +#define AD16C4T_CCEP_CC3EN_POS 8U +#define AD16C4T_CCEP_CC3EN_MSK BIT(AD16C4T_CCEP_CC3EN_POS) + +#define AD16C4T_CCEP_CC2NPOL_POS 7U +#define AD16C4T_CCEP_CC2NPOL_MSK BIT(AD16C4T_CCEP_CC2NPOL_POS) + +#define AD16C4T_CCEP_CC2NEN_POS 6U +#define AD16C4T_CCEP_CC2NEN_MSK BIT(AD16C4T_CCEP_CC2NEN_POS) + +#define AD16C4T_CCEP_CC2POL_POS 5U +#define AD16C4T_CCEP_CC2POL_MSK BIT(AD16C4T_CCEP_CC2POL_POS) + +#define AD16C4T_CCEP_CC2EN_POS 4U +#define AD16C4T_CCEP_CC2EN_MSK BIT(AD16C4T_CCEP_CC2EN_POS) + +#define AD16C4T_CCEP_CC1NPOL_POS 3U +#define AD16C4T_CCEP_CC1NPOL_MSK BIT(AD16C4T_CCEP_CC1NPOL_POS) + +#define AD16C4T_CCEP_CC1NEN_POS 2U +#define AD16C4T_CCEP_CC1NEN_MSK BIT(AD16C4T_CCEP_CC1NEN_POS) + +#define AD16C4T_CCEP_CC1POL_POS 1U +#define AD16C4T_CCEP_CC1POL_MSK BIT(AD16C4T_CCEP_CC1POL_POS) + +#define AD16C4T_CCEP_CC1EN_POS 0U +#define AD16C4T_CCEP_CC1EN_MSK BIT(AD16C4T_CCEP_CC1EN_POS) + +/****************** Bit definition for AD16C4T_COUNT register ************************/ + +#define AD16C4T_COUNT_CNTV_POSS 0U +#define AD16C4T_COUNT_CNTV_POSE 15U +#define AD16C4T_COUNT_CNTV_MSK BITS(AD16C4T_COUNT_CNTV_POSS,AD16C4T_COUNT_CNTV_POSE) + +/****************** Bit definition for AD16C4T_PRES register ************************/ + +#define AD16C4T_PRES_PSCV_POSS 0U +#define AD16C4T_PRES_PSCV_POSE 15U +#define AD16C4T_PRES_PSCV_MSK BITS(AD16C4T_PRES_PSCV_POSS,AD16C4T_PRES_PSCV_POSE) + +/****************** Bit definition for AD16C4T_AR register ************************/ + +#define AD16C4T_AR_ARV_POSS 0U +#define AD16C4T_AR_ARV_POSE 15U +#define AD16C4T_AR_ARV_MSK BITS(AD16C4T_AR_ARV_POSS,AD16C4T_AR_ARV_POSE) + +/****************** Bit definition for AD16C4T_REPAR register ************************/ + +#define AD16C4T_REPAR_REPV_POSS 0U +#define AD16C4T_REPAR_REPV_POSE 7U +#define AD16C4T_REPAR_REPV_MSK BITS(AD16C4T_REPAR_REPV_POSS,AD16C4T_REPAR_REPV_POSE) + +/****************** Bit definition for AD16C4T_CCVAL1 register ************************/ + +#define AD16C4T_CCVAL1_CCRV1_POSS 0U +#define AD16C4T_CCVAL1_CCRV1_POSE 15U +#define AD16C4T_CCVAL1_CCRV1_MSK BITS(AD16C4T_CCVAL1_CCRV1_POSS,AD16C4T_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for AD16C4T_CCVAL2 register ************************/ + +#define AD16C4T_CCVAL2_CCRV2_POSS 0U +#define AD16C4T_CCVAL2_CCRV2_POSE 15U +#define AD16C4T_CCVAL2_CCRV2_MSK BITS(AD16C4T_CCVAL2_CCRV2_POSS,AD16C4T_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for AD16C4T_CCVAL3 register ************************/ + +#define AD16C4T_CCVAL3_CCRV3_POSS 0U +#define AD16C4T_CCVAL3_CCRV3_POSE 15U +#define AD16C4T_CCVAL3_CCRV3_MSK BITS(AD16C4T_CCVAL3_CCRV3_POSS,AD16C4T_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for AD16C4T_CCVAL4 register ************************/ + +#define AD16C4T_CCVAL4_CCRV4_POSS 0U +#define AD16C4T_CCVAL4_CCRV4_POSE 15U +#define AD16C4T_CCVAL4_CCRV4_MSK BITS(AD16C4T_CCVAL4_CCRV4_POSS,AD16C4T_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for AD16C4T_BDCFG register ************************/ + +#define AD16C4T_BDCFG_GOEN_POS 15U +#define AD16C4T_BDCFG_GOEN_MSK BIT(AD16C4T_BDCFG_GOEN_POS) + +#define AD16C4T_BDCFG_AOEN_POS 14U +#define AD16C4T_BDCFG_AOEN_MSK BIT(AD16C4T_BDCFG_AOEN_POS) + +#define AD16C4T_BDCFG_BRKP_POS 13U +#define AD16C4T_BDCFG_BRKP_MSK BIT(AD16C4T_BDCFG_BRKP_POS) + +#define AD16C4T_BDCFG_BRKEN_POS 12U +#define AD16C4T_BDCFG_BRKEN_MSK BIT(AD16C4T_BDCFG_BRKEN_POS) + +#define AD16C4T_BDCFG_OFFSSR_POS 11U +#define AD16C4T_BDCFG_OFFSSR_MSK BIT(AD16C4T_BDCFG_OFFSSR_POS) + +#define AD16C4T_BDCFG_OFFSSI_POS 10U +#define AD16C4T_BDCFG_OFFSSI_MSK BIT(AD16C4T_BDCFG_OFFSSI_POS) + +#define AD16C4T_BDCFG_LOCKLVL_POSS 8U +#define AD16C4T_BDCFG_LOCKLVL_POSE 9U +#define AD16C4T_BDCFG_LOCKLVL_MSK BITS(AD16C4T_BDCFG_LOCKLVL_POSS,AD16C4T_BDCFG_LOCKLVL_POSE) + +#define AD16C4T_BDCFG_DT_POSS 0U +#define AD16C4T_BDCFG_DT_POSE 7U +#define AD16C4T_BDCFG_DT_MSK BITS(AD16C4T_BDCFG_DT_POSS,AD16C4T_BDCFG_DT_POSE) + +/****************** Bit definition for AD16C4T_DMAEN register ************************/ + +#define AD16C4T_DMAEN_TRGIDE_POS 6U +#define AD16C4T_DMAEN_TRGIDE_MSK BIT(AD16C4T_DMAEN_TRGIDE_POS) + +#define AD16C4T_DMAEN_COMDE_POS 5U +#define AD16C4T_DMAEN_COMDE_MSK BIT(AD16C4T_DMAEN_COMDE_POS) + +#define AD16C4T_DMAEN_CH4DE_POS 4U +#define AD16C4T_DMAEN_CH4DE_MSK BIT(AD16C4T_DMAEN_CH4DE_POS) + +#define AD16C4T_DMAEN_CH3DE_POS 3U +#define AD16C4T_DMAEN_CH3DE_MSK BIT(AD16C4T_DMAEN_CH3DE_POS) + +#define AD16C4T_DMAEN_CH2DE_POS 2U +#define AD16C4T_DMAEN_CH2DE_MSK BIT(AD16C4T_DMAEN_CH2DE_POS) + +#define AD16C4T_DMAEN_CH1DE_POS 1U +#define AD16C4T_DMAEN_CH1DE_MSK BIT(AD16C4T_DMAEN_CH1DE_POS) + +#define AD16C4T_DMAEN_UDE_POS 0U +#define AD16C4T_DMAEN_UDE_MSK BIT(AD16C4T_DMAEN_UDE_POS) + +typedef struct +{ + __IO uint32_t CON1; /* 0x000 AD16C4T_CON1 Control register 1 */ + __IO uint32_t CON2; /* 0x004 AD16C4T_CON2 Control register 2 */ + __IO uint32_t SMCON; /* 0x008 AD16C4T_SMCON Slave mode control register */ + __O uint32_t IER; /* 0x00C AD16C4T_IER Interrupt Enable register */ + __O uint32_t IDR; /* 0x010 AD16C4T_IDR Interrupt Disable register */ + __I uint32_t IVS; /* 0x014 AD16C4T_IVS Interrupt Valid status register */ + __I uint32_t RIF; /* 0x018 AD16C4T_RIF Interrupt Raw interrupt Flag */ + __I uint32_t IFM; /* 0x01C AD16C4T_IFM Interrupt Masked interrupt Flag */ + __O uint32_t ICR; /* 0x020 AD16C4T_ICR Interrupt Clear status register */ + __O uint32_t SGE; /* 0x024 AD16C4T_SGE Event generation register */ + __IO uint32_t CHMR1; /* 0x028 AD16C4T_CHMR1 Capture/compare mode register 1 */ + __IO uint32_t CHMR2; /* 0x02C AD16C4T_CHMR2 Capture/compare mode register 2 */ + __IO uint32_t CCEP; /* 0x030 AD16C4T_CCEP Capture/compare enable register */ + __IO uint32_t COUNT; /* 0x034 AD16C4T_COUNT Timer Counter */ + __IO uint32_t PRES; /* 0x038 AD16C4T_PRES Prescaler */ + __IO uint32_t AR; /* 0x03C AD16C4T_AR Auto-reload register */ + __IO uint32_t REPAR; /* 0x040 AD16C4T_REPAR Repetition counter register */ + __IO uint32_t CCVAL1; /* 0x044 AD16C4T_CCVAL1 Capture/compare register 1 */ + __IO uint32_t CCVAL2; /* 0x048 AD16C4T_CCVAL2 Capture/compare register 2 */ + __IO uint32_t CCVAL3; /* 0x04C AD16C4T_CCVAL3 Capture/compare register 3 */ + __IO uint32_t CCVAL4; /* 0x050 AD16C4T_CCVAL4 Capture/compare register 4 */ + __IO uint32_t BDCFG; /* 0x054 AD16C4T_BDCFG Break and dead-time register */ + __IO uint32_t DMAEN; /* 0x058 AD16C4T_DMAEN DMA trigger event enable */ +} AD16C4T_TypeDef; + +#endif +/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF REG_AD16C4T.H****/ + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..e1b57e2773c6fb7b4f19160047f8c1f75aaf12aa --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h @@ -0,0 +1,795 @@ +/** + ************************************************************************************** + * @file REG_ADC.h + * @brief ADC Header File + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for ADC_CFG register ************************/ + +#define ADC_CFG_TESTEN_POSS 8U +#define ADC_CFG_TESTEN_POSE 15U +#define ADC_CFG_TESTEN_MSK BITS(ADC_CFG_TESTEN_POSS,ADC_CFG_TESTEN_POSE) + +#define ADC_CFG_MODE_POS 0U +#define ADC_CFG_MODE_MSK BIT(ADC_CFG_MODE_POS) + +/****************** Bit definition for ADC_SRATE register ************************/ + +#define ADC_SRATE_CNT_POSS 16U +#define ADC_SRATE_CNT_POSE 23U +#define ADC_SRATE_CNT_MSK BITS(ADC_SRATE_CNT_POSS,ADC_SRATE_CNT_POSE) + +#define ADC_SRATE_CNTINI_POSS 8U +#define ADC_SRATE_CNTINI_POSE 15U +#define ADC_SRATE_CNTINI_MSK BITS(ADC_SRATE_CNTINI_POSS,ADC_SRATE_CNTINI_POSE) + +#define ADC_SRATE_CKDIV_POSS 1U +#define ADC_SRATE_CKDIV_POSE 4U +#define ADC_SRATE_CKDIV_MSK BITS(ADC_SRATE_CKDIV_POSS,ADC_SRATE_CKDIV_POSE) + +#define ADC_SRATE_CKEN_POS 0U +#define ADC_SRATE_CKEN_MSK BIT(ADC_SRATE_CKEN_POS) + +/****************** Bit definition for ADC_CHINV register ************************/ + +#define ADC_CHINV_CH15INV_POS 15U +#define ADC_CHINV_CH15INV_MSK BIT(ADC_CHINV_CH15INV_POS) + +#define ADC_CHINV_CH14INV_POS 14U +#define ADC_CHINV_CH14INV_MSK BIT(ADC_CHINV_CH14INV_POS) + +#define ADC_CHINV_CH13INV_POS 13U +#define ADC_CHINV_CH13INV_MSK BIT(ADC_CHINV_CH13INV_POS) + +#define ADC_CHINV_CH12INV_POS 12U +#define ADC_CHINV_CH12INV_MSK BIT(ADC_CHINV_CH12INV_POS) + +#define ADC_CHINV_CH11INV_POS 11U +#define ADC_CHINV_CH11INV_MSK BIT(ADC_CHINV_CH11INV_POS) + +#define ADC_CHINV_CH10INV_POS 10U +#define ADC_CHINV_CH10INV_MSK BIT(ADC_CHINV_CH10INV_POS) + +#define ADC_CHINV_CH9INV_POS 9U +#define ADC_CHINV_CH9INV_MSK BIT(ADC_CHINV_CH9INV_POS) + +#define ADC_CHINV_CH8INV_POS 8U +#define ADC_CHINV_CH8INV_MSK BIT(ADC_CHINV_CH8INV_POS) + +#define ADC_CHINV_CH7INV_POS 7U +#define ADC_CHINV_CH7INV_MSK BIT(ADC_CHINV_CH7INV_POS) + +#define ADC_CHINV_CH6INV_POS 6U +#define ADC_CHINV_CH6INV_MSK BIT(ADC_CHINV_CH6INV_POS) + +#define ADC_CHINV_CH5INV_POS 5U +#define ADC_CHINV_CH5INV_MSK BIT(ADC_CHINV_CH5INV_POS) + +#define ADC_CHINV_CH4INV_POS 4U +#define ADC_CHINV_CH4INV_MSK BIT(ADC_CHINV_CH4INV_POS) + +#define ADC_CHINV_CH3INV_POS 3U +#define ADC_CHINV_CH3INV_MSK BIT(ADC_CHINV_CH3INV_POS) + +#define ADC_CHINV_CH2INV_POS 2U +#define ADC_CHINV_CH2INV_MSK BIT(ADC_CHINV_CH2INV_POS) + +#define ADC_CHINV_CH1INV_POS 1U +#define ADC_CHINV_CH1INV_MSK BIT(ADC_CHINV_CH1INV_POS) + +#define ADC_CHINV_CH0INV_POS 0U +#define ADC_CHINV_CH0INV_MSK BIT(ADC_CHINV_CH0INV_POS) + +/****************** Bit definition for ADC_GAINL register ************************/ + +#define ADC_GAINL_CH7PGA_POSS 21U +#define ADC_GAINL_CH7PGA_POSE 23U +#define ADC_GAINL_CH7PGA_MSK BITS(ADC_GAINL_CH7PGA_POSS,ADC_GAINL_CH7PGA_POSE) + +#define ADC_GAINL_CH6PGA_POSS 18U +#define ADC_GAINL_CH6PGA_POSE 20U +#define ADC_GAINL_CH6PGA_MSK BITS(ADC_GAINL_CH6PGA_POSS,ADC_GAINL_CH6PGA_POSE) + +#define ADC_GAINL_CH5PGA_POSS 15U +#define ADC_GAINL_CH5PGA_POSE 17U +#define ADC_GAINL_CH5PGA_MSK BITS(ADC_GAINL_CH5PGA_POSS,ADC_GAINL_CH5PGA_POSE) + +#define ADC_GAINL_CH4PGA_POSS 12U +#define ADC_GAINL_CH4PGA_POSE 14U +#define ADC_GAINL_CH4PGA_MSK BITS(ADC_GAINL_CH4PGA_POSS,ADC_GAINL_CH4PGA_POSE) + +#define ADC_GAINL_CH3PGA_POSS 9U +#define ADC_GAINL_CH3PGA_POSE 11U +#define ADC_GAINL_CH3PGA_MSK BITS(ADC_GAINL_CH3PGA_POSS,ADC_GAINL_CH3PGA_POSE) + +#define ADC_GAINL_CH2PGA_POSS 6U +#define ADC_GAINL_CH2PGA_POSE 8U +#define ADC_GAINL_CH2PGA_MSK BITS(ADC_GAINL_CH2PGA_POSS,ADC_GAINL_CH2PGA_POSE) + +#define ADC_GAINL_CH1PGA_POSS 3U +#define ADC_GAINL_CH1PGA_POSE 5U +#define ADC_GAINL_CH1PGA_MSK BITS(ADC_GAINL_CH1PGA_POSS,ADC_GAINL_CH1PGA_POSE) + +#define ADC_GAINL_CH0PGA_POSS 0U +#define ADC_GAINL_CH0PGA_POSE 2U +#define ADC_GAINL_CH0PGA_MSK BITS(ADC_GAINL_CH0PGA_POSS,ADC_GAINL_CH0PGA_POSE) + +/****************** Bit definition for ADC_GAINH register ************************/ + +#define ADC_GAINH_CH15PGA_POSS 21U +#define ADC_GAINH_CH15PGA_POSE 23U +#define ADC_GAINH_CH15PGA_MSK BITS(ADC_GAINH_CH15PGA_POSS,ADC_GAINH_CH15PGA_POSE) + +#define ADC_GAINH_CH14PGA_POSS 18U +#define ADC_GAINH_CH14PGA_POSE 20U +#define ADC_GAINH_CH14PGA_MSK BITS(ADC_GAINH_CH14PGA_POSS,ADC_GAINH_CH14PGA_POSE) + +#define ADC_GAINH_CH13PGA_POSS 15U +#define ADC_GAINH_CH13PGA_POSE 17U +#define ADC_GAINH_CH13PGA_MSK BITS(ADC_GAINH_CH13PGA_POSS,ADC_GAINH_CH13PGA_POSE) + +#define ADC_GAINH_CH12PGA_POSS 12U +#define ADC_GAINH_CH12PGA_POSE 14U +#define ADC_GAINH_CH12PGA_MSK BITS(ADC_GAINH_CH12PGA_POSS,ADC_GAINH_CH12PGA_POSE) + +#define ADC_GAINH_CH11PGA_POSS 9U +#define ADC_GAINH_CH11PGA_POSE 11U +#define ADC_GAINH_CH11PGA_MSK BITS(ADC_GAINH_CH11PGA_POSS,ADC_GAINH_CH11PGA_POSE) + +#define ADC_GAINH_CH10PGA_POSS 6U +#define ADC_GAINH_CH10PGA_POSE 8U +#define ADC_GAINH_CH10PGA_MSK BITS(ADC_GAINH_CH10PGA_POSS,ADC_GAINH_CH10PGA_POSE) + +#define ADC_GAINH_CH9PGA_POSS 3U +#define ADC_GAINH_CH9PGA_POSE 5U +#define ADC_GAINH_CH9PGA_MSK BITS(ADC_GAINH_CH9PGA_POSS,ADC_GAINH_CH9PGA_POSE) + +#define ADC_GAINH_CH8PGA_POSS 0U +#define ADC_GAINH_CH8PGA_POSE 2U +#define ADC_GAINH_CH8PGA_MSK BITS(ADC_GAINH_CH8PGA_POSS,ADC_GAINH_CH8PGA_POSE) + +/****************** Bit definition for ADC_FRF register ************************/ + +#define ADC_FRF_FFRST_POS 4U +#define ADC_FRF_FFRST_MSK BIT(ADC_FRF_FFRST_POS) + +#define ADC_FRF_SS3RF_POS 3U +#define ADC_FRF_SS3RF_MSK BIT(ADC_FRF_SS3RF_POS) + +#define ADC_FRF_SS2RF_POS 2U +#define ADC_FRF_SS2RF_MSK BIT(ADC_FRF_SS2RF_POS) + +#define ADC_FRF_SS1RF_POS 1U +#define ADC_FRF_SS1RF_MSK BIT(ADC_FRF_SS1RF_POS) + +#define ADC_FRF_SS0RF_POS 0U +#define ADC_FRF_SS0RF_MSK BIT(ADC_FRF_SS0RF_POS) + +/****************** Bit definition for ADC_SSEN register ************************/ + +#define ADC_SSEN_IDLE_POS 4U +#define ADC_SSEN_IDLE_MSK BIT(ADC_SSEN_IDLE_POS) + +#define ADC_SSEN_SS3EN_POS 3U +#define ADC_SSEN_SS3EN_MSK BIT(ADC_SSEN_SS3EN_POS) + +#define ADC_SSEN_SS2EN_POS 2U +#define ADC_SSEN_SS2EN_MSK BIT(ADC_SSEN_SS2EN_POS) + +#define ADC_SSEN_SS1EN_POS 1U +#define ADC_SSEN_SS1EN_MSK BIT(ADC_SSEN_SS1EN_POS) + +#define ADC_SSEN_SS0EN_POS 0U +#define ADC_SSEN_SS0EN_MSK BIT(ADC_SSEN_SS0EN_POS) + +/****************** Bit definition for ADC_SWTRI register ************************/ + +#define ADC_SWTRI_SS3_POS 3U +#define ADC_SWTRI_SS3_MSK BIT(ADC_SWTRI_SS3_POS) + +#define ADC_SWTRI_SS2_POS 2U +#define ADC_SWTRI_SS2_MSK BIT(ADC_SWTRI_SS2_POS) + +#define ADC_SWTRI_SS1_POS 1U +#define ADC_SWTRI_SS1_MSK BIT(ADC_SWTRI_SS1_POS) + +#define ADC_SWTRI_SS0_POS 0U +#define ADC_SWTRI_SS0_MSK BIT(ADC_SWTRI_SS0_POS) + +/****************** Bit definition for ADC_IER register ************************/ + +#define ADC_IER_TOIE_POS 4U +#define ADC_IER_TOIE_MSK BIT(ADC_IER_TOIE_POS) + +#define ADC_IER_SS3IE_POS 3U +#define ADC_IER_SS3IE_MSK BIT(ADC_IER_SS3IE_POS) + +#define ADC_IER_SS2IE_POS 2U +#define ADC_IER_SS2IE_MSK BIT(ADC_IER_SS2IE_POS) + +#define ADC_IER_SS1IE_POS 1U +#define ADC_IER_SS1IE_MSK BIT(ADC_IER_SS1IE_POS) + +#define ADC_IER_SS0IE_POS 0U +#define ADC_IER_SS0IE_MSK BIT(ADC_IER_SS0IE_POS) + +/****************** Bit definition for ADC_IDR register ************************/ + +#define ADC_IDR_TOID_POS 4U +#define ADC_IDR_TOID_MSK BIT(ADC_IDR_TOID_POS) + +#define ADC_IDR_SS3ID_POS 3U +#define ADC_IDR_SS3ID_MSK BIT(ADC_IDR_SS3ID_POS) + +#define ADC_IDR_SS2ID_POS 2U +#define ADC_IDR_SS2ID_MSK BIT(ADC_IDR_SS2ID_POS) + +#define ADC_IDR_SS1ID_POS 1U +#define ADC_IDR_SS1ID_MSK BIT(ADC_IDR_SS1ID_POS) + +#define ADC_IDR_SS0ID_POS 0U +#define ADC_IDR_SS0ID_MSK BIT(ADC_IDR_SS0ID_POS) + +/****************** Bit definition for ADC_IVS register ************************/ + +#define ADC_IVS_TOIVS_POS 4U +#define ADC_IVS_TOIVS_MSK BIT(ADC_IVS_TOIVS_POS) + +#define ADC_IVS_SS3IVS_POS 3U +#define ADC_IVS_SS3IVS_MSK BIT(ADC_IVS_SS3IVS_POS) + +#define ADC_IVS_SS2IVS_POS 2U +#define ADC_IVS_SS2IVS_MSK BIT(ADC_IVS_SS2IVS_POS) + +#define ADC_IVS_SS1IVS_POS 1U +#define ADC_IVS_SS1IVS_MSK BIT(ADC_IVS_SS1IVS_POS) + +#define ADC_IVS_SS0IVS_POS 0U +#define ADC_IVS_SS0IVS_MSK BIT(ADC_IVS_SS0IVS_POS) + +/****************** Bit definition for ADC_RIF register ************************/ + +#define ADC_RIF_TORIF_POS 4U +#define ADC_RIF_TORIF_MSK BIT(ADC_RIF_TORIF_POS) + +#define ADC_RIF_SS3RIF_POS 3U +#define ADC_RIF_SS3RIF_MSK BIT(ADC_RIF_SS3RIF_POS) + +#define ADC_RIF_SS2RIF_POS 2U +#define ADC_RIF_SS2RIF_MSK BIT(ADC_RIF_SS2RIF_POS) + +#define ADC_RIF_SS1RIF_POS 1U +#define ADC_RIF_SS1RIF_MSK BIT(ADC_RIF_SS1RIF_POS) + +#define ADC_RIF_SS0RIF_POS 0U +#define ADC_RIF_SS0RIF_MSK BIT(ADC_RIF_SS0RIF_POS) + +/****************** Bit definition for ADC_IFM register ************************/ + +#define ADC_IFM_TOIFM_POS 4U +#define ADC_IFM_TOIFM_MSK BIT(ADC_IFM_TOIFM_POS) + +#define ADC_IFM_SS3IFM_POS 3U +#define ADC_IFM_SS3IFM_MSK BIT(ADC_IFM_SS3IFM_POS) + +#define ADC_IFM_SS2IFM_POS 2U +#define ADC_IFM_SS2IFM_MSK BIT(ADC_IFM_SS2IFM_POS) + +#define ADC_IFM_SS1IFM_POS 1U +#define ADC_IFM_SS1IFM_MSK BIT(ADC_IFM_SS1IFM_POS) + +#define ADC_IFM_SS0IFM_POS 0U +#define ADC_IFM_SS0IFM_MSK BIT(ADC_IFM_SS0IFM_POS) + +/****************** Bit definition for ADC_ICR register ************************/ + +#define ADC_ICR_TOICR_POS 4U +#define ADC_ICR_TOICR_MSK BIT(ADC_ICR_TOICR_POS) + +#define ADC_ICR_SS3ICR_POS 3U +#define ADC_ICR_SS3ICR_MSK BIT(ADC_ICR_SS3ICR_POS) + +#define ADC_ICR_SS2ICR_POS 2U +#define ADC_ICR_SS2ICR_MSK BIT(ADC_ICR_SS2ICR_POS) + +#define ADC_ICR_SS1ICR_POS 1U +#define ADC_ICR_SS1ICR_MSK BIT(ADC_ICR_SS1ICR_POS) + +#define ADC_ICR_SS0ICR_POS 0U +#define ADC_ICR_SS0ICR_MSK BIT(ADC_ICR_SS0ICR_POS) + +/****************** Bit definition for ADC_DMA register ************************/ + +#define ADC_DMA_SS3_DMAEN_POS 3U +#define ADC_DMA_SS3_DMAEN_MSK BIT(ADC_DMA_SS3_DMAEN_POS) + +#define ADC_DMA_SS2_DMAEN_POS 2U +#define ADC_DMA_SS2_DMAEN_MSK BIT(ADC_DMA_SS2_DMAEN_POS) + +#define ADC_DMA_SS1_DMAEN_POS 1U +#define ADC_DMA_SS1_DMAEN_MSK BIT(ADC_DMA_SS1_DMAEN_POS) + +#define ADC_DMA_SS0_DMAEN_POS 0U +#define ADC_DMA_SS0_DMAEN_MSK BIT(ADC_DMA_SS0_DMAEN_POS) + +/****************** Bit definition for ADC_SS0_CON register ************************/ + +#define ADC_SS0_CON_SEL_POSS 11U +#define ADC_SS0_CON_SEL_POSE 15U +#define ADC_SS0_CON_SEL_MSK BITS(ADC_SS0_CON_SEL_POSS,ADC_SS0_CON_SEL_POSE) + +#define ADC_SS0_CON_TYP_POS 8U +#define ADC_SS0_CON_TYP_MSK BIT(ADC_SS0_CON_TYP_POS) + +#define ADC_SS0_CON_PRI_POSS 4U +#define ADC_SS0_CON_PRI_POSE 5U +#define ADC_SS0_CON_PRI_MSK BITS(ADC_SS0_CON_PRI_POSS,ADC_SS0_CON_PRI_POSE) + +#define ADC_SS0_CON_ONE_POS 0U +#define ADC_SS0_CON_ONE_MSK BIT(ADC_SS0_CON_ONE_POS) + +/****************** Bit definition for ADC_SS0_MUX0 register ************************/ + +#define ADC_SS0_MUX0_MUX7_POSS 28U +#define ADC_SS0_MUX0_MUX7_POSE 31U +#define ADC_SS0_MUX0_MUX7_MSK BITS(ADC_SS0_MUX0_MUX7_POSS,ADC_SS0_MUX0_MUX7_POSE) + +#define ADC_SS0_MUX0_MUX6_POSS 24U +#define ADC_SS0_MUX0_MUX6_POSE 27U +#define ADC_SS0_MUX0_MUX6_MSK BITS(ADC_SS0_MUX0_MUX6_POSS,ADC_SS0_MUX0_MUX6_POSE) + +#define ADC_SS0_MUX0_MUX5_POSS 20U +#define ADC_SS0_MUX0_MUX5_POSE 23U +#define ADC_SS0_MUX0_MUX5_MSK BITS(ADC_SS0_MUX0_MUX5_POSS,ADC_SS0_MUX0_MUX5_POSE) + +#define ADC_SS0_MUX0_MUX4_POSS 16U +#define ADC_SS0_MUX0_MUX4_POSE 19U +#define ADC_SS0_MUX0_MUX4_MSK BITS(ADC_SS0_MUX0_MUX4_POSS,ADC_SS0_MUX0_MUX4_POSE) + +#define ADC_SS0_MUX0_MUX3_POSS 12U +#define ADC_SS0_MUX0_MUX3_POSE 15U +#define ADC_SS0_MUX0_MUX3_MSK BITS(ADC_SS0_MUX0_MUX3_POSS,ADC_SS0_MUX0_MUX3_POSE) + +#define ADC_SS0_MUX0_MUX2_POSS 8U +#define ADC_SS0_MUX0_MUX2_POSE 11U +#define ADC_SS0_MUX0_MUX2_MSK BITS(ADC_SS0_MUX0_MUX2_POSS,ADC_SS0_MUX0_MUX2_POSE) + +#define ADC_SS0_MUX0_MUX1_POSS 4U +#define ADC_SS0_MUX0_MUX1_POSE 7U +#define ADC_SS0_MUX0_MUX1_MSK BITS(ADC_SS0_MUX0_MUX1_POSS,ADC_SS0_MUX0_MUX1_POSE) + +#define ADC_SS0_MUX0_MUX0_POSS 0U +#define ADC_SS0_MUX0_MUX0_POSE 3U +#define ADC_SS0_MUX0_MUX0_MSK BITS(ADC_SS0_MUX0_MUX0_POSS,ADC_SS0_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS0_MUX1 register ************************/ + +#define ADC_SS0_MUX1_MUX15_POSS 28U +#define ADC_SS0_MUX1_MUX15_POSE 31U +#define ADC_SS0_MUX1_MUX15_MSK BITS(ADC_SS0_MUX1_MUX15_POSS,ADC_SS0_MUX1_MUX15_POSE) + +#define ADC_SS0_MUX1_MUX14_POSS 24U +#define ADC_SS0_MUX1_MUX14_POSE 27U +#define ADC_SS0_MUX1_MUX14_MSK BITS(ADC_SS0_MUX1_MUX14_POSS,ADC_SS0_MUX1_MUX14_POSE) + +#define ADC_SS0_MUX1_MUX13_POSS 20U +#define ADC_SS0_MUX1_MUX13_POSE 23U +#define ADC_SS0_MUX1_MUX13_MSK BITS(ADC_SS0_MUX1_MUX13_POSS,ADC_SS0_MUX1_MUX13_POSE) + +#define ADC_SS0_MUX1_MUX12_POSS 16U +#define ADC_SS0_MUX1_MUX12_POSE 19U +#define ADC_SS0_MUX1_MUX12_MSK BITS(ADC_SS0_MUX1_MUX12_POSS,ADC_SS0_MUX1_MUX12_POSE) + +#define ADC_SS0_MUX1_MUX11_POSS 12U +#define ADC_SS0_MUX1_MUX11_POSE 15U +#define ADC_SS0_MUX1_MUX11_MSK BITS(ADC_SS0_MUX1_MUX11_POSS,ADC_SS0_MUX1_MUX11_POSE) + +#define ADC_SS0_MUX1_MUX10_POSS 8U +#define ADC_SS0_MUX1_MUX10_POSE 11U +#define ADC_SS0_MUX1_MUX10_MSK BITS(ADC_SS0_MUX1_MUX10_POSS,ADC_SS0_MUX1_MUX10_POSE) + +#define ADC_SS0_MUX1_MUX9_POSS 4U +#define ADC_SS0_MUX1_MUX9_POSE 7U +#define ADC_SS0_MUX1_MUX9_MSK BITS(ADC_SS0_MUX1_MUX9_POSS,ADC_SS0_MUX1_MUX9_POSE) + +#define ADC_SS0_MUX1_MUX8_POSS 0U +#define ADC_SS0_MUX1_MUX8_POSE 3U +#define ADC_SS0_MUX1_MUX8_MSK BITS(ADC_SS0_MUX1_MUX8_POSS,ADC_SS0_MUX1_MUX8_POSE) + +/****************** Bit definition for ADC_SS0_END register ************************/ + +#define ADC_SS0_END_IE15_POS 23U +#define ADC_SS0_END_IE15_MSK BIT(ADC_SS0_END_IE15_POS) + +#define ADC_SS0_END_IE14_POS 22U +#define ADC_SS0_END_IE14_MSK BIT(ADC_SS0_END_IE14_POS) + +#define ADC_SS0_END_IE13_POS 21U +#define ADC_SS0_END_IE13_MSK BIT(ADC_SS0_END_IE13_POS) + +#define ADC_SS0_END_IE12_POS 20U +#define ADC_SS0_END_IE12_MSK BIT(ADC_SS0_END_IE12_POS) + +#define ADC_SS0_END_IE11_POS 19U +#define ADC_SS0_END_IE11_MSK BIT(ADC_SS0_END_IE11_POS) + +#define ADC_SS0_END_IE10_POS 18U +#define ADC_SS0_END_IE10_MSK BIT(ADC_SS0_END_IE10_POS) + +#define ADC_SS0_END_IE9_POS 17U +#define ADC_SS0_END_IE9_MSK BIT(ADC_SS0_END_IE9_POS) + +#define ADC_SS0_END_IE8_POS 16U +#define ADC_SS0_END_IE8_MSK BIT(ADC_SS0_END_IE8_POS) + +#define ADC_SS0_END_IE7_POS 15U +#define ADC_SS0_END_IE7_MSK BIT(ADC_SS0_END_IE7_POS) + +#define ADC_SS0_END_IE6_POS 14U +#define ADC_SS0_END_IE6_MSK BIT(ADC_SS0_END_IE6_POS) + +#define ADC_SS0_END_IE5_POS 13U +#define ADC_SS0_END_IE5_MSK BIT(ADC_SS0_END_IE5_POS) + +#define ADC_SS0_END_IE4_POS 12U +#define ADC_SS0_END_IE4_MSK BIT(ADC_SS0_END_IE4_POS) + +#define ADC_SS0_END_IE3_POS 11U +#define ADC_SS0_END_IE3_MSK BIT(ADC_SS0_END_IE3_POS) + +#define ADC_SS0_END_IE2_POS 10U +#define ADC_SS0_END_IE2_MSK BIT(ADC_SS0_END_IE2_POS) + +#define ADC_SS0_END_IE1_POS 9U +#define ADC_SS0_END_IE1_MSK BIT(ADC_SS0_END_IE1_POS) + +#define ADC_SS0_END_IE0_POS 8U +#define ADC_SS0_END_IE0_MSK BIT(ADC_SS0_END_IE0_POS) + +#define ADC_SS0_END_END_POSS 0U +#define ADC_SS0_END_END_POSE 3U +#define ADC_SS0_END_END_MSK BITS(ADC_SS0_END_END_POSS,ADC_SS0_END_END_POSE) + +/****************** Bit definition for ADC_SS0_FSTAT register ************************/ + +#define ADC_SS0_FSTAT_OV_POS 11U +#define ADC_SS0_FSTAT_OV_MSK BIT(ADC_SS0_FSTAT_OV_POS) + +#define ADC_SS0_FSTAT_FULL_POS 10U +#define ADC_SS0_FSTAT_FULL_MSK BIT(ADC_SS0_FSTAT_FULL_POS) + +#define ADC_SS0_FSTAT_UV_POS 9U +#define ADC_SS0_FSTAT_UV_MSK BIT(ADC_SS0_FSTAT_UV_POS) + +#define ADC_SS0_FSTAT_EMPTY_POS 8U +#define ADC_SS0_FSTAT_EMPTY_MSK BIT(ADC_SS0_FSTAT_EMPTY_POS) + +#define ADC_SS0_FSTAT_HPTR_POSS 4U +#define ADC_SS0_FSTAT_HPTR_POSE 7U +#define ADC_SS0_FSTAT_HPTR_MSK BITS(ADC_SS0_FSTAT_HPTR_POSS,ADC_SS0_FSTAT_HPTR_POSE) + +#define ADC_SS0_FSTAT_TPTR_POSS 0U +#define ADC_SS0_FSTAT_TPTR_POSE 3U +#define ADC_SS0_FSTAT_TPTR_MSK BITS(ADC_SS0_FSTAT_TPTR_POSS,ADC_SS0_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS0_DATA register ************************/ + +#define ADC_SS0_DATA_DATA_POSS 0U +#define ADC_SS0_DATA_DATA_POSE 11U +#define ADC_SS0_DATA_DATA_MSK BITS(ADC_SS0_DATA_DATA_POSS,ADC_SS0_DATA_DATA_POSE) + +/****************** Bit definition for ADC_SS1_CON register ************************/ + +#define ADC_SS1_CON_SEL_POSS 11U +#define ADC_SS1_CON_SEL_POSE 15U +#define ADC_SS1_CON_SEL_MSK BITS(ADC_SS1_CON_SEL_POSS,ADC_SS1_CON_SEL_POSE) + +#define ADC_SS1_CON_TYP_POS 8U +#define ADC_SS1_CON_TYP_MSK BIT(ADC_SS1_CON_TYP_POS) + +#define ADC_SS1_CON_PRI_POSS 4U +#define ADC_SS1_CON_PRI_POSE 5U +#define ADC_SS1_CON_PRI_MSK BITS(ADC_SS1_CON_PRI_POSS,ADC_SS1_CON_PRI_POSE) + +#define ADC_SS1_CON_ONE_POS 0U +#define ADC_SS1_CON_ONE_MSK BIT(ADC_SS1_CON_ONE_POS) + +/****************** Bit definition for ADC_SS1_MUX0 register ************************/ + +#define ADC_SS1_MUX0_MUX7_POSS 28U +#define ADC_SS1_MUX0_MUX7_POSE 31U +#define ADC_SS1_MUX0_MUX7_MSK BITS(ADC_SS1_MUX0_MUX7_POSS,ADC_SS1_MUX0_MUX7_POSE) + +#define ADC_SS1_MUX0_MUX6_POSS 24U +#define ADC_SS1_MUX0_MUX6_POSE 27U +#define ADC_SS1_MUX0_MUX6_MSK BITS(ADC_SS1_MUX0_MUX6_POSS,ADC_SS1_MUX0_MUX6_POSE) + +#define ADC_SS1_MUX0_MUX5_POSS 20U +#define ADC_SS1_MUX0_MUX5_POSE 23U +#define ADC_SS1_MUX0_MUX5_MSK BITS(ADC_SS1_MUX0_MUX5_POSS,ADC_SS1_MUX0_MUX5_POSE) + +#define ADC_SS1_MUX0_MUX4_POSS 16U +#define ADC_SS1_MUX0_MUX4_POSE 19U +#define ADC_SS1_MUX0_MUX4_MSK BITS(ADC_SS1_MUX0_MUX4_POSS,ADC_SS1_MUX0_MUX4_POSE) + +#define ADC_SS1_MUX0_MUX3_POSS 12U +#define ADC_SS1_MUX0_MUX3_POSE 15U +#define ADC_SS1_MUX0_MUX3_MSK BITS(ADC_SS1_MUX0_MUX3_POSS,ADC_SS1_MUX0_MUX3_POSE) + +#define ADC_SS1_MUX0_MUX2_POSS 8U +#define ADC_SS1_MUX0_MUX2_POSE 11U +#define ADC_SS1_MUX0_MUX2_MSK BITS(ADC_SS1_MUX0_MUX2_POSS,ADC_SS1_MUX0_MUX2_POSE) + +#define ADC_SS1_MUX0_MUX1_POSS 4U +#define ADC_SS1_MUX0_MUX1_POSE 7U +#define ADC_SS1_MUX0_MUX1_MSK BITS(ADC_SS1_MUX0_MUX1_POSS,ADC_SS1_MUX0_MUX1_POSE) + +#define ADC_SS1_MUX0_MUX0_POSS 0U +#define ADC_SS1_MUX0_MUX0_POSE 3U +#define ADC_SS1_MUX0_MUX0_MSK BITS(ADC_SS1_MUX0_MUX0_POSS,ADC_SS1_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS1_END register ************************/ + +#define ADC_SS1_END_IE7_POS 15U +#define ADC_SS1_END_IE7_MSK BIT(ADC_SS1_END_IE7_POS) + +#define ADC_SS1_END_IE6_POS 14U +#define ADC_SS1_END_IE6_MSK BIT(ADC_SS1_END_IE6_POS) + +#define ADC_SS1_END_IE5_POS 13U +#define ADC_SS1_END_IE5_MSK BIT(ADC_SS1_END_IE5_POS) + +#define ADC_SS1_END_IE4_POS 12U +#define ADC_SS1_END_IE4_MSK BIT(ADC_SS1_END_IE4_POS) + +#define ADC_SS1_END_IE3_POS 11U +#define ADC_SS1_END_IE3_MSK BIT(ADC_SS1_END_IE3_POS) + +#define ADC_SS1_END_IE2_POS 10U +#define ADC_SS1_END_IE2_MSK BIT(ADC_SS1_END_IE2_POS) + +#define ADC_SS1_END_IE1_POS 9U +#define ADC_SS1_END_IE1_MSK BIT(ADC_SS1_END_IE1_POS) + +#define ADC_SS1_END_IE0_POS 8U +#define ADC_SS1_END_IE0_MSK BIT(ADC_SS1_END_IE0_POS) + +#define ADC_SS1_END_END_POSS 0U +#define ADC_SS1_END_END_POSE 2U +#define ADC_SS1_END_END_MSK BITS(ADC_SS1_END_END_POSS,ADC_SS1_END_END_POSE) + +/****************** Bit definition for ADC_SS1_FSTAT register ************************/ + +#define ADC_SS1_FSTAT_OV_POS 11U +#define ADC_SS1_FSTAT_OV_MSK BIT(ADC_SS1_FSTAT_OV_POS) + +#define ADC_SS1_FSTAT_FULL_POS 10U +#define ADC_SS1_FSTAT_FULL_MSK BIT(ADC_SS1_FSTAT_FULL_POS) + +#define ADC_SS1_FSTAT_UV_POS 9U +#define ADC_SS1_FSTAT_UV_MSK BIT(ADC_SS1_FSTAT_UV_POS) + +#define ADC_SS1_FSTAT_EMPTY_POS 8U +#define ADC_SS1_FSTAT_EMPTY_MSK BIT(ADC_SS1_FSTAT_EMPTY_POS) + +#define ADC_SS1_FSTAT_HPTR_POSS 4U +#define ADC_SS1_FSTAT_HPTR_POSE 7U +#define ADC_SS1_FSTAT_HPTR_MSK BITS(ADC_SS1_FSTAT_HPTR_POSS,ADC_SS1_FSTAT_HPTR_POSE) + +#define ADC_SS1_FSTAT_TPTR_POSS 0U +#define ADC_SS1_FSTAT_TPTR_POSE 3U +#define ADC_SS1_FSTAT_TPTR_MSK BITS(ADC_SS1_FSTAT_TPTR_POSS,ADC_SS1_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS1_DATA register ************************/ + +#define ADC_SS1_DATA_DATA_POSS 0U +#define ADC_SS1_DATA_DATA_POSE 11U +#define ADC_SS1_DATA_DATA_MSK BITS(ADC_SS1_DATA_DATA_POSS,ADC_SS1_DATA_DATA_POSE) + +/****************** Bit definition for ADC_SS2_CON register ************************/ + +#define ADC_SS2_CON_SEL_POSS 11U +#define ADC_SS2_CON_SEL_POSE 15U +#define ADC_SS2_CON_SEL_MSK BITS(ADC_SS2_CON_SEL_POSS,ADC_SS2_CON_SEL_POSE) + +#define ADC_SS2_CON_TYP_POS 8U +#define ADC_SS2_CON_TYP_MSK BIT(ADC_SS2_CON_TYP_POS) + +#define ADC_SS2_CON_PRI_POSS 4U +#define ADC_SS2_CON_PRI_POSE 5U +#define ADC_SS2_CON_PRI_MSK BITS(ADC_SS2_CON_PRI_POSS,ADC_SS2_CON_PRI_POSE) + +#define ADC_SS2_CON_ONE_POS 0U +#define ADC_SS2_CON_ONE_MSK BIT(ADC_SS2_CON_ONE_POS) + +/****************** Bit definition for ADC_SS2_MUX0 register ************************/ + +#define ADC_SS2_MUX0_MUX3_POSS 12U +#define ADC_SS2_MUX0_MUX3_POSE 15U +#define ADC_SS2_MUX0_MUX3_MSK BITS(ADC_SS2_MUX0_MUX3_POSS,ADC_SS2_MUX0_MUX3_POSE) + +#define ADC_SS2_MUX0_MUX2_POSS 8U +#define ADC_SS2_MUX0_MUX2_POSE 11U +#define ADC_SS2_MUX0_MUX2_MSK BITS(ADC_SS2_MUX0_MUX2_POSS,ADC_SS2_MUX0_MUX2_POSE) + +#define ADC_SS2_MUX0_MUX1_POSS 4U +#define ADC_SS2_MUX0_MUX1_POSE 7U +#define ADC_SS2_MUX0_MUX1_MSK BITS(ADC_SS2_MUX0_MUX1_POSS,ADC_SS2_MUX0_MUX1_POSE) + +#define ADC_SS2_MUX0_MUX0_POSS 0U +#define ADC_SS2_MUX0_MUX0_POSE 3U +#define ADC_SS2_MUX0_MUX0_MSK BITS(ADC_SS2_MUX0_MUX0_POSS,ADC_SS2_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS2_END register ************************/ + +#define ADC_SS2_END_IE3_POS 11U +#define ADC_SS2_END_IE3_MSK BIT(ADC_SS2_END_IE3_POS) + +#define ADC_SS2_END_IE2_POS 10U +#define ADC_SS2_END_IE2_MSK BIT(ADC_SS2_END_IE2_POS) + +#define ADC_SS2_END_IE1_POS 9U +#define ADC_SS2_END_IE1_MSK BIT(ADC_SS2_END_IE1_POS) + +#define ADC_SS2_END_IE0_POS 8U +#define ADC_SS2_END_IE0_MSK BIT(ADC_SS2_END_IE0_POS) + +#define ADC_SS2_END_END_POSS 0U +#define ADC_SS2_END_END_POSE 1U +#define ADC_SS2_END_END_MSK BITS(ADC_SS2_END_END_POSS,ADC_SS2_END_END_POSE) + +/****************** Bit definition for ADC_SS2_FSTAT register ************************/ + +#define ADC_SS2_FSTAT_OV_POS 11U +#define ADC_SS2_FSTAT_OV_MSK BIT(ADC_SS2_FSTAT_OV_POS) + +#define ADC_SS2_FSTAT_FULL_POS 10U +#define ADC_SS2_FSTAT_FULL_MSK BIT(ADC_SS2_FSTAT_FULL_POS) + +#define ADC_SS2_FSTAT_UV_POS 9U +#define ADC_SS2_FSTAT_UV_MSK BIT(ADC_SS2_FSTAT_UV_POS) + +#define ADC_SS2_FSTAT_EMPTY_POS 8U +#define ADC_SS2_FSTAT_EMPTY_MSK BIT(ADC_SS2_FSTAT_EMPTY_POS) + +#define ADC_SS2_FSTAT_HPTR_POSS 4U +#define ADC_SS2_FSTAT_HPTR_POSE 7U +#define ADC_SS2_FSTAT_HPTR_MSK BITS(ADC_SS2_FSTAT_HPTR_POSS,ADC_SS2_FSTAT_HPTR_POSE) + +#define ADC_SS2_FSTAT_TPTR_POSS 0U +#define ADC_SS2_FSTAT_TPTR_POSE 3U +#define ADC_SS2_FSTAT_TPTR_MSK BITS(ADC_SS2_FSTAT_TPTR_POSS,ADC_SS2_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS2_DATA register ************************/ + +#define ADC_SS2_DATA_DATA_POSS 0U +#define ADC_SS2_DATA_DATA_POSE 11U +#define ADC_SS2_DATA_DATA_MSK BITS(ADC_SS2_DATA_DATA_POSS,ADC_SS2_DATA_DATA_POSE) + +/****************** Bit definition for ADC_SS3_CON register ************************/ + +#define ADC_SS3_CON_SEL_POSS 11U +#define ADC_SS3_CON_SEL_POSE 15U +#define ADC_SS3_CON_SEL_MSK BITS(ADC_SS3_CON_SEL_POSS,ADC_SS3_CON_SEL_POSE) + +#define ADC_SS3_CON_TYP_POS 8U +#define ADC_SS3_CON_TYP_MSK BIT(ADC_SS3_CON_TYP_POS) + +#define ADC_SS3_CON_PRI_POSS 4U +#define ADC_SS3_CON_PRI_POSE 5U +#define ADC_SS3_CON_PRI_MSK BITS(ADC_SS3_CON_PRI_POSS,ADC_SS3_CON_PRI_POSE) + +#define ADC_SS3_CON_ONE_POS 0U +#define ADC_SS3_CON_ONE_MSK BIT(ADC_SS3_CON_ONE_POS) + +/****************** Bit definition for ADC_SS3_MUX0 register ************************/ + +#define ADC_SS3_MUX0_MUX0_POSS 0U +#define ADC_SS3_MUX0_MUX0_POSE 3U +#define ADC_SS3_MUX0_MUX0_MSK BITS(ADC_SS3_MUX0_MUX0_POSS,ADC_SS3_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS3_END register ************************/ + +#define ADC_SS3_END_IE0_POS 8U +#define ADC_SS3_END_IE0_MSK BIT(ADC_SS3_END_IE0_POS) + +#define ADC_SS3_END_END_POS 0U +#define ADC_SS3_END_END_MSK BIT(ADC_SS3_END_END_POS) + +/****************** Bit definition for ADC_SS3_FSTAT register ************************/ + +#define ADC_SS3_FSTAT_OV_POS 11U +#define ADC_SS3_FSTAT_OV_MSK BIT(ADC_SS3_FSTAT_OV_POS) + +#define ADC_SS3_FSTAT_FULL_POS 10U +#define ADC_SS3_FSTAT_FULL_MSK BIT(ADC_SS3_FSTAT_FULL_POS) + +#define ADC_SS3_FSTAT_UV_POS 9U +#define ADC_SS3_FSTAT_UV_MSK BIT(ADC_SS3_FSTAT_UV_POS) + +#define ADC_SS3_FSTAT_EMPTY_POS 8U +#define ADC_SS3_FSTAT_EMPTY_MSK BIT(ADC_SS3_FSTAT_EMPTY_POS) + +#define ADC_SS3_FSTAT_HPTR_POSS 4U +#define ADC_SS3_FSTAT_HPTR_POSE 7U +#define ADC_SS3_FSTAT_HPTR_MSK BITS(ADC_SS3_FSTAT_HPTR_POSS,ADC_SS3_FSTAT_HPTR_POSE) + +#define ADC_SS3_FSTAT_TPTR_POSS 0U +#define ADC_SS3_FSTAT_TPTR_POSE 3U +#define ADC_SS3_FSTAT_TPTR_MSK BITS(ADC_SS3_FSTAT_TPTR_POSS,ADC_SS3_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS3_DATA register ************************/ + +#define ADC_SS3_DATA_DATA_POSS 0U +#define ADC_SS3_DATA_DATA_POSE 11U +#define ADC_SS3_DATA_DATA_MSK BITS(ADC_SS3_DATA_DATA_POSS,ADC_SS3_DATA_DATA_POSE) + +typedef struct +{ + __IO uint32_t CFG; + __IO uint32_t SRATE; + __IO uint32_t CHINV; + __IO uint32_t GAINL; + __IO uint32_t GAINH; + __O uint32_t FRF; + __IO uint32_t SSEN; + __IO uint32_t SWTRI; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __IO uint32_t DMA; + uint32_t RESERVED0 ; + __IO uint32_t SS0_CON; + __IO uint32_t SS0_MUX0; + __IO uint32_t SS0_MUX1; + __IO uint32_t SS0_END; + __I uint32_t SS0_FSTAT; + __IO uint32_t SS0_DATA; + uint32_t RESERVED1[2] ; + __IO uint32_t SS1_CON; + __IO uint32_t SS1_MUX0; + __IO uint32_t SS1_END; + __I uint32_t SS1_FSTAT; + __IO uint32_t SS1_DATA; + uint32_t RESERVED2 ; + __IO uint32_t SS2_CON; + __IO uint32_t SS2_MUX0; + __IO uint32_t SS2_END; + __I uint32_t SS2_FSTAT; + __IO uint32_t SS2_DATA; + uint32_t RESERVED3 ; + __IO uint32_t SS3_CON; + __IO uint32_t SS3_MUX0; + __IO uint32_t SS3_END; + __I uint32_t SS3_FSTAT; + __IO uint32_t SS3_DATA; +} ADC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..dd47cdea101d554d024022e839c8710e02f2e3a9 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h @@ -0,0 +1,193 @@ +/** + ************************************************************************************** + * @file REG_AES.h + * @brief AES Head File + * + * @version V0.01 + * @data 11/16/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __AES_H__ +#define __AES_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for AES_CON register ************************/ + +#define AES_CON_READY_POS 22U +#define AES_CON_READY_MSK BIT(AES_CON_READY_POS) + +#define AES_CON_OT_DMA_ST_POS 21U +#define AES_CON_OT_DMA_ST_MSK BIT(AES_CON_OT_DMA_ST_POS) + +#define AES_CON_IT_DMA_ST_POS 20U +#define AES_CON_IT_DMA_ST_MSK BIT(AES_CON_IT_DMA_ST_POS) + +#define AES_CON_OT_DEPTH_POSS 18U +#define AES_CON_OT_DEPTH_POSE 19U +#define AES_CON_OT_DEPTH_MSK BITS(AES_CON_OT_DEPTH_POSS,AES_CON_OT_DEPTH_POSE) + +#define AES_CON_IT_DEPTH_POSS 16U +#define AES_CON_IT_DEPTH_POSE 17U +#define AES_CON_IT_DEPTH_MSK BITS(AES_CON_IT_DEPTH_POSS,AES_CON_IT_DEPTH_POSE) + +#define AES_CON_RE_INIT_POS 8U +#define AES_CON_RE_INIT_MSK BIT(AES_CON_RE_INIT_POS) + +#define AES_CON_DMA_EN_POSS 6U +#define AES_CON_DMA_EN_POSE 7U +#define AES_CON_DMA_EN_MSK BITS(AES_CON_DMA_EN_POSS,AES_CON_DMA_EN_POSE) + +#define AES_CON_BL_POSS 3U +#define AES_CON_BL_POSE 5U +#define AES_CON_BL_MSK BITS(AES_CON_BL_POSS,AES_CON_BL_POSE) + +#define AES_CON_REV_POS 2U +#define AES_CON_REV_MSK BIT(AES_CON_REV_POS) + +#define AES_CON_MODE_POS 1U +#define AES_CON_MODE_MSK BIT(AES_CON_MODE_POS) + +#define AES_CON_START_POS 0U +#define AES_CON_START_MSK BIT(AES_CON_START_POS) + +/****************** Bit definition for AES_IER register ************************/ + +#define AES_IER_DECIE_POS 1U +#define AES_IER_DECIE_MSK BIT(AES_IER_DECIE_POS) + +#define AES_IER_ENCIE_POS 0U +#define AES_IER_ENCIE_MSK BIT(AES_IER_ENCIE_POS) + +/****************** Bit definition for AES_IDR register ************************/ + +#define AES_IDR_DECID_POS 1U +#define AES_IDR_DECID_MSK BIT(AES_IDR_DECID_POS) + +#define AES_IDR_ENCID_POS 0U +#define AES_IDR_ENCID_MSK BIT(AES_IDR_ENCID_POS) + +/****************** Bit definition for AES_IVS register ************************/ + +#define AES_IVS_DECIVS_POS 1U +#define AES_IVS_DECIVS_MSK BIT(AES_IVS_DECIVS_POS) + +#define AES_IVS_ENCIVS_POS 0U +#define AES_IVS_ENCIVS_MSK BIT(AES_IVS_ENCIVS_POS) + +/****************** Bit definition for AES_RIF register ************************/ + +#define AES_RIF_DECRIF_POS 1U +#define AES_RIF_DECRIF_MSK BIT(AES_RIF_DECRIF_POS) + +#define AES_RIF_ENCRIF_POS 0U +#define AES_RIF_ENCRIF_MSK BIT(AES_RIF_ENCRIF_POS) + +/****************** Bit definition for AES_IFM register ************************/ + +#define AES_IFM_DECIFM_POS 1U +#define AES_IFM_DECIFM_MSK BIT(AES_IFM_DECIFM_POS) + +#define AES_IFM_ENCIFM_POS 0U +#define AES_IFM_ENCIFM_MSK BIT(AES_IFM_ENCIFM_POS) + +/****************** Bit definition for AES_ICR register ************************/ + +#define AES_ICR_DECICR_POS 1U +#define AES_ICR_DECICR_MSK BIT(AES_ICR_DECICR_POS) + +#define AES_ICR_ENCICR_POS 0U +#define AES_ICR_ENCICR_MSK BIT(AES_ICR_ENCICR_POS) + +/****************** Bit definition for AES_DIO register ************************/ + +#define AES_DIO_DIO_POSS 0U +#define AES_DIO_DIO_POSE 31U +#define AES_DIO_DIO_MSK BITS(AES_DIO_DIO_POSS,AES_DIO_DIO_POSE) + +/****************** Bit definition for AES_KEY0 register ************************/ + +#define AES_KEY0_KEY0_POSS 0U +#define AES_KEY0_KEY0_POSE 31U +#define AES_KEY0_KEY0_MSK BITS(AES_KEY0_KEY0_POSS,AES_KEY0_KEY0_POSE) + +/****************** Bit definition for AES_KEY1 register ************************/ + +#define AES_KEY1_KEY1_POSS 0U +#define AES_KEY1_KEY1_POSE 31U +#define AES_KEY1_KEY1_MSK BITS(AES_KEY1_KEY1_POSS,AES_KEY1_KEY1_POSE) + +/****************** Bit definition for AES_KEY2 register ************************/ + +#define AES_KEY2_KEY2_POSS 0U +#define AES_KEY2_KEY2_POSE 31U +#define AES_KEY2_KEY2_MSK BITS(AES_KEY2_KEY2_POSS,AES_KEY2_KEY2_POSE) + +/****************** Bit definition for AES_KEY3 register ************************/ + +#define AES_KEY3_KEY3_POSS 0U +#define AES_KEY3_KEY3_POSE 31U +#define AES_KEY3_KEY3_MSK BITS(AES_KEY3_KEY3_POSS,AES_KEY3_KEY3_POSE) + +/****************** Bit definition for AES_IV0 register ************************/ + +#define AES_IV0_IV0_POSS 0U +#define AES_IV0_IV0_POSE 31U +#define AES_IV0_IV0_MSK BITS(AES_IV0_IV0_POSS,AES_IV0_IV0_POSE) + +/****************** Bit definition for AES_IV1 register ************************/ + +#define AES_IV1_IV1_POSS 0U +#define AES_IV1_IV1_POSE 31U +#define AES_IV1_IV1_MSK BITS(AES_IV1_IV1_POSS,AES_IV1_IV1_POSE) + +/****************** Bit definition for AES_IV2 register ************************/ + +#define AES_IV2_IV2_POSS 0U +#define AES_IV2_IV2_POSE 31U +#define AES_IV2_IV2_MSK BITS(AES_IV2_IV2_POSS,AES_IV2_IV2_POSE) + +/****************** Bit definition for AES_IV3 register ************************/ + +#define AES_IV3_IV3_POSS 0U +#define AES_IV3_IV3_POSE 31U +#define AES_IV3_IV3_MSK BITS(AES_IV3_IV3_POSS,AES_IV3_IV3_POSE) + +typedef struct +{ + __IO uint32_t CON; /* 0x000 AES_CON AES Control Register */ + __O uint32_t IER; /* 0x004 AES_IER AES Interrupt Enable Register */ + __O uint32_t IDR; /* 0x008 AES_IDR AES Interrupt Disable Register */ + __I uint32_t IVS; /* 0x00C AES_IVS AES Interrupt Valid Status Register */ + __I uint32_t RIF; /* 0x010 AES_RIF AES Raw Interrupt Flag Status Register */ + __I uint32_t IFM; /* 0x014 AES_IFM AES Interrupt Flag Masked Register */ + __O uint32_t ICR; /* 0x018 AES_ICR AES Interrupt Clear Register */ + __IO uint32_t DIO; /* 0x01C AES_DIO AES 128-bit Input/Output Data Register */ + __IO uint32_t KEY0; /* 0x020 AES_KEY0 AES 256-bit Keyword Register 0 */ + __IO uint32_t KEY1; /* 0x024 AES_KEY1 AES 256-bit Keyword Register 1 */ + __IO uint32_t KEY2; /* 0x028 AES_KEY2 AES 256-bit Keyword Register 2 */ + __IO uint32_t KEY3; /* 0x02C AES_KEY3 AES 256-bit Keyword Register 3 */ + uint32_t RESERVED0[4] ; + __IO uint32_t IV0; /* 0x040 AES_IV0 AES 128-bit Initial Vector Register 0 */ + __IO uint32_t IV1; /* 0x044 AES_IV1 AES 128-bit Initial Vector Register 1 */ + __IO uint32_t IV2; /* 0x048 AES_IV2 AES 128-bit Initial Vector Register 2 */ + __IO uint32_t IV3; /* 0x04C AES_IV3 AES 128-bit Initial Vector Register 3 */ +} AES_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h new file mode 100644 index 0000000000000000000000000000000000000000..8b1f4e5de6c77fcc89d6e9209e7296175de09446 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h @@ -0,0 +1,95 @@ +/** + ************************************************************************************** + * @file REG_CMP.h + * @brief CMP Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __CMP_H__ +#define __CMP_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for CMP_CON register ************************/ + +#define CMP_CON_REFON_POS 4U +#define CMP_CON_REFON_MSK BIT(CMP_CON_REFON_POS) + +#define CMP_CON_CMPON2_POS 1U +#define CMP_CON_CMPON2_MSK BIT(CMP_CON_CMPON2_POS) + +#define CMP_CON_CMPON1_POS 0U +#define CMP_CON_CMPON1_MSK BIT(CMP_CON_CMPON1_POS) + +/****************** Bit definition for CMP_CFG1 register ************************/ + +#define CMP_CFG1_RS_POSS 4U +#define CMP_CFG1_RS_POSE 5U +#define CMP_CFG1_RS_MSK BITS(CMP_CFG1_RS_POSS,CMP_CFG1_RS_POSE) + +#define CMP_CFG1_FEN_POS 3U +#define CMP_CFG1_FEN_MSK BIT(CMP_CFG1_FEN_POS) + +#define CMP_CFG1_PSEN_POS 2U +#define CMP_CFG1_PSEN_MSK BIT(CMP_CFG1_PSEN_POS) + +#define CMP_CFG1_INSEL_POS 1U +#define CMP_CFG1_INSEL_MSK BIT(CMP_CFG1_INSEL_POS) + +#define CMP_CFG1_IPSEL_POS 0U +#define CMP_CFG1_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS) + +/****************** Bit definition for CMP_CFG2 register ************************/ + +#define CMP_CFG2_RS_POSS 4U +#define CMP_CFG2_RS_POSE 5U +#define CMP_CFG2_RS_MSK BITS(CMP_CFG2_RS_POSS,CMP_CFG2_RS_POSE) + +#define CMP_CFG2_FEN_POS 3U +#define CMP_CFG2_FEN_MSK BIT(CMP_CFG1_FEN_POS) + +#define CMP_CFG2_PSEN_POS 2U +#define CMP_CFG2_PSEN_MSK BIT(CMP_CFG1_PSEN_POS) + +#define CMP_CFG2_INSEL_POS 1U +#define CMP_CFG2_INSEL_MSK BIT(CMP_CFG1_INSEL_POS) + +#define CMP_CFG2_IPSEL_POS 0U +#define CMP_CFG2_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS) + +/****************** Bit definition for CMP_RULT register ************************/ + +#define CMP_RULT_CMPO2_POS 1U +#define CMP_RULT_CMPO2_MSK BIT(CMP_RULT_CMPO2_POS) + +#define CMP_RULT_CMPO1_POS 0U +#define CMP_RULT_CMPO1_MSK BIT(CMP_RULT_CMPO1_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG1; + __IO uint32_t CFG2; + uint32_t RESERVED0[2] ; + __I uint32_t RULT; +} CMP_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..cdbb00b45c61c7d5d4e3e94bf1c28b67474583c7 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h @@ -0,0 +1,125 @@ +/** + ************************************************************************************** + * @file REG_CRC.h + * @brief CRC Head File + * + * @version V0.01 + * @data 11/16/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for CRC_INIT register ************************/ + +#define CRC_INIT_INIT_POSS 0U +#define CRC_INIT_INIT_POSE 31U +#define CRC_INIT_INIT_MSK BITS(CRC_INIT_INIT_POSS,CRC_INIT_INIT_POSE) + +/****************** Bit definition for CRC_POLY register ************************/ + +#define CRC_POLY_POLY_POSS 0U +#define CRC_POLY_POLY_POSE 31U +#define CRC_POLY_POLY_MSK BITS(CRC_POLY_POLY_POSS,CRC_POLY_POLY_POSE) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_COMP register ************************/ + +#define CRC_COMP_COMP_POSS 0U +#define CRC_COMP_COMP_POSE 31U +#define CRC_COMP_COMP_MSK BITS(CRC_COMP_COMP_POSS,CRC_COMP_COMP_POSE) + +/****************** Bit definition for CRC_REMA register ************************/ + +#define CRC_REMA_REMA_POSS 0U +#define CRC_REMA_REMA_POSE 31U +#define CRC_REMA_REMA_MSK BITS(CRC_REMA_REMA_POSS,CRC_REMA_REMA_POSE) + +/****************** Bit definition for CRC_CON register ************************/ + +#define CRC_CON_DMA_POS 16U +#define CRC_CON_DMA_MSK BIT(CRC_CON_DMA_POS) + +#define CRC_CON_MSB_POS 12U +#define CRC_CON_MSB_MSK BIT(CRC_CON_MSB_POS) + +#define CRC_CON_REOUT_POS 10U +#define CRC_CON_REOUT_MSK BIT(CRC_CON_REOUT_POS) + +#define CRC_CON_REIN_POS 8U +#define CRC_CON_REIN_MSK BIT(CRC_CON_REIN_POS) + +#define CRC_CON_SIZE_POSS 4U +#define CRC_CON_SIZE_POSE 5U +#define CRC_CON_SIZE_MSK BITS(CRC_CON_SIZE_POSS,CRC_CON_SIZE_POSE) + +#define CRC_CON_MODE_POSS 2U +#define CRC_CON_MODE_POSE 3U +#define CRC_CON_MODE_MSK BITS(CRC_CON_MODE_POSS,CRC_CON_MODE_POSE) + +#define CRC_CON_RESET_POS 0U +#define CRC_CON_RESET_MSK BIT(CRC_CON_RESET_POS) + +/****************** Bit definition for CRC_DOUT register ************************/ + +#define CRC_DOUT_DOUT_POSS 0U +#define CRC_DOUT_DOUT_POSE 31U +#define CRC_DOUT_DOUT_MSK BITS(CRC_DOUT_DOUT_POSS,CRC_DOUT_DOUT_POSE) + +/****************** Bit definition for CRC_DOUT_XOR register ************************/ + +#define CRC_DOUT_XOR_DOUT_XOR_POSS 0U +#define CRC_DOUT_XOR_DOUT_XOR_POSE 31U +#define CRC_DOUT_XOR_DOUT_XOR_MSK BITS(CRC_DOUT_XOR_DOUT_XOR_POSS,CRC_DOUT_XOR_DOUT_XOR_POSE) + +/****************** Bit definition for CRC_STAT register ************************/ + +#define CRC_STAT_FAIL_POS 8U +#define CRC_STAT_FAIL_MSK BIT(CRC_STAT_FAIL_POS) + +#define CRC_STAT_EMPTY_POS 2U +#define CRC_STAT_EMPTY_MSK BIT(CRC_STAT_EMPTY_POS) + +#define CRC_STAT_BUSY_POS 1U +#define CRC_STAT_BUSY_MSK BIT(CRC_STAT_BUSY_POS) + +#define CRC_STAT_DONE_POS 0U +#define CRC_STAT_DONE_MSK BIT(CRC_STAT_DONE_POS) + +typedef struct +{ + __IO uint32_t INIT; /* 0x000 CRC_INIT CRC Iintial Value Register */ + __IO uint32_t POLY; /* 0x004 CRC_POLY CRC Polynomial Register */ + __IO uint32_t DATA; /* 0x008 CRC_DATA CRC Input Data Register */ + __IO uint32_t COMP; /* 0x00C CRC_COMP CRC Compare Data Register */ + __IO uint32_t REMA; /* 0x010 CRC_REMA CRC Remainder Register */ + __IO uint32_t CON; /* 0x014 CRC_CTRL CRC Control Register */ + __I uint32_t DOUT; /* 0x018 CRC_DOUT CRC Output Data Register */ + __I uint32_t DOUT_XOR; /* 0x01C CRC_DOUT_XOR CRC Output Data Register */ + __I uint32_t STAT; /* 0x020 CRC_STA CRC Status Register */ +} CRC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..73a409e5eb2fd81d6006d211030ffc1fb265a6da --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h @@ -0,0 +1,97 @@ +/** + ************************************************************************************** + * @file REG_DAC.h + * @brief DAC Head File + * + * @version V0.01 + * @data 1/14/2019 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __DAC_H__ +#define __DAC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for DAC_CON register ************************/ + +#define DAC_CON_T_SEL_POSS 9U +#define DAC_CON_T_SEL_POSE 13U +#define DAC_CON_T_SEL_MSK BITS(DAC_CON_T_SEL_POSS,DAC_CON_T_SEL_POSE) + +#define DAC_CON_TRIEN_POS 8U +#define DAC_CON_TRIEN_MSK BIT(DAC_CON_TRIEN_POS) + +#define DAC_CON_MAMP_POSS 3U +#define DAC_CON_MAMP_POSE 6U +#define DAC_CON_MAMP_MSK BITS(DAC_CON_MAMP_POSS,DAC_CON_MAMP_POSE) + +#define DAC_CON_WAVE_POSS 1U +#define DAC_CON_WAVE_POSE 2U +#define DAC_CON_WAVE_MSK BITS(DAC_CON_WAVE_POSS,DAC_CON_WAVE_POSE) + +#define DAC_CON_INVREN_POS 0U +#define DAC_CON_INVREN_MSK BIT(DAC_CON_INVREN_POS) + +/****************** Bit definition for DAC_DIV register ************************/ + +#define DAC_DIV_DIV_VALUE_POSS 0U +#define DAC_DIV_DIV_VALUE_POSE 15U +#define DAC_DIV_DIV_VALUE_MSK BITS(DAC_DIV_DIV_VALUE_POSS,DAC_DIV_DIV_VALUE_POSE) + +/****************** Bit definition for DAC_STAT register ************************/ + +#define DAC_STAT_TX_FULL_POS 1U +#define DAC_STAT_TX_FULL_MSK BIT(DAC_STAT_TX_FULL_POS) + +#define DAC_STAT_BUSY_POS 0U +#define DAC_STAT_BUSY_MSK BIT(DAC_STAT_BUSY_POS) + +/****************** Bit definition for DAC_EN register ************************/ + +#define DAC_EN_DAC_EN_POS 0U +#define DAC_EN_DAC_EN_MSK BIT(DAC_EN_DAC_EN_POS) + +/****************** Bit definition for DAC_DMAC register ************************/ + +#define DAC_DMAC_TXDMAEN_POS 0U +#define DAC_DMAC_TXDMAEN_MSK BIT(DAC_DMAC_TXDMAEN_POS) + +/****************** Bit definition for DAC_TRIG register ************************/ + +#define DAC_TRIG_S_TRIG_POS 0U +#define DAC_TRIG_S_TRIG_MSK BIT(DAC_TRIG_S_TRIG_POS) + +/****************** Bit definition for DAC_DATA register ************************/ + +#define DAC_DATA_TXDATA_POSS 0U +#define DAC_DATA_TXDATA_POSE 11U +#define DAC_DATA_TXDATA_MSK BITS(DAC_DATA_TXDATA_POSS,DAC_DATA_TXDATA_POSE) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t DIV; + __I uint32_t STAT; + __IO uint32_t EN; + __IO uint32_t DMAC; + __O uint32_t TRIG; + __IO uint32_t DATA; +} DAC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..bead8afcdb5e0180745897fda692a1b6b35ffae3 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h @@ -0,0 +1,825 @@ +/** + ************************************************************************************** + * @file REG_DMA.h + * @brief DMA Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_CH5TABIE_POS 11U +#define DMA_IER_CH5TABIE_MSK BIT(DMA_IER_CH5TABIE_POS) + +#define DMA_IER_CH5BTDIE_POS 10U +#define DMA_IER_CH5BTDIE_MSK BIT(DMA_IER_CH5BTDIE_POS) + +#define DMA_IER_CH4TABIE_POS 9U +#define DMA_IER_CH4TABIE_MSK BIT(DMA_IER_CH4TABIE_POS) + +#define DMA_IER_CH4BTDIE_POS 8U +#define DMA_IER_CH4BTDIE_MSK BIT(DMA_IER_CH4BTDIE_POS) + +#define DMA_IER_CH3TABIE_POS 7U +#define DMA_IER_CH3TABIE_MSK BIT(DMA_IER_CH3TABIE_POS) + +#define DMA_IER_CH3BTDIE_POS 6U +#define DMA_IER_CH3BTDIE_MSK BIT(DMA_IER_CH3BTDIE_POS) + +#define DMA_IER_CH2TABIE_POS 5U +#define DMA_IER_CH2TABIE_MSK BIT(DMA_IER_CH2TABIE_POS) + +#define DMA_IER_CH2BTDIE_POS 4U +#define DMA_IER_CH2BTDIE_MSK BIT(DMA_IER_CH2BTDIE_POS) + +#define DMA_IER_CH1TABIE_POS 3U +#define DMA_IER_CH1TABIE_MSK BIT(DMA_IER_CH1TABIE_POS) + +#define DMA_IER_CH1BTDIE_POS 2U +#define DMA_IER_CH1BTDIE_MSK BIT(DMA_IER_CH1BTDIE_POS) + +#define DMA_IER_CH0TABIE_POS 1U +#define DMA_IER_CH0TABIE_MSK BIT(DMA_IER_CH0TABIE_POS) + +#define DMA_IER_CH0BTDIE_POS 0U +#define DMA_IER_CH0BTDIE_MSK BIT(DMA_IER_CH0BTDIE_POS) + +/****************** Bit definition for DMA_IDR register ************************/ + +#define DMA_IDR_CH5TABID_POS 11U +#define DMA_IDR_CH5TABID_MSK BIT(DMA_IDR_CH5TABID_POS) + +#define DMA_IDR_CH5BTDID_POS 10U +#define DMA_IDR_CH5BTDID_MSK BIT(DMA_IDR_CH5BTDID_POS) + +#define DMA_IDR_CH4TABID_POS 9U +#define DMA_IDR_CH4TABID_MSK BIT(DMA_IDR_CH4TABID_POS) + +#define DMA_IDR_CH4BTDID_POS 8U +#define DMA_IDR_CH4BTDID_MSK BIT(DMA_IDR_CH4BTDID_POS) + +#define DMA_IDR_CH3TABID_POS 7U +#define DMA_IDR_CH3TABID_MSK BIT(DMA_IDR_CH3TABID_POS) + +#define DMA_IDR_CH3BTDID_POS 6U +#define DMA_IDR_CH3BTDID_MSK BIT(DMA_IDR_CH3BTDID_POS) + +#define DMA_IDR_CH2TABID_POS 5U +#define DMA_IDR_CH2TABID_MSK BIT(DMA_IDR_CH2TABID_POS) + +#define DMA_IDR_CH2BTDID_POS 4U +#define DMA_IDR_CH2BTDID_MSK BIT(DMA_IDR_CH2BTDID_POS) + +#define DMA_IDR_CH1TABID_POS 3U +#define DMA_IDR_CH1TABID_MSK BIT(DMA_IDR_CH1TABID_POS) + +#define DMA_IDR_CH1BTDID_POS 2U +#define DMA_IDR_CH1BTDID_MSK BIT(DMA_IDR_CH1BTDID_POS) + +#define DMA_IDR_CH0TABID_POS 1U +#define DMA_IDR_CH0TABID_MSK BIT(DMA_IDR_CH0TABID_POS) + +#define DMA_IDR_CH0BTDID_POS 0U +#define DMA_IDR_CH0BTDID_MSK BIT(DMA_IDR_CH0BTDID_POS) + +/****************** Bit definition for DMA_IVS register ************************/ + +#define DMA_IVS_CH5TABIVS_POS 11U +#define DMA_IVS_CH5TABIVS_MSK BIT(DMA_IVS_CH5TABIVS_POS) + +#define DMA_IVS_CH5BTDIVS_POS 10U +#define DMA_IVS_CH5BTDIVS_MSK BIT(DMA_IVS_CH5BTDIVS_POS) + +#define DMA_IVS_CH4TABIVS_POS 9U +#define DMA_IVS_CH4TABIVS_MSK BIT(DMA_IVS_CH4TABIVS_POS) + +#define DMA_IVS_CH4BTDIVS_POS 8U +#define DMA_IVS_CH4BTDIVS_MSK BIT(DMA_IVS_CH4BTDIVS_POS) + +#define DMA_IVS_CH3TABIVS_POS 7U +#define DMA_IVS_CH3TABIVS_MSK BIT(DMA_IVS_CH3TABIVS_POS) + +#define DMA_IVS_CH3BTDIVS_POS 6U +#define DMA_IVS_CH3BTDIVS_MSK BIT(DMA_IVS_CH3BTDIVS_POS) + +#define DMA_IVS_CH2TABIVS_POS 5U +#define DMA_IVS_CH2TABIVS_MSK BIT(DMA_IVS_CH2TABIVS_POS) + +#define DMA_IVS_CH2BTDIVS_POS 4U +#define DMA_IVS_CH2BTDIVS_MSK BIT(DMA_IVS_CH2BTDIVS_POS) + +#define DMA_IVS_CH1TABIVS_POS 3U +#define DMA_IVS_CH1TABIVS_MSK BIT(DMA_IVS_CH1TABIVS_POS) + +#define DMA_IVS_CH1BTDIVS_POS 2U +#define DMA_IVS_CH1BTDIVS_MSK BIT(DMA_IVS_CH1BTDIVS_POS) + +#define DMA_IVS_CH0TABIVS_POS 1U +#define DMA_IVS_CH0TABIVS_MSK BIT(DMA_IVS_CH0TABIVS_POS) + +#define DMA_IVS_CH0BTDIVS_POS 0U +#define DMA_IVS_CH0BTDIVS_MSK BIT(DMA_IVS_CH0BTDIVS_POS) + +/****************** Bit definition for DMA_RIF register ************************/ + +#define DMA_RIF_CH5TABRIF_POS 11U +#define DMA_RIF_CH5TABRIF_MSK BIT(DMA_RIF_CH5TABRIF_POS) + +#define DMA_RIF_CH5BTDRIF_POS 10U +#define DMA_RIF_CH5BTDRIF_MSK BIT(DMA_RIF_CH5BTDRIF_POS) + +#define DMA_RIF_CH4TABRIF_POS 9U +#define DMA_RIF_CH4TABRIF_MSK BIT(DMA_RIF_CH4TABRIF_POS) + +#define DMA_RIF_CH4BTDRIF_POS 8U +#define DMA_RIF_CH4BTDRIF_MSK BIT(DMA_RIF_CH4BTDRIF_POS) + +#define DMA_RIF_CH3TABRIF_POS 7U +#define DMA_RIF_CH3TABRIF_MSK BIT(DMA_RIF_CH3TABRIF_POS) + +#define DMA_RIF_CH3BTDRIF_POS 6U +#define DMA_RIF_CH3BTDRIF_MSK BIT(DMA_RIF_CH3BTDRIF_POS) + +#define DMA_RIF_CH2TABRIF_POS 5U +#define DMA_RIF_CH2TABRIF_MSK BIT(DMA_RIF_CH2TABRIF_POS) + +#define DMA_RIF_CH2BTDRIF_POS 4U +#define DMA_RIF_CH2BTDRIF_MSK BIT(DMA_RIF_CH2BTDRIF_POS) + +#define DMA_RIF_CH1TABRIF_POS 3U +#define DMA_RIF_CH1TABRIF_MSK BIT(DMA_RIF_CH1TABRIF_POS) + +#define DMA_RIF_CH1BTDRIF_POS 2U +#define DMA_RIF_CH1BTDRIF_MSK BIT(DMA_RIF_CH1BTDRIF_POS) + +#define DMA_RIF_CH0TABRIF_POS 1U +#define DMA_RIF_CH0TABRIF_MSK BIT(DMA_RIF_CH0TABRIF_POS) + +#define DMA_RIF_CH0BTDRIF_POS 0U +#define DMA_RIF_CH0BTDRIF_MSK BIT(DMA_RIF_CH0BTDRIF_POS) + +/****************** Bit definition for DMA_IFM register ************************/ + +#define DMA_IFM_CH5TABIFM_POS 11U +#define DMA_IFM_CH5TABIFM_MSK BIT(DMA_IFM_CH5TABIFM_POS) + +#define DMA_IFM_CH5BTDIFM_POS 10U +#define DMA_IFM_CH5BTDIFM_MSK BIT(DMA_IFM_CH5BTDIFM_POS) + +#define DMA_IFM_CH4TABIFM_POS 9U +#define DMA_IFM_CH4TABIFM_MSK BIT(DMA_IFM_CH4TABIFM_POS) + +#define DMA_IFM_CH4BTDIFM_POS 8U +#define DMA_IFM_CH4BTDIFM_MSK BIT(DMA_IFM_CH4BTDIFM_POS) + +#define DMA_IFM_CH3TABIFM_POS 7U +#define DMA_IFM_CH3TABIFM_MSK BIT(DMA_IFM_CH3TABIFM_POS) + +#define DMA_IFM_CH3BTDIFM_POS 6U +#define DMA_IFM_CH3BTDIFM_MSK BIT(DMA_IFM_CH3BTDIFM_POS) + +#define DMA_IFM_CH2TABIFM_POS 5U +#define DMA_IFM_CH2TABIFM_MSK BIT(DMA_IFM_CH2TABIFM_POS) + +#define DMA_IFM_CH2BTDIFM_POS 4U +#define DMA_IFM_CH2BTDIFM_MSK BIT(DMA_IFM_CH2BTDIFM_POS) + +#define DMA_IFM_CH1TABIFM_POS 3U +#define DMA_IFM_CH1TABIFM_MSK BIT(DMA_IFM_CH1TABIFM_POS) + +#define DMA_IFM_CH1BTDIFM_POS 2U +#define DMA_IFM_CH1BTDIFM_MSK BIT(DMA_IFM_CH1BTDIFM_POS) + +#define DMA_IFM_CH0TABIFM_POS 1U +#define DMA_IFM_CH0TABIFM_MSK BIT(DMA_IFM_CH0TABIFM_POS) + +#define DMA_IFM_CH0BTDIFM_POS 0U +#define DMA_IFM_CH0BTDIFM_MSK BIT(DMA_IFM_CH0BTDIFM_POS) + +/****************** Bit definition for DMA_ICR register ************************/ + +#define DMA_ICR_CH5TABICR_POS 11U +#define DMA_ICR_CH5TABICR_MSK BIT(DMA_ICR_CH5TABICR_POS) + +#define DMA_ICR_CH5BTDICR_POS 10U +#define DMA_ICR_CH5BTDICR_MSK BIT(DMA_ICR_CH5BTDICR_POS) + +#define DMA_ICR_CH4TABICR_POS 9U +#define DMA_ICR_CH4TABICR_MSK BIT(DMA_ICR_CH4TABICR_POS) + +#define DMA_ICR_CH4BTDICR_POS 8U +#define DMA_ICR_CH4BTDICR_MSK BIT(DMA_ICR_CH4BTDICR_POS) + +#define DMA_ICR_CH3TABICR_POS 7U +#define DMA_ICR_CH3TABICR_MSK BIT(DMA_ICR_CH3TABICR_POS) + +#define DMA_ICR_CH3BTDICR_POS 6U +#define DMA_ICR_CH3BTDICR_MSK BIT(DMA_ICR_CH3BTDICR_POS) + +#define DMA_ICR_CH2TABICR_POS 5U +#define DMA_ICR_CH2TABICR_MSK BIT(DMA_ICR_CH2TABICR_POS) + +#define DMA_ICR_CH2BTDICR_POS 4U +#define DMA_ICR_CH2BTDICR_MSK BIT(DMA_ICR_CH2BTDICR_POS) + +#define DMA_ICR_CH1TABICR_POS 3U +#define DMA_ICR_CH1TABICR_MSK BIT(DMA_ICR_CH1TABICR_POS) + +#define DMA_ICR_CH1BTDICR_POS 2U +#define DMA_ICR_CH1BTDICR_MSK BIT(DMA_ICR_CH1BTDICR_POS) + +#define DMA_ICR_CH0TABICR_POS 1U +#define DMA_ICR_CH0TABICR_MSK BIT(DMA_ICR_CH0TABICR_POS) + +#define DMA_ICR_CH0BTDICR_POS 0U +#define DMA_ICR_CH0BTDICR_MSK BIT(DMA_ICR_CH0BTDICR_POS) + +/****************** Bit definition for DMA_EMSG register ************************/ + +#define DMA_EMSG_CH5PFSER_POS 23U +#define DMA_EMSG_CH5PFSER_MSK BIT(DMA_EMSG_CH5PFSER_POS) + +#define DMA_EMSG_CH5PFOV_POS 22U +#define DMA_EMSG_CH5PFOV_MSK BIT(DMA_EMSG_CH5PFOV_POS) + +#define DMA_EMSG_CH5SETBUER_POS 21U +#define DMA_EMSG_CH5SETBUER_MSK BIT(DMA_EMSG_CH5SETBUER_POS) + +#define DMA_EMSG_CH5SETBCER_POS 20U +#define DMA_EMSG_CH5SETBCER_MSK BIT(DMA_EMSG_CH5SETBCER_POS) + +#define DMA_EMSG_CH4PFSER_POS 19U +#define DMA_EMSG_CH4PFSER_MSK BIT(DMA_EMSG_CH4PFSER_POS) + +#define DMA_EMSG_CH4PFOV_POS 18U +#define DMA_EMSG_CH4PFOV_MSK BIT(DMA_EMSG_CH4PFOV_POS) + +#define DMA_EMSG_CH4SETBUER_POS 17U +#define DMA_EMSG_CH4SETBUER_MSK BIT(DMA_EMSG_CH4SETBUER_POS) + +#define DMA_EMSG_CH4SETBCER_POS 16U +#define DMA_EMSG_CH4SETBCER_MSK BIT(DMA_EMSG_CH4SETBCER_POS) + +#define DMA_EMSG_CH3PFSER_POS 15U +#define DMA_EMSG_CH3PFSER_MSK BIT(DMA_EMSG_CH3PFSER_POS) + +#define DMA_EMSG_CH3PFOV_POS 14U +#define DMA_EMSG_CH3PFOV_MSK BIT(DMA_EMSG_CH3PFOV_POS) + +#define DMA_EMSG_CH3SETBUER_POS 13U +#define DMA_EMSG_CH3SETBUER_MSK BIT(DMA_EMSG_CH3SETBUER_POS) + +#define DMA_EMSG_CH3SETBCER_POS 12U +#define DMA_EMSG_CH3SETBCER_MSK BIT(DMA_EMSG_CH3SETBCER_POS) + +#define DMA_EMSG_CH2PFSER_POS 11U +#define DMA_EMSG_CH2PFSER_MSK BIT(DMA_EMSG_CH2PFSER_POS) + +#define DMA_EMSG_CH2PFOV_POS 10U +#define DMA_EMSG_CH2PFOV_MSK BIT(DMA_EMSG_CH2PFOV_POS) + +#define DMA_EMSG_CH2SETBUER_POS 9U +#define DMA_EMSG_CH2SETBUER_MSK BIT(DMA_EMSG_CH2SETBUER_POS) + +#define DMA_EMSG_CH2SETBCER_POS 8U +#define DMA_EMSG_CH2SETBCER_MSK BIT(DMA_EMSG_CH2SETBCER_POS) + +#define DMA_EMSG_CH1PFSER_POS 7U +#define DMA_EMSG_CH1PFSER_MSK BIT(DMA_EMSG_CH1PFSER_POS) + +#define DMA_EMSG_CH1PFOV_POS 6U +#define DMA_EMSG_CH1PFOV_MSK BIT(DMA_EMSG_CH1PFOV_POS) + +#define DMA_EMSG_CH1SETBUER_POS 5U +#define DMA_EMSG_CH1SETBUER_MSK BIT(DMA_EMSG_CH1SETBUER_POS) + +#define DMA_EMSG_CH1SETBCER_POS 4U +#define DMA_EMSG_CH1SETBCER_MSK BIT(DMA_EMSG_CH1SETBCER_POS) + +#define DMA_EMSG_CH0PFSER_POS 3U +#define DMA_EMSG_CH0PFSER_MSK BIT(DMA_EMSG_CH0PFSER_POS) + +#define DMA_EMSG_CH0PFOV_POS 2U +#define DMA_EMSG_CH0PFOV_MSK BIT(DMA_EMSG_CH0PFOV_POS) + +#define DMA_EMSG_CH0SETBUER_POS 1U +#define DMA_EMSG_CH0SETBUER_MSK BIT(DMA_EMSG_CH0SETBUER_POS) + +#define DMA_EMSG_CH0SETBCER_POS 0U +#define DMA_EMSG_CH0SETBCER_MSK BIT(DMA_EMSG_CH0SETBCER_POS) + +/****************** Bit definition for DMA_CSR0 register ************************/ + +#define DMA_CSR0_DINCOS_POS 30U +#define DMA_CSR0_DINCOS_MSK BIT(DMA_CSR0_DINCOS_POS) + +#define DMA_CSR0_DBUSEL_POSS 27U +#define DMA_CSR0_DBUSEL_POSE 29U +#define DMA_CSR0_DBUSEL_MSK BITS(DMA_CSR0_DBUSEL_POSS,DMA_CSR0_DBUSEL_POSE) + +#define DMA_CSR0_DDWSEL_POSS 25U +#define DMA_CSR0_DDWSEL_POSE 26U +#define DMA_CSR0_DDWSEL_MSK BITS(DMA_CSR0_DDWSEL_POSS,DMA_CSR0_DDWSEL_POSE) + +#define DMA_CSR0_DINC_POS 24U +#define DMA_CSR0_DINC_MSK BIT(DMA_CSR0_DINC_POS) + +#define DMA_CSR0_SINCOS_POS 22U +#define DMA_CSR0_SINCOS_MSK BIT(DMA_CSR0_SINCOS_POS) + +#define DMA_CSR0_SBUSEL_POSS 19U +#define DMA_CSR0_SBUSEL_POSE 21U +#define DMA_CSR0_SBUSEL_MSK BITS(DMA_CSR0_SBUSEL_POSS,DMA_CSR0_SBUSEL_POSE) + +#define DMA_CSR0_SDWSEL_POSS 17U +#define DMA_CSR0_SDWSEL_POSE 18U +#define DMA_CSR0_SDWSEL_MSK BITS(DMA_CSR0_SDWSEL_POSS,DMA_CSR0_SDWSEL_POSE) + +#define DMA_CSR0_SINC_POS 16U +#define DMA_CSR0_SINC_MSK BIT(DMA_CSR0_SINC_POS) + +#define DMA_CSR0_PHSS_POSS 9U +#define DMA_CSR0_PHSS_POSE 15U +#define DMA_CSR0_PHSS_MSK BITS(DMA_CSR0_PHSS_POSS,DMA_CSR0_PHSS_POSE) + +#define DMA_CSR0_CHPRI_POSS 6U +#define DMA_CSR0_CHPRI_POSE 8U +#define DMA_CSR0_CHPRI_MSK BITS(DMA_CSR0_CHPRI_POSS,DMA_CSR0_CHPRI_POSE) + +#define DMA_CSR0_MODESEL_POSS 4U +#define DMA_CSR0_MODESEL_POSE 5U +#define DMA_CSR0_MODESEL_MSK BITS(DMA_CSR0_MODESEL_POSS,DMA_CSR0_MODESEL_POSE) + +#define DMA_CSR0_DIRMDEN_POS 3U +#define DMA_CSR0_DIRMDEN_MSK BIT(DMA_CSR0_DIRMDEN_POS) + +#define DMA_CSR0_PFCTRL_POS 2U +#define DMA_CSR0_PFCTRL_MSK BIT(DMA_CSR0_PFCTRL_POS) + +#define DMA_CSR0_CIRC_POS 1U +#define DMA_CSR0_CIRC_MSK BIT(DMA_CSR0_CIRC_POS) + +#define DMA_CSR0_CHEN_POS 0U +#define DMA_CSR0_CHEN_MSK BIT(DMA_CSR0_CHEN_POS) + +/****************** Bit definition for DMA_SAR0 register ************************/ + +#define DMA_SAR0_SAR_POSS 0U +#define DMA_SAR0_SAR_POSE 31U +#define DMA_SAR0_SAR_MSK BITS(DMA_SAR0_SAR_POSS,DMA_SAR0_SAR_POSE) + +/****************** Bit definition for DMA_DAR0 register ************************/ + +#define DMA_DAR0_DAR_POSS 0U +#define DMA_DAR0_DAR_POSE 31U +#define DMA_DAR0_DAR_MSK BITS(DMA_DAR0_DAR_POSS,DMA_DAR0_DAR_POSE) + +/****************** Bit definition for DMA_BCR0 register ************************/ + +#define DMA_BCR0_CBCR_POSS 16U +#define DMA_BCR0_CBCR_POSE 31U +#define DMA_BCR0_CBCR_MSK BITS(DMA_BCR0_CBCR_POSS,DMA_BCR0_CBCR_POSE) + +#define DMA_BCR0_BCR_POSS 0U +#define DMA_BCR0_BCR_POSE 15U +#define DMA_BCR0_BCR_MSK BITS(DMA_BCR0_BCR_POSS,DMA_BCR0_BCR_POSE) + +/****************** Bit definition for DMA_CSR1 register ************************/ + +#define DMA_CSR1_DINCOS_POS 30U +#define DMA_CSR1_DINCOS_MSK BIT(DMA_CSR1_DINCOS_POS) + +#define DMA_CSR1_DBUSEL_POSS 27U +#define DMA_CSR1_DBUSEL_POSE 29U +#define DMA_CSR1_DBUSEL_MSK BITS(DMA_CSR1_DBUSEL_POSS,DMA_CSR1_DBUSEL_POSE) + +#define DMA_CSR1_DDWSEL_POSS 25U +#define DMA_CSR1_DDWSEL_POSE 26U +#define DMA_CSR1_DDWSEL_MSK BITS(DMA_CSR1_DDWSEL_POSS,DMA_CSR1_DDWSEL_POSE) + +#define DMA_CSR1_DINC_POS 24U +#define DMA_CSR1_DINC_MSK BIT(DMA_CSR1_DINC_POS) + +#define DMA_CSR1_SINCOS_POS 22U +#define DMA_CSR1_SINCOS_MSK BIT(DMA_CSR1_SINCOS_POS) + +#define DMA_CSR1_SBUSEL_POSS 19U +#define DMA_CSR1_SBUSEL_POSE 21U +#define DMA_CSR1_SBUSEL_MSK BITS(DMA_CSR1_SBUSEL_POSS,DMA_CSR1_SBUSEL_POSE) + +#define DMA_CSR1_SDWSEL_POSS 17U +#define DMA_CSR1_SDWSEL_POSE 18U +#define DMA_CSR1_SDWSEL_MSK BITS(DMA_CSR1_SDWSEL_POSS,DMA_CSR1_SDWSEL_POSE) + +#define DMA_CSR1_SINC_POS 16U +#define DMA_CSR1_SINC_MSK BIT(DMA_CSR1_SINC_POS) + +#define DMA_CSR1_PHSS_POSS 9U +#define DMA_CSR1_PHSS_POSE 15U +#define DMA_CSR1_PHSS_MSK BITS(DMA_CSR1_PHSS_POSS,DMA_CSR1_PHSS_POSE) + +#define DMA_CSR1_CHPRI_POSS 6U +#define DMA_CSR1_CHPRI_POSE 8U +#define DMA_CSR1_CHPRI_MSK BITS(DMA_CSR1_CHPRI_POSS,DMA_CSR1_CHPRI_POSE) + +#define DMA_CSR1_MODESEL_POSS 4U +#define DMA_CSR1_MODESEL_POSE 5U +#define DMA_CSR1_MODESEL_MSK BITS(DMA_CSR1_MODESEL_POSS,DMA_CSR1_MODESEL_POSE) + +#define DMA_CSR1_DIRMDEN_POS 3U +#define DMA_CSR1_DIRMDEN_MSK BIT(DMA_CSR1_DIRMDEN_POS) + +#define DMA_CSR1_PFCTRL_POS 2U +#define DMA_CSR1_PFCTRL_MSK BIT(DMA_CSR1_PFCTRL_POS) + +#define DMA_CSR1_CIRC_POS 1U +#define DMA_CSR1_CIRC_MSK BIT(DMA_CSR1_CIRC_POS) + +#define DMA_CSR1_CHEN_POS 0U +#define DMA_CSR1_CHEN_MSK BIT(DMA_CSR1_CHEN_POS) + +/****************** Bit definition for DMA_SAR1 register ************************/ + +#define DMA_SAR1_SAR_POSS 0U +#define DMA_SAR1_SAR_POSE 31U +#define DMA_SAR1_SAR_MSK BITS(DMA_SAR1_SAR_POSS,DMA_SAR1_SAR_POSE) + +/****************** Bit definition for DMA_DAR1 register ************************/ + +#define DMA_DAR1_DAR_POSS 0U +#define DMA_DAR1_DAR_POSE 31U +#define DMA_DAR1_DAR_MSK BITS(DMA_DAR1_DAR_POSS,DMA_DAR1_DAR_POSE) + +/****************** Bit definition for DMA_BCR1 register ************************/ + +#define DMA_BCR1_CBCR_POSS 16U +#define DMA_BCR1_CBCR_POSE 31U +#define DMA_BCR1_CBCR_MSK BITS(DMA_BCR1_CBCR_POSS,DMA_BCR1_CBCR_POSE) + +#define DMA_BCR1_BCR_POSS 0U +#define DMA_BCR1_BCR_POSE 15U +#define DMA_BCR1_BCR_MSK BITS(DMA_BCR1_BCR_POSS,DMA_BCR1_BCR_POSE) + +/****************** Bit definition for DMA_CSR2 register ************************/ + +#define DMA_CSR2_DINCOS_POS 30U +#define DMA_CSR2_DINCOS_MSK BIT(DMA_CSR2_DINCOS_POS) + +#define DMA_CSR2_DBUSEL_POSS 27U +#define DMA_CSR2_DBUSEL_POSE 29U +#define DMA_CSR2_DBUSEL_MSK BITS(DMA_CSR2_DBUSEL_POSS,DMA_CSR2_DBUSEL_POSE) + +#define DMA_CSR2_DDWSEL_POSS 25U +#define DMA_CSR2_DDWSEL_POSE 26U +#define DMA_CSR2_DDWSEL_MSK BITS(DMA_CSR2_DDWSEL_POSS,DMA_CSR2_DDWSEL_POSE) + +#define DMA_CSR2_DINC_POS 24U +#define DMA_CSR2_DINC_MSK BIT(DMA_CSR2_DINC_POS) + +#define DMA_CSR2_SINCOS_POS 22U +#define DMA_CSR2_SINCOS_MSK BIT(DMA_CSR2_SINCOS_POS) + +#define DMA_CSR2_SBUSEL_POSS 19U +#define DMA_CSR2_SBUSEL_POSE 21U +#define DMA_CSR2_SBUSEL_MSK BITS(DMA_CSR2_SBUSEL_POSS,DMA_CSR2_SBUSEL_POSE) + +#define DMA_CSR2_SDWSEL_POSS 17U +#define DMA_CSR2_SDWSEL_POSE 18U +#define DMA_CSR2_SDWSEL_MSK BITS(DMA_CSR2_SDWSEL_POSS,DMA_CSR2_SDWSEL_POSE) + +#define DMA_CSR2_SINC_POS 16U +#define DMA_CSR2_SINC_MSK BIT(DMA_CSR2_SINC_POS) + +#define DMA_CSR2_PHSS_POSS 9U +#define DMA_CSR2_PHSS_POSE 15U +#define DMA_CSR2_PHSS_MSK BITS(DMA_CSR2_PHSS_POSS,DMA_CSR2_PHSS_POSE) + +#define DMA_CSR2_CHPRI_POSS 6U +#define DMA_CSR2_CHPRI_POSE 8U +#define DMA_CSR2_CHPRI_MSK BITS(DMA_CSR2_CHPRI_POSS,DMA_CSR2_CHPRI_POSE) + +#define DMA_CSR2_MODESEL_POSS 4U +#define DMA_CSR2_MODESEL_POSE 5U +#define DMA_CSR2_MODESEL_MSK BITS(DMA_CSR2_MODESEL_POSS,DMA_CSR2_MODESEL_POSE) + +#define DMA_CSR2_DIRMDEN_POS 3U +#define DMA_CSR2_DIRMDEN_MSK BIT(DMA_CSR2_DIRMDEN_POS) + +#define DMA_CSR2_PFCTRL_POS 2U +#define DMA_CSR2_PFCTRL_MSK BIT(DMA_CSR2_PFCTRL_POS) + +#define DMA_CSR2_CIRC_POS 1U +#define DMA_CSR2_CIRC_MSK BIT(DMA_CSR2_CIRC_POS) + +#define DMA_CSR2_CHEN_POS 0U +#define DMA_CSR2_CHEN_MSK BIT(DMA_CSR2_CHEN_POS) + +/****************** Bit definition for DMA_SAR2 register ************************/ + +#define DMA_SAR2_SAR_POSS 0U +#define DMA_SAR2_SAR_POSE 31U +#define DMA_SAR2_SAR_MSK BITS(DMA_SAR2_SAR_POSS,DMA_SAR2_SAR_POSE) + +/****************** Bit definition for DMA_DAR2 register ************************/ + +#define DMA_DAR2_DAR_POSS 0U +#define DMA_DAR2_DAR_POSE 31U +#define DMA_DAR2_DAR_MSK BITS(DMA_DAR2_DAR_POSS,DMA_DAR2_DAR_POSE) + +/****************** Bit definition for DMA_BCR2 register ************************/ + +#define DMA_BCR2_CBCR_POSS 16U +#define DMA_BCR2_CBCR_POSE 31U +#define DMA_BCR2_CBCR_MSK BITS(DMA_BCR2_CBCR_POSS,DMA_BCR2_CBCR_POSE) + +#define DMA_BCR2_BCR_POSS 0U +#define DMA_BCR2_BCR_POSE 15U +#define DMA_BCR2_BCR_MSK BITS(DMA_BCR2_BCR_POSS,DMA_BCR2_BCR_POSE) + +/****************** Bit definition for DMA_CSR3 register ************************/ + +#define DMA_CSR3_DINCOS_POS 30U +#define DMA_CSR3_DINCOS_MSK BIT(DMA_CSR3_DINCOS_POS) + +#define DMA_CSR3_DBUSEL_POSS 27U +#define DMA_CSR3_DBUSEL_POSE 29U +#define DMA_CSR3_DBUSEL_MSK BITS(DMA_CSR3_DBUSEL_POSS,DMA_CSR3_DBUSEL_POSE) + +#define DMA_CSR3_DDWSEL_POSS 25U +#define DMA_CSR3_DDWSEL_POSE 26U +#define DMA_CSR3_DDWSEL_MSK BITS(DMA_CSR3_DDWSEL_POSS,DMA_CSR3_DDWSEL_POSE) + +#define DMA_CSR3_DINC_POS 24U +#define DMA_CSR3_DINC_MSK BIT(DMA_CSR3_DINC_POS) + +#define DMA_CSR3_SINCOS_POS 22U +#define DMA_CSR3_SINCOS_MSK BIT(DMA_CSR3_SINCOS_POS) + +#define DMA_CSR3_SBUSEL_POSS 19U +#define DMA_CSR3_SBUSEL_POSE 21U +#define DMA_CSR3_SBUSEL_MSK BITS(DMA_CSR3_SBUSEL_POSS,DMA_CSR3_SBUSEL_POSE) + +#define DMA_CSR3_SDWSEL_POSS 17U +#define DMA_CSR3_SDWSEL_POSE 18U +#define DMA_CSR3_SDWSEL_MSK BITS(DMA_CSR3_SDWSEL_POSS,DMA_CSR3_SDWSEL_POSE) + +#define DMA_CSR3_SINC_POS 16U +#define DMA_CSR3_SINC_MSK BIT(DMA_CSR3_SINC_POS) + +#define DMA_CSR3_PHSS_POSS 9U +#define DMA_CSR3_PHSS_POSE 15U +#define DMA_CSR3_PHSS_MSK BITS(DMA_CSR3_PHSS_POSS,DMA_CSR3_PHSS_POSE) + +#define DMA_CSR3_CHPRI_POSS 6U +#define DMA_CSR3_CHPRI_POSE 8U +#define DMA_CSR3_CHPRI_MSK BITS(DMA_CSR3_CHPRI_POSS,DMA_CSR3_CHPRI_POSE) + +#define DMA_CSR3_MODESEL_POSS 4U +#define DMA_CSR3_MODESEL_POSE 5U +#define DMA_CSR3_MODESEL_MSK BITS(DMA_CSR3_MODESEL_POSS,DMA_CSR3_MODESEL_POSE) + +#define DMA_CSR3_DIRMDEN_POS 3U +#define DMA_CSR3_DIRMDEN_MSK BIT(DMA_CSR3_DIRMDEN_POS) + +#define DMA_CSR3_PFCTRL_POS 2U +#define DMA_CSR3_PFCTRL_MSK BIT(DMA_CSR3_PFCTRL_POS) + +#define DMA_CSR3_CIRC_POS 1U +#define DMA_CSR3_CIRC_MSK BIT(DMA_CSR3_CIRC_POS) + +#define DMA_CSR3_CHEN_POS 0U +#define DMA_CSR3_CHEN_MSK BIT(DMA_CSR3_CHEN_POS) + +/****************** Bit definition for DMA_SAR3 register ************************/ + +#define DMA_SAR3_SAR_POSS 0U +#define DMA_SAR3_SAR_POSE 31U +#define DMA_SAR3_SAR_MSK BITS(DMA_SAR3_SAR_POSS,DMA_SAR3_SAR_POSE) + +/****************** Bit definition for DMA_DAR3 register ************************/ + +#define DMA_DAR3_DAR_POSS 0U +#define DMA_DAR3_DAR_POSE 31U +#define DMA_DAR3_DAR_MSK BITS(DMA_DAR3_DAR_POSS,DMA_DAR3_DAR_POSE) + +/****************** Bit definition for DMA_BCR3 register ************************/ + +#define DMA_BCR3_CBCR_POSS 16U +#define DMA_BCR3_CBCR_POSE 31U +#define DMA_BCR3_CBCR_MSK BITS(DMA_BCR3_CBCR_POSS,DMA_BCR3_CBCR_POSE) + +#define DMA_BCR3_BCR_POSS 0U +#define DMA_BCR3_BCR_POSE 15U +#define DMA_BCR3_BCR_MSK BITS(DMA_BCR3_BCR_POSS,DMA_BCR3_BCR_POSE) + +/****************** Bit definition for DMA_CSR4 register ************************/ + +#define DMA_CSR4_DINCOS_POS 30U +#define DMA_CSR4_DINCOS_MSK BIT(DMA_CSR4_DINCOS_POS) + +#define DMA_CSR4_DBUSEL_POSS 27U +#define DMA_CSR4_DBUSEL_POSE 29U +#define DMA_CSR4_DBUSEL_MSK BITS(DMA_CSR4_DBUSEL_POSS,DMA_CSR4_DBUSEL_POSE) + +#define DMA_CSR4_DDWSEL_POSS 25U +#define DMA_CSR4_DDWSEL_POSE 26U +#define DMA_CSR4_DDWSEL_MSK BITS(DMA_CSR4_DDWSEL_POSS,DMA_CSR4_DDWSEL_POSE) + +#define DMA_CSR4_DINC_POS 24U +#define DMA_CSR4_DINC_MSK BIT(DMA_CSR4_DINC_POS) + +#define DMA_CSR4_SINCOS_POS 22U +#define DMA_CSR4_SINCOS_MSK BIT(DMA_CSR4_SINCOS_POS) + +#define DMA_CSR4_SBUSEL_POSS 19U +#define DMA_CSR4_SBUSEL_POSE 21U +#define DMA_CSR4_SBUSEL_MSK BITS(DMA_CSR4_SBUSEL_POSS,DMA_CSR4_SBUSEL_POSE) + +#define DMA_CSR4_SDWSEL_POSS 17U +#define DMA_CSR4_SDWSEL_POSE 18U +#define DMA_CSR4_SDWSEL_MSK BITS(DMA_CSR4_SDWSEL_POSS,DMA_CSR4_SDWSEL_POSE) + +#define DMA_CSR4_SINC_POS 16U +#define DMA_CSR4_SINC_MSK BIT(DMA_CSR4_SINC_POS) + +#define DMA_CSR4_PHSS_POSS 9U +#define DMA_CSR4_PHSS_POSE 15U +#define DMA_CSR4_PHSS_MSK BITS(DMA_CSR4_PHSS_POSS,DMA_CSR4_PHSS_POSE) + +#define DMA_CSR4_CHPRI_POSS 6U +#define DMA_CSR4_CHPRI_POSE 8U +#define DMA_CSR4_CHPRI_MSK BITS(DMA_CSR4_CHPRI_POSS,DMA_CSR4_CHPRI_POSE) + +#define DMA_CSR4_MODESEL_POSS 4U +#define DMA_CSR4_MODESEL_POSE 5U +#define DMA_CSR4_MODESEL_MSK BITS(DMA_CSR4_MODESEL_POSS,DMA_CSR4_MODESEL_POSE) + +#define DMA_CSR4_DIRMDEN_POS 3U +#define DMA_CSR4_DIRMDEN_MSK BIT(DMA_CSR4_DIRMDEN_POS) + +#define DMA_CSR4_PFCTRL_POS 2U +#define DMA_CSR4_PFCTRL_MSK BIT(DMA_CSR4_PFCTRL_POS) + +#define DMA_CSR4_CIRC_POS 1U +#define DMA_CSR4_CIRC_MSK BIT(DMA_CSR4_CIRC_POS) + +#define DMA_CSR4_CHEN_POS 0U +#define DMA_CSR4_CHEN_MSK BIT(DMA_CSR4_CHEN_POS) + +/****************** Bit definition for DMA_SAR4 register ************************/ + +#define DMA_SAR4_SAR_POSS 0U +#define DMA_SAR4_SAR_POSE 31U +#define DMA_SAR4_SAR_MSK BITS(DMA_SAR4_SAR_POSS,DMA_SAR4_SAR_POSE) + +/****************** Bit definition for DMA_DAR4 register ************************/ + +#define DMA_DAR4_DAR_POSS 0U +#define DMA_DAR4_DAR_POSE 31U +#define DMA_DAR4_DAR_MSK BITS(DMA_DAR4_DAR_POSS,DMA_DAR4_DAR_POSE) + +/****************** Bit definition for DMA_BCR4 register ************************/ + +#define DMA_BCR4_CBCR_POSS 16U +#define DMA_BCR4_CBCR_POSE 31U +#define DMA_BCR4_CBCR_MSK BITS(DMA_BCR4_CBCR_POSS,DMA_BCR4_CBCR_POSE) + +#define DMA_BCR4_BCR_POSS 0U +#define DMA_BCR4_BCR_POSE 15U +#define DMA_BCR4_BCR_MSK BITS(DMA_BCR4_BCR_POSS,DMA_BCR4_BCR_POSE) + +/****************** Bit definition for DMA_CSR5 register ************************/ + +#define DMA_CSR5_DINCOS_POS 30U +#define DMA_CSR5_DINCOS_MSK BIT(DMA_CSR5_DINCOS_POS) + +#define DMA_CSR5_DBUSEL_POSS 27U +#define DMA_CSR5_DBUSEL_POSE 29U +#define DMA_CSR5_DBUSEL_MSK BITS(DMA_CSR5_DBUSEL_POSS,DMA_CSR5_DBUSEL_POSE) + +#define DMA_CSR5_DDWSEL_POSS 25U +#define DMA_CSR5_DDWSEL_POSE 26U +#define DMA_CSR5_DDWSEL_MSK BITS(DMA_CSR5_DDWSEL_POSS,DMA_CSR5_DDWSEL_POSE) + +#define DMA_CSR5_DINC_POS 24U +#define DMA_CSR5_DINC_MSK BIT(DMA_CSR5_DINC_POS) + +#define DMA_CSR5_SINCOS_POS 22U +#define DMA_CSR5_SINCOS_MSK BIT(DMA_CSR5_SINCOS_POS) + +#define DMA_CSR5_SBUSEL_POSS 19U +#define DMA_CSR5_SBUSEL_POSE 21U +#define DMA_CSR5_SBUSEL_MSK BITS(DMA_CSR5_SBUSEL_POSS,DMA_CSR5_SBUSEL_POSE) + +#define DMA_CSR5_SDWSEL_POSS 17U +#define DMA_CSR5_SDWSEL_POSE 18U +#define DMA_CSR5_SDWSEL_MSK BITS(DMA_CSR5_SDWSEL_POSS,DMA_CSR5_SDWSEL_POSE) + +#define DMA_CSR5_SINC_POS 16U +#define DMA_CSR5_SINC_MSK BIT(DMA_CSR5_SINC_POS) + +#define DMA_CSR5_PHSS_POSS 9U +#define DMA_CSR5_PHSS_POSE 15U +#define DMA_CSR5_PHSS_MSK BITS(DMA_CSR5_PHSS_POSS,DMA_CSR5_PHSS_POSE) + +#define DMA_CSR5_CHPRI_POSS 6U +#define DMA_CSR5_CHPRI_POSE 8U +#define DMA_CSR5_CHPRI_MSK BITS(DMA_CSR5_CHPRI_POSS,DMA_CSR5_CHPRI_POSE) + +#define DMA_CSR5_MODESEL_POSS 4U +#define DMA_CSR5_MODESEL_POSE 5U +#define DMA_CSR5_MODESEL_MSK BITS(DMA_CSR5_MODESEL_POSS,DMA_CSR5_MODESEL_POSE) + +#define DMA_CSR5_DIRMDEN_POS 3U +#define DMA_CSR5_DIRMDEN_MSK BIT(DMA_CSR5_DIRMDEN_POS) + +#define DMA_CSR5_PFCTRL_POS 2U +#define DMA_CSR5_PFCTRL_MSK BIT(DMA_CSR5_PFCTRL_POS) + +#define DMA_CSR5_CIRC_POS 1U +#define DMA_CSR5_CIRC_MSK BIT(DMA_CSR5_CIRC_POS) + +#define DMA_CSR5_CHEN_POS 0U +#define DMA_CSR5_CHEN_MSK BIT(DMA_CSR5_CHEN_POS) + +/****************** Bit definition for DMA_SAR5 register ************************/ + +#define DMA_SAR5_SAR_POSS 0U +#define DMA_SAR5_SAR_POSE 31U +#define DMA_SAR5_SAR_MSK BITS(DMA_SAR5_SAR_POSS,DMA_SAR5_SAR_POSE) + +/****************** Bit definition for DMA_DAR5 register ************************/ + +#define DMA_DAR5_DAR_POSS 0U +#define DMA_DAR5_DAR_POSE 31U +#define DMA_DAR5_DAR_MSK BITS(DMA_DAR5_DAR_POSS,DMA_DAR5_DAR_POSE) + +/****************** Bit definition for DMA_BCR5 register ************************/ + +#define DMA_BCR5_CBCR_POSS 16U +#define DMA_BCR5_CBCR_POSE 31U +#define DMA_BCR5_CBCR_MSK BITS(DMA_BCR5_CBCR_POSS,DMA_BCR5_CBCR_POSE) + +#define DMA_BCR5_BCR_POSS 0U +#define DMA_BCR5_BCR_POSE 15U +#define DMA_BCR5_BCR_MSK BITS(DMA_BCR5_BCR_POSS,DMA_BCR5_BCR_POSE) + +typedef struct +{ + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __I uint32_t EMSG; + uint32_t RESERVED0 ; + __IO uint32_t CSR0; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t BCR0; + __IO uint32_t CSR1; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t BCR1; + __IO uint32_t CSR2; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t BCR2; + __IO uint32_t CSR3; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t BCR3; + __IO uint32_t CSR4; + __IO uint32_t SAR4; + __IO uint32_t DAR4; + __IO uint32_t BCR4; + __IO uint32_t CSR5; + __IO uint32_t SAR5; + __IO uint32_t DAR5; + __IO uint32_t BCR5; +} DMA_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..92a82288896dd5704158831876e5bb2329851e2c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h @@ -0,0 +1,809 @@ +/** + ************************************************************************************** + * @file REG_EXTI.h + * @brief EXTI Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __EXTI_H__ +#define __EXTI_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for EXTI_IER register ************************/ + +#define EXTI_IER_WAKEUP_POS 21U +#define EXTI_IER_WAKEUP_MSK BIT(EXTI_IER_WAKEUP_POS) + +#define EXTI_IER_PVD0_POS 20U +#define EXTI_IER_PVD0_MSK BIT(EXTI_IER_PVD0_POS) + +#define EXTI_IER_CMP2_POS 17U +#define EXTI_IER_CMP2_MSK BIT(EXTI_IER_CMP2_POS) + +#define EXTI_IER_CMP1_POS 16U +#define EXTI_IER_CMP1_MSK BIT(EXTI_IER_CMP1_POS) + +#define EXTI_IER_GPIO15_POS 15U +#define EXTI_IER_GPIO15_MSK BIT(EXTI_IER_GPIO15_POS) + +#define EXTI_IER_GPIO14_POS 14U +#define EXTI_IER_GPIO14_MSK BIT(EXTI_IER_GPIO14_POS) + +#define EXTI_IER_GPIO13_POS 13U +#define EXTI_IER_GPIO13_MSK BIT(EXTI_IER_GPIO13_POS) + +#define EXTI_IER_GPIO12_POS 12U +#define EXTI_IER_GPIO12_MSK BIT(EXTI_IER_GPIO12_POS) + +#define EXTI_IER_GPIO11_POS 11U +#define EXTI_IER_GPIO11_MSK BIT(EXTI_IER_GPIO11_POS) + +#define EXTI_IER_GPIO10_POS 10U +#define EXTI_IER_GPIO10_MSK BIT(EXTI_IER_GPIO10_POS) + +#define EXTI_IER_GPIO9_POS 9U +#define EXTI_IER_GPIO9_MSK BIT(EXTI_IER_GPIO9_POS) + +#define EXTI_IER_GPIO8_POS 8U +#define EXTI_IER_GPIO8_MSK BIT(EXTI_IER_GPIO8_POS) + +#define EXTI_IER_GPIO7_POS 7U +#define EXTI_IER_GPIO7_MSK BIT(EXTI_IER_GPIO7_POS) + +#define EXTI_IER_GPIO6_POS 6U +#define EXTI_IER_GPIO6_MSK BIT(EXTI_IER_GPIO6_POS) + +#define EXTI_IER_GPIO5_POS 5U +#define EXTI_IER_GPIO5_MSK BIT(EXTI_IER_GPIO5_POS) + +#define EXTI_IER_GPIO4_POS 4U +#define EXTI_IER_GPIO4_MSK BIT(EXTI_IER_GPIO4_POS) + +#define EXTI_IER_GPIO3_POS 3U +#define EXTI_IER_GPIO3_MSK BIT(EXTI_IER_GPIO3_POS) + +#define EXTI_IER_GPIO2_POS 2U +#define EXTI_IER_GPIO2_MSK BIT(EXTI_IER_GPIO2_POS) + +#define EXTI_IER_GPIO1_POS 1U +#define EXTI_IER_GPIO1_MSK BIT(EXTI_IER_GPIO1_POS) + +#define EXTI_IER_GPIO0_POS 0U +#define EXTI_IER_GPIO0_MSK BIT(EXTI_IER_GPIO0_POS) + +/****************** Bit definition for EXTI_IDR register ************************/ + +#define EXTI_IDR_WAKEUP_POS 21U +#define EXTI_IDR_WAKEUP_MSK BIT(EXTI_IDR_WAKEUP_POS) + +#define EXTI_IDR_PVD0_POS 20U +#define EXTI_IDR_PVD0_MSK BIT(EXTI_IDR_PVD0_POS) + +#define EXTI_IDR_CMP2_POS 17U +#define EXTI_IDR_CMP2_MSK BIT(EXTI_IDR_CMP2_POS) + +#define EXTI_IDR_CMP1_POS 16U +#define EXTI_IDR_CMP1_MSK BIT(EXTI_IDR_CMP1_POS) + +#define EXTI_IDR_GPIO15_POS 15U +#define EXTI_IDR_GPIO15_MSK BIT(EXTI_IDR_GPIO15_POS) + +#define EXTI_IDR_GPIO14_POS 14U +#define EXTI_IDR_GPIO14_MSK BIT(EXTI_IDR_GPIO14_POS) + +#define EXTI_IDR_GPIO13_POS 13U +#define EXTI_IDR_GPIO13_MSK BIT(EXTI_IDR_GPIO13_POS) + +#define EXTI_IDR_GPIO12_POS 12U +#define EXTI_IDR_GPIO12_MSK BIT(EXTI_IDR_GPIO12_POS) + +#define EXTI_IDR_GPIO11_POS 11U +#define EXTI_IDR_GPIO11_MSK BIT(EXTI_IDR_GPIO11_POS) + +#define EXTI_IDR_GPIO10_POS 10U +#define EXTI_IDR_GPIO10_MSK BIT(EXTI_IDR_GPIO10_POS) + +#define EXTI_IDR_GPIO9_POS 9U +#define EXTI_IDR_GPIO9_MSK BIT(EXTI_IDR_GPIO9_POS) + +#define EXTI_IDR_GPIO8_POS 8U +#define EXTI_IDR_GPIO8_MSK BIT(EXTI_IDR_GPIO8_POS) + +#define EXTI_IDR_GPIO7_POS 7U +#define EXTI_IDR_GPIO7_MSK BIT(EXTI_IDR_GPIO7_POS) + +#define EXTI_IDR_GPIO6_POS 6U +#define EXTI_IDR_GPIO6_MSK BIT(EXTI_IDR_GPIO6_POS) + +#define EXTI_IDR_GPIO5_POS 5U +#define EXTI_IDR_GPIO5_MSK BIT(EXTI_IDR_GPIO5_POS) + +#define EXTI_IDR_GPIO4_POS 4U +#define EXTI_IDR_GPIO4_MSK BIT(EXTI_IDR_GPIO4_POS) + +#define EXTI_IDR_GPIO3_POS 3U +#define EXTI_IDR_GPIO3_MSK BIT(EXTI_IDR_GPIO3_POS) + +#define EXTI_IDR_GPIO2_POS 2U +#define EXTI_IDR_GPIO2_MSK BIT(EXTI_IDR_GPIO2_POS) + +#define EXTI_IDR_GPIO1_POS 1U +#define EXTI_IDR_GPIO1_MSK BIT(EXTI_IDR_GPIO1_POS) + +#define EXTI_IDR_GPIO0_POS 0U +#define EXTI_IDR_GPIO0_MSK BIT(EXTI_IDR_GPIO0_POS) + +/****************** Bit definition for EXTI_IVS register ************************/ + +#define EXTI_IVS_WAKEUP_POS 21U +#define EXTI_IVS_WAKEUP_MSK BIT(EXTI_IVS_WAKEUP_POS) + +#define EXTI_IVS_PVD0_POS 20U +#define EXTI_IVS_PVD0_MSK BIT(EXTI_IVS_PVD0_POS) + +#define EXTI_IVS_CMP2_POS 17U +#define EXTI_IVS_CMP2_MSK BIT(EXTI_IVS_CMP2_POS) + +#define EXTI_IVS_CMP1_POS 16U +#define EXTI_IVS_CMP1_MSK BIT(EXTI_IVS_CMP1_POS) + +#define EXTI_IVS_GPIO15_POS 15U +#define EXTI_IVS_GPIO15_MSK BIT(EXTI_IVS_GPIO15_POS) + +#define EXTI_IVS_GPIO14_POS 14U +#define EXTI_IVS_GPIO14_MSK BIT(EXTI_IVS_GPIO14_POS) + +#define EXTI_IVS_GPIO13_POS 13U +#define EXTI_IVS_GPIO13_MSK BIT(EXTI_IVS_GPIO13_POS) + +#define EXTI_IVS_GPIO12_POS 12U +#define EXTI_IVS_GPIO12_MSK BIT(EXTI_IVS_GPIO12_POS) + +#define EXTI_IVS_GPIO11_POS 11U +#define EXTI_IVS_GPIO11_MSK BIT(EXTI_IVS_GPIO11_POS) + +#define EXTI_IVS_GPIO10_POS 10U +#define EXTI_IVS_GPIO10_MSK BIT(EXTI_IVS_GPIO10_POS) + +#define EXTI_IVS_GPIO9_POS 9U +#define EXTI_IVS_GPIO9_MSK BIT(EXTI_IVS_GPIO9_POS) + +#define EXTI_IVS_GPIO8_POS 8U +#define EXTI_IVS_GPIO8_MSK BIT(EXTI_IVS_GPIO8_POS) + +#define EXTI_IVS_GPIO7_POS 7U +#define EXTI_IVS_GPIO7_MSK BIT(EXTI_IVS_GPIO7_POS) + +#define EXTI_IVS_GPIO6_POS 6U +#define EXTI_IVS_GPIO6_MSK BIT(EXTI_IVS_GPIO6_POS) + +#define EXTI_IVS_GPIO5_POS 5U +#define EXTI_IVS_GPIO5_MSK BIT(EXTI_IVS_GPIO5_POS) + +#define EXTI_IVS_GPIO4_POS 4U +#define EXTI_IVS_GPIO4_MSK BIT(EXTI_IVS_GPIO4_POS) + +#define EXTI_IVS_GPIO3_POS 3U +#define EXTI_IVS_GPIO3_MSK BIT(EXTI_IVS_GPIO3_POS) + +#define EXTI_IVS_GPIO2_POS 2U +#define EXTI_IVS_GPIO2_MSK BIT(EXTI_IVS_GPIO2_POS) + +#define EXTI_IVS_GPIO1_POS 1U +#define EXTI_IVS_GPIO1_MSK BIT(EXTI_IVS_GPIO1_POS) + +#define EXTI_IVS_GPIO0_POS 0U +#define EXTI_IVS_GPIO0_MSK BIT(EXTI_IVS_GPIO0_POS) + +/****************** Bit definition for EXTI_RIF register ************************/ + +#define EXTI_RIF_WAKEUP_POS 21U +#define EXTI_RIF_WAKEUP_MSK BIT(EXTI_RIF_WAKEUP_POS) + +#define EXTI_RIF_PVD0_POS 20U +#define EXTI_RIF_PVD0_MSK BIT(EXTI_RIF_PVD0_POS) + +#define EXTI_RIF_CMP2_POS 17U +#define EXTI_RIF_CMP2_MSK BIT(EXTI_RIF_CMP2_POS) + +#define EXTI_RIF_CMP1_POS 16U +#define EXTI_RIF_CMP1_MSK BIT(EXTI_RIF_CMP1_POS) + +#define EXTI_RIF_GPIO15_POS 15U +#define EXTI_RIF_GPIO15_MSK BIT(EXTI_RIF_GPIO15_POS) + +#define EXTI_RIF_GPIO14_POS 14U +#define EXTI_RIF_GPIO14_MSK BIT(EXTI_RIF_GPIO14_POS) + +#define EXTI_RIF_GPIO13_POS 13U +#define EXTI_RIF_GPIO13_MSK BIT(EXTI_RIF_GPIO13_POS) + +#define EXTI_RIF_GPIO12_POS 12U +#define EXTI_RIF_GPIO12_MSK BIT(EXTI_RIF_GPIO12_POS) + +#define EXTI_RIF_GPIO11_POS 11U +#define EXTI_RIF_GPIO11_MSK BIT(EXTI_RIF_GPIO11_POS) + +#define EXTI_RIF_GPIO10_POS 10U +#define EXTI_RIF_GPIO10_MSK BIT(EXTI_RIF_GPIO10_POS) + +#define EXTI_RIF_GPIO9_POS 9U +#define EXTI_RIF_GPIO9_MSK BIT(EXTI_RIF_GPIO9_POS) + +#define EXTI_RIF_GPIO8_POS 8U +#define EXTI_RIF_GPIO8_MSK BIT(EXTI_RIF_GPIO8_POS) + +#define EXTI_RIF_GPIO7_POS 7U +#define EXTI_RIF_GPIO7_MSK BIT(EXTI_RIF_GPIO7_POS) + +#define EXTI_RIF_GPIO6_POS 6U +#define EXTI_RIF_GPIO6_MSK BIT(EXTI_RIF_GPIO6_POS) + +#define EXTI_RIF_GPIO5_POS 5U +#define EXTI_RIF_GPIO5_MSK BIT(EXTI_RIF_GPIO5_POS) + +#define EXTI_RIF_GPIO4_POS 4U +#define EXTI_RIF_GPIO4_MSK BIT(EXTI_RIF_GPIO4_POS) + +#define EXTI_RIF_GPIO3_POS 3U +#define EXTI_RIF_GPIO3_MSK BIT(EXTI_RIF_GPIO3_POS) + +#define EXTI_RIF_GPIO2_POS 2U +#define EXTI_RIF_GPIO2_MSK BIT(EXTI_RIF_GPIO2_POS) + +#define EXTI_RIF_GPIO1_POS 1U +#define EXTI_RIF_GPIO1_MSK BIT(EXTI_RIF_GPIO1_POS) + +#define EXTI_RIF_GPIO0_POS 0U +#define EXTI_RIF_GPIO0_MSK BIT(EXTI_RIF_GPIO0_POS) + +/****************** Bit definition for EXTI_IFM register ************************/ + +#define EXTI_IFM_WAKEUP_POS 21U +#define EXTI_IFM_WAKEUP_MSK BIT(EXTI_IFM_WAKEUP_POS) + +#define EXTI_IFM_PVD0_POS 20U +#define EXTI_IFM_PVD0_MSK BIT(EXTI_IFM_PVD0_POS) + +#define EXTI_IFM_CMP2_POS 17U +#define EXTI_IFM_CMP2_MSK BIT(EXTI_IFM_CMP2_POS) + +#define EXTI_IFM_CMP1_POS 16U +#define EXTI_IFM_CMP1_MSK BIT(EXTI_IFM_CMP1_POS) + +#define EXTI_IFM_GPIO15_POS 15U +#define EXTI_IFM_GPIO15_MSK BIT(EXTI_IFM_GPIO15_POS) + +#define EXTI_IFM_GPIO14_POS 14U +#define EXTI_IFM_GPIO14_MSK BIT(EXTI_IFM_GPIO14_POS) + +#define EXTI_IFM_GPIO13_POS 13U +#define EXTI_IFM_GPIO13_MSK BIT(EXTI_IFM_GPIO13_POS) + +#define EXTI_IFM_GPIO12_POS 12U +#define EXTI_IFM_GPIO12_MSK BIT(EXTI_IFM_GPIO12_POS) + +#define EXTI_IFM_GPIO11_POS 11U +#define EXTI_IFM_GPIO11_MSK BIT(EXTI_IFM_GPIO11_POS) + +#define EXTI_IFM_GPIO10_POS 10U +#define EXTI_IFM_GPIO10_MSK BIT(EXTI_IFM_GPIO10_POS) + +#define EXTI_IFM_GPIO9_POS 9U +#define EXTI_IFM_GPIO9_MSK BIT(EXTI_IFM_GPIO9_POS) + +#define EXTI_IFM_GPIO8_POS 8U +#define EXTI_IFM_GPIO8_MSK BIT(EXTI_IFM_GPIO8_POS) + +#define EXTI_IFM_GPIO7_POS 7U +#define EXTI_IFM_GPIO7_MSK BIT(EXTI_IFM_GPIO7_POS) + +#define EXTI_IFM_GPIO6_POS 6U +#define EXTI_IFM_GPIO6_MSK BIT(EXTI_IFM_GPIO6_POS) + +#define EXTI_IFM_GPIO5_POS 5U +#define EXTI_IFM_GPIO5_MSK BIT(EXTI_IFM_GPIO5_POS) + +#define EXTI_IFM_GPIO4_POS 4U +#define EXTI_IFM_GPIO4_MSK BIT(EXTI_IFM_GPIO4_POS) + +#define EXTI_IFM_GPIO3_POS 3U +#define EXTI_IFM_GPIO3_MSK BIT(EXTI_IFM_GPIO3_POS) + +#define EXTI_IFM_GPIO2_POS 2U +#define EXTI_IFM_GPIO2_MSK BIT(EXTI_IFM_GPIO2_POS) + +#define EXTI_IFM_GPIO1_POS 1U +#define EXTI_IFM_GPIO1_MSK BIT(EXTI_IFM_GPIO1_POS) + +#define EXTI_IFM_GPIO0_POS 0U +#define EXTI_IFM_GPIO0_MSK BIT(EXTI_IFM_GPIO0_POS) + +/****************** Bit definition for EXTI_ICR register ************************/ + +#define EXTI_ICR_WAKEUP_POS 21U +#define EXTI_ICR_WAKEUP_MSK BIT(EXTI_ICR_WAKEUP_POS) + +#define EXTI_ICR_PVD0_POS 20U +#define EXTI_ICR_PVD0_MSK BIT(EXTI_ICR_PVD0_POS) + +#define EXTI_ICR_CMP2_POS 17U +#define EXTI_ICR_CMP2_MSK BIT(EXTI_ICR_CMP2_POS) + +#define EXTI_ICR_CMP1_POS 16U +#define EXTI_ICR_CMP1_MSK BIT(EXTI_ICR_CMP1_POS) + +#define EXTI_ICR_GPIO15_POS 15U +#define EXTI_ICR_GPIO15_MSK BIT(EXTI_ICR_GPIO15_POS) + +#define EXTI_ICR_GPIO14_POS 14U +#define EXTI_ICR_GPIO14_MSK BIT(EXTI_ICR_GPIO14_POS) + +#define EXTI_ICR_GPIO13_POS 13U +#define EXTI_ICR_GPIO13_MSK BIT(EXTI_ICR_GPIO13_POS) + +#define EXTI_ICR_GPIO12_POS 12U +#define EXTI_ICR_GPIO12_MSK BIT(EXTI_ICR_GPIO12_POS) + +#define EXTI_ICR_GPIO11_POS 11U +#define EXTI_ICR_GPIO11_MSK BIT(EXTI_ICR_GPIO11_POS) + +#define EXTI_ICR_GPIO10_POS 10U +#define EXTI_ICR_GPIO10_MSK BIT(EXTI_ICR_GPIO10_POS) + +#define EXTI_ICR_GPIO9_POS 9U +#define EXTI_ICR_GPIO9_MSK BIT(EXTI_ICR_GPIO9_POS) + +#define EXTI_ICR_GPIO8_POS 8U +#define EXTI_ICR_GPIO8_MSK BIT(EXTI_ICR_GPIO8_POS) + +#define EXTI_ICR_GPIO7_POS 7U +#define EXTI_ICR_GPIO7_MSK BIT(EXTI_ICR_GPIO7_POS) + +#define EXTI_ICR_GPIO6_POS 6U +#define EXTI_ICR_GPIO6_MSK BIT(EXTI_ICR_GPIO6_POS) + +#define EXTI_ICR_GPIO5_POS 5U +#define EXTI_ICR_GPIO5_MSK BIT(EXTI_ICR_GPIO5_POS) + +#define EXTI_ICR_GPIO4_POS 4U +#define EXTI_ICR_GPIO4_MSK BIT(EXTI_ICR_GPIO4_POS) + +#define EXTI_ICR_GPIO3_POS 3U +#define EXTI_ICR_GPIO3_MSK BIT(EXTI_ICR_GPIO3_POS) + +#define EXTI_ICR_GPIO2_POS 2U +#define EXTI_ICR_GPIO2_MSK BIT(EXTI_ICR_GPIO2_POS) + +#define EXTI_ICR_GPIO1_POS 1U +#define EXTI_ICR_GPIO1_MSK BIT(EXTI_ICR_GPIO1_POS) + +#define EXTI_ICR_GPIO0_POS 0U +#define EXTI_ICR_GPIO0_MSK BIT(EXTI_ICR_GPIO0_POS) + +/****************** Bit definition for EXTI_RTS register ************************/ + +#define EXTI_RTS_WAKEUP_POS 21U +#define EXTI_RTS_WAKEUP_MSK BIT(EXTI_RTS_WAKEUP_POS) + +#define EXTI_RTS_PVD0_POS 20U +#define EXTI_RTS_PVD0_MSK BIT(EXTI_RTS_PVD0_POS) + +#define EXTI_RTS_CMP2_POS 17U +#define EXTI_RTS_CMP2_MSK BIT(EXTI_RTS_CMP2_POS) + +#define EXTI_RTS_CMP1_POS 16U +#define EXTI_RTS_CMP1_MSK BIT(EXTI_RTS_CMP1_POS) + +#define EXTI_RTS_GPIO15_POS 15U +#define EXTI_RTS_GPIO15_MSK BIT(EXTI_RTS_GPIO15_POS) + +#define EXTI_RTS_GPIO14_POS 14U +#define EXTI_RTS_GPIO14_MSK BIT(EXTI_RTS_GPIO14_POS) + +#define EXTI_RTS_GPIO13_POS 13U +#define EXTI_RTS_GPIO13_MSK BIT(EXTI_RTS_GPIO13_POS) + +#define EXTI_RTS_GPIO12_POS 12U +#define EXTI_RTS_GPIO12_MSK BIT(EXTI_RTS_GPIO12_POS) + +#define EXTI_RTS_GPIO11_POS 11U +#define EXTI_RTS_GPIO11_MSK BIT(EXTI_RTS_GPIO11_POS) + +#define EXTI_RTS_GPIO10_POS 10U +#define EXTI_RTS_GPIO10_MSK BIT(EXTI_RTS_GPIO10_POS) + +#define EXTI_RTS_GPIO9_POS 9U +#define EXTI_RTS_GPIO9_MSK BIT(EXTI_RTS_GPIO9_POS) + +#define EXTI_RTS_GPIO8_POS 8U +#define EXTI_RTS_GPIO8_MSK BIT(EXTI_RTS_GPIO8_POS) + +#define EXTI_RTS_GPIO7_POS 7U +#define EXTI_RTS_GPIO7_MSK BIT(EXTI_RTS_GPIO7_POS) + +#define EXTI_RTS_GPIO6_POS 6U +#define EXTI_RTS_GPIO6_MSK BIT(EXTI_RTS_GPIO6_POS) + +#define EXTI_RTS_GPIO5_POS 5U +#define EXTI_RTS_GPIO5_MSK BIT(EXTI_RTS_GPIO5_POS) + +#define EXTI_RTS_GPIO4_POS 4U +#define EXTI_RTS_GPIO4_MSK BIT(EXTI_RTS_GPIO4_POS) + +#define EXTI_RTS_GPIO3_POS 3U +#define EXTI_RTS_GPIO3_MSK BIT(EXTI_RTS_GPIO3_POS) + +#define EXTI_RTS_GPIO2_POS 2U +#define EXTI_RTS_GPIO2_MSK BIT(EXTI_RTS_GPIO2_POS) + +#define EXTI_RTS_GPIO1_POS 1U +#define EXTI_RTS_GPIO1_MSK BIT(EXTI_RTS_GPIO1_POS) + +#define EXTI_RTS_GPIO0_POS 0U +#define EXTI_RTS_GPIO0_MSK BIT(EXTI_RTS_GPIO0_POS) + +/****************** Bit definition for EXTI_FTS register ************************/ + +#define EXTI_FTS_WAKEUP_POS 21U +#define EXTI_FTS_WAKEUP_MSK BIT(EXTI_FTS_WAKEUP_POS) + +#define EXTI_FTS_PVD0_POS 20U +#define EXTI_FTS_PVD0_MSK BIT(EXTI_FTS_PVD0_POS) + +#define EXTI_FTS_CMP2_POS 17U +#define EXTI_FTS_CMP2_MSK BIT(EXTI_FTS_CMP2_POS) + +#define EXTI_FTS_CMP1_POS 16U +#define EXTI_FTS_CMP1_MSK BIT(EXTI_FTS_CMP1_POS) + +#define EXTI_FTS_GPIO15_POS 15U +#define EXTI_FTS_GPIO15_MSK BIT(EXTI_FTS_GPIO15_POS) + +#define EXTI_FTS_GPIO14_POS 14U +#define EXTI_FTS_GPIO14_MSK BIT(EXTI_FTS_GPIO14_POS) + +#define EXTI_FTS_GPIO13_POS 13U +#define EXTI_FTS_GPIO13_MSK BIT(EXTI_FTS_GPIO13_POS) + +#define EXTI_FTS_GPIO12_POS 12U +#define EXTI_FTS_GPIO12_MSK BIT(EXTI_FTS_GPIO12_POS) + +#define EXTI_FTS_GPIO11_POS 11U +#define EXTI_FTS_GPIO11_MSK BIT(EXTI_FTS_GPIO11_POS) + +#define EXTI_FTS_GPIO10_POS 10U +#define EXTI_FTS_GPIO10_MSK BIT(EXTI_FTS_GPIO10_POS) + +#define EXTI_FTS_GPIO9_POS 9U +#define EXTI_FTS_GPIO9_MSK BIT(EXTI_FTS_GPIO9_POS) + +#define EXTI_FTS_GPIO8_POS 8U +#define EXTI_FTS_GPIO8_MSK BIT(EXTI_FTS_GPIO8_POS) + +#define EXTI_FTS_GPIO7_POS 7U +#define EXTI_FTS_GPIO7_MSK BIT(EXTI_FTS_GPIO7_POS) + +#define EXTI_FTS_GPIO6_POS 6U +#define EXTI_FTS_GPIO6_MSK BIT(EXTI_FTS_GPIO6_POS) + +#define EXTI_FTS_GPIO5_POS 5U +#define EXTI_FTS_GPIO5_MSK BIT(EXTI_FTS_GPIO5_POS) + +#define EXTI_FTS_GPIO4_POS 4U +#define EXTI_FTS_GPIO4_MSK BIT(EXTI_FTS_GPIO4_POS) + +#define EXTI_FTS_GPIO3_POS 3U +#define EXTI_FTS_GPIO3_MSK BIT(EXTI_FTS_GPIO3_POS) + +#define EXTI_FTS_GPIO2_POS 2U +#define EXTI_FTS_GPIO2_MSK BIT(EXTI_FTS_GPIO2_POS) + +#define EXTI_FTS_GPIO1_POS 1U +#define EXTI_FTS_GPIO1_MSK BIT(EXTI_FTS_GPIO1_POS) + +#define EXTI_FTS_GPIO0_POS 0U +#define EXTI_FTS_GPIO0_MSK BIT(EXTI_FTS_GPIO0_POS) + +/****************** Bit definition for EXTI_SWI register ************************/ + +#define EXTI_SWI_WAKEUP_POS 21U +#define EXTI_SWI_WAKEUP_MSK BIT(EXTI_SWI_WAKEUP_POS) + +#define EXTI_SWI_PVD0_POS 20U +#define EXTI_SWI_PVD0_MSK BIT(EXTI_SWI_PVD0_POS) + +#define EXTI_SWI_CMP2_POS 17U +#define EXTI_SWI_CMP2_MSK BIT(EXTI_SWI_CMP2_POS) + +#define EXTI_SWI_CMP1_POS 16U +#define EXTI_SWI_CMP1_MSK BIT(EXTI_SWI_CMP1_POS) + +#define EXTI_SWI_GPIO15_POS 15U +#define EXTI_SWI_GPIO15_MSK BIT(EXTI_SWI_GPIO15_POS) + +#define EXTI_SWI_GPIO14_POS 14U +#define EXTI_SWI_GPIO14_MSK BIT(EXTI_SWI_GPIO14_POS) + +#define EXTI_SWI_GPIO13_POS 13U +#define EXTI_SWI_GPIO13_MSK BIT(EXTI_SWI_GPIO13_POS) + +#define EXTI_SWI_GPIO12_POS 12U +#define EXTI_SWI_GPIO12_MSK BIT(EXTI_SWI_GPIO12_POS) + +#define EXTI_SWI_GPIO11_POS 11U +#define EXTI_SWI_GPIO11_MSK BIT(EXTI_SWI_GPIO11_POS) + +#define EXTI_SWI_GPIO10_POS 10U +#define EXTI_SWI_GPIO10_MSK BIT(EXTI_SWI_GPIO10_POS) + +#define EXTI_SWI_GPIO9_POS 9U +#define EXTI_SWI_GPIO9_MSK BIT(EXTI_SWI_GPIO9_POS) + +#define EXTI_SWI_GPIO8_POS 8U +#define EXTI_SWI_GPIO8_MSK BIT(EXTI_SWI_GPIO8_POS) + +#define EXTI_SWI_GPIO7_POS 7U +#define EXTI_SWI_GPIO7_MSK BIT(EXTI_SWI_GPIO7_POS) + +#define EXTI_SWI_GPIO6_POS 6U +#define EXTI_SWI_GPIO6_MSK BIT(EXTI_SWI_GPIO6_POS) + +#define EXTI_SWI_GPIO5_POS 5U +#define EXTI_SWI_GPIO5_MSK BIT(EXTI_SWI_GPIO5_POS) + +#define EXTI_SWI_GPIO4_POS 4U +#define EXTI_SWI_GPIO4_MSK BIT(EXTI_SWI_GPIO4_POS) + +#define EXTI_SWI_GPIO3_POS 3U +#define EXTI_SWI_GPIO3_MSK BIT(EXTI_SWI_GPIO3_POS) + +#define EXTI_SWI_GPIO2_POS 2U +#define EXTI_SWI_GPIO2_MSK BIT(EXTI_SWI_GPIO2_POS) + +#define EXTI_SWI_GPIO1_POS 1U +#define EXTI_SWI_GPIO1_MSK BIT(EXTI_SWI_GPIO1_POS) + +#define EXTI_SWI_GPIO0_POS 0U +#define EXTI_SWI_GPIO0_MSK BIT(EXTI_SWI_GPIO0_POS) + +/****************** Bit definition for EXTI_ADTE register ************************/ + +#define EXTI_ADTE_WAKEUP_POS 21U +#define EXTI_ADTE_WAKEUP_MSK BIT(EXTI_ADTE_WAKEUP_POS) + +#define EXTI_ADTE_PVD0_POS 20U +#define EXTI_ADTE_PVD0_MSK BIT(EXTI_ADTE_PVD0_POS) + +#define EXTI_ADTE_CMP2_POS 17U +#define EXTI_ADTE_CMP2_MSK BIT(EXTI_ADTE_CMP2_POS) + +#define EXTI_ADTE_CMP1_POS 16U +#define EXTI_ADTE_CMP1_MSK BIT(EXTI_ADTE_CMP1_POS) + +#define EXTI_ADTE_GPIO15_POS 15U +#define EXTI_ADTE_GPIO15_MSK BIT(EXTI_ADTE_GPIO15_POS) + +#define EXTI_ADTE_GPIO14_POS 14U +#define EXTI_ADTE_GPIO14_MSK BIT(EXTI_ADTE_GPIO14_POS) + +#define EXTI_ADTE_GPIO13_POS 13U +#define EXTI_ADTE_GPIO13_MSK BIT(EXTI_ADTE_GPIO13_POS) + +#define EXTI_ADTE_GPIO12_POS 12U +#define EXTI_ADTE_GPIO12_MSK BIT(EXTI_ADTE_GPIO12_POS) + +#define EXTI_ADTE_GPIO11_POS 11U +#define EXTI_ADTE_GPIO11_MSK BIT(EXTI_ADTE_GPIO11_POS) + +#define EXTI_ADTE_GPIO10_POS 10U +#define EXTI_ADTE_GPIO10_MSK BIT(EXTI_ADTE_GPIO10_POS) + +#define EXTI_ADTE_GPIO9_POS 9U +#define EXTI_ADTE_GPIO9_MSK BIT(EXTI_ADTE_GPIO9_POS) + +#define EXTI_ADTE_GPIO8_POS 8U +#define EXTI_ADTE_GPIO8_MSK BIT(EXTI_ADTE_GPIO8_POS) + +#define EXTI_ADTE_GPIO7_POS 7U +#define EXTI_ADTE_GPIO7_MSK BIT(EXTI_ADTE_GPIO7_POS) + +#define EXTI_ADTE_GPIO6_POS 6U +#define EXTI_ADTE_GPIO6_MSK BIT(EXTI_ADTE_GPIO6_POS) + +#define EXTI_ADTE_GPIO5_POS 5U +#define EXTI_ADTE_GPIO5_MSK BIT(EXTI_ADTE_GPIO5_POS) + +#define EXTI_ADTE_GPIO4_POS 4U +#define EXTI_ADTE_GPIO4_MSK BIT(EXTI_ADTE_GPIO4_POS) + +#define EXTI_ADTE_GPIO3_POS 3U +#define EXTI_ADTE_GPIO3_MSK BIT(EXTI_ADTE_GPIO3_POS) + +#define EXTI_ADTE_GPIO2_POS 2U +#define EXTI_ADTE_GPIO2_MSK BIT(EXTI_ADTE_GPIO2_POS) + +#define EXTI_ADTE_GPIO1_POS 1U +#define EXTI_ADTE_GPIO1_MSK BIT(EXTI_ADTE_GPIO1_POS) + +#define EXTI_ADTE_GPIO0_POS 0U +#define EXTI_ADTE_GPIO0_MSK BIT(EXTI_ADTE_GPIO0_POS) + +/****************** Bit definition for EXTI_DB register ************************/ + +#define EXTI_DB_WAKEUP_POS 21U +#define EXTI_DB_WAKEUP_MSK BIT(EXTI_DB_WAKEUP_POS) + +#define EXTI_DB_PVD0_POS 20U +#define EXTI_DB_PVD0_MSK BIT(EXTI_DB_PVD0_POS) + +#define EXTI_DB_CMP2_POS 17U +#define EXTI_DB_CMP2_MSK BIT(EXTI_DB_CMP2_POS) + +#define EXTI_DB_CMP1_POS 16U +#define EXTI_DB_CMP1_MSK BIT(EXTI_DB_CMP1_POS) + +#define EXTI_DB_GPIO15_POS 15U +#define EXTI_DB_GPIO15_MSK BIT(EXTI_DB_GPIO15_POS) + +#define EXTI_DB_GPIO14_POS 14U +#define EXTI_DB_GPIO14_MSK BIT(EXTI_DB_GPIO14_POS) + +#define EXTI_DB_GPIO13_POS 13U +#define EXTI_DB_GPIO13_MSK BIT(EXTI_DB_GPIO13_POS) + +#define EXTI_DB_GPIO12_POS 12U +#define EXTI_DB_GPIO12_MSK BIT(EXTI_DB_GPIO12_POS) + +#define EXTI_DB_GPIO11_POS 11U +#define EXTI_DB_GPIO11_MSK BIT(EXTI_DB_GPIO11_POS) + +#define EXTI_DB_GPIO10_POS 10U +#define EXTI_DB_GPIO10_MSK BIT(EXTI_DB_GPIO10_POS) + +#define EXTI_DB_GPIO9_POS 9U +#define EXTI_DB_GPIO9_MSK BIT(EXTI_DB_GPIO9_POS) + +#define EXTI_DB_GPIO8_POS 8U +#define EXTI_DB_GPIO8_MSK BIT(EXTI_DB_GPIO8_POS) + +#define EXTI_DB_GPIO7_POS 7U +#define EXTI_DB_GPIO7_MSK BIT(EXTI_DB_GPIO7_POS) + +#define EXTI_DB_GPIO6_POS 6U +#define EXTI_DB_GPIO6_MSK BIT(EXTI_DB_GPIO6_POS) + +#define EXTI_DB_GPIO5_POS 5U +#define EXTI_DB_GPIO5_MSK BIT(EXTI_DB_GPIO5_POS) + +#define EXTI_DB_GPIO4_POS 4U +#define EXTI_DB_GPIO4_MSK BIT(EXTI_DB_GPIO4_POS) + +#define EXTI_DB_GPIO3_POS 3U +#define EXTI_DB_GPIO3_MSK BIT(EXTI_DB_GPIO3_POS) + +#define EXTI_DB_GPIO2_POS 2U +#define EXTI_DB_GPIO2_MSK BIT(EXTI_DB_GPIO2_POS) + +#define EXTI_DB_GPIO1_POS 1U +#define EXTI_DB_GPIO1_MSK BIT(EXTI_DB_GPIO1_POS) + +#define EXTI_DB_GPIO0_POS 0U +#define EXTI_DB_GPIO0_MSK BIT(EXTI_DB_GPIO0_POS) + +/****************** Bit definition for EXTI_DBCON register ************************/ + +#define EXTI_DBCON_DBPRE_POSS 8U +#define EXTI_DBCON_DBPRE_POSE 15U +#define EXTI_DBCON_DBPRE_MSK BITS(EXTI_DBCON_DBPRE_POSS,EXTI_DBCON_DBPRE_POSE) + +#define EXTI_DBCON_DBCNT_POSS 0U +#define EXTI_DBCON_DBCNT_POSE 2U +#define EXTI_DBCON_DBCNT_MSK BITS(EXTI_DBCON_DBCNT_POSS,EXTI_DBCON_DBCNT_POSE) + +/****************** Bit definition for EXTI_ICFG1 register ************************/ + +#define EXTI_ICFG1_GPIO7_POSS 28U +#define EXTI_ICFG1_GPIO7_POSE 31U +#define EXTI_ICFG1_GPIO7_MSK BITS(EXTI_ICFG1_GPIO7_POSS,EXTI_ICFG1_GPIO7_POSE) + +#define EXTI_ICFG1_GPIO6_POSS 24U +#define EXTI_ICFG1_GPIO6_POSE 27U +#define EXTI_ICFG1_GPIO6_MSK BITS(EXTI_ICFG1_GPIO6_POSS,EXTI_ICFG1_GPIO6_POSE) + +#define EXTI_ICFG1_GPIO5_POSS 20U +#define EXTI_ICFG1_GPIO5_POSE 23U +#define EXTI_ICFG1_GPIO5_MSK BITS(EXTI_ICFG1_GPIO5_POSS,EXTI_ICFG1_GPIO5_POSE) + +#define EXTI_ICFG1_GPIO4_POSS 16U +#define EXTI_ICFG1_GPIO4_POSE 19U +#define EXTI_ICFG1_GPIO4_MSK BITS(EXTI_ICFG1_GPIO4_POSS,EXTI_ICFG1_GPIO4_POSE) + +#define EXTI_ICFG1_GPIO3_POSS 12U +#define EXTI_ICFG1_GPIO3_POSE 15U +#define EXTI_ICFG1_GPIO3_MSK BITS(EXTI_ICFG1_GPIO3_POSS,EXTI_ICFG1_GPIO3_POSE) + +#define EXTI_ICFG1_GPIO2_POSS 8U +#define EXTI_ICFG1_GPIO2_POSE 11U +#define EXTI_ICFG1_GPIO2_MSK BITS(EXTI_ICFG1_GPIO2_POSS,EXTI_ICFG1_GPIO2_POSE) + +#define EXTI_ICFG1_GPIO1_POSS 4U +#define EXTI_ICFG1_GPIO1_POSE 7U +#define EXTI_ICFG1_GPIO1_MSK BITS(EXTI_ICFG1_GPIO1_POSS,EXTI_ICFG1_GPIO1_POSE) + +#define EXTI_ICFG1_GPIO0_POSS 0U +#define EXTI_ICFG1_GPIO0_POSE 3U +#define EXTI_ICFG1_GPIO0_MSK BITS(EXTI_ICFG1_GPIO0_POSS,EXTI_ICFG1_GPIO0_POSE) + +/****************** Bit definition for EXTI_ICFG2 register ************************/ + +#define EXTI_ICFG2_GPIO15_POSS 28U +#define EXTI_ICFG2_GPIO15_POSE 31U +#define EXTI_ICFG2_GPIO15_MSK BITS(EXTI_ICFG2_GPIO15_POSS,EXTI_ICFG2_GPIO15_POSE) + +#define EXTI_ICFG2_GPIO14_POSS 24U +#define EXTI_ICFG2_GPIO14_POSE 27U +#define EXTI_ICFG2_GPIO14_MSK BITS(EXTI_ICFG2_GPIO14_POSS,EXTI_ICFG2_GPIO14_POSE) + +#define EXTI_ICFG2_GPIO13_POSS 20U +#define EXTI_ICFG2_GPIO13_POSE 23U +#define EXTI_ICFG2_GPIO13_MSK BITS(EXTI_ICFG2_GPIO13_POSS,EXTI_ICFG2_GPIO13_POSE) + +#define EXTI_ICFG2_GPIO12_POSS 16U +#define EXTI_ICFG2_GPIO12_POSE 19U +#define EXTI_ICFG2_GPIO12_MSK BITS(EXTI_ICFG2_GPIO12_POSS,EXTI_ICFG2_GPIO12_POSE) + +#define EXTI_ICFG2_GPIO11_POSS 12U +#define EXTI_ICFG2_GPIO11_POSE 15U +#define EXTI_ICFG2_GPIO11_MSK BITS(EXTI_ICFG2_GPIO11_POSS,EXTI_ICFG2_GPIO11_POSE) + +#define EXTI_ICFG2_GPIO10_POSS 8U +#define EXTI_ICFG2_GPIO10_POSE 11U +#define EXTI_ICFG2_GPIO10_MSK BITS(EXTI_ICFG2_GPIO10_POSS,EXTI_ICFG2_GPIO10_POSE) + +#define EXTI_ICFG2_GPIO9_POSS 4U +#define EXTI_ICFG2_GPIO9_POSE 7U +#define EXTI_ICFG2_GPIO9_MSK BITS(EXTI_ICFG2_GPIO9_POSS,EXTI_ICFG2_GPIO9_POSE) + +#define EXTI_ICFG2_GPIO8_POSS 0U +#define EXTI_ICFG2_GPIO8_POSE 3U +#define EXTI_ICFG2_GPIO8_MSK BITS(EXTI_ICFG2_GPIO8_POSS,EXTI_ICFG2_GPIO8_POSE) + +typedef struct +{ + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __IO uint32_t RTS; + __IO uint32_t FTS; + __O uint32_t SWI; + __IO uint32_t ADTE; + __IO uint32_t DB; + __IO uint32_t DBCON; + __IO uint32_t ICFG1; + __IO uint32_t ICFG2; +} EXTI_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h new file mode 100644 index 0000000000000000000000000000000000000000..0b9850cb4e68986ba97ad2ab20b6669da69f4f89 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h @@ -0,0 +1,181 @@ +/** + ************************************************************************************** + * @file REG_FC.h + * @brief FC Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __fc_H__ +#define __fc_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for FC_CMD register ************************/ + +#define FC_CMD_FC_CMD_POSS 0U +#define FC_CMD_FC_CMD_POSE 7U +#define FC_CMD_FC_CMD_MSK BITS(FC_CMD_FC_CMD_POSS,FC_CMD_FC_CMD_POSE) + +/****************** Bit definition for FC_PA register ************************/ + +#define FC_PA_PCNT_POSS 25U +#define FC_PA_PCNT_POSE 31U +#define FC_PA_PCNT_MSK BITS(FC_PA_PCNT_POSS,FC_PA_PCNT_POSE) + +#define FC_PA_IFREN_POS 24U +#define FC_PA_IFREN_MSK BIT(FC_PA_IFREN_POS) + +#define FC_PA_PROG_ADDR_POSS 0U +#define FC_PA_PROG_ADDR_POSE 23U +#define FC_PA_PROG_ADDR_MSK BITS(FC_PA_PROG_ADDR_POSS,FC_PA_PROG_ADDR_POSE) + +/****************** Bit definition for FC_PLD register ************************/ + +#define FC_PLD_PROG_DATA_L_POSS 0U +#define FC_PLD_PROG_DATA_L_POSE 31U +#define FC_PLD_PROG_DATA_L_MSK BITS(FC_PLD_PROG_DATA_L_POSS,FC_PLD_PROG_DATA_L_POSE) + +/****************** Bit definition for FC_PHD register ************************/ + +#define FC_PHD_PROG_DATA_H_POSS 0U +#define FC_PHD_PROG_DATA_H_POSE 31U +#define FC_PHD_PROG_DATA_H_MSK BITS(FC_PHD_PROG_DATA_H_POSS,FC_PHD_PROG_DATA_H_POSE) + +/****************** Bit definition for FC_CON register ************************/ + +#define FC_CON_SLEEP_POS 9U +#define FC_CON_SLEEP_MSK BIT(FC_CON_SLEEP_POS) + +#define FC_CON_PFEN_POS 8U +#define FC_CON_PFEN_MSK BIT(FC_CON_PFEN_POS) + +#define FC_CON_WAIT_POSS 0U +#define FC_CON_WAIT_POSE 1U +#define FC_CON_WAIT_MSK BITS(FC_CON_WAIT_POSS,FC_CON_WAIT_POSE) + +/****************** Bit definition for FC_STAT register ************************/ + +#define FC_STAT_OPVD_POS 2U +#define FC_STAT_OPVD_MSK BIT(FC_STAT_OPVD_POS) + +#define FC_STAT_MUNP2_POS 1U +#define FC_STAT_MUNP2_MSK BIT(FC_STAT_MUNP2_POS) + +#define FC_STAT_MUNP1_POS 0U +#define FC_STAT_MUNP1_MSK BIT(FC_STAT_MUNP1_POS) + +/****************** Bit definition for FC_UPL register ************************/ + +#define FC_UPL_UPL_POSS 0U +#define FC_UPL_UPL_POSE 31U +#define FC_UPL_UPL_MSK BITS(FC_UPL_UPL_POSS,FC_UPL_UPL_POSE) + +/****************** Bit definition for FC_UPH register ************************/ + +#define FC_UPH_UPH_POSS 0U +#define FC_UPH_UPH_POSE 31U +#define FC_UPH_UPH_MSK BITS(FC_UPH_UPH_POSS,FC_UPH_UPH_POSE) + +/****************** Bit definition for FC_OP_TRIM register ************************/ + +#define FC_OP_TRIM_BGTRIMVD_POSS 24U +#define FC_OP_TRIM_BGTRIMVD_POSE 31U +#define FC_OP_TRIM_BGTRIMVD_MSK BITS(FC_OP_TRIM_BGTRIMVD_POSS,FC_OP_TRIM_BGTRIMVD_POSE) + +#define FC_OP_TRIM_BGTRIM_POSS 16U +#define FC_OP_TRIM_BGTRIM_POSE 23U +#define FC_OP_TRIM_BGTRIM_MSK BITS(FC_OP_TRIM_BGTRIM_POSS,FC_OP_TRIM_BGTRIM_POSE) + +#define FC_OP_TRIM_HRCTRIMVD_POSS 8U +#define FC_OP_TRIM_HRCTRIMVD_POSE 15U +#define FC_OP_TRIM_HRCTRIMVD_MSK BITS(FC_OP_TRIM_HRCTRIMVD_POSS,FC_OP_TRIM_HRCTRIMVD_POSE) + +#define FC_OP_TRIM_HRCTRIM_POSS 0U +#define FC_OP_TRIM_HRCTRIM_POSE 7U +#define FC_OP_TRIM_HRCTRIM_MSK BITS(FC_OP_TRIM_HRCTRIM_POSS,FC_OP_TRIM_HRCTRIM_POSE) + +/****************** Bit definition for FC_OP_PRT2L register ************************/ + +#define FC_OP_PRT2L_PRTLV2L_POSS 0U +#define FC_OP_PRT2L_PRTLV2L_POSE 31U +#define FC_OP_PRT2L_PRTLV2L_MSK BITS(FC_OP_PRT2L_PRTLV2L_POSS,FC_OP_PRT2L_PRTLV2L_POSE) + +/****************** Bit definition for FC_OP_PRT2H register ************************/ + +#define FC_OP_PRT2H_PRTLV2H_POSS 0U +#define FC_OP_PRT2H_PRTLV2H_POSE 31U +#define FC_OP_PRT2H_PRTLV2H_MSK BITS(FC_OP_PRT2H_PRTLV2H_POSS,FC_OP_PRT2H_PRTLV2H_POSE) + +/****************** Bit definition for FC_OP_PRT1L register ************************/ + +#define FC_OP_PRT1L_PRTLV1L_POSS 0U +#define FC_OP_PRT1L_PRTLV1L_POSE 31U +#define FC_OP_PRT1L_PRTLV1L_MSK BITS(FC_OP_PRT1L_PRTLV1L_POSS,FC_OP_PRT1L_PRTLV1L_POSE) + +/****************** Bit definition for FC_OP_PRT1H register ************************/ + +#define FC_OP_PRT1H_PRTLV1H_POSS 0U +#define FC_OP_PRT1H_PRTLV1H_POSE 31U +#define FC_OP_PRT1H_PRTLV1H_MSK BITS(FC_OP_PRT1H_PRTLV1H_POSS,FC_OP_PRT1H_PRTLV1H_POSE) + +/****************** Bit definition for FC_OP_REMAP register ************************/ + +#define FC_OP_REMAP_HREMAP_POSS 8U +#define FC_OP_REMAP_HREMAP_POSE 15U +#define FC_OP_REMAP_HREMAP_MSK BITS(FC_OP_REMAP_HREMAP_POSS,FC_OP_REMAP_HREMAP_POSE) + +#define FC_OP_REMAP_SREMAP_POSS 4U +#define FC_OP_REMAP_SREMAP_POSE 5U +#define FC_OP_REMAP_SREMAP_MSK BITS(FC_OP_REMAP_SREMAP_POSS,FC_OP_REMAP_SREMAP_POSE) + +#define FC_OP_REMAP_SEFBASE_POSS 0U +#define FC_OP_REMAP_SEFBASE_POSE 3U +#define FC_OP_REMAP_SEFBASE_MSK BITS(FC_OP_REMAP_SEFBASE_POSS,FC_OP_REMAP_SEFBASE_POSE) + +typedef struct +{ + __IO uint32_t CMD; + __IO uint32_t PA; + __IO uint32_t PLD; + __IO uint32_t PHD; + __IO uint32_t CON; + __I uint32_t STAT; + uint32_t RESERVED0[2] ; + __IO uint32_t UPL; + __IO uint32_t UPH; + uint32_t RESERVED1[2] ; + __I uint32_t OP_TRIM; + uint32_t RESERVED2[4] ; +// uint32_t ADCTRIM_1V; +// uint32_t ADCTRIM_2V; +// uint32_t RESERVED3; + + uint32_t ADCTRIM_VDD5V_VREF5V; + uint32_t ADCTRIM_VDD3V3_VREF3V3; + uint32_t ADCTRIM_VDD5V_VREF2V5; + __I uint32_t OP_PRT2L; + __I uint32_t OP_PRT2H; + __I uint32_t OP_PRT1L; + __I uint32_t OP_PRT1H; + __I uint32_t OP_REMAP; +} FC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..d965ef3b94aa8abf8a88ede1ede6a8eaeceb1e58 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h @@ -0,0 +1,710 @@ +/** + ************************************************************************************** + * @file REG_GPIO.h + * @brief GPIO Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for GPIO_IDATA register ************************/ + +#define GPIO_IDATA_ID15_POS 15U +#define GPIO_IDATA_ID15_MSK BIT(GPIO_IDATA_ID15_POS) + +#define GPIO_IDATA_ID14_POS 14U +#define GPIO_IDATA_ID14_MSK BIT(GPIO_IDATA_ID14_POS) + +#define GPIO_IDATA_ID13_POS 13U +#define GPIO_IDATA_ID13_MSK BIT(GPIO_IDATA_ID13_POS) + +#define GPIO_IDATA_ID12_POS 12U +#define GPIO_IDATA_ID12_MSK BIT(GPIO_IDATA_ID12_POS) + +#define GPIO_IDATA_ID11_POS 11U +#define GPIO_IDATA_ID11_MSK BIT(GPIO_IDATA_ID11_POS) + +#define GPIO_IDATA_ID10_POS 10U +#define GPIO_IDATA_ID10_MSK BIT(GPIO_IDATA_ID10_POS) + +#define GPIO_IDATA_ID9_POS 9U +#define GPIO_IDATA_ID9_MSK BIT(GPIO_IDATA_ID9_POS) + +#define GPIO_IDATA_ID8_POS 8U +#define GPIO_IDATA_ID8_MSK BIT(GPIO_IDATA_ID8_POS) + +#define GPIO_IDATA_ID7_POS 7U +#define GPIO_IDATA_ID7_MSK BIT(GPIO_IDATA_ID7_POS) + +#define GPIO_IDATA_ID6_POS 6U +#define GPIO_IDATA_ID6_MSK BIT(GPIO_IDATA_ID6_POS) + +#define GPIO_IDATA_ID5_POS 5U +#define GPIO_IDATA_ID5_MSK BIT(GPIO_IDATA_ID5_POS) + +#define GPIO_IDATA_ID4_POS 4U +#define GPIO_IDATA_ID4_MSK BIT(GPIO_IDATA_ID4_POS) + +#define GPIO_IDATA_ID3_POS 3U +#define GPIO_IDATA_ID3_MSK BIT(GPIO_IDATA_ID3_POS) + +#define GPIO_IDATA_ID2_POS 2U +#define GPIO_IDATA_ID2_MSK BIT(GPIO_IDATA_ID2_POS) + +#define GPIO_IDATA_ID1_POS 1U +#define GPIO_IDATA_ID1_MSK BIT(GPIO_IDATA_ID1_POS) + +#define GPIO_IDATA_ID0_POS 0U +#define GPIO_IDATA_ID0_MSK BIT(GPIO_IDATA_ID0_POS) + +/****************** Bit definition for GPIO_ODATA register ************************/ + +#define GPIO_ODATA_OD15_POS 15U +#define GPIO_ODATA_OD15_MSK BIT(GPIO_ODATA_OD15_POS) + +#define GPIO_ODATA_OD14_POS 14U +#define GPIO_ODATA_OD14_MSK BIT(GPIO_ODATA_OD14_POS) + +#define GPIO_ODATA_OD13_POS 13U +#define GPIO_ODATA_OD13_MSK BIT(GPIO_ODATA_OD13_POS) + +#define GPIO_ODATA_OD12_POS 12U +#define GPIO_ODATA_OD12_MSK BIT(GPIO_ODATA_OD12_POS) + +#define GPIO_ODATA_OD11_POS 11U +#define GPIO_ODATA_OD11_MSK BIT(GPIO_ODATA_OD11_POS) + +#define GPIO_ODATA_OD10_POS 10U +#define GPIO_ODATA_OD10_MSK BIT(GPIO_ODATA_OD10_POS) + +#define GPIO_ODATA_OD9_POS 9U +#define GPIO_ODATA_OD9_MSK BIT(GPIO_ODATA_OD9_POS) + +#define GPIO_ODATA_OD8_POS 8U +#define GPIO_ODATA_OD8_MSK BIT(GPIO_ODATA_OD8_POS) + +#define GPIO_ODATA_OD7_POS 7U +#define GPIO_ODATA_OD7_MSK BIT(GPIO_ODATA_OD7_POS) + +#define GPIO_ODATA_OD6_POS 6U +#define GPIO_ODATA_OD6_MSK BIT(GPIO_ODATA_OD6_POS) + +#define GPIO_ODATA_OD5_POS 5U +#define GPIO_ODATA_OD5_MSK BIT(GPIO_ODATA_OD5_POS) + +#define GPIO_ODATA_OD4_POS 4U +#define GPIO_ODATA_OD4_MSK BIT(GPIO_ODATA_OD4_POS) + +#define GPIO_ODATA_OD3_POS 3U +#define GPIO_ODATA_OD3_MSK BIT(GPIO_ODATA_OD3_POS) + +#define GPIO_ODATA_OD2_POS 2U +#define GPIO_ODATA_OD2_MSK BIT(GPIO_ODATA_OD2_POS) + +#define GPIO_ODATA_OD1_POS 1U +#define GPIO_ODATA_OD1_MSK BIT(GPIO_ODATA_OD1_POS) + +#define GPIO_ODATA_OD0_POS 0U +#define GPIO_ODATA_OD0_MSK BIT(GPIO_ODATA_OD0_POS) + +/****************** Bit definition for GPIO_BSBR register ************************/ + +#define GPIO_BSBR_BR15_POS 31U +#define GPIO_BSBR_BR15_MSK BIT(GPIO_BSBR_BR15_POS) + +#define GPIO_BSBR_BR14_POS 30U +#define GPIO_BSBR_BR14_MSK BIT(GPIO_BSBR_BR14_POS) + +#define GPIO_BSBR_BR13_POS 29U +#define GPIO_BSBR_BR13_MSK BIT(GPIO_BSBR_BR13_POS) + +#define GPIO_BSBR_BR12_POS 28U +#define GPIO_BSBR_BR12_MSK BIT(GPIO_BSBR_BR12_POS) + +#define GPIO_BSBR_BR11_POS 27U +#define GPIO_BSBR_BR11_MSK BIT(GPIO_BSBR_BR11_POS) + +#define GPIO_BSBR_BR10_POS 26U +#define GPIO_BSBR_BR10_MSK BIT(GPIO_BSBR_BR10_POS) + +#define GPIO_BSBR_BR9_POS 25U +#define GPIO_BSBR_BR9_MSK BIT(GPIO_BSBR_BR9_POS) + +#define GPIO_BSBR_BR8_POS 24U +#define GPIO_BSBR_BR8_MSK BIT(GPIO_BSBR_BR8_POS) + +#define GPIO_BSBR_BR7_POS 23U +#define GPIO_BSBR_BR7_MSK BIT(GPIO_BSBR_BR7_POS) + +#define GPIO_BSBR_BR6_POS 22U +#define GPIO_BSBR_BR6_MSK BIT(GPIO_BSBR_BR6_POS) + +#define GPIO_BSBR_BR5_POS 21U +#define GPIO_BSBR_BR5_MSK BIT(GPIO_BSBR_BR5_POS) + +#define GPIO_BSBR_BR4_POS 20U +#define GPIO_BSBR_BR4_MSK BIT(GPIO_BSBR_BR4_POS) + +#define GPIO_BSBR_BR3_POS 19U +#define GPIO_BSBR_BR3_MSK BIT(GPIO_BSBR_BR3_POS) + +#define GPIO_BSBR_BR2_POS 18U +#define GPIO_BSBR_BR2_MSK BIT(GPIO_BSBR_BR2_POS) + +#define GPIO_BSBR_BR1_POS 17U +#define GPIO_BSBR_BR1_MSK BIT(GPIO_BSBR_BR1_POS) + +#define GPIO_BSBR_BR0_POS 16U +#define GPIO_BSBR_BR0_MSK BIT(GPIO_BSBR_BR0_POS) + +#define GPIO_BSBR_BS15_POS 15U +#define GPIO_BSBR_BS15_MSK BIT(GPIO_BSBR_BS15_POS) + +#define GPIO_BSBR_BS14_POS 14U +#define GPIO_BSBR_BS14_MSK BIT(GPIO_BSBR_BS14_POS) + +#define GPIO_BSBR_BS13_POS 13U +#define GPIO_BSBR_BS13_MSK BIT(GPIO_BSBR_BS13_POS) + +#define GPIO_BSBR_BS12_POS 12U +#define GPIO_BSBR_BS12_MSK BIT(GPIO_BSBR_BS12_POS) + +#define GPIO_BSBR_BS11_POS 11U +#define GPIO_BSBR_BS11_MSK BIT(GPIO_BSBR_BS11_POS) + +#define GPIO_BSBR_BS10_POS 10U +#define GPIO_BSBR_BS10_MSK BIT(GPIO_BSBR_BS10_POS) + +#define GPIO_BSBR_BS9_POS 9U +#define GPIO_BSBR_BS9_MSK BIT(GPIO_BSBR_BS9_POS) + +#define GPIO_BSBR_BS8_POS 8U +#define GPIO_BSBR_BS8_MSK BIT(GPIO_BSBR_BS8_POS) + +#define GPIO_BSBR_BS7_POS 7U +#define GPIO_BSBR_BS7_MSK BIT(GPIO_BSBR_BS7_POS) + +#define GPIO_BSBR_BS6_POS 6U +#define GPIO_BSBR_BS6_MSK BIT(GPIO_BSBR_BS6_POS) + +#define GPIO_BSBR_BS5_POS 5U +#define GPIO_BSBR_BS5_MSK BIT(GPIO_BSBR_BS5_POS) + +#define GPIO_BSBR_BS4_POS 4U +#define GPIO_BSBR_BS4_MSK BIT(GPIO_BSBR_BS4_POS) + +#define GPIO_BSBR_BS3_POS 3U +#define GPIO_BSBR_BS3_MSK BIT(GPIO_BSBR_BS3_POS) + +#define GPIO_BSBR_BS2_POS 2U +#define GPIO_BSBR_BS2_MSK BIT(GPIO_BSBR_BS2_POS) + +#define GPIO_BSBR_BS1_POS 1U +#define GPIO_BSBR_BS1_MSK BIT(GPIO_BSBR_BS1_POS) + +#define GPIO_BSBR_BS0_POS 0U +#define GPIO_BSBR_BS0_MSK BIT(GPIO_BSBR_BS0_POS) + +/****************** Bit definition for GPIO_LCK register ************************/ + +#define GPIO_LCK_LCKK_POS 16U +#define GPIO_LCK_LCKK_MSK BIT(GPIO_LCK_LCKK_POS) + +#define GPIO_LCK_LCK15_POS 15U +#define GPIO_LCK_LCK15_MSK BIT(GPIO_LCK_LCK15_POS) + +#define GPIO_LCK_LCK14_POS 14U +#define GPIO_LCK_LCK14_MSK BIT(GPIO_LCK_LCK14_POS) + +#define GPIO_LCK_LCK13_POS 13U +#define GPIO_LCK_LCK13_MSK BIT(GPIO_LCK_LCK13_POS) + +#define GPIO_LCK_LCK12_POS 12U +#define GPIO_LCK_LCK12_MSK BIT(GPIO_LCK_LCK12_POS) + +#define GPIO_LCK_LCK11_POS 11U +#define GPIO_LCK_LCK11_MSK BIT(GPIO_LCK_LCK11_POS) + +#define GPIO_LCK_LCK10_POS 10U +#define GPIO_LCK_LCK10_MSK BIT(GPIO_LCK_LCK10_POS) + +#define GPIO_LCK_LCK9_POS 9U +#define GPIO_LCK_LCK9_MSK BIT(GPIO_LCK_LCK9_POS) + +#define GPIO_LCK_LCK8_POS 8U +#define GPIO_LCK_LCK8_MSK BIT(GPIO_LCK_LCK8_POS) + +#define GPIO_LCK_LCK7_POS 7U +#define GPIO_LCK_LCK7_MSK BIT(GPIO_LCK_LCK7_POS) + +#define GPIO_LCK_LCK6_POS 6U +#define GPIO_LCK_LCK6_MSK BIT(GPIO_LCK_LCK6_POS) + +#define GPIO_LCK_LCK5_POS 5U +#define GPIO_LCK_LCK5_MSK BIT(GPIO_LCK_LCK5_POS) + +#define GPIO_LCK_LCK4_POS 4U +#define GPIO_LCK_LCK4_MSK BIT(GPIO_LCK_LCK4_POS) + +#define GPIO_LCK_LCK3_POS 3U +#define GPIO_LCK_LCK3_MSK BIT(GPIO_LCK_LCK3_POS) + +#define GPIO_LCK_LCK2_POS 2U +#define GPIO_LCK_LCK2_MSK BIT(GPIO_LCK_LCK2_POS) + +#define GPIO_LCK_LCK1_POS 1U +#define GPIO_LCK_LCK1_MSK BIT(GPIO_LCK_LCK1_POS) + +#define GPIO_LCK_LCK0_POS 0U +#define GPIO_LCK_LCK0_MSK BIT(GPIO_LCK_LCK0_POS) + +/****************** Bit definition for GPIO_MOD register ************************/ + +#define GPIO_MOD_MOD15_POSS 30U +#define GPIO_MOD_MOD15_POSE 31U +#define GPIO_MOD_MOD15_MSK BITS(GPIO_MOD_MOD15_POSS,GPIO_MOD_MOD15_POSE) + +#define GPIO_MOD_MOD14_POSS 28U +#define GPIO_MOD_MOD14_POSE 29U +#define GPIO_MOD_MOD14_MSK BITS(GPIO_MOD_MOD14_POSS,GPIO_MOD_MOD14_POSE) + +#define GPIO_MOD_MOD13_POSS 26U +#define GPIO_MOD_MOD13_POSE 27U +#define GPIO_MOD_MOD13_MSK BITS(GPIO_MOD_MOD13_POSS,GPIO_MOD_MOD13_POSE) + +#define GPIO_MOD_MOD12_POSS 24U +#define GPIO_MOD_MOD12_POSE 25U +#define GPIO_MOD_MOD12_MSK BITS(GPIO_MOD_MOD12_POSS,GPIO_MOD_MOD12_POSE) + +#define GPIO_MOD_MOD11_POSS 22U +#define GPIO_MOD_MOD11_POSE 23U +#define GPIO_MOD_MOD11_MSK BITS(GPIO_MOD_MOD11_POSS,GPIO_MOD_MOD11_POSE) + +#define GPIO_MOD_MOD10_POSS 20U +#define GPIO_MOD_MOD10_POSE 21U +#define GPIO_MOD_MOD10_MSK BITS(GPIO_MOD_MOD10_POSS,GPIO_MOD_MOD10_POSE) + +#define GPIO_MOD_MOD9_POSS 18U +#define GPIO_MOD_MOD9_POSE 19U +#define GPIO_MOD_MOD9_MSK BITS(GPIO_MOD_MOD9_POSS,GPIO_MOD_MOD9_POSE) + +#define GPIO_MOD_MOD8_POSS 16U +#define GPIO_MOD_MOD8_POSE 17U +#define GPIO_MOD_MOD8_MSK BITS(GPIO_MOD_MOD8_POSS,GPIO_MOD_MOD8_POSE) + +#define GPIO_MOD_MOD7_POSS 14U +#define GPIO_MOD_MOD7_POSE 15U +#define GPIO_MOD_MOD7_MSK BITS(GPIO_MOD_MOD7_POSS,GPIO_MOD_MOD7_POSE) + +#define GPIO_MOD_MOD6_POSS 12U +#define GPIO_MOD_MOD6_POSE 13U +#define GPIO_MOD_MOD6_MSK BITS(GPIO_MOD_MOD6_POSS,GPIO_MOD_MOD6_POSE) + +#define GPIO_MOD_MOD5_POSS 10U +#define GPIO_MOD_MOD5_POSE 11U +#define GPIO_MOD_MOD5_MSK BITS(GPIO_MOD_MOD5_POSS,GPIO_MOD_MOD5_POSE) + +#define GPIO_MOD_MOD4_POSS 8U +#define GPIO_MOD_MOD4_POSE 9U +#define GPIO_MOD_MOD4_MSK BITS(GPIO_MOD_MOD4_POSS,GPIO_MOD_MOD4_POSE) + +#define GPIO_MOD_MOD3_POSS 6U +#define GPIO_MOD_MOD3_POSE 7U +#define GPIO_MOD_MOD3_MSK BITS(GPIO_MOD_MOD3_POSS,GPIO_MOD_MOD3_POSE) + +#define GPIO_MOD_MOD2_POSS 4U +#define GPIO_MOD_MOD2_POSE 5U +#define GPIO_MOD_MOD2_MSK BITS(GPIO_MOD_MOD2_POSS,GPIO_MOD_MOD2_POSE) + +#define GPIO_MOD_MOD1_POSS 2U +#define GPIO_MOD_MOD1_POSE 3U +#define GPIO_MOD_MOD1_MSK BITS(GPIO_MOD_MOD1_POSS,GPIO_MOD_MOD1_POSE) + +#define GPIO_MOD_MOD0_POSS 0U +#define GPIO_MOD_MOD0_POSE 1U +#define GPIO_MOD_MOD0_MSK BITS(GPIO_MOD_MOD0_POSS,GPIO_MOD_MOD0_POSE) + +/****************** Bit definition for GPIO_PUD register ************************/ + +#define GPIO_PUD_PUD15_POSS 30U +#define GPIO_PUD_PUD15_POSE 31U +#define GPIO_PUD_PUD15_MSK BITS(GPIO_PUD_PUD15_POSS,GPIO_PUD_PUD15_POSE) + +#define GPIO_PUD_PUD14_POSS 28U +#define GPIO_PUD_PUD14_POSE 29U +#define GPIO_PUD_PUD14_MSK BITS(GPIO_PUD_PUD14_POSS,GPIO_PUD_PUD14_POSE) + +#define GPIO_PUD_PUD13_POSS 26U +#define GPIO_PUD_PUD13_POSE 27U +#define GPIO_PUD_PUD13_MSK BITS(GPIO_PUD_PUD13_POSS,GPIO_PUD_PUD13_POSE) + +#define GPIO_PUD_PUD12_POSS 24U +#define GPIO_PUD_PUD12_POSE 25U +#define GPIO_PUD_PUD12_MSK BITS(GPIO_PUD_PUD12_POSS,GPIO_PUD_PUD12_POSE) + +#define GPIO_PUD_PUD11_POSS 22U +#define GPIO_PUD_PUD11_POSE 23U +#define GPIO_PUD_PUD11_MSK BITS(GPIO_PUD_PUD11_POSS,GPIO_PUD_PUD11_POSE) + +#define GPIO_PUD_PUD10_POSS 20U +#define GPIO_PUD_PUD10_POSE 21U +#define GPIO_PUD_PUD10_MSK BITS(GPIO_PUD_PUD10_POSS,GPIO_PUD_PUD10_POSE) + +#define GPIO_PUD_PUD9_POSS 18U +#define GPIO_PUD_PUD9_POSE 19U +#define GPIO_PUD_PUD9_MSK BITS(GPIO_PUD_PUD9_POSS,GPIO_PUD_PUD9_POSE) + +#define GPIO_PUD_PUD8_POSS 16U +#define GPIO_PUD_PUD8_POSE 17U +#define GPIO_PUD_PUD8_MSK BITS(GPIO_PUD_PUD8_POSS,GPIO_PUD_PUD8_POSE) + +#define GPIO_PUD_PUD7_POSS 14U +#define GPIO_PUD_PUD7_POSE 15U +#define GPIO_PUD_PUD7_MSK BITS(GPIO_PUD_PUD7_POSS,GPIO_PUD_PUD7_POSE) + +#define GPIO_PUD_PUD6_POSS 12U +#define GPIO_PUD_PUD6_POSE 13U +#define GPIO_PUD_PUD6_MSK BITS(GPIO_PUD_PUD6_POSS,GPIO_PUD_PUD6_POSE) + +#define GPIO_PUD_PUD5_POSS 10U +#define GPIO_PUD_PUD5_POSE 11U +#define GPIO_PUD_PUD5_MSK BITS(GPIO_PUD_PUD5_POSS,GPIO_PUD_PUD5_POSE) + +#define GPIO_PUD_PUD4_POSS 8U +#define GPIO_PUD_PUD4_POSE 9U +#define GPIO_PUD_PUD4_MSK BITS(GPIO_PUD_PUD4_POSS,GPIO_PUD_PUD4_POSE) + +#define GPIO_PUD_PUD3_POSS 6U +#define GPIO_PUD_PUD3_POSE 7U +#define GPIO_PUD_PUD3_MSK BITS(GPIO_PUD_PUD3_POSS,GPIO_PUD_PUD3_POSE) + +#define GPIO_PUD_PUD2_POSS 4U +#define GPIO_PUD_PUD2_POSE 5U +#define GPIO_PUD_PUD2_MSK BITS(GPIO_PUD_PUD2_POSS,GPIO_PUD_PUD2_POSE) + +#define GPIO_PUD_PUD1_POSS 2U +#define GPIO_PUD_PUD1_POSE 3U +#define GPIO_PUD_PUD1_MSK BITS(GPIO_PUD_PUD1_POSS,GPIO_PUD_PUD1_POSE) + +#define GPIO_PUD_PUD0_POSS 0U +#define GPIO_PUD_PUD0_POSE 1U +#define GPIO_PUD_PUD0_MSK BITS(GPIO_PUD_PUD0_POSS,GPIO_PUD_PUD0_POSE) + +/****************** Bit definition for GPIO_OT register ************************/ + +#define GPIO_OT_OT15_POS 15U +#define GPIO_OT_OT15_MSK BIT(GPIO_OT_OT15_POS) + +#define GPIO_OT_OT14_POS 14U +#define GPIO_OT_OT14_MSK BIT(GPIO_OT_OT14_POS) + +#define GPIO_OT_OT13_POS 13U +#define GPIO_OT_OT13_MSK BIT(GPIO_OT_OT13_POS) + +#define GPIO_OT_OT12_POS 12U +#define GPIO_OT_OT12_MSK BIT(GPIO_OT_OT12_POS) + +#define GPIO_OT_OT11_POS 11U +#define GPIO_OT_OT11_MSK BIT(GPIO_OT_OT11_POS) + +#define GPIO_OT_OT10_POS 10U +#define GPIO_OT_OT10_MSK BIT(GPIO_OT_OT10_POS) + +#define GPIO_OT_OT9_POS 9U +#define GPIO_OT_OT9_MSK BIT(GPIO_OT_OT9_POS) + +#define GPIO_OT_OT8_POS 8U +#define GPIO_OT_OT8_MSK BIT(GPIO_OT_OT8_POS) + +#define GPIO_OT_OT7_POS 7U +#define GPIO_OT_OT7_MSK BIT(GPIO_OT_OT7_POS) + +#define GPIO_OT_OT6_POS 6U +#define GPIO_OT_OT6_MSK BIT(GPIO_OT_OT6_POS) + +#define GPIO_OT_OT5_POS 5U +#define GPIO_OT_OT5_MSK BIT(GPIO_OT_OT5_POS) + +#define GPIO_OT_OT4_POS 4U +#define GPIO_OT_OT4_MSK BIT(GPIO_OT_OT4_POS) + +#define GPIO_OT_OT3_POS 3U +#define GPIO_OT_OT3_MSK BIT(GPIO_OT_OT3_POS) + +#define GPIO_OT_OT2_POS 2U +#define GPIO_OT_OT2_MSK BIT(GPIO_OT_OT2_POS) + +#define GPIO_OT_OT1_POS 1U +#define GPIO_OT_OT1_MSK BIT(GPIO_OT_OT1_POS) + +#define GPIO_OT_OT0_POS 0U +#define GPIO_OT_OT0_MSK BIT(GPIO_OT_OT0_POS) + +#define GPIO_OT_OT_POSS 0U +#define GPIO_OT_OT_POSE 15U +#define GPIO_OT_OT_MSK BITS(GPIO_OT_OT_POSS,GPIO_OT_OT_POSE) + +/****************** Bit definition for GPIO_DS register ************************/ + +#define GPIO_DS_DS15_POS 15U +#define GPIO_DS_DS15_MSK BIT(GPIO_DS_DS15_POS) + +#define GPIO_DS_DS14_POS 14U +#define GPIO_DS_DS14_MSK BIT(GPIO_DS_DS14_POS) + +#define GPIO_DS_DS13_POS 13U +#define GPIO_DS_DS13_MSK BIT(GPIO_DS_DS13_POS) + +#define GPIO_DS_DS12_POS 12U +#define GPIO_DS_DS12_MSK BIT(GPIO_DS_DS12_POS) + +#define GPIO_DS_DS11_POS 11U +#define GPIO_DS_DS11_MSK BIT(GPIO_DS_DS11_POS) + +#define GPIO_DS_DS10_POS 10U +#define GPIO_DS_DS10_MSK BIT(GPIO_DS_DS10_POS) + +#define GPIO_DS_DS9_POS 9U +#define GPIO_DS_DS9_MSK BIT(GPIO_DS_DS9_POS) + +#define GPIO_DS_DS8_POS 8U +#define GPIO_DS_DS8_MSK BIT(GPIO_DS_DS8_POS) + +#define GPIO_DS_DS7_POS 7U +#define GPIO_DS_DS7_MSK BIT(GPIO_DS_DS7_POS) + +#define GPIO_DS_DS6_POS 6U +#define GPIO_DS_DS6_MSK BIT(GPIO_DS_DS6_POS) + +#define GPIO_DS_DS5_POS 5U +#define GPIO_DS_DS5_MSK BIT(GPIO_DS_DS5_POS) + +#define GPIO_DS_DS4_POS 4U +#define GPIO_DS_DS4_MSK BIT(GPIO_DS_DS4_POS) + +#define GPIO_DS_DS3_POS 3U +#define GPIO_DS_DS3_MSK BIT(GPIO_DS_DS3_POS) + +#define GPIO_DS_DS2_POS 2U +#define GPIO_DS_DS2_MSK BIT(GPIO_DS_DS2_POS) + +#define GPIO_DS_DS1_POS 1U +#define GPIO_DS_DS1_MSK BIT(GPIO_DS_DS1_POS) + +#define GPIO_DS_DS0_POS 0U +#define GPIO_DS_DS0_MSK BIT(GPIO_DS_DS0_POS) + +#define GPIO_DS_DS_POSS 0U +#define GPIO_DS_DS_POSE 15U +#define GPIO_DS_DS_MSK BITS(GPIO_DS_DS_POSS,GPIO_DS_DS_POSE) + +/****************** Bit definition for GPIO_FIR register ************************/ + +#define GPIO_FIR_FIR15_POS 15U +#define GPIO_FIR_FIR15_MSK BIT(GPIO_FIR_FIR15_POS) + +#define GPIO_FIR_FIR14_POS 14U +#define GPIO_FIR_FIR14_MSK BIT(GPIO_FIR_FIR14_POS) + +#define GPIO_FIR_FIR13_POS 13U +#define GPIO_FIR_FIR13_MSK BIT(GPIO_FIR_FIR13_POS) + +#define GPIO_FIR_FIR12_POS 12U +#define GPIO_FIR_FIR12_MSK BIT(GPIO_FIR_FIR12_POS) + +#define GPIO_FIR_FIR11_POS 11U +#define GPIO_FIR_FIR11_MSK BIT(GPIO_FIR_FIR11_POS) + +#define GPIO_FIR_FIR10_POS 10U +#define GPIO_FIR_FIR10_MSK BIT(GPIO_FIR_FIR10_POS) + +#define GPIO_FIR_FIR9_POS 9U +#define GPIO_FIR_FIR9_MSK BIT(GPIO_FIR_FIR9_POS) + +#define GPIO_FIR_FIR8_POS 8U +#define GPIO_FIR_FIR8_MSK BIT(GPIO_FIR_FIR8_POS) + +#define GPIO_FIR_FIR7_POS 7U +#define GPIO_FIR_FIR7_MSK BIT(GPIO_FIR_FIR7_POS) + +#define GPIO_FIR_FIR6_POS 6U +#define GPIO_FIR_FIR6_MSK BIT(GPIO_FIR_FIR6_POS) + +#define GPIO_FIR_FIR5_POS 5U +#define GPIO_FIR_FIR5_MSK BIT(GPIO_FIR_FIR5_POS) + +#define GPIO_FIR_FIR4_POS 4U +#define GPIO_FIR_FIR4_MSK BIT(GPIO_FIR_FIR4_POS) + +#define GPIO_FIR_FIR3_POS 3U +#define GPIO_FIR_FIR3_MSK BIT(GPIO_FIR_FIR3_POS) + +#define GPIO_FIR_FIR2_POS 2U +#define GPIO_FIR_FIR2_MSK BIT(GPIO_FIR_FIR2_POS) + +#define GPIO_FIR_FIR1_POS 1U +#define GPIO_FIR_FIR1_MSK BIT(GPIO_FIR_FIR1_POS) + +#define GPIO_FIR_FIR0_POS 0U +#define GPIO_FIR_FIR0_MSK BIT(GPIO_FIR_FIR0_POS) + +/****************** Bit definition for GPIO_IST register ************************/ + +#define GPIO_IST_IST15_POS 15U +#define GPIO_IST_IST15_MSK BIT(GPIO_IST_IST15_POS) + +#define GPIO_IST_IST14_POS 14U +#define GPIO_IST_IST14_MSK BIT(GPIO_IST_IST14_POS) + +#define GPIO_IST_IST13_POS 13U +#define GPIO_IST_IST13_MSK BIT(GPIO_IST_IST13_POS) + +#define GPIO_IST_IST12_POS 12U +#define GPIO_IST_IST12_MSK BIT(GPIO_IST_IST12_POS) + +#define GPIO_IST_IST11_POS 11U +#define GPIO_IST_IST11_MSK BIT(GPIO_IST_IST11_POS) + +#define GPIO_IST_IST10_POS 10U +#define GPIO_IST_IST10_MSK BIT(GPIO_IST_IST10_POS) + +#define GPIO_IST_IST9_POS 9U +#define GPIO_IST_IST9_MSK BIT(GPIO_IST_IST9_POS) + +#define GPIO_IST_IST8_POS 8U +#define GPIO_IST_IST8_MSK BIT(GPIO_IST_IST8_POS) + +#define GPIO_IST_IST7_POS 7U +#define GPIO_IST_IST7_MSK BIT(GPIO_IST_IST7_POS) + +#define GPIO_IST_IST6_POS 6U +#define GPIO_IST_IST6_MSK BIT(GPIO_IST_IST6_POS) + +#define GPIO_IST_IST5_POS 5U +#define GPIO_IST_IST5_MSK BIT(GPIO_IST_IST5_POS) + +#define GPIO_IST_IST4_POS 4U +#define GPIO_IST_IST4_MSK BIT(GPIO_IST_IST4_POS) + +#define GPIO_IST_IST3_POS 3U +#define GPIO_IST_IST3_MSK BIT(GPIO_IST_IST3_POS) + +#define GPIO_IST_IST2_POS 2U +#define GPIO_IST_IST2_MSK BIT(GPIO_IST_IST2_POS) + +#define GPIO_IST_IST1_POS 1U +#define GPIO_IST_IST1_MSK BIT(GPIO_IST_IST1_POS) + +#define GPIO_IST_IST0_POS 0U +#define GPIO_IST_IST0_MSK BIT(GPIO_IST_IST0_POS) + +#define GPIO_IST_IST_POSS 0U +#define GPIO_IST_IST_POSE 15U +#define GPIO_IST_IST_MSK BITS(GPIO_IST_IST_POSS, GPIO_IST_IST_POSE) + +/****************** Bit definition for GPIO_AFL register ************************/ + +#define GPIO_AFL_AF7_POSS 28U +#define GPIO_AFL_AF7_POSE 31U +#define GPIO_AFL_AF7_MSK BITS(GPIO_AFL_AF7_POSS,GPIO_AFL_AF7_POSE) + +#define GPIO_AFL_AF6_POSS 24U +#define GPIO_AFL_AF6_POSE 27U +#define GPIO_AFL_AF6_MSK BITS(GPIO_AFL_AF6_POSS,GPIO_AFL_AF6_POSE) + +#define GPIO_AFL_AF5_POSS 20U +#define GPIO_AFL_AF5_POSE 23U +#define GPIO_AFL_AF5_MSK BITS(GPIO_AFL_AF5_POSS,GPIO_AFL_AF5_POSE) + +#define GPIO_AFL_AF4_POSS 16U +#define GPIO_AFL_AF4_POSE 19U +#define GPIO_AFL_AF4_MSK BITS(GPIO_AFL_AF4_POSS,GPIO_AFL_AF4_POSE) + +#define GPIO_AFL_AF3_POSS 12U +#define GPIO_AFL_AF3_POSE 15U +#define GPIO_AFL_AF3_MSK BITS(GPIO_AFL_AF3_POSS,GPIO_AFL_AF3_POSE) + +#define GPIO_AFL_AF2_POSS 8U +#define GPIO_AFL_AF2_POSE 11U +#define GPIO_AFL_AF2_MSK BITS(GPIO_AFL_AF2_POSS,GPIO_AFL_AF2_POSE) + +#define GPIO_AFL_AF1_POSS 4U +#define GPIO_AFL_AF1_POSE 7U +#define GPIO_AFL_AF1_MSK BITS(GPIO_AFL_AF1_POSS,GPIO_AFL_AF1_POSE) + +#define GPIO_AFL_AF0_POSS 0U +#define GPIO_AFL_AF0_POSE 3U +#define GPIO_AFL_AF0_MSK BITS(GPIO_AFL_AF0_POSS,GPIO_AFL_AF0_POSE) + +/****************** Bit definition for GPIO_AFH register ************************/ + +#define GPIO_AFH_AF15_POSS 28U +#define GPIO_AFH_AF15_POSE 31U +#define GPIO_AFH_AF15_MSK BITS(GPIO_AFH_AF15_POSS,GPIO_AFH_AF15_POSE) + +#define GPIO_AFH_AF14_POSS 24U +#define GPIO_AFH_AF14_POSE 27U +#define GPIO_AFH_AF14_MSK BITS(GPIO_AFH_AF14_POSS,GPIO_AFH_AF14_POSE) + +#define GPIO_AFH_AF13_POSS 20U +#define GPIO_AFH_AF13_POSE 23U +#define GPIO_AFH_AF13_MSK BITS(GPIO_AFH_AF13_POSS,GPIO_AFH_AF13_POSE) + +#define GPIO_AFH_AF12_POSS 16U +#define GPIO_AFH_AF12_POSE 19U +#define GPIO_AFH_AF12_MSK BITS(GPIO_AFH_AF12_POSS,GPIO_AFH_AF12_POSE) + +#define GPIO_AFH_AF11_POSS 12U +#define GPIO_AFH_AF11_POSE 15U +#define GPIO_AFH_AF11_MSK BITS(GPIO_AFH_AF11_POSS,GPIO_AFH_AF11_POSE) + +#define GPIO_AFH_AF10_POSS 8U +#define GPIO_AFH_AF10_POSE 11U +#define GPIO_AFH_AF10_MSK BITS(GPIO_AFH_AF10_POSS,GPIO_AFH_AF10_POSE) + +#define GPIO_AFH_AF9_POSS 4U +#define GPIO_AFH_AF9_POSE 7U +#define GPIO_AFH_AF9_MSK BITS(GPIO_AFH_AF9_POSS,GPIO_AFH_AF9_POSE) + +#define GPIO_AFH_AF8_POSS 0U +#define GPIO_AFH_AF8_POSE 3U +#define GPIO_AFH_AF8_MSK BITS(GPIO_AFH_AF8_POSS,GPIO_AFH_AF8_POSE) + +typedef struct +{ + __I uint32_t IDATA; + __IO uint32_t ODATA; + __O uint32_t BSBR; + __IO uint32_t LCK; + __IO uint32_t MOD; + __IO uint32_t PUD; + __IO uint32_t OT; + __IO uint32_t DS; + __IO uint32_t FIR; + __IO uint32_t IST; + __IO uint32_t AFL; + __IO uint32_t AFH; +} GPIO_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h new file mode 100644 index 0000000000000000000000000000000000000000..d1ffd0d102ecff98692b9b2f6a9ad493c35896eb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h @@ -0,0 +1,75 @@ +/** + ************************************************************************************** + * @file REG_HDIV.h + * @brief HDIV Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __hdiv_H__ +#define __hdiv_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for HDIV_DIVDR register ************************/ + +#define HDIV_DIVDR_DIVS_POSS 0U +#define HDIV_DIVDR_DIVS_POSE 31U +#define HDIV_DIVDR_DIVD_MSK BITS(HDIV_DIVDR_DIVD_POSS,HDIV_DIVDR_DIVD_POSE) + +/****************** Bit definition for HDIV_DIVSR register ************************/ + +#define HDIV_DIVSR_DIVS_POSS 0U +#define HDIV_DIVSR_DIVS_POSE 31U +#define HDIV_DIVSR_DIVS_MSK BITS(HDIV_DIVSR_DIVS_POSS,HDIV_DIVSR_DIVS_POSE) + +/****************** Bit definition for HDIV_DIVQR register ************************/ + +#define HDIV_DIVQR_DIVQ_POSS 0U +#define HDIV_DIVQR_DIVQ_POSE 31U +#define HDIV_DIVQR_DIVQ_MSK BITS(HDIV_DIVQR_DIVQ_POSS,HDIV_DIVQR_DIVQ_POSE) + +/****************** Bit definition for HDIV_DIVRR register ************************/ + +#define HDIV_DIVRR_DIVR_POSS 0U +#define HDIV_DIVRR_DIVR_POSE 31U +#define HDIV_DIVRR_DIVR_MSK BITS(HDIV_DIVRR_DIVR_POSS,HDIV_DIVRR_DIVR_POSE) + +/****************** Bit definition for HDIV_DIVSTAT register ************************/ + +#define HDIV_DIVSTAT_SIGN_POS 2U +#define HDIV_DIVSTAT_SIGN_MSK BIT(HDIV_DIVSTAT_SIGN_POS) + +#define HDIV_DIVSTAT_DIV0_POS 1U +#define HDIV_DIVSTAT_DIV0_MSK BIT(HDIV_DIVSTAT_DIV0_POS) + +#define HDIV_DIVSTAT_BUSY_POS 0U +#define HDIV_DIVSTAT_BUSY_MSK BIT(HDIV_DIVSTAT_BUSY_POS) + +typedef struct +{ + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __I uint32_t DIVSTAT; +} HDIV_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..887eb01e0363751a70792031988f9c99770a1bb0 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h @@ -0,0 +1,623 @@ +/** + ************************************************************************************** + * @file REG_I2C.h + * @brief I2C Head File + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_PECEN_POS 23U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ALERTEN_POS 22U +#define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) + +#define I2C_CON1_SMBDEN_POS 21U +#define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) + +#define I2C_CON1_SMBHEN_POS 20U +#define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) + +#define I2C_CON1_GCEN_POS 19U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_NOSTRETCH_POS 17U +#define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) + +#define I2C_CON1_SBC_POS 16U +#define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) + +#define I2C_CON1_RXDMAEN_POS 15U +#define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) + +#define I2C_CON1_TXDMAEN_POS 14U +#define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) + +#define I2C_CON1_DNF_POSS 8U +#define I2C_CON1_DNF_POSE 11U +#define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS,I2C_CON1_DNF_POSE) + +#define I2C_CON1_PE_POS 0U +#define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_ACK_UPD_POS 29U +#define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) + +#define I2C_CON2_HOLDACK_POS 28U +#define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) + +#define I2C_CON2_PECBYTE_POS 26U +#define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) + +#define I2C_CON2_AUTOEND_POS 25U +#define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) + +#define I2C_CON2_RELOAD_POS 24U +#define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) + +#define I2C_CON2_NBYTES_POSS 16U +#define I2C_CON2_NBYTES_POSE 23U +#define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS,I2C_CON2_NBYTES_POSE) + +#define I2C_CON2_NACK_POS 15U +#define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) + +#define I2C_CON2_STOP_POS 14U +#define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) + +#define I2C_CON2_START_POS 13U +#define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) + +#define I2C_CON2_HEAD10R_POS 12U +#define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) + +#define I2C_CON2_ADD10_POS 11U +#define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) + +#define I2C_CON2_RD_WRN_POS 10U +#define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) + +#define I2C_CON2_SADD_POSS 0U +#define I2C_CON2_SADD_POSE 9U +#define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS,I2C_CON2_SADD_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_OA1EN_POS 15U +#define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) + +#define I2C_ADDR1_OA1MODE_POS 10U +#define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) + +#define I2C_ADDR1_OA1_POSS 0U +#define I2C_ADDR1_OA1_POSE 9U +#define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS,I2C_ADDR1_OA1_POSE) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_OA2EN_POS 15U +#define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) + +#define I2C_ADDR2_OA2MSK_POSS 8U +#define I2C_ADDR2_OA2MSK_POSE 10U +#define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS,I2C_ADDR2_OA2MSK_POSE) + +#define I2C_ADDR2_OA2_POSS 1U +#define I2C_ADDR2_OA2_POSE 7U +#define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS,I2C_ADDR2_OA2_POSE) + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +#define I2C_TIMINGR_PRESC_POSS 28U +#define I2C_TIMINGR_PRESC_POSE 31U +#define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS,I2C_TIMINGR_PRESC_POSE) + +#define I2C_TIMINGR_SCLDEL_POSS 20U +#define I2C_TIMINGR_SCLDEL_POSE 23U +#define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS,I2C_TIMINGR_SCLDEL_POSE) + +#define I2C_TIMINGR_SDADEL_POSS 16U +#define I2C_TIMINGR_SDADEL_POSE 19U +#define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS,I2C_TIMINGR_SDADEL_POSE) + +#define I2C_TIMINGR_SCLH_POSS 8U +#define I2C_TIMINGR_SCLH_POSE 15U +#define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS,I2C_TIMINGR_SCLH_POSE) + +#define I2C_TIMINGR_SCLL_POSS 0U +#define I2C_TIMINGR_SCLL_POSE 7U +#define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS,I2C_TIMINGR_SCLL_POSE) + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +#define I2C_TIMEOUTR_TEXTEN_POS 31U +#define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) + +#define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +#define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +#define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS,I2C_TIMEOUTR_TIMEOUTB_POSE) + +#define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +#define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) + +#define I2C_TIMEOUTR_TIDLE_POS 12U +#define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) + +#define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +#define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +#define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS,I2C_TIMEOUTR_TIMEOUTA_POSE) + +/****************** Bit definition for I2C_STAT register ************************/ + +#define I2C_STAT_ADDCODE_POSS 17U +#define I2C_STAT_ADDCODE_POSE 23U +#define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS,I2C_STAT_ADDCODE_POSE) + +#define I2C_STAT_DIR_POS 16U +#define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) + +#define I2C_STAT_BUSY_POS 15U +#define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) + +#define I2C_STAT_TCR_POS 11U +#define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) + +#define I2C_STAT_TC_POS 10U +#define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) + +#define I2C_STAT_RXTH_POS 9U +#define I2C_STAT_RXTH_MSK BIT(I2C_STAT_RXTH_POS) + +#define I2C_STAT_RXUD_POS 8U +#define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) + +#define I2C_STAT_RXOV_POS 7U +#define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) + +#define I2C_STAT_RXF_POS 6U +#define I2C_STAT_RXF_MSK BIT(I2C_STAT_RXF_POS) + +#define I2C_STAT_RXE_POS 5U +#define I2C_STAT_RXE_MSK BIT(I2C_STAT_RXE_POS) + +#define I2C_STAT_TXTH_POS 4U +#define I2C_STAT_TXTH_MSK BIT(I2C_STAT_TXTH_POS) + +#define I2C_STAT_TXUD_POS 3U +#define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) + +#define I2C_STAT_TXOV_POS 2U +#define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) + +#define I2C_STAT_TXF_POS 1U +#define I2C_STAT_TXF_MSK BIT(I2C_STAT_TXF_POS) + +#define I2C_STAT_TXE_POS 0U +#define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) + +/****************** Bit definition for I2C_FCON register ************************/ + +#define I2C_FCON_RXFTH_POSS 14U +#define I2C_FCON_RXFTH_POSE 15U +#define I2C_FCON_RXFTH_MSK BITS(I2C_FCON_RXFTH_POSS,I2C_FCON_RXFTH_POSE) + +#define I2C_FCON_RXFRST_POS 13U +#define I2C_FCON_RXFRST_MSK BIT(I2C_FCON_RXFRST_POS) + +#define I2C_FCON_RXFLV_POSS 8U +#define I2C_FCON_RXFLV_POSE 12U +#define I2C_FCON_RXFLV_MSK BITS(I2C_FCON_RXFLV_POSS,I2C_FCON_RXFLV_POSE) + +#define I2C_FCON_TXFTH_POSS 6U +#define I2C_FCON_TXFTH_POSE 7U +#define I2C_FCON_TXFTH_MSK BITS(I2C_FCON_TXFTH_POSS,I2C_FCON_TXFTH_POSE) + +#define I2C_FCON_TXFRST_POS 5U +#define I2C_FCON_TXFRST_MSK BIT(I2C_FCON_TXFRST_POS) + +#define I2C_FCON_TXFLV_POSS 0U +#define I2C_FCON_TXFLV_POSE 4U +#define I2C_FCON_TXFLV_MSK BITS(I2C_FCON_TXFLV_POSS,I2C_FCON_TXFLV_POSE) + +/****************** Bit definition for I2C_PECR register ************************/ + +#define I2C_PECR_PEC_POSS 0U +#define I2C_PECR_PEC_POSE 7U +#define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS,I2C_PECR_PEC_POSE) + +/****************** Bit definition for I2C_RXDATA register ************************/ + +#define I2C_RXDATA_RXDATA_POSS 0U +#define I2C_RXDATA_RXDATA_POSE 7U +#define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS,I2C_RXDATA_RXDATA_POSE) + +/****************** Bit definition for I2C_TXDATA register ************************/ + +#define I2C_TXDATA_TXDATA_POSS 0U +#define I2C_TXDATA_TXDATA_POSE 7U +#define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS,I2C_TXDATA_TXDATA_POSE) + +/****************** Bit definition for I2C_IER register ************************/ + +#define I2C_IER_ALERTIE_POS 20U +#define I2C_IER_ALERTIE_MSK BIT(I2C_IER_ALERTIE_POS) + +#define I2C_IER_TOUTIE_POS 19U +#define I2C_IER_TOUTIE_MSK BIT(I2C_IER_TOUTIE_POS) + +#define I2C_IER_PECEIE_POS 18U +#define I2C_IER_PECEIE_MSK BIT(I2C_IER_PECEIE_POS) + +#define I2C_IER_ARLOIE_POS 17U +#define I2C_IER_ARLOIE_MSK BIT(I2C_IER_ARLOIE_POS) + +#define I2C_IER_BERRIE_POS 16U +#define I2C_IER_BERRIE_MSK BIT(I2C_IER_BERRIE_POS) + +#define I2C_IER_STOPIE_POS 14U +#define I2C_IER_STOPIE_MSK BIT(I2C_IER_STOPIE_POS) + +#define I2C_IER_NACKIE_POS 13U +#define I2C_IER_NACKIE_MSK BIT(I2C_IER_NACKIE_POS) + +#define I2C_IER_ADDRIE_POS 12U +#define I2C_IER_ADDRIE_MSK BIT(I2C_IER_ADDRIE_POS) + +#define I2C_IER_TCRIE_POS 11U +#define I2C_IER_TCRIE_MSK BIT(I2C_IER_TCRIE_POS) + +#define I2C_IER_TCIE_POS 10U +#define I2C_IER_TCIE_MSK BIT(I2C_IER_TCIE_POS) + +#define I2C_IER_RXTHIE_POS 9U +#define I2C_IER_RXTHIE_MSK BIT(I2C_IER_RXTHIE_POS) + +#define I2C_IER_RXUDIE_POS 8U +#define I2C_IER_RXUDIE_MSK BIT(I2C_IER_RXUDIE_POS) + +#define I2C_IER_RXOVIE_POS 7U +#define I2C_IER_RXOVIE_MSK BIT(I2C_IER_RXOVIE_POS) + +#define I2C_IER_RXFIE_POS 6U +#define I2C_IER_RXFIE_MSK BIT(I2C_IER_RXFIE_POS) + +#define I2C_IER_TXTHIE_POS 4U +#define I2C_IER_TXTHIE_MSK BIT(I2C_IER_TXTHIE_POS) + +#define I2C_IER_TXUDIE_POS 3U +#define I2C_IER_TXUDIE_MSK BIT(I2C_IER_TXUDIE_POS) + +#define I2C_IER_TXOVIE_POS 2U +#define I2C_IER_TXOVIE_MSK BIT(I2C_IER_TXOVIE_POS) + +#define I2C_IER_TXEIE_POS 0U +#define I2C_IER_TXEIE_MSK BIT(I2C_IER_TXEIE_POS) + +/****************** Bit definition for I2C_IDR register ************************/ + +#define I2C_IDR_ALERTID_POS 20U +#define I2C_IDR_ALERTID_MSK BIT(I2C_IDR_ALERTID_POS) + +#define I2C_IDR_TOUTID_POS 19U +#define I2C_IDR_TOUTID_MSK BIT(I2C_IDR_TOUTID_POS) + +#define I2C_IDR_PECEID_POS 18U +#define I2C_IDR_PECEID_MSK BIT(I2C_IDR_PECEID_POS) + +#define I2C_IDR_ARLOID_POS 17U +#define I2C_IDR_ARLOID_MSK BIT(I2C_IDR_ARLOID_POS) + +#define I2C_IDR_BERRID_POS 16U +#define I2C_IDR_BERRID_MSK BIT(I2C_IDR_BERRID_POS) + +#define I2C_IDR_STOPID_POS 14U +#define I2C_IDR_STOPID_MSK BIT(I2C_IDR_STOPID_POS) + +#define I2C_IDR_NACKID_POS 13U +#define I2C_IDR_NACKID_MSK BIT(I2C_IDR_NACKID_POS) + +#define I2C_IDR_ADDRID_POS 12U +#define I2C_IDR_ADDRID_MSK BIT(I2C_IDR_ADDRID_POS) + +#define I2C_IDR_TCRID_POS 11U +#define I2C_IDR_TCRID_MSK BIT(I2C_IDR_TCRID_POS) + +#define I2C_IDR_TCID_POS 10U +#define I2C_IDR_TCID_MSK BIT(I2C_IDR_TCID_POS) + +#define I2C_IDR_RXTHID_POS 9U +#define I2C_IDR_RXTHID_MSK BIT(I2C_IDR_RXTHID_POS) + +#define I2C_IDR_RXUDID_POS 8U +#define I2C_IDR_RXUDID_MSK BIT(I2C_IDR_RXUDID_POS) + +#define I2C_IDR_RXOVID_POS 7U +#define I2C_IDR_RXOVID_MSK BIT(I2C_IDR_RXOVID_POS) + +#define I2C_IDR_RXFID_POS 6U +#define I2C_IDR_RXFID_MSK BIT(I2C_IDR_RXFID_POS) + +#define I2C_IDR_TXTHID_POS 4U +#define I2C_IDR_TXTHID_MSK BIT(I2C_IDR_TXTHID_POS) + +#define I2C_IDR_TXUDID_POS 3U +#define I2C_IDR_TXUDID_MSK BIT(I2C_IDR_TXUDID_POS) + +#define I2C_IDR_TXOVID_POS 2U +#define I2C_IDR_TXOVID_MSK BIT(I2C_IDR_TXOVID_POS) + +#define I2C_IDR_TXEID_POS 0U +#define I2C_IDR_TXEID_MSK BIT(I2C_IDR_TXEID_POS) + +/****************** Bit definition for I2C_IVS register ************************/ + +#define I2C_IVS_ALERTIV_POS 20U +#define I2C_IVS_ALERTIV_MSK BIT(I2C_IVS_ALERTIV_POS) + +#define I2C_IVS_TOUTIV_POS 19U +#define I2C_IVS_TOUTIV_MSK BIT(I2C_IVS_TOUTIV_POS) + +#define I2C_IVS_PECEIV_POS 18U +#define I2C_IVS_PECEIV_MSK BIT(I2C_IVS_PECEIV_POS) + +#define I2C_IVS_ARLOIV_POS 17U +#define I2C_IVS_ARLOIV_MSK BIT(I2C_IVS_ARLOIV_POS) + +#define I2C_IVS_BERRIV_POS 16U +#define I2C_IVS_BERRIV_MSK BIT(I2C_IVS_BERRIV_POS) + +#define I2C_IVS_STOPIV_POS 14U +#define I2C_IVS_STOPIV_MSK BIT(I2C_IVS_STOPIV_POS) + +#define I2C_IVS_NACKIV_POS 13U +#define I2C_IVS_NACKIV_MSK BIT(I2C_IVS_NACKIV_POS) + +#define I2C_IVS_ADDRIV_POS 12U +#define I2C_IVS_ADDRIV_MSK BIT(I2C_IVS_ADDRIV_POS) + +#define I2C_IVS_TCRIV_POS 11U +#define I2C_IVS_TCRIV_MSK BIT(I2C_IVS_TCRIV_POS) + +#define I2C_IVS_TCIV_POS 10U +#define I2C_IVS_TCIV_MSK BIT(I2C_IVS_TCIV_POS) + +#define I2C_IVS_RXTHIV_POS 9U +#define I2C_IVS_RXTHIV_MSK BIT(I2C_IVS_RXTHIV_POS) + +#define I2C_IVS_RXUDIV_POS 8U +#define I2C_IVS_RXUDIV_MSK BIT(I2C_IVS_RXUDIV_POS) + +#define I2C_IVS_RXOVIV_POS 7U +#define I2C_IVS_RXOVIV_MSK BIT(I2C_IVS_RXOVIV_POS) + +#define I2C_IVS_RXFIV_POS 6U +#define I2C_IVS_RXFIV_MSK BIT(I2C_IVS_RXFIV_POS) + +#define I2C_IVS_TXTHIV_POS 4U +#define I2C_IVS_TXTHIV_MSK BIT(I2C_IVS_TXTHIV_POS) + +#define I2C_IVS_TXUDIV_POS 3U +#define I2C_IVS_TXUDIV_MSK BIT(I2C_IVS_TXUDIV_POS) + +#define I2C_IVS_TXOVIV_POS 2U +#define I2C_IVS_TXOVIV_MSK BIT(I2C_IVS_TXOVIV_POS) + +#define I2C_IVS_TXEIV_POS 0U +#define I2C_IVS_TXEIV_MSK BIT(I2C_IVS_TXEIV_POS) + +/****************** Bit definition for I2C_RIF register ************************/ + +#define I2C_RIF_ALERTRI_POS 20U +#define I2C_RIF_ALERTRI_MSK BIT(I2C_RIF_ALERTRI_POS) + +#define I2C_RIF_TOUTRI_POS 19U +#define I2C_RIF_TOUTRI_MSK BIT(I2C_RIF_TOUTRI_POS) + +#define I2C_RIF_PECERI_POS 18U +#define I2C_RIF_PECERI_MSK BIT(I2C_RIF_PECERI_POS) + +#define I2C_RIF_ARLORI_POS 17U +#define I2C_RIF_ARLORI_MSK BIT(I2C_RIF_ARLORI_POS) + +#define I2C_RIF_BERRRI_POS 16U +#define I2C_RIF_BERRRI_MSK BIT(I2C_RIF_BERRRI_POS) + +#define I2C_RIF_STOPRI_POS 14U +#define I2C_RIF_STOPRI_MSK BIT(I2C_RIF_STOPRI_POS) + +#define I2C_RIF_NACKRI_POS 13U +#define I2C_RIF_NACKRI_MSK BIT(I2C_RIF_NACKRI_POS) + +#define I2C_RIF_ADDRRI_POS 12U +#define I2C_RIF_ADDRRI_MSK BIT(I2C_RIF_ADDRRI_POS) + +#define I2C_RIF_TCRRI_POS 11U +#define I2C_RIF_TCRRI_MSK BIT(I2C_RIF_TCRRI_POS) + +#define I2C_RIF_TCRI_POS 10U +#define I2C_RIF_TCRI_MSK BIT(I2C_RIF_TCRI_POS) + +#define I2C_RIF_RXTHRI_POS 9U +#define I2C_RIF_RXTHRI_MSK BIT(I2C_RIF_RXTHRI_POS) + +#define I2C_RIF_RXUDRI_POS 8U +#define I2C_RIF_RXUDRI_MSK BIT(I2C_RIF_RXUDRI_POS) + +#define I2C_RIF_RXOVRI_POS 7U +#define I2C_RIF_RXOVRI_MSK BIT(I2C_RIF_RXOVRI_POS) + +#define I2C_RIF_RXFRI_POS 6U +#define I2C_RIF_RXFRI_MSK BIT(I2C_RIF_RXFRI_POS) + +#define I2C_RIF_TXTHRI_POS 4U +#define I2C_RIF_TXTHRI_MSK BIT(I2C_RIF_TXTHRI_POS) + +#define I2C_RIF_TXUDRI_POS 3U +#define I2C_RIF_TXUDRI_MSK BIT(I2C_RIF_TXUDRI_POS) + +#define I2C_RIF_TXOVRI_POS 2U +#define I2C_RIF_TXOVRI_MSK BIT(I2C_RIF_TXOVRI_POS) + +#define I2C_RIF_TXERI_POS 0U +#define I2C_RIF_TXERI_MSK BIT(I2C_RIF_TXERI_POS) + +/****************** Bit definition for I2C_IFM register ************************/ + +#define I2C_IFM_ALERTFM_POS 20U +#define I2C_IFM_ALERTFM_MSK BIT(I2C_IFM_ALERTFM_POS) + +#define I2C_IFM_TOUTFM_POS 19U +#define I2C_IFM_TOUTFM_MSK BIT(I2C_IFM_TOUTFM_POS) + +#define I2C_IFM_PECEFM_POS 18U +#define I2C_IFM_PECEFM_MSK BIT(I2C_IFM_PECEFM_POS) + +#define I2C_IFM_ARLOFM_POS 17U +#define I2C_IFM_ARLOFM_MSK BIT(I2C_IFM_ARLOFM_POS) + +#define I2C_IFM_BERRFM_POS 16U +#define I2C_IFM_BERRFM_MSK BIT(I2C_IFM_BERRFM_POS) + +#define I2C_IFM_STOPFM_POS 14U +#define I2C_IFM_STOPFM_MSK BIT(I2C_IFM_STOPFM_POS) + +#define I2C_IFM_NACKFM_POS 13U +#define I2C_IFM_NACKFM_MSK BIT(I2C_IFM_NACKFM_POS) + +#define I2C_IFM_ADDRFM_POS 12U +#define I2C_IFM_ADDRFM_MSK BIT(I2C_IFM_ADDRFM_POS) + +#define I2C_IFM_TCRFM_POS 11U +#define I2C_IFM_TCRFM_MSK BIT(I2C_IFM_TCRFM_POS) + +#define I2C_IFM_TCFM_POS 10U +#define I2C_IFM_TCFM_MSK BIT(I2C_IFM_TCFM_POS) + +#define I2C_IFM_RXTHFM_POS 9U +#define I2C_IFM_RXTHFM_MSK BIT(I2C_IFM_RXTHFM_POS) + +#define I2C_IFM_RXUDFM_POS 8U +#define I2C_IFM_RXUDFM_MSK BIT(I2C_IFM_RXUDFM_POS) + +#define I2C_IFM_RXOVFM_POS 7U +#define I2C_IFM_RXOVFM_MSK BIT(I2C_IFM_RXOVFM_POS) + +#define I2C_IFM_RXFFM_POS 6U +#define I2C_IFM_RXFFM_MSK BIT(I2C_IFM_RXFFM_POS) + +#define I2C_IFM_TXTHFM_POS 4U +#define I2C_IFM_TXTHFM_MSK BIT(I2C_IFM_TXTHFM_POS) + +#define I2C_IFM_TXUDFM_POS 3U +#define I2C_IFM_TXUDFM_MSK BIT(I2C_IFM_TXUDFM_POS) + +#define I2C_IFM_TXOVFM_POS 2U +#define I2C_IFM_TXOVFM_MSK BIT(I2C_IFM_TXOVFM_POS) + +#define I2C_IFM_TXEFM_POS 0U +#define I2C_IFM_TXEFM_MSK BIT(I2C_IFM_TXEFM_POS) + +/****************** Bit definition for I2C_ICR register ************************/ + +#define I2C_ICR_ALERTIC_POS 20U +#define I2C_ICR_ALERTIC_MSK BIT(I2C_ICR_ALERTIC_POS) + +#define I2C_ICR_TOUTIC_POS 19U +#define I2C_ICR_TOUTIC_MSK BIT(I2C_ICR_TOUTIC_POS) + +#define I2C_ICR_PECEIC_POS 18U +#define I2C_ICR_PECEIC_MSK BIT(I2C_ICR_PECEIC_POS) + +#define I2C_ICR_ARLOIC_POS 17U +#define I2C_ICR_ARLOIC_MSK BIT(I2C_ICR_ARLOIC_POS) + +#define I2C_ICR_BERRIC_POS 16U +#define I2C_ICR_BERRIC_MSK BIT(I2C_ICR_BERRIC_POS) + +#define I2C_ICR_STOPIC_POS 14U +#define I2C_ICR_STOPIC_MSK BIT(I2C_ICR_STOPIC_POS) + +#define I2C_ICR_NACKIC_POS 13U +#define I2C_ICR_NACKIC_MSK BIT(I2C_ICR_NACKIC_POS) + +#define I2C_ICR_ADDRIC_POS 12U +#define I2C_ICR_ADDRIC_MSK BIT(I2C_ICR_ADDRIC_POS) + +#define I2C_ICR_TCRIC_POS 11U +#define I2C_ICR_TCRIC_MSK BIT(I2C_ICR_TCRIC_POS) + +#define I2C_ICR_TCIC_POS 10U +#define I2C_ICR_TCIC_MSK BIT(I2C_ICR_TCIC_POS) + +#define I2C_ICR_RXTHIC_POS 9U +#define I2C_ICR_RXTHIC_MSK BIT(I2C_ICR_RXTHIC_POS) + +#define I2C_ICR_RXUDIC_POS 8U +#define I2C_ICR_RXUDIC_MSK BIT(I2C_ICR_RXUDIC_POS) + +#define I2C_ICR_RXOVIC_POS 7U +#define I2C_ICR_RXOVIC_MSK BIT(I2C_ICR_RXOVIC_POS) + +#define I2C_ICR_RXFIC_POS 6U +#define I2C_ICR_RXFIC_MSK BIT(I2C_ICR_RXFIC_POS) + +#define I2C_ICR_TXTHIC_POS 4U +#define I2C_ICR_TXTHIC_MSK BIT(I2C_ICR_TXTHIC_POS) + +#define I2C_ICR_TXUDIC_POS 3U +#define I2C_ICR_TXUDIC_MSK BIT(I2C_ICR_TXUDIC_POS) + +#define I2C_ICR_TXOVIC_POS 2U +#define I2C_ICR_TXOVIC_MSK BIT(I2C_ICR_TXOVIC_POS) + +#define I2C_ICR_TXEIC_POS 0U +#define I2C_ICR_TXEIC_MSK BIT(I2C_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __I uint32_t STAT; + __IO uint32_t FCON; + __I uint32_t PECR; + __I uint32_t RXDATA; + __O uint32_t TXDATA; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} I2C_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..a5c657c89a200c9a6ab8be6ae356e261aefe558b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h @@ -0,0 +1,73 @@ +/** + ************************************************************************************** + * @file reg_IWDG.h + * @brief IWDG Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __IWDG_H__ +#define __IWDG_H__ + +typedef struct +{ + __O uint32_t KR ; /* 0x00 IWDG_KR - Key register */ + __IO uint32_t PR ; /* 0x04 IWDG_PR - Prescaler register */ + __IO uint32_t RLR ; /* 0x08 IWDG_RLR - Reload register */ + __I uint32_t FR ; /* 0x0C IWDG_SR - Status register */ + __IO uint32_t WINR; /* 0x10 IWDG_WINR - Window register */ +} IWDG_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for IWDG_KR register ************************/ + +#define IWDG_KR_KEY_POSS 0U +#define IWDG_KR_KEY_POSE 15U +#define IWDG_KR_KEY_MSK BITS(IWDG_KR_KEY_POSS,IWDG_KR_KEY_POSE) + +/****************** Bit definition for IWDG_PR register ************************/ + +#define IWDG_PR_PR_POSS 0U +#define IWDG_PR_PR_POSE 2U +#define IWDG_PR_PR_MSK BITS(IWDG_PR_PR_POSS,IWDG_PR_PR_POSE) + +/****************** Bit definition for IWDG_RLR register ************************/ + +#define IWDG_RLR_RL_POSS 0U +#define IWDG_RLR_RL_POSE 12U +#define IWDG_RLR_RL_MSK BITS(IWDG_RLR_RL_POSS,IWDG_RLR_RL_POSE) + +/****************** Bit definition for IWDG_FR register ************************/ + +#define IWDG_FR_BUSY_POS 15U +#define IWDG_FR_BUSY_MSK BIT(IWDG_FR_BUSY_POS) + +#define IWDG_FR_STR_POS 12U +#define IWDG_FR_STR_MSK BIT(IWDG_FR_STR_POS) + +#define IWDG_FR_CNT_POSS 0U +#define IWDG_FR_CNT_POSE 11U +#define IWDG_FR_CNT_MSK BITS(IWDG_FR_CNT_POSS,IWDG_FR_CNT_POSE) + +/****************** Bit definition for IWDG_WINR register ************************/ + +#define IWDG_WINR_WIN_POSS 0U +#define IWDG_WINR_WIN_POSE 31U +#define IWDG_WINR_WIN_MSK BITS(IWDG_WINR_WIN_POSS,IWDG_WINR_WIN_POSE) + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h new file mode 100644 index 0000000000000000000000000000000000000000..ebb675dafe20efdc33ca6bb903ee45352c59c7f3 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h @@ -0,0 +1,211 @@ +/** + ************************************************************************************** + * @file reg_MCM.h + * @brief MCM Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __MCM_H__ +#define __MCM_H__ + +typedef struct +{ + __IO uint32_t RAMP_INI; // 0x00 MCM Ramp Generator Initialization Register + __IO uint32_t RAMP_IDATA; // 0x04 MCM Ramp Generator Initial Data Register + __IO uint32_t RAMP_DIV; // 0x08 MCM Ramp Clock Divider Register + __IO uint32_t RAMP_SCALE; // 0x0C MCM Ramp Generator Output Scale Register + __IO uint32_t RAMP_STEP; // 0x10 MCM Step Increment of the Ramp Output Register + __IO uint32_t RAMP_SET; // 0x14 MCM Ramp Generator Reference Data Register + __IO uint32_t RAMP_EN; // 0x18 MCM Ramp Generator Enable Register + __I uint32_t RAMP_DO; // 0x1C MCM Ramp Generator Output Register + __IO uint32_t RMAP_CON; // 0x20 MCM Connect Ramp Generator to PI control Register + __IO uint32_t IX_UPD; // 0x24 MCM Inverse Transform Update Register + __IO uint32_t IX_VQ; // 0x28 MCM Inverse Park Transform Vq Input Register + __IO uint32_t IX_VD; // 0x2C MCM Inverse Park Transform Vd Input Register + __I uint32_t IX_VA; // 0x30 MCM Inverse Clarke Transform Va Output Register + __I uint32_t IX_VB; // 0x34 MCM Inverse Clarke Transform Vb Output Register + __I uint32_t IX_VC; // 0x38 MCM Inverse Clarke Transform Vc Output Register + __I uint32_t IX_VALPHA; // 0x3C MCM Inverse Clarke Transform Valpha Output Register + __I uint32_t IX_VBETA; // 0x40 MCM Inverse Clarke Transform Vbeta Output Register + __I uint32_t IX_SVMVA; // 0x44 MCM Inverse Clarke Transform SVPWM Va Output Register + __I uint32_t IX_SVMVB; // 0x48 MCM Inverse Clarke Transform SVPWM Vb Output Register + __I uint32_t IX_SVMVC; // 0x4C MCM Inverse Clarke Transform SVPWM Vc Output Register + __I uint32_t IX_DONE; // 0x50 MCM Inverse Transform Processing Status Register + __I uint32_t IX_SDONE; // 0x54 MCM Inverse SVPWM Process Status Register + __IO uint32_t IX_CON; // 0x58 MCM Connect PI Control To The Inverse Transform Register + __IO uint32_t IX_NORMAL; // 0x5C MCM Normal Clarke Inverse Transform Register + __IO uint32_t X_UPD; // 0x60 MCM Transform Function Update Register + __IO uint32_t X_IA; // 0x64 MCM Clarke Transform Ia Input Register + __IO uint32_t X_IB; // 0x68 MCM Clarke Transform Ib Input Register + __IO uint32_t X_IC; // 0x6C MCM Clarke Transform Ic Input Register + __I uint32_t X_IALPHA; // 0x70 MCM Clarke Transform Ialpha Output Register + __I uint32_t X_IBETA; // 0x74 MCM Clarke Transform Ibeta Output Register + __I uint32_t X_ID; // 0x78 MCM Park Transform Id Output Register + __I uint32_t X_IQ; // 0x7C MCM Park Transform Iq Output Register + __I uint32_t X_DONE; // 0x80 MCM Transform Process Status Register + __IO uint32_t X_CON; // 0x84 MCM Forward Transform Input Source Selection Register + uint32_t REV88; // 0x88 RESERVED + __IO uint32_t PI0_UPD; // 0x8C MCM PI Control 0 Update Register + __IO uint32_t PI0_INI; // 0x90 MCM Initialize PI Control 0 Register + __IO uint32_t PI0_IDATA; // 0x94 MCM PI Control 0 Initial Data Register + __IO uint32_t PI0_ELIMIT; // 0x98 MCM PI Control 0 Error Limit Register + __IO uint32_t PI0_KP; // 0x9C MCM PI Control 0 Kp Coefficient Register + __IO uint32_t PI0_KI; // 0xA0 MCM PI Control 0 Ki Coefficient Register + __IO uint32_t PI0_REF; // 0xA4 MCM PI Control 0 Reference Value Register + __IO uint32_t PI0_ACTUAL; // 0xA8 MCM PI Control 0 Actual Value Register + __IO uint32_t PI0_MIN; // 0xAC MCM PI Control 0 Minimum Output Register + __IO uint32_t PI0_MAX; // 0xB0 MCM PI Control 0 Maximum Output Register + __I uint32_t PI0_DO; // 0xB4 MCM PI Control 0 Data Out Register + __IO uint32_t PI0_OSCALE; // 0xB8 MCM PI Control 0 Data Output Scale Register + __I uint32_t PI_DONE; // 0xBC MCM PI Control Processing Status Register + __IO uint32_t PI1_UPD; // 0xC0 MCM PI Control 1 Update Register + __IO uint32_t PI1_INI; // 0xC4 MCM Initialize PI Control 1 Register + __IO uint32_t PI1_IDATA; // 0xC8 MCM PI Control 1 Initial Data Register + __IO uint32_t PI1_ELIMIT; // 0xCC MCM PI Control 1 Error Limit Register + __IO uint32_t PI1_KP; // 0xD0 MCM PI Control 1 Kp Coefficient Register + __IO uint32_t PI1_KI; // 0xD4 MCM PI Control 1 Ki Coefficient Register + __IO uint32_t PI1_REF; // 0xD8 MCM PI Control 1 Reference Value Register + __IO uint32_t PI1_ACTUAL; // 0xDC MCM PI Control 1 Actual Value Register + __IO uint32_t PI1_MIN; // 0xE0 MCM PI Control 1 Minimum Output Register + __IO uint32_t PI1_MAX; // 0xE4 MCM PI Control 1 Maximum Output Register + __I uint32_t PI1_DO; // 0xE8 MCM PI Control 1 Data Out Register + __IO uint32_t PI1_OSCALE; // 0xEC MCM PI Control 1 Data Output Scale Register + __IO uint32_t PI2_UPD; // 0xF0 MCM PI Control 2 Update Register + __IO uint32_t PI2_INI; // 0xF4 MCM Initialize PI Control 2 Register + __IO uint32_t PI2_IDATA; // 0xF8 MCM PI Control 2 Initial Data Register + __IO uint32_t PI2_ELIMIT; // 0xFC MCM PI Control 2 Error Limit Register + __IO uint32_t PI2_KP; // 0x100 MCM PI Control 2 Kp Coefficient Register + __IO uint32_t PI2_KI; // 0x104 MCM PI Control 2 Ki Coefficient Register + __IO uint32_t PI2_REF; // 0x108 MCM PI Control 2 Reference Value Register + __IO uint32_t PI2_ACTUAL; // 0x10C MCM PI Control 2 Actual Value Register + __IO uint32_t PI2_MIN; // 0x110 MCM PI Control 2 Minimum Output Register + __IO uint32_t PI2_MAX; // 0x114 MCM PI Control 2 Maximum Output Register + __I uint32_t PI2_DO; // 0x118 MCM PI Control 2 Data Out Register + __IO uint32_t PI2_OSCALE; // 0x11C MCM PI Control 2 Data Output Scale Register + __IO uint32_t COR_START; // 0x120 MCM Start CORDIC Calculation Register + __IO uint32_t COR_X; // 0x124 MCM CORDIC X Input Register + __IO uint32_t COR_Y; // 0x128 MCM CORDIC Y Input Register + __I uint32_t COR_RES; // 0x12C MCM CORDIC Result Register + __I uint32_t COR_DONE; // 0x130 MCM CORDIC Processing Status Register + __IO uint32_t COR_CON; // 0x134 MCM CORDIC Input Selection Register + uint32_t REV138; // 0x138 RESERVED + uint32_t REV13C; // 0x13C RESERVED + __IO uint32_t LPFA_INI; // 0x140 MCM LPF A Channel Initialize Register + __IO uint32_t LPFA_UPD; // 0x144 MCM LPF A Channel Update Register + __IO uint32_t LPFA_DIN; // 0x148 MCM LPF A Input Register + __IO uint32_t LPFA_A0; // 0x14C MCM LPF A a0 Coefficient Register + __IO uint32_t LPFA_B0; // 0x150 MCM LPF A b0 Coefficient Register + __IO uint32_t LPFA_B1; // 0x154 MCM LPF A b1 Coefficient Register + + __IO uint32_t LPFA_A0SCALE; // 0x158 MCM LPF A a0 Coefficient Scale Register + __IO uint32_t LPFA_B0SCALE; // 0x15C MCM LPF A b0 Coefficient Scale Register + __IO uint32_t LPFA_B1SCALE; // 0x160 MCM LPF A b1 Coefficient Scale Register + + __I uint32_t LPFA_DO; // 0x164 MCM LPF A Data Output Register + __I uint32_t LPFA_DONE; // 0x168 MCM LPF A Process Status Register + __IO uint32_t LPFB_INI; // 0x16C MCM LPF B Channel Initialize Register + __IO uint32_t LPFB_UPD; // 0x170 MCM LPF B Channel Update Register + __IO uint32_t LPFB_DIN; // 0x174 MCM LPF B Input Register + __IO uint32_t LPFB_A0; // 0x178 MCM LPF B a0 Coefficient Register + __IO uint32_t LPFB_B0; // 0x17C MCM LPF B b0 Coefficient Register + __IO uint32_t LPFB_B1; // 0x180 MCM LPF B b1 Coefficient Register + + __IO uint32_t LPFB_A0SCALE; // 0x184 MCM LPF B a0 Coefficient Scale Register + __IO uint32_t LPFB_B0SCALE; // 0x188 MCM LPF B b0 Coefficient Scale Register + __IO uint32_t LPFB_B1SCALE; // 0x18C MCM LPF B b1 Coefficient Scale Register + + __I uint32_t LPFB_DO; // 0x190 MCM LPF B Data Output Register + __I uint32_t LPFB_DONE; // 0x194 MCM LPF B Process Status Register + __IO uint32_t LPFC_INI; // 0x198 MCM LPF C Channel Initialize Register + __IO uint32_t LPFC_UPD; // 0x19C MCM LPF C Channel Update Register + __IO uint32_t LPFC_DIN; // 0x1A0 MCM LPF C Input Register + __IO uint32_t LPFC_A0; // 0x1A4 MCM LPF C a0 Coefficient Register + __IO uint32_t LPFC_B0; // 0x1A8 MCM LPF C b0 Coefficient Register + __IO uint32_t LPFC_B1; // 0x1AC MCM LPF C b1 Coefficient Register + + __IO uint32_t LPFC_A0SCALE; // 0x1B0 MCM LPF C a0 Coefficient Scale Register + __IO uint32_t LPFC_B0SCALE; // 0x1B4 MCM LPF C b0 Coefficient Scale Register + __IO uint32_t LPFC_B1SCALE; // 0x1B8 MCM LPF C b1 Coefficient Scale Register + + __I uint32_t LPFC_DO; // 0x1BC MCM LPF C Data Output Register + __I uint32_t LPFC_DONE; // 0x1C0 MCM LPF C Process Status Register + __IO uint32_t GL_UPD; // 0x1C4 MCM Global Update Register + __IO uint32_t GL_STAT; // 0x1C8 MCM Global Status Register + __IO uint32_t THETA_SIN; // 0x1CC MCM Sine Angle Register + __IO uint32_t THETA_COS; // 0x1D0 MCM Cosine Angle Register + __IO uint32_t PI_TYPE; // 0x1D4 MCM PI Control Type Register + __IO uint32_t MOTOR_DIR; // 0x1D8 MCM Motor Direction Register + __I uint32_t MCM_VER; // 0x1DC MCM Version Register + __IO uint32_t SMC_UPD; // 0x1E0 MCM Slide Mode Controller Update Register + __IO uint32_t SMC_INI; // 0x1E4 MCM Slide Mode Controller Initialization Register + __IO uint32_t SMC_ALPHAINI; // 0x1E8 MCM Slide Mode Controller Alpha Initial Data Register + __IO uint32_t SMC_BETAINI; // 0x1EC MCM Slide Mode Controller Beta Initial Data Register + __IO uint32_t SMC_A0; // 0x1F0 MCM Slide Mode Controller Dynamic LPF coefficient Register + __IO uint32_t SMC_ELIMIT; // 0x1F4 MCM Slide Mode Controller Error Limit Register + __IO uint32_t SMC_KSLIDE; // 0x1F8 MCM Slide Mode Controller Z Factor Error Amplification Register + __I uint32_t SMC_DONE; // 0x1FC MCM Slide Mode Controller Process Status Register + __IO uint32_t SMC_IEALPHA; // 0x200 MCM SMC Estimated Current Alpha Register + __IO uint32_t SMC_IEBETA; // 0x204 MCM SMC Estimated Current Beta Register + __IO uint32_t SMC_IALPHA; // 0x208 MCM SMC Measured Current Alpha Register + __IO uint32_t SMC_IBETA; // 0x20C MCM SMC Measured Current Beta Register + __IO uint32_t SMC_DISI; // 0x210 MCM SMC Estimated Current Input Selection Register + __I uint32_t SMC_ZALPHA; // 0x214 MCM SMC Z Factor Alpha Register + __I uint32_t SMC_ZBETA; // 0x218 MCM SMC Z Factor Beta Register + __I uint32_t SMC_BEMF1A; // 0x21C MCM SMC Estimated BEMF Alpha Register + __I uint32_t SMC_BEMF1B; // 0x220 MCM SMC Estimated BEMF Beta Register + __I uint32_t SMC_BEMF2A; // 0x224 MCM SMC BEMF Filtered Alpha Register + __I uint32_t SMC_BEMF2B; // 0x228 MCM SMC BEMF Filtered Beta Register + __IO uint32_t SMC_LPFSCALE; // 0x22C MCM SMC LPF Coefficient Scale Factor Register + uint32_t REV230; // 0x230 RESERVED + __IO uint32_t VM_UPD; // 0x234 MCM Virtual Motor Update Register + __IO uint32_t VM_INI; // 0x238 MCM Virtual Motor Initialization Register + __IO uint32_t VM_ALPHAINI; // 0x23C MCM Virtual Motor Initial Data Alpha Register + __IO uint32_t VM_BETAINI; // 0x240 MCM Virtual Motor Initial Data Beta Register + __IO uint32_t VM_KF; // 0x244 MCM Virtual Motor F Constant Register + __IO uint32_t VM_KG; // 0x248 MCM Virtual Motor G Constant Register + __IO uint32_t VM_VALPHA; // 0x24C MCM Virtual Motor Voltage Vector Alpha Register + __IO uint32_t VM_VBETA; // 0x250 MCM Virtual Motor Voltage Vector BETA Register + __IO uint32_t VM_BEMFA; // 0x254 MCM Virtual Motor BEMF Vector Alpha Register + __IO uint32_t VM_BEMFB; // 0x258 MCM Virtual Motor BEMF Vector BETA Register + __IO uint32_t VM_ZALPHA; // 0x25C MCM Virtual Motor Z Vector Alpha Register + __IO uint32_t VM_ZBETA; // 0x260 MCM Virtual Motor Z Vector BETA Register + __IO uint32_t VM_DISZ; // 0x264 MCM Virtual Motor Z Factor Input Selection Register + __I uint32_t VM_DONE; // 0x268 MCM Virtual Motor Process Status Register + __I uint32_t VM_IEALPHA; // 0x26C MCM Virtual Motor Estimated IS Result Alpha Register + __I uint32_t VM_IEBETA; // 0x270 MCM Virtual Motor Estimated IS Result BETA Register + __IO uint32_t VM_CON; // 0x274 MCM Virtual Motor Connect Register + + __IO uint32_t VM_KFSCALE; // 0x278 MCM Virtual Motor F Constant Scale Register + __IO uint32_t VM_KGSCALE; // 0x27C MCM Virtual Motor G Constant Scale Register + __IO uint32_t VM_CONVS; // 0x280 MCM Virtual Motor Voltage Connect Register + + uint32_t REV284; // 0x284 RESERVED + __IO uint32_t SVM_UPD; // 0x288 MCM SVM Update Register + __IO uint32_t SVM_CON; // 0x28C MCM SVM Source Input Select Register + __IO uint32_t SVM_DINA; // 0x290 MCM SVM Phase A Register + __IO uint32_t SVM_DINB; // 0x294 MCM SVM Phase B Register + __IO uint32_t SVM_DINC; // 0x298 MCM SVM Phase C Register +} MCM_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for WWDG_CR register ************************/ + + + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h new file mode 100644 index 0000000000000000000000000000000000000000..3a7d2f5dcf7ae1db494b2e6fb746d1ed20a096b6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h @@ -0,0 +1,58 @@ +/** + ************************************************************************************** + * @file reg_MSWD.h + * @brief WWDG Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __MSWD_H__ +#define __MSWD_H__ + +typedef struct +{ + __IO uint32_t CFG; // 0x00 SW_CFG Serial Wire Configure Register + __IO uint32_t JTAG2SWD; // 0x04 SW_JTAG2SW Serial Wire JTAG2SWD Register + __IO uint32_t LINERESET; // 0x08 SW_LINERESET Serial Wire LINERESET Resister + __O uint32_t STS; // 0x0C SW_STS Serial Wire STATUS Register + __IO uint32_t DP_IDR_ABORT; // 0x10 SW_DP_IDR_ABORT Serial Wire DP R-IDR W-ABORT Register + __IO uint32_t DP_CSR_WCR; // 0x14 SW_DP_CSR_WCR Serial Wire DP R-CSR W-WCR Register + __IO uint32_t DP_RESEND_SELECT; // 0x18 SW_DP_RESEND_SELECT Serial Wire DP R-RESEND W-SELECT Register + __IO uint32_t DP_RDBUF_ROUTESEL; // 0x1C SW_DP_RDBUF_ROUTESEL Serial Wire DP R-RDBUF W-ROUTESEL Register + __IO uint32_t AP_CSW; // 0x20 SW_AP_CSW Serial Wire AP CSW Register + __IO uint32_t AP_TAR; // 0x24 SW_AP_TAR Serial Wire AP TAR Register + __IO uint32_t AP_DRW; // 0x28 SW_AP_DRW Serial Wire AP DRW Register + __IO uint32_t AP_BD0; // 0x2C SW_AP_BD0 Serial Wire AP BD0 Register + __IO uint32_t AP_BD1; // 0x30 SW_AP_BD1 Serial Wire AP BD1 Register + __IO uint32_t AP_BD2; // 0x34 SW_AP_BD2 Serial Wire AP BD2 Register + __IO uint32_t AP_BD3; // 0x38 SW_AP_BD3 Serial Wire AP BD3 Register + __IO uint32_t AP_CFG; // 0x3C SW_AP_CFG Serial Wire AP CFG Register + __IO uint32_t AP_BASE; // 0x40 SW_AP_BASE Serial Wire AP BASE Register + __IO uint32_t AP_IDR; // 0x44 SW_AP_IDR Serial Wire AP IDR Register + uint32_t RES0; // 0x48 + uint32_t RES1; // 0x4C + __IO uint32_t ISP_CMD; // 0x50 SW_ISP_CMD Serial Wire ISP Command Register + __IO uint32_t ISP_DAT; // 0x54 SW_ISP_DAT Serial Wire ISP Data Register +} MSWD_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for WWDG_CR register ************************/ + + + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h new file mode 100644 index 0000000000000000000000000000000000000000..af6a59c419c117717c4c78a7b020e59a70d2461e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h @@ -0,0 +1,585 @@ +/** + ************************************************************************************** + * @file REG_RCU.h + * @brief RCU Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __RCU_H__ +#define __RCU_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for RCU_CON register ************************/ + +#define RCU_CON_SWRDY_POS 24U +#define RCU_CON_SWRDY_MSK BIT(RCU_CON_SWRDY_POS) + +#define RCU_CON_CSSFLG_POS 23U +#define RCU_CON_CSSFLG_MSK BIT(RCU_CON_CSSFLG_POS) + +#define RCU_CON_PLL1RDY_POS 21U +#define RCU_CON_PLL1RDY_MSK BIT(RCU_CON_PLL1RDY_POS) + +#define RCU_CON_PLL0RDY_POS 20U +#define RCU_CON_PLL0RDY_MSK BIT(RCU_CON_PLL0RDY_POS) + +#define RCU_CON_LOSCRDY_POS 19U +#define RCU_CON_LOSCRDY_MSK BIT(RCU_CON_LOSCRDY_POS) + +#define RCU_CON_LRCRDY_POS 18U +#define RCU_CON_LRCRDY_MSK BIT(RCU_CON_LRCRDY_POS) + +#define RCU_CON_HOSCRDY_POS 17U +#define RCU_CON_HOSCRDY_MSK BIT(RCU_CON_HOSCRDY_POS) + +#define RCU_CON_HRCRDY_POS 16U +#define RCU_CON_HRCRDY_MSK BIT(RCU_CON_HRCRDY_POS) + +#define RCU_CON_CSSON_POS 7U +#define RCU_CON_CSSON_MSK BIT(RCU_CON_CSSON_POS) + +#define RCU_CON_PLL1ON_POS 5U +#define RCU_CON_PLL1ON_MSK BIT(RCU_CON_PLL1ON_POS) + +#define RCU_CON_PLL0ON_POS 4U +#define RCU_CON_PLL0ON_MSK BIT(RCU_CON_PLL0ON_POS) + +#define RCU_CON_LOSCON_POS 3U +#define RCU_CON_LOSCON_MSK BIT(RCU_CON_LOSCON_POS) + +#define RCU_CON_LRCON_POS 2U +#define RCU_CON_LRCON_MSK BIT(RCU_CON_LRCON_POS) + +#define RCU_CON_HOSCON_POS 1U +#define RCU_CON_HOSCON_MSK BIT(RCU_CON_HOSCON_POS) + +#define RCU_CON_HRCON_POS 0U +#define RCU_CON_HRCON_MSK BIT(RCU_CON_HRCON_POS) + +/****************** Bit definition for RCU_CFG register ************************/ + +#define RCU_CFG_CKCFG_POS 31U +#define RCU_CFG_CKCFG_MSK BIT(RCU_CFG_CKCFG_POS) + +#define RCU_CFG_MPRE_POSS 28U +#define RCU_CFG_MPRE_POSE 30U +#define RCU_CFG_MPRE_MSK BITS(RCU_CFG_MPRE_POSS,RCU_CFG_MPRE_POSE) + +#define RCU_CFG_MSW_POSS 24U +#define RCU_CFG_MSW_POSE 27U +#define RCU_CFG_MSW_MSK BITS(RCU_CFG_MSW_POSS,RCU_CFG_MSW_POSE) + +#define RCU_CFG_PLLMUL_POSS 17U +#define RCU_CFG_PLLMUL_POSE 21U +#define RCU_CFG_PLLMUL_MSK BITS(RCU_CFG_PLLMUL_POSS,RCU_CFG_PLLMUL_POSE) + +#define RCU_CFG_PLLSRC_POS 16U +#define RCU_CFG_PLLSRC_MSK BIT(RCU_CFG_PLLSRC_POS) + +#define RCU_CFG_HOSCDIV_POSS 12U +#define RCU_CFG_HOSCDIV_POSE 14U +#define RCU_CFG_HOSCDIV_MSK BITS(RCU_CFG_HOSCDIV_POSS,RCU_CFG_HOSCDIV_POSE) + +#define RCU_CFG_PPRE_POSS 8U +#define RCU_CFG_PPRE_POSE 10U +#define RCU_CFG_PPRE_MSK BITS(RCU_CFG_PPRE_POSS,RCU_CFG_PPRE_POSE) + +#define RCU_CFG_HPRE_POSS 4U +#define RCU_CFG_HPRE_POSE 7U +#define RCU_CFG_HPRE_MSK BITS(RCU_CFG_HPRE_POSS,RCU_CFG_HPRE_POSE) + +#define RCU_CFG_SW_POSS 0U +#define RCU_CFG_SW_POSE 2U +#define RCU_CFG_SW_MSK BITS(RCU_CFG_SW_POSS,RCU_CFG_SW_POSE) + +/****************** Bit definition for RCU_STCALIB register ************************/ + +#define RCU_STCALIB_SKEW_POS 30U +#define RCU_STCALIB_SKEW_MSK BIT(RCU_STCALIB_SKEW_POS) + +#define RCU_STCALIB_TENMS_POSS 0U +#define RCU_STCALIB_TENMS_POSE 23U +#define RCU_STCALIB_TENMS_MSK BITS(RCU_STCALIB_TENMS_POSS,RCU_STCALIB_TENMS_POSE) + +/****************** Bit definition for RCU_PSCK register ************************/ + +#define RCU_PSCK_I2S2CKSL_POSS 2U +#define RCU_PSCK_I2S2CKSL_POSE 3U +#define RCU_PSCK_I2S2CKSL_MSK BITS(RCU_PSCK_I2S2CKSL_POSS,RCU_PSCK_I2S2CKSL_POSE) + +#define RCU_PSCK_I2S1CKSL_POSS 0U +#define RCU_PSCK_I2S1CKSL_POSE 1U +#define RCU_PSCK_I2S1CKSL_MSK BITS(RCU_PSCK_I2S1CKSL_POSS,RCU_PSCK_I2S1CKSL_POSE) + +/****************** Bit definition for RCU_AHBRST register ************************/ + +#define RCU_AHBRST_GPDEN_POS 19U +#define RCU_AHBRST_GPDEN_MSK BIT(RCU_AHBRST_GPDEN_POS) + +#define RCU_AHBRST_GPCEN_POS 18U +#define RCU_AHBRST_GPCEN_MSK BIT(RCU_AHBRST_GPCEN_POS) + +#define RCU_AHBRST_GPBEN_POS 17U +#define RCU_AHBRST_GPBEN_MSK BIT(RCU_AHBRST_GPBEN_POS) + +#define RCU_AHBRST_GPAEN_POS 16U +#define RCU_AHBRST_GPAEN_MSK BIT(RCU_AHBRST_GPAEN_POS) + +#define RCU_AHBRST_HDIVEN_POS 15U +#define RCU_AHBRST_HDIVEN_MSK BIT(RCU_AHBRST_HDIVEN_POS) + +#define RCU_AHBRST_USBEN_POS 14U +#define RCU_AHBRST_USBEN_MSK BIT(RCU_AHBRST_USBEN_POS) + +#define RCU_AHBRST_AESEN_POS 13U +#define RCU_AHBRST_AESEN_MSK BIT(RCU_AHBRST_AESEN_POS) + +#define RCU_AHBRST_CRCEN_POS 12U +#define RCU_AHBRST_CRCEN_MSK BIT(RCU_AHBRST_CRCEN_POS) + +#define RCU_AHBRST_RTCEN_POS 6U +#define RCU_AHBRST_RTCEN_MSK BIT(RCU_AHBRST_RTCEN_POS) + +#define RCU_AHBRST_DMA1EN_POS 0U +#define RCU_AHBRST_DMA1EN_MSK BIT(RCU_AHBRST_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1RST register ************************/ + +#define RCU_APB1RST_DACEN_POS 23U +#define RCU_APB1RST_DACEN_MSK BIT(RCU_APB1RST_DACEN_POS) + +#define RCU_APB1RST_I2C2EN_POS 22U +#define RCU_APB1RST_I2C2EN_MSK BIT(RCU_APB1RST_I2C2EN_POS) + +#define RCU_APB1RST_I2C1EN_POS 21U +#define RCU_APB1RST_I2C1EN_MSK BIT(RCU_APB1RST_I2C1EN_POS) + +#define RCU_APB1RST_SUART2EN_POS 20U +#define RCU_APB1RST_SUART2EN_MSK BIT(RCU_APB1RST_SUART2EN_POS) + +#define RCU_APB1RST_SUART1EN_POS 19U +#define RCU_APB1RST_SUART1EN_MSK BIT(RCU_APB1RST_SUART1EN_POS) + +#define RCU_APB1RST_UART3EN_POS 18U +#define RCU_APB1RST_UART3EN_MSK BIT(RCU_APB1RST_UART3EN_POS) + +#define RCU_APB1RST_UART2EN_POS 17U +#define RCU_APB1RST_UART2EN_MSK BIT(RCU_APB1RST_UART2EN_POS) + +#define RCU_APB1RST_SPI2EN_POS 14U +#define RCU_APB1RST_SPI2EN_MSK BIT(RCU_APB1RST_SPI2EN_POS) + +#define RCU_APB1RST_IWDTEN_POS 12U +#define RCU_APB1RST_IWDTEN_MSK BIT(RCU_APB1RST_IWDTEN_POS) + +#define RCU_APB1RST_WWDTEN_POS 11U +#define RCU_APB1RST_WWDTEN_MSK BIT(RCU_APB1RST_WWDTEN_POS) + +#define RCU_APB1RST_BS16T1EN_POS 4U +#define RCU_APB1RST_BS16T1EN_MSK BIT(RCU_APB1RST_BS16T1EN_POS) + +#define RCU_APB1RST_GP16C4T3EN_POS 3U +#define RCU_APB1RST_GP16C4T3EN_MSK BIT(RCU_APB1RST_GP16C4T3EN_POS) + +#define RCU_APB1RST_GP16C4T2EN_POS 2U +#define RCU_APB1RST_GP16C4T2EN_MSK BIT(RCU_APB1RST_GP16C4T2EN_POS) + +#define RCU_APB1RST_GP16C4T1EN_POS 1U +#define RCU_APB1RST_GP16C4T1EN_MSK BIT(RCU_APB1RST_GP16C4T1EN_POS) + +#define RCU_APB1RST_GP32C4T1EN_POS 0U +#define RCU_APB1RST_GP32C4T1EN_MSK BIT(RCU_APB1RST_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2RST register ************************/ + +#define RCU_APB2RST_CMPEN_POS 23U +#define RCU_APB2RST_CMPEN_MSK BIT(RCU_APB2RST_CMPEN_POS) + +#define RCU_APB2RST_GP16C2T4EN_POS 19U +#define RCU_APB2RST_GP16C2T4EN_MSK BIT(RCU_APB2RST_GP16C2T4EN_POS) + +#define RCU_APB2RST_GP16C2T3EN_POS 18U +#define RCU_APB2RST_GP16C2T3EN_MSK BIT(RCU_APB2RST_GP16C2T3EN_POS) + +#define RCU_APB2RST_GP16C2T2EN_POS 17U +#define RCU_APB2RST_GP16C2T2EN_MSK BIT(RCU_APB2RST_GP16C2T2EN_POS) + +#define RCU_APB2RST_GP16C2T1EN_POS 16U +#define RCU_APB2RST_GP16C2T1EN_MSK BIT(RCU_APB2RST_GP16C2T1EN_POS) + +#define RCU_APB2RST_UART1EN_POS 14U +#define RCU_APB2RST_UART1EN_MSK BIT(RCU_APB2RST_UART1EN_POS) + +#define RCU_APB2RST_SPI1EN_POS 12U +#define RCU_APB2RST_SPI1EN_MSK BIT(RCU_APB2RST_SPI1EN_POS) + +#define RCU_APB2RST_AD16C4T1EN_POS 11U +#define RCU_APB2RST_AD16C4T1EN_MSK BIT(RCU_APB2RST_AD16C4T1EN_POS) + +#define RCU_APB2RST_ADCEN_POS 9U +#define RCU_APB2RST_ADCEN_MSK BIT(RCU_APB2RST_ADCEN_POS) + +/****************** Bit definition for RCU_AHBEN register ************************/ + +#define RCU_AHBEN_GPDEN_POS 19U +#define RCU_AHBEN_GPDEN_MSK BIT(RCU_AHBEN_GPDEN_POS) + +#define RCU_AHBEN_GPCEN_POS 18U +#define RCU_AHBEN_GPCEN_MSK BIT(RCU_AHBEN_GPCEN_POS) + +#define RCU_AHBEN_GPBEN_POS 17U +#define RCU_AHBEN_GPBEN_MSK BIT(RCU_AHBEN_GPBEN_POS) + +#define RCU_AHBEN_GPAEN_POS 16U +#define RCU_AHBEN_GPAEN_MSK BIT(RCU_AHBEN_GPAEN_POS) + +#define RCU_AHBEN_HDIVEN_POS 15U +#define RCU_AHBEN_HDIVEN_MSK BIT(RCU_AHBEN_HDIVEN_POS) + +#define RCU_AHBEN_USBEN_POS 14U +#define RCU_AHBEN_USBEN_MSK BIT(RCU_AHBEN_USBEN_POS) + +#define RCU_AHBEN_AESEN_POS 13U +#define RCU_AHBEN_AESEN_MSK BIT(RCU_AHBEN_AESEN_POS) + +#define RCU_AHBEN_CRCEN_POS 12U +#define RCU_AHBEN_CRCEN_MSK BIT(RCU_AHBEN_CRCEN_POS) + +#define RCU_AHBEN_RTCEN_POS 6U +#define RCU_AHBEN_RTCEN_MSK BIT(RCU_AHBEN_RTCEN_POS) + +#define RCU_AHBEN_DMA1EN_POS 0U +#define RCU_AHBEN_DMA1EN_MSK BIT(RCU_AHBEN_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1EN register ************************/ + +#define RCU_APB1EN_DACEN_POS 23U +#define RCU_APB1EN_DACEN_MSK BIT(RCU_APB1EN_DACEN_POS) + +#define RCU_APB1EN_I2C2EN_POS 22U +#define RCU_APB1EN_I2C2EN_MSK BIT(RCU_APB1EN_I2C2EN_POS) + +#define RCU_APB1EN_I2C1EN_POS 21U +#define RCU_APB1EN_I2C1EN_MSK BIT(RCU_APB1EN_I2C1EN_POS) + +#define RCU_APB1EN_SUART2EN_POS 20U +#define RCU_APB1EN_SUART2EN_MSK BIT(RCU_APB1EN_SUART2EN_POS) + +#define RCU_APB1EN_SUART1EN_POS 19U +#define RCU_APB1EN_SUART1EN_MSK BIT(RCU_APB1EN_SUART1EN_POS) + +#define RCU_APB1EN_UART3EN_POS 18U +#define RCU_APB1EN_UART3EN_MSK BIT(RCU_APB1EN_UART3EN_POS) + +#define RCU_APB1EN_UART2EN_POS 17U +#define RCU_APB1EN_UART2EN_MSK BIT(RCU_APB1EN_UART2EN_POS) + +#define RCU_APB1EN_SPI2EN_POS 14U +#define RCU_APB1EN_SPI2EN_MSK BIT(RCU_APB1EN_SPI2EN_POS) + +#define RCU_APB1EN_IWDTEN_POS 12U +#define RCU_APB1EN_IWDTEN_MSK BIT(RCU_APB1EN_IWDTEN_POS) + +#define RCU_APB1EN_WWDTEN_POS 11U +#define RCU_APB1EN_WWDTEN_MSK BIT(RCU_APB1EN_WWDTEN_POS) + +#define RCU_APB1EN_BS16T1EN_POS 4U +#define RCU_APB1EN_BS16T1EN_MSK BIT(RCU_APB1EN_BS16T1EN_POS) + +#define RCU_APB1EN_GP16C4T3EN_POS 3U +#define RCU_APB1EN_GP16C4T3EN_MSK BIT(RCU_APB1EN_GP16C4T3EN_POS) + +#define RCU_APB1EN_GP16C4T2EN_POS 2U +#define RCU_APB1EN_GP16C4T2EN_MSK BIT(RCU_APB1EN_GP16C4T2EN_POS) + +#define RCU_APB1EN_GP16C4T1EN_POS 1U +#define RCU_APB1EN_GP16C4T1EN_MSK BIT(RCU_APB1EN_GP16C4T1EN_POS) + +#define RCU_APB1EN_GP32C4T1EN_POS 0U +#define RCU_APB1EN_GP32C4T1EN_MSK BIT(RCU_APB1EN_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2EN register ************************/ + +#define RCU_APB2EN_CMPEN_POS 23U +#define RCU_APB2EN_CMPEN_MSK BIT(RCU_APB2EN_CMPEN_POS) + +#define RCU_APB2EN_GP16C2T4EN_POS 19U +#define RCU_APB2EN_GP16C2T4EN_MSK BIT(RCU_APB2EN_GP16C2T4EN_POS) + +#define RCU_APB2EN_GP16C2T3EN_POS 18U +#define RCU_APB2EN_GP16C2T3EN_MSK BIT(RCU_APB2EN_GP16C2T3EN_POS) + +#define RCU_APB2EN_GP16C2T2EN_POS 17U +#define RCU_APB2EN_GP16C2T2EN_MSK BIT(RCU_APB2EN_GP16C2T2EN_POS) + +#define RCU_APB2EN_GP16C2T1EN_POS 16U +#define RCU_APB2EN_GP16C2T1EN_MSK BIT(RCU_APB2EN_GP16C2T1EN_POS) + +#define RCU_APB2EN_UART1EN_POS 14U +#define RCU_APB2EN_UART1EN_MSK BIT(RCU_APB2EN_UART1EN_POS) + +#define RCU_APB2EN_SPI1EN_POS 12U +#define RCU_APB2EN_SPI1EN_MSK BIT(RCU_APB2EN_SPI1EN_POS) + +#define RCU_APB2EN_AD16C4T1EN_POS 11U +#define RCU_APB2EN_AD16C4T1EN_MSK BIT(RCU_APB2EN_AD16C4T1EN_POS) + +#define RCU_APB2EN_ADCEN_POS 9U +#define RCU_APB2EN_ADCEN_MSK BIT(RCU_APB2EN_ADCEN_POS) + +/****************** Bit definition for RCU_AHBSL register ************************/ + +#define RCU_AHBSL_GPDEN_POS 19U +#define RCU_AHBSL_GPDEN_MSK BIT(RCU_AHBSL_GPDEN_POS) + +#define RCU_AHBSL_GPCEN_POS 18U +#define RCU_AHBSL_GPCEN_MSK BIT(RCU_AHBSL_GPCEN_POS) + +#define RCU_AHBSL_GPBEN_POS 17U +#define RCU_AHBSL_GPBEN_MSK BIT(RCU_AHBSL_GPBEN_POS) + +#define RCU_AHBSL_GPAEN_POS 16U +#define RCU_AHBSL_GPAEN_MSK BIT(RCU_AHBSL_GPAEN_POS) + +#define RCU_AHBSL_HDIVEN_POS 15U +#define RCU_AHBSL_HDIVEN_MSK BIT(RCU_AHBSL_HDIVEN_POS) + +#define RCU_AHBSL_USBEN_POS 14U +#define RCU_AHBSL_USBEN_MSK BIT(RCU_AHBSL_USBEN_POS) + +#define RCU_AHBSL_AESEN_POS 13U +#define RCU_AHBSL_AESEN_MSK BIT(RCU_AHBSL_AESEN_POS) + +#define RCU_AHBSL_CRCEN_POS 12U +#define RCU_AHBSL_CRCEN_MSK BIT(RCU_AHBSL_CRCEN_POS) + +#define RCU_AHBSL_RTCEN_POS 6U +#define RCU_AHBSL_RTCEN_MSK BIT(RCU_AHBSL_RTCEN_POS) + +#define RCU_AHBSL_DMA1EN_POS 0U +#define RCU_AHBSL_DMA1EN_MSK BIT(RCU_AHBSL_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1SL register ************************/ + +#define RCU_APB1SL_DACEN_POS 23U +#define RCU_APB1SL_DACEN_MSK BIT(RCU_APB1SL_DACEN_POS) + +#define RCU_APB1SL_I2C2EN_POS 22U +#define RCU_APB1SL_I2C2EN_MSK BIT(RCU_APB1SL_I2C2EN_POS) + +#define RCU_APB1SL_I2C1EN_POS 21U +#define RCU_APB1SL_I2C1EN_MSK BIT(RCU_APB1SL_I2C1EN_POS) + +#define RCU_APB1SL_SUART2EN_POS 20U +#define RCU_APB1SL_SUART2EN_MSK BIT(RCU_APB1SL_SUART2EN_POS) + +#define RCU_APB1SL_SUART1EN_POS 19U +#define RCU_APB1SL_SUART1EN_MSK BIT(RCU_APB1SL_SUART1EN_POS) + +#define RCU_APB1SL_UART3EN_POS 18U +#define RCU_APB1SL_UART3EN_MSK BIT(RCU_APB1SL_UART3EN_POS) + +#define RCU_APB1SL_UART2EN_POS 17U +#define RCU_APB1SL_UART2EN_MSK BIT(RCU_APB1SL_UART2EN_POS) + +#define RCU_APB1SL_SPI2EN_POS 14U +#define RCU_APB1SL_SPI2EN_MSK BIT(RCU_APB1SL_SPI2EN_POS) + +#define RCU_APB1SL_IWDTEN_POS 12U +#define RCU_APB1SL_IWDTEN_MSK BIT(RCU_APB1SL_IWDTEN_POS) + +#define RCU_APB1SL_WWDTEN_POS 11U +#define RCU_APB1SL_WWDTEN_MSK BIT(RCU_APB1SL_WWDTEN_POS) + +#define RCU_APB1SL_BS16T1EN_POS 4U +#define RCU_APB1SL_BS16T1EN_MSK BIT(RCU_APB1SL_BS16T1EN_POS) + +#define RCU_APB1SL_GP16C4T3EN_POS 3U +#define RCU_APB1SL_GP16C4T3EN_MSK BIT(RCU_APB1SL_GP16C4T3EN_POS) + +#define RCU_APB1SL_GP16C4T2EN_POS 2U +#define RCU_APB1SL_GP16C4T2EN_MSK BIT(RCU_APB1SL_GP16C4T2EN_POS) + +#define RCU_APB1SL_GP16C4T1EN_POS 1U +#define RCU_APB1SL_GP16C4T1EN_MSK BIT(RCU_APB1SL_GP16C4T1EN_POS) + +#define RCU_APB1SL_GP32C4T1EN_POS 0U +#define RCU_APB1SL_GP32C4T1EN_MSK BIT(RCU_APB1SL_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2SL register ************************/ + +#define RCU_APB2SL_CMPEN_POS 23U +#define RCU_APB2SL_CMPEN_MSK BIT(RCU_APB2SL_CMPEN_POS) + +#define RCU_APB2SL_GP16C2T4EN_POS 19U +#define RCU_APB2SL_GP16C2T4EN_MSK BIT(RCU_APB2SL_GP16C2T4EN_POS) + +#define RCU_APB2SL_GP16C2T3EN_POS 18U +#define RCU_APB2SL_GP16C2T3EN_MSK BIT(RCU_APB2SL_GP16C2T3EN_POS) + +#define RCU_APB2SL_GP16C2T2EN_POS 17U +#define RCU_APB2SL_GP16C2T2EN_MSK BIT(RCU_APB2SL_GP16C2T2EN_POS) + +#define RCU_APB2SL_GP16C2T1EN_POS 16U +#define RCU_APB2SL_GP16C2T1EN_MSK BIT(RCU_APB2SL_GP16C2T1EN_POS) + +#define RCU_APB2SL_UART1EN_POS 14U +#define RCU_APB2SL_UART1EN_MSK BIT(RCU_APB2SL_UART1EN_POS) + +#define RCU_APB2SL_SPI1EN_POS 12U +#define RCU_APB2SL_SPI1EN_MSK BIT(RCU_APB2SL_SPI1EN_POS) + +#define RCU_APB2SL_AD16C4T1EN_POS 11U +#define RCU_APB2SL_AD16C4T1EN_MSK BIT(RCU_APB2SL_AD16C4T1EN_POS) + +#define RCU_APB2SL_ADCEN_POS 9U +#define RCU_APB2SL_ADCEN_MSK BIT(RCU_APB2SL_ADCEN_POS) + +/****************** Bit definition for RCU_AHBDSL register ************************/ + +#define RCU_AHBDSL_GPDEN_POS 19U +#define RCU_AHBDSL_GPDEN_MSK BIT(RCU_AHBDSL_GPDEN_POS) + +#define RCU_AHBDSL_GPCEN_POS 18U +#define RCU_AHBDSL_GPCEN_MSK BIT(RCU_AHBDSL_GPCEN_POS) + +#define RCU_AHBDSL_GPBEN_POS 17U +#define RCU_AHBDSL_GPBEN_MSK BIT(RCU_AHBDSL_GPBEN_POS) + +#define RCU_AHBDSL_GPAEN_POS 16U +#define RCU_AHBDSL_GPAEN_MSK BIT(RCU_AHBDSL_GPAEN_POS) + +#define RCU_AHBDSL_HDIVEN_POS 15U +#define RCU_AHBDSL_HDIVEN_MSK BIT(RCU_AHBDSL_HDIVEN_POS) + +#define RCU_AHBDSL_USBEN_POS 14U +#define RCU_AHBDSL_USBEN_MSK BIT(RCU_AHBDSL_USBEN_POS) + +#define RCU_AHBDSL_AESEN_POS 13U +#define RCU_AHBDSL_AESEN_MSK BIT(RCU_AHBDSL_AESEN_POS) + +#define RCU_AHBDSL_CRCEN_POS 12U +#define RCU_AHBDSL_CRCEN_MSK BIT(RCU_AHBDSL_CRCEN_POS) + +#define RCU_AHBDSL_RTCEN_POS 6U +#define RCU_AHBDSL_RTCEN_MSK BIT(RCU_AHBDSL_RTCEN_POS) + +#define RCU_AHBDSL_DMA1EN_POS 0U +#define RCU_AHBDSL_DMA1EN_MSK BIT(RCU_AHBDSL_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1DSL register ************************/ + +#define RCU_APB1DSL_DACEN_POS 23U +#define RCU_APB1DSL_DACEN_MSK BIT(RCU_APB1DSL_DACEN_POS) + +#define RCU_APB1DSL_I2C2EN_POS 22U +#define RCU_APB1DSL_I2C2EN_MSK BIT(RCU_APB1DSL_I2C2EN_POS) + +#define RCU_APB1DSL_I2C1EN_POS 21U +#define RCU_APB1DSL_I2C1EN_MSK BIT(RCU_APB1DSL_I2C1EN_POS) + +#define RCU_APB1DSL_SUART2EN_POS 20U +#define RCU_APB1DSL_SUART2EN_MSK BIT(RCU_APB1DSL_SUART2EN_POS) + +#define RCU_APB1DSL_SUART1EN_POS 19U +#define RCU_APB1DSL_SUART1EN_MSK BIT(RCU_APB1DSL_SUART1EN_POS) + +#define RCU_APB1DSL_UART3EN_POS 18U +#define RCU_APB1DSL_UART3EN_MSK BIT(RCU_APB1DSL_UART3EN_POS) + +#define RCU_APB1DSL_UART2EN_POS 17U +#define RCU_APB1DSL_UART2EN_MSK BIT(RCU_APB1DSL_UART2EN_POS) + +#define RCU_APB1DSL_SPI2EN_POS 14U +#define RCU_APB1DSL_SPI2EN_MSK BIT(RCU_APB1DSL_SPI2EN_POS) + +#define RCU_APB1DSL_IWDTEN_POS 12U +#define RCU_APB1DSL_IWDTEN_MSK BIT(RCU_APB1DSL_IWDTEN_POS) + +#define RCU_APB1DSL_WWDTEN_POS 11U +#define RCU_APB1DSL_WWDTEN_MSK BIT(RCU_APB1DSL_WWDTEN_POS) + +#define RCU_APB1DSL_BS16T1EN_POS 4U +#define RCU_APB1DSL_BS16T1EN_MSK BIT(RCU_APB1DSL_BS16T1EN_POS) + +#define RCU_APB1DSL_GP16C4T3EN_POS 3U +#define RCU_APB1DSL_GP16C4T3EN_MSK BIT(RCU_APB1DSL_GP16C4T3EN_POS) + +#define RCU_APB1DSL_GP16C4T2EN_POS 2U +#define RCU_APB1DSL_GP16C4T2EN_MSK BIT(RCU_APB1DSL_GP16C4T2EN_POS) + +#define RCU_APB1DSL_GP16C4T1EN_POS 1U +#define RCU_APB1DSL_GP16C4T1EN_MSK BIT(RCU_APB1DSL_GP16C4T1EN_POS) + +#define RCU_APB1DSL_GP32C4T1EN_POS 0U +#define RCU_APB1DSL_GP32C4T1EN_MSK BIT(RCU_APB1DSL_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2DSL register ************************/ + +#define RCU_APB2DSL_CMPEN_POS 23U +#define RCU_APB2DSL_CMPEN_MSK BIT(RCU_APB2DSL_CMPEN_POS) + +#define RCU_APB2DSL_GP16C2T4EN_POS 19U +#define RCU_APB2DSL_GP16C2T4EN_MSK BIT(RCU_APB2DSL_GP16C2T4EN_POS) + +#define RCU_APB2DSL_GP16C2T3EN_POS 18U +#define RCU_APB2DSL_GP16C2T3EN_MSK BIT(RCU_APB2DSL_GP16C2T3EN_POS) + +#define RCU_APB2DSL_GP16C2T2EN_POS 17U +#define RCU_APB2DSL_GP16C2T2EN_MSK BIT(RCU_APB2DSL_GP16C2T2EN_POS) + +#define RCU_APB2DSL_GP16C2T1EN_POS 16U +#define RCU_APB2DSL_GP16C2T1EN_MSK BIT(RCU_APB2DSL_GP16C2T1EN_POS) + +#define RCU_APB2DSL_UART1EN_POS 14U +#define RCU_APB2DSL_UART1EN_MSK BIT(RCU_APB2DSL_UART1EN_POS) + +#define RCU_APB2DSL_SPI1EN_POS 12U +#define RCU_APB2DSL_SPI1EN_MSK BIT(RCU_APB2DSL_SPI1EN_POS) + +#define RCU_APB2DSL_AD16C4T1EN_POS 11U +#define RCU_APB2DSL_AD16C4T1EN_MSK BIT(RCU_APB2DSL_AD16C4T1EN_POS) + +#define RCU_APB2DSL_ADCEN_POS 9U +#define RCU_APB2DSL_ADCEN_MSK BIT(RCU_APB2DSL_ADCEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __IO uint32_t STCALIB; + __IO uint32_t PSCK; + __IO uint32_t AHBRST; + __IO uint32_t APB1RST; + __IO uint32_t APB2RST; + __IO uint32_t AHBEN; + __IO uint32_t APB1EN; + __IO uint32_t APB2EN; + __IO uint32_t AHBSL; + __IO uint32_t APB1SL; + __IO uint32_t APB2SL; + __IO uint32_t AHBDSL; + __IO uint32_t APB1DSL; + __IO uint32_t APB2DSL; +} RCU_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..a22674f22ba6a7731f234366828397339c10ab1d --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h @@ -0,0 +1,613 @@ +/** + ************************************************************************************** + * @file REG_RTC.h + * @brief RTC Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __RTC_H__ +#define __RTC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_MODE_POS 30U +#define RTC_CON_MODE_MSK BIT(RTC_CON_MODE_POS) + +#define RTC_CON_CALVAL_POSS 24U +#define RTC_CON_CALVAL_POSE 29U +#define RTC_CON_CALVAL_MSK BITS(RTC_CON_CALVAL_POSS,RTC_CON_CALVAL_POSE) + +#define RTC_CON_SCALE_POSS 16U +#define RTC_CON_SCALE_POSE 23U +#define RTC_CON_SCALE_MSK BITS(RTC_CON_SCALE_POSS,RTC_CON_SCALE_POSE) + +#define RTC_CON_PSCALE_POSS 8U +#define RTC_CON_PSCALE_POSE 14U +#define RTC_CON_PSCALE_MSK BITS(RTC_CON_PSCALE_POSS,RTC_CON_PSCALE_POSE) + +#define RTC_CON_CYCLE_POS 5U +#define RTC_CON_CYCLE_MSK BIT(RTC_CON_CYCLE_POS) + +#define RTC_CON_CALIB_POS 4U +#define RTC_CON_CALIB_MSK BIT(RTC_CON_CALIB_POS) + +#define RTC_CON_CKSEL_POSS 2U +#define RTC_CON_CKSEL_POSE 3U +#define RTC_CON_CKSEL_MSK BITS(RTC_CON_CKSEL_POSS,RTC_CON_CKSEL_POSE) + +#define RTC_CON_RTCEN_POS 0U +#define RTC_CON_RTCEN_MSK BIT(RTC_CON_RTCEN_POS) + +/****************** Bit definition for RTC_WKUP register ************************/ + +#define RTC_WKUP_WKSCAL_POSS 26U +#define RTC_WKUP_WKSCAL_POSE 29U +#define RTC_WKUP_WKSCAL_MSK BITS(RTC_WKUP_WKSCAL_POSS,RTC_WKUP_WKSCAL_POSE) + +#define RTC_WKUP_WKSEL_POSS 24U +#define RTC_WKUP_WKSEL_POSE 25U +#define RTC_WKUP_WKSEL_MSK BITS(RTC_WKUP_WKSEL_POSS,RTC_WKUP_WKSEL_POSE) + +#define RTC_WKUP_WKCAL_POSS 0U +#define RTC_WKUP_WKCAL_POSE 23U +#define RTC_WKUP_WKCAL_MSK BITS(RTC_WKUP_WKCAL_POSS,RTC_WKUP_WKCAL_POSE) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_WEEK_POSS 24U +#define RTC_TIME_WEEK_POSE 26U +#define RTC_TIME_WEEK_MSK BITS(RTC_TIME_WEEK_POSS,RTC_TIME_WEEK_POSE) + +#define RTC_TIME_HOUR_T_POSS 20U +#define RTC_TIME_HOUR_T_POSE 21U +#define RTC_TIME_HOUR_T_MSK BITS(RTC_TIME_HOUR_T_POSS,RTC_TIME_HOUR_T_POSE) + +#define RTC_TIME_HOUR_U_POSS 16U +#define RTC_TIME_HOUR_U_POSE 19U +#define RTC_TIME_HOUR_U_MSK BITS(RTC_TIME_HOUR_U_POSS,RTC_TIME_HOUR_U_POSE) + +#define RTC_TIME_MIN_T_POSS 12U +#define RTC_TIME_MIN_T_POSE 14U +#define RTC_TIME_MIN_T_MSK BITS(RTC_TIME_MIN_T_POSS,RTC_TIME_MIN_T_POSE) + +#define RTC_TIME_MIN_U_POSS 8U +#define RTC_TIME_MIN_U_POSE 11U +#define RTC_TIME_MIN_U_MSK BITS(RTC_TIME_MIN_U_POSS,RTC_TIME_MIN_U_POSE) + +#define RTC_TIME_SEC_T_POSS 4U +#define RTC_TIME_SEC_T_POSE 6U +#define RTC_TIME_SEC_T_MSK BITS(RTC_TIME_SEC_T_POSS,RTC_TIME_SEC_T_POSE) + +#define RTC_TIME_SEC_U_POSS 0U +#define RTC_TIME_SEC_U_POSE 3U +#define RTC_TIME_SEC_U_MSK BITS(RTC_TIME_SEC_U_POSS,RTC_TIME_SEC_U_POSE) + +/****************** Bit definition for RTC_CAL register ************************/ + +#define RTC_CAL_YEAR_T_POSS 20U +#define RTC_CAL_YEAR_T_POSE 23U +#define RTC_CAL_YEAR_T_MSK BITS(RTC_CAL_YEAR_T_POSS,RTC_CAL_YEAR_T_POSE) + +#define RTC_CAL_YEAR_U_POSS 16U +#define RTC_CAL_YEAR_U_POSE 19U +#define RTC_CAL_YEAR_U_MSK BITS(RTC_CAL_YEAR_U_POSS,RTC_CAL_YEAR_U_POSE) + +#define RTC_CAL_MON_T_POS 12U +#define RTC_CAL_MON_T_MSK BIT(RTC_CAL_MON_T_POS) + +#define RTC_CAL_MON_U_POSS 8U +#define RTC_CAL_MON_U_POSE 11U +#define RTC_CAL_MON_U_MSK BITS(RTC_CAL_MON_U_POSS,RTC_CAL_MON_U_POSE) + +#define RTC_CAL_DATE_T_POSS 4U +#define RTC_CAL_DATE_T_POSE 5U +#define RTC_CAL_DATE_T_MSK BITS(RTC_CAL_DATE_T_POSS,RTC_CAL_DATE_T_POSE) + +#define RTC_CAL_DATE_U_POSS 0U +#define RTC_CAL_DATE_U_POSE 3U +#define RTC_CAL_DATE_U_MSK BITS(RTC_CAL_DATE_U_POSS,RTC_CAL_DATE_U_POSE) + +/****************** Bit definition for RTC_ALTIME register ************************/ + +#define RTC_ALTIME_WEEK_POSS 24U +#define RTC_ALTIME_WEEK_POSE 26U +#define RTC_ALTIME_WEEK_MSK BITS(RTC_ALTIME_WEEK_POSS,RTC_ALTIME_WEEK_POSE) + +#define RTC_ALTIME_HOUR_T_POSS 20U +#define RTC_ALTIME_HOUR_T_POSE 21U +#define RTC_ALTIME_HOUR_T_MSK BITS(RTC_ALTIME_HOUR_T_POSS,RTC_ALTIME_HOUR_T_POSE) + +#define RTC_ALTIME_HOUR_U_POSS 16U +#define RTC_ALTIME_HOUR_U_POSE 19U +#define RTC_ALTIME_HOUR_U_MSK BITS(RTC_ALTIME_HOUR_U_POSS,RTC_ALTIME_HOUR_U_POSE) + +#define RTC_ALTIME_MIN_T_POSS 12U +#define RTC_ALTIME_MIN_T_POSE 14U +#define RTC_ALTIME_MIN_T_MSK BITS(RTC_ALTIME_MIN_T_POSS,RTC_ALTIME_MIN_T_POSE) + +#define RTC_ALTIME_MIN_U_POSS 8U +#define RTC_ALTIME_MIN_U_POSE 11U +#define RTC_ALTIME_MIN_U_MSK BITS(RTC_ALTIME_MIN_U_POSS,RTC_ALTIME_MIN_U_POSE) + +#define RTC_ALTIME_SEC_T_POSS 4U +#define RTC_ALTIME_SEC_T_POSE 6U +#define RTC_ALTIME_SEC_T_MSK BITS(RTC_ALTIME_SEC_T_POSS,RTC_ALTIME_SEC_T_POSE) + +#define RTC_ALTIME_SEC_U_POSS 0U +#define RTC_ALTIME_SEC_U_POSE 3U +#define RTC_ALTIME_SEC_U_MSK BITS(RTC_ALTIME_SEC_U_POSS,RTC_ALTIME_SEC_U_POSE) + +/****************** Bit definition for RTC_ALCAL register ************************/ + +#define RTC_ALCAL_YEAR_T_POSS 20U +#define RTC_ALCAL_YEAR_T_POSE 23U +#define RTC_ALCAL_YEAR_T_MSK BITS(RTC_ALCAL_YEAR_T_POSS,RTC_ALCAL_YEAR_T_POSE) + +#define RTC_ALCAL_YEAR_U_POSS 16U +#define RTC_ALCAL_YEAR_U_POSE 19U +#define RTC_ALCAL_YEAR_U_MSK BITS(RTC_ALCAL_YEAR_U_POSS,RTC_ALCAL_YEAR_U_POSE) + +#define RTC_ALCAL_MON_T_POS 12U +#define RTC_ALCAL_MON_T_MSK BIT(RTC_ALCAL_MON_T_POS) + +#define RTC_ALCAL_MON_U_POSS 8U +#define RTC_ALCAL_MON_U_POSE 11U +#define RTC_ALCAL_MON_U_MSK BITS(RTC_ALCAL_MON_U_POSS,RTC_ALCAL_MON_U_POSE) + +#define RTC_ALCAL_DATE_T_POSS 4U +#define RTC_ALCAL_DATE_T_POSE 5U +#define RTC_ALCAL_DATE_T_MSK BITS(RTC_ALCAL_DATE_T_POSS,RTC_ALCAL_DATE_T_POSE) + +#define RTC_ALCAL_DATE_U_POSS 0U +#define RTC_ALCAL_DATE_U_POSE 3U +#define RTC_ALCAL_DATE_U_MSK BITS(RTC_ALCAL_DATE_U_POSS,RTC_ALCAL_DATE_U_POSE) + +/****************** Bit definition for RTC_ALEN register ************************/ + +#define RTC_ALEN_YEAR_POS 6U +#define RTC_ALEN_YEAR_MSK BIT(RTC_ALEN_YEAR_POS) + +#define RTC_ALEN_MONTH_POS 5U +#define RTC_ALEN_MONTH_MSK BIT(RTC_ALEN_MONTH_POS) + +#define RTC_ALEN_DATE_POS 4U +#define RTC_ALEN_DATE_MSK BIT(RTC_ALEN_DATE_POS) + +#define RTC_ALEN_WEEK_POS 3U +#define RTC_ALEN_WEEK_MSK BIT(RTC_ALEN_WEEK_POS) + +#define RTC_ALEN_HOUR_POS 2U +#define RTC_ALEN_HOUR_MSK BIT(RTC_ALEN_HOUR_POS) + +#define RTC_ALEN_MIN_POS 1U +#define RTC_ALEN_MIN_MSK BIT(RTC_ALEN_MIN_POS) + +#define RTC_ALEN_SEC_POS 0U +#define RTC_ALEN_SEC_MSK BIT(RTC_ALEN_SEC_POS) + +/****************** Bit definition for RTC_TRIG register ************************/ + +#define RTC_TRIG_WKTM_POS 16U +#define RTC_TRIG_WKTM_MSK BIT(RTC_TRIG_WKTM_POS) + +#define RTC_TRIG_F1HZ_POS 15U +#define RTC_TRIG_F1HZ_MSK BIT(RTC_TRIG_F1HZ_POS) + +#define RTC_TRIG_RYEAR_POS 14U +#define RTC_TRIG_RYEAR_MSK BIT(RTC_TRIG_RYEAR_POS) + +#define RTC_TRIG_RMON_POS 13U +#define RTC_TRIG_RMON_MSK BIT(RTC_TRIG_RMON_POS) + +#define RTC_TRIG_RDATE_POS 12U +#define RTC_TRIG_RDATE_MSK BIT(RTC_TRIG_RDATE_POS) + +#define RTC_TRIG_RWEEK_POS 11U +#define RTC_TRIG_RWEEK_MSK BIT(RTC_TRIG_RWEEK_POS) + +#define RTC_TRIG_RHOUR_POS 10U +#define RTC_TRIG_RHOUR_MSK BIT(RTC_TRIG_RHOUR_POS) + +#define RTC_TRIG_RMIN_POS 9U +#define RTC_TRIG_RMIN_MSK BIT(RTC_TRIG_RMIN_POS) + +#define RTC_TRIG_RSEC_POS 8U +#define RTC_TRIG_RSEC_MSK BIT(RTC_TRIG_RSEC_POS) + +#define RTC_TRIG_AMALL_POS 7U +#define RTC_TRIG_AMALL_MSK BIT(RTC_TRIG_AMALL_POS) + +#define RTC_TRIG_AYEAR_POS 6U +#define RTC_TRIG_AYEAR_MSK BIT(RTC_TRIG_AYEAR_POS) + +#define RTC_TRIG_AMON_POS 5U +#define RTC_TRIG_AMON_MSK BIT(RTC_TRIG_AMON_POS) + +#define RTC_TRIG_ADTAE_POS 4U +#define RTC_TRIG_ADTAE_MSK BIT(RTC_TRIG_ADTAE_POS) + +#define RTC_TRIG_AWEEK_POS 3U +#define RTC_TRIG_AWEEK_MSK BIT(RTC_TRIG_AWEEK_POS) + +#define RTC_TRIG_AHOUR_POS 2U +#define RTC_TRIG_AHOUR_MSK BIT(RTC_TRIG_AHOUR_POS) + +#define RTC_TRIG_AMIN_POS 1U +#define RTC_TRIG_AMIN_MSK BIT(RTC_TRIG_AMIN_POS) + +#define RTC_TRIG_ASEC_POS 0U +#define RTC_TRIG_ASEC_MSK BIT(RTC_TRIG_ASEC_POS) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_WKTM_POS 16U +#define RTC_IER_WKTM_MSK BIT(RTC_IER_WKTM_POS) + +#define RTC_IER_F1HZ_POS 15U +#define RTC_IER_F1HZ_MSK BIT(RTC_IER_F1HZ_POS) + +#define RTC_IER_RYEAR_POS 14U +#define RTC_IER_RYEAR_MSK BIT(RTC_IER_RYEAR_POS) + +#define RTC_IER_RMON_POS 13U +#define RTC_IER_RMON_MSK BIT(RTC_IER_RMON_POS) + +#define RTC_IER_RDATE_POS 12U +#define RTC_IER_RDATE_MSK BIT(RTC_IER_RDATE_POS) + +#define RTC_IER_RWEEK_POS 11U +#define RTC_IER_RWEEK_MSK BIT(RTC_IER_RWEEK_POS) + +#define RTC_IER_RHOUR_POS 10U +#define RTC_IER_RHOUR_MSK BIT(RTC_IER_RHOUR_POS) + +#define RTC_IER_RMIN_POS 9U +#define RTC_IER_RMIN_MSK BIT(RTC_IER_RMIN_POS) + +#define RTC_IER_RSEC_POS 8U +#define RTC_IER_RSEC_MSK BIT(RTC_IER_RSEC_POS) + +#define RTC_IER_AMALL_POS 7U +#define RTC_IER_AMALL_MSK BIT(RTC_IER_AMALL_POS) + +#define RTC_IER_AYEAR_POS 6U +#define RTC_IER_AYEAR_MSK BIT(RTC_IER_AYEAR_POS) + +#define RTC_IER_AMON_POS 5U +#define RTC_IER_AMON_MSK BIT(RTC_IER_AMON_POS) + +#define RTC_IER_ADTAE_POS 4U +#define RTC_IER_ADTAE_MSK BIT(RTC_IER_ADTAE_POS) + +#define RTC_IER_AWEEK_POS 3U +#define RTC_IER_AWEEK_MSK BIT(RTC_IER_AWEEK_POS) + +#define RTC_IER_AHOUR_POS 2U +#define RTC_IER_AHOUR_MSK BIT(RTC_IER_AHOUR_POS) + +#define RTC_IER_AMIN_POS 1U +#define RTC_IER_AMIN_MSK BIT(RTC_IER_AMIN_POS) + +#define RTC_IER_ASEC_POS 0U +#define RTC_IER_ASEC_MSK BIT(RTC_IER_ASEC_POS) + +/****************** Bit definition for RTC_IDR register ************************/ + +#define RTC_IDR_WKTM_POS 16U +#define RTC_IDR_WKTM_MSK BIT(RTC_IDR_WKTM_POS) + +#define RTC_IDR_F1HZ_POS 15U +#define RTC_IDR_F1HZ_MSK BIT(RTC_IDR_F1HZ_POS) + +#define RTC_IDR_RYEAR_POS 14U +#define RTC_IDR_RYEAR_MSK BIT(RTC_IDR_RYEAR_POS) + +#define RTC_IDR_RMON_POS 13U +#define RTC_IDR_RMON_MSK BIT(RTC_IDR_RMON_POS) + +#define RTC_IDR_RDATE_POS 12U +#define RTC_IDR_RDATE_MSK BIT(RTC_IDR_RDATE_POS) + +#define RTC_IDR_RWEEK_POS 11U +#define RTC_IDR_RWEEK_MSK BIT(RTC_IDR_RWEEK_POS) + +#define RTC_IDR_RHOUR_POS 10U +#define RTC_IDR_RHOUR_MSK BIT(RTC_IDR_RHOUR_POS) + +#define RTC_IDR_RMIN_POS 9U +#define RTC_IDR_RMIN_MSK BIT(RTC_IDR_RMIN_POS) + +#define RTC_IDR_RSEC_POS 8U +#define RTC_IDR_RSEC_MSK BIT(RTC_IDR_RSEC_POS) + +#define RTC_IDR_AMALL_POS 7U +#define RTC_IDR_AMALL_MSK BIT(RTC_IDR_AMALL_POS) + +#define RTC_IDR_AYEAR_POS 6U +#define RTC_IDR_AYEAR_MSK BIT(RTC_IDR_AYEAR_POS) + +#define RTC_IDR_AMON_POS 5U +#define RTC_IDR_AMON_MSK BIT(RTC_IDR_AMON_POS) + +#define RTC_IDR_ADTAE_POS 4U +#define RTC_IDR_ADTAE_MSK BIT(RTC_IDR_ADTAE_POS) + +#define RTC_IDR_AWEEK_POS 3U +#define RTC_IDR_AWEEK_MSK BIT(RTC_IDR_AWEEK_POS) + +#define RTC_IDR_AHOUR_POS 2U +#define RTC_IDR_AHOUR_MSK BIT(RTC_IDR_AHOUR_POS) + +#define RTC_IDR_AMIN_POS 1U +#define RTC_IDR_AMIN_MSK BIT(RTC_IDR_AMIN_POS) + +#define RTC_IDR_ASEC_POS 0U +#define RTC_IDR_ASEC_MSK BIT(RTC_IDR_ASEC_POS) + +/****************** Bit definition for RTC_IVS register ************************/ + +#define RTC_IVS_WKTM_POS 16U +#define RTC_IVS_WKTM_MSK BIT(RTC_IVS_WKTM_POS) + +#define RTC_IVS_F1HZ_POS 15U +#define RTC_IVS_F1HZ_MSK BIT(RTC_IVS_F1HZ_POS) + +#define RTC_IVS_RYEAR_POS 14U +#define RTC_IVS_RYEAR_MSK BIT(RTC_IVS_RYEAR_POS) + +#define RTC_IVS_RMON_POS 13U +#define RTC_IVS_RMON_MSK BIT(RTC_IVS_RMON_POS) + +#define RTC_IVS_RDATE_POS 12U +#define RTC_IVS_RDATE_MSK BIT(RTC_IVS_RDATE_POS) + +#define RTC_IVS_RWEEK_POS 11U +#define RTC_IVS_RWEEK_MSK BIT(RTC_IVS_RWEEK_POS) + +#define RTC_IVS_RHOUR_POS 10U +#define RTC_IVS_RHOUR_MSK BIT(RTC_IVS_RHOUR_POS) + +#define RTC_IVS_RMIN_POS 9U +#define RTC_IVS_RMIN_MSK BIT(RTC_IVS_RMIN_POS) + +#define RTC_IVS_RSEC_POS 8U +#define RTC_IVS_RSEC_MSK BIT(RTC_IVS_RSEC_POS) + +#define RTC_IVS_AMALL_POS 7U +#define RTC_IVS_AMALL_MSK BIT(RTC_IVS_AMALL_POS) + +#define RTC_IVS_AYEAR_POS 6U +#define RTC_IVS_AYEAR_MSK BIT(RTC_IVS_AYEAR_POS) + +#define RTC_IVS_AMON_POS 5U +#define RTC_IVS_AMON_MSK BIT(RTC_IVS_AMON_POS) + +#define RTC_IVS_ADTAE_POS 4U +#define RTC_IVS_ADTAE_MSK BIT(RTC_IVS_ADTAE_POS) + +#define RTC_IVS_AWEEK_POS 3U +#define RTC_IVS_AWEEK_MSK BIT(RTC_IVS_AWEEK_POS) + +#define RTC_IVS_AHOUR_POS 2U +#define RTC_IVS_AHOUR_MSK BIT(RTC_IVS_AHOUR_POS) + +#define RTC_IVS_AMIN_POS 1U +#define RTC_IVS_AMIN_MSK BIT(RTC_IVS_AMIN_POS) + +#define RTC_IVS_ASEC_POS 0U +#define RTC_IVS_ASEC_MSK BIT(RTC_IVS_ASEC_POS) + +/****************** Bit definition for RTC_RIF register ************************/ + +#define RTC_RIF_WKTM_POS 16U +#define RTC_RIF_WKTM_MSK BIT(RTC_RIF_WKTM_POS) + +#define RTC_RIF_F1HZ_POS 15U +#define RTC_RIF_F1HZ_MSK BIT(RTC_RIF_F1HZ_POS) + +#define RTC_RIF_RYEAR_POS 14U +#define RTC_RIF_RYEAR_MSK BIT(RTC_RIF_RYEAR_POS) + +#define RTC_RIF_RMON_POS 13U +#define RTC_RIF_RMON_MSK BIT(RTC_RIF_RMON_POS) + +#define RTC_RIF_RDATE_POS 12U +#define RTC_RIF_RDATE_MSK BIT(RTC_RIF_RDATE_POS) + +#define RTC_RIF_RWEEK_POS 11U +#define RTC_RIF_RWEEK_MSK BIT(RTC_RIF_RWEEK_POS) + +#define RTC_RIF_RHOUR_POS 10U +#define RTC_RIF_RHOUR_MSK BIT(RTC_RIF_RHOUR_POS) + +#define RTC_RIF_RMIN_POS 9U +#define RTC_RIF_RMIN_MSK BIT(RTC_RIF_RMIN_POS) + +#define RTC_RIF_RSEC_POS 8U +#define RTC_RIF_RSEC_MSK BIT(RTC_RIF_RSEC_POS) + +#define RTC_RIF_AMALL_POS 7U +#define RTC_RIF_AMALL_MSK BIT(RTC_RIF_AMALL_POS) + +#define RTC_RIF_AYEAR_POS 6U +#define RTC_RIF_AYEAR_MSK BIT(RTC_RIF_AYEAR_POS) + +#define RTC_RIF_AMON_POS 5U +#define RTC_RIF_AMON_MSK BIT(RTC_RIF_AMON_POS) + +#define RTC_RIF_ADTAE_POS 4U +#define RTC_RIF_ADTAE_MSK BIT(RTC_RIF_ADTAE_POS) + +#define RTC_RIF_AWEEK_POS 3U +#define RTC_RIF_AWEEK_MSK BIT(RTC_RIF_AWEEK_POS) + +#define RTC_RIF_AHOUR_POS 2U +#define RTC_RIF_AHOUR_MSK BIT(RTC_RIF_AHOUR_POS) + +#define RTC_RIF_AMIN_POS 1U +#define RTC_RIF_AMIN_MSK BIT(RTC_RIF_AMIN_POS) + +#define RTC_RIF_ASEC_POS 0U +#define RTC_RIF_ASEC_MSK BIT(RTC_RIF_ASEC_POS) + +/****************** Bit definition for RTC_IFM register ************************/ + +#define RTC_IFM_WKTM_POS 16U +#define RTC_IFM_WKTM_MSK BIT(RTC_IFM_WKTM_POS) + +#define RTC_IFM_F1HZ_POS 15U +#define RTC_IFM_F1HZ_MSK BIT(RTC_IFM_F1HZ_POS) + +#define RTC_IFM_RYEAR_POS 14U +#define RTC_IFM_RYEAR_MSK BIT(RTC_IFM_RYEAR_POS) + +#define RTC_IFM_RMON_POS 13U +#define RTC_IFM_RMON_MSK BIT(RTC_IFM_RMON_POS) + +#define RTC_IFM_RDATE_POS 12U +#define RTC_IFM_RDATE_MSK BIT(RTC_IFM_RDATE_POS) + +#define RTC_IFM_RWEEK_POS 11U +#define RTC_IFM_RWEEK_MSK BIT(RTC_IFM_RWEEK_POS) + +#define RTC_IFM_RHOUR_POS 10U +#define RTC_IFM_RHOUR_MSK BIT(RTC_IFM_RHOUR_POS) + +#define RTC_IFM_RMIN_POS 9U +#define RTC_IFM_RMIN_MSK BIT(RTC_IFM_RMIN_POS) + +#define RTC_IFM_RSEC_POS 8U +#define RTC_IFM_RSEC_MSK BIT(RTC_IFM_RSEC_POS) + +#define RTC_IFM_AMALL_POS 7U +#define RTC_IFM_AMALL_MSK BIT(RTC_IFM_AMALL_POS) + +#define RTC_IFM_AYEAR_POS 6U +#define RTC_IFM_AYEAR_MSK BIT(RTC_IFM_AYEAR_POS) + +#define RTC_IFM_AMON_POS 5U +#define RTC_IFM_AMON_MSK BIT(RTC_IFM_AMON_POS) + +#define RTC_IFM_ADTAE_POS 4U +#define RTC_IFM_ADTAE_MSK BIT(RTC_IFM_ADTAE_POS) + +#define RTC_IFM_AWEEK_POS 3U +#define RTC_IFM_AWEEK_MSK BIT(RTC_IFM_AWEEK_POS) + +#define RTC_IFM_AHOUR_POS 2U +#define RTC_IFM_AHOUR_MSK BIT(RTC_IFM_AHOUR_POS) + +#define RTC_IFM_AMIN_POS 1U +#define RTC_IFM_AMIN_MSK BIT(RTC_IFM_AMIN_POS) + +#define RTC_IFM_ASEC_POS 0U +#define RTC_IFM_ASEC_MSK BIT(RTC_IFM_ASEC_POS) + +/****************** Bit definition for RTC_ICR register ************************/ + +#define RTC_ICR_WKTM_POS 16U +#define RTC_ICR_WKTM_MSK BIT(RTC_ICR_WKTM_POS) + +#define RTC_ICR_F1HZ_POS 15U +#define RTC_ICR_F1HZ_MSK BIT(RTC_ICR_F1HZ_POS) + +#define RTC_ICR_RYEAR_POS 14U +#define RTC_ICR_RYEAR_MSK BIT(RTC_ICR_RYEAR_POS) + +#define RTC_ICR_RMON_POS 13U +#define RTC_ICR_RMON_MSK BIT(RTC_ICR_RMON_POS) + +#define RTC_ICR_RDATE_POS 12U +#define RTC_ICR_RDATE_MSK BIT(RTC_ICR_RDATE_POS) + +#define RTC_ICR_RWEEK_POS 11U +#define RTC_ICR_RWEEK_MSK BIT(RTC_ICR_RWEEK_POS) + +#define RTC_ICR_RHOUR_POS 10U +#define RTC_ICR_RHOUR_MSK BIT(RTC_ICR_RHOUR_POS) + +#define RTC_ICR_RMIN_POS 9U +#define RTC_ICR_RMIN_MSK BIT(RTC_ICR_RMIN_POS) + +#define RTC_ICR_RSEC_POS 8U +#define RTC_ICR_RSEC_MSK BIT(RTC_ICR_RSEC_POS) + +#define RTC_ICR_AMALL_POS 7U +#define RTC_ICR_AMALL_MSK BIT(RTC_ICR_AMALL_POS) + +#define RTC_ICR_AYEAR_POS 6U +#define RTC_ICR_AYEAR_MSK BIT(RTC_ICR_AYEAR_POS) + +#define RTC_ICR_AMON_POS 5U +#define RTC_ICR_AMON_MSK BIT(RTC_ICR_AMON_POS) + +#define RTC_ICR_ADTAE_POS 4U +#define RTC_ICR_ADTAE_MSK BIT(RTC_ICR_ADTAE_POS) + +#define RTC_ICR_AWEEK_POS 3U +#define RTC_ICR_AWEEK_MSK BIT(RTC_ICR_AWEEK_POS) + +#define RTC_ICR_AHOUR_POS 2U +#define RTC_ICR_AHOUR_MSK BIT(RTC_ICR_AHOUR_POS) + +#define RTC_ICR_AMIN_POS 1U +#define RTC_ICR_AMIN_MSK BIT(RTC_ICR_AMIN_POS) + +#define RTC_ICR_ASEC_POS 0U +#define RTC_ICR_ASEC_MSK BIT(RTC_ICR_ASEC_POS) + +/****************** Bit definition for RTC_STAT register ************************/ + +#define RTC_STAT_SYNDONE_POS 1U +#define RTC_STAT_SYNDONE_MSK BIT(RTC_STAT_SYNDONE_POS) + +#define RTC_STAT_EMPTY_POS 0U +#define RTC_STAT_EMPTY_MSK BIT(RTC_STAT_EMPTY_POS) + +/****************** Bit definition for RTC_BKEN register ************************/ + +#define RTC_BKEN_BKEN_POS 0U +#define RTC_BKEN_BKEN_MSK BIT(RTC_BKEN_BKEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t WKUP; + __IO uint32_t TIME; + __IO uint32_t CAL; + __IO uint32_t ALTIME; + __IO uint32_t ALCAL; + __IO uint32_t ALEN; + __IO uint32_t TRIG; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + uint32_t RESERVED0[2] ; + __I uint32_t STAT; + __IO uint32_t BKEN; +} RTC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..0d7fbf6ccccea2d1d756f952a0416f5a88d9ede4 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h @@ -0,0 +1,444 @@ +/** + ************************************************************************************** + * @file REG_SPI.h + * @brief SPI Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __SPI_H__ +#define __SPI_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_RXFTH_POSS 14U +#define SPI_CON2_RXFTH_POSE 15U +#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) + +#define SPI_CON2_TXFTH_POSS 12U +#define SPI_CON2_TXFTH_POSE 13U +#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) + +#define SPI_CON2_FRF_POS 4U +#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) + +#define SPI_CON2_NSSP_POS 3U +#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_RXFLV_POSS 24U +#define SPI_STAT_RXFLV_POSE 28U +#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) + +#define SPI_STAT_TXFLV_POSS 16U +#define SPI_STAT_TXFLV_POSE 20U +#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) + +#define SPI_STAT_BUSY_POS 15U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_CHSIDE_POS 14U +#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) + +#define SPI_STAT_RXTH_POS 12U +#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) + +#define SPI_STAT_RXUD_POS 11U +#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) + +#define SPI_STAT_RXOV_POS 10U +#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) + +#define SPI_STAT_RXF_POS 9U +#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) + +#define SPI_STAT_RXE_POS 8U +#define SPI_STAT_RXE_MSK BIT(SPI_STAT_RXE_POS) + +#define SPI_STAT_TXTH_POS 4U +#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) + +#define SPI_STAT_TXUD_POS 3U +#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) + +#define SPI_STAT_TXOV_POS 2U +#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) + +#define SPI_STAT_TXF_POS 1U +#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) + +#define SPI_STAT_TXE_POS 0U +#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_DATA_POSS 0U +#define SPI_DATA_DATA_POSE 15U +#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_CRCPOLY_POSS 0U +#define SPI_CRCPOLY_CRCPOLY_POSE 15U +#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_RXCRC_POSS 0U +#define SPI_RXCRC_RXCRC_POSE 15U +#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_TXCRC_POSS 0U +#define SPI_TXCRC_TXCRC_POSE 15U +#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +#define SPI_I2SCFG_I2SMOD_POS 11U +#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) + +#define SPI_I2SCFG_I2SE_POS 10U +#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) + +#define SPI_I2SCFG_I2SCFG_POSS 8U +#define SPI_I2SCFG_I2SCFG_POSE 9U +#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) + +#define SPI_I2SCFG_PCMSYNC_POS 7U +#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) + +#define SPI_I2SCFG_I2SSTD_POSS 4U +#define SPI_I2SCFG_I2SSTD_POSE 5U +#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) + +#define SPI_I2SCFG_CKPOL_POS 3U +#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) + +#define SPI_I2SCFG_DATLEN_POSS 1U +#define SPI_I2SCFG_DATLEN_POSE 2U +#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) + +#define SPI_I2SCFG_CHLEN_POS 0U +#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) + +/****************** Bit definition for SPI_I2SPR register ************************/ + +#define SPI_I2SPR_EXTCKEN_POS 10U +#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) + +#define SPI_I2SPR_MCKOE_POS 9U +#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) + +#define SPI_I2SPR_ODD_POS 8U +#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) + +#define SPI_I2SPR_I2SDIV_POSS 0U +#define SPI_I2SPR_I2SDIV_POSE 7U +#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) + +/****************** Bit definition for SPI_IER register ************************/ + +#define SPI_IER_FREIE_POS 18U +#define SPI_IER_FREIE_MSK BIT(SPI_IER_FREIE_POS) + +#define SPI_IER_MODFIE_POS 17U +#define SPI_IER_MODFIE_MSK BIT(SPI_IER_MODFIE_POS) + +#define SPI_IER_CRCERRIE_POS 16U +#define SPI_IER_CRCERRIE_MSK BIT(SPI_IER_CRCERRIE_POS) + +#define SPI_IER_RXTHIE_POS 12U +#define SPI_IER_RXTHIE_MSK BIT(SPI_IER_RXTHIE_POS) + +#define SPI_IER_RXUDIE_POS 11U +#define SPI_IER_RXUDIE_MSK BIT(SPI_IER_RXUDIE_POS) + +#define SPI_IER_RXOVIE_POS 10U +#define SPI_IER_RXOVIE_MSK BIT(SPI_IER_RXOVIE_POS) + +#define SPI_IER_RXFIE_POS 9U +#define SPI_IER_RXFIE_MSK BIT(SPI_IER_RXFIE_POS) + +#define SPI_IER_TXTHIE_POS 4U +#define SPI_IER_TXTHIE_MSK BIT(SPI_IER_TXTHIE_POS) + +#define SPI_IER_TXUDIE_POS 3U +#define SPI_IER_TXUDIE_MSK BIT(SPI_IER_TXUDIE_POS) + +#define SPI_IER_TXOVIE_POS 2U +#define SPI_IER_TXOVIE_MSK BIT(SPI_IER_TXOVIE_POS) + +#define SPI_IER_TXEIE_POS 0U +#define SPI_IER_TXEIE_MSK BIT(SPI_IER_TXEIE_POS) + +/****************** Bit definition for SPI_IDR register ************************/ + +#define SPI_IDR_FREID_POS 18U +#define SPI_IDR_FREID_MSK BIT(SPI_IDR_FREID_POS) + +#define SPI_IDR_MODFID_POS 17U +#define SPI_IDR_MODFID_MSK BIT(SPI_IDR_MODFID_POS) + +#define SPI_IDR_CRCERRID_POS 16U +#define SPI_IDR_CRCERRID_MSK BIT(SPI_IDR_CRCERRID_POS) + +#define SPI_IDR_RXTHID_POS 12U +#define SPI_IDR_RXTHID_MSK BIT(SPI_IDR_RXTHID_POS) + +#define SPI_IDR_RXUDID_POS 11U +#define SPI_IDR_RXUDID_MSK BIT(SPI_IDR_RXUDID_POS) + +#define SPI_IDR_RXOVID_POS 10U +#define SPI_IDR_RXOVID_MSK BIT(SPI_IDR_RXOVID_POS) + +#define SPI_IDR_RXFID_POS 9U +#define SPI_IDR_RXFID_MSK BIT(SPI_IDR_RXFID_POS) + +#define SPI_IDR_TXTHID_POS 4U +#define SPI_IDR_TXTHID_MSK BIT(SPI_IDR_TXTHID_POS) + +#define SPI_IDR_TXUDID_POS 3U +#define SPI_IDR_TXUDID_MSK BIT(SPI_IDR_TXUDID_POS) + +#define SPI_IDR_TXOVID_POS 2U +#define SPI_IDR_TXOVID_MSK BIT(SPI_IDR_TXOVID_POS) + +#define SPI_IDR_TXEID_POS 0U +#define SPI_IDR_TXEID_MSK BIT(SPI_IDR_TXEID_POS) + +/****************** Bit definition for SPI_IVS register ************************/ + +#define SPI_IVS_FREIV_POS 18U +#define SPI_IVS_FREIV_MSK BIT(SPI_IVS_FREIV_POS) + +#define SPI_IVS_MODFIV_POS 17U +#define SPI_IVS_MODFIV_MSK BIT(SPI_IVS_MODFIV_POS) + +#define SPI_IVS_CRCERRIV_POS 16U +#define SPI_IVS_CRCERRIV_MSK BIT(SPI_IVS_CRCERRIV_POS) + +#define SPI_IVS_RXTHIV_POS 12U +#define SPI_IVS_RXTHIV_MSK BIT(SPI_IVS_RXTHIV_POS) + +#define SPI_IVS_RXUDIV_POS 11U +#define SPI_IVS_RXUDIV_MSK BIT(SPI_IVS_RXUDIV_POS) + +#define SPI_IVS_RXOVIV_POS 10U +#define SPI_IVS_RXOVIV_MSK BIT(SPI_IVS_RXOVIV_POS) + +#define SPI_IVS_RXFIV_POS 9U +#define SPI_IVS_RXFIV_MSK BIT(SPI_IVS_RXFIV_POS) + +#define SPI_IVS_TXTHIV_POS 4U +#define SPI_IVS_TXTHIV_MSK BIT(SPI_IVS_TXTHIV_POS) + +#define SPI_IVS_TXUDIV_POS 3U +#define SPI_IVS_TXUDIV_MSK BIT(SPI_IVS_TXUDIV_POS) + +#define SPI_IVS_TXOVIV_POS 2U +#define SPI_IVS_TXOVIV_MSK BIT(SPI_IVS_TXOVIV_POS) + +#define SPI_IVS_TXEIV_POS 0U +#define SPI_IVS_TXEIV_MSK BIT(SPI_IVS_TXEIV_POS) + +/****************** Bit definition for SPI_RIF register ************************/ + +#define SPI_RIF_FRERI_POS 18U +#define SPI_RIF_FRERI_MSK BIT(SPI_RIF_FRERI_POS) + +#define SPI_RIF_MODFRI_POS 17U +#define SPI_RIF_MODFRI_MSK BIT(SPI_RIF_MODFRI_POS) + +#define SPI_RIF_CRCERRRI_POS 16U +#define SPI_RIF_CRCERRRI_MSK BIT(SPI_RIF_CRCERRRI_POS) + +#define SPI_RIF_RXTHRI_POS 12U +#define SPI_RIF_RXTHRI_MSK BIT(SPI_RIF_RXTHRI_POS) + +#define SPI_RIF_RXUDRI_POS 11U +#define SPI_RIF_RXUDRI_MSK BIT(SPI_RIF_RXUDRI_POS) + +#define SPI_RIF_RXOVRI_POS 10U +#define SPI_RIF_RXOVRI_MSK BIT(SPI_RIF_RXOVRI_POS) + +#define SPI_RIF_RXFRI_POS 9U +#define SPI_RIF_RXFRI_MSK BIT(SPI_RIF_RXFRI_POS) + +#define SPI_RIF_TXTHRI_POS 4U +#define SPI_RIF_TXTHRI_MSK BIT(SPI_RIF_TXTHRI_POS) + +#define SPI_RIF_TXUDRI_POS 3U +#define SPI_RIF_TXUDRI_MSK BIT(SPI_RIF_TXUDRI_POS) + +#define SPI_RIF_TXOVRI_POS 2U +#define SPI_RIF_TXOVRI_MSK BIT(SPI_RIF_TXOVRI_POS) + +#define SPI_RIF_TXERI_POS 0U +#define SPI_RIF_TXERI_MSK BIT(SPI_RIF_TXERI_POS) + +/****************** Bit definition for SPI_IFM register ************************/ + +#define SPI_IFM_FREFM_POS 18U +#define SPI_IFM_FREFM_MSK BIT(SPI_IFM_FREFM_POS) + +#define SPI_IFM_MODFFM_POS 17U +#define SPI_IFM_MODFFM_MSK BIT(SPI_IFM_MODFFM_POS) + +#define SPI_IFM_CRCERRFM_POS 16U +#define SPI_IFM_CRCERRFM_MSK BIT(SPI_IFM_CRCERRFM_POS) + +#define SPI_IFM_RXTHFM_POS 12U +#define SPI_IFM_RXTHFM_MSK BIT(SPI_IFM_RXTHFM_POS) + +#define SPI_IFM_RXUDFM_POS 11U +#define SPI_IFM_RXUDFM_MSK BIT(SPI_IFM_RXUDFM_POS) + +#define SPI_IFM_RXOVFM_POS 10U +#define SPI_IFM_RXOVFM_MSK BIT(SPI_IFM_RXOVFM_POS) + +#define SPI_IFM_RXFFM_POS 9U +#define SPI_IFM_RXFFM_MSK BIT(SPI_IFM_RXFFM_POS) + +#define SPI_IFM_TXTHFM_POS 4U +#define SPI_IFM_TXTHFM_MSK BIT(SPI_IFM_TXTHFM_POS) + +#define SPI_IFM_TXUDFM_POS 3U +#define SPI_IFM_TXUDFM_MSK BIT(SPI_IFM_TXUDFM_POS) + +#define SPI_IFM_TXOVFM_POS 2U +#define SPI_IFM_TXOVFM_MSK BIT(SPI_IFM_TXOVFM_POS) + +#define SPI_IFM_TXEFM_POS 0U +#define SPI_IFM_TXEFM_MSK BIT(SPI_IFM_TXEFM_POS) + +/****************** Bit definition for SPI_ICR register ************************/ + +#define SPI_ICR_FREIC_POS 18U +#define SPI_ICR_FREIC_MSK BIT(SPI_ICR_FREIC_POS) + +#define SPI_ICR_MODFIC_POS 17U +#define SPI_ICR_MODFIC_MSK BIT(SPI_ICR_MODFIC_POS) + +#define SPI_ICR_CRCERRIC_POS 16U +#define SPI_ICR_CRCERRIC_MSK BIT(SPI_ICR_CRCERRIC_POS) + +#define SPI_ICR_RXTHIC_POS 12U +#define SPI_ICR_RXTHIC_MSK BIT(SPI_ICR_RXTHIC_POS) + +#define SPI_ICR_RXUDIC_POS 11U +#define SPI_ICR_RXUDIC_MSK BIT(SPI_ICR_RXUDIC_POS) + +#define SPI_ICR_RXOVIC_POS 10U +#define SPI_ICR_RXOVIC_MSK BIT(SPI_ICR_RXOVIC_POS) + +#define SPI_ICR_RXFIC_POS 9U +#define SPI_ICR_RXFIC_MSK BIT(SPI_ICR_RXFIC_POS) + +#define SPI_ICR_TXTHIC_POS 4U +#define SPI_ICR_TXTHIC_MSK BIT(SPI_ICR_TXTHIC_POS) + +#define SPI_ICR_TXUDIC_POS 3U +#define SPI_ICR_TXUDIC_MSK BIT(SPI_ICR_TXUDIC_POS) + +#define SPI_ICR_TXOVIC_POS 2U +#define SPI_ICR_TXOVIC_MSK BIT(SPI_ICR_TXOVIC_POS) + +#define SPI_ICR_TXEIC_POS 0U +#define SPI_ICR_TXEIC_MSK BIT(SPI_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __I uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; + __IO uint32_t I2SCFG; + __IO uint32_t I2SPR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} SPI_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h new file mode 100644 index 0000000000000000000000000000000000000000..675d9484c9841ad57b31a1f37ddeef6c85b4e8c8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h @@ -0,0 +1,215 @@ +/** + ************************************************************************************** + * @file REG_SYSCFG.h + * @brief SYSCFG Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __SYSCFG_H__ +#define __SYSCFG_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for SYSCFG_REMAP register ************************/ + +#define SYSCFG_REMAP_REALMOD_POSS 10U +#define SYSCFG_REMAP_REALMOD_POSE 11U +#define SYSCFG_REMAP_REALMOD_MSK BITS(SYSCFG_REMAP_REALMOD_POSS,SYSCFG_REMAP_REALMOD_POSE) + +#define SYSCFG_REMAP_EFBASE_POSS 4U +#define SYSCFG_REMAP_EFBASE_POSE 7U +#define SYSCFG_REMAP_EFBASE_MSK BITS(SYSCFG_REMAP_EFBASE_POSS,SYSCFG_REMAP_EFBASE_POSE) + +#define SYSCFG_REMAP_MEMMOD_POSS 2U +#define SYSCFG_REMAP_MEMMOD_POSE 3U +#define SYSCFG_REMAP_MEMMOD_MSK BITS(SYSCFG_REMAP_MEMMOD_POSS,SYSCFG_REMAP_MEMMOD_POSE) + +#define SYSCFG_REMAP_REMAP_POS 0U +#define SYSCFG_REMAP_REMAP_MSK BIT(SYSCFG_REMAP_REMAP_POS) + +/****************** Bit definition for SYSCFG_TRIM register ************************/ + +#define SYSCFG_TRIM_CNT_POSS 20U +#define SYSCFG_TRIM_CNT_POSE 31U +#define SYSCFG_TRIM_CNT_MSK BITS(SYSCFG_TRIM_CNT_POSS,SYSCFG_TRIM_CNT_POSE) + +#define SYSCFG_TRIM_FAIL_POS 18U +#define SYSCFG_TRIM_FAIL_MSK BIT(SYSCFG_TRIM_FAIL_POS) + +#define SYSCFG_TRIM_NOEQU_POS 17U +#define SYSCFG_TRIM_NOEQU_MSK BIT(SYSCFG_TRIM_NOEQU_POS) + +#define SYSCFG_TRIM_BUSY_POS 16U +#define SYSCFG_TRIM_BUSY_MSK BIT(SYSCFG_TRIM_BUSY_POS) + +#define SYSCFG_TRIM_HRCTRIM_POSS 8U +#define SYSCFG_TRIM_HRCTRIM_POSE 15U +#define SYSCFG_TRIM_HRCTRIM_MSK BITS(SYSCFG_TRIM_HRCTRIM_POSS,SYSCFG_TRIM_HRCTRIM_POSE) + +#define SYSCFG_TRIM_TSRC_POS 1U +#define SYSCFG_TRIM_TSRC_MSK BIT(SYSCFG_TRIM_TSRC_POS) + +#define SYSCFG_TRIM_TRIM_POS 0U +#define SYSCFG_TRIM_TRIM_MSK BIT(SYSCFG_TRIM_TRIM_POS) + +/****************** Bit definition for SYSCFG_IRSEL register ************************/ + +#define SYSCFG_IRSEL_PLR_POS 8U +#define SYSCFG_IRSEL_PLR_MSK BIT(SYSCFG_IRSEL_PLR_POS) + +#define SYSCFG_IRSEL_SEL2_POSS 4U +#define SYSCFG_IRSEL_SEL2_POSE 7U +#define SYSCFG_IRSEL_SEL2_MSK BITS(SYSCFG_IRSEL_SEL2_POSS,SYSCFG_IRSEL_SEL2_POSE) + +#define SYSCFG_IRSEL_SEL1_POSS 0U +#define SYSCFG_IRSEL_SEL1_POSE 3U +#define SYSCFG_IRSEL_SEL1_MSK BITS(SYSCFG_IRSEL_SEL1_POSS,SYSCFG_IRSEL_SEL1_POSE) + +/****************** Bit definition for SYSCFG_CFG register ************************/ + +#define SYSCFG_CFG_DBGH_EN_POSS 16U +#define SYSCFG_CFG_DBGH_EN_POSE 31U +#define SYSCFG_CFG_DBGH_EN_MSK BITS(SYSCFG_CFG_DBGH_EN_POSS,SYSCFG_CFG_DBGH_EN_POSE) + +#define SYSCFG_CFG_PVD_LCK_POS 14U +#define SYSCFG_CFG_PVD_LCK_MSK BIT(SYSCFG_CFG_PVD_LCK_POS) + +#define SYSCFG_CFG_CSS_LCK_POS 13U +#define SYSCFG_CFG_CSS_LCK_MSK BIT(SYSCFG_CFG_CSS_LCK_POS) + +#define SYSCFG_CFG_CPU_LCK_POS 12U +#define SYSCFG_CFG_CPU_LCK_MSK BIT(SYSCFG_CFG_CPU_LCK_POS) + +#define SYSCFG_CFG_VTST_POSS 8U +#define SYSCFG_CFG_VTST_POSE 9U +#define SYSCFG_CFG_VTST_MSK BITS(SYSCFG_CFG_VTST_POSS,SYSCFG_CFG_VTST_POSE) + +#define SYSCFG_CFG_NRSTREQ_POS 7U +#define SYSCFG_CFG_NRSTREQ_MSK BIT(SYSCFG_CFG_NRSTREQ_POS) + +#define SYSCFG_CFG_CURRGEN_POS 5U +#define SYSCFG_CFG_CURRGEN_MSK BIT(SYSCFG_CFG_CURRGEN_POS) + +#define SYSCFG_CFG_TEMPEN_POS 4U +#define SYSCFG_CFG_TEMPEN_MSK BIT(SYSCFG_CFG_TEMPEN_POS) + +#define SYSCFG_CFG_VREFEN_POS 3U +#define SYSCFG_CFG_VREFEN_MSK BIT(SYSCFG_CFG_VREFEN_POS) + +#define SYSCFG_CFG_VRLS_POSS 0U +#define SYSCFG_CFG_VRLS_POSE 2U +#define SYSCFG_CFG_VRLS_MSK BITS(SYSCFG_CFG_VRLS_POSS,SYSCFG_CFG_VRLS_POSE) + +/****************** Bit definition for SYSCFG_PWCON register ************************/ + +#define SYSCFG_PWCON_IOLOCK_POS 23U +#define SYSCFG_PWCON_IOLOCK_MSK BIT(SYSCFG_PWCON_IOLOCK_POS) + +#define SYSCFG_PWCON_BGTRIM_POSS 17U +#define SYSCFG_PWCON_BGTRIM_POSE 20U +#define SYSCFG_PWCON_BGTRIM_MSK BITS(SYSCFG_PWCON_BGTRIM_POSS,SYSCFG_PWCON_BGTRIM_POSE) + +#define SYSCFG_PWCON_HRCLOCK_POS 16U +#define SYSCFG_PWCON_HRCLOCK_MSK BIT(SYSCFG_PWCON_HRCLOCK_POS) + +#define SYSCFG_PWCON_HRCTRIM_POSS 8U +#define SYSCFG_PWCON_HRCTRIM_POSE 15U +#define SYSCFG_PWCON_HRCTRIM_MSK BITS(SYSCFG_PWCON_HRCTRIM_POSS,SYSCFG_PWCON_HRCTRIM_POSE) + +#define SYSCFG_PWCON_LOSCDRV_POSS 5U +#define SYSCFG_PWCON_LOSCDRV_POSE 7U +#define SYSCFG_PWCON_LOSCDRV_MSK BITS(SYSCFG_PWCON_LOSCDRV_POSS,SYSCFG_PWCON_LOSCDRV_POSE) + +#define SYSCFG_PWCON_PVDEN_POS 4U +#define SYSCFG_PWCON_PVDEN_MSK BIT(SYSCFG_PWCON_PVDEN_POS) + +#define SYSCFG_PWCON_PVLS_POSS 0U +#define SYSCFG_PWCON_PVLS_POSE 3U +#define SYSCFG_PWCON_PVLS_MSK BITS(SYSCFG_PWCON_PVLS_POSS,SYSCFG_PWCON_PVLS_POSE) + +/****************** Bit definition for SYSCFG_WKCON register ************************/ + +#define SYSCFG_WKCON_WKCLR_POS 31U +#define SYSCFG_WKCON_WKCLR_MSK BIT(SYSCFG_WKCON_WKCLR_POS) + +#define SYSCFG_WKCON_LPLS_POSS 28U +#define SYSCFG_WKCON_LPLS_POSE 30U +#define SYSCFG_WKCON_LPLS_MSK BITS(SYSCFG_WKCON_LPLS_POSS,SYSCFG_WKCON_LPLS_POSE) + +#define SYSCFG_WKCON_WKEG_POSS 16U +#define SYSCFG_WKCON_WKEG_POSE 27U +#define SYSCFG_WKCON_WKEG_MSK BITS(SYSCFG_WKCON_WKEG_POSS,SYSCFG_WKCON_WKEG_POSE) + +#define SYSCFG_WKCON_WKEN_POSS 0U +#define SYSCFG_WKCON_WKEN_POSE 11U +#define SYSCFG_WKCON_WKEN_MSK BITS(SYSCFG_WKCON_WKEN_POSS,SYSCFG_WKCON_WKEN_POSE) + +/****************** Bit definition for SYSCFG_WKSTAT register ************************/ + +#define SYSCFG_WKSTAT_FLAG_POS 16U +#define SYSCFG_WKSTAT_FLAG_MSK BIT(SYSCFG_WKSTAT_FLAG_POS) + +#define SYSCFG_WKSTAT_FG_POSS 0U +#define SYSCFG_WKSTAT_FG_POSE 11U +#define SYSCFG_WKSTAT_FG_MSK BITS(SYSCFG_WKSTAT_FG_POSS,SYSCFG_WKSTAT_FG_POSE) + +/****************** Bit definition for SYSCFG_BKREG0 register ************************/ + +#define SYSCFG_BKREG0_BKREG0_POSS 0U +#define SYSCFG_BKREG0_BKREG0_POSE 31U +#define SYSCFG_BKREG0_BKREG0_MSK BITS(SYSCFG_BKREG0_BKREG0_POSS,SYSCFG_BKREG0_BKREG0_POSE) + +/****************** Bit definition for SYSCFG_BKREG1 register ************************/ + +#define SYSCFG_BKREG1_BKREG1_POSS 0U +#define SYSCFG_BKREG1_BKREG1_POSE 31U +#define SYSCFG_BKREG1_BKREG1_MSK BITS(SYSCFG_BKREG1_BKREG1_POSS,SYSCFG_BKREG1_BKREG1_POSE) + +/****************** Bit definition for SYSCFG_BKREG2 register ************************/ + +#define SYSCFG_BKREG2_BKREG2_POSS 0U +#define SYSCFG_BKREG2_BKREG2_POSE 31U +#define SYSCFG_BKREG2_BKREG2_MSK BITS(SYSCFG_BKREG2_BKREG2_POSS,SYSCFG_BKREG2_BKREG2_POSE) + +/****************** Bit definition for SYSCFG_BKREG3 register ************************/ + +#define SYSCFG_BKREG3_BKREG3_POSS 0U +#define SYSCFG_BKREG3_BKREG3_POSE 29U +#define SYSCFG_BKREG3_BKREG3_MSK BITS(SYSCFG_BKREG3_BKREG3_POSS,SYSCFG_BKREG3_BKREG3_POSE) + +typedef struct +{ + __O uint32_t REMAP; + __O uint32_t TRIM; + __IO uint32_t IRSEL; + uint32_t RESERVED0[12] ; + __IO uint32_t CFG; + __IO uint32_t PWCON; + uint32_t RESERVED1 ; + __IO uint32_t WKCON; + __I uint32_t WKSTAT; + __IO uint32_t BKREG0; + __IO uint32_t BKREG1; + __IO uint32_t BKREG2; + __IO uint32_t BKREG3; +} SYSCFG_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h new file mode 100644 index 0000000000000000000000000000000000000000..13122aef46b42f4f92ed933d9b8a77f921cc83a3 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h @@ -0,0 +1,113 @@ +/** + ************************************************************************************** + * @file reg_TICK.h + * @brief TICK Head File + * + * @version V1.00.01 + * @date 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __TICK_H__ +#define __TICK_H__ + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for TICK_CSR register ************************/ + +#define TICK_CSR_ENABLE_POS 0U +#define TICK_CSR_ENABLE_MSK BIT(TICK_CSR_ENABLE_POS) + +#define TICK_CSR_TICKINT_POS 1U +#define TICK_CSR_TICKINT_MSK BIT(TICK_CSR_TICKINT_POS) + +#define TICK_CSR_CLKSOURCE_POS 2U +#define TICK_CSR_CLKSOURCE_MSK BIT(TICK_CSR_CLKSOURCE_POS) + +#define TICK_CSR_COUNTFLAG_POS 16U +#define TICK_CSR_COUNTFLAG_MSK BIT(TICK_CSR_COUNTFLAG_POS) + +/****************** Bit definition for TICK_RVR register ************************/ + +#define TICK_RVR_RELOAD_POSS 0U +#define TICK_RVR_RELOAD_POSE 23U +#define TICK_RVR_RELOAD_MSK BITS(TICK_RVR_RELOAD_POSS,TICK_RVR_RELOAD_POSE) + +/****************** Bit definition for TICK_CVR register ************************/ + +#define TICK_CVR_CURRENT_POSS 0U +#define TICK_CVR_CURRENT_POSE 23U +#define TICK_CVR_CURRENT_MSK BITS(TICK_CVR_CURRENT_POSS,TICK_CVR_CURRENT_POSE) + + +/****************** Bit definition for TICK_CALIB register ************************/ + +#define TICK_CALIB_TENMS_POSS 0U +#define TICK_CALIB_TENMS_POSE 23U +#define TICK_CALIB_TENMS_MSK BITS(TICK_CALIB_TENMS_POSS,TICK_CALIB_TENMS_POSE) + +#define TICK_CALIB_SKEW_POS 30U +#define TICK_CALIB_SKEW_MSK BIT(TICK_CALIB_SKEW_POS) + +#define TICK_CALIB_NOREF_POS 31U +#define TICK_CALIB_NOREF_MSK BIT(TICK_CALIB_NOREF_POS) + + +/* TICK Register */ +#define pTICK TICK + +/* TICK CSR Register(TICK_CSR) */ +#define CSR_COUNTFLAG(x) (x<<16) /* Indicates whether the counter has counted to 0 since the last read of this register + 0 timer has not counted to 0 + 1 timer has counted to 0 */ +#define CSR_CLKSOURCE(x) (x<<2) /* Indicates the SysTick clock source: + 0 SysTick uses the optional external reference clock + 1 SysTick uses the processor clock */ +#define CSR_TICKINT(x) (x<<1) /* Indicates whether counting to 0 causes the status of the SysTick exception to change to pending: + 0 count to 0 does not affect the SysTick exception status + 1 count to 0 changes the SysTick exception status to pending */ +#define CSR_ENABLE(x) (x<<0) /* /Indicates the enabled status of the SysTick counter: + 0 counter is disabled + 1 counter is operating */ + + +/* TICK RVR Register(TICK_RVR) */ +#define RVR_RELOAD(x) (x<<0) /* The value to load into the SYST_CVR register when the counter reaches 0 */ + + +/* TICK CVR Register(TICK_CVR) */ +#define CVR_CURRENT(x) (x<<0) /* Current counter value + This is the value of the counter at the time it is sampled */ + + +/* TICK CALIB Register(TICK_CALIB) */ +#define CALIB_NOREF(x) (x<<31) /* Indicates whether the IMPLEMENTATION DEFINED reference clock is provided: + 0 the reference clock is implemented + 1 the reference clock is not implemented + When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot be cleared to 0 */ +#define CALIB_SKEW(x) (x<<30) /* Indicates whether the 10ms calibration value is exact: + 0 10ms calibration value is exact + 1 10ms calibration value is inexact, because of the clock frequency */ +#define CALIB_TENMS(x) (x<<0) /* Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. + If this field is zero, the calibration value is not known */ +typedef struct +{ + __IO uint32_t CSR; /* 0x0, Control and Status */ + __IO uint32_t RVR; /* 0x4, Reload Value */ + __IO uint32_t CVR; /* 0x8, Current Value */ + __I uint32_t CALIB; /* 0xC, Calibration */ +} TICK_TypeDef; + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..1cd5670f8edf067178451720645f2d19d1478944 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h @@ -0,0 +1,606 @@ +/** + ************************************************************************************** + * @file REG_UART.h + * @brief UART Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __UART_H__ +#define __UART_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for UART_RXBUF register ************************/ + +#define UART_RXBUF_RXBUF_POSS 0U +#define UART_RXBUF_RXBUF_POSE 8U +#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) + +/****************** Bit definition for UART_TXBUF register ************************/ + +#define UART_TXBUF_TXBUF_POSS 0U +#define UART_TXBUF_TXBUF_POSE 8U +#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCON register ************************/ + +#define UART_LCON_TXEN_POS 15U +#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) + +#define UART_LCON_RXEN_POS 14U +#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) + +#define UART_LCON_DBCEN_POS 13U +#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) + +#define UART_LCON_BREAK_POS 10U +#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) + +#define UART_LCON_SWAP_POS 9U +#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) + +#define UART_LCON_TXINV_POS 8U +#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) + +#define UART_LCON_RXINV_POS 7U +#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) + +#define UART_LCON_DATAINV_POS 6U +#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) + +#define UART_LCON_MSB_POS 5U +#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) + +#define UART_LCON_PS_POS 4U +#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) + +#define UART_LCON_PE_POS 3U +#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) + +#define UART_LCON_STOP_POS 2U +#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) + +#define UART_LCON_DLS_POSS 0U +#define UART_LCON_DLS_POSE 1U +#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) + +/****************** Bit definition for UART_MCON register ************************/ + +#define UART_MCON_TXDMAEN_POS 15U +#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) + +#define UART_MCON_RXDMAEN_POS 14U +#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) + +#define UART_MCON_ABRREPT_POS 11U +#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) + +#define UART_MCON_ABRMOD_POSS 9U +#define UART_MCON_ABRMOD_POSE 10U +#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) + +#define UART_MCON_ABREN_POS 8U +#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) + +#define UART_MCON_BKREQ_POS 5U +#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) + +#define UART_MCON_HDEN_POS 4U +#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) + +#define UART_MCON_IREN_POS 3U +#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) + +#define UART_MCON_AFCEN_POS 2U +#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) + +#define UART_MCON_RTSSET_POS 1U +#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) + +#define UART_MCON_LPBKEN_POS 0U +#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) + +/****************** Bit definition for UART_RS485 register ************************/ + +#define UART_RS485_DLY_POSS 16U +#define UART_RS485_DLY_POSE 23U +#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) + +#define UART_RS485_ADDR_POSS 8U +#define UART_RS485_ADDR_POSE 15U +#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) + +#define UART_RS485_AADINV_POS 3U +#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) + +#define UART_RS485_AADACEN_POS 2U +#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) + +#define UART_RS485_AADNEN_POS 1U +#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) + +#define UART_RS485_AADEN_POS 0U +#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) + +/****************** Bit definition for UART_SCARD register ************************/ + +#define UART_SCARD_BLEN_POSS 24U +#define UART_SCARD_BLEN_POSE 31U +#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) + +#define UART_SCARD_GT_POSS 16U +#define UART_SCARD_GT_POSE 23U +#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) + +#define UART_SCARD_PSC_POSS 8U +#define UART_SCARD_PSC_POSE 15U +#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) + +#define UART_SCARD_SCCNT_POSS 3U +#define UART_SCARD_SCCNT_POSE 5U +#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) + +#define UART_SCARD_SCLKEN_POS 2U +#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) + +#define UART_SCARD_SCNACK_POS 1U +#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) + +#define UART_SCARD_SCEN_POS 0U +#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) + +/****************** Bit definition for UART_LIN register ************************/ + +#define UART_LIN_LINBKREQ_POS 2U +#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) + +#define UART_LIN_LINBDL_POS 1U +#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) + +#define UART_LIN_LINEN_POS 0U +#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_RTOEN_POS 24U +#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCON register ************************/ + +#define UART_FCON_TXFL_POSS 11U +#define UART_FCON_TXFL_POSE 15U +#define UART_FCON_TXFL_MSK BITS(UART_FCON_TXFL_POSS,UART_FCON_TXFL_POSE) + +#define UART_FCON_TXTH_POSS 9U +#define UART_FCON_TXTH_POSE 10U +#define UART_FCON_TXTH_MSK BITS(UART_FCON_TXTH_POSS,UART_FCON_TXTH_POSE) + +#define UART_FCON_TFRST_POS 8U +#define UART_FCON_TFRST_MSK BIT(UART_FCON_TFRST_POS) + +#define UART_FCON_RXFL_POSS 3U +#define UART_FCON_RXFL_POSE 7U +#define UART_FCON_RXFL_MSK BITS(UART_FCON_RXFL_POSS,UART_FCON_RXFL_POSE) + +#define UART_FCON_RXTH_POSS 1U +#define UART_FCON_RXTH_POSE 2U +#define UART_FCON_RXTH_MSK BITS(UART_FCON_RXTH_POSS,UART_FCON_RXTH_POSE) + +#define UART_FCON_RFRST_POS 0U +#define UART_FCON_RFRST_MSK BIT(UART_FCON_RFRST_POS) + +/****************** Bit definition for UART_STAT register ************************/ + +#define UART_STAT_TFOERR_POS 18U +#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) + +#define UART_STAT_TFFULL_POS 17U +#define UART_STAT_TFFULL_MSK BIT(UART_STAT_TFFULL_POS) + +#define UART_STAT_TFEMPTY_POS 16U +#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) + +#define UART_STAT_TFTH_POS 15U +#define UART_STAT_TFTH_MSK BIT(UART_STAT_TFTH_POS) + +#define UART_STAT_TSBUSY_POS 14U +#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) + +#define UART_STAT_RFUERR_POS 13U +#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) + +#define UART_STAT_RFOERR_POS 12U +#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) + +#define UART_STAT_RFFULL_POS 11U +#define UART_STAT_RFFULL_MSK BIT(UART_STAT_RFFULL_POS) + +#define UART_STAT_RFEMPTY_POS 10U +#define UART_STAT_RFEMPTY_MSK BIT(UART_STAT_RFEMPTY_POS) + +#define UART_STAT_RFTH_POS 9U +#define UART_STAT_RFTH_MSK BIT(UART_STAT_RFTH_POS) + +#define UART_STAT_RSBUSY_POS 8U +#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) + +#define UART_STAT_CTSSTA_POS 3U +#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) + +#define UART_STAT_BKERR_POS 2U +#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) + +#define UART_STAT_FERR_POS 1U +#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) + +#define UART_STAT_PERR_POS 0U +#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_TFOVER_POS 18U +#define UART_IER_TFOVER_MSK BIT(UART_IER_TFOVER_POS) + +#define UART_IER_TFEMPTY_POS 16U +#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) + +#define UART_IER_TFTH_POS 15U +#define UART_IER_TFTH_MSK BIT(UART_IER_TFTH_POS) + +#define UART_IER_TBC_POS 14U +#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) + +#define UART_IER_RFUERR_POS 13U +#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) + +#define UART_IER_RFOERR_POS 12U +#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) + +#define UART_IER_RFFULL_POS 11U +#define UART_IER_RFFULL_MSK BIT(UART_IER_RFFULL_POS) + +#define UART_IER_RFTH_POS 9U +#define UART_IER_RFTH_MSK BIT(UART_IER_RFTH_POS) + +#define UART_IER_NOISE_POS 8U +#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) + +#define UART_IER_EOB_POS 7U +#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) + +#define UART_IER_LINBK_POS 6U +#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) + +#define UART_IER_ADDRM_POS 5U +#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) + +#define UART_IER_RXTO_POS 4U +#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) + +#define UART_IER_DCTS_POS 3U +#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) + +#define UART_IER_ABTO_POS 2U +#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) + +#define UART_IER_ABEND_POS 1U +#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) + +#define UART_IER_RXBERR_POS 0U +#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_TFOVER_POS 18U +#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) + +#define UART_IDR_TFEMPTY_POS 16U +#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) + +#define UART_IDR_TFTH_POS 15U +#define UART_IDR_TFTH_MSK BIT(UART_IDR_TFTH_POS) + +#define UART_IDR_TBC_POS 14U +#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) + +#define UART_IDR_RFUERR_POS 13U +#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) + +#define UART_IDR_RFOERR_POS 12U +#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) + +#define UART_IDR_RFFULL_POS 11U +#define UART_IDR_RFFULL_MSK BIT(UART_IDR_RFFULL_POS) + +#define UART_IDR_RFTH_POS 9U +#define UART_IDR_RFTH_MSK BIT(UART_IDR_RFTH_POS) + +#define UART_IDR_NOISE_POS 8U +#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) + +#define UART_IDR_EOB_POS 7U +#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) + +#define UART_IDR_LINBK_POS 6U +#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) + +#define UART_IDR_ADDRM_POS 5U +#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) + +#define UART_IDR_RXTO_POS 4U +#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) + +#define UART_IDR_DCTS_POS 3U +#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) + +#define UART_IDR_ABTO_POS 2U +#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) + +#define UART_IDR_ABEND_POS 1U +#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) + +#define UART_IDR_RXBERR_POS 0U +#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_TFOVER_POS 18U +#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) + +#define UART_IVS_TFEMPTY_POS 16U +#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) + +#define UART_IVS_TFTH_POS 15U +#define UART_IVS_TFTH_MSK BIT(UART_IVS_TFTH_POS) + +#define UART_IVS_TBC_POS 14U +#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) + +#define UART_IVS_RFUERR_POS 13U +#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) + +#define UART_IVS_RFOERR_POS 12U +#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) + +#define UART_IVS_RFFULL_POS 11U +#define UART_IVS_RFFULL_MSK BIT(UART_IVS_RFFULL_POS) + +#define UART_IVS_RFTH_POS 9U +#define UART_IVS_RFTH_MSK BIT(UART_IVS_RFTH_POS) + +#define UART_IVS_NOISE_POS 8U +#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) + +#define UART_IVS_EOB_POS 7U +#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) + +#define UART_IVS_LINBK_POS 6U +#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) + +#define UART_IVS_ADDRM_POS 5U +#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) + +#define UART_IVS_RXTO_POS 4U +#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) + +#define UART_IVS_DCTS_POS 3U +#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) + +#define UART_IVS_ABTO_POS 2U +#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) + +#define UART_IVS_ABEND_POS 1U +#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) + +#define UART_IVS_RXBERR_POS 0U +#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_TFOVER_POS 18U +#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) + +#define UART_RIF_TFEMPTY_POS 16U +#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) + +#define UART_RIF_TFTH_POS 15U +#define UART_RIF_TFTH_MSK BIT(UART_RIF_TFTH_POS) + +#define UART_RIF_TBC_POS 14U +#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) + +#define UART_RIF_RFUERR_POS 13U +#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) + +#define UART_RIF_RFOERR_POS 12U +#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) + +#define UART_RIF_RFFULL_POS 11U +#define UART_RIF_RFFULL_MSK BIT(UART_RIF_RFFULL_POS) + +#define UART_RIF_RFTH_POS 9U +#define UART_RIF_RFTH_MSK BIT(UART_RIF_RFTH_POS) + +#define UART_RIF_NOISE_POS 8U +#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) + +#define UART_RIF_EOB_POS 7U +#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) + +#define UART_RIF_LINBK_POS 6U +#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) + +#define UART_RIF_ADDRM_POS 5U +#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) + +#define UART_RIF_RXTO_POS 4U +#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) + +#define UART_RIF_DCTS_POS 3U +#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) + +#define UART_RIF_ABTO_POS 2U +#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) + +#define UART_RIF_ABEND_POS 1U +#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) + +#define UART_RIF_RXBERR_POS 0U +#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_TFOVER_POS 18U +#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) + +#define UART_IFM_TFEMPTY_POS 16U +#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) + +#define UART_IFM_TFTH_POS 15U +#define UART_IFM_TFTH_MSK BIT(UART_IFM_TFTH_POS) + +#define UART_IFM_TBC_POS 14U +#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) + +#define UART_IFM_RFUERR_POS 13U +#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) + +#define UART_IFM_RFOERR_POS 12U +#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) + +#define UART_IFM_RFFULL_POS 11U +#define UART_IFM_RFFULL_MSK BIT(UART_IFM_RFFULL_POS) + +#define UART_IFM_RFTH_POS 9U +#define UART_IFM_RFTH_MSK BIT(UART_IFM_RFTH_POS) + +#define UART_IFM_NOISE_POS 8U +#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) + +#define UART_IFM_EOB_POS 7U +#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) + +#define UART_IFM_LINBK_POS 6U +#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) + +#define UART_IFM_ADDRM_POS 5U +#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) + +#define UART_IFM_RXTO_POS 4U +#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) + +#define UART_IFM_DCTS_POS 3U +#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) + +#define UART_IFM_ABTO_POS 2U +#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) + +#define UART_IFM_ABEND_POS 1U +#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) + +#define UART_IFM_RXBERR_POS 0U +#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_TFOVER_POS 18U +#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) + +#define UART_ICR_TFEMPTY_POS 16U +#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) + +#define UART_ICR_TFTH_POS 15U +#define UART_ICR_TFTH_MSK BIT(UART_ICR_TFTH_POS) + +#define UART_ICR_TBC_POS 14U +#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) + +#define UART_ICR_RFUERR_POS 13U +#define UART_ICR_RFUERR_MSK BIT(UART_ICR_RFUERR_POS) + +#define UART_ICR_RFOERR_POS 12U +#define UART_ICR_RFOERR_MSK BIT(UART_ICR_RFOERR_POS) + +#define UART_ICR_RFFULL_POS 11U +#define UART_ICR_RFFULL_MSK BIT(UART_ICR_RFFULL_POS) + +#define UART_ICR_RFTH_POS 9U +#define UART_ICR_RFTH_MSK BIT(UART_ICR_RFTH_POS) + +#define UART_ICR_NOISE_POS 8U +#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) + +#define UART_ICR_EOB_POS 7U +#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) + +#define UART_ICR_LINBK_POS 6U +#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) + +#define UART_ICR_ADDRM_POS 5U +#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) + +#define UART_ICR_RXTO_POS 4U +#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) + +#define UART_ICR_DCTS_POS 3U +#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) + +#define UART_ICR_ABTO_POS 2U +#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) + +#define UART_ICR_ABEND_POS 1U +#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) + +#define UART_ICR_RXBERR_POS 0U +#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) + +typedef struct +{ + __I uint32_t RXBUF; + __IO uint32_t TXBUF; + __IO uint32_t BRR; + __IO uint32_t LCON; + __IO uint32_t MCON; + __IO uint32_t RS485; + __IO uint32_t SCARD; + __IO uint32_t LIN; + __IO uint32_t RTOR; + __O uint32_t FCON; + __I uint32_t STAT; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h new file mode 100644 index 0000000000000000000000000000000000000000..96858065519d45137f8841acf4c2c9d63247eb8a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h @@ -0,0 +1,873 @@ +/** + ************************************************************************************** + * @file reg_usb.h + * @brief USB Head File + * @data 5/22/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_USB_H__ +#define __REG_USB_H__ + + +/******************************************************************************/ +/* ṹ嶨 */ +/******************************************************************************/ + +/* ṹ */ +/* #pragma anon_unions */ + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_ADDR_POSS 0U +#define USB_FADDR_ADDR_POSE 6U +#define USB_FADDR_ADDR_MSK BITS(USB_FADDR_ADDR_POSS,USB_FADDR_ADDR_POSE) + +/****************** Bit definition for USB_POWER register ************************/ + +#define USB_POWER_ISOUDT_POSS 7U +#define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POSS) + +#define USB_POWER_RESET_POSS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POSS) + +#define USB_POWER_RESUME_POSS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POSS) + +#define USB_POWER_SUSPEND_POSS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POSS) + +#define USB_POWER_SUSPENDEN_POSS 0U +#define USB_POWER_SUSPENDEN_MSK BIT(USB_POWER_SUSPENDEN_POSS) + +/****************** Bit definition for USB_DPDMCTL register ************************/ + +#define USB_DPDMCTL_DPPUD_POSS 3U +#define USB_DPDMCTL_DPPUD_POSE 4U +#define USB_DPDMCTL_DPPUD_MSK BITS(USB_DPDMCTL_DPPUD_POSS,USB_DPDMCTL_DPPUD_POSE) + +#define USB_DPDMCTL_DMPUD_POSS 1U +#define USB_DPDMCTL_DMPUD_POSE 2U +#define USB_DPDMCTL_DMPUD_MSK BITS(USB_DPDMCTL_DMPUD_POSS,USB_DPDMCTL_DMPUD_POSE) + +#define USB_DPDMCTL_PHYPWREN_POS 0U +#define USB_DPDMCTL_PHYPWREN_MSK BIT(USB_DPDMCTL_PHYPWREN_POS) + +/****************** Bit definition for USB_SWCID register ************************/ + +#define USB_SWCID_HOST_POSS 1U +#define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POSS) + +#define USB_SWCID_CIDCTRL_POSS 0U +#define USB_SWCID_CIDCTRL_MSK BIT(USB_SWCID_CIDCTRL_POSS) + +/****************** Bit definition for USB_SWVBUS register ************************/ + +#define USB_SWVBUS_VALTH_POS 3U +#define USB_SWVBUS_VALTH_MSK BIT(USB_SWVBUS_VALTH_POS) + +#define USB_SWVBUS_SESVALTH_POS 2U +#define USB_SWVBUS_SESVALTH_MSK BIT(USB_SWVBUS_SESVALTH_POS) + +#define USB_SWVBUS_SESENDTH_POS 1U +#define USB_SWVBUS_SESENDTH_MSK BIT(USB_SWVBUS_SESENDTH_POS) + +#define USB_SWVBUS_SIGCTRL_POS 0U +#define USB_SWVBUS_SIGCTRL_MSK BIT(USB_SWVBUS_SIGCTRL_POS) + +/****************** Bit definition for USB_TMODE register ************************/ + +#define USB_TMODE_PROTECT_POSS 1U +#define USB_TMODE_PROTECT_POSE 7U +#define USB_TMODE_PROTECT_MSK BITS(USB_TMODE_PROTECT_POSS,USB_TMODE_PROTECT_POSE) + +#define USB_TMODE_ENABLE_POS 0U +#define USB_TMODE_ENABLE_MSK BIT(USB_TMODE_ENABLE_POS) + +/****************** Bit definition for USB_FRAME1 register ************************/ + +#define USB_FRAME1_LOWFRAME_POSS 0U +#define USB_FRAME1_LOWFRAME_POSE 7U +#define USB_FRAME1_LOWFRAME_MSK BITS(USB_FRAME1_LOWFRAME_POSS,USB_FRAME1_LOWFRAME_POSE) + +/****************** Bit definition for USB_FRAME2 register ************************/ + +#define USB_FRAME2_UPFRAME_POSS 0U +#define USB_FRAME2_UPFRAME_POSE 2U +#define USB_FRAME2_UPFRAME_MSK BITS(USB_FRAME2_UPFRAME_POSS,USB_FRAME2_UPFRAME_POSE) + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EPTIDX_POSS 0U +#define USB_INDEX_EPTIDX_POSE 3U +#define USB_INDEX_EPTIDX_MSK BITS(USB_INDEX_EPTIDX_POSS,USB_INDEX_EPTIDX_POSE) + +/****************** Bit definition for USB_DEVCTRL register ************************/ + +#define USB_DEVCTRL_FSDEV_POS 6U +#define USB_DEVCTRL_FSDEV_MSK BIT(USB_DEVCTRL_FSDEV_POS) + +#define USB_DEVCTRL_LSDEV_POS 5U +#define USB_DEVCTRL_LSDEV_MSK BIT(USB_DEVCTRL_LSDEV_POS) + +#define USB_DEVCTRL_HOST_POS 2U +#define USB_DEVCTRL_HOST_MSK BIT(USB_DEVCTRL_HOST_POS) + +#define USB_DEVCTRL_HOSTREQ_POS 1U +#define USB_DEVCTRL_HOSTREQ_MSK BIT(USB_DEVCTRL_HOSTREQ_POS) + +#define USB_DEVCTRL_SESSION_POS 0U +#define USB_DEVCTRL_SESSION_MSK BIT(USB_DEVCTRL_SESSION_POS) + +/****************** Bit definition for USB_TXMAXP register ************************/ + +#define USB_TXMAXP_MAXSIZE_POSS 0U +#define USB_TXMAXP_MAXSIZE_POSE 7U +#define USB_TXMAXP_MAXSIZE_MSK BITS(USB_TXMAXP_MAXSIZE_POSS,USB_TXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_CSR0L_TXCSRL register ************************/ + +// +//Endpoint 0 +// +/* host mode */ +#define USB_CSR0L_TXCSRL_NAKTO_POS 7U +#define USB_CSR0L_TXCSRL_NAKTO_MSK BIT(USB_CSR0L_TXCSRL_NAKTO_POS) + +#define USB_CSR0L_TXCSRL_STATUSPKT_POS 6U +#define USB_CSR0L_TXCSRL_STATUSPKT_MSK BIT(USB_CSR0L_TXCSRL_STATUSPKT_POS) + +#define USB_CSR0L_TXCSRL_REQPKT_POS 5U +#define USB_CSR0L_TXCSRL_REQPKT_MSK BIT(USB_CSR0L_TXCSRL_REQPKT_POS) + +#define USB_CSR0L_TXCSRL_ERROR_POS 4U +#define USB_CSR0L_TXCSRL_ERROR_MSK BIT(USB_CSR0L_TXCSRL_ERROR_POS) + +#define USB_CSR0L_TXCSRL_SETUPPKT_POS 3U +#define USB_CSR0L_TXCSRL_SETUPPKT_MSK BIT(USB_CSR0L_TXCSRL_SETUPPKT_POS) + +/* device mode */ +#define USB_CSR0L_TXCSRL_SETENDC_POS 7U +#define USB_CSR0L_TXCSRL_SETENDC_MSK BIT(USB_CSR0L_TXCSRL_SETENDC_POS) + +#define USB_CSR0L_TXCSRL_RXRDYC_POS 6U +#define USB_CSR0L_TXCSRL_RXRDYC_MSK BIT(USB_CSR0L_TXCSRL_RXRDYC_POS) + +#define USB_CSR0L_TXCSRL_STALL_POS 5U +#define USB_CSR0L_TXCSRL_STALL_MSK BIT(USB_CSR0L_TXCSRL_STALL_POS) + +#define USB_CSR0L_TXCSRL_SETEND_POS 4U +#define USB_CSR0L_TXCSRL_SETEND_MSK BIT(USB_CSR0L_TXCSRL_SETEND_POS) + +#define USB_CSR0L_TXCSRL_DATAEND_POS 3U +#define USB_CSR0L_TXCSRL_DATAEND_MSK BIT(USB_CSR0L_TXCSRL_DATAEND_POS) + +#define USB_CSR0L_TXCSRL_STALLED_POS 2U +#define USB_CSR0L_TXCSRL_STALLED_MSK BIT(USB_CSR0L_TXCSRL_STALLED_POS) + +#define USB_CSR0L_TXCSRL_TXRDY_POS 1U +#define USB_CSR0L_TXCSRL_TXRDY_MSK BIT(USB_CSR0L_TXCSRL_TXRDY_POS) + +#define USB_CSR0L_TXCSRL_RXRDY_POS 0U +#define USB_CSR0L_TXCSRL_RXRDY_MSK BIT(USB_CSR0L_TXCSRL_RXRDY_POS) + +// +//Endpoint 1-6 +// +/* host mode */ +#define USB_CSR0L_TXCSRL_NACKOUT_POS 7U +#define USB_CSR0L_TXCSRL_NACKOUT_MSK BIT(USB_CSR0L_TXCSRL_NACKOUT_POS) + +#define USB_CSR0L_TXCSRL_CLRDATAT_POS 6U +#define USB_CSR0L_TXCSRL_CLRDATAT_MSK BIT(USB_CSR0L_TXCSRL_CLRDATAT_POS) + +#define USB_CSR0L_TXCSRL_RXSTALL_POS 5U +#define USB_CSR0L_TXCSRL_RXSTALL_MSK BIT(USB_CSR0L_TXCSRL_RXSTALL_POS) + +#define USB_CSR0L_TXCSRL_TXPKTRDY_POS 0U +#define USB_CSR0L_TXCSRL_TXPKTRDY_MSK BIT(USB_CSR0L_TXCSRL_TXPKTRDY_POS) + +/* device mode */ +#define USB_CSR0L_TXCSRL_INCOMPTX_POS 7U +#define USB_CSR0L_TXCSRL_INCOMPTX_MSK BIT(USB_CSR0L_TXCSRL_INCOMPTX_POS) + +#define USB_CSR0L_TXCSRL_CLRDATAT_POS 6U +#define USB_CSR0L_TXCSRL_CLRDATAT_MSK BIT(USB_CSR0L_TXCSRL_CLRDATAT_POS) + +#define USB_CSR0L_TXCSRL_SENTSTALL_POS 5U +#define USB_CSR0L_TXCSRL_SENTSTALL_MSK BIT(USB_CSR0L_TXCSRL_SENTSTALL_POS) + +#define USB_CSR0L_TXCSRL_SENDSTALL_POS 4U +#define USB_CSR0L_TXCSRL_SENDSTALL_MSK BIT(USB_CSR0L_TXCSRL_SENDSTALL_POS) + +#define USB_CSR0L_TXCSRL_FLUSHFIFO_POS 3U +#define USB_CSR0L_TXCSRL_FLUSHFIFO_MSK BIT(USB_CSR0L_TXCSRL_FLUSHFIFO_POS) + +#define USB_CSR0L_TXCSRL_UNDERRUN_POS 2U +#define USB_CSR0L_TXCSRL_UNDERRUN_MSK BIT(USB_CSR0L_TXCSRL_UNDERRUN_POS) + +#define USB_CSR0L_TXCSRL_FIFONE_POS 1U +#define USB_CSR0L_TXCSRL_FIFONE_MSK BIT(USB_CSR0L_TXCSRL_FIFONE_POS) + +#define USB_CSR0L_TXCSRL_TXPKTRDY_POS 0U +#define USB_CSR0L_TXCSRL_TXPKTRDY_MSK BIT(USB_CSR0L_TXCSRL_TXPKTRDY_POS) + +/****************** Bit definition for USB_CSR0H_TXCSRH register ************************/ +// +//For endpoint 0 +// +#define USB_CSR0H_TXCSRH_FLUSH_POS 0U +#define USB_CSR0H_TXCSRH_FLUSH_MSK BIT(USB_CSR0H_TXCSRH_FLUSH_POS) + +// +//For endpoint 1-6 +// +#define USB_CSR0H_TXCSRH_AUTOSET_POS 7U +#define USB_CSR0H_TXCSRH_AUTOSET_MSK BIT(USB_CSR0H_TXCSRH_AUTOSET_POS) + +#define USB_CSR0H_TXCSRH_ISO_POS 6U +#define USB_CSR0H_TXCSRH_ISO_MSK BIT(USB_CSR0H_TXCSRH_ISO_POS) + +#define USB_CSR0H_TXCSRH_MODE_POS 5U +#define USB_CSR0H_TXCSRH_MODE_MSK BIT(USB_CSR0H_TXCSRH_MODE_POS) + +#define USB_CSR0H_TXCSRH_FDT_POS 3U +#define USB_CSR0H_TXCSRH_FDT_MSK BIT(USB_CSR0H_TXCSRH_FDT_POS) + +/****************** Bit definition for USB_RXMAXP register ************************/ + +#define USB_RXMAXP_MAXSIZE_POSS 0U +#define USB_RXMAXP_MAXSIZE_POSE 7U +#define USB_RXMAXP_MAXSIZE_MSK BITS(USB_RXMAXP_MAXSIZE_POSS,USB_RXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_RXCSRL register ************************/ + +#define USB_RXCSRL_CLRDT_POS 7U +#define USB_RXCSRL_CLRDT_MSK BIT(USB_RXCSRL_CLRDT_POS) + +#define USB_RXCSRL_STALLED_POS 6U +#define USB_RXCSRL_STALLED_MSK BIT(USB_RXCSRL_STALLED_POS) + +#define USB_RXCSRL_REQPKT_POS 5U +#define USB_RXCSRL_REQPKT_MSK BIT(USB_RXCSRL_REQPKT_POS) + +#define USB_RXCSRL_STALL_POS 5U +#define USB_RXCSRL_STALL_MSK BIT(USB_RXCSRL_STALL_POS) + +#define USB_RXCSRL_FLUSH_POS 4U +#define USB_RXCSRL_FLUSH_MSK BIT(USB_RXCSRL_FLUSH_POS) + +#define USB_RXCSRL_DATAERR_NAKTO_POS 3U +#define USB_RXCSRL_DATAERR_NAKTO_MSK BIT(USB_RXCSRL_DATAERR_NAKTO_POS) + +#define USB_RXCSRL_ERROR_POS 2U +#define USB_RXCSRL_ERROR_MSK BIT(USB_RXCSRL_ERROR_POS) + +#define USB_RXCSRL_OVERRUN_POS 2U +#define USB_RXCSRL_OVERRUN_MSK BIT(USB_RXCSRL_OVERRUN_POS) + +#define USB_RXCSRL_FULL_POS 1U +#define USB_RXCSRL_FULL_MSK BIT(USB_RXCSRL_FULL_POS) + +#define USB_RXCSRL_RXRDY_POS 0U +#define USB_RXCSRL_RXRDY_MSK BIT(USB_RXCSRL_RXRDY_POS) + +/****************** Bit definition for USB_RXCSRH register ************************/ + +#define USB_RXCSRH_AUTOCLR_POS 7U +#define USB_RXCSRH_AUTOCLR_MSK BIT(USB_RXCSRH_AUTOCLR_POS) + +#define USB_RXCSRH_AUTOREQ_POS 6U +#define USB_RXCSRH_AUTOREQ_MSK BIT(USB_RXCSRH_AUTOREQ_POS) + +#define USB_RXCSRH_ISO_POS 6U +#define USB_RXCSRH_ISO_MSK BIT(USB_RXCSRH_ISO_POS) + +/****************** Bit definition for USB_RXCOUNT1 register ************************/ + +#define USB_RXCOUNT1_COUNT_POSS 0U +#define USB_RXCOUNT1_COUNT_POSE 6U +#define USB_RXCOUNT1_COUNT_MSK BITS(USB_RXCOUNT1_COUNT_POSS,USB_RXCOUNT1_COUNT_POSE) + +#define USB_RXCOUNT1_PKTLOW_POSS 0U +#define USB_RXCOUNT1_PKTLOW_POSE 7U +#define USB_RXCOUNT1_PKTLOW_MSK BITS(USB_RXCOUNT1_PKTLOW_POSS,USB_RXCOUNT1_PKTLOW_POSE) + +/****************** Bit definition for USB_RXCOUNT2 register ************************/ + +#define USB_RXCOUNT2_PKTHIGH_POSS 0U +#define USB_RXCOUNT2_PKTHIGH_POSE 2U +#define USB_RXCOUNT2_PKTHIGH_MSK BITS(USB_RXCOUNT2_PKTHIGH_POSS,USB_RXCOUNT2_PKTHIGH_POSE) + +/****************** Bit definition for USB_TXTYPE register ************************/ + +#define USB_TXTYPE_PROTOCOL_POSS 4U +#define USB_TXTYPE_PROTOCOL_POSE 5U +#define USB_TXTYPE_PROTOCOL_MSK BITS(USB_TXTYPE_PROTOCOL_POSS,USB_TXTYPE_PROTOCOL_POSE) + +#define USB_TXTYPE_TEPN_POSS 0U +#define USB_TXTYPE_TEPN_POSE 3U +#define USB_TXTYPE_TEPN_MSK BITS(USB_TXTYPE_TEPN_POSS,USB_TXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_NAKLIMIT0_TXINTERVAL register ************************/ + +#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSS 0U +#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSE 7U +#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_MSK BITS(USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSS,USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_RXTYPE register ************************/ + +#define USB_RXTYPE_PROTOCOL_POSS 4U +#define USB_RXTYPE_PROTOCOL_POSE 5U +#define USB_RXTYPE_PROTOCOL_MSK BITS(USB_RXTYPE_PROTOCOL_POSS,USB_RXTYPE_PROTOCOL_POSE) + +#define USB_RXTYPE_TEPN_POSS 0U +#define USB_RXTYPE_TEPN_POSE 3U +#define USB_RXTYPE_TEPN_MSK BITS(USB_RXTYPE_TEPN_POSS,USB_RXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_RXINTERVAL register ************************/ + +#define USB_RXINTERVAL_NAKLMT_POSS 0U +#define USB_RXINTERVAL_NAKLMT_POSE 7U +#define USB_RXINTERVAL_NAKLMT_MSK BITS(USB_RXINTERVAL_NAKLMT_POSS,USB_RXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_TXFIFO1 register ************************/ + +#define USB_TXFIFO1_ADDRL_POSS 0U +#define USB_TXFIFO1_ADDRL_POSE 7U +#define USB_TXFIFO1_ADDRL_MSK BITS(USB_TXFIFO1_ADDRL_POSS,USB_TXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_TXFIFO2 register ************************/ + +#define USB_TXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_TXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_TXFIFO2_MAXPKTSIZE_MSK BITS(USB_TXFIFO2_MAXPKTSIZE_POSS,USB_TXFIFO2_MAXPKTSIZE_POSE) + +#define USB_TXFIFO2_DPB_POS 4U +#define USB_TXFIFO2_DPB_MSK BIT(USB_TXFIFO2_DPB_POS) + +#define USB_TXFIFO2_ADDRH_POSS 0U +#define USB_TXFIFO2_ADDRH_POSE 3U +#define USB_TXFIFO2_ADDRH_MSK BITS(USB_TXFIFO2_ADDRH_POSS,USB_TXFIFO2_ADDRH_POSE) + +/****************** Bit definition for USB_RXFIFO1 register ************************/ + +#define USB_RXFIFO1_ADDRL_POSS 0U +#define USB_RXFIFO1_ADDRL_POSE 7U +#define USB_RXFIFO1_ADDRL_MSK BITS(USB_RXFIFO1_ADDRL_POSS,USB_RXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_RXFIFO2 register ************************/ + +#define USB_RXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_RXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_RXFIFO2_MAXPKTSIZE_MSK BITS(USB_RXFIFO2_MAXPKTSIZE_POSS,USB_RXFIFO2_MAXPKTSIZE_POSE) + +#define USB_RXFIFO2_DPB_POS 4U +#define USB_RXFIFO2_DPB_MSK BIT(USB_RXFIFO2_DPB_POS) + +#define USB_RXFIFO2_ADDRH_POSS 0U +#define USB_RXFIFO2_ADDRH_POSE 3U +#define USB_RXFIFO2_ADDRH_MSK BITS(USB_RXFIFO2_ADDRH_POSS,USB_RXFIFO2_ADDRH_POSE) + +/************* Bit definition for USB_EP0FIFO/USB_EPxFIFO register *****************/ + +#define USB_EPxFIFO_FIFO_POSS 0U +#define USB_EPxFIFO_FIFO_POSE 7U +#define USB_EPxFIFO_FIFO_MSK BITS(USB_EPxFIFO_FIFO_POSS,USB_EPxFIFO_FIFO_POSE) + +/****************** Bit definition for USB_TXIER register ************************/ + +#define USB_TXIER_EP6IE_POS 6U +#define USB_TXIER_EP6IE_MSK BIT(USB_TXIER_EP6IE_POS) + +#define USB_TXIER_EP5IE_POS 5U +#define USB_TXIER_EP5IE_MSK BIT(USB_TXIER_EP5IE_POS) + +#define USB_TXIER_EP4IE_POS 4U +#define USB_TXIER_EP4IE_MSK BIT(USB_TXIER_EP4IE_POS) + +#define USB_TXIER_EP3IE_POS 3U +#define USB_TXIER_EP3IE_MSK BIT(USB_TXIER_EP3IE_POS) + +#define USB_TXIER_EP2IE_POS 2U +#define USB_TXIER_EP2IE_MSK BIT(USB_TXIER_EP2IE_POS) + +#define USB_TXIER_EP1IE_POS 1U +#define USB_TXIER_EP1IE_MSK BIT(USB_TXIER_EP1IE_POS) + +#define USB_TXIER_EP0IE_POS 0U +#define USB_TXIER_EP0IE_MSK BIT(USB_TXIER_EP0IE_POS) + +/****************** Bit definition for USB_RXIER register ************************/ + +#define USB_RXIER_EP6IE_POS 6U +#define USB_RXIER_EP6IE_MSK BIT(USB_RXIER_EP6IE_POS) + +#define USB_RXIER_EP5IE_POS 5U +#define USB_RXIER_EP5IE_MSK BIT(USB_RXIER_EP5IE_POS) + +#define USB_RXIER_EP4IE_POS 4U +#define USB_RXIER_EP4IE_MSK BIT(USB_RXIER_EP4IE_POS) + +#define USB_RXIER_EP3IE_POS 3U +#define USB_RXIER_EP3IE_MSK BIT(USB_RXIER_EP3IE_POS) + +#define USB_RXIER_EP2IE_POS 2U +#define USB_RXIER_EP2IE_MSK BIT(USB_RXIER_EP2IE_POS) + +#define USB_RXIER_EP1IE_POS 1U +#define USB_RXIER_EP1IE_MSK BIT(USB_RXIER_EP1IE_POS) + +/****************** Bit definition for USB_TXIDR register ************************/ + +#define USB_TXIDR_EP6ID_POS 6U +#define USB_TXIDR_EP6ID_MSK BIT(USB_TXIDR_EP6ID_POS) + +#define USB_TXIDR_EP5ID_POS 5U +#define USB_TXIDR_EP5ID_MSK BIT(USB_TXIDR_EP5ID_POS) + +#define USB_TXIDR_EP4ID_POS 4U +#define USB_TXIDR_EP4ID_MSK BIT(USB_TXIDR_EP4ID_POS) + +#define USB_TXIDR_EP3ID_POS 3U +#define USB_TXIDR_EP3ID_MSK BIT(USB_TXIDR_EP3ID_POS) + +#define USB_TXIDR_EP2ID_POS 2U +#define USB_TXIDR_EP2ID_MSK BIT(USB_TXIDR_EP2ID_POS) + +#define USB_TXIDR_EP1ID_POS 1U +#define USB_TXIDR_EP1ID_MSK BIT(USB_TXIDR_EP1ID_POS) + +#define USB_TXIDR_EP0ID_POS 0U +#define USB_TXIDR_EP0ID_MSK BIT(USB_TXIDR_EP0ID_POS) + +/****************** Bit definition for USB_RXIDR register ************************/ + +#define USB_RXIDR_EP6ID_POS 6U +#define USB_RXIDR_EP6ID_MSK BIT(USB_RXIDR_EP6ID_POS) + +#define USB_RXIDR_EP5ID_POS 5U +#define USB_RXIDR_EP5ID_MSK BIT(USB_RXIDR_EP5ID_POS) + +#define USB_RXIDR_EP4ID_POS 4U +#define USB_RXIDR_EP4ID_MSK BIT(USB_RXIDR_EP4ID_POS) + +#define USB_RXIDR_EP3ID_POS 3U +#define USB_RXIDR_EP3ID_MSK BIT(USB_RXIDR_EP3ID_POS) + +#define USB_RXIDR_EP2ID_POS 2U +#define USB_RXIDR_EP2ID_MSK BIT(USB_RXIDR_EP2ID_POS) + +#define USB_RXIDR_EP1ID_POS 1U +#define USB_RXIDR_EP1ID_MSK BIT(USB_RXIDR_EP1ID_POS) + +/****************** Bit definition for USB_TXIVS register ************************/ + +#define USB_TXIVS_EP6IVS_POS 6U +#define USB_TXIVS_EP6IVS_MSK BIT(USB_TXIVS_EP6IVS_POS) + +#define USB_TXIVS_EP5IVS_POS 5U +#define USB_TXIVS_EP5IVS_MSK BIT(USB_TXIVS_EP5IVS_POS) + +#define USB_TXIVS_EP4IVS_POS 4U +#define USB_TXIVS_EP4IVS_MSK BIT(USB_TXIVS_EP4IVS_POS) + +#define USB_TXIVS_EP3IVS_POS 3U +#define USB_TXIVS_EP3IVS_MSK BIT(USB_TXIVS_EP3IVS_POS) + +#define USB_TXIVS_EP2IVS_POS 2U +#define USB_TXIVS_EP2IVS_MSK BIT(USB_TXIVS_EP2IVS_POS) + +#define USB_TXIVS_EP1IVS_POS 1U +#define USB_TXIVS_EP1IVS_MSK BIT(USB_TXIVS_EP1IVS_POS) + +#define USB_TXIVS_EP0IVS_POS 0U +#define USB_TXIVS_EP0IVS_MSK BIT(USB_TXIVS_EP0IVS_POS) + +/****************** Bit definition for USB_RXIVS register ************************/ + +#define USB_RXIVS_EP6IVS_POS 6U +#define USB_RXIVS_EP6IVS_MSK BIT(USB_RXIVS_EP6IVS_POS) + +#define USB_RXIVS_EP5IVS_POS 5U +#define USB_RXIVS_EP5IVS_MSK BIT(USB_RXIVS_EP5IVS_POS) + +#define USB_RXIVS_EP4IVS_POS 4U +#define USB_RXIVS_EP4IVS_MSK BIT(USB_RXIVS_EP4IVS_POS) + +#define USB_RXIVS_EP3IVS_POS 3U +#define USB_RXIVS_EP3IVS_MSK BIT(USB_RXIVS_EP3IVS_POS) + +#define USB_RXIVS_EP2IVS_POS 2U +#define USB_RXIVS_EP2IVS_MSK BIT(USB_RXIVS_EP2IVS_POS) + +#define USB_RXIVS_EP1IVS_POS 1U +#define USB_RXIVS_EP1IVS_MSK BIT(USB_RXIVS_EP1IVS_POS) + +/****************** Bit definition for USB_TXRIF register ************************/ + +#define USB_TXRIF_EP6RIF_POS 6U +#define USB_TXRIF_EP6RIF_MSK BIT(USB_TXRIF_EP6RIF_POS) + +#define USB_TXRIF_EP5RIF_POS 5U +#define USB_TXRIF_EP5RIF_MSK BIT(USB_TXRIF_EP5RIF_POS) + +#define USB_TXRIF_EP4RIF_POS 4U +#define USB_TXRIF_EP4RIF_MSK BIT(USB_TXRIF_EP4RIF_POS) + +#define USB_TXRIF_EP3RIF_POS 3U +#define USB_TXRIF_EP3RIF_MSK BIT(USB_TXRIF_EP3RIF_POS) + +#define USB_TXRIF_EP2RIF_POS 2U +#define USB_TXRIF_EP2RIF_MSK BIT(USB_TXRIF_EP2RIF_POS) + +#define USB_TXRIF_EP1RIF_POS 1U +#define USB_TXRIF_EP1RIF_MSK BIT(USB_TXRIF_EP1RIF_POS) + +#define USB_TXRIF_EP0RIF_POS 0U +#define USB_TXRIF_EP0RIF_MSK BIT(USB_TXRIF_EP0RIF_POS) + +/****************** Bit definition for USB_RXRIF register ************************/ + +#define USB_RXRIF_EP6RIF_POS 6U +#define USB_RXRIF_EP6RIF_MSK BIT(USB_RXRIF_EP6RIF_POS) + +#define USB_RXRIF_EP5RIF_POS 5U +#define USB_RXRIF_EP5RIF_MSK BIT(USB_RXRIF_EP5RIF_POS) + +#define USB_RXRIF_EP4RIF_POS 4U +#define USB_RXRIF_EP4RIF_MSK BIT(USB_RXRIF_EP4RIF_POS) + +#define USB_RXRIF_EP3RIF_POS 3U +#define USB_RXRIF_EP3RIF_MSK BIT(USB_RXRIF_EP3RIF_POS) + +#define USB_RXRIF_EP2RIF_POS 2U +#define USB_RXRIF_EP2RIF_MSK BIT(USB_RXRIF_EP2RIF_POS) + +#define USB_RXRIF_EP1RIF_POS 1U +#define USB_RXRIF_EP1RIF_MSK BIT(USB_RXRIF_EP1RIF_POS) + +/****************** Bit definition for USB_TXIFM register ************************/ + +#define USB_TXIFM_EP6IFM_POS 6U +#define USB_TXIFM_EP6IFM_MSK BIT(USB_TXIFM_EP6IFM_POS) + +#define USB_TXIFM_EP5IFM_POS 5U +#define USB_TXIFM_EP5IFM_MSK BIT(USB_TXIFM_EP5IFM_POS) + +#define USB_TXIFM_EP4IFM_POS 4U +#define USB_TXIFM_EP4IFM_MSK BIT(USB_TXIFM_EP4IFM_POS) + +#define USB_TXIFM_EP3IFM_POS 3U +#define USB_TXIFM_EP3IFM_MSK BIT(USB_TXIFM_EP3IFM_POS) + +#define USB_TXIFM_EP2IFM_POS 2U +#define USB_TXIFM_EP2IFM_MSK BIT(USB_TXIFM_EP2IFM_POS) + +#define USB_TXIFM_EP1IFM_POS 1U +#define USB_TXIFM_EP1IFM_MSK BIT(USB_TXIFM_EP1IFM_POS) + +#define USB_TXIFM_EP0IFM_POS 0U +#define USB_TXIFM_EP0IFM_MSK BIT(USB_TXIFM_EP0IFM_POS) + +/****************** Bit definition for USB_RXIFM register ************************/ + +#define USB_RXIFM_EP6IFM_POS 6U +#define USB_RXIFM_EP6IFM_MSK BIT(USB_RXIFM_EP6IFM_POS) + +#define USB_RXIFM_EP5IFM_POS 5U +#define USB_RXIFM_EP5IFM_MSK BIT(USB_RXIFM_EP5IFM_POS) + +#define USB_RXIFM_EP4IFM_POS 4U +#define USB_RXIFM_EP4IFM_MSK BIT(USB_RXIFM_EP4IFM_POS) + +#define USB_RXIFM_EP3IFM_POS 3U +#define USB_RXIFM_EP3IFM_MSK BIT(USB_RXIFM_EP3IFM_POS) + +#define USB_RXIFM_EP2IFM_POS 2U +#define USB_RXIFM_EP2IFM_MSK BIT(USB_RXIFM_EP2IFM_POS) + +#define USB_RXIFM_EP1IFM_POS 1U +#define USB_RXIFM_EP1IFM_MSK BIT(USB_RXIFM_EP1IFM_POS) + +/****************** Bit definition for USB_TXICR register ************************/ + +#define USB_TXICR_EP6ICR_POS 6U +#define USB_TXICR_EP6ICR_MSK BIT(USB_TXICR_EP6ICR_POS) + +#define USB_TXICR_EP5ICR_POS 5U +#define USB_TXICR_EP5ICR_MSK BIT(USB_TXICR_EP5ICR_POS) + +#define USB_TXICR_EP4ICR_POS 4U +#define USB_TXICR_EP4ICR_MSK BIT(USB_TXICR_EP4ICR_POS) + +#define USB_TXICR_EP3ICR_POS 3U +#define USB_TXICR_EP3ICR_MSK BIT(USB_TXICR_EP3ICR_POS) + +#define USB_TXICR_EP2ICR_POS 2U +#define USB_TXICR_EP2ICR_MSK BIT(USB_TXICR_EP2ICR_POS) + +#define USB_TXICR_EP1ICR_POS 1U +#define USB_TXICR_EP1ICR_MSK BIT(USB_TXICR_EP1ICR_POS) + +#define USB_TXICR_EP0ICR_POS 0U +#define USB_TXICR_EP0ICR_MSK BIT(USB_TXICR_EP0ICR_POS) + +/****************** Bit definition for USB_RXICR register ************************/ + +#define USB_RXICR_EP6ICR_POS 6U +#define USB_RXICR_EP6ICR_MSK BIT(USB_RXICR_EP6ICR_POS) + +#define USB_RXICR_EP5ICR_POS 5U +#define USB_RXICR_EP5ICR_MSK BIT(USB_RXICR_EP5ICR_POS) + +#define USB_RXICR_EP4ICR_POS 4U +#define USB_RXICR_EP4ICR_MSK BIT(USB_RXICR_EP4ICR_POS) + +#define USB_RXICR_EP3ICR_POS 3U +#define USB_RXICR_EP3ICR_MSK BIT(USB_RXICR_EP3ICR_POS) + +#define USB_RXICR_EP2ICR_POS 2U +#define USB_RXICR_EP2ICR_MSK BIT(USB_RXICR_EP2ICR_POS) + +#define USB_RXICR_EP1ICR_POS 1U +#define USB_RXICR_EP1ICR_MSK BIT(USB_RXICR_EP1ICR_POS) + +/****************** Bit definition for USB_IER register ************************/ + +#define USB_IER_SESREQIE_POS 6U +#define USB_IER_SESREQIE_MSK BIT(USB_IER_SESREQIE_POS) + +#define USB_IER_DISCONIE_POS 5U +#define USB_IER_DISCONIE_MSK BIT(USB_IER_DISCONIE_POS) + +#define USB_IER_CONIE_POS 4U +#define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS) + +#define USB_IER_SOFIE_POS 3U +#define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS) + +#define USB_IER_BABIE_POS 2U +#define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS) + +#define USB_IER_RESTIE_POS 2U +#define USB_IER_RESTIE_MSK BIT(USB_IER_RESTIE_POS) + +#define USB_IER_RESIE_POS 1U +#define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS) + +#define USB_IER_SUSPDIE_POS 0U +#define USB_IER_SUSPDIE_MSK BIT(USB_IER_SUSPDIE_POS) + +/****************** Bit definition for USB_IDR register ************************/ + +#define USB_IDR_SESREQID_POS 6U +#define USB_IDR_SESREQID_MSK BIT(USB_IDR_SESREQID_POS) + +#define USB_IDR_DISCONID_POS 5U +#define USB_IDR_DISCONID_MSK BIT(USB_IDR_DISCONID_POS) + +#define USB_IDR_CONID_POS 4U +#define USB_IDR_CONID_MSK BIT(USB_IDR_CONID_POS) + +#define USB_IDR_SOFID_POS 3U +#define USB_IDR_SOFID_MSK BIT(USB_IDR_SOFID_POS) + +#define USB_IDR_BABID_POS 2U +#define USB_IDR_BABID_MSK BIT(USB_IDR_BABID_POS) + +#define USB_IDR_RESTID_POS 2U +#define USB_IDR_RESTID_MSK BIT(USB_IDR_RESTID_POS) + +#define USB_IDR_RESID_POS 1U +#define USB_IDR_RESID_MSK BIT(USB_IDR_RESID_POS) + +#define USB_IDR_SUSPDID_POS 0U +#define USB_IDR_SUSPDID_MSK BIT(USB_IDR_SUSPDID_POS) + +/****************** Bit definition for USB_IVS register ************************/ + +#define USB_IVS_SESREQIVS_POS 6U +#define USB_IVS_SESREQIVS_MSK BIT(USB_IVS_SESREQIVS_POS) + +#define USB_IVS_DISCONIVS_POS 5U +#define USB_IVS_DISCONIVS_MSK BIT(USB_IVS_DISCONIVS_POS) + +#define USB_IVS_CONIVS_POS 4U +#define USB_IVS_CONIVS_MSK BIT(USB_IVS_CONIVS_POS) + +#define USB_IVS_SOFIVS_POS 3U +#define USB_IVS_SOFIVS_MSK BIT(USB_IVS_SOFIVS_POS) + +#define USB_IVS_BABIVS_POS 2U +#define USB_IVS_BABIVS_MSK BIT(USB_IVS_BABIVS_POS) + +#define USB_IVS_RESTIVS_POS 2U +#define USB_IVS_RESTIVS_MSK BIT(USB_IVS_RESTIVS_POS) + +#define USB_IVS_RESIVS_POS 1U +#define USB_IVS_RESIVS_MSK BIT(USB_IVS_RESIVS_POS) + +#define USB_IVS_SUSPDIVS_POS 0U +#define USB_IVS_SUSPDIVS_MSK BIT(USB_IVS_SUSPDIVS_POS) + +/****************** Bit definition for USB_RIF register ************************/ + +#define USB_RIF_SESREQRIF_POS 6U +#define USB_RIF_SESREQRIF_MSK BIT(USB_RIF_SESREQRIF_POS) + +#define USB_RIF_DISCONRIF_POS 5U +#define USB_RIF_DISCONRIF_MSK BIT(USB_RIF_DISCONRIF_POS) + +#define USB_RIF_CONRIF_POS 4U +#define USB_RIF_CONRIF_MSK BIT(USB_RIF_CONRIF_POS) + +#define USB_RIF_SOFRIF_POS 3U +#define USB_RIF_SOFRIF_MSK BIT(USB_RIF_SOFRIF_POS) + +#define USB_RIF_BABRIF_POS 2U +#define USB_RIF_BABRIF_MSK BIT(USB_RIF_BABRIF_POS) + +#define USB_RIF_RESTRIF_POS 2U +#define USB_RIF_RESTRIF_MSK BIT(USB_RIF_RESTRIF_POS) + +#define USB_RIF_RESRIF_POS 1U +#define USB_RIF_RESRIF_MSK BIT(USB_RIF_RESRIF_POS) + +#define USB_RIF_SUSPDRIF_POS 0U +#define USB_RIF_SUSPDRIF_MSK BIT(USB_RIF_SUSPDRIF_POS) + +/****************** Bit definition for USB_IFM register ************************/ + +#define USB_IFM_SESREQIFM_POS 6U +#define USB_IFM_SESREQIFM_MSK BIT(USB_IFM_SESREQIFM_POS) + +#define USB_IFM_DISCONIFM_POS 5U +#define USB_IFM_DISCONIFM_MSK BIT(USB_IFM_DISCONIFM_POS) + +#define USB_IFM_CONIFM_POS 4U +#define USB_IFM_CONIFM_MSK BIT(USB_IFM_CONIFM_POS) + +#define USB_IFM_SOFIFM_POS 3U +#define USB_IFM_SOFIFM_MSK BIT(USB_IFM_SOFIFM_POS) + +#define USB_IFM_BABIFM_POS 2U +#define USB_IFM_BABIFM_MSK BIT(USB_IFM_BABIFM_POS) + +#define USB_IFM_RESTIFM_POS 2U +#define USB_IFM_RESTIFM_MSK BIT(USB_IFM_RESTIFM_POS) + +#define USB_IFM_RESIFM_POS 1U +#define USB_IFM_RESIFM_MSK BIT(USB_IFM_RESIFM_POS) + +#define USB_IFM_SUSPDIFM_POS 0U +#define USB_IFM_SUSPDIFM_MSK BIT(USB_IFM_SUSPDIFM_POS) + +/****************** Bit definition for USB_ICR register ************************/ + +#define USB_ICR_SESREQICR_POS 6U +#define USB_ICR_SESREQICR_MSK BIT(USB_ICR_SESREQICR_POS) + +#define USB_ICR_DISCONICR_POS 5U +#define USB_ICR_DISCONICR_MSK BIT(USB_ICR_DISCONICR_POS) + +#define USB_ICR_CONICR_POS 4U +#define USB_ICR_CONICR_MSK BIT(USB_ICR_CONICR_POS) + +#define USB_ICR_SOFICR_POS 3U +#define USB_ICR_SOFICR_MSK BIT(USB_ICR_SOFICR_POS) + +#define USB_ICR_BABICR_POS 2U +#define USB_ICR_BABICR_MSK BIT(USB_ICR_BABICR_POS) + +#define USB_ICR_RESTICR_POS 2U +#define USB_ICR_RESTICR_MSK BIT(USB_ICR_RESTICR_POS) + +#define USB_ICR_RESICR_POS 1U +#define USB_ICR_RESICR_MSK BIT(USB_ICR_RESICR_POS) + +#define USB_ICR_SUSPDICR_POS 0U +#define USB_ICR_SUSPDICR_MSK BIT(USB_ICR_SUSPDICR_POS) + +typedef struct +{ + __IO uint8_t FADDR ; //0x0000 Function address register. + __IO uint8_t POWER ; //0x0001 Power management register. + __IO uint8_t DPDMCTRL ; //0x0002 DP DM Control register. + __IO uint8_t SWCID ; //0x0003 Softwave CID register. + __IO uint8_t SWVBUS ; //0x0004 Softwave VBUS register. + __IO uint8_t TMODE ; //0x0005 Test Mode register. + __IO uint8_t RES002[6] ; //0x0006~0x0B, Reserved + __IO uint8_t FRAME1 ; //0x000C, Frame number bits 0 to 7. + __IO uint8_t FRAME2 ; //0x000D, Frame number bits 8 to 10. + __IO uint8_t INDEX ; //0x000E, Index register for selecting the endp + __IO uint8_t DEVCTRL ; //0x000F, USB device control register. + __IO uint8_t TXMAXP ; //0x0010, Peripheral mode - Maximum packet size + __IO uint8_t CSR0L_TXCSRL ;//0x0011, Peripheral mode - Control Status regi + __IO uint8_t CSR0H_TXCSRH ;//0x0012, Peripheral mode - Control Status regi + __IO uint8_t RXMAXP ; //0x0013, Peripheral mode - Maximum packet size + __IO uint8_t RXCSR1 ; //0x0014, Peripheral mode - Control Status regi + __IO uint8_t RXCSR2 ; //0x0015, Peripheral mode - Control Status regi + __IO uint8_t RXCOUNT1 ; //0x0016, Peripheral mode - Number of bytes in + __IO uint8_t RXCOUNT2 ; //0x0017, Peripheral mode - Number of bytes in + __IO uint8_t TXTYPE ; //0x0018, Peripheral mode - // + __IO uint8_t NAKLIMIT0_TXINTERVAL ; //0x0019, Peripheral mode - // + __IO uint8_t RXTYPE ; //0x001A, Peripheral mode - // + __IO uint8_t RXINTERVAL ; //0x001B, Peripheral mode - // + __IO uint8_t TXFIFO1 ; //0x001C, Tx Endpoint FIFO details + __IO uint8_t TXFIFO2 ; //0x001D, Tx Endpoint FIFO details + __IO uint8_t RXFIFO1 ; //0x001E, Rx Endpoint FIFO details + __IO uint8_t RXFIFO2 ; //0x001F, Rx Endpoint FIFO details + __IO uint8_t EP0FIFO ; //0x0020, FIFOs for Endpoints 0. + __IO uint8_t RES021[3] ; //0x0021~0x23, Reserved + __IO uint8_t EP1FIFO ; //0x0024, FIFOs for Endpoints 1. + __IO uint8_t RES025[3] ; //0x0025~0x27, Reserved + __IO uint8_t EP2FIFO ; //0x0028, FIFOs for Endpoints 2. + __IO uint8_t RES029[3] ; //0x0029~0x2B, Reserved + __IO uint8_t EP3FIFO ; //0x002C, FIFOs for Endpoints 3. + __IO uint8_t RES02D[3] ; //0x002D~0x2F, Reserved + __IO uint8_t EP4FIFO ; //0x0030, FIFOs for Endpoints 4. + __IO uint8_t RES031[3] ; //0x0031~0x33, Reserved + __IO uint8_t EP5FIFO ; //0x0034, FIFOs for Endpoints 5. + __IO uint8_t RES035[3] ; //0x0035~0x37, Reserved + __IO uint8_t EP6FIFO ; //0x0038, FIFOs for Endpoints 6. + __IO uint8_t RES039[71] ; //0x0039~0x7C, Reserved + __IO uint8_t TXIER ; //0x0080, TX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES081 ; //0x0081, Reserved + __IO uint8_t RXIER ; //0x0082, RX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES083 ; //0x0083, Reserved + __IO uint8_t TXIDR ; //0x0084, TX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES085 ; //0x0085, Reserved + __IO uint8_t RXIDR ; //0x0086, RX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES087 ; //0x0087, Reserved + __IO uint8_t TXIVS ; //0x0088, TX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES089 ; //0x0089, Reserved + __IO uint8_t RXIVS ; //0x008A, RX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES08B ; //0x008B, Reserved + __IO uint8_t TXRIF ; //0x008C, TX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08D ; //0x008D, Reserved + __IO uint8_t RXRIF ; //0x008E, RX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08F ; //0x008F, Reserved + __IO uint8_t TXIFM ; //0x0090, TX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES091 ; //0x0091, Reserved + __IO uint8_t RXIFM ; //0x0092, RX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES093 ; //0x0093, Reserved + __IO uint8_t TXICR ; //0x0094, TX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES095 ; //0x0095, Reserved + __IO uint8_t RXICR ; //0x0096, RX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES097[9] ; //0x0097~0x9C, Reserved + __O uint32_t IER ; //0x00A0, USB Interrupt Enable Register + __O uint32_t IDR ; //0x00A4, USB Interrupt Disable Register + __I uint32_t IVS ; //0x00A8, USB Interrupt Valid Register + __I uint32_t RIF ; //0x00AC, USB Raw Interrupt Flag Status Register + __I uint32_t IFM ; //0x00B0, USB Interrupt Flag Masked Status + __O uint32_t ICR ; //0x00B4, USB Interrupt Clear Register +} USBCTRL_TypeDef; + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..0c64ea3d43ccf9f6d141e5ffe7cfb960fd51549b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h @@ -0,0 +1,88 @@ +/** + ************************************************************************************** + * @file reg_WWDG.h + * @brief WWDG Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __WWDG_H__ +#define __WWDG_H__ + +typedef struct +{ + __IO uint32_t CR; /* 0x00 WWDG_CR Control register */ + __IO uint32_t CFR; /* 0x04 WWDG_CFR Configuration register */ + __O uint32_t IER; /* 0x08 WWDG_IER Interrupt enable register */ + __O uint32_t IDR; /* 0x0C WWDG_IDR Interrupt disable register */ + __I uint32_t IVS; /* 0x10 WWDG_IVS Interrupt valid status */ + __I uint32_t RIF; /* 0x14 WWDG_RIF Raw interrupt flag */ + __I uint32_t IFM; /* 0x18 WWDG_IFM Interrupt flag masked */ + __O uint32_t ICR; /* 0x1C WWDG_ICR Interrupt clear register */ +} WWDG_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for WWDG_CR register ************************/ + +#define WWDG_CR_WDGA_POS 7U +#define WWDG_CR_WDGA_MSK BIT(WWDG_CR_WDGA_POS) + +#define WWDG_CR_T_POSS 0U +#define WWDG_CR_T_POSE 6U +#define WWDG_CR_T_MSK BITS(WWDG_CR_T_POSS,WWDG_CR_T_POSE) + +/****************** Bit definition for WWDG_CFR register ************************/ + +#define WWDG_CFR_WDGTB_POS 7U +#define WWDG_CFR_WDGTB_MSK BIT(WWDG_CFR_WDGTB_POS) + +#define WWDG_CFR_W_POSS 0U +#define WWDG_CFR_W_POSE 6U +#define WWDG_CFR_W_MSK BITS(WWDG_CFR_W_POSS,WWDG_CFR_W_POSE) + +/****************** Bit definition for WWDG_IER register ************************/ + +#define WWDG_IER_EWIS_POS 7U +#define WWDG_IER_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_IDR register ************************/ + +#define WWDG_IDR_EWIS_POS 7U +#define WWDG_IDR_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_IVS register ************************/ + +#define WWDG_IVS_EWIS_POS 7U +#define WWDG_IVS_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_RIF register ************************/ + +#define WWDG_RIF_EWIS_POS 7U +#define WWDG_RIF_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_IFM register ************************/ + +#define WWDG_IFM_EWIS_POS 7U +#define WWDG_IFM_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_ICR register ************************/ + +#define WWDG_ICR_EWIS_POS 7U +#define WWDG_ICR_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..b1ee6dcf18ad887719577641ab7d07ce9d9a9800 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h @@ -0,0 +1,92 @@ +/** + ************************************************************************************** + * @file REG_WWDT.h + * @brief WWDT Head File + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_WWDT_H__ +#define __REG_WWDT_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WDGA_POS 7U +#define WWDT_CON_WDGA_MSK BIT(WWDT_CON_WDGA_POS) + +#define WWDT_CON_T_POSS 0U +#define WWDT_CON_T_POSE 6U +#define WWDT_CON_T_MSK BITS(WWDT_CON_T_POSS,WWDT_CON_T_POSE) + +/****************** Bit definition for WWDT_CFG register ************************/ + +#define WWDT_CFG_WDGTB_POSS 7U +#define WWDT_CFG_WDGTB_POSE 8U +#define WWDT_CFG_WDGTB_MSK BITS(WWDT_CFG_WDGTB_POSS,WWDT_CFG_WDGTB_POSE) + +#define WWDT_CFG_W_POSS 0U +#define WWDT_CFG_W_POSE 6U +#define WWDT_CFG_W_MSK BITS(WWDT_CFG_W_POSS,WWDT_CFG_W_POSE) + +/****************** Bit definition for WWDT_IER register ************************/ + +#define WWDT_IER_EWIS_POS 0U +#define WWDT_IER_EWIS_MSK BIT(WWDT_IER_EWIS_POS) + +/****************** Bit definition for WWDT_IDR register ************************/ + +#define WWDT_IDR_EWIS_POS 0U +#define WWDT_IDR_EWIS_MSK BIT(WWDT_IDR_EWIS_POS) + +/****************** Bit definition for WWDT_IVS register ************************/ + +#define WWDT_IVS_EWIS_POS 0U +#define WWDT_IVS_EWIS_MSK BIT(WWDT_IVS_EWIS_POS) + +/****************** Bit definition for WWDT_RIF register ************************/ + +#define WWDT_RIF_EWIF_POS 0U +#define WWDT_RIF_EWIF_MSK BIT(WWDT_RIF_EWIF_POS) + +/****************** Bit definition for WWDT_IFM register ************************/ + +#define WWDT_IFM_EWIM_POS 0U +#define WWDT_IFM_EWIM_MSK BIT(WWDT_IFM_EWIM_POS) + +/****************** Bit definition for WWDT_ICR register ************************/ + +#define WWDT_ICR_EWIC_POS 0U +#define WWDT_ICR_EWIC_MSK BIT(WWDT_ICR_EWIC_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} WWDT_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h new file mode 100644 index 0000000000000000000000000000000000000000..2810051370a15c4781e0de78dd79f3167a566811 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h @@ -0,0 +1,389 @@ +/******************************************************************* +* *file : ES32F0271_sub.h +* *description: ES32F0271 Device Head File +* *author : Eastsoft AE Team +* *version : V1.00.01 +* *data : 4/10/2018 +* +* *Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. +*******************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup ES32F0271_SUB1 + * @{ + */ + +#ifndef __ES32F0271_SUB_H__ +#define __ES32F0271_SUB_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief defines 'read only' 、'write only'、 'read / write' permissions. + */ +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief configuration of the cortex-M3 processor and core peripherals. + */ + +#define __MPU_PRESENT 0 /*!< cm0ikmcu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< cm0ikmcu Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** + * @} + */ + +/** @addtogroup peripherals_interrupt_number_definition + * @{ + */ + +typedef enum IRQn +{ + + /****** ES32 Processor Exceptions Numbers ******************************************************/ + + /*************** Cortex-M0 Processor Exceptions Numbers **************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + + /**************** ES32F0271_SUB specific Exceptions Numbers **************************/ + WWDT_IRQn = 0, /* 0 | WWDT Interrupt */ + PVD_IRQn = 1, /* 1 | PVD Interrupt EXTI[20] */ + RTC_IRQn = 2, /* 2 | RTC Interrupt */ + WAKEUP_IRQn = 3, /* 3 | WAKEUP Interrupt EXTI[21] */ + CM0IKMCU_IRQ04_IRQn = 4, /* 4 | Interrupt */ + EXTI_0to1_IRQn = 5, /* 5 | EXTI[1:0] Interrupt GPIOx[1:0] */ + EXTI_2to3_IRQn = 6, /* 6 | EXTI[3:2] Interrupt GPIOx[3:2] */ + EXTI_4to15_IRQn = 7, /* 7 | EXTI[15:4] Interrupt GPIOx[15:4] */ + CM0IKMCU_IRQ08_IRQn = 8, /* 8 | Interrupt */ + DMA1_CH0_IRQn = 9, /* 9 | DMA1_CH0 Interrupt */ + DMA1_CH12_IRQn = 10, /* 10 | DMA1_CH12 Interrupt */ + DMA1_CH345_IRQn = 11, /* 11 | DMA1_CH345 Interrupt */ + ADC_CMP_IRQn = 12, /* 12 | ADC/COMP0-3 Interrupt EXTI[19:16]) */ + AD16C4T1_IRQn = 13, /* 13 | AD16C4T1 Interrupt */ + BS16T1_IRQn = 14, /* 14 | BS16T1 Interrupt */ + GP32C4T1_IRQn = 15, /* 15 | GP32C4T1 Interrupt */ + GP16C4T1_IRQn = 16, /* 16 | GP16C4T1 Interrupt */ + GP16C4T2_IRQn = 17, /* 17 | GP16C4T2 Interrupt */ + GP16C4T3_IRQn = 18, /* 18 | GP16C4T3 Interrupt */ + GP16C2T1_IRQn = 19, /* 19 | GP16C2T1 Interrupt */ + GP16C2T2_IRQn = 20, /* 20 | GP16C2T2 Interrupt */ + GP16C2T3_IRQn = 21, /* 21 | GP16C2T3 Interrupt */ + GP16C2T4_IRQn = 22, /* 22 | GP16C2T4 Interrupt */ + I2C1_IRQn = 23, /* 23 | I2C1 Interrupt */ + I2C2_IRQn = 24, /* 24 | I2C2 Interrupt */ + SPI1_IRQn = 25, /* 25 | SPI1 Interrupt */ + SPI2_IRQn = 26, /* 26 | SPI2 Interrupt */ + UART1_IRQn = 27, /* 27 | UART1 Interrupt */ + UART2_IRQn = 28, /* 28 | UART2 Interrupt */ + UART3_IRQn = 29, /* 29 | UART3 Interrupt */ + SUART12_IRQn = 30, /* 30 | SUART1/2 Interrupt */ + USB_IRQn = 31 /* 31 | USB Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/* Includes-------------------------------------------------------------------------------*/ + +#include "core_cm0.h" +#include +#include +#include "system_es32f027x.h" +/** + * @brief these files declare Peripheral register bit_definition. + */ +#include "reg_rcu.h" +#include "reg_syscfg.h" +#include "reg_fc.h" +#include "reg_dma.h" +#include "reg_gpio.h" +#include "reg_i2c.h" +#include "reg_uart.h" +#include "reg_adc.h" +#include "reg_cmp.h" +#include "reg_dac.h" +#include "reg_spi.h" +#include "reg_crc.h" +#include "reg_ad16c4t.h" +#include "reg_hdiv.h" +#include "reg_aes.h" +#include "reg_wwdt.h" +#include "reg_rtc.h" +#include "reg_mswd.h" +#include "reg_mcm.h" +#include "reg_exti.h" +#include "reg_usb.h" + +/******************************************************************************/ +/* Peripheral register */ +/******************************************************************************/ + +/* allow anonymous structures and anonymous enumeration */ +/* #pragma anon_unions */ + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +/********************* Base addresses *************************/ +#define FLASH_BASE (0x08000000UL) +#define FLASH_INFO_BASE (0x1FFFE000UL) /* EFLASH Info ( 6K Bytes) - Boot Loader Memory */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40010000UL) +#define AHB1_BASE (0x40020000UL) +#define AHB2_BASE (0x48000000UL) +#define CM0IN_BASE (0xE0000000UL) + +/* Cortex簧-M0 internal Peripherals - CM0IN_BASE: 0xE0000000*/ +#define TICK_BASE (CM0IN_BASE + 0xE010) + +#define SRAM1_BASE (SRAM_BASE + 0x0000) // SRAM1 Memory ( 4K Bytes) +#define SRAM2_BASE (SRAM_BASE + 0x1000) // SRAM2 Memory ( 4K Bytes) for Rev.B +#define STACK_SIZE 0x00000400>>2 // Stack size (in Words) +#define SRAMTOP 0x1000//0x2000 // Jackey 2018.9.5 + +/***************** peripherals base addresses ********************/ +/* APB1 */ +#define GP32C4T1_BASE (APB1_BASE + 0x0000) +#define GP16C4T1_BASE (APB1_BASE + 0x0400) +#define GP16C4T2_BASE (APB1_BASE + 0x0800) +#define GP16C4T3_BASE (APB1_BASE + 0x0C00) +#define BS16T1_BASE (APB1_BASE + 0x1000) +#define WWDT_BASE (APB1_BASE + 0x2C00) +#define IWDT_BASE (APB1_BASE + 0x3000) +#define SPI2_BASE (APB1_BASE + 0x3800) +#define UART2_BASE (APB1_BASE + 0x4400) +#define UART3_BASE (APB1_BASE + 0x4800) +#define SUART1_BASE (APB1_BASE + 0x4C00) +#define SUART2_BASE (APB1_BASE + 0x5000) +#define I2C1_BASE (APB1_BASE + 0x5400) +#define I2C2_BASE (APB1_BASE + 0x5800) +#define DAC_BASE (APB1_BASE + 0x5C00) +#define PWR_BASE (APB1_BASE + 0x7000) +/* APB2 */ +#define EXTI_BASE (APB2_BASE + 0x0400) +#define ADC_BASE (APB2_BASE + 0x2400) +#define AD16C4T1_BASE (APB2_BASE + 0x2C00) +#define SPI1_BASE (APB2_BASE + 0x3000) +#define UART1_BASE (APB2_BASE + 0x3800) +#define GP16C2T1_BASE (APB2_BASE + 0x4000) +#define GP16C2T2_BASE (APB2_BASE + 0x4400) +#define GP16C2T3_BASE (APB2_BASE + 0x4800) +#define GP16C2T4_BASE (APB2_BASE + 0x4C00) +#define MCM_BASE (APB2_BASE + 0x5400) +#define DBGMCU_BASE (APB2_BASE + 0x5800) +#define COMP_BASE (APB2_BASE + 0x5C00) +/* AHB1 */ +#define DMA1_BASE (AHB1_BASE + 0x0000) +#define RCU_BASE (AHB1_BASE + 0x1000) +#define SYSCFG_BASE (AHB1_BASE + 0x1400) +#define RTC_BASE (AHB1_BASE + 0x1800) +#define EFLASH_BASE (AHB1_BASE + 0x2000) +#define MSWD_BASE (AHB1_BASE + 0x2C00) +#define CRC_BASE (AHB1_BASE + 0x3000) +#define AES_BASE (AHB1_BASE + 0x3400) +#define USB_BASE (AHB1_BASE + 0x3800) +#define HDIV_BASE (AHB1_BASE + 0x3C00) +/* AHB2 */ +#define GPIOA_BASE (AHB2_BASE + 0x0000) +#define GPIOB_BASE (AHB2_BASE + 0x0400) +#define GPIOC_BASE (AHB2_BASE + 0x0800) +#define GPIOD_BASE (AHB2_BASE + 0x0C00) +#define GPIOE_BASE (AHB2_BASE + 0x1000) +#define GPIOF_BASE (AHB2_BASE + 0x1400) + +/********************* Peripheral declaration *************************/ +#define TICK (( TICK_TypeDef *) TICK_BASE) +#define GPIOA (( GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB (( GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC (( GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD (( GPIO_TypeDef *) GPIOD_BASE) +#define DMA1 (( DMA_TypeDef *) DMA1_BASE) +#define RCU (( RCU_TypeDef *) RCU_BASE) +#define SYSCFG (( SYSCFG_TypeDef *) SYSCFG_BASE) +#define FC (( FC_TypeDef *) EFLASH_BASE) +#define CRC (( CRC_TypeDef *) CRC_BASE) +#define AES (( AES_TypeDef *) AES_BASE) +#define HDIV (( HDIV_TypeDef *) HDIV_BASE) +#define MSWD (( MSWD_TypeDef *) MSWD_BASE) +#define USB (( USBCTRL_TypeDef *) USB_BASE) +#define USBH (( USBCTRL_TypeDef *) USB_BASE) +#define USBD (( USBCTRL_TypeDef *) USB_BASE) +#define IWDT (( IWDT_TypeDef *) IWDT_BASE) +#define WWDT (( WWDT_TypeDef *) WWDT_BASE) +#define ADC (( ADC_TypeDef *) ADC_BASE) +#define AD16C4T1 (( AD16C4T_TypeDef *) AD16C4T1_BASE) +#define GP32C4T1 (( AD16C4T_TypeDef *) GP32C4T1_BASE) +#define GP16C4T1 (( AD16C4T_TypeDef *) GP16C4T1_BASE) +#define GP16C4T2 (( AD16C4T_TypeDef *) GP16C4T2_BASE) +#define GP16C4T3 (( AD16C4T_TypeDef *) GP16C4T3_BASE) +#define GP16C2T1 (( AD16C4T_TypeDef *) GP16C2T1_BASE) +#define GP16C2T2 (( AD16C4T_TypeDef *) GP16C2T2_BASE) +#define GP16C2T3 (( AD16C4T_TypeDef *) GP16C2T3_BASE) +#define GP16C2T4 (( AD16C4T_TypeDef *) GP16C2T4_BASE) +#define BS16T1 (( AD16C4T_TypeDef *) BS16T1_BASE) +#define SPI1 (( SPI_TypeDef *) SPI1_BASE) +#define SPI2 (( SPI_TypeDef *) SPI2_BASE) +#define I2C1 (( I2C_TypeDef *) I2C1_BASE) +#define I2C2 (( I2C_TypeDef *) I2C2_BASE) +#define DAC (( DAC_TypeDef *) DAC_BASE) +#define CMP (( CMP_TypeDef *) COMP_BASE) +#define UART1 (( UART_TypeDef *) UART1_BASE) +#define UART2 (( UART_TypeDef *) UART2_BASE) +#define UART3 (( UART_TypeDef *) UART3_BASE) +#define SUART1 (( UART_TypeDef *) SUART1_BASE) +#define SUART2 (( UART_TypeDef *) SUART2_BASE) +#define EXTI (( EXTI_TypeDef *) EXTI_BASE) +#define RTC (( RTC_TypeDef *) RTC_BASE) +#define MCM (( MCM_TypeDef *) MCM_BASE) +/* Special stuff */ +#define MSG_INCR ( __IO uint8_t *) (DBGMCU_BASE + 0x50) +#define MSG_WR ( __IO uint32_t *) (DBGMCU_BASE + 0x54) +#define MSG_END ( __IO uint32_t *) (DBGMCU_BASE + 0x58) +#define MSG_INCR_S ( __IO uint32_t *) (DBGMCU_BASE + 0x5C) +#define MSG_INCR_X ( __IO uint32_t *) (DBGMCU_BASE + 0x60) +#define MSG_INCR_B ( __IO uint32_t *) (DBGMCU_BASE + 0x64) +#define MSG_PTR ( __IO uint8_t **) (DBGMCU_BASE + 0x68) +#define MSG_INCR_D ( __IO uint32_t *) (DBGMCU_BASE + 0x78) +#define INCR_ERR_CNT ( __IO uint32_t *) (DBGMCU_BASE + 0x6C) + +#define END_SIM *MSG_END +#define SIM_FAIL 0xFFFFAAAA +#define SIM_PASS 0xFFFF5555 +/******************************************************************************/ +/* macros */ +/******************************************************************************/ + +/** @addtogroup Public_macros + * @{ + */ +#if defined (__CC_ARM) +#define __INLINE__ __inline +#else +#define __INLINE__ inline +#endif + +#define __isr__ + +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ +do \ +{ \ + if (!(x)) \ + { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) +#else +#define assert_param(x) +#endif + +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) + +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) &\ + (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) + +#define SET_BIT(REG, SETMASK) ((REG) |= (SETMASK)) + +#define CLEAR_BIT(REG, SETMASK) ((REG) &= ~(SETMASK)) + +#define READ_BIT(REG, SETMASK) ((REG) & (SETMASK)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/** + * @} + */ + +/******************************************************************************/ +/* types */ +/******************************************************************************/ +/** @addtogroup Public_types + * @{ + */ +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} TypeFunc,FuncState; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus, PinStatus; + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +typedef enum +{ + BIT_RESET = 0x0, + BIT_SET = 0x1, +} BitStatus; + +typedef enum +{ + FALSE = 0x0, + TRUE = 0x1, +} TypeBool; + +typedef enum +{ + UNLOCK = 0x0, + LOCK = 0x1, +} LockState; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + +/** + * @} Public_types + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} ES32F0271_SUB + */ + +/** + * @} CMSIS + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h new file mode 100644 index 0000000000000000000000000000000000000000..71a3270c6e3093d4ddb0dd5b793dc0c72ca6d82f --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h @@ -0,0 +1,183 @@ +/* rt_misc.h: definitions for miscellaneous retargetable functions + * + * Copyright 1999,2013-2014 ARM Limited. All rights reserved. + * + * RCS $Revision$ + * Checkin $Date$ + * Revising $Author$ + */ + +#ifndef __RT_MISC_H +#define __RT_MISC_H +#define __ARMCLIB_VERSION 5060019 + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* + * This will be called during startup if it's defined, in order to + * allow a user reimplementation of getenv() to initialise itself. + */ +extern void _getenv_init(void); + +/* + * This will be called during startup if it's defined, in order to + * allow a user reimplementation of clock() to initialise itself. + */ +extern void _clock_init(void); + +/* + * This must return a pointer to __USER_LIBSPACE_SIZE bytes of + * zero-initialised space, used to store vital static data such as + * errno, the heap state, and the FP status word. + */ +#define __USER_LIBSPACE_SIZE 96 +extern void *__user_libspace(void); + +/* + * This is the library init function itself, provided just in case + * a user needs to call it directly. It is called just after + * __rt_stackheap_init(), and passed an initial chunk of memory to + * use as a heap. It returns argc and argv ready to be passed to + * main(). (The __argc_argv structure contains four words rather + * than just two, in case you need to pass anything else to main() + * such as the Unix envp. For AArch64 struct __argc_argv is 8 words + * (4 registers) and explicit padding is used to ensure argc is in w0.) + */ +struct __argc_argv { +#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \ + (defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)) + int padding; +#endif + int argc; +#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \ + !(defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)) + int padding; +#endif + char **argv; + void *r2; + void *r3; +}; +extern __value_in_regs struct __argc_argv +__rt_lib_init(unsigned /*heapbase*/, unsigned /*heaptop*/); + +/* + * This function is responsible for constructing argc and argv to + * be passed to main(). Normally it works by calling + * _sys_command_string() and then splitting up the returned command + * line. If you define main() without arguments, the compiler also + * defines an empty version of this function to save time. In + * special circumstances, you might need to redefine this function + * explicitly yourself. + */ +__value_in_regs struct __argc_argv __ARM_get_argv(void */*internal use only*/); + +/* + * This is the library shutdown function, analogous to + * __rt_lib_init(). + */ +extern void __rt_lib_shutdown(void); + +/* + * The medium-level exit function. exit() calls atexit()-registered + * functions and shuts down the library; _sys_exit() does neither + * of those things; __rt_exit() shuts down the library but doesn't + * call atexit() functions. + */ +extern void __rt_exit(int /*returncode*/); /* never returns */ + +/* + * This can be defined to override the standard memory models' way + * of determining where to put the initial stack and heap. + * + * The input parameters R0 and R2 contain nothing useful. The input + * parameters SP and SL are the values that were in SP and SL when + * the program began execution (so you can return them if you want + * to keep that stack). + * + * The two `limit' fields in the return structure are ignored if + * you are using the one-region memory model: the memory region is + * taken to be all the space between heap_base and stack_base. + */ +struct __initial_stackheap { + unsigned heap_base; /* low-address end of initial heap */ + unsigned stack_base; /* high-address end of initial stack */ + unsigned heap_limit; /* high-address end of initial heap */ + unsigned stack_limit; /* low-address end of initial stack */ +}; +extern __value_in_regs struct __initial_stackheap +__user_initial_stackheap(unsigned /*R0*/, unsigned /*SP*/, + unsigned /*R2*/, unsigned /*SL*/); + +/* + * This can be defined to give bounds on the address space the heap + * will ever use. + */ +struct __heap_extent { + uintptr_t base; + size_t range; +}; +extern __value_in_regs struct __heap_extent +__user_heap_extent(uintptr_t /*ignore*/, size_t /*ignore*/); + +/* + * This can be defined to specify how much spare stack is needed + * below SL in addition to the 256 bytes required by ATPCS: + * `always' gives the number of bytes of extra stack required at + * all instants (so that an interrupt handler has space to run in, + * for example), while `cleanup' gives the number of bytes of extra + * stack required to be available after a stack overflow has + * occurred, so that the stack overflow routine (e.g. SIGSTAK + * handler) has room to tidy up. + */ +struct __stack_slop { + unsigned always, cleanup; +}; +extern __value_in_regs struct __stack_slop +__user_stack_slop(unsigned /*ignore*/, unsigned /*ignore*/); + +/* + * This can be defined to return extra blocks of memory, separate + * from the initial one, to be used by the heap. It should place a + * pointer to a block of at least the requested size in `*base', + * and return the size of the block. It should return 0 if no such + * block can be returned, in which case the value stored at `*base' + * is never used. + */ +extern size_t __user_heap_extend(int /*ignore*/, + void ** /*base*/, + size_t /*requestedsize*/); + +/* + * Redefine this to completely override the C handling of signals + * (bypassing the signal() mechanism). Return values are 0 to + * continue execution, or a non-zero value to cause an exit with + * that return code. + */ +int __raise(int /*sig*/, intptr_t /*type*/); + +/* + * Redefine this to change the default handling of signals. The + * interface is the same as __raise(), but this function will only + * get called after the C signal handling mechanism has declined to + * process the signal. + */ +int __default_signal_handler(int /*sig*/, intptr_t /*type*/); + +/* + * Redefine this to replace the library's entire signal handling + * mechanism in the most efficient possible way. The default + * implementation of this is what calls __raise (above). + */ +void __rt_raise(int /*sig*/, intptr_t /*type*/); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html new file mode 100644 index 0000000000000000000000000000000000000000..dce80ba62c72cc960649193235529b61a0068b3d --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html @@ -0,0 +1,16 @@ + + + + +ReleaseNote +

ES32F0271 Device Release Note

+

V1.00 2019-1-4

+

初版发布

+

V1.03 2019-09-23

+
    +
  1. Drivers\CMSIS\Device\EastSoft\ES32F0271\Startup\iar\ : 增加startup_es32f027x.s
    2. + +
+

 

+ + \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s new file mode 100644 index 0000000000000000000000000000000000000000..bda1ad6ecd778a0e18ec55a0d832913d1221060a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s @@ -0,0 +1,256 @@ +;******************************************************************************* +; file : startup_ES32f027x.s +; description: ES32F027x Device Startup File +; author : Eastsoft MCU Software Team +; data : 10 Dec 2018 +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +;******************************************************************************* + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ;0, load top of stack + DCD Reset_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD 0 ;4, MPU Fault Handler + DCD 0 ;5, Bus Fault Handler + DCD 0 ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD 0 ;12, Reserved + DCD 0 ;13, Reserved + DCD PENDSV_Handler ;14, PENDSV Handler + DCD SYSTICK_Handler ;15, SYSTICK Handler + DCD WWDT_IRQHandler ;16, WWDT IRQHandler + DCD PVD_IRQHandler ;17, PVD IRQHandler + DCD RTC_IRQHandler ;18, RTC IRQHandler + DCD LowPowerWakeup_IRQHandler ;19, LowPowerWakeup IRQHandler + DCD 0 ;20, Reserved + DCD EXTI0_1_IRQHandler ;21, EXTI01_1 IRQHandler + DCD EXTI2_3_IRQHandler ;22, EXTI2_3 IRQHandler + DCD EXTI4_15_IRQHandler ;23, EXTI4_15 IRQHandler + DCD 0 ;24, Reserved + DCD DMA1_CH0_IRQHandler ;25, DMA1_CH1 IRQHandler + DCD DMA1_CH1_2_IRQHandler ;26, DMA1_CH2_3 IRQHandler + DCD DMA1_CH3_5_IRQHandler ;27, DMA1_CH4_7 IRQHandler + DCD ADC_CMP_IRQHandler ;28, ADC_CMP IRQHandler + DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler + DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler + DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler + DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler + DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler + DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler + DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler + DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler + DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler + DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler + DCD I2C1_IRQHandler ;39, I2C1 IRQHandler + DCD I2C2_IRQHandler ;40, I2C2 IRQHandler + DCD SPI1_IRQHandler ;41, SPI1 IRQHandler + DCD SPI2_IRQHandler ;42, SPI2 IRQHandler + DCD UART1_IRQHandler ;43, UART1 IRQHandler + DCD UART2_IRQHandler ;44, UART2 IRQHandler + DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler + DCD SUART1_SUART2_IRQHandler ;46, SUART1_SUART2 IRQHandler + DCD USB_IRQHandler ;47, USB IRQHandler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PENDSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PENDSV_Handler + B PENDSV_Handler + + PUBWEAK SYSTICK_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SYSTICK_Handler + B SYSTICK_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK LowPowerWakeup_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LowPowerWakeup_IRQHandler + B LowPowerWakeup_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_CH0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH0_IRQHandler + B DMA1_CH0_IRQHandler + + PUBWEAK DMA1_CH1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_2_IRQHandler + B DMA1_CH1_2_IRQHandler + + PUBWEAK DMA1_CH3_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH3_5_IRQHandler + B DMA1_CH3_5_IRQHandler + + PUBWEAK ADC_CMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_CMP_IRQHandler + B ADC_CMP_IRQHandler + + PUBWEAK AD16C4T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_IRQHandler + B AD16C4T1_IRQHandler + + PUBWEAK BS16T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T1_IRQHandler + B BS16T1_IRQHandler + + PUBWEAK GP32C4T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP32C4T1_IRQHandler + B GP32C4T1_IRQHandler + + PUBWEAK GP16C4T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T1_IRQHandler + B GP16C4T1_IRQHandler + + PUBWEAK GP16C4T2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T2_IRQHandler + B GP16C4T2_IRQHandler + + PUBWEAK GP16C4T3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T3_IRQHandler + B GP16C4T3_IRQHandler + + PUBWEAK GP16C2T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T1_IRQHandler + B GP16C2T1_IRQHandler + + PUBWEAK GP16C2T2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T2_IRQHandler + B GP16C2T2_IRQHandler + + PUBWEAK GP16C2T3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T3_IRQHandler + B GP16C2T3_IRQHandler + + PUBWEAK GP16C2T4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T4_IRQHandler + B GP16C2T4_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK UART3_AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_AES_IRQHandler + B UART3_AES_IRQHandler + + PUBWEAK SUART1_SUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SUART1_SUART2_IRQHandler + B SUART1_SUART2_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c new file mode 100644 index 0000000000000000000000000000000000000000..4c4e15ee4c80c85604ce452f8a092d678f6212cc --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c @@ -0,0 +1,321 @@ + +// +// Boot (vectors) file for Cortex-M0 Integration Kit +// + +#include +#include +#include +#include "es32F0271_sub.h" + +// +// Build a stand-alone image +// + +#pragma import(__use_no_semihosting) + + +/*----------------------------------------------------------------------*/ +/*-------------- Interrupt Handlers --------------*/ +/*----------------------------------------------------------------------*/ +// The following functions are defined weakly to allow the user +// to override them at link time simply by declaring their own +// function of the same name. +// +// If no user function is provided, the weak function is used. +// +//------------------------------------ IRQ NMI Handler +__weak void NMI_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ Hard Fault Handler +__weak void HardFault_Handler(void) +{ + //printf("Hard Fault\r\n"); + while(1); +} +//------------------------------------ IRQ SVCall Handler +__weak void SVC_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ PendSV Handler +__weak void PendSV_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ SysTick Handler +__weak void SysTick_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ 31 +__weak void USB_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 30 +__weak void SUART12_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 29 +__weak void UART3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 28 +__weak void UART2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 27 +__weak void UART1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 26 +__weak void SPI2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 25 +__weak void SPI1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 24 +__weak void I2C2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 23 +__weak void I2C1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 22 +__weak void GPTIMC4_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 21 +__weak void GPTIMC3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 20 +__weak void GPTIMC2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 19 +__weak void GPTIMC1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 18 +__weak void GPTIMB3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 17 +__weak void GPTIMB2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 16 +__weak void GPTIMB1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 15 +__weak void GPTIMA1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 14 +__weak void BSTIM1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 13 +__weak void ADTIM1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 12 +__weak void ADC_COMP_IRQHandler(void) +{ + // while(1); +} +//------------------------------------ IRQ 11 +__weak void DMA1_CH345_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 10 +__weak void DMA1_CH12_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 9 +__weak void DMA1_CH0_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 8 +//------------------------------------ IRQ 7 +__weak void EXTI_4to15_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 6 +__weak void EXTI_2to3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 5 +__weak void EXTI_0to1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 4 +//------------------------------------ IRQ 3 +__weak void WAKEUP_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 2 +__weak void RTC_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 1 +__weak void PVD_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 0 +__weak void WWDT_IRQHandler(void) +{ + while(1); +} + + +/*----------------------------------------------------------------------*/ +/*-------------- Defined Handler --------------*/ +/*----------------------------------------------------------------------*/ +__weak void Default_IRQHandler(void) +{ + while(1); +} + +/*----------------------------------------------------------------------*/ +/*-------------- Symbols defined in linker script ---------*/ +/*----------------------------------------------------------------------*/ + +extern void __main(void); + +/*----------------------------------------------------------------------*/ +/*-------------- Reset Handler --------------*/ +/*----------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __main(); + while(1) {;} // In case main() fails +} + +/*----------------------------------------------------------------------*/ +/*-------------- Set up Vector Table --------------*/ +/*----------------------------------------------------------------------*/ +typedef void (*const vect_t)(void) __irq; + +vect_t __Vectors[] +__attribute__ ((section("vectors"))) = { + (vect_t)(SRAM1_BASE+SRAMTOP),//(vect_t)(0x20000F80), // Top of Stack - Allowing 4 words for DEBUGDRIVERDATA + (vect_t)Reset_Handler, // Reset Handler + (vect_t)NMI_Handler, // NMI Handler + (vect_t)HardFault_Handler,// Hard Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + (vect_t)SVC_Handler, // SVCall Handler + 0, // Reserved + 0, // Reserved + (vect_t)PendSV_Handler, // PendSV Handler + (vect_t)SysTick_Handler, // SysTick Handler + /*----------External Exceptions---------------------------------------------*/ + // External Interrupts 0 - 31 + // These are essentially unused, so will all + // take the same default handler if invoked. + // External Interrupts + //|=========================================| + //| IRQ NO. | M621 | + //|-----------------------------------------| + (vect_t)WWDT_IRQHandler, //| 0 | WWDG | | + (vect_t)PVD_IRQHandler, //| 1 | PVD | EXTI[20] | + (vect_t)RTC_IRQHandler, //| 2 | RTC | | + (vect_t)WAKEUP_IRQHandler, //| 3 | WAKEUP | EXTI[21] | + (vect_t)Default_IRQHandler, //| 4 | | | + (vect_t)EXTI_0to1_IRQHandler, //| 5 | EXTI[1:0] | GPIOx[1:0] | + (vect_t)EXTI_2to3_IRQHandler, //| 6 | EXTI[3:2] | GPIOx[3:2] | + (vect_t)EXTI_4to15_IRQHandler, //| 7 | EXTI[15:4] | GPIOx[15:4] | + (vect_t)Default_IRQHandler, //| 8 | | | + (vect_t)DMA1_CH0_IRQHandler, //| 9 | DMA1_CH0 | | + (vect_t)DMA1_CH12_IRQHandler, //| 10 | DMA1_CH12 | | + (vect_t)DMA1_CH345_IRQHandler, //| 11 | DMA1_CH345 | | + (vect_t)ADC_COMP_IRQHandler, //| 12 | ADC/COMP0-3 | EXTI[19:16] | + (vect_t)ADTIM1_IRQHandler, //| 13 | ADTIM1 | | + (vect_t)BSTIM1_IRQHandler, //| 14 | BSTIM1 | | + (vect_t)GPTIMA1_IRQHandler, //| 15 | GPTIMA1 | | + (vect_t)GPTIMB1_IRQHandler, //| 16 | GPTIMB1 | | + (vect_t)GPTIMB2_IRQHandler, //| 17 | GPTIMB2 | | + (vect_t)GPTIMB3_IRQHandler, //| 18 | GPTIMB3 | | + (vect_t)GPTIMC1_IRQHandler, //| 19 | GPTIMC1 | | + (vect_t)GPTIMC2_IRQHandler, //| 20 | GPTIMC2 | | + (vect_t)GPTIMC3_IRQHandler, //| 21 | GPTIMC3 | | + (vect_t)GPTIMC4_IRQHandler, //| 22 | GPTIMC4 | | + (vect_t)I2C1_IRQHandler, //| 23 | I2C1 | | + (vect_t)I2C2_IRQHandler, //| 24 | I2C2 | | + (vect_t)SPI1_IRQHandler, //| 25 | SPI1 | | + (vect_t)SPI2_IRQHandler, //| 26 | SPI2 | | + (vect_t)UART1_IRQHandler, //| 27 | UART1 | | + (vect_t)UART2_IRQHandler, //| 28 | UART2 | | + (vect_t)UART3_IRQHandler, //| 29 | UART3 | | + (vect_t)SUART12_IRQHandler, //| 30 | SUART1/2 | | + (vect_t)USB_IRQHandler //| 31 | USB | | + //==========================================| +}; + + +/*----------------------------------------------------------------------*/ +/*-------------- Set up initial stack and heap --------------*/ +/*----------------------------------------------------------------------*/ +__value_in_regs struct __initial_stackheap +__user_initial_stackheap(unsigned hb, unsigned sb, unsigned hl, unsigned sl) +{ + struct __initial_stackheap s; + + s.heap_base = hb; + s.stack_base = sb; + s.heap_limit = s.stack_base; + s.stack_limit = s.heap_base; + return s; +} + +/*----------------------------------------------------------------------*/ +/*------ Set test status bits in testbench when main() exits -------*/ +/*----------------------------------------------------------------------*/ +void _sys_exit(int return_code) +{ + while(1); +} + + + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s new file mode 100644 index 0000000000000000000000000000000000000000..78c14566c3787dae557b46ee5b30a2a393c69e17 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s @@ -0,0 +1,244 @@ +;******************************************************************************* +; *file : startup_ES32F027x.s +; *description: ES32F027x Device Startup File +; *author : Eastsoft MCU Software Team +; *version : V0.01 +; *data : 12/10/2018 +; +; *Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +;******************************************************************************* + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + ; External Interrupts + DCD Reset_Handler ;1, Reset Handler + DCD NMI_Handler ;2, NMI Handler + DCD HardFault_Handler ;3, HARDFAULT Handler + DCD 0 ;4, Reserved + DCD 0 ;5, Reserved + DCD 0 ;6, Reserved + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, SVC Handler + DCD 0 ;12, Reserved + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, PENDSV Handler + DCD SysTick_Handler ;15, SYSTICK Handler + DCD WWDT_IRQHandler ;16, WWDT IRQHandler + DCD PVD_IRQHandler ;17, PVD IRQHandler + DCD RTC_IRQHandler ;18, RTC IRQHandler + DCD LowPowerWakeup_IRQHandler ;19, LowPowerWakeup IRQHandler + DCD 0 ;20, Reserved + DCD EXTI0_1_IRQHandler ;21, EXTI01_1 IRQHandler + DCD EXTI2_3_IRQHandler ;22, EXTI2_3 IRQHandler + DCD EXTI4_15_IRQHandler ;23, EXTI4_15 IRQHandler + DCD 0 ;24, Reserved + DCD DMA1_CH0_IRQHandler ;25, DMA1_CH0 IRQHandler + DCD DMA1_CH1_2_IRQHandler ;26, DMA1_CH1_2 IRQHandler + DCD DMA1_CH3_5_IRQHandler ;27, DMA1_CH3_5 IRQHandler + DCD ADC_CMP_IRQHandler ;28, ADC_CMP IRQHandler + DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler + DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler + DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler + DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler + DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler + DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler + DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler + DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler + DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler + DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler + DCD I2C1_IRQHandler ;39, I2C1 IRQHandler + DCD I2C2_IRQHandler ;40, I2C2 IRQHandler + DCD SPI1_IRQHandler ;41, SPI1 IRQHandler + DCD SPI2_IRQHandler ;42, SPI2 IRQHandler + DCD UART1_IRQHandler ;43, UART1 IRQHandler + DCD UART2_IRQHandler ;44, UART2 IRQHandler + DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler + DCD SUART1_SUART2_IRQHandler ;46, SUART1_SUART2 IRQHandler + DCD USB_IRQHandler ;47, USB IRQHandler + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception IRQHandlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT LowPowerWakeup_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_CH0_IRQHandler [WEAK] + EXPORT DMA1_CH1_2_IRQHandler [WEAK] + EXPORT DMA1_CH3_5_IRQHandler [WEAK] + EXPORT ADC_CMP_IRQHandler [WEAK] + EXPORT AD16C4T1_IRQHandler [WEAK] + EXPORT BS16T1_IRQHandler [WEAK] + EXPORT GP32C4T1_IRQHandler [WEAK] + EXPORT GP16C4T1_IRQHandler [WEAK] + EXPORT GP16C4T2_IRQHandler [WEAK] + EXPORT GP16C4T3_IRQHandler [WEAK] + EXPORT GP16C2T1_IRQHandler [WEAK] + EXPORT GP16C2T2_IRQHandler [WEAK] + EXPORT GP16C2T3_IRQHandler [WEAK] + EXPORT GP16C2T4_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_AES_IRQHandler [WEAK] + EXPORT SUART1_SUART2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + + +WWDT_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +LowPowerWakeup_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_CH0_IRQHandler +DMA1_CH1_2_IRQHandler +DMA1_CH3_5_IRQHandler +ADC_CMP_IRQHandler +AD16C4T1_IRQHandler +BS16T1_IRQHandler +GP32C4T1_IRQHandler +GP16C4T1_IRQHandler +GP16C4T2_IRQHandler +GP16C4T3_IRQHandler +GP16C2T1_IRQHandler +GP16C2T2_IRQHandler +GP16C2T3_IRQHandler +GP16C2T4_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_AES_IRQHandler +SUART1_SUART2_IRQHandler +USB_IRQHandler + + + B . + + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c new file mode 100644 index 0000000000000000000000000000000000000000..e8a1ed21c0235902bbece97627636b693fd2dc45 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c @@ -0,0 +1,472 @@ +/* + *----------------------------------------------------------------------------- + * The confidential and proprietary information contained in this file may + * only be used by a person authorised under and to the extent permitted + * by a subsisting licensing agreement from ARM Limited. + * + * (C) COPYRIGHT 2009-2010 ARM Limited. + * ALL RIGHTS RESERVED + * + * This entire notice must be reproduced on all copies of this file + * and copies of this file may only be made by a person if such person is + * permitted to do so under the terms of a subsisting license agreement + * from ARM Limited. + * + * SVN Information + * + * Checked In : $Date: 2008-12-31 10:59:44 +0000 (Wed, 31 Dec 2008) $ + * + * Revision : $Revision: 97564 $ + * + * Release Information : Cortex-M0-AT510-r0p0-03rel0 + *----------------------------------------------------------------------------- + */ + + +#include + + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for armcc */ + #define __INLINE __inline /*!< inline keyword for armcc */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for iarcc */ + #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ + #define __nop __no_operation /*!< no operation intrinsic in iarcc */ + +#elif defined ( __GNUC__ ) + #define __ASM asm /*!< asm keyword for gcc */ + #define __INLINE inline /*!< inline keyword for gcc */ +#endif + + + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + + +#pragma diag_default=Pe940 + + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); +} + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int32_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +#endif + + + + + + + + + + + + + + + + + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c new file mode 100644 index 0000000000000000000000000000000000000000..1303e0765e88b926081916b00540f1aab56218e7 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c @@ -0,0 +1,55 @@ +/******************************************************************************/ +/* RETARGET.C: 'Retarget' layer for target-dependent low level functions */ +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + +#include +#include + +//#pragma import(__use_no_semihosting_swi) + +__weak uint8_t sendchar(uint8_t ui8char) +{ + (void) ui8char; + return 0; +} + + +int ITM_fputc(int ch); /* ITM debug */ + +struct __FILE +{ +int handle; /* Add whatever you need here */ +}; +FILE __stdout; + + +int fputc(int ch, FILE *f) +{ + return (sendchar(ch)); +} + + +int ferror(FILE *f) +{ + /* Your implementation of ferror */ + return EOF; +} + + +void _ttywrch(int ch) +{ + sendchar(ch); +} + + +void _sys_exit(int return_code) +{ +label: + goto label; /* endless loop */ +} diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c new file mode 100644 index 0000000000000000000000000000000000000000..6112c52bb4ca5f2292919972f8b23029367bbfb1 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c @@ -0,0 +1,79 @@ +/** + ************************************************************************************** + * @file system_es32f027x.c + * @brief System File. + * + * @version V0.01 + * @data 5/17/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Incudes--------------------------------------------------------*/ +#include "system_es32f027x.h" + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup System_ES32F027X + * @{ + */ + +/* Public Functions -----------------------------------------------------------*/ +/* Public Init Structure ------------------------------------------------------*/ +/* Public Macros --------------------------------------------------------------*/ +/* Public Constants -----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Private Constants-----------------------------------------------------------*/ + +/* Private Variables ----------------------------------------------------------*/ +/** @addtogroup Private_Variables + * @{ + */ + +/** + * @brief update the value of SystemCoreClock after changing the system clock. + */ +unsigned int SystemCoreClock = 4000000; +unsigned int SystemFrequency_SysClk = 4000000; +unsigned int SystemFrequency_AHBClk = 4000000; +unsigned int SystemFrequency_APBClk = 4000000; +unsigned int PLL1Frequency = 48000000; +unsigned int PLL0Frequency = 4000000; + +/** + * @} Private_Variables + */ + +/* Private Functions ----------------------------------------------------------*/ +/** @addtogroup Private_Functions + * @{ + */ + +/** + * @brief:SystemInit. + * @param:none + * @retval:none + */ +void SystemInit (void) +{ +} + +/** + * @} Private_Functions + */ + +/** + * @} System_ES32F072X + */ + +/** + * @} CMSIS + */ +/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027X.H **********/ + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h new file mode 100644 index 0000000000000000000000000000000000000000..d2cee80354f455407f220592ef5f73702946ec02 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h @@ -0,0 +1,83 @@ +/** + ************************************************************************************** + * @file SYSTEM_ES32F027x.H + * @brief es32f0271 system head file. + * + * @version V0.01 + * @data 5/17/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __SYSTEM_ES32F027x_H__ +#define __SYSTEM_ES32F027x_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes -------------------------------------------------------*/ +#include + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup System_ES32F027x + * @{ + */ + +/* Public Functions -----------------------------------------------------------*/ +/* Public Init Structure ------------------------------------------------------*/ +/* Public Macros --------------------------------------------------------------*/ +/* Public Constants -----------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Private Constants-----------------------------------------------------------*/ + +/* Public Types ---------------------------------------------------------------*/ +/** @addtogroup Public_Types + * @{ + */ +extern unsigned int SystemCoreClock; +extern unsigned int SystemFrequency_SysClk; +extern unsigned int SystemFrequency_AHBClk; +extern unsigned int SystemFrequency_APBClk; +extern unsigned int PLL1Frequency; +extern unsigned int PLL0Frequency; + +/* Exported function -------------------------------------------------*/ +/** @addtogroup Public_Functions + * @{ + */ + +extern void SystemInit (void); + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} Public_Functions + */ + +/** + * @} Public_Types + */ + +/** + * @} System_ES32F027x + */ + +/** + * @} CMSIS + */ +/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027x.H **********/ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..dfea7460e9a79e5b20670d947e6a52a894b29801 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..80a3e8bbe72b8c54f34a0f40aa1e01f2bfb3308f --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9dd26aa8110a0a90babc7b297c5bc6d5eb4216 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..093d35b9e5cfe6477ce7a71c842af5f35dabf5c8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..5c4c20e8777bf1177e03acbb6fca4b80f9b61362 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..94212eb87a94d11bb8346c6fff99d5fbf838c0ac --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..5d0f07e8accbfdd00dbace8fdf02f98825cfb6f9 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..edcaee3d4ab1e4026b53858e06930dd53d71f038 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..660f612aa31fe2a71cc786af5cac407e41fdd144 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000000000000000000000000000000000..47a39893aced51da4790b504c92a3bde53204a19 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000000000000000000000000000000000..0951a1f78126b48bf8279a71ecdafbbe4fc50f11 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..a3f1b9ac33045732b0ccef9bf592fbc544ccfb10 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000000000000000000000000000000000..f8f30c3496a16d62409066e4ded26c404e7ae813 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000000000000000000000000000000000..7d1d478af2a958f21304ecc743b4ee6bd5a0eb02 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000000000000000000000000000000000..a2c0d0805729739413b170af6a47410f89d854de --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000000000000000000000000000000000..b1efbcae7c733a636cfb4e043b6c4858e84ac6b6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..a11a3817a23491db120b26564d07c7cb1257b59e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2118 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000000000000000000000000000000000..1fe53bf012f4345356dd119fa0f03162f4d04dc6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000000000000000000000000000000000..9aab5e5b3ea5330bb524038aec36100126a59be5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000000000000000000000000000000000..a569ef2acec4a2966777053c6c51498b21aadbbd --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..aa180c9e5967841134fa5b37a488fa3e5e3f2f2f --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000000000000000000000000000000000..0ccfc74fe5b640ec5703495996872a5b6bcf1270 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000000000000000000000000000000000..0d09749f3a5066f0e061783a1e67972b72ab61a7 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h b/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h new file mode 100644 index 0000000000000000000000000000000000000000..02930af3e61a20ac95d8d52c23ceb923a9d99c23 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h @@ -0,0 +1,707 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + *---------------------------------------------------------------------------- + * + * Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency 100000000 + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/index.html b/bsp/essemi/es32f0271/libraries/CMSIS/index.html new file mode 100644 index 0000000000000000000000000000000000000000..c6da0802b47f310a1c6ae260189b80a126f0a3bb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/index.html @@ -0,0 +1,14 @@ + + + +Redirect to the CMSIS main page after 0 seconds + + + + + + +If the automatic redirection is failing, click open CMSIS Documentation. + + + diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h new file mode 100644 index 0000000000000000000000000000000000000000..672719a20b634e7f99bf34050fbc0689a0f1a342 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h @@ -0,0 +1,4484 @@ +/** + ************************************************************************************** + * @file md_AD16C4T.h + * @brief ES32F0271 Header file of MD AD16C4T module. + * + * @version V0.01 + * @date 3/12/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. AMD rights reserved. + * + ************************************************************************************** + */ + /* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_AD16C4T_H__ +#define __MD_AD16C4T_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* Includes -------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_ad16c4t.h" + + +/** @addtogroup Micro_Driver + * @{ + */ +#if defined (AD16C4T1) + +/** @defgroup AD16C4T AD16C4T + * @brief AD16C4T module driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private Macros ----------------------------------------------------------*/ + + + +/* Public Constants -----------------------------------------------------------*/ + +/** @defgroup MD_AD16C4T_Public_Constants Public Constants + * @brief AD16C4T module driver + * @{ + */ +/* AD16C4T_CON1 macros define*/ +#define MD_AD16C4T_DEBUGSELECT_INPUT (0 << AD16C4T_CON1_DBGSEL_POS) /*!< Channel input*/ +#define MD_AD16C4T_DEBUGSELECT_OUTPUT (1 << AD16C4T_CON1_DBGSEL_POS) /*!< Channel output*/ + +#define MD_AD16C4T_COMPAREINPUT_DISABLE (0 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input is disabled*/ +#define MD_AD16C4T_COMPAREINPUT_0 (1 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 0*/ +#define MD_AD16C4T_COMPAREINPUT_1 (2 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 1*/ +#define MD_AD16C4T_COMPAREINPUT_2 (3 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 2*/ +#define MD_AD16C4T_COMPAREINPUT_3 (4 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 3*/ + +#define MD_AD16C4T_COMPAREPOLARITY_LOW (0 << AD16C4T_CON1_CMPSELP_POS) /*!< Compare input is active low*/ +#define MD_AD16C4T_COMPAREPOLARITY_HIGH (1 << AD16C4T_CON1_CMPSELP_POS) /*!< Compare input is active high*/ + +#define MD_AD16C4T_CLOCKDIVSION_DIV1 (0 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=tCK_INT*/ +#define MD_AD16C4T_CLOCKDIVSION_DIV2 (1 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=2*tCK_INT*/ +#define MD_AD16C4T_CLOCKDIVSION_DIV4 (2 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=4*tCK_INT*/ + +#define MD_AD16C4T_CENTERALIGNED_DISABLE (0 << AD16C4T_CON1_CMSEL_POSS) /*!< Edge-aligned mode*/ +#define MD_AD16C4T_CENTERALIGNED_DOWN (1 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 1*/ +#define MD_AD16C4T_CENTERALIGNED_UP (2 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 2*/ +#define MD_AD16C4T_CENTERALIGNED_BOTH (3 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 3*/ + +#define MD_AD16C4T_UPCOUNTER (0 << AD16C4T_CON1_DIRSEL_POS) /*!< Counter used as upcounter*/ +#define MD_AD16C4T_DOWNCOUNTER (1 << AD16C4T_CON1_DIRSEL_POS) /*!< Counter used as downcounter*/ + +#define MD_AD16C4T_ONEPULSEMODE_DISABLE (0 << AD16C4T_CON1_SPMEN_POS) /*!< Counter is not stopped at update event*/ +#define MD_AD16C4T_ONEPULSEMODE_ENABLE (1 << AD16C4T_CON1_SPMEN_POS) /*!< Counter stops counting at the next update event*/ + +#define MD_AD16C4T_UPDATESOURCE_NORMAL (0 << AD16C4T_CON1_UERSEL_POS) /*!< Counter overflow/underflow, Setting the UG bit, Update generation through the slave mode controller generate an update interrupt*/ +#define MD_AD16C4T_UPDATESOURCE_COUNTER (1 << AD16C4T_CON1_UERSEL_POS) /*!< Only counter overflow/underflow generates an update interrupt or DMA request if Enabled*/ + +/* AD16C4T_CON2 macros define*/ +#define MD_AD16C4T_IDLEOUTPUT_LOW 0 /*!< OC1=0 (after a dead-time if OC1N is implemented) when MOE=0*/ +#define MD_AD16C4T_IDLEOUTPUT_HIGH 1 /*!< OC1=1 (after a dead-time if OC1N is implemented) when MOE=0*/ + +#define MD_AD16C4T_TI1INPUT_CH1 (0 << AD16C4T_CON2_I1SEL_POS) /*!< The TIMx_CH1 pin is connected to TI1 input*/ +#define MD_AD16C4T_TI1INPUT_XOR (1 << AD16C4T_CON2_I1SEL_POS) /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)*/ + +#define MD_AD16C4T_MASTERMODE_RESET (0 << AD16C4T_CON2_MMSEL_POSS) /*!< Reset mode*/ +#define MD_AD16C4T_MASTERMODE_ENABLE (1 << AD16C4T_CON2_MMSEL_POSS) /*!< Enable mode*/ +#define MD_AD16C4T_MASTERMODE_UPDATE (2 << AD16C4T_CON2_MMSEL_POSS) /*!< Update mode*/ +#define MD_AD16C4T_MASTERMODE_COMPAREPULSE (3 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare Pulse mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE1 (4 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 1 mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE2 (5 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 2 mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE3 (6 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 3 mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE4 (7 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 4 mode*/ + +#define MD_AD16C4T_DMASELECTION_COMPARE (0 << AD16C4T_CON2_CCDMASEL_POS) /*!< CCx DMA request sent when CCx event occurs*/ +#define MD_AD16C4T_DMASELECTION_UPDATE (1 << AD16C4T_CON2_CCDMASEL_POS) /*!< CCx DMA requests sent when update event occurs*/ + +#define MD_AD16C4T_UPDATESELECTION_COMG (0 << AD16C4T_CON2_CCUSEL_POS) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only*/ +#define MD_AD16C4T_UPDATESELECTION_BOTH (1 << AD16C4T_CON2_CCUSEL_POS) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI*/ + +#define MD_AD16C4T_CCPRELOAD_DISABLE (0 << AD16C4T_CON2_CCPCEN_POS) /*!< CCxE, CCxNE and OCxM bits are not preloaded*/ +#define MD_AD16C4T_CCPRELOAD_ENABLE (1 << AD16C4T_CON2_CCPCEN_POS) /*!< CCxE, CCxNE and OCxM bits are preloaded*/ + +/* AD16C4T_SMCON macros define*/ +#define MD_AD16C4T_ETRPOLARITY_NONINVERTED (0 << AD16C4T_SMCON_ETPOL_POS) /*!< ETR is non-inverted*/ +#define MD_AD16C4T_ETRPOLARITY_INVERTED (1 << AD16C4T_SMCON_ETPOL_POS) /*!< ETR is inverted*/ + +#define MD_AD16C4T_ETRFILTER_FDIV1 (0 << AD16C4T_SMCON_ETFLT_POSS) /*!< No filter*/ +#define MD_AD16C4T_ETRFILTER_FDIV1N2 (1 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 2*/ +#define MD_AD16C4T_ETRFILTER_FDIV1N4 (2 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 4*/ +#define MD_AD16C4T_ETRFILTER_FDIV1N8 (3 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV2N6 (4 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 2, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV2N8 (5 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 2, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV4N6 (6 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 4, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV4N8 (7 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 4, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV8N6 (8 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 8, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV8N8 (9 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 8, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV16N5 (10 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 5*/ +#define MD_AD16C4T_ETRFILTER_FDIV16N6 (11 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV16N8 (12 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV32N5 (13 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 5*/ +#define MD_AD16C4T_ETRFILTER_FDIV32N6 (14 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV32N8 (15 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 8*/ + +#define MD_AD16C4T_MASTERSLAVE_NODELAY (0 << AD16C4T_SMCON_MSCFG_POS) /*!< No action*/ +#define MD_AD16C4T_MASTERSLAVE_DELAY (1 << AD16C4T_SMCON_MSCFG_POS) /*!< The effect of an event on the trigger input (TRGI) is delayed to allow a perfect*/ + +#define MD_AD16C4T_TRIGGERSELECT_ITR0 (0 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 0*/ +#define MD_AD16C4T_TRIGGERSELECT_ITR1 (1 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 1*/ +#define MD_AD16C4T_TRIGGERSELECT_ITR2 (2 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 2*/ +#define MD_AD16C4T_TRIGGERSELECT_ITR3 (3 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 3*/ +#define MD_AD16C4T_TRIGGERSELECT_TI1FED (4 << AD16C4T_SMCON_TSSEL_POSS) /*!< TI1 Edge Detector*/ +#define MD_AD16C4T_TRIGGERSELECT_TI1FP1 (5 << AD16C4T_SMCON_TSSEL_POSS) /*!< Filtered Timer Input 1*/ +#define MD_AD16C4T_TRIGGERSELECT_TI2FP2 (6 << AD16C4T_SMCON_TSSEL_POSS) /*!< Filtered Timer Input 2*/ +#define MD_AD16C4T_TRIGGERSELECT_ETRF (7 << AD16C4T_SMCON_TSSEL_POSS) /*!< External Trigger input*/ + +#define MD_AD16C4T_OCREFCLEAR_CMP (0 << AD16C4T_SMCON_CHCSEL_POS) /*!< OCREF_CLR is connected to the CMP_IN input*/ +#define MD_AD16C4T_OCREFCLEAR_ETRF (1 << AD16C4T_SMCON_CHCSEL_POS) /*!< OCREF_CLR is connected to ETRF*/ + +#define MD_AD16C4T_SLAVEMODE_DISABLE (0 << AD16C4T_SMCON_SMODS_POSS) /*!< Slave mode disabled*/ +#define MD_AD16C4T_SLAVEMODE_ENCODER1 (1 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 1*/ +#define MD_AD16C4T_SLAVEMODE_ENCODER2 (2 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 2*/ +#define MD_AD16C4T_SLAVEMODE_ENCODER3 (3 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 3*/ +#define MD_AD16C4T_SLAVEMODE_RESET (4 << AD16C4T_SMCON_SMODS_POSS) /*!< Reset Mode*/ +#define MD_AD16C4T_SLAVEMODE_GATED (5 << AD16C4T_SMCON_SMODS_POSS) /*!< Gated Mode*/ +#define MD_AD16C4T_SLAVEMODE_TRIGGER (6 << AD16C4T_SMCON_SMODS_POSS) /*!< Trigger Mode*/ +#define MD_AD16C4T_SLAVEMODE_EXTERNALCLOCK (7 << AD16C4T_SMCON_SMODS_POSS) /*!< External Clock Mode 1*/ + +/* AD16C4T_IER IDR IVS RIF IFM ICR macros define*/ +#define MD_AD16C4T_INTERRUPTFALG_CC4OI (1 << AD16C4T_IER_CH4OVI_POS) /*!< Capture/Compare 4 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC3OI (1 << AD16C4T_IER_CH3OVI_POS) /*!< Capture/Compare 3 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC2OI (1 << AD16C4T_IER_CH2OVI_POS) /*!< Capture/Compare 2 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC1OI (1 << AD16C4T_IER_CH1OVI_POS) /*!< Capture/Compare 1 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_BI (1 << AD16C4T_IER_BRKI_POS) /*!< Break interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_TI (1 << AD16C4T_IER_TRGI_POS) /*!< Trigger interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_COMI (1 << AD16C4T_IER_COMI_POS) /*!< COM interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC4I (1 << AD16C4T_IER_CH4I_POS) /*!< Capture/Compare 4 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC3I (1 << AD16C4T_IER_CH3I_POS) /*!< Capture/Compare 3 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC2I (1 << AD16C4T_IER_CH2I_POS) /*!< Capture/Compare 2 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC1I (1 << AD16C4T_IER_CH1I_POS) /*!< Capture/Compare 1 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_UI (1 << AD16C4T_IER_UI_POS) /*!< Update interrupt*/ + +/* AD16C4T_SGE macros define*/ +#define MD_AD16C4T_EVENTGENERATION_BG (1 << AD16C4T_SGE_SGBRK_POS) /*!< Break generation*/ +#define MD_AD16C4T_EVENTGENERATION_TG (1 << AD16C4T_SGE_SGTRG_POS) /*!< Trigger generation*/ +#define MD_AD16C4T_EVENTGENERATION_COMG (1 << AD16C4T_SGE_SGCOM_POS) /*!< Capture/Compare control update generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC4G (1 << AD16C4T_SGE_SGCH4_POS) /*!< Capture/Compare 4 generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC3G (1 << AD16C4T_SGE_SGCH3_POS) /*!< Capture/Compare 3 generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC2G (1 << AD16C4T_SGE_SGCH2_POS) /*!< Capture/Compare 2 generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC1G (1 << AD16C4T_SGE_SGCH1_POS) /*!< Capture/Compare 1 generation*/ +#define MD_AD16C4T_EVENTGENERATION_UG (1 << AD16C4T_SGE_SGU_POS) /*!< Update generation*/ + +/* AD16C4T_CHMR1 CHMR2 output macros define*/ +#define MD_AD16C4T_OUTPUTMODE_DISABLE 0 /*!< Frozen*/ +#define MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH 1 /*!< Set channel 1 to active level on match*/ +#define MD_AD16C4T_OUTPUTMODE_LOWONMSTCH 2 /*!< Set channel 1 to inactive level on match*/ +#define MD_AD16C4T_OUTPUTMODE_TOGGLE 3 /*!< Toggle*/ +#define MD_AD16C4T_OUTPUTMODE_FORCELOW 4 /*!< Force inactive level*/ +#define MD_AD16C4T_OUTPUTMODE_FORCEHIGH 5 /*!< Force active level*/ +#define MD_AD16C4T_OUTPUTMODE_PWMMODE1 6 /*!< PWM mode 1*/ +#define MD_AD16C4T_OUTPUTMODE_PWMMODE2 7 /*!< PWM mode 2*/ + +#define MD_AD16C4T_CHMODE_OUTPUT 0 /*!< CCx channel is configured as output*/ +#define MD_AD16C4T_CHMODE_INPUT_DIRECT 1 /*!< CCx channel is configured as input, ICx is mapped direct*/ +#define MD_AD16C4T_CHMODE_INPUT_INDIRECT 2 /*!< CCx channel is configured as input, ICx is mapped indirect*/ +#define MD_AD16C4T_CHMODE_INPUT_TRC 3 /*!< CCx channel is configured as input, ICx is mapped TRC*/ + +/* AD16C4T_CHMR1 CHMR2 input macros define*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1 0 /*!< No filter*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1N2 1 /*!< fSAMPLING = fCK_INT, N = 2*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1N4 2 /*!< fSAMPLING = fCK_INT, N = 4*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1N8 3 /*!< fSAMPLING = fCK_INT, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV2N6 4 /*!< fSAMPLING = fDTS / 2, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV2N8 5 /*!< fSAMPLING = fDTS / 2, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV4N6 6 /*!< fSAMPLING = fDTS / 4, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV4N8 7 /*!< fSAMPLING = fDTS / 4, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV8N6 8 /*!< fSAMPLING = fDTS / 8, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV8N8 9 /*!< fSAMPLING = fDTS / 8, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV16N5 10 /*!< fSAMPLING = fDTS / 16, N = 5*/ +#define MD_AD16C4T_INPUTFILTER_FDIV16N6 11 /*!< fSAMPLING = fDTS / 16, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV16N8 12 /*!< fSAMPLING = fDTS / 16, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV32N5 13 /*!< fSAMPLING = fDTS / 32, N = 5*/ +#define MD_AD16C4T_INPUTFILTER_FDIV32N6 14 /*!< fSAMPLING = fDTS / 32, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV32N8 15 /*!< fSAMPLING = fDTS / 32, N = 8*/ + +#define MD_AD16C4T_INPUTPRESCALE_DIV1 0 /*!< no prescaler*/ +#define MD_AD16C4T_INPUTPRESCALE_DIV2 1 /*!< capture is done once every 2 events*/ +#define MD_AD16C4T_INPUTPRESCALE_DIV4 2 /*!< capture is done once every 4 events*/ +#define MD_AD16C4T_INPUTPRESCALE_DIV8 3 /*!< capture is done once every 8 events*/ + +/* AD16C4T_CCEP input macros define*/ +#define MD_AD16C4T_OUTPUTPOLARITY_HIGH 0 /*!< active high*/ +#define MD_AD16C4T_OUTPUTPOLARITY_LOW 1 /*!< active low*/ + +/* AD16C4T_BDCFG input macros define*/ +#define MD_AD16C4T_BREAKPOLARITY_LOW (0 << AD16C4T_BDCFG_BRKP_POS) /*!< Break input BRK is active low*/ +#define MD_AD16C4T_BREAKPOLARITY_HIGH (1 << AD16C4T_BDCFG_BRKP_POS) /*!< Break input BRK is active high */ + +#define MD_AD16C4T_OFFSTATERUN_DISABLE (0 << AD16C4T_BDCFG_OFFSSR_POS) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are disabled*/ +#define MD_AD16C4T_OFFSTATERUN_ENABLE (1 << AD16C4T_BDCFG_OFFSSR_POS) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are enabled*/ + +#define MD_AD16C4T_OFFSTATEIDLE_DISABLE (0 << AD16C4T_BDCFG_OFFSSI_POS) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are disabled*/ +#define MD_AD16C4T_OFFSTATEIDLE_ENABLE (1 << AD16C4T_BDCFG_OFFSSI_POS) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are forced*/ + +#define MD_AD16C4T_LOCKLEVEL_0 (0 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK OFF*/ +#define MD_AD16C4T_LOCKLEVEL_1 (1 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 1*/ +#define MD_AD16C4T_LOCKLEVEL_2 (2 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 2*/ +#define MD_AD16C4T_LOCKLEVEL_3 (3 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 3*/ + +/** + * @} MD_AD16C4T_Public_Constants + */ + +/* Public Macro ------------------------------------------------------------*/ +/** @defgroup MD_AD16C4T_Public_Macro Public Macro + * @brief AD16C4T module driver + * @{ + */ + +/** + * @brief Timer CON1 setup. + * @param timx AD16C4T instance + * @param value (DBGSEL | CMPSEL | CMPSELP | DFCKSEL | ARPEN | CMSEL | DIRSEL | SPMEN | UERSEL | DISUE | CNTEN) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CON1, value); +} + +/** + * @brief GET Timer CON1 register value. + * @param timx AD16C4T instance + * @retval Timer CON1 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CON1)); +} + +/** + * @brief Timer debug mode select. + * @param timx AD16C4T instance + * @param DebugSelect Debug mode output select + @arg @ref MD_AD16C4T_DEBUGSELECT_INPUT + @arg @ref MD_AD16C4T_DEBUGSELECT_OUTPUT + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_dbgsel(AD16C4T_TypeDef *timx, uint32_t DebugSelect) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_DBGSEL_MSK, DebugSelect); +} + +/** + * @brief Get timer debug mode select. + * @param timx AD16C4T instance + * @retval Timer debug mode select. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dbgsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DBGSEL_MSK) >> AD16C4T_CON1_DBGSEL_POS); +} + +/** + * @brief Timer compare input selection. + * @param timx AD16C4T instance + * @param CompareSelection Compare input selection + @arg @ref MD_AD16C4T_COMPAREINPUT_DISABLE + @arg @ref MD_AD16C4T_COMPAREINPUT_0 + @arg @ref MD_AD16C4T_COMPAREINPUT_1 + @arg @ref MD_AD16C4T_COMPAREINPUT_2 + @arg @ref MD_AD16C4T_COMPAREINPUT_3 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_cmpsel(AD16C4T_TypeDef *timx, uint32_t CompareSelection) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_CMPSEL_MSK, CompareSelection); +} + +/** + * @brief Get timer compare input selection. + * @param timx AD16C4T instance + * @retval Timer compare input selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmpsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CMPSEL_MSK) >> AD16C4T_CON1_CMPSEL_POSS); +} + +/** + * @brief Timer compare input selection polarity setup. + * @param timx AD16C4T instance + * @param ComparePolarity compare input selection polarity + @arg @ref MD_AD16C4T_COMPAREPOLARITY_LOW + @arg @ref MD_AD16C4T_COMPAREPOLARITY_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_cmpselp(AD16C4T_TypeDef *timx, uint32_t ComparePolarity) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_CMPSELP_MSK, ComparePolarity); +} + +/** + * @brief Get timer compare input selection polarity. + * @param timx AD16C4T instance + * @retval Timer compare input selection polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmpselp(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CMPSELP_MSK) >> AD16C4T_CON1_CMPSELP_POS); +} + +/** + * @brief Timer clock division setup. + * @param timx AD16C4T instance + * @param ClockDivision Clock division + @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV1 + @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV2 + @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV4 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_dfcksel(AD16C4T_TypeDef *timx, uint32_t ClockDivision) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_DFCKSEL_MSK, ClockDivision); +} + +/** + * @brief Get timer Clock division. + * @param timx AD16C4T instance + * @retval Timer Clock division. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dfcksel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DFCKSEL_MSK) >> AD16C4T_CON1_DFCKSEL_POSS); +} + +/** + * @brief Timer auto-reload preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_arpen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK); +} + +/** + * @brief Timer auto-reload preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_con1_arpen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK); +} + +/** + * @brief Indicates whether the timer auto-reload preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_arpen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK) == (AD16C4T_CON1_ARPEN_MSK)); +} + +/** + * @brief Timer center-aligned mode selection setup. + * @param timx AD16C4T instance + * @param CenterAlignedMode center-aligned mode selection + @arg @ref MD_AD16C4T_CENTERALIGNED_DISABLE + @arg @ref MD_AD16C4T_CENTERALIGNED_DOWN + @arg @ref MD_AD16C4T_CENTERALIGNED_UP + @arg @ref MD_AD16C4T_CENTERALIGNED_BOTH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_cmsel(AD16C4T_TypeDef *timx, uint32_t CenterAlignedMode) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_CMSEL_MSK, CenterAlignedMode); +} + +/** + * @brief Get timer center-aligned mode selection. + * @param timx AD16C4T instance + * @retval Timer center-aligned mode selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CMSEL_MSK) >> AD16C4T_CON1_CMSEL_POSS); +} + +/** + * @brief Timer counting direction setup. + * @param timx AD16C4T instance + * @param direction Counting direction + @arg @ref MD_AD16C4T_UPCOUNTER + @arg @ref MD_AD16C4T_DOWNCOUNTER + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_dirsel(AD16C4T_TypeDef *timx, uint32_t direction) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_DIRSEL_MSK, direction); +} + +/** + * @brief Get timer counting direction. + * @param timx AD16C4T instance + * @retval Timer counting direction. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dirsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DIRSEL_MSK) >> AD16C4T_CON1_DIRSEL_POS); +} + +/** + * @brief Timer one pulse mode enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_spmen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK); +} + +/** + * @brief Timer one pulse mode disable. + * @param timx AD16C4T instance + * @retval None. + */ + +__STATIC_INLINE void md_ad16c4t_disable_con1_spmen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK); +} + +/** + * @brief Indicates whether the timer one pulse mode is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_spmen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK) == (AD16C4T_CON1_SPMEN_MSK)); +} + +/** + * @brief Timer update request source setup. + * @param timx AD16C4T instance + * @param UpdateSource Update request source select + @arg @ref MD_AD16C4T_UPDATESOURCE_NORMAL + @arg @ref MD_AD16C4T_UPDATESOURCE_COUNTER + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_uersel(AD16C4T_TypeDef *timx, uint32_t UpdateSource) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_UERSEL_MSK, UpdateSource); +} + +/** + * @brief Get timer update request source. + * @param timx AD16C4T instance + * @retval Timer update request source. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_uersel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_UERSEL_MSK) >> AD16C4T_CON1_UERSEL_POS); +} + +/** + * @brief Timer update event enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_disue(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK); +} + +/** + * @brief Timer update event disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disble_con1_disue(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK); +} + +/** + * @brief Indicates whether the timer update event is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_disue(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK) == (AD16C4T_CON1_DISUE_MSK)); +} + +/** + * @brief Timer counter enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_cnten(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK); +} + + +/** + * @brief Timer counter disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_con1_cnten(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_cnten(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK) == (AD16C4T_CON1_CNTEN_MSK)); +} + +/** + * @brief Timer CON2 setup. + * @param timx AD16C4T instance + * @param value (OISS4 | OISS3N | OISS3 | OISS2N | OISS2 | OISS1N | OISS1 | I1SEL | MMSEL | CCDMASEL | CCUSEL | CCPCEN) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CON2, value); +} + +/** + * @brief GET Timer CON2 register value. + * @param timx AD16C4T instance + * @retval Timer CON2 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CON2)); +} + +/** + * @brief Timer output idle state 4 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss4(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS4_MSK, (IdleOutput << AD16C4T_CON2_OISS4_POS)); +} + +/** + * @brief Get timer output idle state 4. + * @param timx AD16C4T instance + * @retval Timer output idle state 4. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss4(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS4_MSK) >> AD16C4T_CON2_OISS4_POS); +} + +/** + * @brief Timer output idle state 3N setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss3n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS3N_MSK, (IdleOutput << AD16C4T_CON2_OISS3N_POS)); +} + +/** + * @brief Get timer output idle state 3N. + * @param timx AD16C4T instance + * @retval Timer output idle state 3N. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss3n(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS3N_MSK) >> AD16C4T_CON2_OISS3N_POS); +} + +/** + * @brief Timer output idle state 3 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss3(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS3_MSK, (IdleOutput << AD16C4T_CON2_OISS3_POS)); +} + +/** + * @brief Get timer output idle state 3. + * @param timx AD16C4T instance + * @retval Timer output idle state 3. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss3(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS3_MSK) >> AD16C4T_CON2_OISS3_POS); +} + +/** + * @brief Timer output idle state 2N setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss2n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS2N_MSK, (IdleOutput << AD16C4T_CON2_OISS2N_POS)); +} + +/** + * @brief Get timer output idle state 2N. + * @param timx AD16C4T instance + * @retval Timer output idle state 2N. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss2n(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS2N_MSK) >> AD16C4T_CON2_OISS2N_POS); +} + +/** + * @brief Timer output idle state 2 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss2(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS2_MSK, (IdleOutput << AD16C4T_CON2_OISS2_POS)); +} + +/** + * @brief Get timer output idle state 2. + * @param timx AD16C4T instance + * @retval Timer output idle state 2. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss2(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS2_MSK) >> AD16C4T_CON2_OISS2_POS); +} + +/** + * @brief Timer output idle state 1N setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss1n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS1N_MSK, (IdleOutput << AD16C4T_CON2_OISS1N_POS)); +} + +/** + * @brief Get timer output idle state 1N. + * @param timx AD16C4T instance + * @retval Timer output idle state 1N. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss1n(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS1N_MSK) >> AD16C4T_CON2_OISS1N_POS); +} + +/** + * @brief Timer output idle state 1 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss1(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS1_MSK, (IdleOutput << AD16C4T_CON2_OISS1_POS)); +} + +/** + * @brief Get timer output idle state 1. + * @param timx AD16C4T instance + * @retval Timer output idle state 1. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss1(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS1_MSK) >> AD16C4T_CON2_OISS1_POS); +} + +/** + * @brief Timer TI1 selection setup. + * @param timx AD16C4T instance + * @param TI1Input TI1 input select + @arg @ref MD_AD16C4T_TI1INPUT_CH1 + @arg @ref MD_AD16C4T_TI1INPUT_XOR + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_i1sel(AD16C4T_TypeDef *timx, uint32_t TI1Input) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_I1SEL_MSK, TI1Input); +} + +/** + * @brief Get timer TI1 selection. + * @param timx AD16C4T instance + * @retval Timer TI1 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_i1sel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_I1SEL_MSK) >> AD16C4T_CON2_I1SEL_POS); +} + +/** + * @brief Timer master mode selection setup. + * @param timx AD16C4T instance + * @param MasterMode Master mode selection + @arg @ref MD_AD16C4T_MASTERMODE_RESET + @arg @ref MD_AD16C4T_MASTERMODE_ENABLE + @arg @ref MD_AD16C4T_MASTERMODE_UPDATE + @arg @ref MD_AD16C4T_MASTERMODE_COMPAREPULSE + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE1 + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE2 + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE3 + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE4 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_mmsel(AD16C4T_TypeDef *timx, uint32_t MasterMode) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_MMSEL_MSK, MasterMode); +} + +/** + * @brief Get timer master mode selection. + * @param timx AD16C4T instance + * @retval Timer master mode selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_mmsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_MMSEL_MSK) >> AD16C4T_CON2_MMSEL_POSS); +} + +/** + * @brief Timer capture/compare DMA selection setup. + * @param timx AD16C4T instance + * @param DMASelection Capture/compare DMA selection + @arg @ref MD_AD16C4T_DMASELECTION_COMPARE + @arg @ref MD_AD16C4T_DMASELECTION_UPDATE + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_ccdmasel(AD16C4T_TypeDef *timx, uint32_t DMASelection) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_CCDMASEL_MSK, DMASelection); +} + +/** + * @brief Get timer capture/compare DMA selection. + * @param timx AD16C4T instance + * @retval Timer capture/compare DMA selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_ccdmasel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_CCDMASEL_MSK) >> AD16C4T_CON2_CCDMASEL_POS); +} + +/** + * @brief Timer capture/compare control update selection setup. + * @param timx AD16C4T instance + * @param UpdateSelection Capture/compare control update selection + @arg @ref MD_AD16C4T_UPDATESELECTION_COMG + @arg @ref MD_AD16C4T_UPDATESELECTION_BOTH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_ccusel(AD16C4T_TypeDef *timx, uint32_t UpdateSelection) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_CCUSEL_MSK, UpdateSelection); +} + +/** + * @brief Get timer capture/compare control update selection. + * @param timx AD16C4T instance + * @retval Timer capture/compare control update selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_ccusel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_CCUSEL_MSK) >> AD16C4T_CON2_CCUSEL_POS); +} + +/** + * @brief Timer capture/compare preloaded control enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con2_ccpcen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK); +} + +/** + * @brief Timer capture/compare preloaded control disable. + * @param timx AD16C4T instance + * @retval None. + */ + +__STATIC_INLINE void md_ad16c4t_disable_con2_ccpcen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK); +} + +/** + * @brief Indicates whether the timer capture/compare preloaded control is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con2_ccpcen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK) == (AD16C4T_CON2_CCPCEN_MSK)); +} + +/** + * @brief Timer SMCON setup. + * @param timx AD16C4T instance + * @param value (ETPOL | ECM2EN | ETFLT | MSCFG | TSSEL | CHCSEL | SMODS) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->SMCON, value); +} + +/** + * @brief GET Timer SMCON register value. + * @param timx AD16C4T instance + * @retval Timer SMCON register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->SMCON)); +} + +/** + * @brief Timer external trigger polarity setup. + * @param timx AD16C4T instance + * @param ETRPolarity External trigger polarity + @arg @ref MD_AD16C4T_ETRPOLARITY_NONINVERTED + @arg @ref MD_AD16C4T_ETRPOLARITY_INVERTED + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_etpol(AD16C4T_TypeDef *timx, uint32_t ETRPolarity) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_ETPOL_MSK, ETRPolarity); +} + +/** + * @brief Get timer external trigger polarity. + * @param timx AD16C4T instance + * @retval Timer external trigger polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_etpol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ETPOL_MSK) >> AD16C4T_SMCON_ETPOL_POS); +} + +/** + * @brief Timer external clock enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_smcon_ecm2en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK); +} + + +/** + * @brief Timer external clock disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_smcon_ecm2en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK); +} + +/** + * @brief Indicates whether the timer external clock is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_smcon_ecm2en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK) == (AD16C4T_SMCON_ECM2EN_MSK)); +} + +/** + * @brief Timer external trigger filter setup. + * @param timx AD16C4T instance + * @param ETRFilter External trigger filter + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_etflt(AD16C4T_TypeDef *timx, uint32_t ETRFilter) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_ETFLT_MSK, ETRFilter); +} + +/** + * @brief Get timer external trigger filter. + * @param timx AD16C4T instance + * @retval Timer external trigger filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_etflt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ETFLT_MSK) >> AD16C4T_SMCON_ETFLT_POSS); +} + +/** + * @brief Timer master/slave mode setup. + * @param timx AD16C4T instance + * @param MSMode master/slave mode + @arg @ref MD_AD16C4T_MASTERSLAVE_NODELAY + @arg @ref MD_AD16C4T_MASTERSLAVE_DELAY + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_mscfg(AD16C4T_TypeDef *timx, uint32_t MSMode) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_MSCFG_MSK, MSMode); +} + +/** + * @brief Get timer master/slave mode. + * @param timx AD16C4T instance + * @retval Timer master/slave mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_mscfg(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_MSCFG_MSK) >> AD16C4T_SMCON_MSCFG_POS); +} + +/** + * @brief Timer trigger selection setup. + * @param timx AD16C4T instance + * @param TriggerSelect Trigger selection + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR0 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR1 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR2 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR3 + @arg @ref MD_AD16C4T_TRIGGERSELECT_TI1FED + @arg @ref MD_AD16C4T_TRIGGERSELECT_TI1FP1 + @arg @ref MD_AD16C4T_TRIGGERSELECT_TI2FP2 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ETRF + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_tssel(AD16C4T_TypeDef *timx, uint32_t TriggerSelect) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_TSSEL_MSK, TriggerSelect); +} + +/** + * @brief Get timer trigger selection. + * @param timx AD16C4T instance + * @retval Timer trigger selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_tssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_TSSEL_MSK) >> AD16C4T_SMCON_TSSEL_POSS); +} + +/** + * @brief Timer OCREF clear selection setup. + * @param timx AD16C4T instance + * @param OCREFSelect OCREF clear selection + @arg @ref MD_AD16C4T_OCREFCLEAR_CMP + @arg @ref MD_AD16C4T_OCREFCLEAR_ETRF + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_chcsel(AD16C4T_TypeDef *timx, uint32_t OCREFSelect) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_CHCSEL_MSK, OCREFSelect); +} + +/** + * @brief Get timer OCREF clear selection. + * @param timx AD16C4T instance + * @retval Timer OCREF clear selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_chcsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_CHCSEL_MSK) >> AD16C4T_SMCON_CHCSEL_POS); +} + +/** + * @brief Timer slave mode selection setup. + * @param timx AD16C4T instance + * @param SlaveMode Slave mode selection + @arg @ref MD_AD16C4T_SLAVEMODE_DISABLE + @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER1 + @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER2 + @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER3 + @arg @ref MD_AD16C4T_SLAVEMODE_RESET + @arg @ref MD_AD16C4T_SLAVEMODE_GATED + @arg @ref MD_AD16C4T_SLAVEMODE_TRIGGER + @arg @ref MD_AD16C4T_SLAVEMODE_EXTERNALCLOCK + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_smods(AD16C4T_TypeDef *timx, uint32_t SlaveMode) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_SMODS_MSK, SlaveMode); +} + +/** + * @brief Get timer slave mode selection. + * @param timx AD16C4T instance + * @retval Timer slave mode selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_smods(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_SMODS_MSK) >> AD16C4T_SMCON_SMODS_POSS); +} + +/** + * @brief Timer IER setup. + * @param timx AD16C4T instance + * @param value (CH4OVI | CH3OVI | CH2OVI | CH1OVI | BRKI | TRGI | COMI | CH4I | CH3I | CH2I | CH1I | UI) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ier(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->IER, value); +} + +/** + * @brief Timer cpture/compare 4 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch4ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH4OVI_MSK); +} + +/** + * @brief Timer cpture/compare 3 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch3ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH3OVI_MSK); +} + +/** + * @brief Timer cpture/compare 2 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch2ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH2OVI_MSK); +} + +/** + * @brief Timer cpture/compare 1 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch1ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH1OVI_MSK); +} + +/** + * @brief Timer break interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_brki(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_BRKI_MSK); +} + +/** + * @brief Timer trigger interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_trgi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_TRGI_MSK); +} + +/** + * @brief Timer COM interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_comi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_COMI_MSK); +} + +/** + * @brief Timer capture/compare 4 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch4i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH4I_MSK); +} + +/** + * @brief Timer capture/compare 3 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch3i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH3I_MSK); +} + +/** + * @brief Timer capture/compare 2 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch2i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH2I_MSK); +} + +/** + * @brief Timer capture/compare 1 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch1i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH1I_MSK); +} + +/** + * @brief Timer update interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ui(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_UI_MSK); +} + +/** + * @brief Timer IDR setup. + * @param timx AD16C4T instance + * @param value (CH4OVI | CH3OVI | CH2OVI | CH1OVI | BRKI | TRGI | COMI | CH4I | CH3I | CH2I | CH1I | UI) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_idr(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->IDR, value); +} + +/** + * @brief Timer cpture/compare 4 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch4ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH4OVI_MSK); +} + +/** + * @brief Timer cpture/compare 3 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch3ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH3OVI_MSK); +} + +/** + * @brief Timer cpture/compare 2 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch2ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH2OVI_MSK); +} + +/** + * @brief Timer cpture/compare 1 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch1ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH1OVI_MSK); +} + +/** + * @brief Timer break interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_brki(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_BRKI_MSK); +} + +/** + * @brief Timer trigger interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_trgi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_TRGI_MSK); +} + +/** + * @brief Timer COM interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_comi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_COMI_MSK); +} + +/** + * @brief Timer capture/compare 4 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch4i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH4I_MSK); +} + +/** + * @brief Timer capture/compare 3 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch3i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH3I_MSK); +} + +/** + * @brief Timer capture/compare 2 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch2i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH2I_MSK); +} + +/** + * @brief Timer capture/compare 1 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch1i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH1I_MSK); +} + +/** + * @brief Timer update interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ui(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_UI_MSK); +} + +/** + * @brief Get timer IVS setup. + * @param timx AD16C4T instance + * @retval Timer IVS setup. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ivs(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->IVS)); +} + +/** + * @brief Indicates whether the timer capture/compare 4 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch4ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH4OVI_MSK) == (AD16C4T_IVS_CH4OVI_MSK)); +} + +/** + * @brief Indicates whether the timer capture/compare 3 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch3ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH3OVI_MSK) == (AD16C4T_IVS_CH3OVI_MSK)); +} + +/** + * @brief Indicates whether the timer cpture/compare 2 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch2ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH2OVI_MSK) == (AD16C4T_IVS_CH2OVI_MSK)); +} + +/** + * @brief Indicates whether the timer capture/compare 1 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch1ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH1OVI_MSK) == (AD16C4T_IVS_CH1OVI_MSK)); +} + +/** + * @brief Indicates whether the timer break interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_brki(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_BRKI_MSK) == (AD16C4T_IVS_BRKI_MSK)); +} + +/** + * @brief Indicates whether the timer trigger interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_trgi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_TRGI_MSK) == (AD16C4T_IVS_TRGI_MSK)); +} + +/** + * @brief Indicates whether the timer COM interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_comi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_COMI_MSK) == (AD16C4T_IVS_COMI_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch4i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH4I_MSK) == (AD16C4T_IVS_CH4I_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch3i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH3I_MSK) == (AD16C4T_IVS_CH3I_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch2i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH2I_MSK) == (AD16C4T_IVS_CH2I_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch1i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH1I_MSK) == (AD16C4T_IVS_CH1I_MSK)); +} + +/** + * @brief Indicates whether the timer update interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ui(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_UI_MSK) == (AD16C4T_IVS_UI_MSK)); +} + +/** + * @brief Get timer RIF flag. + * @param timx AD16C4T instance + * @retval Timer RIF flag. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_rif(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->RIF)); +} + +/** + * @brief Get timer capture/compare 4 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch4ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH4OVI_MSK) == (AD16C4T_RIF_CH4OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 3 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch3ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH3OVI_MSK) == (AD16C4T_RIF_CH3OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 2 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch2ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH2OVI_MSK) == (AD16C4T_RIF_CH2OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 1 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch1ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH1OVI_MSK) == (AD16C4T_RIF_CH1OVI_MSK)); +} + +/** + * @brief Get timer break interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_brki(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_BRKI_MSK) == (AD16C4T_RIF_BRKI_MSK)); +} + +/** + * @brief Get timer trigger interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_trgi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_TRGI_MSK) == (AD16C4T_RIF_TRGI_MSK)); +} + +/** + * @brief Get timer COM interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_comi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_COMI_MSK) == (AD16C4T_RIF_COMI_MSK)); +} + +/** + * @brief Get timer capture/compare 4 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch4i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH4I_MSK) == (AD16C4T_RIF_CH4I_MSK)); +} + +/** + * @brief Get timer capture/compare 3 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch3i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH3I_MSK) == (AD16C4T_RIF_CH3I_MSK)); +} + +/** + * @brief Get timer capture/compare 2 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch2i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH2I_MSK) == (AD16C4T_RIF_CH2I_MSK)); +} + +/** + * @brief Get timer capture/compare 1 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch1i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH1I_MSK) == (AD16C4T_RIF_CH1I_MSK)); +} + +/** + * @brief Get timer update interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ui(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_UI_MSK) == (AD16C4T_RIF_UI_MSK)); +} + +/** + * @brief Get timer IFM flag. + * @param timx AD16C4T instance + * @retval Timer IFM flag. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ifm(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->IFM)); +} + +/** + * @brief Get timer capture/compare 4 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch4ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH4OVI_MSK) == (AD16C4T_IFM_CH4OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 3 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch3ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH3OVI_MSK) == (AD16C4T_IFM_CH3OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 2 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch2ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH2OVI_MSK) == (AD16C4T_IFM_CH2OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 1 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch1ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH1OVI_MSK) == (AD16C4T_IFM_CH1OVI_MSK)); +} + +/** + * @brief Get timer break interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_brki(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_BRKI_MSK) == (AD16C4T_IFM_BRKI_MSK)); +} + +/** + * @brief Get timer trigger interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_trgi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_TRGI_MSK) == (AD16C4T_IFM_TRGI_MSK)); +} + +/** + * @brief Get timer COM interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_comi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_COMI_MSK) == (AD16C4T_IFM_COMI_MSK)); +} + +/** + * @brief Get timer capture/compare 4 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch4i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH4I_MSK) == (AD16C4T_IFM_CH4I_MSK)); +} + +/** + * @brief Get timer capture/compare 3 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch3i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH3I_MSK) == (AD16C4T_IFM_CH3I_MSK)); +} + +/** + * @brief Get timer capture/compare 2 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch2i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH2I_MSK) == (AD16C4T_IFM_CH2I_MSK)); +} + +/** + * @brief Get timer capture/compare 1 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch1i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH1I_MSK) == (AD16C4T_IFM_CH1I_MSK)); +} + +/** + * @brief Get timer update interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ui(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_UI_MSK) == (AD16C4T_IFM_UI_MSK)); +} + +/** + * @brief Timer ICR setup. + * @param timx AD16C4T instance + * @param value (CC4OI | CC3OI | CC2OI | CC1OI | BI | TI | COMI | CC4I | CC3I | CC2I | CC1I | UI) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_icr(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->ICR, value); +} + +/** + * @brief Clear timer cpture/compare 4 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch4ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH4OVI_MSK); +} + +/** + * @brief Clear timer cpture/compare 3 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch3ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH3OVI_MSK); +} + +/** + * @brief Clear timer cpture/compare 2 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch2ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH2OVI_MSK); +} + +/** + * @brief Clear timer cpture/compare 1 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch1ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH1OVI_MSK); +} + +/** + * @brief Clear timer break interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_brki(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_BRKI_MSK); +} + +/** + * @brief Clear timer trigger interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_trgi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_TRGI_MSK); +} + +/** + * @brief Clear timer COM interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_comi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_COMI_MSK); +} + +/** + * @brief Clear timer capture/compare 4 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch4i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH4I_MSK); +} + +/** + * @brief Clear timer capture/compare 3 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch3i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH3I_MSK); +} + +/** + * @brief Clear timer capture/compare 2 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch2i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH2I_MSK); +} + +/** + * @brief Clear timer capture/compare 1 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch1i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH1I_MSK); +} + +/** + * @brief Clear timer upadte flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ui(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_UI_MSK); +} + +/** + * @brief Timer SGE setup. + * @param timx AD16C4T instance + * @param value (SGBRK | SGTRG | SGCOM | SGCH4 | SGCH3 | SGCH2 | SGCH1 | SGU) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->SGE, value); +} + +/** + * @brief Timer break generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgbrk(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGBRK_MSK); +} + +/** + * @brief Timer trigger generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgtrg(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGTRG_MSK); +} + +/** + * @brief Timer COM generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgcom(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCOM_MSK); +} + +/** + * @brief Timer Capture/Compare 4 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch4(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH4_MSK); +} + +/** + * @brief Timer Capture/Compare 3 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch3(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH3_MSK); +} + +/** + * @brief Timer Capture/Compare 2 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch2(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH2_MSK); +} + +/** + * @brief Timer Capture/Compare 1 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch1(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH1_MSK); +} + +/** + * @brief Timer update generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgu(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGU_MSK); +} + +/** + * @brief Timer CHMR1 setup. + * @param timx AD16C4T instance + * @param value output (CH2OCLREN | CH2MOD | CH2PEN | CH2FEN | CC2SSEL | CH1OCLREN | CH1MOD | CH1PEN | CH1FEN | CC1SSEL) + * input (I2FLT | I2PRES | CC2SSEL | I1FLT | I1PRES | CC1SSEL) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CHMR1, value); +} + +/** + * @brief GET Timer CHMR1 register value. + * @param timx AD16C4T instance + * @retval Timer CHMR1 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CHMR1)); +} + +/** + * @brief Timer output compare 2 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK); +} + +/** + * @brief Timer output compare 2 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 2 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK)); +} + +/** + * @brief Timer output compare 2 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_ch2mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, (OutputMode << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); +} + +/** + * @brief Get timer output compare 2 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 2 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_ch2mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK) >> AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS); +} + +/** + * @brief Timer output compare 2 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK); +} + +/** + * @brief Timer output compare 2 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 2 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK)); +} + +/** + * @brief Timer output compare 2 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK); +} + +/** + * @brief Timer output compare 2 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 2 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 2 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_cc2ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 2 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 2 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_cc2ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK) >> AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS); +} + +/** + * @brief Timer output compare 1 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK); +} + +/** + * @brief Timer output compare 1 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 1 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK)); +} + +/** + * @brief Timer output compare 1 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_ch1mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, (OutputMode << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); +} + +/** + * @brief Get timer output compare 1 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 1 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_ch1mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK) >> AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS); +} + +/** + * @brief Timer output compare 1 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK); +} + +/** + * @brief Timer output compare 1 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 1 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK)); +} + +/** + * @brief Timer output compare 1 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK); +} + +/** + * @brief Timer output compare 1 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 1 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 1 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_cc1ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 1 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 1 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_cc1ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK) >> AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS); +} + +/** + * @brief Timer input capture 2 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i2flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2FLT_MSK, (InputFliter << AD16C4T_CHMR1_INPUT_I2FLT_POSS)); +} + +/** + * @brief Get timer input capture 2 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 2 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i2flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2FLT_MSK) >> AD16C4T_CHMR1_INPUT_I2FLT_POSS); +} + +/** + * @brief Timer input capture 2 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i2pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2PRES_MSK, (InputPrescale << AD16C4T_CHMR1_INPUT_I2PRES_POSS)); +} + +/** + * @brief Get timer input capture 2 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 2 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i2pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2PRES_MSK) >> AD16C4T_CHMR1_INPUT_I2PRES_POSS); +} + +/** + * @brief Timer cpture/compare 2 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_cc2ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC2SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_INPUT_CC2SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 2 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 2 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_cc2ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC2SSEL_MSK) >> AD16C4T_CHMR1_INPUT_CC2SSEL_POSS); +} + +/** + * @brief Timer input capture 1 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i1flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1FLT_MSK, (InputFliter << AD16C4T_CHMR1_INPUT_I1FLT_POSS)); +} + +/** + * @brief Get timer input capture 1 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 1 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i1flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1FLT_MSK) >> AD16C4T_CHMR1_INPUT_I1FLT_POSS); +} + +/** + * @brief Timer input capture 1 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i1pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1PRES_MSK, (InputPrescale << AD16C4T_CHMR1_INPUT_I1PRES_POSS)); +} + +/** + * @brief Get timer input capture 1 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 1 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i1pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1PRES_MSK) >> AD16C4T_CHMR1_INPUT_I1PRES_POSS); +} + +/** + * @brief Timer cpture/compare 1 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_cc1ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC1SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_INPUT_CC1SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 1 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 1 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_cc1ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC1SSEL_MSK) >> AD16C4T_CHMR1_INPUT_CC1SSEL_POSS); +} + +/** + * @brief Timer CHMR2 setup. + + * @param timx AD16C4T instance + * @param value output (CH4OCLREN | CH4MOD | CH4PEN | CH4FEN | CC4SSEL | CH3OCLREN | CH3MOD | CH3PEN | CH3FEN | CC3SSEL) + * input (I4FLT | I4PRES | CC4SSEL | I3FLT | I3PRES | CC3SSEL) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CHMR2, value); +} + +/** + * @brief GET Timer CHMR2 register value. + * @param timx AD16C4T instance + * @retval Timer CHMR2 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CHMR2)); +} + +/** + * @brief Timer output compare 4 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK); +} + +/** + * @brief Timer output compare 4 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 4 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK)); +} + +/** + * @brief Timer output compare 4 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_ch4mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK, (OutputMode << AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS)); +} + +/** + * @brief Get timer output compare 4 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 4 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_ch4mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK) >> AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS); +} + +/** + * @brief Timer output compare 4 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK); +} + +/** + * @brief Timer output compare 4 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 4 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK)); +} + +/** + * @brief Timer output compare 4 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK); +} + +/** + * @brief Timer output compare 4 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 4 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 4 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_cc4ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 4 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 4 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_cc4ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK) >> AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS); +} + +/** + * @brief Timer output compare 3 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK); +} + +/** + * @brief Timer output compare 3 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 3 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK)); +} + +/** + * @brief Timer output compare 3 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_ch3mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK, (OutputMode << AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS)); +} + +/** + * @brief Get timer output compare 3 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 3 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_ch3mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK) >> AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS); +} + +/** + * @brief Timer output compare 3 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK); +} + +/** + * @brief Timer output compare 3 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 3 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK)); +} + +/** + * @brief Timer output compare 3 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK); +} + +/** + * @brief Timer output compare 3 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 3 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 3 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_cc3ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 3 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 3 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_cc3ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK) >> AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS); +} + +/** + * @brief Timer input capture 4 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i4flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4FLT_MSK, (InputFliter << AD16C4T_CHMR2_INPUT_I4FLT_POSS)); +} + +/** + * @brief Get timer input capture 4 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 4 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i4flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4FLT_MSK) >> AD16C4T_CHMR2_INPUT_I4FLT_POSS); +} + +/** + * @brief Timer input capture 4 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i4pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4PRES_MSK, (InputPrescale << AD16C4T_CHMR2_INPUT_I4PRES_POSS)); +} + +/** + * @brief Get timer input capture 4 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 4 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i4pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4PRES_MSK) >> AD16C4T_CHMR2_INPUT_I4PRES_POSS); +} + +/** + * @brief Timer cpture/compare 4 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_cc4ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC4SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_INPUT_CC4SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 4 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 4 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_cc4ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC4SSEL_MSK) >> AD16C4T_CHMR2_INPUT_CC4SSEL_POSS); +} + +/** + * @brief Timer input capture 3 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i3flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3FLT_MSK, (InputFliter << AD16C4T_CHMR2_INPUT_I3FLT_POSS)); +} + +/** + * @brief Get timer input capture 3 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 3 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i3flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3FLT_MSK) >> AD16C4T_CHMR2_INPUT_I3FLT_POSS); +} + +/** + * @brief Timer input capture 3 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i3pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3PRES_MSK, (InputPrescale << AD16C4T_CHMR2_INPUT_I3PRES_POSS)); +} + +/** + * @brief Get timer input capture 3 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 3 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i3pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3PRES_MSK) >> AD16C4T_CHMR2_INPUT_I3PRES_POSS); +} + +/** + * @brief Timer cpture/compare 3 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_cc3ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC3SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_INPUT_CC3SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 3 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 3 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_cc3ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC3SSEL_MSK) >> AD16C4T_CHMR2_INPUT_CC3SSEL_POSS); +} + +/** + * @brief Timer CCEP setup. + * @param timx AD16C4T instance + * @param value (CC4NPOL | CC4POL | CC4EN | CC3NPOL | CC3NEN | CC3POL | CC3EN | CC2NPOL | + * CC2NEN | CC2POL | CC2EN | CC1NPOL | CC1NEN | CC1POL | CC1EN ) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCEP, value); +} + +/** + * @brief GET Timer CCEP register value. + * @param timx AD16C4T instance + * @retval Timer CCEP register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCEP)); +} + +/** + * @brief Timer capture/compare 4 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc4npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC4NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC4NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 4 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 4 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc4npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4NPOL_MSK) >> AD16C4T_CCEP_CC4NPOL_POS); +} + +/** + * @brief Timer capture/compare 4 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc4pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC4POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC4POL_POS)); +} + +/** + * @brief Get timer capture/compare 4 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 4 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc4pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4POL_MSK) >> AD16C4T_CCEP_CC4POL_POS); +} + +/** + * @brief Timer Capture/Compare 4 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc4en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK); +} + +/** + * @brief Timer Capture/Compare 4 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc4en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc4en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK) == (AD16C4T_CCEP_CC4EN_MSK)); +} + +/** + * @brief Timer capture/compare 3 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc3npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC3NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC3NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 3 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 3 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc3npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3NPOL_MSK) >> AD16C4T_CCEP_CC3NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 3 complementary output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc3nen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK); +} + +/** + * @brief Timer Capture/Compare 3 complementary output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc3nen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 complementary output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc3nen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK) == (AD16C4T_CCEP_CC3NEN_MSK)); +} + +/** + * @brief Timer capture/compare 3 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc3pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC3POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC3POL_POS)); +} + +/** + * @brief Get timer capture/compare 3 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 3 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc3pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3POL_MSK) >> AD16C4T_CCEP_CC3POL_POS); +} + +/** + * @brief Timer Capture/Compare 3 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc3en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK); +} + +/** + * @brief Timer Capture/Compare 3 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc3en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc3en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK) == (AD16C4T_CCEP_CC3EN_MSK)); +} + +/** + * @brief Timer capture/compare 2 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc2npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC2NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC2NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 2 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 2 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc2npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2NPOL_MSK) >> AD16C4T_CCEP_CC2NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 2 complementary output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc2nen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK); +} + +/** + * @brief Timer Capture/Compare 2 complementary output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc2nen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 complementary output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc2nen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK) == (AD16C4T_CCEP_CC2NEN_MSK)); +} + +/** + * @brief Timer capture/compare 2 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc2pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC2POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC2POL_POS)); +} + +/** + * @brief Get timer capture/compare 2 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 2 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc2pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2POL_MSK) >> AD16C4T_CCEP_CC2POL_POS); +} + +/** + * @brief Timer Capture/Compare 2 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc2en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK); +} + +/** + * @brief Timer Capture/Compare 2 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc2en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc2en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK) == (AD16C4T_CCEP_CC2EN_MSK)); +} + +/** + * @brief Timer capture/compare 1 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc1npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC1NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC1NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 1 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 1 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc1npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1NPOL_MSK) >> AD16C4T_CCEP_CC1NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 1 complementary output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc1nen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK); +} + +/** + * @brief Timer Capture/Compare 1 complementary output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc1nen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 complementary output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc1nen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK) == (AD16C4T_CCEP_CC1NEN_MSK)); +} + +/** + * @brief Timer capture/compare 1 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc1pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC1POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC1POL_POS)); +} + +/** + * @brief Get timer capture/compare 1 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 1 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc1pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1POL_MSK) >> AD16C4T_CCEP_CC1POL_POS); +} + +/** + * @brief Timer Capture/Compare 1 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc1en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK); +} + +/** + * @brief Timer Capture/Compare 1 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc1en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc1en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK) == (AD16C4T_CCEP_CC1EN_MSK)); +} + +/** + * @brief Timer COUNT setup. + * @param timx AD16C4T instance + * @param value COUNT + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_count(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->COUNT, value); +} + +/** + * @brief GET Timer COUNT register value. + * @param timx AD16C4T instance + * @retval Timer COUNT register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_count(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->COUNT)); +} + +/** + * @brief Timer counter value setup. + * @param timx AD16C4T instance + * @param counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_count_cntv(AD16C4T_TypeDef *timx, uint32_t counter) +{ + MODIFY_REG(timx->COUNT, AD16C4T_COUNT_CNTV_MSK, counter); +} + +/** + * @brief Get timer counter value. + * @param timx AD16C4T instance + * @retval Timer counter value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_cnt_cntv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->COUNT, AD16C4T_COUNT_CNTV_MSK) >> AD16C4T_COUNT_CNTV_POSS); +} + +/** + * @brief Timer PRES setup. + * @param timx AD16C4T instance + * @param value PRES + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_pres(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->PRES, value); +} + +/** + * @brief GET Timer PRES register value. + * @param timx AD16C4T instance + * @retval Timer PRES register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_pres(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->PRES)); +} + +/** + * @brief Timer prescaler value setup. + * @param timx AD16C4T instance + * @param prescaler Prescaler value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_pres_pscv(AD16C4T_TypeDef *timx, uint32_t prescaler) +{ + MODIFY_REG(timx->PRES, AD16C4T_PRES_PSCV_MSK, prescaler); +} + +/** + * @brief Get timer prescaler value. + * @param timx AD16C4T instance + * @retval Timer prescaler value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_pres_pscv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->PRES, AD16C4T_PRES_PSCV_MSK) >> AD16C4T_PRES_PSCV_POSS); +} + +/** + * @brief Timer AR setup. + * @param timx AD16C4T instance + * @param value AR + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ar(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->AR, value); +} + +/** + * @brief GET Timer AR register value. + * @param timx AD16C4T instance + * @retval Timer AR register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ar(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->AR)); +} + +/** + * @brief Timer auto-reload value setup. + * @param timx AD16C4T instance + * @param reload Auto-reload value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ar_arv(AD16C4T_TypeDef *timx, uint32_t reload) +{ + MODIFY_REG(timx->AR, AD16C4T_AR_ARV_MSK, reload); +} + +/** + * @brief Get timer auto-reload value. + * @param timx AD16C4T instance + * @retval Timer auto-reload value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ar_arv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->AR, AD16C4T_AR_ARV_MSK) >> AD16C4T_AR_ARV_POSS); +} + +/** + * @brief Timer REPAR setup. + * @param timx AD16C4T instance + * @param value REPAR + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_rcr(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->REPAR, value); +} + +/** + * @brief GET Timer REPAR register value. + * @param timx AD16C4T instance + * @retval Timer REPAR register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_repar(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->REPAR)); +} + +/** + * @brief Timer repetition counter value setup. + * @param timx AD16C4T instance + * @param repetition Repetition counter value (between Min_Data=0 and Max_Data=0xFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_repar_repv(AD16C4T_TypeDef *timx, uint32_t repetition) +{ + MODIFY_REG(timx->REPAR, AD16C4T_REPAR_REPV_MSK, repetition); +} + +/** + * @brief Get timer repetition counter value. + * @param timx AD16C4T instance + * @retval Timer repetition counter value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_repar_repv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->REPAR, AD16C4T_REPAR_REPV_MSK) >> AD16C4T_REPAR_REPV_POSS); +} + +/** + * @brief Timer CCVAL1 setup. + * @param timx AD16C4T instance + * @param value CCVAL1 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval1(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL1, value); +} + +/** + * @brief GET Timer CCVAL1 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL1 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval1(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL1)); +} + +/** + * @brief Timer capture/compare value 1 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 1 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval1_ccrv1(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL1, AD16C4T_CCVAL1_CCRV1_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 1. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 1. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval1_ccrv1(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL1, AD16C4T_CCVAL1_CCRV1_MSK) >> AD16C4T_CCVAL1_CCRV1_POSS); +} + +/** + * @brief Timer CCVAL2 setup. + * @param timx AD16C4T instance + * @param value CCVAL2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval2(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL2, value); +} + +/** + * @brief GET Timer CCVAL2 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL2 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval2(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL2)); +} + +/** + * @brief Timer capture/compare value 2 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 2 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval2_ccrv2(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL2, AD16C4T_CCVAL2_CCRV2_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 2. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 2. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval2_ccrv2(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL2, AD16C4T_CCVAL2_CCRV2_MSK) >> AD16C4T_CCVAL2_CCRV2_POSS); +} + +/** + * @brief Timer CCVAL3 setup. + * @param timx AD16C4T instance + * @param value CCVAL3 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval3(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL3, value); +} + +/** + * @brief GET Timer CCVAL3 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL3 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval3(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL3)); +} + +/** + * @brief Timer capture/compare value 3 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 3 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval3_ccrv3(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL3, AD16C4T_CCVAL3_CCRV3_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 3. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 3. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval3_ccrv3(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL3, AD16C4T_CCVAL3_CCRV3_MSK) >> AD16C4T_CCVAL3_CCRV3_POSS); +} + +/** + * @brief Timer CCVAL4 setup. + * @param timx AD16C4T instance + * @param value CCVAL4 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval4(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL4, value); +} + +/** + * @brief GET Timer CCVAL4 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL4 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval4(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL4)); +} + +/** + * @brief Timer capture/compare value 4 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 4 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval4_ccrv4(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL4, AD16C4T_CCVAL4_CCRV4_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 4. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 4. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval4_ccrv4(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL4, AD16C4T_CCVAL4_CCRV4_MSK) >> AD16C4T_CCVAL4_CCRV4_POSS); +} + +/** + * @brief Timer BDCFG setup. + * @param timx AD16C4T instance + * @param value (GOEN | AOEN | BRKP | BRKEN | OFFSSR | OFFSSI | LOCKLVL | DT) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->BDCFG, value); +} + +/** + * @brief GET Timer BDCFG register value. + * @param timx AD16C4T instance + * @retval Timer BDCFG register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->BDCFG)); +} + +/** + * @brief Timer main output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_bdcfg_goen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK); +} + +/** + * @brief Timer main output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_bdcfg_goen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK); +} + +/** + * @brief Indicates whether the timer main output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_goen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK) == (AD16C4T_BDCFG_GOEN_MSK)); +} + +/** + * @brief Timer automatic output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_bdcfg_aoen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK); +} + +/** + * @brief Timer automatic output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_bdcfg_aoen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK); +} + +/** + * @brief Indicates whether the timer automatic output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_aoen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK) == (AD16C4T_BDCFG_AOEN_MSK)); +} + +/** + * @brief Timer break polarity setup. + * @param timx AD16C4T instance + * @param BreakPolarity Break polarity + * @arg @ref MD_AD16C4T_BREAKPOLARITY_LOW + * @arg @ref MD_AD16C4T_BREAKPOLARITY_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_brkp(AD16C4T_TypeDef *timx, uint32_t BreakPolarity) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_BRKP_MSK, BreakPolarity); +} + +/** + * @brief Get timer break polarity. + * @param timx AD16C4T instance + * @retval Timer break polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_brkp(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKP_MSK) >> AD16C4T_BDCFG_BRKP_POS); +} + +/** + * @brief Timer break enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_bdcfg_brken(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK); +} + +/** + * @brief Timer break disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_bdcfg_brken(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK); +} + +/** + * @brief Indicates whether the timer break is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_brken(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK) == (AD16C4T_BDCFG_BRKEN_MSK)); +} + +/** + * @brief Timer off-state selection for run mode setup. + * @param timx AD16C4T instance + * @param OffStateRun Off-state selection for run mode + * @arg @ref MD_AD16C4T_OFFSTATERUN_DISABLE + * @arg @ref MD_AD16C4T_OFFSTATERUN_ENABLE + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_offssr(AD16C4T_TypeDef *timx, uint32_t OffStateRun) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_OFFSSR_MSK, OffStateRun); +} + +/** + * @brief Get timer off-state selection for run mode. + * @param timx AD16C4T instance + * @retval Timer off-state selection for run mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_offssr(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_OFFSSR_MSK) >> AD16C4T_BDCFG_OFFSSR_POS); +} + +/** + * @brief Timer off-state selection for idle mode setup. + * @param timx AD16C4T instance + * @param OffStateIdle Off-state selection for idle mode + * @arg @ref MD_AD16C4T_OFFSTATEIDLE_DISABLE + * @arg @ref MD_AD16C4T_OFFSTATEIDLE_ENABLE + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_offssi(AD16C4T_TypeDef *timx, uint32_t OffStateIdle) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_OFFSSI_MSK, OffStateIdle); +} + +/** + * @brief Get timer off-state selection for idle mode. + * @param timx AD16C4T instance + * @retval Timer off-state selection for idle mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_offssi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_OFFSSI_MSK) >> AD16C4T_BDCFG_OFFSSI_POS); +} + +/** + * @brief Timer lock configuration setup. + * @param timx AD16C4T instance + * @param LockLevel Lock configuration + * @arg @ref MD_AD16C4T_LOCKLEVEL_0 + * @arg @ref MD_AD16C4T_LOCKLEVEL_1 + * @arg @ref MD_AD16C4T_LOCKLEVEL_2 + * @arg @ref MD_AD16C4T_LOCKLEVEL_3 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_locklvl(AD16C4T_TypeDef *timx, uint32_t LockLevel) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_LOCKLVL_MSK, LockLevel); +} + +/** + * @brief Get timer lock configuration. + * @param timx AD16C4T instance + * @retval Timer lock configuration. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_locklvl(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_LOCKLVL_MSK) >> AD16C4T_BDCFG_LOCKLVL_POSS); +} + +/** + * @brief Timer dead-time generator setup. + * @param timx AD16C4T instance + * @param DeadTime Dead-time generator (between Min_Data=0 and Max_Data=0xFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_dt(AD16C4T_TypeDef *timx, uint32_t DeadTime) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_DT_MSK, DeadTime); +} + +/** + * @brief Get timer dead-time generator. + * @param timx AD16C4T instance + * @retval Timer dead-time generator. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_dt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_DT_MSK) >> AD16C4T_BDCFG_DT_POSS); +} + +/** + * @brief Timer DMAEN setup. + * @param timx AD16C4T instance + * @param value (TRGIDE | COMDE | CH4DE | CH3DE | CH2DE | CH1DE | UDE) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_dmaen(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->DMAEN, value); +} + +/** + * @brief GET Timer DMAEN register value. + * @param timx AD16C4T instance + * @retval Timer DMAEN register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_dmaen(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->DMAEN)); +} + +/** + * @brief Timer trigger DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_trgide(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK); +} + +/** + * @brief Timer trigger DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_trgide(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK); +} + +/** + * @brief Indicates whether the timer trigger DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_trgide(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK) == (AD16C4T_DMAEN_TRGIDE_MSK)); +} + +/** + * @brief Timer COM DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_comde(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK); +} + +/** + * @brief Timer COM DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_comde(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK); +} + +/** + * @brief Indicates whether the timer trigger COM request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_comde(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK) == (AD16C4T_DMAEN_COMDE_MSK)); +} + +/** + * @brief Timer Capture/Compare 4 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch4de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK); +} + +/** + * @brief Timer Capture/Compare 4 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch4de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch4de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK) == (AD16C4T_DMAEN_CH4DE_MSK)); +} + +/** + * @brief Timer Capture/Compare 3 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch3de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK); +} + +/** + * @brief Timer Capture/Compare 3 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch3de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch3de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK) == (AD16C4T_DMAEN_CH3DE_MSK)); +} + +/** + * @brief Timer Capture/Compare 2 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch2de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK); +} + +/** + * @brief Timer Capture/Compare 2 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch2de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch2de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK) == (AD16C4T_DMAEN_CH2DE_MSK)); +} + +/** + * @brief Timer Capture/Compare 1 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch1de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK); +} + +/** + * @brief Timer Capture/Compare 1 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch1de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch1de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK) == (AD16C4T_DMAEN_CH1DE_MSK)); +} + +/** + * @brief Timer update DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ude(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK); +} + +/** + * @brief Timer update DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ude(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare update DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ude(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK) == (AD16C4T_DMAEN_UDE_MSK)); +} +/** + * @} MD_AD16C4T_Public_Macro + */ + +/* Public functions -----------------------------------------------------------*/ + + + +/** + * @} AD16C4T + */ + + +#endif + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..3c3bdbc5f85bd817163d23908de1b3a97c8abc1a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h @@ -0,0 +1,6109 @@ +/** + ****************************************************************************** + * @file md_ADC.h + * @brief ES32F0271 ADC Header File. + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_ADC_H__ +#define __MD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_adc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined ADC + +/** @defgroup ADC ADC + * @brief ADC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup MD_ADC_Public_Constants ADC Public Constants + * @{ + */ + +/** + * @brief ADC Init structure. + */ +typedef struct +{ + uint8_t VRLS; + uint8_t SSx; + uint32_t Sel; + uint32_t Type; + uint32_t Cntini; + uint32_t Cnt; + uint8_t End; + uint8_t Ckdiv; +} md_adc_inittypedef; +/** @defgroup MD_ADC_CFG ADC_CFG Register + * @{ + */ +#define MD_ADC_CFG_TESTEN (0xEDU) /** @brief data ADC Test Enable */ + +#define MD_ADC_CFG_MODE_NORMAL (0x00000000U<CFG, ADC_CFG_TESTEN_MSK, MD_ADC_CFG_TESTEN<CFG, ADC_CFG_MODE_MSK, Mode<CFG, ADC_CFG_MODE_MSK))>>ADC_CFG_MODE_POS); +} + +/** + * @brief Set ADC Wait Counter Value. + * @note Set the wait cycle between each ADC sample. + * @param ADCx ADC Instance + * @param CNT Value between Min_Value=0x00 and Max_Value=0xFF + * @retval None + */ +__STATIC_INLINE void md_adc_set_srate_cnt(ADC_TypeDef *ADCx, uint32_t cnt) +{ + MODIFY_REG(ADCx->SRATE, ADC_SRATE_CNT_MSK, cnt<SRATE, ADC_SRATE_CNT_MSK))>>ADC_SRATE_CNT_POSS); +} + +/** + * @brief Set ADC Wait Counter Initial Value. + * @note Set the Initial Value of ADC wait counter. + * @param ADCx ADC Instance + * @param CNTINI + * @arg @ref CNTINI Value between Min_Value=0x00 and Max_Value=0xFF + * @retval None + */ +__STATIC_INLINE void md_adc_set_srate_cntini(ADC_TypeDef *adcx, uint32_t cntini) +{ + MODIFY_REG(adcx->SRATE, ADC_SRATE_CNTINI_MSK, cntini<SRATE, ADC_SRATE_CNTINI_MSK))>>ADC_SRATE_CNTINI_POSS); +} + +/** + * @brief Set ADC Converter Clock Division. + * @note Get the division ratio of ADC converter clock. 0 to 15 division ratio + * where 0 indicates no division is implemented. To modify CLKDIV, user + * should first set CLKEN to 0 and re-enable this bit after modification + * on CLKDIV. + * @param ADCx ADC Instance + * @param ADC Converter Clock Division + * @arg @ref MD_ADC_SRATE_CKDIV1 + * @arg @ref MD_ADC_SRATE_CKDIV2 + * @arg @ref MD_ADC_SRATE_CKDIV4 + * @arg @ref MD_ADC_SRATE_CKDIV6 + * @arg @ref MD_ADC_SRATE_CKDIV8 + * @arg @ref MD_ADC_SRATE_CKDIV10 + * @arg @ref MD_ADC_SRATE_CKDIV12 + * @arg @ref MD_ADC_SRATE_CKDIV14 + * @arg @ref MD_ADC_SRATE_CKDIV16 + * @arg @ref MD_ADC_SRATE_CKDIV18 + * @arg @ref MD_ADC_SRATE_CKDIV20 + * @arg @ref MD_ADC_SRATE_CKDIV22 + * @arg @ref MD_ADC_SRATE_CKDIV24 + * @arg @ref MD_ADC_SRATE_CKDIV26 + * @arg @ref MD_ADC_SRATE_CKDIV28 + * @arg @ref MD_ADC_SRATE_CKDIV30 + * @retval None + */ +__STATIC_INLINE void md_adc_set_srate_clkdiv(ADC_TypeDef *ADCx, uint32_t clkdiv) +{ + MODIFY_REG(ADCx->SRATE, ADC_SRATE_CKDIV_MSK, clkdiv<SRATE, ADC_SRATE_CKDIV_MSK))>>ADC_SRATE_CKDIV_POSS); +} + +/** + * @brief ADC clock enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_clken(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK); +} + +/** + * @brief ADC clock sisable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_clken(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK); +} + +/** + * @brief Check if ADC clock is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_clken(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK) == (ADC_SRATE_CKEN_MSK)); +} + +/** + * @brief Channel 15 Invert Control enable. + * @note This is used to invert the data of channel 15. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch15inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); +} + +/** + * @brief Channel 15 Invert Control disable. + * @note This is used to invert the data of channel 15. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch15inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); +} + +/** + * @brief Check if Channel 15 Invert Control is enabled. + * @note This is used to invert the data of channel 15. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch15inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK) == (ADC_CHINV_CH15INV_MSK)); +} + +/** + * @brief Channel 14 Invert Control enable. + * @note This is used to invert the data of channel 14. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch14inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK); +} + +/** + * @brief Channel 14 Invert Control disable. + * @note This is used to invert the data of channel 14. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch14inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK); +} + +/** + * @brief Check if Channel 14 Invert Control is enabled. + * @note This is used to invert the data of channel 14. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch14inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK) == (ADC_CHINV_CH14INV_MSK)); +} + +/** + * @brief Channel 13 Invert Control enable. + * @note This is used to invert the data of channel 13. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch13inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK); +} + +/** + * @brief Channel 13 Invert Control disable. + * @note This is used to invert the data of channel 13. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch13inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK); +} + +/** + * @brief Check if Channel 13 Invert Control is enabled. + * @note This is used to invert the data of channel 13. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch13inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK) == (ADC_CHINV_CH13INV_MSK)); +} + +/** + * @brief Channel 12 Invert Control enable. + * @note This is used to invert the data of channel 12. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch12inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK); +} + +/** + * @brief Channel 12 Invert Control disable. + * @note This is used to invert the data of channel 12. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch12inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK); +} + +/** + * @brief Check if Channel 12 Invert Control is enabled. + * @note This is used to invert the data of channel 12. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch12inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK) == (ADC_CHINV_CH12INV_MSK)); +} + +/** + * @brief Channel 11 Invert Control enable. + * @note This is used to invert the data of channel 11. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch11inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); +} + +/** + * @brief Channel 11 Invert Control disable. + * @note This is used to invert the data of channel 11. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch11inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH11INV_MSK); +} + +/** + * @brief Check if Channel 11 Invert Control is enabled. + * @note This is used to invert the data of channel 11. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch11inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH11INV_MSK) == (ADC_CHINV_CH11INV_MSK)); +} + +/** + * @brief Channel 10 Invert Control enable. + * @note This is used to invert the data of channel 10. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch10inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK); +} + +/** + * @brief Channel 10 Invert Control disable. + * @note This is used to invert the data of channel 10. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch10inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK); +} + +/** + * @brief Check if Channel 10 Invert Control is enabled. + * @note This is used to invert the data of channel 10. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch10inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK) == (ADC_CHINV_CH10INV_MSK)); +} + +/** + * @brief Channel 9 Invert Control enable. + * @note This is used to invert the data of channel 9. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch9inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK); +} + +/** + * @brief Channel 9 Invert Control disable. + * @note This is used to invert the data of channel 9. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch9inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK); +} + +/** + * @brief Check if Channel 9 Invert Control is enabled. + * @note This is used to invert the data of channel 9. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch9inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK) == (ADC_CHINV_CH9INV_MSK)); +} + +/** + * @brief Channel 8 Invert Control enable. + * @note This is used to invert the data of channel 8. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch8inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK); +} + +/** + * @brief Channel 8 Invert Control disable. + * @note This is used to invert the data of channel 8. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch8inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK); +} + +/** + * @brief Check if Channel 8 Invert Control is enabled. + * @note This is used to invert the data of channel 8. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch8inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK) == (ADC_CHINV_CH8INV_MSK)); +} + +/** + * @brief Channel 7 Invert Control enable. + * @note This is used to invert the data of channel 7. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch7inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK); +} + +/** + * @brief Channel 7 Invert Control disable. + * @note Disable invert data channel 7. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch7inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK); +} + +/** + * @brief Check if Channel 7 Invert Control is enabled. + * @note Check invert state of data channel 7. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch7inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK) == (ADC_CHINV_CH7INV_MSK)); +} + +/** + * @brief Channel 6 Invert Control enable. + * @note This is used to invert the data of channel 6. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch6inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK); +} + +/** + * @brief Channel 6 Invert Control disable. + * @note Disable invert data channel 6. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch6inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK); +} + +/** + * @brief Check if Channel 6 Invert Control is enabled. + * @note Check invert state of data channel 6. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch6inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK) == (ADC_CHINV_CH6INV_MSK)); +} + +/** + * @brief Channel 5 Invert Control enable. + * @note This is used to invert the data of channel 5. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch5inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK); +} + +/** + * @brief Channel 5 Invert Control disable. + * @note Disable invert data channel 5. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch5inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK); +} + +/** + * @brief Check if Channel 5 Invert Control is enabled. + * @note Check invert state of data channel 5. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch5inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK) == (ADC_CHINV_CH5INV_MSK)); +} + +/** + * @brief Channel 4 Invert Control enable. + * @note This is used to invert the data of channel 4. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch4inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK); +} + +/** + * @brief Channel 4 Invert Control disable. + * @note Disable invert data channel 4. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch4inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK); +} + +/** + * @brief Check if Channel 4 Invert Control is enabled. + * @note Check invert state of data channel 4. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch4inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK) == (ADC_CHINV_CH4INV_MSK)); +} + +/** + * @brief Channel 3 Invert Control enable. + * @note This is used to invert the data of channel 3. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch3inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK); +} + +/** + * @brief Channel 3 Invert Control disable. + * @note Disable invert data channel 3. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch3inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK); +} + +/** + * @brief Check if Channel 3 Invert Control is enabled. + * @note Check invert state of data of channel 3. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch3inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK) == (ADC_CHINV_CH3INV_MSK)); +} + +/** + * @brief Channel 2 Invert Control enable. + * @note This is used to invert the data of channel 2. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch2inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK); +} + +/** + * @brief Channel 2 Invert Control disable. + * @note Disable invert data channel 2. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch2inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK); +} + +/** + * @brief Check if Channel 2 Invert Control is enabled. + * @note Check invert state of data of channel 2. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch2inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK) == (ADC_CHINV_CH2INV_MSK)); +} + +/** + * @brief Channel 1 Invert Control enable. + * @note This is used to invert the data of channel 1. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch1inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK); +} + +/** + * @brief Channel 1 Invert Control disable. + * @note Disable invert data channel 1. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch1inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK); +} + +/** + * @brief Check if Channel 1 Invert Control is enabled. + * @note Check invert of data of channel 1. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch1inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK) == (ADC_CHINV_CH1INV_MSK)); +} + +/** + * @brief Channel 0 Invert Control enable. + * @note This is used to invert the data of channel 0. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch0inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK); +} + +/** + * @brief Channel 0 Invert Control disable. + * @note Disable invert data channel 0. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch0inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK); +} + +/** + * @brief Check if Channel 0 Invert Control is enabled. + * @note Check invert state of data of channel 0. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch0inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK) == (ADC_CHINV_CH0INV_MSK)); +} + +/** + * @brief Set ADC SRATE register. + * @note This is used to set SRATE register. + * @param ADCx ADC Instance + * @param SRATE + * @retval NONE. + */ +__STATIC_INLINE void md_adc_set_srate(ADC_TypeDef *adcx, uint32_t srate) +{ + WRITE_REG(adcx->SRATE, srate); +} + +/** + * @brief Get ADC SRATE register. + * @note This is used to read SRATE register. + * @param ADCx ADC Instance + * @param SRATE + * @retval SRATE Register Value. + */ +__STATIC_INLINE uint32_t md_adc_get_srate(ADC_TypeDef *adcx) +{ + return READ_REG(adcx->SRATE); +} + +/** + * @brief Set ADC Channel 7 PGA Gain. + * @note This is used to select channel 7 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch7pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH7PGA_MSK, Gain<GAINL, ADC_GAINL_CH7PGA_MSK)>>ADC_GAINL_CH7PGA_POSS); +} + +/** + * @brief Set ADC Channel 6 PGA Gain. + * @note This is used to select channel 6 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch6pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH6PGA_MSK, Gain<GAINL, ADC_GAINL_CH6PGA_MSK)>>ADC_GAINL_CH6PGA_POSS); +} + +/** + * @brief Set ADC Channel 5 PGA Gain. + * @note This is used to select channel 5 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch5pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH5PGA_MSK, Gain<GAINL, ADC_GAINL_CH5PGA_MSK)>>ADC_GAINL_CH5PGA_POSS); +} + +/** + * @brief Set ADC Channel 4 PGA Gain. + * @note This is used to select channel 4 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch4pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH4PGA_MSK, Gain<GAINL, ADC_GAINL_CH4PGA_MSK)>>ADC_GAINL_CH4PGA_POSS); +} + +/** + * @brief Set ADC Channel 3 PGA Gain. + * @note This is used to select channel 3 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch3pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH3PGA_MSK, Gain<GAINL, ADC_GAINL_CH3PGA_MSK)>>ADC_GAINL_CH3PGA_POSS); +} + +/** + * @brief Set ADC Channel 2 PGA Gain. + * @note This is used to select channel 2 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch2pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH2PGA_MSK, Gain<GAINL, ADC_GAINL_CH2PGA_MSK)>>ADC_GAINL_CH2PGA_POSS); +} + +/** + * @brief Set ADC Channel 1 PGA Gain. + * @note This is used to select channel 1 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch1pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH1PGA_MSK, Gain<GAINL, ADC_GAINL_CH1PGA_MSK)>>ADC_GAINL_CH1PGA_POSS); +} + +/** + * @brief Set ADC Channel 0 PGA Gain. + * @note This is used to select channel 0 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch0pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH0PGA_MSK, Gain<GAINL, ADC_GAINL_CH0PGA_MSK)>>ADC_GAINL_CH0PGA_POSS); +} + +/** + * @brief Set ADC Channels 0~7 PGA Gain. + * @note This is used to select channels 0-7 PGA gain. + * @param ADCx ADC Instance + * @param GainL Register Values for CH0~CH7. + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl(ADC_TypeDef *ADCx, uint32_t GainL) +{ + WRITE_REG(ADCx->GAINL, GainL); +} + +/** + * @brief Get ADC Channels 0~7 PGA Gain. + * @note This is used to read channels 0-7 PGA gain. + * @param ADCx ADC Instance + * @retval GainL Register Values for CH0~CH7. + */ +__STATIC_INLINE uint32_t md_adc_get_gainl(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->GAINL); +} + +/** + * @brief Set ADC Channel 15 PGA Gain. + * @note This is used to select channel 15 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch15pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH15PGA_MSK, Gain<GAINH, ADC_GAINH_CH15PGA_MSK)>>ADC_GAINH_CH15PGA_POSS); +} + +/** + * @brief Set ADC Channel 14 PGA Gain. + * @note This is used to select channel 14 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch14pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH14PGA_MSK, Gain<GAINH, ADC_GAINH_CH14PGA_MSK)>>ADC_GAINH_CH14PGA_POSS); +} + +/** + * @brief Set ADC Channel 13 PGA Gain. + * @note This is used to select channel 13 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch13pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH13PGA_MSK, Gain<GAINH, ADC_GAINH_CH13PGA_MSK)>>ADC_GAINH_CH13PGA_POSS); +} + +/** + * @brief Set ADC Channel 12 PGA Gain. + * @note This is used to select channel 12 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch12pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH12PGA_MSK, Gain<GAINH, ADC_GAINH_CH12PGA_MSK)>>ADC_GAINH_CH12PGA_POSS); +} + +/** + * @brief Set ADC Channel 11 PGA Gain. + * @note This is used to select channel 11 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch11pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH11PGA_MSK, Gain<GAINH, ADC_GAINH_CH11PGA_MSK)>>ADC_GAINH_CH11PGA_POSS); +} + +/** + * @brief Set ADC Channel 10 PGA Gain. + * @note This is used to select channel 10 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch10pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH10PGA_MSK, Gain<GAINH, ADC_GAINH_CH10PGA_MSK)>>ADC_GAINH_CH10PGA_POSS); +} + +/** + * @brief Set ADC Channel 9 PGA Gain. + * @note This is used to select channel 9 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch9pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH9PGA_MSK, Gain<GAINH, ADC_GAINH_CH9PGA_MSK)>>ADC_GAINH_CH9PGA_POSS); +} + +/** + * @brief Set ADC Channel 8 PGA Gain. + * @note This is used to select channel 8 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch8pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH8PGA_MSK, Gain<GAINH, ADC_GAINH_CH8PGA_MSK)>>ADC_GAINH_CH8PGA_POSS); +} + +/** + * @brief Set ADC Channels 8~15 PGA Gain. + * @note This register is used to select channels 8-15 PGA gain. + * @param GainH Register Values for CH8~CH15. + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh(ADC_TypeDef *ADCx, uint32_t GainH) +{ + WRITE_REG(ADCx->GAINH, GainH); +} + +/** + * @brief Get ADC Channels 8~15 PGA Gain. + * @note This register is used to read channels 8-15 PGA gain. + * @param ADCx ADC Instance + * @retval GainH Register Values for CH8~CH15. + */ +__STATIC_INLINE uint32_t md_adc_get_gainh(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->GAINH); +} + +/** + * @brief Refresh ADC FIFOs SS0~SS3. + * @note This register allowed users to reset ADC FIFO when starting a + * new Sample Sequencer. + * @param ADCx ADC Instance + * @param Value if bit (1 or 0) + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ffrst(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_FFRST_MSK); +} + +/** + * @brief Get ADC FIFO Refresh Status. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_frf_ffrst(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->FRF, ADC_FRF_FFRST_MSK)>>ADC_FRF_FFRST_POS); +} + +/** + * @brief Refresh ADC SS3 FIFO. + * @note This register is used to refresh the FIFO of sequencer 3 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss3rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS3RF_MSK); +} + +/** + * @brief Refresh ADC SS32 FIFO. + * @note This register is used to refresh the FIFO of sequencer 2 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss2rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS2RF_MSK); +} + +/** + * @brief Refresh ADC SS1 FIFO. + * @note This register is used to refresh the FIFO of sequencer 1 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss1rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS1RF_MSK); +} + +/** + * @brief Refresh ADC SS0 FIFO. + * @note This register is used to refresh the FIFO of sequencer 0 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss0rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS0RF_MSK); +} + +/** + * @brief Refresh ADC FIFO Register. + * @note This is used to set RFR register. + * @param ADCx ADC Instance + * @param Register Value + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf(ADC_TypeDef *ADCx, uint32_t Value) +{ + WRITE_REG(ADCx->FRF, Value); +} + +/** + * @brief Get ADC FIFO Refresh Register. + * @note This is used to get RFR register. + * @param ADCx ADC Instance + * @retval Register Value + */ +__STATIC_INLINE uint32_t md_adc_get_frf(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->FRF); +} + +/** + * @brief Check if all ADC Sequencer is idle. + * @note Check if SS0~SS3 is idle. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_idle(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_IDLE_MSK) == (ADC_SSEN_IDLE_MSK)); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Enable. + * @note User can set this bit to enable sample sequencer 3 (SS3). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss3en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Disable. + * @note Disable sample sequencer 3 (SS3). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss3en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss3en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK) == (ADC_SSEN_SS3EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Enable. + * @note User can set this bit to enable sample sequencer 2 (SS2). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss2en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Disable. + * @note Disable sample sequencer 2 (SS2). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss2en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 2 (SS2) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss2en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK) == (ADC_SSEN_SS2EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Enable. + * @note User can set this bit to enable sample sequencer 1 (SS1). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss1en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Disable. + * @note Disable sample sequencer 1 (SS1). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss1en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss1en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK) == (ADC_SSEN_SS1EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Enable. + * @note User can set this bit to enable sequencer 0 (SS0). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss0en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK); +} + +/** + * @brief AADC Sample Sequencer 0 (SS0) Disable. + * @note Disable sample sequencer 0 (SS0). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss0en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 0 (SS0) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss0en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK) == (ADC_SSEN_SS0EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Initiate. + * @note Triggers smapling on SS3 if the sequencer is enabled in the ADC_SSEN_SS3EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS3_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Initiate. + * @note Triggers smapling on SS2 if the sequencer is enabled in the ADC_SSEN_SS2EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS2_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Initiate. + * @note Triggers smapling on SS1 if the sequencer is enabled in the ADC_SSEN_SS1EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS1_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Initiate. + * @note Triggers smapling on SS0 if the sequencer is enabled in the ADC_SSEN_SS0EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS0_MSK); +} + +/** + * @brief ADC Timeout Interrupt Enable. + * @note User can set this bit to enable timeout Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_toie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_TOIE_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Interrupt Enable. + * @note User can set this bit to enable sequencer 3 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss3ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS3IE_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Interrupt Enable. + * @note User can set this bit to enable sequencer 2 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss2ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS2IE_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Interrupt Enable. + * @note User can set this bit to enable sequencer 1 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss1ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS1IE_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Interrupt Enable. + * @note User can set this bit to enable sequencer 0 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss0ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS0IE_MSK); +} + +/** + * @brief ADC Timeout Interrupt Disable. + * @note User can set this bit to disable timeout Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_toid(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_TOID_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Interrupt Disable. + * @note User can set this bit to disable sequencer 3 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss3id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS3ID_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Interrupt Disable. + * @note User can set this bit to disable sequencer 2 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss2id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS2ID_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Interrupt Disable. + * @note User can set this bit to disable sequencer 1 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss1id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS1ID_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Interrupt Disable. + * @note User can set this bit to disable sequencer 0 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss0id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS0ID_MSK); +} + +/** + * @brief Check if ADC Timeout Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_toivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_TOIVS_MSK) == (ADC_IVS_TOIVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss3ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS3IVS_MSK) == (ADC_IVS_SS3IVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 2 (SS2) Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss2ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS2IVS_MSK) == (ADC_IVS_SS2IVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss1ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS1IVS_MSK) == (ADC_IVS_SS1IVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 0 (SS0) Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss0ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS0IVS_MSK) == (ADC_IVS_SS0IVS_MSK)); +} + +/** + * @brief Check Timeout Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_torif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_TORIF_MSK) == (ADC_RIF_TORIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 3 (SS3) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss3rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS3RIF_MSK) == (ADC_RIF_SS3RIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 2 (SS2) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss2rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS2RIF_MSK) == (ADC_RIF_SS2RIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 1 (SS1) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss1rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS1RIF_MSK) == (ADC_RIF_SS1RIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 0 (SS0) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss0rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS0RIF_MSK) == (ADC_RIF_SS0RIF_MSK)); +} + +/** + * @brief Check Timeout Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_torif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_TOIFM_MSK) == (ADC_IFM_TOIFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 3 (SS3) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss3rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS3IFM_MSK) == (ADC_IFM_SS3IFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 2 (SS2) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss2rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS2IFM_MSK) == (ADC_IFM_SS2IFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 1 (SS1) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss1rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS1IFM_MSK) == (ADC_IFM_SS1IFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 0 (SS0) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss0rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS0IFM_MSK) == (ADC_IFM_SS0IFM_MSK)); +} + +/** + * @brief ADC Timeout Interrupt Clear. + * @note User can set this bit to clear timeout interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_toicr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_TOICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Interrupt Clear. + * @note User can set this bit to clear SS3 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss3icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS3ICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Interrupt Clear. + * @note User can set this bit to clear SS2 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss2icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS2ICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Interrupt Clear. + * @note User can set this bit to clear SS1 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss1icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS1ICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Interrupt Clear. + * @note User can set this bit to clear SS0 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss0icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS0ICR_MSK); +} + +/** + * @brief ADC SS3 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S3, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss3dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK); +} + +/** + * @brief ADC SS3 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss3dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS3 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss3dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK) == (ADC_DMA_SS3_DMAEN_MSK)); +} + +/** + * @brief ADC SS2 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S2, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss2dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK); +} + +/** + * @brief ADC SS2 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss2dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS2 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss2dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK) == (ADC_DMA_SS2_DMAEN_MSK)); +} + +/** + * @brief ADC SS1 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S1, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss1dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK); +} + +/** + * @brief ADC SS1 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss1dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS1 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss1dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK) == (ADC_DMA_SS1_DMAEN_MSK)); +} + +/** + * @brief ADC SS0 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S0, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss0dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK); +} + +/** + * @brief ADC SS0 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss0dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS3 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss0dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK) == (ADC_DMA_SS0_DMAEN_MSK)); +} + +/** + * @brief Set SS0 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 0. + * @param ADCx ADC Instance. + * @param Sample sequencer trigger sources. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_SEL_MSK, TrigSource<SS0_CON, ADC_SS0_CON_SEL_MSK)>>ADC_SS0_CON_SEL_POSS); +} + +/** + * @brief Set ADC Sample Sequencer 0 (SS0) Trigger Type select. + * @note User can set this bit to select the type of trigger. + * @param Sample sequencer trigger types. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_TYP_MSK, TrigType<SS0_CON, ADC_SS0_CON_TYP_MSK)>>ADC_SS0_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 0 (SS0) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS0. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param Sample sequencer trigger priorities. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS0_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS0_CON_PRI_SECOND + * @arg @ref MD_ADC_SS0_CON_PRI_THIRD + * @arg @ref MD_ADC_SS0_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_con_pri(ADC_TypeDef *ADCx, uint32_t priority) +{ + MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_PRI_MSK, priority<SS0_CON, ADC_SS0_CON_PRI_MSK)>>ADC_SS0_CON_PRI_POSS); +} + +/** + * @brief Enable One Shot Trigger Mode. + * @note When set HIGH, each trigger will only sample once and use one slot in FIFO. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_enable_ss0_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS0_CON, ADC_SS0_CON_ONE_MSK); +} + +/** + * @brief Disable One Shot Trigger Mode. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss0_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS0_CON, ADC_SS0_CON_ONE_MSK); +} + +/** + * @brief Set 8th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux7(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX7_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX7_MSK)>>ADC_SS0_MUX0_MUX7_POSS); +} + +/** + * @brief Set 7th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux6(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX6_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX6_MSK)>>ADC_SS0_MUX0_MUX6_POSS); +} + +/** + * @brief Set 6th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux5(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX5_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX5_MSK)>>ADC_SS0_MUX0_MUX5_POSS); +} + +/** + * @brief Set 5th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux4(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX4_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX4_MSK)>>ADC_SS0_MUX0_MUX4_POSS); +} + +/** + * @brief Set 4th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX3_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX3_MSK)>>ADC_SS0_MUX0_MUX3_POSS); +} + +/** + * @brief Set 3rd Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX2_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX2_MSK)>>ADC_SS0_MUX0_MUX2_POSS); +} + +/** + * @brief Set 2nd Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX1_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX1_MSK)>>ADC_SS0_MUX0_MUX1_POSS); +} + +/** + * @brief Set 1st Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX0_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX0_MSK)>>ADC_SS0_MUX0_MUX0_POSS); +} + +/** + * @brief Set ADC channels MUX 0~7. + * @note Set ADC SS0_MUX0 register. + * @note Mapping ADINx to ADC channels 0~7. + + * @param ADC Channel + * @param MUX Register + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS0_MUX0, RegValue); +} + +/** + * @brief Get ADC channels MUX 0~7. + * @note Get ADC SS0_MUX0 register. + * @param ADCx ADC Instance + * @retval SS0_MUX0 Register Value + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_mux0(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS0_MUX0); +} + +/** + * @brief Set 16th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux15(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX15_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX15_MSK)>>ADC_SS0_MUX1_MUX15_POSS); +} + +/** + * @brief Set 15th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux14(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX14_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX14_MSK)>>ADC_SS0_MUX1_MUX14_POSS); +} + +/** + * @brief Set 14th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux13(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX13_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX13_MSK)>>ADC_SS0_MUX1_MUX13_POSS); +} + +/** + * @brief Set 13th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux12(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX12_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX12_MSK)>>ADC_SS0_MUX1_MUX12_POSS); +} + +/** + * @brief Set 12th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux11(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX11_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX11_MSK)>>ADC_SS0_MUX1_MUX11_POSS); +} + +/** + * @brief Set 11th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux10(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX10_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX10_MSK)>>ADC_SS0_MUX1_MUX10_POSS); +} + +/** + * @brief Set 10th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux9(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX9_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX9_MSK)>>ADC_SS0_MUX1_MUX9_POSS); +} + +/** + * @brief Set 9th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux8(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX8_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX8_MSK)>>ADC_SS0_MUX1_MUX8_POSS); +} + +/** + * @brief Set ADC channels MUX 8~15. + * @note Set SS0_MUX1 register for channels 8~15. + * @param ADCx ADC Instance. + * @param SS0 MUX1 Register. + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_mux1(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS0_MUX1, RegValue); +} + +/** + * @brief Get ADC channels MUX 8~15. + * @note Get SS0_MUX1 register for channels 8~15. + * @param ADCx ADC Instance. + * @retval SS0 MUX1 Register. + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_mux1(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS0_MUX1); +} + +/** + * @brief 16th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie15(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK); +} + +/** + * @brief 16th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie15(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK); +} + +/** + * @brief Check if 16th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie15(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK) == (ADC_SS0_END_IE15_MSK)); +} + +/** + * @brief 15th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie14(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK); +} + +/** + * @brief 15th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie14(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK); +} + +/** + * @brief Check if 15th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie14(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK) == (ADC_SS0_END_IE14_MSK)); +} + +/** + * @brief 14th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie13(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK); +} + +/** + * @brief 14th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie13(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK); +} + +/** + * @brief Check if 14th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie13(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK) == (ADC_SS0_END_IE13_MSK)); +} + +/** + * @brief 13th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie12(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK); +} + +/** + * @brief 13th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie12(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK); +} + +/** + * @brief Check if 13th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie12(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK) == (ADC_SS0_END_IE12_MSK)); +} + +/** + * @brief 12th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie11(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK); +} + +/** + * @brief 12th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie11(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK); +} + +/** + * @brief Check 12th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie11(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK) == (ADC_SS0_END_IE11_MSK)); +} + +/** + * @brief 11th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie10(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK); +} + +/** + * @brief 11th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie10(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK); +} + +/** + * @brief Check if 11th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie10(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK) == (ADC_SS0_END_IE10_MSK)); +} + +/** + * @brief 10th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie9(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK); +} + +/** + * @brief 10th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie9(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK); +} + +/** + * @brief Check if 10th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie9(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK) == (ADC_SS0_END_IE9_MSK)); +} + +/** + * @brief 9th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie8(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK); +} + +/** + * @brief 9th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie8(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK); +} + +/** + * @brief Check if 9th Sample Interrupt is Enable. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie8(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK) == (ADC_SS0_END_IE8_MSK)); +} + +/** + * @brief 8th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie7(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie7(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK); +} + +/** + * @brief Check if 8th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie7(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK) == (ADC_SS0_END_IE7_MSK)); +} + +/** + * @brief 7th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie6(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK); +} + +/** + * @brief 7th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie6(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK); +} + +/** + * @brief Check if 7th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie6(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK) == (ADC_SS0_END_IE6_MSK)); +} + + +/** + * @brief 6th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie5(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK); +} + +/** + * @brief 6th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie5(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK); +} + +/** + * @brief Check if 6th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie5(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK) == (ADC_SS0_END_IE5_MSK)); +} + +/** + * @brief 5th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie4(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK); +} + +/** + * @brief 5th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie4(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK); +} + +/** + * @brief Check if 5th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie4(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK) == (ADC_SS0_END_IE4_MSK)); +} + +/** + * @brief 4th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK); +} + +/** + * @brief 4th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK); +} + +/** + * @brief Check if 4th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK) == (ADC_SS0_END_IE3_MSK)); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK); +} + +/** + * @brief 3rd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK); +} + +/** + * @brief Check if 3rd Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK) == (ADC_SS0_END_IE2_MSK)); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK); +} + +/** + * @brief 2nd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK); +} + +/** + * @brief Check if 2nd Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK) == (ADC_SS0_END_IE1_MSK)); +} + +/** + * @brief 1st Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK); +} + +/** + * @brief 1st Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK); +} + +/** + * @brief Check if 1st Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK) == (ADC_SS0_END_IE0_MSK)); +} + +/** + * @brief Set ADC SS0 sample counts. + * @note User can set this register to select how many times will ADC samples data. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x0F. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss0_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS0_END, ADC_SS0_END_END_MSK, EndValue<SS0_END, ADC_SS0_END_END_MSK)>>ADC_SS0_END_END_POSS); +} + +/** + * @brief Set ADC Sample Sequence 0 End Control Register. + * @note Set ADC_SS0_END register + * @param ADCx ADC Instance + * @param ADC_SS0_END Register Value + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS0_END, ADC_SS0_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC Sample Sequence 0 End Control Register. + * @param ADCx ADC Instance + * @retval ADC_SS0_END Register Value + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS0_END); +} + +/** + * @brief Set ADC Sample Sequencer 0 (SS0) FIFO Overflow status + * @note When the FIFO is full and a write was requested. + * When an overflow is detected, the most recent write is dropped. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 0 (SS0) FIFO Overflow status + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_OV_MSK)>>ADC_SS0_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT OV is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_OV_MSK) == (ADC_SS0_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS0 FSTAT FULL + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_FULL_MSK)>>ADC_SS0_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT FULL is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_FULL_MSK) == (ADC_SS0_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC SS0 FSTAT UV. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss0_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC SS0 FSTAT UV + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_UV_MSK)>>ADC_SS0_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT UV is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_UV_MSK) == (ADC_SS0_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS0 FSTAT EMPTY + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_EMPTY_MSK)>>ADC_SS0_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT EMPTY is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_EMPTY_MSK) == (ADC_SS0_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS0 FSTAT HPTR + * @note The field contains the current head pointer index, which is the + * next entry to be written to FIFO. + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_HPTR_MSK)>>ADC_SS0_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS0 FSTAT TPTR + * @note The field contains the current tail pointer index, which is the + * next entry to be read from FIFO. + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_TPTR_MSK)>>ADC_SS0_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 0(SS0) result FIFO data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance + * @retval ADC Sampled Data + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS0_DATA)); +} + +/** + * @brief Set SS1 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 1. + * @param ADCx ADC Instance + * @param Sample sequencer trigger sources. + * This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS1_CON, ADC_SS1_CON_SEL_MSK, TrigSource<SS1_CON, ADC_SS1_CON_SEL_MSK)>>ADC_SS1_CON_SEL_POSS); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Trigger Type select. + * @note User can set this bit to select the type of trigger. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS1_CON, ADC_SS1_CON_TYP_MSK, TrigType<SS1_CON, ADC_SS1_CON_TYP_MSK)>>ADC_SS1_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 1 (SS1) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS1. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS0_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS0_CON_PRI_SECOND + * @arg @ref MD_ADC_SS0_CON_PRI_THIRD + * @arg @ref MD_ADC_SS0_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_con_pri(ADC_TypeDef *adcx, uint32_t priority) +{ + MODIFY_REG(adcx->SS1_CON, ADC_SS1_CON_PRI_MSK, priority<SS1_CON, ADC_SS1_CON_PRI_MSK)>>ADC_SS1_CON_PRI_POSS); +} + +/** + * @brief One Shot Trigger Mode enable. + * @note When set HIGH, each trigger will only sample once and use one + * slot in FIFO. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_enable_ss1_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS1_CON, ADC_SS1_CON_ONE_MSK); +} + +/** + * @brief One Shot Trigger Mode disable. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss1_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS1_CON, ADC_SS1_CON_ONE_MSK); +} + +/** + * @brief Set ADC SS1 MUX7 ADINx Input Pin. + * @note 8th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux7(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX7_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX7_MSK)>>ADC_SS1_MUX0_MUX7_POSS); +} + +/** + * @brief Set ADC SS1 MUX6 Input ADIN Pin. + * @note 7th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux6(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX6_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX6_MSK)>>ADC_SS1_MUX0_MUX6_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX5 Input ADIN Pin. + * @note 6th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux5(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX5_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX5_MSK)>>ADC_SS1_MUX0_MUX5_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX4 Input ADIN Pin. + * @note 5th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux4(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX4_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX4_MSK)>>ADC_SS1_MUX0_MUX4_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX3 Input ADIN Pin. + * @note 4th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX3_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX3_MSK)>>ADC_SS1_MUX0_MUX3_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX2 Input ADIN Pin. + * @note 3rd Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX2_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX2_MSK)>>ADC_SS1_MUX0_MUX2_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX1 Input ADIN Pin. + * @note 2nd Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX1_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX1_MSK)>>ADC_SS1_MUX0_MUX1_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX0 Input ADIN Pin. + * @note 1st Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX0_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX0_MSK)>>ADC_SS1_MUX0_MUX0_POSS); +} + +/** + * @brief Set ADC_SS1_MUX0 register. + * @note Set ADC_SS1_MUX0 channels 0~7. + * @param ADCx ADC Instance. + * @param ADC_SS1_MUX0 register value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS1_MUX0, RegValue); +} + +/** + * @brief Get ADC_SS1_MUX0 register. + * @param ADCx ADC Instance. + * @retval ADC_SS1_MUX0 register value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_mux0(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS1_MUX0); +} + +/** + * @brief 8th Sample Interrupt Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie7(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie7(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK); +} + +/** + * @brief Check if 8th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie7(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK) == (ADC_SS1_END_IE7_MSK)); +} + +/** + * @brief 7th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie6(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK); +} + +/** + * @brief 7th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie6(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK); +} + +/** + * @brief Check if 7th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie6(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK) == (ADC_SS1_END_IE6_MSK)); +} + + +/** + * @brief 6th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss10_end_ie5(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie5(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK); +} + +/** + * @brief Check if 6th Sample Interrupt is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie5(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK) == (ADC_SS1_END_IE5_MSK)); +} + +/** + * @brief 5th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie4(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK); +} + +/** + * @brief 5th Sample Interrupt Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie4(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK); +} + +/** + * @brief Check if 5th Sample Interrupt is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie4(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK) == (ADC_SS1_END_IE4_MSK)); +} + +/** + * @brief 4th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK); +} + +/** + * @brief Check if 4th Sample Interrupt is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK) == (ADC_SS1_END_IE3_MSK)); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK); +} + +/** + * @brief Check if 3rd Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK) == (ADC_SS1_END_IE2_MSK)); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK); +} + +/** + * @brief 2nd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK); +} + +/** + * @brief Check if 2nd Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK) == (ADC_SS1_END_IE1_MSK)); +} + +/** + * @brief 1st Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK); +} + +/** + * @brief 1st Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK); +} + +/** + * @brief Check if 1st Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK) == (ADC_SS1_END_IE0_MSK)); +} + +/** + * @brief Set end sample counts. + * @note User can set this register to select how many times will ADC + * samples data. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x07. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS1_END, ADC_SS1_END_END_MSK, EndValue<SS1_END, ADC_SS1_END_END_MSK)>>ADC_SS1_END_END_POSS); +} + +/** + * @brief Set ADC_SS1_END Control Register + * @param ADCx ADC Instance. + * @param ADC_SS1_END register value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS1_END, ADC_SS1_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC_SS1_End Control Register + * @param ADCx ADC Instance. + * @retval ADC_SS1_END register value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS1_END); +} + +/** + * @brief Set ADC Sample Sequencer 1 (SS1) FIFO Overflow status. + * @note When the FIFO is full and a write was requested, the + * most recent write is dropped. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 1 (SS1) FIFO Overflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_OV_MSK)>>ADC_SS1_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) FIFO Overflow is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_OV_MSK) == (ADC_SS1_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS1 FIFO Full status + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_FULL_MSK)>>ADC_SS1_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS1 FIFO Full is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_FULL_MSK) == (ADC_SS1_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC Sample Sequencer 1 (SS1) FIFO Underflow status. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 1 (SS1) FIFO Underflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_UV_MSK)>>ADC_SS1_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) FIFO Underflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_UV_MSK) == (ADC_SS1_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS1 FIFO Empty status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_EMPTY_MSK)>>ADC_SS1_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS1 FIFO Empty is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_EMPTY_MSK) == (ADC_SS1_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS1 FIFO Head Pointer. + * @note The field contains the current head pointer index, which is the + * next entry to be written to FIFO. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x0F + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_HPTR_MSK)>>ADC_SS1_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS1 FIFO Tail Pointer. + * @note The field contains the current tail pointer index, which is the + * next entry to be read from FIFO. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x0F + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_TPTR_MSK)>>ADC_SS1_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 1(SS1) Conversion Result Data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance. + * @retval ADC Sampled Data. + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS1_DATA)); +} + +/** + * @brief Set ADC SS2 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 1. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS2_CON, ADC_SS2_CON_SEL_MSK, TrigSource<SS2_CON, ADC_SS2_CON_SEL_MSK)>>ADC_SS2_CON_SEL_POSS); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Trigger Type select. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS2_CON, ADC_SS2_CON_TYP_MSK, TrigType<SS2_CON, ADC_SS2_CON_TYP_MSK)>>ADC_SS2_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 2(SS2) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS2. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS_CON_PRI_SECOND + * @arg @ref MD_ADC_SS_CON_PRI_THIRD + * @arg @ref MD_ADC_SS_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_con_pri(ADC_TypeDef *adcx, uint32_t priority) +{ + MODIFY_REG(adcx->SS2_CON, ADC_SS2_CON_PRI_MSK, priority<SS2_CON, ADC_SS2_CON_PRI_MSK)>>ADC_SS2_CON_PRI_POSS); +} + +/** + * @brief Enable One Shot Trigger Mode. + * @note When set HIGH, each trigger will only sample once and use one + * slot in FIFO. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS2_CON, ADC_SS2_CON_ONE_MSK); +} + +/** + * @brief Disable One Shot Trigger Mode. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS2_CON, ADC_SS2_CON_ONE_MSK); +} + +/** + * @brief 4th Sample Input Select.. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX3_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX3_MSK)>>ADC_SS2_MUX0_MUX3_POSS); +} + +/** + * @brief 3rd Sample Input Select. + * @param ADCx ADC Instance. + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX2_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX2_MSK)>>ADC_SS2_MUX0_MUX2_POSS); +} + +/** + * @brief 2nd Sample Input Select. + * @param ADCx ADC Instance. + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX1_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX1_MSK)>>ADC_SS2_MUX0_MUX1_POSS); +} + +/** + * @brief 1st Sample Input Select. + * @param ADCx ADC Instance. + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX0_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX0_MSK)>>ADC_SS2_MUX0_MUX0_POSS); +} + +/** + * @brief Set ADC_SS2_MUX0 register value. + * @param ADCx ADC Instance. + * @param ADC_SS2_MUX0 Register + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS2_MUX0, RegValue); +} + +/** + * @brief Get ADC_SS2_MUX0 register value. + * @param ADCx ADC Instance. + * @retval ADC_SS2_MUX0 Register + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_mux0(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS2_MUX0); +} + +/** + * @brief 4th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK); +} + +/** + * @brief 4th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK); +} + +/** + * @brief Check if 4th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK) == (ADC_SS2_END_IE3_MSK)); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK); +} + +/** + * @brief 3rd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK); +} + +/** + * @brief Check if 3rd Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK) == (ADC_SS2_END_IE2_MSK)); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS2_END_IE1_MSK); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE1_MSK); +} + +/** + * @brief Check if 2nd Sample Interrupt Enable is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS2_END_IE1_MSK) == (ADC_SS2_END_IE1_MSK)); +} + +/** + * @brief 1st Sample Interrupt Enable + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK); +} + +/** + * @brief 4th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK); +} + +/** + * @brief Check if 1st Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK) == (ADC_SS2_END_IE0_MSK)); +} + +/** + * @brief Set ADC SS2 END sample. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x03 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS2_END, ADC_SS2_END_END_MSK, EndValue<SS2_END, ADC_SS2_END_END_MSK)>>ADC_SS2_END_END_POSS); +} + +/** + * @brief Set ADC_SS2_End Control Register. + * @param ADCx ADC Instance. + * @param ADC_SS2_End Register Value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss2_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS2_END, ADC_SS2_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC_SS2_End Control Register. + * @param ADCx ADC Instance. + * @retval ADC_SS2_End Register Value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS2_END); +} + +/** + * @brief Set ADC Sample Sequencer 2(SS2) FIFO Overflow status. + * @note When the FIFO is full and a write was requested, the + * most recent write is dropped. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss2_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 2(SS2) FIFO Overflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_OV_MSK)>>ADC_SS2_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 2(SS2) FIFO Overflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_OV_MSK) == (ADC_SS2_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS2 FIFO Full status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_FULL_MSK)>>ADC_SS2_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS2 FIFO Full is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_FULL_MSK) == (ADC_SS2_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC Sample Sequencer 2(SS2) FIFO Underflow status. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss2_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 2(SS2) FIFO Underflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_UV_MSK)>>ADC_SS2_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 2(SS2) FIFO Underflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_UV_MSK) == (ADC_SS2_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS2 FIFO Empty status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_EMPTY_MSK)>>ADC_SS2_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS2 FIFO Empty is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_EMPTY_MSK) == (ADC_SS2_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS2 FIFO Head Pointer. + * @param ADCx ADC Instance. + * @retval Return value between Min_Data=0x00 and Max_Data=0x0F. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_HPTR_MSK)>>ADC_SS2_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS2 FSTAT TPTR + * @param ADCx ADC Instance + * @retval Return value between Min_Data=0x00 and Max_Data=0x0F. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_TPTR_MSK)>>ADC_SS2_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 2(SS2) Conversion Result Data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance. + * @retval ADC Sampled Data. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS2_DATA)); +} + +/** + * @brief Set SS3 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 3. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss3_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS3_CON, ADC_SS3_CON_SEL_MSK, TrigSource<SS3_CON, ADC_SS3_CON_SEL_MSK)>>ADC_SS3_CON_SEL_POSS); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Trigger Type select. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss3_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS3_CON, ADC_SS3_CON_TYP_MSK, TrigType<SS3_CON, ADC_SS3_CON_TYP_MSK)>>ADC_SS3_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 3(SS3) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS2. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS_CON_PRI_SECOND + * @arg @ref MD_ADC_SS_CON_PRI_THIRD + * @arg @ref MD_ADC_SS_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss3_con_pri(ADC_TypeDef *adcx, uint32_t priority) +{ + MODIFY_REG(adcx->SS3_CON, ADC_SS3_CON_PRI_MSK, priority<SS3_CON, ADC_SS3_CON_PRI_MSK)>>ADC_SS3_CON_PRI_POSS); +} + +/** + * @brief Enable ADC sample sequencer 3(SS3) one shot mode. + * @note When set HIGH, each trigger will only sample once and use one + * slot in FIFO. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss3_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS3_CON, ADC_SS3_CON_ONE_MSK); +} + +/** + * @brief Disable ADC sample sequencer 3(SS3) one shot mode. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss3_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS3_CON, ADC_SS3_CON_ONE_MSK); +} + +/** + * @brief Enable ADC SS3 1th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss3_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK); +} + +/** + * @brief Disable ADC SS3 1th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss3_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK); +} + +/** + * @brief Check if ADC SS3 1th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss3_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK) == (ADC_SS3_END_IE0_MSK)); +} + +/** + * @brief Set ADC SS3 END sample. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x01. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS3_END, ADC_SS3_END_END_MSK, EndValue<SS3_END, ADC_SS3_END_END_MSK)>>ADC_SS3_END_END_POS); +} + +/** + * @brief Set ADC_SS3_End Control Register. + * @param ADCx ADC Instance. + * @param ADC_SS3_END Register Value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS2_END, ADC_SS3_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC_SS3_End Control Register + * @param ADCx ADC Instance. + * @retval ADC_SS3_End Register Value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS3_END); +} + +/** + * @brief Set ADC Sample Sequencer 3 (SS3) FIFO Overflow status. + * @note When the FIFO is full and a write was requested, the + * most recent write is dropped. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS3_END, ADC_SS3_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 3 (SS3) FIFO Overflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_OV_MSK)>>ADC_SS3_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) FIFO Overflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_OV_MSK) == (ADC_SS3_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS3 FIFO Full status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_FULL_MSK)>>ADC_SS3_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS3 FIFO Full status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_FULL_MSK) == (ADC_SS3_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC Sample Sequencer 3 (SS3) FIFO Underflow status. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS3_END, ADC_SS3_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 3 (SS3) FIFO Underflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_UV_MSK)>>ADC_SS3_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) FIFO Underflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_UV_MSK) == (ADC_SS3_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS3 FIFO Empty. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_EMPTY_MSK)>>ADC_SS3_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS3 FIFO Empty is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_EMPTY_MSK) == (ADC_SS3_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS3 FIFO Head Pointer. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x01. + */ +__STATIC_INLINE uint32_t md_adc_get_ss23_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_HPTR_MSK)>>ADC_SS3_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS3 FIFO Tail Pointer. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x01. + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_TPTR_MSK)>>ADC_SS3_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 3(SS3) Conversion Result Data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance. + * @retval ADC Sampled Data. + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS3_DATA)); +} + +/** @defgroup MD_ADC_PM_WRITE_READ Common Write and read registers Macros + * @} + */ +#endif + +void md_adc_init(ADC_TypeDef *ADCx, md_adc_inittypedef *ADC_InitStruct,uint8_t *); +void md_adc_calibration_data(double, double ,double * ,double *); +void md_adc_get_data(uint8_t, double, double, uint16_t *); +/** + * @} MD_ADC_Public_Macros + */ + +/** @} ADC + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..e4e16693d54de70434bfb43f83a617e45e2195b6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h @@ -0,0 +1,941 @@ +/** + ****************************************************************************** + * @file md_aes.h + * @brief M601 AES Head File. + * + * @version V0.01 + * @date 28/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_AES_H__ +#define __MD_AES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (AES) + +/** @defgroup AES AES + * @brief AES micro driver + * @{ + */ + +/* Private Types --------------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Public Types ---------------------------------------------------------------*/ +/** @defgroup MD_AES_INIT AES public init structure + * @brief + * @{ + */ +typedef struct +{ + volatile uint8_t aes_con_bl; + volatile uint8_t aes_con_mode; + volatile uint32_t aes_key[4]; + volatile uint32_t aes_iv[4]; + volatile uint32_t aes_din[4]; + volatile uint32_t aes_dout[4]; +} md_aes_init_typedef; +/** + * @} MD_AES_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_AES_Public_Constants AES Public Constants + * @brief + * @{ + */ + +/** @defgroup MD_AES_CON_registers AES Control Registers + * @brief + * @{ + */ +#define MD_AES_CON_READY_BUSY 0 /*!< This allow user to read AES Encryption/Decryption Ready Status. */ +#define MD_AES_CON_READY_READY 1 /*!< This allow user to read AES Encryption/Decryption Ready Status. */ +#define MD_AES_CON_OT_DMA_ST_PASS 1 /*!< This allow user to read AES DMA Output Status. */ +#define MD_AES_CON_OT_DMA_ST_FAIL 0 /*!< This allow user to read AES DMA Output Status. */ +#define MD_AES_CON_IT_DMA_ST_PASS 1 /*!< This allow user to read AES DMA Input Status. */ +#define MD_AES_CON_IT_DMA_ST_FAIL 0 /*!< This allow user to read AES DMA Input Status. */ +#define MD_AES_CON_OT_DEPTH_0 0 /*!< This allow user to read AES DIO data depth status (X=0). */ +#define MD_AES_CON_OT_DEPTH_1 1 /*!< This allow user to read AES DIO data depth status (X=1). */ +#define MD_AES_CON_OT_DEPTH_2 2 /*!< This allow user to read AES DIO data depth status (X=2). */ +#define MD_AES_CON_OT_DEPTH_3 3 /*!< This allow user to read AES DIO data depth status (X=3). */ +#define MD_AES_CON_IT_DEPTH_0 0 /*!< This allow user to read AES DIO data depth status (X=0). */ +#define MD_AES_CON_IT_DEPTH_1 1 /*!< This allow user to read AES DIO data depth status (X=1). */ +#define MD_AES_CON_IT_DEPTH_2 2 /*!< This allow user to read AES DIO data depth status (X=2). */ +#define MD_AES_CON_IT_DEPTH_3 3 /*!< This allow user to read AES DIO data depth status (X=3). */ +#define MD_AES_CON_RE_INIT_SET 1 /*!< This allow user to set AES Re-initial. */ +#define MD_AES_CON_RE_INIT_UNSET 0 /*!< This allow user to set AES Re-initial. */ +#define MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) /*!< This allow user to set AES DMA Function Enable. 0:AES input DMA disable */ +#define MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) /*!< This allow user to set AES DMA Function Enable. 1:AES input DMA enable */ +#define MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1 /*!< This allow user to set AES DMA Function Enable. 0:AES output DMA disable */ +#define MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) /*!< This allow user to set AES DMA Function Enable. 1:AES outut DMA enable */ +#define MD_AES_CON_BL_CBC 0 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 000:CBC */ +#define MD_AES_CON_BL_CFB 1 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 001:CFB */ +#define MD_AES_CON_BL_OFB 2 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 010:OFB */ +#define MD_AES_CON_BL_CTR 3 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 011:CTR */ +#define MD_AES_CON_BL_ECB 4 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 100:ECB */ +#define MD_AES_CON_BL_GCM 5 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 101:GCM */ +#define MD_AES_CON_REV_NORMAL 0 /*!< This allow user to set AES Input Reverse. 0:Normal Mode */ +#define MD_AES_CON_REV_REVERSE 1 /*!< This allow user to set AES Input Reverse. 1:KEY, IV, DI, DO Byte Reverse Mode */ +#define MD_AES_CON_MODE_ENCRYPT 0 /*!< This allow user to set AES Mode Control. 0:Encryption Mode */ +#define MD_AES_CON_MODE_DECRYPT 1 /*!< This allow user to set AES Mode Control. 1:Decryption Mode */ +#define MD_AES_CON_START 1 /*!< This allow user to set AES Start. AES function will start after this bit is set to 1. */ +/** + * @} MD_AES_CON_registers + */ + +/** @defgroup MD_AES_IER_registers AES Interrupt Enable Registers + * @brief + * @{ + */ +#define MD_AES_IER_DECIE 1 /*!< This allow user to set AES Decryption Interrupt Enable. */ +#define MD_AES_IER_ENCIE 1 /*!< This allow user to set AES Encryption Interrupt Enable. */ +/** + * @} MD_AES_IER_registers + */ + +/** @defgroup MD_AES_IDR_registers AES Interrupt Disable Registers + * @brief + * @{ + */ +#define MD_AES_IDR_DECID 1 /*!< This allow user to set AES Decryption Interrupt Disable. */ +#define MD_AES_IDR_ENCID 1 /*!< This allow user to set AES Encryption Interrupt Disable. */ +/** + * @} MD_AES_IDR_registers + */ + +/** @defgroup MD_AES_IVS_registers AES Interrupt Valid Status Registers + * @brief + * @{ + */ +#define MD_AES_IVS_DECIVS_DISABLE 0 /*!< This allow user to set AES Decryption Interrupt Valid Status. 0:AES Decryption interrupt is disabled. */ +#define MD_AES_IVS_DECIVS_ENABLE 1 /*!< This allow user to set AES Decryption Interrupt Valid Status. 1:AES Decryption interrupt is enabled. */ +#define MD_AES_IVS_ENCIVS_DISABLE 0 /*!< This allow user to set AES Encryption Interrupt Valid Status. 0:AES Encryption interrupt is disabled. */ +#define MD_AES_IVS_ENCIVS_ENABLE 1 /*!< This allow user to set AES Encryption Interrupt Valid Status. 1:AES Encryption interrupt is enabled. */ +/** + * @} MD_AES_IVS_registers + */ + +/** @defgroup MD_AES_RIF_registers AES Raw Interrupt Flag Registers + * @brief + * @{ + */ +#define MD_AES_RIF_DECRIF_NO_INTERRUPT 0 /*!< This allow user to set AES Decryption Raw Interrupt Flag Status. 0: No interrupt. */ +#define MD_AES_RIF_DECRIF_INTERRUPT 1 /*!< This allow user to set AES Decryption Raw Interrupt Flag Status. 1: AES Decryption interrupt is asserting. */ +#define MD_AES_RIF_ENCRIF_NO_INTERRUPT 0 /*!< This allow user to set AES Encryption Raw Interrupt Flag Status. 0: No interrupt. */ +#define MD_AES_RIF_ENCRIF_INTERRUPT 1 /*!< This allow user to set AES Encryption Raw Interrupt Flag Status. 1: AES Encryption interrupt is asserting. */ +/** + * @} MD_AES_RIF_registers + */ + +/** @defgroup MD_AES_IFM_registers AES Interrupt Flag Mask Registers + * @brief + * @{ + */ +#define MD_AES_IFM_DECRIF_MASK 0 /*!< This allow user to set AES Decryption Interrupt Flag Masked Status. 0: No interrupt or the interrupt has been masked. */ +#define MD_AES_IFM_DECRIF_SIGNAL 1 /*!< This allow user to set AES Decryption Interrupt Flag Masked Status. 1: AES Decryption interrupt has been signalled. */ +#define MD_AES_IFM_ENCRIF_MASK 0 /*!< This allow user to set AES Encryption Interrupt Flag Masked Status. 0: No interrupt or the interrupt has been masked. */ +#define MD_AES_IFM_ENCRIF_SIGNAL 1 /*!< This allow user to set AES Encryption Interrupt Flag Masked Status. 1: AES Encryption interrupt has been signalled. */ +/** + * @} MD_AES_IFM_registers + */ + +/** @defgroup MD_AES_ICR_registers AES Interrupt Clear Registers + * @brief + * @{ + */ +#define MD_AES_ICR_DECICR 1 /*!< This allow user to set AES Decryption Interrupt Clear. User can set this bit to clear AES Decryption interrupt status. */ +#define MD_AES_ICR_ENCICR 1 /*!< This allow user to set AES Decryption Interrupt Clear. User can set this bit to clear AES Encryption interrupt status. */ +/** + * @} MD_AES_ICR_registers + */ + +/** + * @} MD_AES_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_AES_Public_Macros AES Public Macros + * @brief + * @{ + */ + +/** + * @brief AES Control Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY 0 + * @arg @ref MD_AES_CON_READY_READY 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_OT_DEPTH_0 0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 3 + * @arg @ref MD_AES_CON_IT_DEPTH_0 0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 3 + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + * @arg @ref MD_AES_CON_START 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->CON, value); +} + +/** + * @brief AES Control Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY 0 + * @arg @ref MD_AES_CON_READY_READY 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_OT_DEPTH_0 0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 3 + * @arg @ref MD_AES_CON_IT_DEPTH_0 0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 3 + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + * @arg @ref MD_AES_CON_START 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con(AES_TypeDef *aes) +{ + return (READ_REG(aes->CON)); +} + +/** + * @brief AES Encryption / Decryption Ready Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY 0 + * @arg @ref MD_AES_CON_READY_READY 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_ready(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_READY_MSK) >> AES_CON_READY_POS) & 0x1); +} + +/** + * @brief AES DMA Output Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 0 + * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_ot_dma_st(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_OT_DMA_ST_MSK) >> AES_CON_OT_DMA_ST_POS) & 0x1); +} + +/** + * @brief AES DMA Intput Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 0 + * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_it_dma_st(AES_TypeDef *aes, uint32_t value) +{ + return ((READ_BIT(aes->CON, AES_CON_IT_DMA_ST_MSK) >> AES_CON_IT_DMA_ST_POS) & 0x1); +} + +/** + * @brief AES DIO data depth status (X=0,1,2,3) + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_OT_DEPTH_0 0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 3 + */ +__STATIC_INLINE uint32_t md_aes_get_con_ot_depth(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_OT_DEPTH_MSK) >> AES_CON_OT_DEPTH_POSS) & 0x3); +} + +/** + * @brief AES DIO data depth status (X=0,1,2,3) + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_IT_DEPTH_0 0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 3 + */ +__STATIC_INLINE uint32_t md_aes_get_con_it_depth(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_IT_DEPTH_MSK) >> AES_CON_IT_DEPTH_POSS) & 0x3); +} + +/** + * @brief AES Re-initial + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_re_init(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_RE_INIT_MSK, (value << AES_CON_RE_INIT_POS)); +} + +/** + * @brief AES Re-initial + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + */ +__STATIC_INLINE uint32_t md_aes_get_con_re_init(AES_TypeDef *aes) +{ + + return ((READ_BIT(aes->CON, AES_CON_RE_INIT_MSK) >> AES_CON_RE_INIT_POS) & 0x1); +} + +/** + * @brief AES DMA Function Enable + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_dma_en(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_DMA_EN_MSK, (value << AES_CON_DMA_EN_POSS)); +} + +/** + * @brief AES DMA Function Enable + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + */ +__STATIC_INLINE uint32_t md_aes_get_con_dma_en(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_DMA_EN_MSK) >> AES_CON_DMA_EN_POSS) & 0x3); +} + +/** + * @brief Block Cipher Encryption / Decryption Mode + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_bl(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_BL_MSK, (value << AES_CON_BL_POSS)); +} + +/** + * @brief Block Cipher Encryption / Decryption Mode + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + */ +__STATIC_INLINE uint32_t md_aes_get_con_bl(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_BL_MSK) >> AES_CON_BL_POSS) & 0x7); +} + +/** + * @brief AES Input Reverse + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_rev(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_REV_MSK, (value << AES_CON_REV_POS)); +} + +/** + * @brief AES Input Reverse + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_rev(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_REV_MSK) >> AES_CON_REV_POS) & 0x1); +} + +/** + * @brief AES Mode Control + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_mode(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_MODE_MSK, (value << AES_CON_MODE_POS)); +} + +/** + * @brief AES Mode Control + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_mode(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_MODE_MSK) >> AES_CON_MODE_POS) & 0x1); +} + +/** + * @brief AES Start + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_START 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_start(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_START_MSK, (value << AES_CON_START_POS)); +} + +/** + * @brief AES Start + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_START 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_start(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_START_MSK) >> AES_CON_START_POS) & 0x1); +} + +/** + * @brief AES Interrupt Enable Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_IER_DECIE 1 + * @arg @ref MD_AES_IER_ENCIE 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_ier(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IER, value); +} + +/** + * @brief AES Decryption Interrupt Enable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_enable_ier_decie(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IER, AES_IER_DECIE_MSK, (1 << AES_IER_DECIE_POS)); +} + +/** + * @brief AES Encryption Interrupt Enable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_enable_ier_encie(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IER, AES_IER_ENCIE_MSK, (1 << AES_IER_ENCIE_POS)); +} + +/** + * @brief AES Interrupt Disable Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_IDR_DECID 1 + * @arg @ref MD_AES_IDR_ENCID 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_idr(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IDR, value); +} + +/** + * @brief AES Decryption Interrupt Disable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_disable_idr_decid(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IDR, AES_IDR_DECID_MSK, (1 << AES_IDR_DECID_POS)); +} + +/** + * @brief AES Encryption Interrupt Disable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_disable_idr_encid(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IDR, AES_IDR_DECID_MSK, (1 << AES_IDR_DECID_POS)); +} + +/** + * @brief AES Interrupt Valid Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_IVS_DECIVS_DISABLE 0 + * @arg @ref MD_AES_IVS_DECIVS_ENABLE 1 + * @arg @ref MD_AES_IVS_ENCIVS_DISABLE 0 + * @arg @ref MD_AES_IVS_ENCIVS_ENABLE 1 + */ +__STATIC_INLINE uint32_t md_aes_get_ivs(AES_TypeDef *aes) +{ + return (READ_REG(aes->IVS)); +} + +/** + * @brief AES Decryption Interrupt Valid Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_enabled_ivs_decivs(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IVS, AES_IVS_DECIVS_MSK) >> AES_IVS_DECIVS_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Encryption Interrupt Valid Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_enabled_ivs_encivs(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IVS, AES_IVS_ENCIVS_MSK) >> AES_IVS_ENCIVS_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Raw Interrupt Flag Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @reg MD_AES_RIF_DECRIF_NO_INTERRUPT 0 + * @arg @reg MD_AES_RIF_DECRIF_INTERRUPT 1 + */ +__STATIC_INLINE uint32_t md_aes_get_rif(AES_TypeDef *aes) +{ + return (READ_REG(aes->RIF)); +} + +/** + * @brief AES Encryption Raw Interrupt Flag Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_active_rif_decrif(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->RIF, AES_RIF_DECRIF_MSK) >> AES_RIF_DECRIF_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Encryption Raw Interrupt Flag Status + * @param Mode This parameter can be one of the following values: + * @arg value true, false + * @retval None. + */ +__STATIC_INLINE bool md_aes_is_active_rif_encrif(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->RIF, AES_RIF_ENCRIF_MSK) >> AES_RIF_ENCRIF_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @reg MD_AES_IFM_DECRIF_MASK 0 + * @arg @reg MD_AES_IFM_DECRIF_SIGNAL 1 + * @arg @reg MD_AES_IFM_ENCRIF_MASK 0 + * @arg @reg MD_AES_IFM_ENCRIF_SIGNAL 1 + */ +__STATIC_INLINE uint32_t md_aes_get_ifm(AES_TypeDef *aes) +{ + return (READ_REG(aes->IFM)); +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_active_ifm_decifm(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IFM, AES_IFM_DECIFM_MSK) >> AES_IFM_DECIFM_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_active_ifm_encifm(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IFM, AES_IFM_ENCIFM_MSK) >> AES_IFM_ENCIFM_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Interrupt Clear Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @reg MD_AES_ICR_DECICR 1 + * @arg @reg MD_AES_ICR_ENCICR 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_icr(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->ICR, value); +} + +/** + * @brief AES Decryption Interrupt Clear + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_clear_icr_decicr(AES_TypeDef *aes) +{ + MODIFY_REG(aes->ICR, AES_ICR_DECICR_MSK, (1 << AES_ICR_DECICR_POS)); +} + +/** + * @brief AES Encryption Interrupt Clear + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_clear_icr_encicr(AES_TypeDef *aes) +{ + MODIFY_REG(aes->ICR, AES_ICR_ENCICR_MSK, (1 << AES_ICR_ENCICR_POS)); +} + +/** + * @brief AES 128-bit Input / Ouput Data Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_dio(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->DIO, value); +} + +/** + * @brief AES 128-bit Input / Ouput Data Register + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +//#pragma push +//#pragma O0 +__STATIC_INLINE uint32_t md_aes_get_dio(AES_TypeDef *aes) +{ + return (READ_REG(aes->DIO)); +} +//#pragma pop + +/** + * @brief AES 128-bit Keyword Register 0 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key0(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY0, value); +} + +/** + * @brief AES 128-bit Keyword Register 0 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key0(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY0)); +} + +/** + * @brief AES 128-bit Keyword Register 1 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key1(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY1, value); +} + +/** + * @brief AES 128-bit Keyword Register 1 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key1(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY1)); +} + +/** + * @brief AES 128-bit Keyword Register 2 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key2(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY2, value); +} + +/** + * @brief AES 128-bit Keyword Register 2 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key2(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY2)); +} + +/** + * @brief AES 128-bit Keyword Register 3 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key3(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY3, value); +} + +/** + * @brief AES 128-bit Keyword Register 3 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key3(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY3)); +} + +/** + * @brief AES 128-bit Initial Vector Register 0 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv0(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV0, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 0 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv0(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV0)); +} + +/** + * @brief AES 128-bit Initial Vector Register 1 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv1(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV1, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 1 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv1(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV1)); +} + +/** + * @brief AES 128-bit Initial Vector Register 2 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv2(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV2, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 2 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv2(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV2)); +} + +/** + * @brief AES 128-bit Initial Vector Register 3 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv3(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV3, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 3 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv3(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV3)); +} + +/** + * @} MD_AES_Public_Macros + */ + +/** + * @} AES + */ + +#endif + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h new file mode 100644 index 0000000000000000000000000000000000000000..b2b6d2b2e0fbf3d7c1237319d12982d1d74be13c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file md_CMP.h + * @brief ES32F0271 CMP Head File. + * + * @version V1.00.01 + * @date 11/23/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + + /* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CMP_H__ +#define __MD_CMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_cmp.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (CMP) +/** @defgroup CMP CMP + * @brief CMP micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ + +/** @defgroup MD_CMP_Public_Constants CMP Public Constants + * @{ + */ + +/** @defgroup MD_CMP_PC_CARS CMP Reference voltage + * @{ + */ +#define MD_CMP_CARS_1_25V (0x00000000UL) /*!< @brief Select CARS for 0.25*5V */ +#define MD_CMP_CARS_2_50V (0x00000001UL) /*!< @brief Select CARS for 0.5*5V */ +#define MD_CMP_CARS_3_75V (0x00000002UL) /*!< @brief Select CARS for 0.75*5V */ +#define MD_CMP_CARS_5_00V (0x00000003UL) /*!< @brief Select CARS for 5V */ + +/** + * @} MD_CMP_PC_CARS + */ + + +/** + * @} MD_CMP_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_CMP_Public_Macros CMP Public Macros + * @{ + */ + +/** @defgroup MD_CMP_PF_CON CMP Control Register + * @{ + */ +/** + * @brief Set CMP control register (CMP_CON) + * @param cmp CMP Instance + * @param value The value write in CMP_CON + * @retval None + */ +__STATIC_INLINE void md_cmp_set_con(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CON, value); +} + +/** + * @brief Get CMP control register (CMP_CON) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_con(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CON)); +} + +/** + * @brief Enable Comparator 1 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_con_cmpon1(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CON, CMP_CON_CMPON1_MSK); +} +/** + * @brief Disable Comparator 1 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_con_cmpon1(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CON, CMP_CON_CMPON1_MSK); +} + +/** + * @brief Check if Comparator 1 enable set is enable + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_con_cmpon1(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CON, CMP_CON_CMPON1_MSK)); +} + +/** + * @brief Enable Comparator 2 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_con_cmpon2(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CON, CMP_CON_CMPON2_MSK); +} +/** + * @brief Disable Comparator 2 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_con_cmpon2(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CON, CMP_CON_CMPON2_MSK); +} + +/** + * @brief Check if Comparator 2 enable set is enable + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_con_caon2(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CON, CMP_CON_CMPON2_MSK)); +} + +/** + * @} MD_CMP_PF_CON + */ + + +/** @defgroup MD_CMP_PF_Configuration CMP Configuration Manangement + * @{ + */ + + +/** + * @brief Set CMP control register 1(CMP_CFG1) + * @param cmp CMP Instance + * @param value The value write in CMP_CFG1 + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg1(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CFG1, value); +} +/** + * @brief Get CMP control register 1(CMP_CFG1) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg1(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CFG1)); +} + + +/** + * @brief Set Comparator 1 reference voltage selection. + * @param cmp CMP Instance + * @param RefVol This parameter can be one of the following values: + * @arg MD_CMP_CARS_1_25V + * @arg MD_CMP_CARS_2_50V + * @arg MD_CMP_CARS_3_75V + * @arg MD_CMP_CARS_5_00V + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg1_rs(CMP_TypeDef *cmp, uint32_t RefVol) +{ + MODIFY_REG(cmp->CFG1, CMP_CFG1_RS_MSK, RefVol<CFG1, CMP_CFG1_RS_MSK) >> CMP_CFG1_RS_POSS); +} + + +/** + * @brief Enable Comparator 1 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_fen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK); +} +/** + * @brief Disable Comparator 1 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_fen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK); +} + +/** + * @brief Check if Comparator 1 Filter circuit is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_fen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK) == (CMP_CFG1_FEN_MSK)); +} + + +/** + * @brief Enable comparator 1 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_psen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK); +} +/** + * @brief Disable comparator 1 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_psen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK); +} + +/** + * @brief Check if comparator 1 reverse circuit enable is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_capsen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK) == (CMP_CFG1_PSEN_MSK) ); +} + + +/** + * @brief Enable Comparator 1 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_insel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK); +} +/** + * @brief Disable Comparator 1 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_insel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK); +} + +/** + * @brief Check if comparator 1 Negative input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_insel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK) == (CMP_CFG1_INSEL_MSK)); +} + + +/** + * @brief Enable comparator 1 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_ipsel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK); +} +/** + * @brief Disable comparator 1 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_ipsel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK); +} + +/** + * @brief Check if comparator 1 Positive input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_ipsel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK) == (CMP_CFG1_IPSEL_MSK)); +} + + +/** + * @brief Set CMP control register 2(CMP_CFG2) + * @param cmp CMP Instance + * @param value The value write in CMP_CFG2 + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg2(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CFG2, value); +} +/** + * @brief Get CMP control register 2(CMP_CFG2) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg2(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CFG2)); +} + + +/** + * @brief Set Comparator 2 reference voltage selection. + * @param cmp CMP Instance + * @param RefVol This parameter can be one of the following values: + * @arg MD_CMP_CARS_1_25V + * @arg MD_CMP_CARS_2_50V + * @arg MD_CMP_CARS_3_75V + * @arg MD_CMP_CARS_5_00V + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg2_rs(CMP_TypeDef *cmp, uint32_t RefVol) +{ + MODIFY_REG(cmp->CFG2, CMP_CFG2_RS_MSK, RefVol << CMP_CFG2_RS_POSS); +} + +/** + * @brief Return Comparator 2 reference voltage + * @param cmp CMP Instance + * @retval None + * @arg MD_CMP_CARS_1_25V + * @arg MD_CMP_CARS_2_50V + * @arg MD_CMP_CARS_3_75V + * @arg MD_CMP_CARS_5_00V + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg2_rs(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_RS_MSK) >> CMP_CFG2_RS_POSS); +} + + +/** + * @brief Enable Comparator 2 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_fen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK); +} +/** + * @brief Disable Comparator 2 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_fen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK); +} + +/** + * @brief Check if Comparator 2 Filter circuit is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_fen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK) == (CMP_CFG2_FEN_MSK)) ; +} + + +/** + * @brief Enable comparator 2 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_psen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK); +} +/** + * @brief Disable comparator 2 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_psen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK); +} + +/** + * @brief Check if comparator 2 reverse circuit enable is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_psen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK) == (CMP_CFG2_PSEN_MSK)); +} + + +/** + * @brief Enable Comparator 2 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_insel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK); +} +/** + * @brief Disable Comparator 2 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_insel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK); +} + +/** + * @brief Check if comparator 2 Negative input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_insel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK) == (CMP_CFG2_INSEL_MSK)); +} + + +/** + * @brief Enable comparator 2 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_ipsel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK); +} +/** + * @brief Disable comparator 2 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_ipsel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK); +} + +/** + * @brief Check if comparator 2 Positive input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_ipsel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK) == (CMP_CFG2_IPSEL_MSK)); +} + + +/** + * @} MD_CMP_PF_Configuration + */ + +/** @defgroup MD_CMP_PC_RULT CMP Comparator Output Register. + * @{ + */ + +/** + * @brief Return Comparator output result(CMP_RULT) + * @param cmp CMP Instance + * @retval The state of 1 or 0 + */ +__STATIC_INLINE uint32_t md_cmp_get_rult(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->RULT)); +} + +/** + * @brief Return Comparator 1 output result + * @param cmp CMP Instance + * @retval The state of 1 or 0 + */ +__STATIC_INLINE uint32_t md_cmp_get_rult_cmpo1(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->RULT, CMP_RULT_CMPO1_MSK)); +} +/** + * @brief Return Comparator 2 output result + * @param cmp CMP Instance + * @retval The state of 1 or 0 + */ +__STATIC_INLINE uint32_t md_cmp_get_rult_cmpo2(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->RULT, CMP_RULT_CMPO2_MSK)); +} + + +/** + * @} MD_CMP_PC_RULT + */ + + +/** + * @} MD_CMP_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ + +/** + * @} CMP + */ + +#endif + + +/** + * @} Micro_Driver + */ + +#endif + +#ifdef __cplusplus +} +#endif + + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..f1b65692e7711aa5bd86017a53d8256606b0398e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h @@ -0,0 +1,519 @@ +/** + ****************************************************************************** + * @file md_crc.h + * @brief M601 CRC Head File. + * + * @version V0.01 + * @date 28/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CRC_H__ +#define __MD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (CRC) + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ + +/* Private Types --------------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Public Types ---------------------------------------------------------------*/ +/** @defgroup MD_CRC_INIT CRC public init structure + * @brief + * @{ + */ +typedef struct +{ + uint32_t xorout; + uint32_t refout; + uint32_t refin; + uint32_t byte; + uint32_t mode; + uint32_t req; + uint32_t ds; + uint32_t rst; +} md_crc_init_typedef; +/** + * @} MD_CRC_INIT + */ + +/* Public Constants -----------------------------------------------------------*/ +/** @defgroup MD_CRC_Public_Constants CRC Public Constants + * @brief + * @{ + */ + +/** @defgroup MD_CRC_CON_registers CRC Control Registers + * @brief + * @{ + */ +#define MD_CRC_CON_DMA_ON 1 /*!< This allow user to enable DMA function. */ +#define MD_CRC_CON_DMA_OFF 0 /*!< This allow user to disable DMA function. */ +#define MD_CRC_CON_MSB_ON 1 /*!< User can set this bit to change the 'byte' order of input data. */ +#define MD_CRC_CON_MSB_OFF 1 /*!< User can set this bit to change the 'byte' order of input data. */ +#define MD_CRC_CON_REOUT 0 /*!< This allow user to reverse the order of CRC output data. */ +#define MD_CRC_CON_REOUT_REV 1 /*!< This allow user to reverse the order of CRC output data. */ +#define MD_CRC_CON_REIN 0 /*!< This allow user to reverse the order of CRC input data. */ +#define MD_CRC_CON_REIN_REV 1 /*!< This allow user to reverse the order of CRC input data. */ +#define MD_CRC_CON_SIZE_POLY32 0 /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_SIZE_POLY16 1 /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_SIZE_POLY8 2 /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_MODE_COMP_DISABLE 0 /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_MODE_COMP_ZERO 1 /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_MODE_COMP_ENABLE 2 /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_RESET 1 /*!< User can set this bit to reset CRC function. */ +/** + * @} MD_CRC_CON_registers + */ + +/** @defgroup MD_CRC_STAT_registers CRC Status Registers + * @brief + * @{ + */ +#define MD_CRC_STAT_FAIL 1 /*!< This bit is set when CRC result is not correct. */ +#define MD_CRC_STAT_EMPTY 1 /*!< This bit is cleaned after an CRC calculation. */ +#define MD_CRC_STAT_BUSY 1 /*!< This bit is set when CRC module is calculating result. */ +#define MD_CRC_STAT_DONE 1 /*!< This bit is set when CRC calculation is finish. */ +/** + * @} MD_CRC_STAT_registers + */ + +/** + * @} MD_CRC_Public_Constants + */ + +/* Public Macros --------------------------------------------------------------*/ +/** @defgroup MD_CRC_Public_Macros CRC Public Macros + * @brief + * @{ + */ + +/** + * @brief This register is used to write the CRC initial data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_init(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->INIT, value); +} + +/** + * @brief This register is used to read the CRC initial data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_init(CRC_TypeDef *crc) +{ + return (READ_REG(crc->INIT)); +} + +/** + * @brief This register is used to write the coefficient of the CRC polynomial. Default coefficient is for CRC32. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_poly(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->POLY, value); +} + +/** + * @brief This register is used to read the coefficient of the CRC polynomial. Default coefficient is for CRC32. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_poly(CRC_TypeDef *crc) +{ + return (READ_REG(crc->POLY)); +} + +/** + * @brief This register is used to write the CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_data(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->DATA, value); +} + +/** + * @brief This register is used to read the CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_data(CRC_TypeDef *crc) +{ + return (READ_REG(crc->DATA)); +} + +/** + * @brief This register is used to compare with the CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_comp(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->COMP, value); +} + +/** + * @brief This register is used to compare with the CRC output data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_comp(CRC_TypeDef *crc) +{ + return (READ_REG(crc->COMP)); +} + +/** + * @brief This register is used to set a parameter to do exclusive OR with CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_rema(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->REMA, value); +} + +/** + * @brief This register is used to set a parameter to do exclusive OR with CRC output data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_rema(CRC_TypeDef *crc) +{ + return (READ_REG(crc->REMA)); +} + +/** + * @brief This register is used to set a parameter. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_DMA_ON 1 + * @arg @ref MD_CRC_CON_DMA_OFF 0 + * @arg @ref MD_CRC_CON_MSB_ON 1 + * @arg @ref MD_CRC_CON_MSB_OFF 0 + * @arg @ref MD_CRC_CON_REOUT 0 + * @arg @ref MD_CRC_CON_REOUT_REV 1 + * @arg @ref MD_CRC_CON_REIN 0 + * @arg @ref MD_CRC_CON_REIN_REV 1 + * @arg @ref MD_CRC_CON_SIZE_POLY32 0 + * @arg @ref MD_CRC_CON_SIZE_POLY16 1 + * @arg @ref MD_CRC_CON_SIZE_POLY8 2 + * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE 0 + * @arg @ref MD_CRC_CON_MODE_COMP_ZERO 1 + * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE 2 + * @arg @ref MD_CRC_CON_RESET 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->CON, value); +} + +/** + * @brief This register is used to get a parameter. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_con(CRC_TypeDef *crc) +{ + return (READ_REG(crc->CON)); +} + +/** + * @brief This function allow user to enable DMA function. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_DMA_ON 1 + * @arg @ref MD_CRC_CON_DMA_OFF 0 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_dma(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_DMA_MSK, value << CRC_CON_DMA_POS); +} + +/** + * @brief This function allow user to enable DMA function. + * @param CRC Instance + * @retval value 0: disable, 1: enable. + */ +__STATIC_INLINE uint32_t md_crc_get_con_dma(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_DMA_MSK) >> CRC_CON_DMA_POS) & 0x1); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_MSB_ON 1 + * @arg @ref MD_CRC_CON_MSB_OFF 0 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_msb(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_MSB_MSK, value << CRC_CON_MSB_POS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval value 0: disable, 1: enable. + */ +__STATIC_INLINE uint32_t md_crc_get_con_msb(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_MSB_MSK) >> CRC_CON_MSB_POS) & 0x1); +} + +/** + * @brief This function allow user to reverse the order of CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @reg MD_CRC_CON_REOUT 0 + * @arg @reg MD_CRC_CON_REOUT_REV 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_reout(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_REOUT_MSK, value << CRC_CON_REOUT_POS); +} + +/** + * @brief This function allow user to reverse the order of CRC output data. + * @param CRC Instance + * @retval value 0: Disable reverse operation, 1: Reverse output data. + */ +__STATIC_INLINE uint32_t md_crc_get_con_reout(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_REOUT_MSK) >> CRC_CON_REOUT_POS) & 0x1); +} + +/** + * @brief This function allow user to reverse the order of CRC input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @reg MD_CRC_CON_REIN 0 + * @arg @reg MD_CRC_CON_REIN_REV 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_rein(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_REIN_MSK, value << CRC_CON_REIN_POS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval value 0: Disable reverse operation, 1: Bit reversal done by byte. + */ +__STATIC_INLINE uint32_t md_crc_get_con_rein(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_REIN_MSK) >> CRC_CON_REIN_POS) & 0x1); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_SIZE_POLY32 0 + * @arg @ref MD_CRC_CON_SIZE_POLY16 1 + * @arg @ref MD_CRC_CON_SIZE_POLY8 2 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_size(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_SIZE_MSK, value << CRC_CON_SIZE_POSS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval value 00: 32 bit polynomial, 01: 16 bit polynomial, 10: 8 bit polynomial. + */ +__STATIC_INLINE uint32_t md_crc_get_con_size(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_SIZE_MSK) >> CRC_CON_SIZE_POSS) & 0x3); +} + +/** + * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE 0 + * @arg @ref MD_CRC_CON_MODE_COMP_ZERO 1 + * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE 2 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_mode(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_MODE_MSK, value << CRC_CON_MODE_POSS); +} + +/** + * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. + * @param CRC Instance + * @retval value 00: Disable compare function, 01: Compare CRC result with 32’h0000_0000, 10: Compare CRC result with CRC_COMP. + */ +__STATIC_INLINE uint32_t md_crc_get_con_mode(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_MODE_MSK) >> CRC_CON_MODE_POSS) & 0x3); +} + +/** + * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_RESET 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_reset(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_RESET_MSK, value << CRC_CON_RESET_POS); +} + +/** + * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. + * @param CRC Instance + * @retval value 0. + */ +__STATIC_INLINE uint32_t md_crc_get_con_reset(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_RESET_MSK) >> CRC_CON_RESET_POS) & 0x1); +} + +/** + * @brief This register is used to show the CRC calculation result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_dout(CRC_TypeDef *crc) +{ + return (READ_REG(crc->DOUT)); +} + +/** + * @brief This register is used to show the CRC calculation exculsive OR result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_dout_xor(CRC_TypeDef *crc) +{ + return (READ_REG(crc->DOUT_XOR)); +} + +/** + * @brief This register is used to show the CRC calculation exculsive OR result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_stat(CRC_TypeDef *crc) +{ + return (READ_REG(crc->STAT)); +} + +/** + * @brief This bit is set when CRC result is not correct. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_FAIL 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_fail(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->STAT, CRC_STAT_FAIL_MSK) >> CRC_STAT_FAIL_POS) & 0x1); +} + +/** + * @brief This bit is cleaned after an CRC calculation. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_EMPTY 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_empty(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->STAT, CRC_STAT_EMPTY_MSK) >> CRC_STAT_EMPTY_POS) & 0x1); +} + +/** + * @brief This bit is set when CRC module is calculating result. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_BUSY 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_busy(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->STAT, CRC_STAT_BUSY_MSK) >> CRC_STAT_BUSY_POS) & 0x1); +} + +/** + * @brief This bit is set when CRC module is calculating result. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_DONE 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_done(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->STAT, CRC_STAT_DONE_MSK) >> CRC_STAT_DONE_POS); +} + +/** + * @} MD_CRC_Public_Macros + */ + +/** + * @} CRC + */ + +#endif + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..199fc195b1345342f0b73e8a88f25edbebe9d8fa --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file md_ADC.h + * @brief ES32F0271 DAC Header File. + * + * @version V1.00.01 + * @date 01/14/2019 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_DAC_H__ +#define __MD_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_dac.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined DAC + +/** @defgroup DAC DAC + * @brief DAC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup MD_DAC_Public_Constants DAC Public Constants + * @{ + */ + +/** @defgroup MD_DAC_CON DAC_CON Register + * @{ + */ + +#define MD_ADC_CON_TSEL_SW (0x00000000U<CON, DAC_CON_INVREN_MSK); +} + +/** + * @brief DAC INVREN Disable. + * @param None + * @retval None + */ +__STATIC_INLINE void md_dac_disable_con_invren(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CON, DAC_CON_INVREN_MSK); +} + +/** + * @brief Check if DAC INVREN is enabled. + * @param None + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_enabled_con_invren(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->CON, DAC_CON_INVREN_MSK) == (DAC_CON_INVREN_MSK)); +} + +/** + * @brief TRIGGER enable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_enable_con_trien(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CON, DAC_CON_TRIEN_MSK); +} + +/** + * @brief TRIGGER Disable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_disable_en_trien(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CON, DAC_CON_TRIEN_MSK); +} + +/** + * @brief Check if DAC TRIGGER is enabled. + * @param DACx DAC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_enabled_con_trien(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->EN, DAC_CON_TRIEN_MSK) == (DAC_CON_TRIEN_MSK)); +} + +/** + * @brief Set DACx DIV register. + * @note This bits can only be written none zero value. + * @param DACx DAC Instance. + * @param DIV value. + * @retval None + */ +__STATIC_INLINE void md_dac_set_div(DAC_TypeDef *DACx, uint32_t div) +{ + WRITE_REG(DACx->DIV, div); +} + +/** + * @brief Set DACx DAC_CON WAVE value. + * @param DACx DAC Instance. + * @param WAVE value. + * @retval None + */ +__STATIC_INLINE void md_dac_set_con_wave(DAC_TypeDef *DACx, uint32_t wave) +{ + MODIFY_REG(DACx->CON, DAC_CON_MAMP_MSK, wave<CON, DAC_CON_MAMP_MSK, mamp<CON, DAC_CON_T_SEL_MSK, tsel<TRIG, DAC_TRIG_S_TRIG_MSK); +} + +/** + * @brief Check if Transmit FIFO full. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer full. + * @param DACx DAC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_active_flag_stat_txfull(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->STAT, DAC_STAT_TX_FULL_MSK) == (DAC_STAT_TX_FULL_MSK)); +} + +/** + * @brief Check if Transmit DAC is busy. + * @param DACx DAC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_active_flag_stat_busy(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->STAT, DAC_STAT_BUSY_MSK) == (DAC_STAT_BUSY_MSK)); +} + +/** + * @brief DAC enable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_enable_en_dacen(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->EN, DAC_EN_DAC_EN_MSK); +} + +/** + * @brief DAC Disable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_disable_en_dacen(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->EN, DAC_EN_DAC_EN_MSK); +} + +/** + * @brief Set DACx data register. + * @param DACx DAC Instance. + * @param Tx data value. + * @retval None + */ +__STATIC_INLINE void md_dac_set_txdata(DAC_TypeDef *DACx, uint32_t data) +{ + WRITE_REG(DACx->DATA, data); +} + +#endif + +/** + * @} MD_GPIO_Public_Macros + */ + +/** @} ADC + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..521ce1e61ecce88de6f5ee4de05ab0c9585d2427 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h @@ -0,0 +1,5561 @@ +/** + ****************************************************************************** + * @file md_DMA.h + * @brief ES32F0271 DMA HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_DMA_H__ +#define __MD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_dma.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA DMA + * @brief DMA micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_DMA_PT_INIT DMA Public Init structures + * @{ + */ + +/** + * @brief MD DMA Init Structure definition + */ + + +/** + * @} MD_DMA_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Constants DMA Public Constants + * @{ + */ + +/** @defgroup MD_DMA_DINCOS Destination Increment Offset Size + * @{ + */ +#define MD_DMA_DINCOS_LINKED_DWSEL (0x00000000UL) /** @brief The offset size for the peripheral address calculation is + linked to the DWSEL */ +#define MD_DMA_DINCOS_FIXED_TO_4 (0X00000001UL) /** @brief The offset size for the peripheral address calculation is + fixed to 4 (32-bit alignment). */ +/** + * @} MD_DMA_DINCOS + */ + +/** @defgroup MD_DMA_DBUSEL Destination Transfer Burst Selection + * @{ + */ +#define MD_DMA_DBUSEL_SINGLE (0x00000000U) +#define MD_DMA_DBUSEL_WRAP4 (0x00000002U) +#define MD_DMA_DBUSEL_INCR4 (0x00000003U) +#define MD_DMA_DBUSEL_WRAP8 (0x00000004U) +#define MD_DMA_DBUSEL_INCR8 (0x00000005U) +#define MD_DMA_DBUSEL_WRAP16 (0x00000006U) +#define MD_DMA_DBUSEL_INCR16 (0x00000007U) +/** + * @} MD_DMA_DBUSEL + */ + +/** @defgroup MD_DMA_DDWSEL Destination Transfer Data Width Selection. + * @{ + */ +#define MD_DMA_DDWSEL_ONE_BYTE (0x00000000UL) /** @brief One byte (8-bit) is transferred for every DMA operation. */ +#define MD_DMA_DDWSEL_ONE_HALF_WORD (0x00000001UL) /** @brief One half-word (16-bit) is transferred for every DMA operation. */ +#define MD_DMA_DDWSEL_ONE_WORD (0x00000002UL) /** @brief One word (32-bit) is transferred for every DMA operation. */ +/** + * @} MD_DMA_DDWSEL + */ + +/** @defgroup MD_DMA_SINCOS Source Increment Offset Size + * @{ + */ +#define MD_DMA_SINCOS_LINKED_SWSEL (0x00000000UL) /** @brief The offset size for the peripheral address calculation is + linked to the SWSEL */ +#define MD_DMA_SINCOS_FIXED_TO_4 (0X00000001UL) /** @brief The offset size for the peripheral address calculation is + fixed to 4 (32-bit alignment). */ +/** + * @} MD_DMA_SINCOS + */ + +/** @defgroup MD_DMA_SBUSEL Source Transfer Burst Selection. + * @{ + */ +#define MD_DMA_SBUSEL_SINGLE (0x00000000U) +#define MD_DMA_SBUSEL_WRAP4 (0x00000002U) +#define MD_DMA_SBUSEL_INCR4 (0x00000003U) +#define MD_DMA_SBUSEL_WRAP8 (0x00000004U) +#define MD_DMA_SBUSEL_INCR8 (0x00000005U) +#define MD_DMA_SBUSEL_WRAP16 (0x00000006U) +#define MD_DMA_SBUSEL_INCR16 (0x00000007U) +/** + * @} MD_DMA_SBUSEL + */ + +/** @defgroup MD_DMA_SDWSEL Source Transfer Data Width Selection. + * @{ + */ +#define MD_DMA_SDWSEL_ONE_BYTE (0x00000000UL) /** @brief One byte (8-bit) is transferred for every DMA operation. */ +#define MD_DMA_SDWSEL_ONE_HALF_WORD (0x00000001UL) /** @brief One half-word (16-bit) is transferred for every DMA operation. */ +#define MD_DMA_SDWSEL_ONE_WORD (0x00000002UL) /** @brief One word (32-bit) is transferred for every DMA operation. */ +/** + * @} MD_DMA_SDWSEL + */ + +/** @defgroup MD_DMA_CHPRI DMA Channel Priority. + * @{ + */ +#define MD_DMA_CHPRI_LV0 (0x00000000U) +#define MD_DMA_CHPRI_LV1 (0x00000001U) +#define MD_DMA_CHPRI_LV2 (0x00000002U) +#define MD_DMA_CHPRI_LV3 (0x00000003U) +#define MD_DMA_CHPRI_LV4 (0x00000004U) +#define MD_DMA_CHPRI_LV5 (0x00000005U) +/** + * @} MD_DMA_CHPRI + */ + +/** @defgroup MD_DMA_MODESEL DMA Mode Select. + * @{ + */ +#define MD_DMA_MODESEL_MEM_TO_MEM (0x0000000UL) /** @brief Memory to Memory mode (Memory-to-Memory). */ +#define MD_DMA_MODESEL_PER_TO_MEM (0x0000001UL) /** @brief Peripheral to Memory mode (Peripheral-to-Memory). */ +#define MD_DMA_MODESEL_MEM_TO_PER (0x0000002UL) /** @brief Memory to Peripheral mode (Memory-to-Peripheral). */ +/** + * @} MD_DMA_MODESEL + */ + +/** @defgroup MD_DMA_PFCTRL Peripheral flow controller + * @{ + */ +#define MD_DMA_PFCTRL_DMA_CTRL (0x0000000UL) /** @brief The DMA is the flow controller */ +#define MD_DMA_PFCTRL_PER_CTRL (0x0000001UL) /** @brief The peripheral is the flow controller */ +/** + * @} MD_DMA_PFCTRL + */ + +/** @defgroup MD_DMA_PHSS Peripheral Handshake Software Select + * @{ + */ +#define MD_DMA_PHSS_UART1_TX (0x0000000UL) +#define MD_DMA_PHSS_UART2_TX (0x0000001UL) +#define MD_DMA_PHSS_UART3_TX (0x0000002UL) +#define MD_DMA_PHSS_SUART1_TX (0x0000003UL) +#define MD_DMA_PHSS_SUART2_TX (0x0000004UL) +#define MD_DMA_PHSS_SPI1_TX (0x0000005UL) +#define MD_DMA_PHSS_SPI2_TX (0x0000006UL) +#define MD_DMA_PHSS_I2C1_TX (0x0000007UL) +#define MD_DMA_PHSS_I2C2_TX (0x0000008UL) +#define MD_DMA_PHSS_AES_IN (0x0000009UL) +#define MD_DMA_PHSS_DAC (0x000000AUL) +#define MD_DMA_PHSS_CRC (0x000000BUL) +#define MD_DMA_PHSS_UART1_RX (0x000000FUL) +#define MD_DMA_PHSS_UART2_RX (0x0000010UL) +#define MD_DMA_PHSS_UART3_RX (0x0000011UL) +#define MD_DMA_PHSS_SUART1_RX (0x0000012UL) +#define MD_DMA_PHSS_SUART2_RX (0x0000013UL) +#define MD_DMA_PHSS_SPI1_RTX (0x0000014UL) +#define MD_DMA_PHSS_SPI2_RX (0x0000015UL) +#define MD_DMA_PHSS_I2C1_RX (0x0000016UL) +#define MD_DMA_PHSS_I2C2_RX (0x0000017UL) +#define MD_DMA_PHSS_AES_OUT (0x0000018UL) +#define MD_DMA_PHSS_ADCSS0 (0x0000019UL) +#define MD_DMA_PHSS_ADCSS1 (0x000001AUL) +#define MD_DMA_PHSS_ADCSS2 (0x000001BUL) +#define MD_DMA_PHSS_ADCSS3 (0x000001CUL) +#define MD_DMA_PHSS_BS16T1_UP (0x0000020UL) +#define MD_DMA_PHSS_AD16C4T1_CH1 (0x0000021UL) +#define MD_DMA_PHSS_AD16C4T1_CH2 (0x0000022UL) +#define MD_DMA_PHSS_AD16C4T1_CH3 (0x0000023UL) +#define MD_DMA_PHSS_AD16C4T1_CH4 (0x0000024UL) +#define MD_DMA_PHSS_AD16C4T1_UP (0x0000025UL) +#define MD_DMA_PHSS_AD16C4T1_TRIG (0x0000026UL) +#define MD_DMA_PHSS_AD16C4T1_COM (0x0000027UL) +#define MD_DMA_PHSS_GP32C4T1_CH1 (0x0000028UL) +#define MD_DMA_PHSS_GP32C4T1_CH2 (0x0000029UL) +#define MD_DMA_PHSS_GP32C4T1_CH3 (0x000002AUL) +#define MD_DMA_PHSS_GP32C4T1_CH4 (0x000002BUL) +#define MD_DMA_PHSS_GP32C4T1_UP (0x000002CUL) +#define MD_DMA_PHSS_GP32C4T1_TRIG (0x000002DUL) +#define MD_DMA_PHSS_GP16C4T1_CH1 (0x000002EUL) +#define MD_DMA_PHSS_GP16C4T1_CH2 (0x000002FUL) +#define MD_DMA_PHSS_GP16C4T1_CH3 (0x0000030UL) +#define MD_DMA_PHSS_GP16C4T1_CH4 (0x0000031UL) +#define MD_DMA_PHSS_GP16C4T1_UP (0x0000032UL) +#define MD_DMA_PHSS_GP16C4T1_TRIG (0x0000033UL) +#define MD_DMA_PHSS_GP16C4T2_CH1 (0x0000034UL) +#define MD_DMA_PHSS_GP16C4T2_CH2 (0x0000035UL) +#define MD_DMA_PHSS_GP16C4T2_CH3 (0x0000036UL) +#define MD_DMA_PHSS_GP16C4T2_CH4 (0x0000037UL) +#define MD_DMA_PHSS_GP16C4T2_UP (0x0000038UL) +#define MD_DMA_PHSS_GP16C4T2_TRIG (0x0000039UL) +#define MD_DMA_PHSS_GP16C4T3_CH1 (0x000003AUL) +#define MD_DMA_PHSS_GP16C4T3_CH2 (0x000003BUL) +#define MD_DMA_PHSS_GP16C4T3_CH3 (0x000003CUL) +#define MD_DMA_PHSS_GP16C4T3_CH4 (0x000003DUL) +#define MD_DMA_PHSS_GP16C4T3_UP (0x000003EUL) +#define MD_DMA_PHSS_GP16C4T3_TRIG (0x000003FUL) +#define MD_DMA_PHSS_GP16C2T1_CH1 (0x0000040UL) +#define MD_DMA_PHSS_GP16C2T1_CH2 (0x0000041UL) +#define MD_DMA_PHSS_GP16C2T1_UP (0x0000042UL) +#define MD_DMA_PHSS_GP16C2T1_TRIG (0x0000043UL) +#define MD_DMA_PHSS_GP16C2T1_COM (0x0000044UL) +#define MD_DMA_PHSS_GP16C2T2_CH1 (0x0000046UL) +#define MD_DMA_PHSS_GP16C2T2_CH2 (0x0000047UL) +#define MD_DMA_PHSS_GP16C2T2_UP (0x0000048UL) +#define MD_DMA_PHSS_GP16C2T2_TRIG (0x0000049UL) +#define MD_DMA_PHSS_GP16C2T2_COM (0x000004AUL) +#define MD_DMA_PHSS_GP16C2T3_CH1 (0x000004CUL) +#define MD_DMA_PHSS_GP16C2T3_CH2 (0x000004DUL) +#define MD_DMA_PHSS_GP16C2T3_UP (0x000004EUL) +#define MD_DMA_PHSS_GP16C2T3_TRIG (0x000004FUL) +#define MD_DMA_PHSS_GP16C2T3_COM (0x0000050UL) +#define MD_DMA_PHSS_GP16C2T4_CH1 (0x0000052UL) +#define MD_DMA_PHSS_GP16C2T4_CH2 (0x0000053UL) +#define MD_DMA_PHSS_GP16C2T4_UP (0x0000054UL) +#define MD_DMA_PHSS_GP16C2T4_TRIG (0x0000055UL) +#define MD_DMA_PHSS_GP16C2T4_COM (0x0000056UL) +/** + * @} MD_DMA_PHSS + */ + +/** + * @} MD_DMA_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Macros DMA Public Macros + * @{ + */ + +/** + * @brief DMA Channel 5 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch5tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH5TABIE_MSK); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch5btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH5BTDIE_MSK); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch4tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH4TABIE_MSK); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch4btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH4BTDIE_MSK); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch3tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH3TABIE_MSK); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch3btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH3BTDIE_MSK); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch2tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH2TABIE_MSK); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch2btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH2BTDIE_MSK); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch1tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH1TABIE_MSK); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch1btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH1BTDIE_MSK); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch0tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH0TABIE_MSK); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch0btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH0BTDIE_MSK); +} + +/** @defgroup MD_DMA_IER_CH5TABIE CH5TABIE + * @brief Set DMA Channel 5 TABORT Interrupt Enable bit for md_dma_set_ier() function used + * @param ch5tabie This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_dma_set_ier_ch5tabie_fun(ch5tabie) (ch5tabie<IER, (ch5tabie|ch5btdie|ch4tabie|ch4btdie|ch3tabie|ch3btdie|ch2tabie|ch2btdie|ch1tabie|ch1btdie|ch0tabie|ch0btdie)); +} + +/** + * @brief DMA Channel 5 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch5tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH5TABID_MSK); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch5btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH5BTDID_MSK); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch4tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH4TABID_MSK); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch4btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH4BTDID_MSK); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch3tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH3TABID_MSK); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch3btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH3BTDID_MSK); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch2tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH2TABID_MSK); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch2btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH2BTDID_MSK); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch1tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH1TABID_MSK); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch1btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH1BTDID_MSK); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch0tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH0TABID_MSK); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch0btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH0BTDID_MSK); +} + + +/** + * @brief DMA Channel 5 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH5TABIVS_MSK)>>DMA_IVS_CH5TABIVS_POS); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH5BTDIVS_MSK)>>DMA_IVS_CH5BTDIVS_POS); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH4TABIVS_MSK)>>DMA_IVS_CH4TABIVS_POS); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH4BTDIVS_MSK)>>DMA_IVS_CH4BTDIVS_POS); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH3TABIVS_MSK)>>DMA_IVS_CH3TABIVS_POS); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH3BTDIVS_MSK)>>DMA_IVS_CH3BTDIVS_POS); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH2TABIVS_MSK)>>DMA_IVS_CH2TABIVS_POS); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH2BTDIVS_MSK)>>DMA_IVS_CH2BTDIVS_POS); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH1TABIVS_MSK)>>DMA_IVS_CH1TABIVS_POS); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH1BTDIVS_MSK)>>DMA_IVS_CH1BTDIVS_POS); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH0TABIVS_MSK)>>DMA_IVS_CH0TABIVS_POS); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH0BTDIVS_MSK)>>DMA_IVS_CH0BTDIVS_POS); +} +/** + * @brief Get DMA interrupt valid status register + * @param dma DMA Instance + * @retval DMA channel interrupt valid status + */ +__STATIC_INLINE uint32_t md_dma_get_ivs(DMA_TypeDef *dma) +{ + return (READ_REG(dma->IVS)); +} + +/** + * @brief DMA Channel 5 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH5TABRIF_MSK)>>DMA_RIF_CH5TABRIF_POS); +} +/** + * @brief DMA Channel 5 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH5BTDRIF_MSK)>>DMA_RIF_CH5BTDRIF_POS); +} +/** + * @brief DMA Channel 4 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH4TABRIF_MSK)>>DMA_RIF_CH4TABRIF_POS); +} +/** + * @brief DMA Channel 4 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH4BTDRIF_MSK)>>DMA_RIF_CH4BTDRIF_POS); +} +/** + * @brief DMA Channel 3 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH3TABRIF_MSK)>>DMA_RIF_CH3TABRIF_POS); +} +/** + * @brief DMA Channel 3 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH3BTDRIF_MSK)>>DMA_RIF_CH3BTDRIF_POS); +} +/** + * @brief DMA Channel 2 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH2TABRIF_MSK)>>DMA_RIF_CH2TABRIF_POS); +} +/** + * @brief DMA Channel 2 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH2BTDRIF_MSK)>>DMA_RIF_CH2BTDRIF_POS); +} +/** + * @brief DMA Channel 1 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH1TABRIF_MSK)>>DMA_RIF_CH1TABRIF_POS); +} +/** + * @brief DMA Channel 1 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH1BTDRIF_MSK)>>DMA_RIF_CH1BTDRIF_POS); +} +/** + * @brief DMA Channel 0 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH0TABRIF_MSK)>>DMA_RIF_CH0TABRIF_POS); +} +/** + * @brief DMA Channel 0 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH0BTDRIF_MSK)>>DMA_RIF_CH0BTDRIF_POS); +} +/** + * @brief Get DMA raw interrupt flag status register + * @param dma DMA Instance + * @retval DMA channel raw interrupt flag status + */ +__STATIC_INLINE uint32_t md_dma_get_rif(DMA_TypeDef *dma) +{ + return (READ_REG(dma->RIF)); +} + +/** + * @brief DMA Channel 5 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch5tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH5TABIFM_MSK)>>DMA_IFM_CH5TABIFM_POS); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch5btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH5BTDIFM_MSK)>>DMA_IFM_CH5BTDIFM_POS); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch4tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH4TABIFM_MSK)>>DMA_IFM_CH4TABIFM_POS); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch4btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH4BTDIFM_MSK)>>DMA_IFM_CH4BTDIFM_POS); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch3tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH3TABIFM_MSK)>>DMA_IFM_CH3TABIFM_POS); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch3btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH3BTDIFM_MSK)>>DMA_IFM_CH3BTDIFM_POS); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch2tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH2TABIFM_MSK)>>DMA_IFM_CH2TABIFM_POS); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch2btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH2BTDIFM_MSK)>>DMA_IFM_CH2BTDIFM_POS); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch1tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH1TABIFM_MSK)>>DMA_IFM_CH1TABIFM_POS); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch1btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH1BTDIFM_MSK)>>DMA_IFM_CH1BTDIFM_POS); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch0tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH0TABIFM_MSK)>>DMA_IFM_CH0TABIFM_POS); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch0btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH0BTDIFM_MSK)>>DMA_IFM_CH0BTDIFM_POS); +} +/** + * @brief Get DMA interrupt flag masked status register + * @param dma DMA Instance + * @retval DMA channel interrupt flag masked status + */ +__STATIC_INLINE uint32_t md_dma_get_ifm(DMA_TypeDef *dma) +{ + return (READ_REG(dma->IFM)); +} + + +/** + * @brief DMA Channel 5 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch5tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH5TABICR_MSK); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch5btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH5BTDICR_MSK); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch4tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH4TABICR_MSK); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch4btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH4BTDICR_MSK); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch3tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH3TABICR_MSK); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch3btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH3BTDICR_MSK); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch2tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH2TABICR_MSK); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch2btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH2BTDICR_MSK); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch1tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH1TABICR_MSK); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch1btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH1BTDICR_MSK); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch0tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH0TABICR_MSK); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch0btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH0BTDICR_MSK); +} + +/** @defgroup MD_DMA_ICR_CH5TABICR CH5TABICR + * @brief Set DMA Channel 5 TABORT Interrupt Clear bit for md_dma_set_icr() function used + * @param ch5tabicr This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_dma_set_icr_ch5tabicr_fun(ch5tabicr) (ch5tabicr<ICR, ( ch5tabicr|ch5btdicr|ch4tabicr|ch4btdicr|ch3tabicr|ch3btdicr|ch2tabicr|ch2btdicr| + ch1tabicr|ch1btdicr|ch0tabicr|ch0btdicr)); +} +/** + * @brief Set DMA interrupt clear register(2) + * @param dma DMA Instance + * @param icr is interrupt clear register + * @retval None + */ +__STATIC_INLINE void md_dma_set_icr_icr(DMA_TypeDef *dma, uint32_t icr) +{ + WRITE_REG(dma->ICR, icr); +} + + +/** + * @brief DMA Channel 5 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5PFSER_MSK)>>DMA_EMSG_CH5PFSER_POS); +} +/** + * @brief DMA Channel 5 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5PFOV_MSK)>>DMA_EMSG_CH5PFOV_POS); +} +/** + * @brief DMA Channel 5 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5SETBUER_MSK)>>DMA_EMSG_CH5SETBUER_POS); +} +/** + * @brief DMA Channel 5 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5SETBCER_MSK)>>DMA_EMSG_CH5SETBCER_POS); +} +/** + * @brief DMA Channel 4 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4PFSER_MSK)>>DMA_EMSG_CH4PFSER_POS); +} +/** + * @brief DMA Channel 4 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4PFOV_MSK)>>DMA_EMSG_CH4PFOV_POS); +} +/** + * @brief DMA Channel 4 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4SETBUER_MSK)>>DMA_EMSG_CH4SETBUER_POS); +} +/** + * @brief DMA Channel 4 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4SETBCER_MSK)>>DMA_EMSG_CH4SETBCER_POS); +} +/** + * @brief DMA Channel 3 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3PFSER_MSK)>>DMA_EMSG_CH3PFSER_POS); +} +/** + * @brief DMA Channel 3 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3PFOV_MSK)>>DMA_EMSG_CH3PFOV_POS); +} +/** + * @brief DMA Channel 3 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3SETBUER_MSK)>>DMA_EMSG_CH3SETBUER_POS); +} +/** + * @brief DMA Channel 3 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3SETBCER_MSK)>>DMA_EMSG_CH3SETBCER_POS); +} +/** + * @brief DMA Channel 2 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2PFSER_MSK)>>DMA_EMSG_CH2PFSER_POS); +} +/** + * @brief DMA Channel 2 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2PFOV_MSK)>>DMA_EMSG_CH2PFOV_POS); +} +/** + * @brief DMA Channel 2 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2SETBUER_MSK)>>DMA_EMSG_CH2SETBUER_POS); +} +/** + * @brief DMA Channel 2 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2SETBCER_MSK)>>DMA_EMSG_CH2SETBCER_POS); +} +/** + * @brief DMA Channel 1 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1PFSER_MSK)>>DMA_EMSG_CH1PFSER_POS); +} +/** + * @brief DMA Channel 1 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1PFOV_MSK)>>DMA_EMSG_CH1PFOV_POS); +} +/** + * @brief DMA Channel 1 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1SETBUER_MSK)>>DMA_EMSG_CH1SETBUER_POS); +} +/** + * @brief DMA Channel 1 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1SETBCER_MSK)>>DMA_EMSG_CH1SETBCER_POS); +} +/** + * @brief DMA Channel 0 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0PFSER_MSK)>>DMA_EMSG_CH0PFSER_POS); +} +/** + * @brief DMA Channel 0 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0PFOV_MSK)>>DMA_EMSG_CH0PFOV_POS); +} +/** + * @brief DMA Channel 0 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0SETBUER_MSK)>>DMA_EMSG_CH0SETBUER_POS); +} +/** + * @brief DMA Channel 0 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0SETBCER_MSK)>>DMA_EMSG_CH0SETBCER_POS); +} +/** + * @brief Get DMA error message register + * @param dma DMA Instance + * @retval DMA channel error message status + */ +__STATIC_INLINE uint32_t md_dma_get_emsg(DMA_TypeDef *dma) +{ + return (READ_REG(dma->EMSG)); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DINCOS_MSK, (dincos<CSR0, DMA_CSR0_DINCOS_MSK)>>DMA_CSR0_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DBUSEL_MSK, (dbusel<CSR0, DMA_CSR0_DBUSEL_MSK)>>DMA_CSR0_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DDWSEL_MSK, (ddwsel<CSR0, DMA_CSR0_DDWSEL_MSK)>>DMA_CSR0_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DINC_MSK, (dinc<CSR0, DMA_CSR0_DINC_MSK)>>DMA_CSR0_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SINCOS_MSK, (sincos<CSR0, DMA_CSR0_SINCOS_MSK)>>DMA_CSR0_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SBUSEL_MSK, (sbusel<CSR0, DMA_CSR0_SBUSEL_MSK)>>DMA_CSR0_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SDWSEL_MSK, (sdwsel<CSR0, DMA_CSR0_SDWSEL_MSK)>>DMA_CSR0_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param sinc can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sinc(DMA_TypeDef *dma, uint32_t sinc) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SINC_MSK, (sinc<CSR0, DMA_CSR0_SINC_MSK)>>DMA_CSR0_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_PHSS_MSK, (phss<CSR0, DMA_CSR0_PHSS_MSK)>>DMA_CSR0_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_CHPRI_MSK, (chpri<CSR0, DMA_CSR0_CHPRI_MSK)>>DMA_CSR0_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_MODESEL_MSK, (modesel<CSR0, DMA_CSR0_MODESEL_MSK)>>DMA_CSR0_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DIRMDEN_MSK, (dirmden<CSR0, DMA_CSR0_DIRMDEN_MSK)>>DMA_CSR0_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_PFCTRL_MSK, (pfctrl<CSR0, DMA_CSR0_PFCTRL_MSK)>>DMA_CSR0_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_CIRC_MSK, (circ<CSR0, DMA_CSR0_CIRC_MSK)>>DMA_CSR0_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_CHEN_MSK, (chen<CSR0, DMA_CSR0_CHEN_MSK)>>DMA_CSR0_CHEN_POS); +} + +/** @defgroup MD_DMA_CSR0_DINCOS DINCOS + * @brief Set Destination Increment Offset Size bit for md_dma_set_cs0() function used + * @param dincos This parameter can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @{ + */ +#define md_dma_set_csr0_dincos_fun(dincos) (dincos<CSR0, (dincos|dbusel|ddwsel|dinc|sincos|sbusel|sdwsel|sinc| + phss|chpri|modesel|dirmden|pfctrl|circ|chen)); +} + + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar0_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR0, DMA_SAR0_SAR_MSK, (sar<SAR0, DMA_SAR0_SAR_MSK)>>DMA_SAR0_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar0_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR0, DMA_DAR0_DAR_MSK, (dar<DAR0, DMA_DAR0_DAR_MSK)>>DMA_DAR0_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr0_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR0, DMA_BCR0_CBCR_MSK)>>DMA_BCR0_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr0_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR0, DMA_BCR0_BCR_MSK, (bcr<BCR0, DMA_BCR0_BCR_MSK)>>DMA_BCR0_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DINCOS_MSK, (dincos<CSR1, DMA_CSR1_DINCOS_MSK)>>DMA_CSR1_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DBUSEL_MSK, (dbusel<CSR1, DMA_CSR1_DBUSEL_MSK)>>DMA_CSR1_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DDWSEL_MSK, (ddwsel<CSR1, DMA_CSR1_DDWSEL_MSK)>>DMA_CSR1_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DINC_MSK, (dinc<CSR1, DMA_CSR1_DINC_MSK)>>DMA_CSR1_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SINCOS_MSK, (sincos<CSR1, DMA_CSR1_SINCOS_MSK)>>DMA_CSR1_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SBUSEL_MSK, (sbusel<CSR1, DMA_CSR1_SBUSEL_MSK)>>DMA_CSR1_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SDWSEL_MSK, (sdwsel<CSR1, DMA_CSR1_SDWSEL_MSK)>>DMA_CSR1_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SINC_MSK, (dinc<CSR1, DMA_CSR1_SINC_MSK)>>DMA_CSR1_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_PHSS_MSK, (phss<CSR1, DMA_CSR1_PHSS_MSK)>>DMA_CSR1_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_CHPRI_MSK, (chpri<CSR1, DMA_CSR1_CHPRI_MSK)>>DMA_CSR1_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_MODESEL_MSK, (modesel<CSR1, DMA_CSR1_MODESEL_MSK)>>DMA_CSR1_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DIRMDEN_MSK, (dirmden<CSR1, DMA_CSR1_DIRMDEN_MSK)>>DMA_CSR1_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_PFCTRL_MSK, (pfctrl<CSR1, DMA_CSR1_PFCTRL_MSK)>>DMA_CSR1_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_CIRC_MSK, (circ<CSR1, DMA_CSR1_CIRC_MSK)>>DMA_CSR1_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_CHEN_MSK, (chen<CSR1, DMA_CSR1_CHEN_MSK)>>DMA_CSR1_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar1_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR1, DMA_SAR1_SAR_MSK, (sar<SAR1, DMA_SAR1_SAR_MSK)>>DMA_SAR1_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar1_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR1, DMA_DAR1_DAR_MSK, (dar<DAR1, DMA_DAR1_DAR_MSK)>>DMA_DAR1_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr1_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR1, DMA_BCR1_CBCR_MSK)>>DMA_BCR1_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr1_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR1, DMA_BCR1_BCR_MSK, (bcr<BCR1, DMA_BCR1_BCR_MSK)>>DMA_BCR1_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DINCOS_MSK, (dincos<CSR2, DMA_CSR2_DINCOS_MSK)>>DMA_CSR2_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DBUSEL_MSK, (dbusel<CSR2, DMA_CSR2_DBUSEL_MSK)>>DMA_CSR2_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DDWSEL_MSK, (ddwsel<CSR2, DMA_CSR2_DDWSEL_MSK)>>DMA_CSR2_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DINC_MSK, (dinc<CSR2, DMA_CSR2_DINC_MSK)>>DMA_CSR2_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SINCOS_MSK, (sincos<CSR2, DMA_CSR2_SINCOS_MSK)>>DMA_CSR2_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SBUSEL_MSK, (sbusel<CSR2, DMA_CSR2_SBUSEL_MSK)>>DMA_CSR2_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SDWSEL_MSK, (sdwsel<CSR2, DMA_CSR2_SDWSEL_MSK)>>DMA_CSR2_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SINC_MSK, (dinc<CSR2, DMA_CSR2_SINC_MSK)>>DMA_CSR2_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_PHSS_MSK, (phss<CSR2, DMA_CSR2_PHSS_MSK)>>DMA_CSR2_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_CHPRI_MSK, (chpri<CSR2, DMA_CSR2_CHPRI_MSK)>>DMA_CSR2_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_MODESEL_MSK, (modesel<CSR2, DMA_CSR2_MODESEL_MSK)>>DMA_CSR2_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DIRMDEN_MSK, (dirmden<CSR2, DMA_CSR2_DIRMDEN_MSK)>>DMA_CSR2_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_PFCTRL_MSK, (pfctrl<CSR2, DMA_CSR2_PFCTRL_MSK)>>DMA_CSR2_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_CIRC_MSK, (circ<CSR2, DMA_CSR2_CIRC_MSK)>>DMA_CSR2_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_CHEN_MSK, (chen<CSR2, DMA_CSR2_CHEN_MSK)>>DMA_CSR2_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar2_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR2, DMA_SAR2_SAR_MSK, (sar<SAR2, DMA_SAR2_SAR_MSK)>>DMA_SAR2_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar2_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR2, DMA_DAR2_DAR_MSK, (dar<DAR2, DMA_DAR2_DAR_MSK)>>DMA_DAR2_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr2_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR2, DMA_BCR2_CBCR_MSK)>>DMA_BCR2_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr2_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR2, DMA_BCR2_BCR_MSK, (bcr<BCR2, DMA_BCR2_BCR_MSK)>>DMA_BCR2_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DINCOS_MSK, (dincos<CSR3, DMA_CSR3_DINCOS_MSK)>>DMA_CSR3_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DBUSEL_MSK, (dbusel<CSR3, DMA_CSR3_DBUSEL_MSK)>>DMA_CSR3_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DDWSEL_MSK, (ddwsel<CSR3, DMA_CSR3_DDWSEL_MSK)>>DMA_CSR3_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DINC_MSK, (dinc<CSR3, DMA_CSR3_DINC_MSK)>>DMA_CSR3_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SINCOS_MSK, (sincos<CSR3, DMA_CSR3_SINCOS_MSK)>>DMA_CSR3_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SBUSEL_MSK, (sbusel<CSR3, DMA_CSR3_SBUSEL_MSK)>>DMA_CSR3_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SDWSEL_MSK, (sdwsel<CSR3, DMA_CSR3_SDWSEL_MSK)>>DMA_CSR3_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SINC_MSK, (dinc<CSR3, DMA_CSR3_SINC_MSK)>>DMA_CSR3_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_PHSS_MSK, (phss<CSR3, DMA_CSR3_PHSS_MSK)>>DMA_CSR3_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_CHPRI_MSK, (chpri<CSR3, DMA_CSR3_CHPRI_MSK)>>DMA_CSR3_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_MODESEL_MSK, (modesel<CSR3, DMA_CSR3_MODESEL_MSK)>>DMA_CSR3_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DIRMDEN_MSK, (dirmden<CSR3, DMA_CSR3_DIRMDEN_MSK)>>DMA_CSR3_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_PFCTRL_MSK, (pfctrl<CSR3, DMA_CSR3_PFCTRL_MSK)>>DMA_CSR3_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_CIRC_MSK, (circ<CSR3, DMA_CSR3_CIRC_MSK)>>DMA_CSR3_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_CHEN_MSK, (chen<CSR3, DMA_CSR3_CHEN_MSK)>>DMA_CSR3_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar3_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR3, DMA_SAR3_SAR_MSK, (sar<SAR3, DMA_SAR3_SAR_MSK)>>DMA_SAR3_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar3_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR3, DMA_DAR3_DAR_MSK, (dar<DAR3, DMA_DAR3_DAR_MSK)>>DMA_DAR3_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr3_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR3, DMA_BCR3_CBCR_MSK)>>DMA_BCR3_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr3_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR3, DMA_BCR3_BCR_MSK, (bcr<BCR3, DMA_BCR3_BCR_MSK)>>DMA_BCR3_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DINCOS_MSK, (dincos<CSR4, DMA_CSR4_DINCOS_MSK)>>DMA_CSR4_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DBUSEL_MSK, (dbusel<CSR4, DMA_CSR4_DBUSEL_MSK)>>DMA_CSR4_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DDWSEL_MSK, (ddwsel<CSR4, DMA_CSR4_DDWSEL_MSK)>>DMA_CSR4_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DINC_MSK, (dinc<CSR4, DMA_CSR4_DINC_MSK)>>DMA_CSR4_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SINCOS_MSK, (sincos<CSR4, DMA_CSR4_SINCOS_MSK)>>DMA_CSR4_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SBUSEL_MSK, (sbusel<CSR4, DMA_CSR4_SBUSEL_MSK)>>DMA_CSR4_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SDWSEL_MSK, (sdwsel<CSR4, DMA_CSR4_SDWSEL_MSK)>>DMA_CSR4_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SINC_MSK, (dinc<CSR4, DMA_CSR4_SINC_MSK)>>DMA_CSR4_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_PHSS_MSK, (phss<CSR4, DMA_CSR4_PHSS_MSK)>>DMA_CSR4_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_CHPRI_MSK, (chpri<CSR4, DMA_CSR4_CHPRI_MSK)>>DMA_CSR4_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_MODESEL_MSK, (modesel<CSR4, DMA_CSR4_MODESEL_MSK)>>DMA_CSR4_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DIRMDEN_MSK, (dirmden<CSR4, DMA_CSR4_DIRMDEN_MSK)>>DMA_CSR4_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_PFCTRL_MSK, (pfctrl<CSR4, DMA_CSR4_PFCTRL_MSK)>>DMA_CSR4_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_CIRC_MSK, (circ<CSR4, DMA_CSR4_CIRC_MSK)>>DMA_CSR4_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_CHEN_MSK, (chen<CSR4, DMA_CSR4_CHEN_MSK)>>DMA_CSR4_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar4_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR4, DMA_SAR4_SAR_MSK, (sar<SAR4, DMA_SAR4_SAR_MSK)>>DMA_SAR4_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar4_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR4, DMA_DAR4_DAR_MSK, (dar<DAR4, DMA_DAR4_DAR_MSK)>>DMA_DAR4_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr4_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR4, DMA_BCR4_CBCR_MSK)>>DMA_BCR4_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr4_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR4, DMA_BCR4_BCR_MSK, (bcr<BCR4, DMA_BCR4_BCR_MSK)>>DMA_BCR4_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DINCOS_MSK, (dincos<CSR5, DMA_CSR5_DINCOS_MSK)>>DMA_CSR5_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DBUSEL_MSK, (dbusel<CSR5, DMA_CSR5_DBUSEL_MSK)>>DMA_CSR5_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DDWSEL_MSK, (ddwsel<CSR5, DMA_CSR5_DDWSEL_MSK)>>DMA_CSR5_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DINC_MSK, (dinc<CSR5, DMA_CSR5_DINC_MSK)>>DMA_CSR5_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SINCOS_MSK, (sincos<CSR5, DMA_CSR5_SINCOS_MSK)>>DMA_CSR5_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SBUSEL_MSK, (sbusel<CSR5, DMA_CSR5_SBUSEL_MSK)>>DMA_CSR5_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SDWSEL_MSK, (sdwsel<CSR5, DMA_CSR5_SDWSEL_MSK)>>DMA_CSR5_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SINC_MSK, (dinc<CSR5, DMA_CSR5_SINC_MSK)>>DMA_CSR5_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_PHSS_MSK, (phss<CSR5, DMA_CSR5_PHSS_MSK)>>DMA_CSR5_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_CHPRI_MSK, (chpri<CSR5, DMA_CSR5_CHPRI_MSK)>>DMA_CSR5_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_MODESEL_MSK, (modesel<CSR5, DMA_CSR5_MODESEL_MSK)>>DMA_CSR5_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DIRMDEN_MSK, (dirmden<CSR5, DMA_CSR5_DIRMDEN_MSK)>>DMA_CSR5_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_PFCTRL_MSK, (pfctrl<CSR5, DMA_CSR5_PFCTRL_MSK)>>DMA_CSR5_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_CIRC_MSK, (circ<CSR5, DMA_CSR5_CIRC_MSK)>>DMA_CSR5_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_CHEN_MSK, (chen<CSR5, DMA_CSR5_CHEN_MSK)>>DMA_CSR5_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar5_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR5, DMA_SAR5_SAR_MSK, (sar<SAR5, DMA_SAR5_SAR_MSK)>>DMA_SAR5_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar5_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR5, DMA_DAR5_DAR_MSK, (dar<DAR5, DMA_DAR5_DAR_MSK)>>DMA_DAR5_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr5_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR5, DMA_BCR5_CBCR_MSK)>>DMA_BCR5_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr5_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR5, DMA_BCR5_BCR_MSK, (bcr<BCR5, DMA_BCR5_BCR_MSK)>>DMA_BCR5_BCR_POSS); +} + +/** + * @} MD_DMA_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup MD_DMA_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_DMA_Basic_Configuration + */ + + +/** + * @} MD_DMA_Public_Functions + */ + +#endif + +/** + * @} DMA + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..7f00f8320e03f0d68bb9cf6fa15fc064abdd593e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h @@ -0,0 +1,5167 @@ +/** + ****************************************************************************** + * @file md_EXTI.h + * @brief ES32F0271 EXTI HEAD File. + * + * @version V1.00.01 + * @date 22/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_EXTI_H__ +#define __MD_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_exti.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (EXTI) +/** @defgroup EXTI EXTI + * @brief EXTI micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ + +/** @defgroup MD_EXTI_Public_Constants EXTI Public Constants + * @{ + */ + +/** @defgroup MD_EXTI_PC_Source EXTI Line Source + * @{ + */ +#define MD_EXTI_Pin_GPIOA (0x00000000UL) /*!< @brief Select GPIOA for EXTIx */ +#define MD_EXTI_Pin_GPIOB (0x00000001UL) /*!< @brief Select GPIOB for EXTIx */ +#define MD_EXTI_Pin_GPIOC (0x00000002UL) /*!< @brief Select GPIOC for EXTIx */ +#define MD_EXTI_Pin_GPIOD (0x00000003UL) /*!< @brief Select GPIOD for EXTIx */ + + /** + * @} MD_EXTI_PC_Source + */ + +/** +* @} MD_EXTI_Public_Constants +*/ + + + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_EXTI_Public_Macros EXTI Public Macros + * @{ + */ + + + +/** @defgroup MD_EXTI_PF_Basic_Configuration EXTI Configuration Management + * @{ + */ +/** + * @brief Set EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @param value The value write in EXTI->ICFG1 + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICFG1, value); +} + +/** + * @brief Get EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ICFG1)); +} + +/** + * @brief Set EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @param value The value write in EXTI->ICFG2 + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICFG2, value); +} + +/** + * @brief Get EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ICFG2)); +} + +/** + * @brief Set EXTI0 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio0(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO0_MSK, Source); +} + +/** + * @brief Get EXTI0 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO0_MSK)>>EXTI_ICFG1_GPIO0_POSS); +} + +/** + * @brief Set EXTI1 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio1(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO1_MSK, Source << EXTI_ICFG1_GPIO1_POSS); +} + +/** + * @brief Get EXTI1 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO1_MSK)>>EXTI_ICFG1_GPIO1_POSS); +} + +/** + * @brief Set EXTI2 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio2(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO2_MSK, Source << EXTI_ICFG1_GPIO2_POSS); +} + +/** + * @brief Get EXTI2 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO2_MSK)>>EXTI_ICFG1_GPIO2_POSS); +} + +/** + * @brief Set EXTI3 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio3(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO3_MSK, Source << EXTI_ICFG1_GPIO3_POSS); +} + +/** + * @brief Get EXTI3 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio3(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO3_MSK)>>EXTI_ICFG1_GPIO0_POSS); +} + +/** + * @brief Set EXTI4 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio4(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO4_MSK, Source << EXTI_ICFG1_GPIO4_POSS); +} + +/** + * @brief Get EXTI4 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio4(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO4_MSK)>>EXTI_ICFG1_GPIO4_POSS); +} + +/** + * @brief Set EXTI5 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio5(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO5_MSK, Source << EXTI_ICFG1_GPIO5_POSS); +} + +/** + * @brief Get EXTI5 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio5(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO5_MSK)>>EXTI_ICFG1_GPIO5_POSS); +} + +/** + * @brief Set EXTI6 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio6(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO6_MSK, Source << EXTI_ICFG1_GPIO6_POSS); +} + +/** + * @brief Get EXTI6 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio6(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO6_MSK)>>EXTI_ICFG1_GPIO6_POSS); +} + +/** + * @brief Set EXTI7 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio7(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO7_MSK, Source << EXTI_ICFG1_GPIO7_POSS); +} + +/** + * @brief Get EXTI7 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO7_MSK)>>EXTI_ICFG1_GPIO7_POSS); +} + + +/** + * @brief Set EXTI8 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio8(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO8_MSK, Source << EXTI_ICFG2_GPIO8_POSS); +} + +/** + * @brief Get EXTI8 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio8(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO8_MSK)>>EXTI_ICFG2_GPIO8_POSS); +} + +/** + * @brief Set EXTI9 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio9(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO9_MSK, Source << EXTI_ICFG2_GPIO9_POSS); +} + +/** + * @brief Get EXTI9 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio9(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO9_MSK)>>EXTI_ICFG2_GPIO9_POSS); +} + +/** + * @brief Set EXTI10 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio10(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO10_MSK, Source << EXTI_ICFG2_GPIO10_POSS); +} + +/** + * @brief Get EXTI10 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio10(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO10_MSK)>>EXTI_ICFG2_GPIO10_POSS); +} + +/** + * @brief Set EXTI11 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio11(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO11_MSK, Source << EXTI_ICFG2_GPIO11_POSS); +} + +/** + * @brief Get EXTI11 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio11(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO11_MSK)>>EXTI_ICFG2_GPIO11_POSS); +} + +/** + * @brief Set EXTI12 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio12(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO12_MSK, Source << EXTI_ICFG2_GPIO12_POSS); +} + +/** + * @brief Get EXTI12 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio12(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO12_MSK)>>EXTI_ICFG2_GPIO12_POSS); +} + +/** + * @brief Set EXTI13 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio13(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO13_MSK, Source << EXTI_ICFG2_GPIO13_POSS); +} + +/** + * @brief Get EXTI13 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio13(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO13_MSK)>>EXTI_ICFG2_GPIO13_POSS); +} + +/** + * @brief Set EXTI14 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio14(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO14_MSK, Source << EXTI_ICFG2_GPIO14_POSS); +} + +/** + * @brief Get EXTI14 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio14(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO14_MSK)>>EXTI_ICFG2_GPIO14_POSS); +} + +/** + * @brief Set EXTI15 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio15(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO15_MSK, Source << EXTI_ICFG2_GPIO15_POSS); +} + +/** + * @brief Get EXTI15 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO15_MSK)>>EXTI_ICFG2_GPIO15_POSS); +} + +/** + * @} MD_EXTI_PF_Basic_Configuration + */ + +/** @defgroup MD_EXTI_PF_RTS EXTI Rising Edge Trigger Selection Register + * @{ + */ + +/** + * @brief Set rising trigger event configuration bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->RTS + * @retval None + */ +__STATIC_INLINE void md_exti_set_rts(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->RTS, value); +} + +/** + * @brief Get rising trigger event configuration bit of line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_rts(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->RTS)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK) == (EXTI_RTS_GPIO0_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK) == (EXTI_RTS_GPIO1_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK) == (EXTI_RTS_GPIO2_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK) == (EXTI_RTS_GPIO3_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK) == (EXTI_RTS_GPIO4_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK) == (EXTI_RTS_GPIO5_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK) == (EXTI_RTS_GPIO6_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK) == (EXTI_RTS_GPIO7_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK) == (EXTI_RTS_GPIO8_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK) == (EXTI_RTS_GPIO9_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK) == (EXTI_RTS_GPIO10_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK) == (EXTI_RTS_GPIO11_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK) == (EXTI_RTS_GPIO12_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK) == (EXTI_RTS_GPIO13_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK) == (EXTI_RTS_GPIO14_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 15 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK) == (EXTI_RTS_GPIO15_MSK)); +} + + +/** + * @brief Enable rising trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_CMP1_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_CMP1_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_CMP1_MSK) == (EXTI_RTS_CMP1_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_CMP2_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_CMP2_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_CMP2_MSK) == (EXTI_RTS_CMP2_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_PVD0_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_PVD0_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_PVD0_MSK) == (EXTI_RTS_PVD0_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK) == (EXTI_RTS_WAKEUP_MSK)); +} + +/** + * @} MD_EXTI_PF_RTS + */ + +/** @defgroup MD_EXTI_PF_FTS EXTI Falling Edge Trigger Selection Register + * @{ + */ + +/** + * @brief Set falling trigger event configuration bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->FTS + * @retval None + */ +__STATIC_INLINE void md_exti_set_fts(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->FTS, value); +} + +/** + * @brief Get falling trigger event configuration bit of line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_fts(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->FTS)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK) == (EXTI_FTS_GPIO0_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK) == (EXTI_FTS_GPIO1_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK) == (EXTI_FTS_GPIO2_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK) == (EXTI_FTS_GPIO3_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK) == (EXTI_FTS_GPIO4_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK) == (EXTI_FTS_GPIO5_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK) == (EXTI_FTS_GPIO6_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK) == (EXTI_FTS_GPIO7_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK) == (EXTI_FTS_GPIO8_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK) == (EXTI_FTS_GPIO9_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK) == (EXTI_FTS_GPIO10_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK) == (EXTI_FTS_GPIO11_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK) == (EXTI_FTS_GPIO12_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK) == (EXTI_FTS_GPIO13_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK) == (EXTI_FTS_GPIO14_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 15 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK) == (EXTI_FTS_GPIO15_MSK)); +} + + + +/** + * @brief Enable falling trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_CMP1_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_CMP1_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_CMP1_MSK) == (EXTI_FTS_CMP1_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_CMP2_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 18 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_CMP2_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 18 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_CMP2_MSK) == (EXTI_RTS_CMP2_MSK)); +} + + +/** + * @brief Enable falling trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_PVD0_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_PVD0_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_PVD0_MSK) == (EXTI_FTS_PVD0_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK) == (EXTI_FTS_WAKEUP_MSK)); +} + + + +/** + * @} MD_EXTI_PF_FTS + */ + +/** @defgroup MD_EXTI_PF_SWI EXTI Software Interrupt Event register + * @{ + */ + +/** + * @brief Set software interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->SWI + * @retval None + */ +__STATIC_INLINE void md_exti_set_swi(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->SWI, value); +} + +/** + * @brief Get software interrupt on line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_swi(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->SWI)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK); +} + +/** + * @brief Disable software interrupt on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK); +} + +/** + * @brief Check if software interrupt on line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK) == (EXTI_SWI_GPIO0_MSK)); +} + +/** + * @brief Enable software interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK); +} + +/** + * @brief Disable software interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK); +} + +/** + * @brief Check if software interrupt on line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK) == (EXTI_SWI_GPIO1_MSK)); +} + +/** + * @brief Enable software interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK); +} + +/** + * @brief Disable software interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK); +} + +/** + * @brief Check if software interrupt on line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK) == (EXTI_SWI_GPIO2_MSK)); +} + +/** + * @brief Enable software interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK); +} + +/** + * @brief Disable software interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK); +} + +/** + * @brief Check if software interrupt on line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK) == (EXTI_SWI_GPIO3_MSK)); +} + +/** + * @brief Enable software interrupt on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK); +} + +/** + * @brief Check if software interrupt on line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK) == (EXTI_SWI_GPIO4_MSK)); +} + +/** + * @brief Enable software interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK); +} + +/** + * @brief Disable software interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK); +} + +/** + * @brief Check if software interrupt on line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK) == (EXTI_SWI_GPIO5_MSK)); +} + +/** + * @brief Enable software interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK); +} + +/** + * @brief Disable software interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK); +} + +/** + * @brief Check if software interrupt on line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK) == (EXTI_SWI_GPIO6_MSK)); +} + +/** + * @brief Enable software interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK); +} + +/** + * @brief Disable software interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK); +} + +/** + * @brief Check if software interrupt on line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK) == (EXTI_SWI_GPIO7_MSK)); +} + +/** + * @brief Enable software interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK); +} + +/** + * @brief Disable software interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK); +} + +/** + * @brief Check if software interrupt on line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK) == (EXTI_SWI_GPIO8_MSK)); +} + +/** + * @brief Enable software interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK); +} + +/** + * @brief Disable software interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK); +} + +/** + * @brief Check if software interrupt on line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK) == (EXTI_SWI_GPIO9_MSK)); +} + +/** + * @brief Enable software interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK); +} + +/** + * @brief Disable software interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK); +} + +/** + * @brief Check if software interrupt on line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK) == (EXTI_SWI_GPIO10_MSK)); +} + +/** + * @brief Enable software interrupt on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO11_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); +} + +/** + * @brief Check if software interrupt on line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO11_MSK) == (EXTI_SWI_GPIO11_MSK)); +} + +/** + * @brief Enable software interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK); +} + +/** + * @brief Disable software interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK); +} + +/** + * @brief Check if software interrupt on line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK) == (EXTI_SWI_GPIO12_MSK)); +} + +/** + * @brief Enable software interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK); +} + +/** + * @brief Disable software interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK); +} + +/** + * @brief Check if software interrupt on line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK) == (EXTI_SWI_GPIO13_MSK)); +} + +/** + * @brief Enable software interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK); +} + +/** + * @brief Disable software interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK); +} + +/** + * @brief Check if software interrupt on line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK) == (EXTI_SWI_GPIO14_MSK)); +} + +/** + * @brief Enable software interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK); +} + +/** + * @brief Disable software interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK); +} + +/** + * @brief Check if software interrupt on line is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK) == (EXTI_SWI_GPIO15_MSK)); +} + +/** + * @brief Enable software interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_CMP1_MSK); +} + +/** + * @brief Disable software interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_CMP1_MSK); +} + +/** + * @brief Check if software interrupt on line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_CMP1_MSK) == (EXTI_SWI_CMP1_MSK)); +} + +/** + * @brief Enable software interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_CMP2_MSK); +} + +/** + * @brief Disable software interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_CMP2_MSK); +} + +/** + * @brief Check if software interrupt on line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_CMP2_MSK) == (EXTI_SWI_CMP2_MSK)); +} + + +/** + * @brief Enable software interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_PVD0_MSK); +} + +/** + * @brief Disable software interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_PVD0_MSK); +} + +/** + * @brief Check if software interrupt on line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_PVD0_MSK) == (EXTI_SWI_PVD0_MSK)); +} + +/** + * @brief Enable software interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK); +} + +/** + * @brief Disable software interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK); +} + +/** + * @brief Check if software interrupt on line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK) == (EXTI_SWI_WAKEUP_MSK)); +} + +/** + * @} MD_EXTI_PF_SWI + */ + + +/** @defgroup MD_EXTI_PF_ADTE EXTI ADC Trigger Enable Register + * @{ + */ +/** + * @brief Set ADC trigger enable on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ADTE + * @retval None + */ +__STATIC_INLINE void md_exti_set_adte(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ADTE, value); +} + +/** + * @brief Get ADC trigger enable on line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_adte(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ADTE)); +} + +/** + * @brief Enable ADC trigger on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK); +} + +/** + * @brief Disable ADC trigger on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK); +} + +/** + * @brief Check if ADC trigger on line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK) == (EXTI_ADTE_GPIO0_MSK)); +} + +/** + * @brief Enable ADC trigger on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK); +} + +/** + * @brief Disable ADC trigger on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK); +} + +/** + * @brief Check if ADC trigger on line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK) == (EXTI_ADTE_GPIO1_MSK)); +} + +/** + * @brief Enable ADC trigger on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK); +} + +/** + * @brief Disable ADC trigger on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK); +} + +/** + * @brief Check if ADC trigger on line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK) == (EXTI_ADTE_GPIO2_MSK)); +} + +/** + * @brief Enable ADC trigger on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK); +} + +/** + * @brief Disable ADC trigger on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK); +} + +/** + * @brief Check if ADC trigger on line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK) == (EXTI_ADTE_GPIO3_MSK)); +} + +/** + * @brief Enable ADC trigger on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK); +} + +/** + * @brief Disable ADC trigger on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK); +} + +/** + * @brief Check if ADC trigger on line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK) == (EXTI_ADTE_GPIO4_MSK)); +} + +/** + * @brief Enable ADC trigger on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK); +} + +/** + * @brief Disable ADC trigger on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK); +} + +/** + * @brief Check if ADC trigger on line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK) == (EXTI_ADTE_GPIO5_MSK)); +} + +/** + * @brief Enable ADC trigger on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK); +} + +/** + * @brief Disable ADC trigger on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK); +} + +/** + * @brief Check if ADC trigger on line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK) == (EXTI_ADTE_GPIO6_MSK)); +} + +/** + * @brief Enable ADC trigger on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK); +} + +/** + * @brief Disable ADC trigger on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK); +} + +/** + * @brief Check if ADC trigger on line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK) == (EXTI_ADTE_GPIO7_MSK)); +} + +/** + * @brief Enable ADC trigger on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK); +} + +/** + * @brief Disable ADC trigger on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK); +} + +/** + * @brief Check if ADC trigger on line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK) == (EXTI_ADTE_GPIO8_MSK)); +} + +/** + * @brief Enable ADC trigger on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK); +} + +/** + * @brief Disable ADC trigger on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK); +} + +/** + * @brief Check if ADC trigger on line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK) == (EXTI_ADTE_GPIO9_MSK)); +} + +/** + * @brief Enable ADC trigger on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK); +} + +/** + * @brief Disable ADC trigger on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK); +} + +/** + * @brief Check if ADC trigger on line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK) == (EXTI_ADTE_GPIO10_MSK)); +} + +/** + * @brief Enable ADC trigger on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK); +} + +/** + * @brief Disable ADC trigger on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK); +} + +/** + * @brief Check if ADC trigger on line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK) == (EXTI_ADTE_GPIO11_MSK)); +} + +/** + * @brief Enable ADC trigger on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK); +} + +/** + * @brief Disable ADC trigger on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK); +} + +/** + * @brief Check if ADC trigger on line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK) == (EXTI_ADTE_GPIO12_MSK)); +} + +/** + * @brief Enable ADC trigger on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK); +} + +/** + * @brief Disable ADC trigger on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK); +} + +/** + * @brief Check if ADC trigger on line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK) == (EXTI_ADTE_GPIO13_MSK)); +} + +/** + * @brief Enable ADC trigger on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK); +} + +/** + * @brief Disable ADC trigger on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK); +} + +/** + * @brief Check if ADC trigger on line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK) == (EXTI_ADTE_GPIO14_MSK)); +} + +/** + * @brief Enable ADC trigger on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK); +} + +/** + * @brief Disable ADC trigger on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK); +} + +/** + * @brief Check if ADC trigger on line is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK) == (EXTI_ADTE_GPIO15_MSK)); +} + +/** + * @brief Enable ADC trigger on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK); +} + +/** + * @brief Disable ADC trigger on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK); +} + +/** + * @brief Check if ADC trigger on line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK) == (EXTI_ADTE_CMP1_MSK)); +} + +/** + * @brief Enable ADC trigger on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK); +} + +/** + * @brief Disable ADC trigger on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK); +} + +/** + * @brief Check if ADC trigger on line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK) == (EXTI_ADTE_CMP2_MSK)); +} + +/** + * @brief Enable ADC trigger on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK); +} + +/** + * @brief Disable ADC trigger on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK); +} + +/** + * @brief Check if ADC trigger on line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK) == (EXTI_ADTE_PVD0_MSK)); +} + +/** + * @brief Enable ADC trigger on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK); +} + +/** + * @brief Disable ADC trigger on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK); +} + +/** + * @brief Check if ADC trigger on line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK) == (EXTI_ADTE_WAKEUP_MSK)); +} + + +/** + * @} MD_EXTI_PF_ADTE + */ + +/** @defgroup MD_EXTI_PF_INTERRUNPT_MANAGEMENT EXTI Interrupt Management + * @{ + */ + +/** @defgroup MD_EXTI_PF_IER EXTI Interrupt Enable Register + * @{ + */ + + +/** + * @brief Set interrupt enable on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IER + * @retval None + */ +__STATIC_INLINE void md_spi_set_exti_ier(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->IER, value); +} + +/** + * @brief Enable interrupt on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO0_MSK); +} + +/** + * @brief Enable interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO1_MSK); +} + +/** + * @brief Enable interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO2_MSK); +} + +/** + * @brief Enable interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO3_MSK); +} + +/** + * @brief Enable interrupt on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO4_MSK); +} + +/** + * @brief Enable interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO5_MSK); +} + +/** + * @brief Enable interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO6_MSK); +} + +/** + * @brief Enable interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO7_MSK); +} + +/** + * @brief Enable interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO8_MSK); +} + +/** + * @brief Enable interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO9_MSK); +} + +/** + * @brief Enable interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO10_MSK); +} + +/** + * @brief Enable interrupt on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO11_MSK); +} + +/** + * @brief Enable interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO12_MSK); +} + +/** + * @brief Enable interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO13_MSK); +} + +/** + * @brief Enable interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO14_MSK); +} + +/** + * @brief Enable interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO15_MSK); +} + + +/** + * @brief Enable interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_CMP1_MSK); +} + +/** + * @brief Enable interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_CMP2_MSK); +} + +/** + * @brief Enable interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_PVD0_MSK); +} + +/** + * @brief Enable interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_WAKEUP_MSK); +} + +/** + * @} MD_EXTI_PF_IER + */ + +/** @defgroup MD_EXTI_PF_IDR EXTI Interrupt Disable Register + * @{ + */ + +/** + * @brief Disable interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IDR + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->IDR, value); +} + + +/** + * @brief Disable interrupt on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO0_MSK); +} + +/** + * @brief Disable interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO1_MSK); +} + +/** + * @brief Disable interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO2_MSK); +} + +/** + * @brief Disable interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO3_MSK); +} + +/** + * @brief Disable interrupt on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO4_MSK); +} + +/** + * @brief Disable interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO5_MSK); +} + +/** + * @brief Disable interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO6_MSK); +} + +/** + * @brief Disable interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO7_MSK); +} + +/** + * @brief Disable interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO8_MSK); +} + +/** + * @brief Disable interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO9_MSK); +} + +/** + * @brief Disable interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO10_MSK); +} + +/** + * @brief Disable interrupt on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO11_MSK); +} + +/** + * @brief Disable interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO12_MSK); +} + +/** + * @brief Disable interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO13_MSK); +} + +/** + * @brief Disable interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->IDR, EXTI_IDR_GPIO14_MSK); +} + +/** + * @brief Disable interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO15_MSK); +} + +/** + * @brief Disable interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->IDR, EXTI_IDR_CMP1_MSK); +} + +/** + * @brief Disable interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_CMP2_MSK); +} + +/** + * @brief Disable interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_PVD0_MSK); +} + +/** + * @brief Disable interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_WAKEUP_MSK); +} + + +/** + * @} MD_EXTI_PF_IDR + */ + +/** @defgroup MD_EXTI_PF_ICR EXTI Interrupt Clear Register + * @{ + */ + +/** + * @brief Interrupt Clear on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ICR + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICR, value); +} + +/** + * @brief Interrupt Clear on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO0_MSK); +} + +/** + * @brief Interrupt Clear on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO1_MSK); +} + +/** + * @brief Interrupt Clear on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO2_MSK); +} + +/** + * @brief Interrupt Clear on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO3_MSK); +} + +/** + * @brief Interrupt Clear on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO4_MSK); +} + +/** + * @brief Interrupt Clear on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO5_MSK); +} + +/** + * @brief Interrupt Clear on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO6_MSK); +} + +/** + * @brief Interrupt Clear on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO7_MSK); +} + +/** + * @brief Interrupt Clear on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO8_MSK); +} + +/** + * @brief Interrupt Clear on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO9_MSK); +} + +/** + * @brief Interrupt Clear on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO10_MSK); +} + +/** + * @brief Interrupt Clear on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO11_MSK); +} + +/** + * @brief Interrupt Clear on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO12_MSK); +} + +/** + * @brief Interrupt Clear on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO13_MSK); +} + +/** + * @brief Interrupt Clear on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO14_MSK); +} + +/** + * @brief Interrupt Clear on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO15_MSK); +} + + +/** + * @brief Interrupt Clear on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_CMP1_MSK); +} + +/** + * @brief Interrupt Clear on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_CMP2_MSK); +} + + +/** + * @brief Interrupt Clear on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_PVD0_MSK); +} + +/** + * @brief Interrupt Clear on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_WAKEUP_MSK); +} + +/** + * @} MD_EXTI_PF_ICR + */ + +/** @defgroup MD_EXTI_PF_IVS EXTI Interrupt Valid Status Register + * @{ + */ + +/** + * @brief Interrupt Valid Status on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IVS + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs(EXTI_TypeDef *exti, uint32_t value) +{ + return (READ_REG(exti->IVS)); +} + +/** + * @brief Interrupt Valid Status on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO0_MSK) == EXTI_IVS_GPIO0_POS); +} + +/** + * @brief Interrupt Valid Status on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO1_MSK) == EXTI_IVS_GPIO1_POS); +} + +/** + * @brief Interrupt Valid Status on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO2_MSK) == EXTI_IVS_GPIO2_POS); +} + +/** + * @brief Interrupt Valid Status on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO3_MSK) == EXTI_IVS_GPIO3_POS); +} + +/** + * @brief Interrupt Valid Status on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO4_MSK) == EXTI_IVS_GPIO4_POS); +} + +/** + * @brief Interrupt Valid Status on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO5_MSK)>>EXTI_IVS_GPIO5_POS); +} + +/** + * @brief Interrupt Valid Status on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO6_MSK) == EXTI_IVS_GPIO6_POS); +} + +/** + * @brief Interrupt Valid Status on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO7_MSK) == EXTI_IVS_GPIO7_POS); +} + +/** + * @brief Interrupt Valid Status on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO8_MSK) == EXTI_IVS_GPIO8_POS); +} + +/** + * @brief Interrupt Valid Status on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO9_MSK) == EXTI_IVS_GPIO9_POS); +} + +/** + * @brief Interrupt Valid Status on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO10_MSK) == EXTI_IVS_GPIO10_POS); +} + +/** + * @brief Interrupt Valid Status on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO11_MSK) == EXTI_IVS_GPIO11_POS); +} + +/** + * @brief Interrupt Valid Status on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO12_MSK) == EXTI_IVS_GPIO12_POS); +} + +/** + * @brief Interrupt Valid Status on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO13_MSK) == EXTI_IVS_GPIO13_POS); +} + +/** + * @brief Interrupt Valid Status on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO14_MSK) == EXTI_IVS_GPIO14_POS); +} + +/** + * @brief Interrupt Valid Status on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO15_MSK) == EXTI_IVS_GPIO15_POS); +} + +/** + * @brief Interrupt Valid Status on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_CMP1_MSK) == EXTI_IVS_CMP1_POS); +} + +/** + * @brief Interrupt Valid Status on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_CMP2_MSK) == EXTI_IVS_CMP2_POS); +} + + +/** + * @brief Interrupt Valid Status on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_PVD0_MSK) == EXTI_IVS_PVD0_POS); +} + +/** + * @brief Interrupt Valid Status on line 21 + * @param exti EXTI Instance + * @retval None + */ + +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_WAKEUP_MSK) == EXTI_IVS_WAKEUP_POS); +} + + +/** + * @} MD_EXTI_PF_IVS + */ + +/** @defgroup MD_EXTI_PF_IFM EXTI Interrupt Flag Masked Status Register + * @{ + */ + +/** + * @brief Check if Interrupt Flag Masked Status on line is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->IFM)); +} + + +/** + * @brief Check if Interrupt Flag Masked Status on line 0 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO0_MSK) == EXTI_IFM_GPIO0_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 1 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO1_MSK) == EXTI_IFM_GPIO1_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 2 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO2_MSK) == EXTI_IFM_GPIO2_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 3 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio3(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO3_MSK) == EXTI_IFM_GPIO3_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 4 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio4(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO4_MSK) == EXTI_IFM_GPIO4_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 5 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio5(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO5_MSK) == EXTI_IFM_GPIO5_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 6 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio6(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO6_MSK) == EXTI_IFM_GPIO6_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 7 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO7_MSK) == EXTI_IFM_GPIO7_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 8 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio8(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO8_MSK) == EXTI_IFM_GPIO8_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 9 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio9(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO9_MSK) == EXTI_IFM_GPIO9_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 10 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio10(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO10_MSK) == EXTI_IFM_GPIO10_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 11 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio11(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO11_MSK) == EXTI_IFM_GPIO11_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 12 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio12(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO12_MSK) == EXTI_IFM_GPIO12_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 13 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio13(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO13_MSK) == EXTI_IFM_GPIO13_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 14 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio14(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO14_MSK) == EXTI_IFM_GPIO14_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 15 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO15_MSK) == EXTI_IFM_GPIO15_POS); +} + + +/** + * @brief Check if Interrupt Flag Masked Status on line 16 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_cmp1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_CMP1_MSK) == EXTI_IFM_CMP1_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 17 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_cmp2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_CMP2_MSK) == EXTI_IFM_CMP2_POS); +} + + +/** + * @brief Check if Interrupt Flag Masked Status on line 20 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_pvd0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_PVD0_MSK) == EXTI_IFM_PVD0_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 21 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_WAKEUP(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_WAKEUP_MSK) == EXTI_IFM_WAKEUP_POS); +} + +/** + * @} MD_EXTI_PF_IFM + */ + +/** @defgroup MD_EXTI_PF_RIF EXTI Raw Interrupt Flag Status Register + * @{ + */ + + +/** + * @brief Check if Raw interrupt flag Status on line is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->RIF)); +} + + +/** + * @brief Check if Raw interrupt flag Status on line 0 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO0_MSK) == EXTI_RIF_GPIO0_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 1 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO1_MSK) == EXTI_RIF_GPIO1_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 2 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO2_MSK) == EXTI_RIF_GPIO2_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 3 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio3(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO3_MSK) == EXTI_RIF_GPIO3_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 4 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio4(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO4_MSK) == EXTI_RIF_GPIO4_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 5 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio5(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO5_MSK) == EXTI_RIF_GPIO5_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 6 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio6(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO6_MSK) == EXTI_RIF_GPIO6_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 7 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO7_MSK) == EXTI_RIF_GPIO7_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 8 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio8(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO8_MSK) == EXTI_RIF_GPIO8_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 9 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio9(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO9_MSK) == EXTI_RIF_GPIO9_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 10 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio10(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO10_MSK) == EXTI_RIF_GPIO10_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 11 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio11(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO11_MSK) == EXTI_RIF_GPIO11_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 12 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio12(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO12_MSK) == EXTI_RIF_GPIO12_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 13 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio13(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO13_MSK) == EXTI_RIF_GPIO13_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 14 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio14(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO14_MSK) == EXTI_RIF_GPIO14_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 15 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO15_MSK) == EXTI_RIF_GPIO15_POS); +} + + +/** + * @brief Check if Raw interrupt flag Status on line 16 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_cmp1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_CMP1_MSK) == EXTI_RIF_CMP1_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 17 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_cmp2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_CMP2_MSK) == EXTI_RIF_CMP2_POS); +} + + +/** + * @brief Check if Raw interrupt flag Status on line 20 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_pvd0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_PVD0_MSK) == EXTI_RIF_PVD0_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 21 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_WAKEUP(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_WAKEUP_MSK) == EXTI_RIF_WAKEUP_POS); +} + + +/** + * @} MD_EXTI_PF_RIF + */ + + + + +/** + * @} MD_EXTI_PF_INTERRUNPT_MANAGEMENT + */ + + + + + + +/** @defgroup MD_EXTI_PF_DEBOUNCE_SETTING EXTI Debounce Management + * @{ + */ +/** + * @brief Set debounce enable bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->DB + * @retval None + */ +__STATIC_INLINE void md_spi_set_exti_db(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->DB, value); +} + +/** + * @brief Get debounce enable bit of line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_exti_db(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->DB)); +} + +/** + * @brief Enable debounce enable bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO0_MSK); +} + +/** + * @brief Disable debounce enable bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO0_MSK); +} + +/** + * @brief Check if debounce enable bit of line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO0_MSK) == (EXTI_DB_GPIO0_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO1_MSK); +} + +/** + * @brief Disable debounce enable bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO1_MSK); +} + +/** + * @brief Check if debounce enable bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO1_MSK) == (EXTI_DB_GPIO1_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO2_MSK); +} + +/** + * @brief Disable debounce enable bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO2_MSK); +} + +/** + * @brief Check if debounce enable bit of line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO2_MSK) == (EXTI_DB_GPIO2_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO3_MSK); +} + +/** + * @brief Disable debounce enable bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO3_MSK); +} + +/** + * @brief Check if debounce enable bit of line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO3_MSK) == (EXTI_DB_GPIO3_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO4_MSK); +} + +/** + * @brief Disable debounce enable bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO4_MSK); +} + +/** + * @brief Check if debounce enable bit of line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO4_MSK) == (EXTI_DB_GPIO4_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO5_MSK); +} + +/** + * @brief Disable debounce enable bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO5_MSK); +} + +/** + * @brief Check if debounce enable bit of line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO5_MSK) == (EXTI_DB_GPIO5_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO6_MSK); +} + +/** + * @brief Disable debounce enable bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO6_MSK); +} + +/** + * @brief Check if debounce enable bit of line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO6_MSK) == (EXTI_DB_GPIO6_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO7_MSK); +} + +/** + * @brief Disable debounce enable bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO7_MSK); +} + +/** + * @brief Check if debounce enable bit of line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO7_MSK) == (EXTI_DB_GPIO7_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO8_MSK); +} + +/** + * @brief Disable debounce enable bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO1_MSK); +} + +/** + * @brief Check if debounce enable bit of line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO8_MSK) == (EXTI_DB_GPIO8_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO9_MSK); +} + +/** + * @brief Disable debounce enable bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO9_MSK); +} + +/** + * @brief Check if debounce enable bit of line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO9_MSK) == (EXTI_DB_GPIO9_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO10_MSK); +} + +/** + * @brief Disable debounce enable bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO10_MSK); +} + +/** + * @brief Check if debounce enable bit of line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO10_MSK) == (EXTI_DB_GPIO10_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO11_MSK); +} + +/** + * @brief Disable debounce enable bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO11_MSK); +} + +/** + * @brief Check if debounce enable bit of line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO11_MSK) == (EXTI_DB_GPIO11_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO12_MSK); +} + +/** + * @brief Disable debounce enable bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO12_MSK); +} + +/** + * @brief Check if debounce enable bit of line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO12_MSK) == (EXTI_DB_GPIO12_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO13_MSK); +} + +/** + * @brief Disable debounce enable bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO13_MSK); +} + +/** + * @brief Check if debounce enable bit of line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO13_MSK) == (EXTI_DB_GPIO13_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO14_MSK); +} + +/** + * @brief Disable debounce enable bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO14_MSK); +} + +/** + * @brief Check if debounce enable bit of line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO14_MSK) == (EXTI_DB_GPIO14_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO15_MSK); +} + +/** + * @brief Disable debounce enable bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO15_MSK); +} + +/** + * @brief Check if debounce enable bit of line 15 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO15_MSK) == (EXTI_DB_GPIO15_MSK)); +} + + +/** + * @brief Enable debounce enable bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_CMP1_MSK); +} + +/** + * @brief Disable debounce enable bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_CMP1_MSK); +} + +/** + * @brief Check if debounce enable bit of line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_CMP1_MSK) == (EXTI_DB_CMP1_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_CMP2_MSK); +} + +/** + * @brief Disable debounce enable bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_CMP2_MSK); +} + +/** + * @brief Check if debounce enable bit of line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_CMP2_MSK) == (EXTI_DB_CMP2_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_PVD0_MSK); +} + +/** + * @brief Disable debounce enable bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_PVD0_MSK); +} + +/** + * @brief Check if debounce enable bit of line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_PVD0_MSK) == (EXTI_DB_PVD0_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_WAKEUP_MSK); +} + +/** + * @brief Disable debounce enable bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_WAKEUP_MSK); +} + +/** + * @brief Check if debounce enable bit of line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_WAKEUP_MSK) == (EXTI_DB_WAKEUP_MSK)); +} + +/** + * @brief Set Debounce counter + * @param exti EXTI Port + * @param dbcnt This bit can be one of following valus: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_exti_set_dbcon_dbcnt(EXTI_TypeDef *exti, uint32_t dbcnt) +{ + MODIFY_REG(exti->DBCON, EXTI_DBCON_DBCNT_MSK, (dbcnt<DBCON, EXTI_DBCON_DBCNT_MSK)>>EXTI_DBCON_DBCNT_POSS); +} + +/** + * @brief Set Debounce prescale + * @param exti EXTI Port + * @param prescale This bit can be one of following valus: + * @arg Max Value 255 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_exti_set_dbcon_dbpre(EXTI_TypeDef *exti, uint32_t prescale) +{ + MODIFY_REG(exti->DBCON, EXTI_DBCON_DBPRE_MSK, (prescale<DBCON, EXTI_DBCON_DBPRE_MSK)>>EXTI_DBCON_DBPRE_POSS); +} + + +/** + * @} MD_EXTI_PF_DEBOUNCE_SETTING + */ + + + + + + +/** + * @} MD_EXTI_Public_Macros + */ + + + + +/* Public functions -----------------------------------------------------------*/ + + + +/** + * @} EXTI + */ + +#endif + + + +/** + * @} Micro_Driver + */ + +#endif + +#ifdef __cplusplus +} +#endif + + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h new file mode 100644 index 0000000000000000000000000000000000000000..a7d85653bd8bc9dfdb0e60da6820ec53b67d19ce --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h @@ -0,0 +1,832 @@ +/** + ****************************************************************************** + * @file md_FC.h + * @brief ES32F0271 FC HEAD File. + * + * @version V1.00.01 + * @date 11/20/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_FC_H__ +#define __MD_FC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_fc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (FC) + +/** @defgroup FC FC + * @brief FC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Types FC Public Types + * @{ + */ + +/** + * @brief MD FC Parameter Structure definition + */ +typedef struct +{ + uint32_t SAddr; /*!< Specifies the FC sector address to be erased. + This parameter should be aligned with 0x400*/ + + uint32_t SAddrC; /*!< Specifies the complement of FC sector address to be erased. + This parameter should be the complement of FC page address*/ + + uint16_t BCnt; /*!< Specifies the control byte count. + For program, this parameter should be aligned with 8 and smaller than 0x400 + For read, this parameter should be aligned with 4*/ + + uint32_t *pU32Buf; /*!< Specifies the uint32_t data buffer to program. + This parameter should be the pointer to uint32_t*/ + +} md_fc_ControlTypeDef; + +/** + * @brief MD FC Update Protect Level Structure definition + */ +typedef struct +{ + uint32_t UpdateL; /*!< Specifies the protect page bit mapping low byte (page 31~0) (0=protect, 1=unprotect). + This parameter can be any value between 0~65535*/ + + uint32_t UpdateH; /*!< Specifies the protect page bit mapping high byte (page 63~32) (0=protect, 1=unprotect). + This parameter can be any value between 0~65535*/ + + uint32_t ClearL; /*!< Specifies the reserve page bit mapping low byte (page 31~0) (0=reserve, 1=erase). + This parameter can be any value between 0~65535*/ + + uint32_t ClearH; /*!< Specifies the reserve page bit mapping high byte (page 63~32) (0=reserve, 1=erase). + This parameter can be any value between 0~65535*/ + +} md_fc_UpdProtTypeDef; + +/** + * @} MD_FC_Public_Types + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Constants FC Public Constants + * @{ + */ + +#define MD_FC_PC_EF_MPAGESZ (0x00000400UL) /** @brief Select main page size */ +#define MD_FC_PC_EF_IPAGESZ (0x00000400UL) /** @brief Select information page size */ +#define MD_FC_PC_EF_MERASEID (0xA5A5AA55UL) /** @brief Select main erase ID */ + +#define MD_FC_PC_CMD_PROG_EFLASH (0xF0) /** @brief Program EFlash */ +#define MD_FC_PC_CMD_SECTOR_ERASE (0xF1) /** @brief Sector Erase */ +#define MD_FC_PC_CMD_MACRO_ERASE (0xF2) /** @brief Macro Erase */ +#define MD_FC_PC_CMD_UPDATE_LV1_PROTECT (0xF3) /** @brief Update Lv1 Protect */ +#define MD_FC_PC_CMD_UPDATE_LV2_PROTECT (0xF4) /** @brief Update Lv2 Protect */ +#define MD_FC_PC_CMD_OPTION_BYTE_ERASE (0xF5) /** @brief Option Byte Erase(Only for ISP) */ + +#define MD_FC_PC_SREMAP_MAIN (0x00) /** @brief Main Flash memory mapped at 0x0000 0000 */ +#define MD_FC_PC_SREMAP_SYSTEM (0x01) /** @brief System Flash memory mapped at 0x0000 0000 */ +#define MD_FC_PC_SREMAP_SRAM (0x02) /** @brief SRAM mapped at 0x0000 0000 */ + +/** + * @} MD_FC_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Macros FC Public Macros + * @{ + */ + +/** @defgroup MD_FC_PM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_FC_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define MD_FC_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @brief Modify value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be written in the register + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_FC_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +/** + * @brief Set bit value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be set in the register + * @retval None + */ +#define MD_FC_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Clear bit value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be cleared in the register + * @retval None + */ +#define MD_FC_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Read bit value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be read in the register + * @retval Register bit value + */ +#define MD_FC_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @} MD_FC_PM_WRITE_READ + */ + +/** @defgroup MD_FC_Macro_Drivers FC Public Macro Drivers + * @{ + */ + +/** + * @brief Set FC CMD + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_cmd(uint32_t U32) +{ + MD_FC_WRITEREG(FC, CMD, U32); +} + +/** + * @brief Get FC CMD + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_cmd(void) +{ + return (MD_FC_READREG(FC, CMD)); +} + +/** + * @brief Set FC CMD Flash Command + * @note After procedure is finished, Flash command will be cleaned by itself + * @param @arg @ref MD_FC_PC_CMD_PROG_EFLASH(0xF0) : Program EFlash + * @arg @ref MD_FC_PC_CMD_SECTOR_ERASE(0xF1) : Sector Erase + * @arg @ref MD_FC_PC_CMD_MACRO_ERASE(0xF2) : Macro Erase + * @arg @ref MD_FC_PC_CMD_UPDATE_LV1_PROTECT(0xF3) : Update Lv1 Protect + * @arg @ref MD_FC_PC_CMD_UPDATE_LV2_PROTECT(0xF4) : Update Lv2 Protect + * @arg @ref MD_FC_PC_CMD_OPTION_BYTE_ERASE(0xF5) : Option Byte Erase(Only for ISP) + * @arg Else : Reserved + * @retval None + */ +__STATIC_INLINE void md_fc_set_fc_cmd(uint32_t Cmd) +{ + MD_FC_MODIFYREG(FC, CMD, FC_CMD_FC_CMD_MSK, (Cmd<>FC_CMD_FC_CMD_POSS); +} + +/** + * @brief Set FC PA + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa(uint32_t U32) +{ + MD_FC_WRITEREG(FC, PA, U32); +} + +/** + * @brief Get FC PA + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_pa(void) +{ + return (MD_FC_READREG(FC, PA)); +} + +/** + * @brief Set FC Program Counter + * @note Provide maximum 128 times continuous program + * @note Meanwhile user needs to fill out FC_PLD, FC_PHD and FC_CMD only + * @param @arg Max Value 0x7f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa_pcnt(uint32_t PCnt) +{ + MD_FC_MODIFYREG(FC, PA, FC_PA_PCNT_MSK, (((PCnt>>3)-1)<>FC_PA_PCNT_POSS); +} + +/** + * @brief Enable FC Information Block + * @note User can program/erase Info. Block page 7 when Flash protect is disable + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_enable_pa_ifren(void) +{ + MD_FC_SET_BIT(FC, PA, FC_PA_IFREN_MSK); +} + +/** + * @brief Disable FC Information Block + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_disble_pa_ifren(void) +{ + MD_FC_CLEAR_BIT(FC, PA, FC_PA_IFREN_MSK); +} + +/** + * @brief Is FC Information Block Enabled + * @param None + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_pa_ifren(void) +{ + return (MD_FC_READBIT(FC, PA, FC_PA_IFREN_MSK)>>FC_PA_IFREN_POS); +} + +/** + * @brief Set FC Program/Erase Address + * @note Program : PROG_ADDR[15:3] is double word address + * @note Sector Erase : PROG_ADDR[15:10] is page address, and PROG_ADDR[9:0] dont care + * @note Macro Erase : PROG_ADDR[15:0] dont care + * @param @arg Max Value 0xffc0 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa_prog_addr(uint32_t PAddr) +{ + MD_FC_MODIFYREG(FC, PA, FC_PA_PROG_ADDR_MSK, (PAddr<>FC_PA_PROG_ADDR_POSS); +} + +/** + * @brief Set FC Program Low Data + * @note Eflash supports 64 bits data program, this register provides Low 32 bits data + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pld(uint32_t U32) +{ + MD_FC_WRITEREG(FC, PLD, U32); +} + +/** + * @brief Get FC Program Low Data + * @note Eflash supports 64 bits data program, this register provides Low 32 bits data + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_pld(void) +{ + return (MD_FC_READREG(FC, PLD)); +} + +/** + * @brief Set FC Program High Data + * @note Eflash supports 64 bits data program, this register provides high 32 bits data + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_phd(uint32_t U32) +{ + MD_FC_WRITEREG(FC, PHD, U32); +} + +/** + * @brief Get FC Program High Data + * @note Eflash supports 64 bits data program, this register provides high 32 bits data + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_phd(void) +{ + return (MD_FC_READREG(FC, PHD)); +} + +/** + * @brief Set FC CON + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_con(uint32_t U32) +{ + MD_FC_WRITEREG(FC, CON, U32); +} + +/** + * @brief Get FC CON + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_con(void) +{ + return (MD_FC_READREG(FC, CON)); +} + +/** + * @brief Enable FC Control Sleep + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_enable_con_sleep(void) +{ + MD_FC_SET_BIT(FC, CON, FC_CON_SLEEP_MSK); +} + +/** + * @brief Disable FC Control Sleep + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_disable_con_sleep(void) +{ + MD_FC_CLEAR_BIT(FC, CON, FC_CON_SLEEP_MSK); +} + +/** + * @brief Is FC Control Sleep Enabled + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param None + * @retval The retval can be one of the following values: + * 0x0:Disable Flash sleep mask function + * 0x1:Enable Flash sleep mask function + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_con_sleep(void) +{ + return (MD_FC_READBIT(FC, CON, FC_CON_SLEEP_MSK)>>FC_CON_SLEEP_POS); +} + +/** + * @brief Enable FC Control PreFetch + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_enable_con_pfen(void) +{ + MD_FC_SET_BIT(FC, CON, FC_CON_PFEN_MSK); +} + +/** + * @brief Disable FC Control PreFetch + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_disable_con_pfen(void) +{ + MD_FC_CLEAR_BIT(FC, CON, FC_CON_PFEN_MSK); +} + +/** + * @brief Is FC Control PreFetch Enabled + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param None + * @retval The retval can be one of the following values: + * 0x0:Disable pre-fetch function + * 0x1:Enable pre-fetch function + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_con_pfen(void) +{ + return (MD_FC_READBIT(FC, CON, FC_CON_PFEN_MSK)>>FC_CON_PFEN_POS); +} + +/** + * @brief Set FC Control Wait Cycle + * @note Eflash supports 64 bits data program, this register provides high 32 bits data + * @param @arg Max Value 0x3 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_con_wait(uint32_t Wait) +{ + MD_FC_MODIFYREG(FC, CON, FC_CON_WAIT_MSK, (Wait<>FC_CON_WAIT_POSS); +} + +/** + * @brief Get FC STAT + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_sta(void) +{ + return (MD_FC_READREG(FC, STAT)); +} + +/** + * @brief Get FC Status Option Valid + * @note This bit is set when Option Byte Data is valid + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Option Byte Data is valid + * @arg Min Value 0x0 : Option Byte Data is invalid + */ +__STATIC_INLINE uint8_t md_fc_get_stat_opvd(void) +{ + return (MD_FC_READBIT(FC, STAT, FC_STAT_OPVD_MSK)>>FC_STAT_OPVD_POS); +} + +/** + * @brief Get FC Status Main Unprotect Level2 Status + * @note This bit is set when Flash main block is unprotect + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Lv2 Protect Function is disabled + * @arg Min Value 0x0 : Lv2 Protect Function is enabled + */ +__STATIC_INLINE uint8_t md_fc_get_stat_munp2(void) +{ + return (MD_FC_READBIT(FC, STAT, FC_STAT_MUNP2_MSK)>>FC_STAT_MUNP2_POS); +} + +/** + * @brief Get FC Status Main Unprotect Level1 Status + * @note This bit is set when Flash main block is unprotect + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Lv1 Protect Function is disabled + * @arg Min Value 0x0 : Lv1 Protect Function is enabled + */ +__STATIC_INLINE uint8_t md_fc_get_stat_munp1(void) +{ + return (MD_FC_READBIT(FC, STAT, FC_STAT_MUNP1_MSK)>>FC_STAT_MUNP1_POS); +} + +/** + * @brief Set FC Protect Update Low Data + * @note Update main block Lv2 Protect Page 0 ~ Page 31 + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_upl(uint32_t U32) +{ + MD_FC_WRITEREG(FC, UPL, U32); +} + +/** + * @brief Get FC Protect Update Low Data + * @note Update main block Lv2 Protect Page 0 ~ Page 31 + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_upl(void) +{ + return (MD_FC_READREG(FC, UPL)); +} + +/** + * @brief Set FC Protect Update High Data + * @note Update main block Lv2 Protect Page 63 ~ Page 32 + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_uph(uint32_t U32) +{ + MD_FC_WRITEREG(FC, UPH, U32); +} + +/** + * @brief Get FC Protect Update High Data + * @note Update main block Lv2 Protect Page 63 ~ Page 32 + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_uph(void) +{ + return (MD_FC_READREG(FC, UPH)); +} + +/** + * @brief Get FC OP_TRIM + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim(void) +{ + return (MD_FC_READREG(FC, OP_TRIM)); +} + +/** + * @brief Get FC OP_TRIM BangGap trim valid + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 BG Trim is Valid + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_bgtrimvd(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_BGTRIMVD_MSK)>>FC_OP_TRIM_BGTRIMVD_POSS); +} + +/** + * @brief Get FC Trim BangGap trim value + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_bgtrim(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_BGTRIM_MSK)>>FC_OP_TRIM_BGTRIM_POSS); +} + +/** + * @brief Get FC Trim HRC calibration value valid + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 BG Trim is Valid + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_hrctrimvd(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_HRCTRIMVD_MSK)>>FC_OP_TRIM_HRCTRIMVD_POSS); +} + +/** + * @brief Get FC Trim HRC calibration value + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_hrctrim(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_HRCTRIM_MSK)>>FC_OP_TRIM_HRCTRIM_POSS); +} + +/** + * @brief Get FC Lv2 Protect Low 32 bits + * @note Lv2 Protect Page 0 ~ Page 31.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt2l(void) +{ + return (MD_FC_READREG(FC, OP_PRT2L)); +} + +/** + * @brief Get FC Lv2 Protect High 32 bits + * @note Lv2 Protect Page 63 ~ Page 32.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt2h(void) +{ + return (MD_FC_READREG(FC, OP_PRT2H)); +} + +/** + * @brief Get FC Lv1 Protect Low 32 bits + * @note Lv1 Protect Page 0 ~ Page 31.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt1l(void) +{ + return (MD_FC_READREG(FC, OP_PRT1L)); +} + +/** + * @brief Get FC Lv1 Protect High 32 bits + * @note Lv1 Protect Page 63 ~ Page 32.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt1h(void) +{ + return (MD_FC_READREG(FC, OP_PRT1H)); +} + +/** + * @brief Get FC OP_REMAP + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_remap(void) +{ + return (MD_FC_READREG(FC, OP_REMAP)); +} + +/** + * @brief Get FC Hardware Remap Option + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 skip boot loader + */ +__STATIC_INLINE uint8_t md_fc_get_op_remap_hremap(void) +{ + return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_HREMAP_MSK)>>FC_OP_REMAP_HREMAP_POSS); +} + +/** + * @brief Get FC Software Remap Option + * @param None + * @retval The retval can be one of the following values: + * @arg @ref MD_FC_PC_SREMAP_MAIN(0x0) : Main Flash memory mapped at 0x0000 0000 + * @arg @ref MD_FC_PC_SREMAP_SYSTEM(0x1) : System Flash memory mapped at 0x0000 0000 + * @arg @ref MD_FC_PC_SREMAP_SRAM(0x2) : SRAM mapped at 0x0000 0000 + * @arg Else : Reserved + */ +__STATIC_INLINE uint8_t md_fc_get_op_remap_sremap(void) +{ + return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_SREMAP_MSK)>>FC_OP_REMAP_SREMAP_POSS); +} + +/** + * @brief Get FC Software Remap Base Address Settng Data + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + * @note This value is invalid if the value in SREMAP field is 0x3 + */ +__STATIC_INLINE uint8_t md_fc_get_op_remap_sefbase(void) +{ + return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_SEFBASE_MSK)>>FC_OP_REMAP_SEFBASE_POSS); +} + +/** + * @} MD_FC_Macro_Drivers + */ + +/** + * @} MD_FC_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Functions FC Public Functions + * @{ + */ +ErrorStatus md_fc_merase(uint32_t MEraseID); +ErrorStatus md_fc_serase(md_fc_ControlTypeDef *pSErasePara); +ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara); +ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara); +ErrorStatus md_fc_updprotl1(md_fc_UpdProtTypeDef *pUpdPL1Para); +ErrorStatus md_fc_updprotl2(md_fc_UpdProtTypeDef *pUpdPL2Para); +ErrorStatus md_fc_updremap(uint8_t UpdRemap); +/** + * @} MD_FC_Public_Functions + */ + +#endif + +/** + * @} FC + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..a096fa7a01a57bd0e1d249d4feb6a43fd9dc5a08 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h @@ -0,0 +1,2873 @@ +/** + ****************************************************************************** + * @file md_GPIO.h + * @brief ES32F0271 GPIO HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_GPIO_H__ +#define __MD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_gpio.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) + +/** @defgroup GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_GPIO_PT_INIT GPIO Public Init structures + * @{ + */ + +/** + * @brief MD GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref MD_GPIO_PC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_mode().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_OT. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_output_type().*/ + + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_pull().*/ + + uint32_t OutDrive; /*!< Specifies the output driving current for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_DS. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_get_ds().*/ + + uint32_t Function; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_FUNCTION. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_function0_7() and md_gpio_set_function8_15().*/ +} md_gpio_inittypedef; + +/** + * @} MD_GPIO_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_GPIO_Public_Constants GPIO Public Constants + * @{ + */ + +/** @defgroup MD_GPIO_PC_PIN PIN + * @{ + */ +#define MD_GPIO_PIN_0 (0X1<<0) /*!< Select pin 0 */ +#define MD_GPIO_PIN_1 (0X1<<1) /*!< Select pin 1 */ +#define MD_GPIO_PIN_2 (0X1<<2) /*!< Select pin 2 */ +#define MD_GPIO_PIN_3 (0X1<<3) /*!< Select pin 3 */ +#define MD_GPIO_PIN_4 (0X1<<4) /*!< Select pin 4 */ +#define MD_GPIO_PIN_5 (0X1<<5) /*!< Select pin 5 */ +#define MD_GPIO_PIN_6 (0X1<<6) /*!< Select pin 6 */ +#define MD_GPIO_PIN_7 (0X1<<7) /*!< Select pin 7 */ +#define MD_GPIO_PIN_8 (0X1<<8) /*!< Select pin 8 */ +#define MD_GPIO_PIN_9 (0X1<<9) /*!< Select pin 9 */ +#define MD_GPIO_PIN_10 (0X1<<10) /*!< Select pin 10 */ +#define MD_GPIO_PIN_11 (0X1<<11) /*!< Select pin 11 */ +#define MD_GPIO_PIN_12 (0X1<<12) /*!< Select pin 12 */ +#define MD_GPIO_PIN_13 (0X1<<13) /*!< Select pin 13 */ +#define MD_GPIO_PIN_14 (0X1<<14) /*!< Select pin 14 */ +#define MD_GPIO_PIN_15 (0X1<<15) /*!< Select pin 15 */ +#define MD_GPIO_PIN_ALL (MD_GPIO_PIN_0 | MD_GPIO_PIN_1 | MD_GPIO_PIN_2 | \ + MD_GPIO_PIN_3 | MD_GPIO_PIN_4 | MD_GPIO_PIN_5 | \ + MD_GPIO_PIN_6 | MD_GPIO_PIN_7 | MD_GPIO_PIN_8 | \ + MD_GPIO_PIN_9 | MD_GPIO_PIN_10 | MD_GPIO_PIN_11 | \ + MD_GPIO_PIN_12 | MD_GPIO_PIN_13 | MD_GPIO_PIN_14 | \ + MD_GPIO_PIN_15) /*!< Select all pins */ +/** + * @} MD_GPIO_PC_PIN + */ + +/** @defgroup MD_GPIO_PC_MODE Mode + * @{ + */ +#define MD_GPIO_MODE_INPUT (0x00000000UL) /** @brief Select input mode */ +#define MD_GPIO_MODE_OUTPUT (0X00000001UL) /** @brief Select output mode */ +#define MD_GPIO_MODE_FUNCTION (0X00000002UL) /** @brief Select function mode */ +#define MD_GPIO_MODE_ANALOG (0x00000003UL) /** @brief Select analog mode */ +/** + * @} MD_GPIO_PC_MODE + */ + +/** @defgroup MD_GPIO_PC_OT Output Type + * @{ + */ +#define MD_GPIO_OUTPUT_PUSHPULL (0x00000000U) /** @brief Select push-pull as output type */ +#define MD_GPIO_OUTPUT_OPENDRAIN (0x00000001U) /** @brief Select open-drain as output type */ +/** + * @} MD_GPIO_PC_OT + */ + +/** @defgroup MD_GPIO_PC_PULL Pull Up Pull Down + * @{ + */ +#define MD_GPIO_PULL_FLOATING (0x00000000UL) /** @brief Select I/O no pull */ +#define MD_GPIO_PULL_UP (0x00000001UL) /** @brief Select I/O pull up */ +#define MD_GPIO_PULL_DOWN (0x00000002UL) /** @brief Select I/O pull down */ +/** + * @} MD_GPIO_PC_PULL + */ + +/** @defgroup MD_GPIO_PC_DS Output driving/sinking current + * @{ + */ +#define MD_GPIO_DS_16mA (0x00000001U) /** @brief Select I/O 16mA driving/sinking current */ +#define MD_GPIO_DS_8mA (0x00000000U) /** @brief Select I/O 8mA driving/sinking current */ +/** + * @} MD_GPIO_PC_DS + */ + +/** @defgroup MD_GPIO_PC_FUNCTION Alternate Function + * @{ + */ +#define MD_GPIO_AF0 (0x00000000UL) /** @brief Select alternate function 0 */ +#define MD_GPIO_AF1 (0x00000001UL) /** @brief Select alternate function 1 */ +#define MD_GPIO_AF2 (0x00000002UL) /** @brief Select alternate function 2 */ +#define MD_GPIO_AF3 (0x00000003UL) /** @brief Select alternate function 3 */ +#define MD_GPIO_AF4 (0x00000004UL) /** @brief Select alternate function 4 */ +#define MD_GPIO_AF5 (0x00000005UL) /** @brief Select alternate function 5 */ +#define MD_GPIO_AF6 (0x00000006UL) /** @brief Select alternate function 6 */ +#define MD_GPIO_AF7 (0x00000007UL) /** @brief Select alternate function 7 */ +#define MD_GPIO_AF8 (0x00000008UL) /** @brief Select alternate function 8 */ +/** + * @} MD_GPIO_PC_FUNCTION + */ + +/** @defgroup MD_GPIO_PC_FILTER Input Filter + * @{ + */ +#define MD_GPIO_FILTER_BYPASS (0x00000000UL) /** @brief Select bypass */ +#define MD_GPIO_FILTER_GLITCH (0x00000001UL) /** @brief Select glitch free for 20ns plus */ +/** + * @} MD_GPIO_PC_FILTER + */ + +/** @defgroup MD_GPIO_PC_IST Input Schmitt Trigger + * @{ + */ +#define MD_GPIO_IST_TTL (0x00000000UL) /** @brief Select TTL IO Level */ +#define MD_GPIO_IST_CMOS (0x00000001UL) /** @brief Select CMOS IO Level */ +/** + * @} MD_GPIO_PC_IST + */ + +/** @defgroup MD_GPIO_ODATA_SEL GPIO Output Select + * @{ + */ +#define MD_GPIO_OUTPUT_LOW (0x00000000UL) /** @brief Select GPIO Output Low*/ +#define MD_GPIO_OUTPUT_HIGH (0x00000001UL) /** @brief Select GPIO Output High*/ +/** + * @} MD_GPIO_ODATA_SEL + */ + +/** + * @} MD_GPIO_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_GPIO_Public_Macros GPIO Public Macros + * @{ + */ + +/** @defgroup MD_GPIO_MOD_MOD15 MOD15 + * @brief Set MOD15 configure I/O mode bit for md_gpio_set_mod() function used + * @param mod15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + * @{ + */ +#define md_gpio_set_mod_mod15_fun(mod15) (mod15<MOD, (mod15|mod14|mod13|mod12|mod11|mod10|mod9|mod8|mod7|mod6|mod5|mod4|mod3|mod2|mod1|mod0)); +} + + + + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void md_gpio_set_mode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MOD, (GPIO_MOD_MOD0_MSK << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t md_gpio_get_mode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MOD, + (GPIO_MOD_MOD0_MSK << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** @defgroup MD_GPIO_OT_OT15 OT15 + * @brief Set OT15 output data bit for md_gpio_set_ot() function used + * @param ot15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + * @{ + */ +#define md_gpio_set_ot_ot15_fun(ot15) (ot15<OT, (ot15|ot14|ot13|ot12|ot11|ot10|ot9|ot8|ot7|ot6|ot5|ot4|ot3|ot2|ot1|ot0)); +} + + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @param GPIOx GPIO Port + * @param Pin This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param OutputType This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void md_gpio_set_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OT, (GPIO_OT_OT0_MSK << (POSITION_VAL(Pin))), (OutputType << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t md_gpio_get_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)((READ_BIT(GPIOx->OT, + (GPIO_OT_OT_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))) & (0x1U)); +} + + +/** @defgroup MD_GPIO_PUD_PUD15 PUD15 + * @brief Set PUD15 I/O pull-up or pull-down bit for md_gpio_set_pud() function used + * @param pud15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + * @{ + */ +#define md_gpio_set_pud_pud15_fun(pud15) (pud15<PUD, (pud15|pud14|pud13|pud12|pud11|pud10|pud9|pud8|pud7|pud6|pud5|pud4|pud3|pud2|pud1|pud0)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUD, (GPIO_PUD_PUD0_MSK << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t md_gpio_get_pull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUD, + (GPIO_PUD_PUD0_MSK << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + + +/** @defgroup MD_GPIO_DS_DS15 DS15 + * @brief Set DS15 I/O Driving/Sinking current bit for md_gpio_set_ds() function used + * @param ds15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_DS_8mA + * @arg @ref MD_GPIO_DS_16mA + * @{ + */ +#define md_gpio_set_ds_ds15_fun(ds15) (ds15<DS, (ds15|ds14|ds13|ds12|ds11|ds10|ds9|ds8|ds7|ds6|ds5|ds4|ds3|ds2|ds1|ds0)); +} + + +/** + * @brief Configure gpio output driving/sinking current a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Odrv This parameter can be one of the following values: + * @arg @ref MD_GPIO_DS_8mA + * @arg @ref MD_GPIO_DS_16mA + * @retval None + */ +__STATIC_INLINE void md_gpio_set_ds(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Odrv) +{ + MODIFY_REG(GPIOx->DS, (GPIO_DS_DS_MSK << (POSITION_VAL(Pin))), (Odrv << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return gpio output driving/sinking current a dedicated pin on a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_DS_8mA + * @arg @ref MD_GPIO_DS_16mA + */ +__STATIC_INLINE uint32_t md_gpio_get_ds(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DS, + (GPIO_DS_DS_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); +} + +/** @defgroup MD_GPIO_AFL_AF0 AF0 + * @brief Set AF0 Alternate function selection bit for md_gpio_set_afl() function used + * @param af0 This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @{ + */ +#define md_gpio_set_afl_af0_fun(af0) (af0<AFL, (af7|af6|af5|af4|af3|af2|af1|af0)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @param Function This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) +{ + MODIFY_REG(GPIOx->AFL, (GPIO_AFL_AF0_MSK << (POSITION_VAL(Pin) * 4U)), + (Function << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + */ +__STATIC_INLINE uint32_t md_gpio_get_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFL, + (GPIO_AFL_AF0_MSK << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + + +/** @defgroup MD_GPIO_AFH_AF8 AF8 + * @brief Set AF8 Alternate function selection bit for md_gpio_set_afh() function used + * @param af8 This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @{ + */ +#define md_gpio_set_afh_af8_fun(af8) (af8<AFH, (af15|af14|af13|af12|af11|af10|af9|af8)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Function This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) +{ + MODIFY_REG(GPIOx->AFH, (GPIO_AFH_AF8_MSK << (POSITION_VAL(Pin >> 8U) * 4U)), + (Function << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + */ +__STATIC_INLINE uint32_t md_gpio_get_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFH, + (GPIO_AFH_AF8_MSK << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note LOCK key write sequence: + * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] + * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_lock(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->LCK, PinMask); +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_gpio_get_lock(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCK, PinMask) == (PinMask)); +} + + + +/** @defgroup MD_GPIO_IST_IST15 IST15 + * @brief Set IST15 configure the input schmitt trigger level bit for md_gpio_set_ist_fun() function used + * @param ist15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + * @{ + */ +#define md_gpio_set_ist_ist15_fun(ist15) (ist15<IST, (ist15|ist14|ist13|ist12|ist11|ist10|ist9|ist8|ist7|ist6|ist5|ist4|ist3|ist2|ist1|ist0)); +} + +/** + * @brief Configure GPIOx port Input Schmitt Trigger Register. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Iolev This parameter can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + * @retval None + */ +__STATIC_INLINE void md_gpio_set_ist(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Iolev) +{ + MODIFY_REG(GPIOx->IST, (GPIO_IST_IST_MSK << (POSITION_VAL(Pin))), (Iolev << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return GPIOx port Input Schmitt Trigger Register + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval The retval can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + */ +__STATIC_INLINE uint32_t md_gpio_get_ist(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->IST, (GPIO_IST_IST_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); +} + +/** + * @brief Return full input data register value for a dedicated port. + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t md_gpio_get_input_port(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDATA)); +} + + + + +/** @defgroup MD_GPIO_ODATA_OD15 OD15 + * @brief Set OD15 set/reset bit for md_gpio_set_bsbr() function used + * @param od15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_LOW + * @arg @ref MD_GPIO_OUTPUT_HIGH + * @{ + */ +#define md_gpio_set_odata_od15_fun(od15) (od15<ODATA, (od15|od14|od13|od12|od11|od10|od9|od8|od7|od6|od5|od4|od3|od2|od1|od0)); +} + + + + + +/** + * @brief Write output data register for the port. + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void md_gpio_set_output_port(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODATA, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t md_gpio_get_output_port(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODATA)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_high(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSBR, PinMask); +} + +/** + * @brief Reset several pins to low level on dedicated gpio port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_low(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSBR, (PinMask << 16)); +} + + +/** @defgroup MD_GPIO_FIR_FIR15 FIR15 + * @brief Set FIR15 configure the input signal over thought a glitch filter bit for md_gpio_set_fir() function used + * @param fir15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_FILTER_BYPASS + * @arg @ref MD_GPIO_FILTER_GLITCH + * @{ + */ +#define md_gpio_set_fir_fir15_fun(fir15) (fir15<FIR, (fir15|fir14|fir13|fir12|fir11|fir10|fir9|fir8|fir7|fir6|fir5|fir4|fir3|fir2|fir1|fir0)); +} + + +/** + * @brief Write input filter register for the port. + * @note These bits are written by software to configure + * the input signal over thought a glitch filter. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_filter(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->FIR, PinMask); +} + +/** + * @brief Return full input filter data register value for a dedicated port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_gpio_get_filter(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->FIR, PinMask) == (PinMask)); +} + +/** + * @} MD_GPIO_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup MD_GPIO_PF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @} MD_GPIO_PF_Port_Configuration + */ + +/** @defgroup MD_GPIO_PF_Data_Access Data Access + * @{ + */ + +/** + * @} MD_GPIO_PF_Data_Access + */ + + +/** @defgroup MD_GPIO_PF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx); +ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct); +void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct); + +/** + * @} MD_GPIO_PF_Init + */ + +/** + * @} MD_GPIO_Public_Functions + */ + +#endif + +/** + * @} GPIO + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h new file mode 100644 index 0000000000000000000000000000000000000000..5baf2d5d2364f984ca854923a1d81e364b4f7dd5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h @@ -0,0 +1,292 @@ +/** + ****************************************************************************** + * @file md_HDIV.h + * @brief ES32F0271 HDIV HEAD File. + * + * @version V1.00.01 + * @date 11/20/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_HDIV_H__ +#define __MD_HDIV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_hdiv.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (HDIV) + +/** @defgroup HDIV HDIV + * @brief HDIV micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ + +/** + * @brief MD HDIV Parameter Structure definition + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_HDIV_Public_Constants HDIV Public Constants + * @{ + */ + +/** + * @} MD_HDIV_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_HDIV_Public_Macros HDIV Public Macros + * @{ + */ + +/** @defgroup MD_HDIV_PM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_HDIV_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define MD_HDIV_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @brief Modify value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be written in the register + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_HDIV_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +/** + * @brief Set bit value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be set in the register + * @retval None + */ +#define MD_HDIV_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Clear bit value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be cleased in the register + * @retval None + */ +#define MD_HDIV_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Read bit value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be read in the register + * @retval Register bit value + */ +#define MD_HDIV_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @} MD_HDIV_PM_WRITE_READ + */ + +/** @defgroup MD_HDIV_Macro_Drivers HDIV Public Macro Drivers + * @{ + */ + +/** + * @brief Set HDIV DIVDR + * @note This register is given the dividend of divider before calculation starting + * @note When this register is written, hardware divider will start calculate + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_hdiv_set_divdr(uint32_t U32) +{ + MD_HDIV_WRITEREG(HDIV, DIVDR, U32); +} + +/** + * @brief Get HDIV DIVIDEND + * @note This register is given the dividend of divider before calculation starting + * @note When this register is written, hardware divider will start calculate + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divdr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVDR)); +} + +/** + * @brief Set HDIV DIVSR + * @note This register is given the divisor of divider before calculation starts + * @note When this register is written, hardware divider will start calculate + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_hdiv_set_divsr(uint32_t U32) +{ + MD_HDIV_WRITEREG(HDIV, DIVSR, U32); +} + +/** + * @brief Get HDIV DIVSR + * @note This register is given the divisor of divider before calculation starts. + * @note When this register is written, hardware divider will start calculate + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divsr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVSR)); +} + +/** + * @brief Get HDIV DIVQR + * @note This register holds the quotient result of divider after calculation complete + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divqr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVQR)); +} + +/** + * @brief Get HDIV DIVRR + * @note This register holds the remainder result of divider after calculation complete + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divrr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVRR)); +} + +/** + * @brief Get HDIV DIVSTAT + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x7 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divstat(void) +{ + return (MD_HDIV_READREG(HDIV, DIVSTAT)); +} + +/** + * @brief Is HDIV DIVSTAT SIGN Active + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Signed + * @arg Min Value 0x0 : Unsigned + */ +__STATIC_INLINE uint8_t md_hdiv_get_divsts_sign(void) +{ + return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_SIGN_MSK)>>HDIV_DIVSTAT_SIGN_POS); +} + +/** + * @brief Is HDIV DIVSTAT DIV0 Active + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : The divisor is 0 + * @arg Min Value 0x0 : The divisor is not 0 + */ +__STATIC_INLINE uint8_t md_hdiv_get_divsts_div0(void) +{ + return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_DIV0_MSK)>>HDIV_DIVSTAT_DIV0_POS); +} + +/** + * @brief Is HDIV DIVSTAT BUSY Active + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : The divider is busy + * @arg Min Value 0x0 : The divider is not busy + */ +__STATIC_INLINE uint8_t md_hdiv_get_divsts_busy(void) +{ + return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_BUSY_MSK)>>HDIV_DIVSTAT_BUSY_POS); +} + +/** + * @} MD_HDIV_Macro_Drivers + */ + +/** + * @} MD_HDIV_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_HDIV_Public_Functions HDIV Public Functions + * @{ + */ + +/** + * @} MD_HDIV_Public_Functions + */ + +#endif + +/** + * @} HDIV + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..9f2e2ff964225944ae73df335e3e3691d58885c4 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h @@ -0,0 +1,3273 @@ +/** + ****************************************************************************** + * @file md_i2c.h + * @brief ES32F0271 I2C HEAD File. + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_I2C_H__ +#define __MD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_i2c.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (I2C1) | defined (I2C2) + +/** @defgroup I2C I2C + * @brief I2C micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + + +/* Public Init Structure ------------------------------------------------------*/ +/** @defgroup MD_I2C_PT_INIT I2C Public Init structure + * @brief I2C Init structure. + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section in Reference manual */ + + uint32_t Address1; /*!< Specifies the first device address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddrSize; /*!< Specifies the device address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t Address2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t Address2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ +} md_i2c_inittypedef; +/** + * @} MD_I2C_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_I2C_Public_Constants I2C Public Constants + * @{ + */ + +/** @defgroup MD_I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define MD_I2C_ADDRESSINGMODE_7BIT (0x00000000U) /*!< DISABLE */ +#define MD_I2C_ADDRESSINGMODE_10BIT (I2C_CON2_ADD10_MSK) /*!< I2C_CON2_ADD10_MSK = 1<<11 */ +/** + * @} MD_I2C_ADDRESSING_MODE + */ + +/** @defgroup MD_I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define MD_I2C_DUALADDRESS_DISABLE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_DUALADDRESS_ENABLE (I2C_ADDR2_OA2EN_MSK) /*!< I2C_ADDR2_OA2EN_MSK = 1<<15 */ +/** + * @} MD_I2C_DUAL_ADDRESSING_MODE + */ + +/** @defgroup MD_I2C_TIMING_CONFIG I2C Timing Config + * @note pllmul<<28|presc<<24|scll<<16|sclh<<8|sdadel<<4|scldel + * @{ + */ +/* pllmul presc scll sclh sdadel scldel */ +#define CLK10kHz8M (1<<28) |(1<<24) |(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 8MHz; CLK = 10kHz */ +#define CLK100kHz8M (1<<28) |(1<<24) |(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 8MHz; CLK = 100kHz */ +#define CLK400kHz8M (1<<28) |(0<<24) |(9<<16) |(3<<8) |(1<<4)|(3) /*!< APB = 8MHz; CLK = 400kHz */ +#define CLK500kHz8M (1<<28) |(0<<24) |(6<<16) |(3<<8) |(0<<4)|(1) /*!< APB = 8MHz; CLK = 500kHz */ +#define CLK10kHz16M (3<<28) |(3<<24) |(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 16MHz; CLK = 10kHz */ +#define CLK100kHz16M (3<<28) |(3<<24) |(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 16MHz; CLK = 100kHz */ +#define CLK400kHz16M (3<<28) |(1<<24) |(9<<16) |(3<<8) |(2<<4)|(3) /*!< APB = 16MHz; CLK = 400kHz */ +#define CLK1000kHz16M (3<<28) |(0<<24) |(4<<16) |(2<<8) |(0<<4)|(2) /*!< APB = 16MHz; CLK = 1000kHz */ +#define CLK10kHz48M (11U<<28)|(0xB<<24)|(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 48MHz; CLK = 10kHz */ +#define CLK100kHz48M (11U<<28)|(0xB<<24)|(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 48MHz; CLK = 100kHz */ +#define CLK400kHz48M (11U<<28)|(5<<24) |(9<<16) |(3<<8) |(3<<4)|(3) /*!< APB = 48MHz; CLK = 400kHz */ +#define CLK1000kHz48M (11U<<28)|(5<<24) |(3<<16) |(1<<8) |(0<<4)|(1) /*!< APB = 48MHz; CLK = 1000kHz */ +/** + * @} MD_I2C_TIMING_CONFIG + */ + +/** @defgroup MD_I2C_ADDRESS2_MASKS I2C Address2 Masks + * @{ + */ +#define MD_I2C_ADDR2_NOMASK (0x0000U) /*!< NOMASK */ +#define MD_I2C_ADDR2_MASK01 (0x0100U) /*!< MASK01 */ +#define MD_I2C_ADDR2_MASK02 (0x0200U) /*!< MASK02 */ +#define MD_I2C_ADDR2_MASK03 (0x0300U) /*!< MASK03 */ +#define MD_I2C_ADDR2_MASK04 (0x0400U) /*!< MASK04 */ +#define MD_I2C_ADDR2_MASK05 (0x0500U) /*!< MASK05 */ +#define MD_I2C_ADDR2_MASK06 (0x0600U) /*!< MASK06 */ +#define MD_I2C_ADDR2_MASK07 (0x0700U) /*!< MASK07 */ +/** + * @} MD_I2C_ADDRESS2_MASKS + */ + +/** @defgroup MD_I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define MD_I2C_GENERALCALL_DISABLE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_GENERALCALL_ENABLE (I2C_CON1_GCEN_MSK) /*!< I2C_CON1_GCEN_MSK = 1<<19 */ +/** + * @} MD_I2C_GENERAL_CALL_ADDRESSING_MODE + */ + +/** @defgroup MD_I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define MD_I2C_NOSTRETCH_DISABLE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_NOSTRETCH_ENABLE (I2C_CON1_NOSTRETCH_MSK) /*!< I2C_CON1_NOSTRETCH_MSK = 1<<17 */ +/** + * @} MD_I2C_NOSTRETCH_MODE + */ + +/** @defgroup MD_I2C_MODE I2C Mode + * @{ + */ +#define MD_I2C_MODE_NONE ((uint8_t)0x00U /*!< None */ +#define MD_I2C_MODE_MASTER ((uint8_t)0x10U) /*!< Master */ +#define MD_I2C_MODE_SLAVE ((uint8_t)0x20U) /*!< Slave */ +#define MD_I2C_MODE_MEM ((uint8_t)0x40U) /*!< Mem */ +/** + * @} MD_I2C_MODE + */ + +/** @defgroup MD_I2C_PECBYTE_ENABLE Pecbyte Enable + * @{ + */ +#define MD_I2C_PECBYTE_ENABLE I2C_CON2_PECBYTE_MSK /*!< I2C_CON2_PECBYTE_MSK = 1<<26 */ +/** + * @} MD_I2C_PECBYTE_ENABLE + */ + +/** @defgroup MD_I2C_AUTOEND_ENABLE I2C Autoend Enable + * @{ + */ +#define MD_I2C_SOFTEND_MODE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_AUTOEND_MODE (I2C_CON2_AUTOEND_MSK) /*!< I2C_CON2_AUTOEND_MSK = 1<<25 */ +/** + * @} MD_I2C_AUTOEND_ENABLE + */ + +/** @defgroup MD_I2C_RELOAD_MODE I2C Reload Mode + * @{ + */ +#define MD_I2C_NORELOAD_MODE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_RELOAD_MODE (I2C_CON2_RELOAD_MSK) /*!< I2C_CON2_RELOAD_MSK = 1<<24 */ +/** + * @} MD_I2C_RELOAD_MODE + */ + +/** @defgroup MD_I2C_NACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define MD_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define MD_I2C_NACK I2C_CON2_NACK_MSK /*!< NACK is sent after current received byte, I2C_CON2_NACK_MSK = 1<<15 */ +/** + * @} MD_I2C_NACKNOWLEDGE + */ + +/** @defgroup MD_I2C_STOP_GENERATION Stop Generation + * @{ + */ +#define MD_I2C_STOP_GENERATION I2C_CON2_STOP_MSK /*!< I2C_CON2_STOP_MSK = 1<<14 */ +/** + * @} MD_I2C_STOP_GENERATION + */ + +/** @defgroup MD_I2C_START_GENERATION Start Generation + * @{ + */ +#define MD_I2C_START_GENERATION I2C_CON2_START_MSK /*!< I2C_CON2_PECBYTE_MSK = 1<<13 */ +/** + * @} MD_I2C_START_GENERATION + */ + +/** @defgroup MD_I2C_HEAD10R Acknowledge Generation + * @{ + */ +#define MD_I2C_GENERAL_10BIT_READ 0x00000000U /*!< DISABLE */ +#define MD_I2C_SIMPLIFIED_10BIT_READ I2C_CON2_HEAD10R_MSK /*!< I2C_CON2_HEAD10R_MSK = 1<<12 */ +/** + * @} MD_I2C_HEAD10R + */ + +/** @defgroup MD_I2C_TRANSFER_DIRECTION Transfer direction (master mode) + * @{ + */ +#define MD_I2C_MASTER_WRITE 0x00000000U /*!< Master Write */ +#define MD_I2C_MASTER_READ I2C_CON2_RD_WRN_MSK /*!< I2C_CON2_RD_WRN_MSK = 1<<10 */ +/** + * @} MD_I2C_TRANSFER_DIRECTION + */ + +/** @defgroup MD_I2C_OA1_MODE Own Address 1 mode + * @{ + */ +#define MD_I2C_OA1_7BIT 0x00000000U /*!< OA1 7-bit mode */ +#define MD_I2C_OA1_10BIT I2C_ADDR1_OA1MODE_MSK /*!< I2C_ADDR1_OA1MODE_MSK = 1<<10 */ +/** + * @} MD_I2C_OA1_MODE + */ + +/** @defgroup MD_I2C_TIDLE_MODE Tidle mode + * @{ + */ +#define MD_I2C_LOW_TIMEOUTA 0x00000000U /*!< TIMEOUTA is used to detect SCL low timeout */ +#define MD_I2C_IDLE_TIMEOUTA I2C_TIMEOUTR_TIDLE_MSK /*!< TIMEOUTA is used to detectbus idle condition, I2C_TIMEOUTR_TIDLE_MSK = 1<<12 */ +/** + * @} MD_I2C_TIDLE_MODE + */ + +/** @defgroup MD_I2C_RXFIFO_THRESHOLD FIFO Threshold + * @{ + */ +#define MD_I2C_RXFIFO_THRESHOLD_RX1 0U<CON1, Reg_Value); +} + +/** + * @brief I2C Get CON1 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_con1(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->CON1)); +} + +/** + * @brief I2C PEC Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_pecen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); +} + +/** + * @brief I2C PEC Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_pecen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); +} + +/** + * @brief Indicate if I2C PEC is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to '0' + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_pecen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK) == (I2C_CON1_PECEN_MSK)); +} + +/** + * @brief I2C Alert Enable + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_alerten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); +} + +/** + * @brief I2C Alert Disable + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_alerten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); +} + +/** + * @brief Indicate if I2C PEC is enabled + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_alerten(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK) == (I2C_CON1_ALERTEN_MSK)); +} + +/** + * @brief I2C SMBus Device Default address Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_smbden(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); +} + +/** + * @brief I2C SMBus Device Default address Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_smbden(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); +} + +/** + * @brief Indicate if I2C SMBus Device Default address is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_smbden(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK) == (I2C_CON1_SMBDEN_MSK)); +} + +/** + * @brief I2C SMBus Host address Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_smbhen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); +} + +/** + * @brief I2C SMBus Host address Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_smbhen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); +} + +/** + * @brief Indicate if I2C SMBus Host address is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_smbhen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK) == (I2C_CON1_SMBHEN_MSK)); +} + +/** + * @brief I2C general call Enable + * @note This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_gcen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); +} + +/** + * @brief I2C general call Disable + * @note This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_gcen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); +} + +/** + * @brief Indicate if I2C general call is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_gcen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK) == (I2C_CON1_GCEN_MSK)); +} + +/** + * @brief I2C clock stretching Disable + * @note Clock stretching disables. This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_nostretch(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); +} + +/** + * @brief I2C clock stretching Enable + * @note Clock stretching enables.This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_nostretch(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); +} + +/** + * @brief Indicate if I2C clock nostretching is enabled + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_nostretch(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK) == (I2C_CON1_NOSTRETCH_MSK)); +} + +/** + * @brief I2C slave byte control Enable + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_sbc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); +} + +/** + * @brief I2C slave byte control Disable + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_sbc(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); +} + +/** + * @brief Indicate if I2C slave byte control is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_sbc(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK) == (I2C_CON1_SBC_MSK)); +} + +/** + * @brief I2C DMA reception requests Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_rxdmaen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); +} + +/** + * @brief I2C DMA reception requests Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_rxdmaen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); +} + +/** + * @brief Indicate if I2C DMA reception requests is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_rxdmaen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK) == (I2C_CON1_RXDMAEN_MSK)); +} + +/** + * @brief I2C DMA transmission requests Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_txdmaen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); +} + +/** + * @brief I2C DMA transmission requests Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_txdmaen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); +} + +/** + * @brief Indicate if I2C DMA transmission requests is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_txdmaen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK) == (I2C_CON1_TXDMAEN_MSK)); +} + +/** + * @brief Set I2C digital noise filter + * @note If the analog filter is also enabled,the digital filter is added to the analog filter. + * This filter can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param filter_capability digital noise filter capability + * @arg Max Value 0xFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con1_dnf(I2C_TypeDef *I2Cx, uint32_t filter_capability) +{ + MODIFY_REG(I2Cx->CON1, I2C_CON1_DNF_MSK, filter_capability<CON1, I2C_CON1_DNF_MSK)>>I2C_CON1_DNF_POSS); +} + +/** + * @brief I2C Peripheral Enable + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_pe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); +} + +/** + * @brief I2C Peripheral Disable + * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_pe(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); +} + +/** + * @brief Indicate if Peripheral is enabled + * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_pe(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_PE_MSK) == (I2C_CON1_PE_MSK)); +} + +/** + * @brief I2C Set CON2 + * @note None + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->CON2, Reg_Value); +} + +/** + * @brief I2C Get CON2 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_con2(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->CON2)); +} + +/** + * @brief I2C Set ACK Update + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_ack_upd(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_ACK_UPD_MSK); +} + +/** + * @brief I2C Hold Ack Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con2_holdack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); +} + +/** + * @brief I2C Hold Ack Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con2_holdack(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); +} + +/** + * @brief Indicate if I2C Hold Ack is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con2_holdack(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK) == (I2C_CON2_HOLDACK_MSK)); +} + +/** + * @brief Set I2C Packet error checking byte + * @note This bit is set by software, and cleared by hardware when the PEC is transferred, + * or when a STOP condition or an Address matched is received, also when PE=0. + * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, + * and when SBC is 0 in the slave mode. + * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @param setbit + * @arg @ref MD_I2C_PECBYTE_ENABLE + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_pecbyte(I2C_TypeDef *I2Cx, uint32_t setbit) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_PECBYTE_MSK, setbit); +} + +/** + * @brief Get I2C Packet error checking byte + * @note This bit is set by software, and cleared by hardware when the PEC is transferred, + * or when a STOP condition or an Address matched is received, also when PE=0. + * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, + * and when SBC is 0 in the slave mode. + * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_pecbyte(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_PECBYTE_MSK)>>I2C_CON2_PECBYTE_POS); +} + +/** + * @brief Set I2C automatic end mode or software end mode(master mode) + * @note This bit has no effect in slave mode or when the RELOAD bit is set. + * Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + * Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + * @param I2Cx I2C Instance + * @param setbit + * @arg @ref MD_I2C_SOFTEND_MODE + * @arg @ref MD_I2C_AUTOEND_MODE + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_autoend(I2C_TypeDef *I2Cx, uint32_t setbit) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_AUTOEND_MSK, setbit); +} + +/** + * @brief Get I2C automatic or software end mode(master mode) + * @note This bit has no effect in slave mode or when the RELOAD bit is set. + * Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + * Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_autoend(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_AUTOEND_MSK)>>I2C_CON2_AUTOEND_POS); +} + +/** + * @brief Set I2C NBYTES reload mode or not + * @note RELOAD = 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). + * RELOAD = 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). + * TCR flag is set when NBYTES data are transferred, stretching SCL low. + * @param I2Cx I2C Instance + * @param setbit + * @arg @ref MD_I2C_NORELOAD_MODE + * @arg @ref MD_I2C_RELOAD_MODE + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_reload(I2C_TypeDef *I2Cx, uint32_t setbit) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_RELOAD_MSK, setbit); +} + +/** + * @brief Get I2C RELOAD value + * @note RELOAD = 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). + * RELOAD = 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). + * TCR flag is set when NBYTES data are transferred, stretching SCL low. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_reload(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RELOAD_MSK)>>I2C_CON2_RELOAD_POS); +} + +/** + * @brief Set I2C number of bytes + * @note The number of bytes to be transmitted/received is programmed there. + * This field is dont care in slave mode with SBC=0. + * Changing these bits when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param nbytes number of bytes + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_nbytes(I2C_TypeDef *I2Cx, uint32_t nbytes) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_NBYTES_MSK, nbytes<CON2, I2C_CON2_NBYTES_MSK)>>I2C_CON2_NBYTES_POSS); +} + +/** + * @brief Set I2C NACK generation(slave mode) + * @note Writing 0 to this bit has no effect. This bit is used in slave mode only. + * When an overrun occurs in slave receiver NOSTRETCH mode,a NACK is automatically generated whatever the NACK bit value. + * When hardware PEC checking is enabled(PECBYTE = 1),the PEC acknowledge value does not depend on the NACK value. + * @param I2Cx I2C Instance + * @param nack nack generation + * @arg @ref MD_I2C_NACK + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_nack(I2C_TypeDef *I2Cx, uint32_t nack) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_NACK_MSK, nack); +} + +/** + * @brief Get I2C NACK bit state(slave mode) + * @note NACK=1: will generate NACK + * NACK=0: will generate ACK + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_NACK_MSK)>>I2C_CON2_NACK_POS); +} + +/** + * @brief Set I2C Stop generation(master mode) + * @note Writing 0 to this bit has no effect. + * @param I2Cx I2C Instance + * @param stop_generate stop generate + * @arg MD_I2C_STOP_GENERATION + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_stop(I2C_TypeDef *I2Cx, uint32_t stop_generate) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_STOP_MSK, stop_generate); +} + +/** + * @brief Get I2C state of STOP bit(master mode) + * @note Writing 0 to this bit has no effect. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_STOP_MSK)>>I2C_CON2_STOP_POS); +} + +/** + * @brief Set I2C Start generation + * @note Writing 0 to this bit has no effect.The START bit can be set even if the bus is BUSY or I2C is in slave mode. + * In 10-bit addressing mode, if a NACK is received on the first part of the address, + * the START bit is not cleared by hardware and the master will resend the address sequence. + * @param I2Cx I2C Instance + * @param start_generate stop generate + * @arg MD_I2C_START_GENERATION + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_start(I2C_TypeDef *I2Cx, uint32_t start_generate) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_START_MSK, start_generate); +} + +/** + * @brief Get I2C state of START bit + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_start(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_START_MSK)>>I2C_CON2_START_POS); +} + +/** + * @brief Set the master operates in 10-bit addressing mode(master receiver mode) + * @note Changing this bit when the START bit is set is not allowed. + * It can be used when the 10-bit transmission was done before. + * @param I2Cx I2C Instance + * @param read_header format of read header + * @arg @ref MD_I2C_GENERAL_10BIT_READ + * @arg @ref MD_I2C_SIMPLIFIED_10BIT_READ + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_head10r(I2C_TypeDef *I2Cx, uint32_t read_header) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_HEAD10R_MSK, read_header); +} + +/** + * @brief Indicate if I2C 10-bit address header only read direction is enabled(master receiver mode) + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_head10r(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_HEAD10R_MSK)>>I2C_CON2_HEAD10R_POS); +} + +/** + * @brief I2C 10-bit addressing mode Enable(master mode) + * @note Changing this bit when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param addrmode + @arg @ref MD_I2C_ADDRESSINGMODE_7BIT + @arg @ref MD_I2C_ADDRESSINGMODE_10BIT + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_add10(I2C_TypeDef *I2Cx, uint32_t addrmode) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_ADD10_MSK, addrmode); +} + +/** + * @brief Get I2C addressing mode is 10-bit or 7-bit mode(master mode) + * @note ADD10=1: 10-bit mode + * ADD10=0: 7-bit mode + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_add10(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_ADD10_MSK)>>I2C_CON2_ADD10_POS); +} + +/** + * @brief Set Master transfer direction(master mode) + * @note Changing this bit when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param direction + * @arg @ref MD_I2C_MASTER_WRITE + * @arg @ref MD_I2C_MASTER_READ + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_rd_wrn(I2C_TypeDef *I2Cx, uint32_t direction) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_RD_WRN_MSK, direction); +} + +/** + * @brief Get Master transfer direction(master mode) + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_rd_wrn(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RD_WRN_MSK)>>I2C_CON2_RD_WRN_POS); +} + +/** + * @brief Set I2C slave address(master mode) + * @note Changing these bits when the START bit is set is not allowed + * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @param slave_addr I2C slave address + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_sadd(I2C_TypeDef *I2Cx, uint32_t slave_addr) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_SADD_MSK, slave_addr); +} + +/** + * @brief Get I2C slave address(master mode) + * @note Changing these bits when the START bit is set is not allowed + * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @retval I2C slave address + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + */ +__STATIC_INLINE uint32_t md_i2c_get_sadd_7bit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_SADD_MSK)); +} + +/** + * @brief Set I2C ADDR1 + * @note These bits can be written only when OA1EN=0 except OA1EN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->ADDR1, Reg_Value); +} + +/** + * @brief Get I2C ADDR1 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->ADDR1)); +} + +/** + * @brief I2C address register 1 Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr1_oa1en(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); +} + +/** + * @brief I2C address register 1 Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_addr1_oa1en(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); +} + +/** + * @brief Indicate if address register 1 is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_addr1_oa1en(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK) == (I2C_ADDR1_OA1EN_MSK)); +} + +/** + * @brief Set I2C OA1 bit mode + * @param I2Cx I2C Instance + * @param oa1mode + * @arg @ref MD_I2C_OA1_7BIT + * @arg @ref MD_I2C_OA1_10BIT + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1_oa1mode(I2C_TypeDef *I2Cx, uint32_t oa1mode) +{ + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK, oa1mode); +} + +/** + * @brief Get I2C own address 1 mode + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1_oa1mode(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK)>>I2C_ADDR1_OA1MODE_POS); +} + +/** + * @brief Set I2C address1 + * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @param own_addr I2C own address1 + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1_oa1(I2C_TypeDef *I2Cx, uint32_t own_addr) +{ + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, own_addr); +} + +/** + * @brief Get I2C address1 + * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @retval I2C own address1 + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1_oa1(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK)); +} + +/** + * @brief Set I2C ADDR2 + * @note These bits can be written only when OA2EN=0 except OA2EN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->ADDR2, Reg_Value); +} + +/** + * @brief Get I2C ADDR2 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr2(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->ADDR2)); +} + +/** + * @brief I2C own address register 2 Enable + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr2_oa2en(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); +} + +/** + * @brief I2C own address register 2 Disable + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_addr2_oa2en(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); +} + +/** + * @brief Indicate if address register 2 is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_addr2_oa2en(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK) == (I2C_ADDR2_OA2EN_MSK)); +} + +/** + * @brief Set I2C own address2 mask + * @note These bits can be written only when OA2EN=0. + * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + * @param I2Cx I2C Instance + * @param oa2_mask I2C own address2 mask + * @arg @ref MD_I2C_ADDR2_NOMASK + * @arg @ref MD_I2C_ADDR2_MASK01 + * @arg @ref MD_I2C_ADDR2_MASK02 + * @arg @ref MD_I2C_ADDR2_MASK03 + * @arg @ref MD_I2C_ADDR2_MASK04 + * @arg @ref MD_I2C_ADDR2_MASK05 + * @arg @ref MD_I2C_ADDR2_MASK06 + * @arg @ref MD_I2C_ADDR2_MASK07 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2_oa2mask(I2C_TypeDef *I2Cx, uint32_t oa2_mask) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK, oa2_mask); +} + +/** + * @brief Get I2C address2 mask + * @note None + * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + * @param I2Cx I2C Instance + * @retval I2C own address2 mask(value 0 to 7) + */ +__STATIC_INLINE uint32_t md_i2c_get_addr2_oa2mask(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK)>>I2C_ADDR2_OA2MSK_POSS); +} + +/** + * @brief Set I2C own address2 + * @note These bits can be written only when OA2EN=0. + * @param I2Cx I2C Instance + * @param own_addr I2C own address2 + * @arg Max Value 0x7F + * @arg Min Value 0x1 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2_oa2(I2C_TypeDef *I2Cx, uint32_t own_addr) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, own_addr <ADDR2, I2C_ADDR2_OA2_MSK)>>I2C_ADDR2_OA2_POSS); +} + +/** + * @brief Set I2C TIMINGR + * @note These bits must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->TIMINGR, Reg_Value); +} + +/** + * @brief Get I2C TIMINGR + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->TIMINGR)); +} + +/** + * @brief Set I2C Timing prescaler + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param timing_prescaler + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_presc(I2C_TypeDef *I2Cx, uint32_t timing_prescaler) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK, timing_prescaler << I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Get I2C Timing prescaler + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval timing_prescaler + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_presc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK)>>I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Set I2C date setup time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param data_setup_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_scldel(I2C_TypeDef *I2Cx, uint32_t data_setup_time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, data_setup_time <TIMINGR, I2C_TIMINGR_SCLDEL_MSK)>>I2C_TIMINGR_SCLDEL_POSS); +} + +/** + * @brief Set I2C date hold time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param data_hold_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_sdadel(I2C_TypeDef *I2Cx, uint32_t data_hold_time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, data_hold_time << I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Get I2C date hold time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval data_hold_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_sdadel(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK)>>I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Set I2C SCL high period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param SCL_hperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_sclh(I2C_TypeDef *I2Cx, uint32_t SCL_hperiod) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK, SCL_hperiod << I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Get I2C SCL high period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval SCL_hperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_sclh(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK)>>I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Set I2C SCL low period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param SCL_lperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_scll(I2C_TypeDef *I2Cx, uint32_t SCL_lperiod) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, SCL_lperiod << I2C_TIMINGR_SCLL_POSS); +} + +/** + * @brief Get I2C SCL low period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval SCL_lperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_scll(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK)); +} + +/** + * @brief Set I2C TIMEOUTR + * @note These bits can be written only when TEXTEN=0 and TIMEOUTEN=0 except TEXTEN and TIMEOUTEN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->TIMEOUTR, Reg_Value); +} + +/** + * @brief Get I2C TIMEOUTR + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->TIMEOUTR)); +} + +/** + * @brief I2C Extended clock timeout Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_timeoutr_texten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); +} + +/** + * @brief I2C Extended clock timeout Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_timeoutr_texten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); +} + +/** + * @brief Indicate if I2C Extended clock timeout is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_timeoutr_texten(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK) == (I2C_TIMEOUTR_TEXTEN_MSK)); +} + +/** + * @brief Set I2C Bus timeout B + * @note These bits can be written only when TEXTEN = 0 + * @param I2Cx I2C Instance + * @param timeoutb Bus timeout B + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr_timeoutb(I2C_TypeDef *I2Cx, uint32_t timeoutb) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK, timeoutb << I2C_TIMEOUTR_TIMEOUTB_POSS); +} + +/** + * @brief Get I2C Bus timeout B + * @note These bits can be written only when TEXTEN = 0 + * @param I2Cx I2C Instance + * @retval Bus timeout B + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr_timeoutb(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK)>>I2C_TIMEOUTR_TIMEOUTB_POSS); +} + +/** + * @brief I2C clock timeout Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_timeoutr_timeouten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); +} + +/** + * @brief I2C clock timeout Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_timeoutr_timeouten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); +} + +/** + * @brief Indicate if I2C clock timeout is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_timeoutr_timeouten(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK) == (I2C_TIMEOUTR_TIMEOUTEN_MSK)); +} + +/** + * @brief Set I2C Tidle to decide a timeouta mode + * @note This bit can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @param tidle_mode + * @arg @ref MD_I2C_LOW_TIMEOUTA + * @arg @ref MD_I2C_IDLE_TIMEOUTA + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr_tidle(I2C_TypeDef *I2Cx, uint32_t tidle_mode) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK, tidle_mode); +} + +/** + * @brief Get I2C Tidle to know a timeouta mode + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr_tidle(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK)>>I2C_TIMEOUTR_TIDLE_POS); +} + +/** + * @brief Set I2C Bus timeout A + * @note These bits can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @param timeouta Bus timeout A + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr_timeouta(I2C_TypeDef *I2Cx, uint32_t timeouta) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK, timeouta << I2C_TIMEOUTR_TIMEOUTA_POSS); +} + +/** + * @brief Get I2C Bus timeout A + * @note These bits can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @retval Bus timeout A + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr_timeouta(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK)); +} + +/** + * @brief Get I2C STAT + * @note All bits are read-only + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_stat(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->STAT)); +} + +/** + * @brief Get address match code(slave mode) + * @note These bits are updated with the received address when an address match event occurs(ADDR=1). + * @param I2Cx I2C Instance + * @retval 7-bit received address value + */ +__STATIC_INLINE uint32_t md_i2c_get_stat_addcode(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_ADDCODE_MSK)>>I2C_STAT_ADDCODE_POSS); +} + +/** + * @brief Get transfer direction(slave mode) + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_stat_dir(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR_MSK)>>I2C_STAT_DIR_POS); +} + +/** + * @brief Indicate if I2C busy flag is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_busy(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_BUSY_MSK) == (I2C_STAT_BUSY_MSK)); +} + +/** + * @brief Indicate if I2C transfer complete reload flag (TCR) is active + * @note This bit is cleared by hardware when PE = 0. + * This flag is only for master mode,or for slave mode when the SBC bit is set + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_tcr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TCR_MSK) == (I2C_STAT_TCR_MSK)); +} + +/** + * @brief Indicate if I2C transfer complete flag (TC) is active + * @note This bit is cleared by hardware when PE = 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_tc(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TC_MSK) == (I2C_STAT_TC_MSK)); +} + +/** + * @brief Indicate if I2C Rx FIFO level over threshold flag (RXTH) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxth(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXTH_MSK) == (I2C_STAT_RXTH_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer underflow flag (RXUD) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxud(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXUD_MSK) == (I2C_STAT_RXUD_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer overflow flag (RXOV) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxov(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXOV_MSK) == (I2C_STAT_RXOV_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer full flag (RXF) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxf(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXF_MSK) == (I2C_STAT_RXF_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer empty flag (RXE) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxe(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXE_MSK) == (I2C_STAT_RXE_MSK)); +} + +/** + * @brief Indicate if I2C Tx FIFO level over threshold flag (TXTH) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txth(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXTH_MSK) == (I2C_STAT_TXTH_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer underflow flag (TXUD) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_is_active_stat_txud(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXUD_MSK) == (I2C_STAT_TXUD_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer overflow flag (TXOV) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txov(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXOV_MSK) == (I2C_STAT_TXOV_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer full flag (TXF) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txf(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXF_MSK) == (I2C_STAT_TXF_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer empty flag (TXE) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txe(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXE_MSK) == (I2C_STAT_TXE_MSK)); +} + +/** + * @brief Set I2C FCON + * @note FIFO trigger threshold must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->FCON, Reg_Value); +} + +/** + * @brief Get I2C FCON + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_fcon(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->FCON)); +} + +/** + * @brief Set RXFIFO trigger threshold + * @note Receive FIFO trigger threshold must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param rxfifo_trigger_threshold This parameter can be one of the following values: + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX1 + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX4 + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX8 + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX14 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_rxfth(I2C_TypeDef *I2Cx, uint32_t rxfifo_trigger_threshold) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_RXFTH_MSK, rxfifo_trigger_threshold); +} + +/** + * @brief Get RXFIFO trigger threshold + * @note None + * @param I2Cx I2C Instance + * @retval The retval can be 0 to 3 + */ +__STATIC_INLINE uint32_t md_i2c_get_fcon_rxfth(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_RXFTH_MSK)>>I2C_FCON_RXFTH_POSS); +} + +/** + * @brief Set I2C RXFIFO reset + * @note None + * @param I2Cx I2C Instance + * @arg @ref MD_I2C_RXFIFO_RESET + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_rxfrst(I2C_TypeDef *I2Cx, uint32_t reset) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_RXFRST_MSK, reset); +} + +/** + * @brief Get I2C RXFIFO level + * @note None + * @param I2Cx I2C Instance + * @retval It's from 0 to 16 + */ +__STATIC_INLINE uint32_t md_i2c_get_rxfifo_level(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_RXFLV_MSK)>>I2C_FCON_RXFLV_POSS); +} + +/** + * @brief Set TXFIFO trigger threshold + * @param I2Cx I2C Instance + * @param txfifo_trigger_threshold This parameter can be one of the following values: + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX0 + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX2 + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX4 + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX8 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_txfth(I2C_TypeDef *I2Cx, uint32_t txfifo_trigger_threshold) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_TXFTH_MSK, txfifo_trigger_threshold); +} + +/** + * @brief Get TXFIFO trigger threshold + * @param I2Cx I2C Instance + * @retval It's from 0 to 3 + */ +__STATIC_INLINE uint32_t md_i2c_get_txfifo_trigger_threshold(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_TXFTH_MSK)>>I2C_FCON_TXFTH_POSS); +} + +/** + * @brief I2C TXFIFO reset + * @note None + * @param I2Cx I2C Instance + * @arg @ref MD_I2C_TXFIFO_RESET + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_txfrst(I2C_TypeDef *I2Cx, uint32_t reset) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_TXFRST_MSK, reset); +} + +/** + * @brief Get TXFIFO level + * @note None + * @param I2Cx I2C Instance + * @retval It's from 0 to 16 + */ +__STATIC_INLINE uint32_t md_i2c_get_txfifo_level(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_TXFLV_MSK)); +} + +/** + * @brief Get packet error checking register + * @note None + * @param I2Cx I2C Instance + * @retval 8-bit pec value + */ +__STATIC_INLINE uint32_t md_i2c_get_pecr_pec(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->PECR, I2C_PECR_PEC_MSK)); +} + +/** + * @brief 8-bit receive data + * @note None + * @param I2Cx I2C Instance + * @retval 8-bit receive data + */ +__STATIC_INLINE uint32_t md_i2c_recv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RXDATA, I2C_RXDATA_RXDATA_MSK)); +} + +/** + * @brief 8-bit transmit data + * @note These bits can be written only when TXE = 1. + * @param I2Cx I2C Instance + * @param txdata Transmit Data + * @arg Max value 0xFF + * @arg Min value 0 + * @retval None + */ +__STATIC_INLINE void md_i2c_send(I2C_TypeDef *I2Cx, uint32_t txdata) +{ + MODIFY_REG(I2Cx->TXDATA, I2C_TXDATA_TXDATA_MSK, txdata); +} + +/** + * @brief Set I2C IER + * @note None + * @param I2Cx I2C Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_i2c_set_ier(I2C_TypeDef *I2Cx, uint32_t ier) +{ + WRITE_REG(I2Cx->IER, ier); +} + +/** + * @brief Enable SMBus alert interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_alertie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ALERTIE_MSK); +} + +/** + * @brief Enable timeout interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_toutie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TOUTIE_MSK); +} + +/** + * @brief Enable PEC error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_peceie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_PECEIE_MSK); +} + +/** + * @brief Enable arbitration loss interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_arloie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ARLOIE_MSK); +} + +/** + * @brief Enable bus error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_berrie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_BERRIE_MSK); +} + +/** + * @brief Enable stop detection interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_stopie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_STOPIE_MSK); +} + +/** + * @brief Enable NACK reception interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_nackie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_NACKIE_MSK); +} + +/** + * @brief Enable address matched interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_addrie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ADDRIE_MSK); +} + +/** + * @brief Enable transfer complete and reload interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_tcrie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TCRIE_MSK); +} + +/** + * @brief Enable transfer complete interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_tcie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TCIE_MSK); +} + +/** + * @brief Enable receive buffer over threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxthie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXTHIE_MSK); +} + +/** + * @brief Enable receive buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxudie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXUDIE_MSK); +} + +/** + * @brief Enable receive buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxovie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXOVIE_MSK); +} + +/** + * @brief Enable receive buffer full interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxfie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXFIE_MSK); +} + +/** + * @brief Enable transmit buffer under threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txthie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXTHIE_MSK); +} + +/** + * @brief Enable transmit buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txudie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXUDIE_MSK); +} + +/** + * @brief Enable transmit buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txovie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXOVIE_MSK); +} + +/** + * @brief Enable transmit buffer empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txeie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXEIE_MSK); +} + +/** + * @brief Set I2C IDR + * @note None + * @param I2Cx I2C Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_i2c_set_idr(I2C_TypeDef *I2Cx, uint32_t idr) +{ + WRITE_REG(I2Cx->IDR, idr); +} + +/** + * @brief Disable SMBus alert interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_alertid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_ALERTID_MSK); +} + +/** + * @brief Disable timeout interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_toutid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TOUTID_MSK); +} + +/** + * @brief Disable PEC error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_peceid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_PECEID_MSK); +} + +/** + * @brief Disable arbitration loss interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_arloid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_ARLOID_MSK); +} + +/** + * @brief Disable bus error interrupt. + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_berrid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_BERRID_MSK); +} + +/** + * @brief Disable stop detection interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_stopid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_STOPID_MSK); +} + +/** + * @brief Disable NACK reception interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_nackid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_NACKID_MSK); +} + +/** + * @brief Disable address matched interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_addrid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_ADDRID_MSK); +} + +/** + * @brief Disable transfer complete and reload interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_tcrid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TCRID_MSK); +} + +/** + * @brief Disable transfer complete interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_tcid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TCID_MSK); +} + +/** + * @brief Disable receive buffer over threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxthid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXTHID_MSK); +} + +/** + * @brief Disable receive buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxudid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXUDID_MSK); +} + +/** + * @brief Disable receive buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxovid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXOVID_MSK); +} + +/** + * @brief Disable receive buffer full interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxfid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXFID_MSK); +} + +/** + * @brief Disable transmit buffer under threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txthid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXTHID_MSK); +} + +/** + * @brief Disable transmit buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txudid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXUDID_MSK); +} + +/** + * @brief Disable transmit buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txovid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXOVID_MSK); +} + +/** + * @brief Disable transmit buffer empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txeid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXEID_MSK); +} + +/** + * @brief Get I2C IVS + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_ivs(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->IVS)); +} + +/** + * @brief Check if SMBus alert interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_alertiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ALERTIV_MSK) == (I2C_IVS_ALERTIV_MSK)); +} + +/** + * @brief Check if timeout interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_toutiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TOUTIV_MSK) == (I2C_IVS_TOUTIV_MSK)); +} + +/** + * @brief Check if PEC error interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_peceiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_PECEIV_MSK) == (I2C_IVS_PECEIV_MSK)); +} + +/** + * @brief Check if arbitration loss interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_arloiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ARLOIV_MSK) == (I2C_IVS_ARLOIV_MSK)); +} + +/** + * @brief Check if bus error interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_berriv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_BERRIV_MSK) == (I2C_IVS_BERRIV_MSK)); +} + +/** + * @brief Check if stop detection interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_stopiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_STOPIV_MSK) == (I2C_IVS_STOPIV_MSK)); +} + +/** + * @brief Check if NACK reception interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_nackiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_NACKIV_MSK) == (I2C_IVS_NACKIV_MSK)); +} + +/** + * @brief Check if address matched interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_addriv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ADDRIV_MSK) == (I2C_IVS_ADDRIV_MSK)); +} + +/** + * @brief Check if transfer complete and reload interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_tcriv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TCRIV_MSK) == (I2C_IVS_TCRIV_MSK)); +} + +/** + * @brief Check if transfer complete interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_tciv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TCIV_MSK) == (I2C_IVS_TCIV_MSK)); +} + +/** + * @brief Check if receive buffer over threshold interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxthiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXTHIV_MSK) == (I2C_IVS_RXTHIV_MSK)); +} + +/** + * @brief Check if receive buffer underrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxudiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXUDIV_MSK) == (I2C_IVS_RXUDIV_MSK)); +} + +/** + * @brief Check if receive buffer ovrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxoviv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXOVIV_MSK) == (I2C_IVS_RXOVIV_MSK)); +} + +/** + * @brief Check if receive buffer full interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxfiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXFIV_MSK) == (I2C_IVS_RXFIV_MSK)); +} + +/** + * @brief Check if transmit buffer under threshold interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txthiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXTHIV_MSK) == (I2C_IVS_TXTHIV_MSK)); +} + +/** + * @brief Check if transmit buffer underrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txudiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXUDIV_MSK) == (I2C_IVS_TXUDIV_MSK)); +} + +/** + * @brief Check if transmit buffer ovrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txoviv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXOVIV_MSK) == (I2C_IVS_TXOVIV_MSK)); +} + +/** + * @brief Check if transmit buffer empty interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txeiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXEIV_MSK) == (I2C_IVS_TXEIV_MSK)); +} + +/** + * @brief Get I2C RIF + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_rif(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->RIF)); +} + +/** + * @brief Get SMBus alert raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_alertri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ALERTRI_MSK) == (I2C_RIF_ALERTRI_MSK)); +} + +/** + * @brief Get timeout raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_toutri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TOUTRI_MSK) == (I2C_RIF_TOUTRI_MSK)); +} + +/** + * @brief Get PEC error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_peceri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_PECERI_MSK) == (I2C_RIF_PECERI_MSK)); +} + +/** + * @brief Get arbitration loss raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_arlori(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ARLORI_MSK) == (I2C_RIF_ARLORI_MSK)); +} + +/** + * @brief Get bus error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_berrri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_BERRRI_MSK) == (I2C_RIF_BERRRI_MSK)); +} + +/** + * @brief Get stop detection raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_stopri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_STOPRI_MSK) == (I2C_RIF_STOPRI_MSK)); +} + +/** + * @brief Get NACK reception raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_nackri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_NACKRI_MSK) == (I2C_RIF_NACKRI_MSK)); +} + +/** + * @brief Get address matched raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_addrri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ADDRRI_MSK) == (I2C_RIF_ADDRRI_MSK)); +} + +/** + * @brief Get transfer complete and reload raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_tcrri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TCRRI_MSK) == (I2C_RIF_TCRRI_MSK)); +} + +/** + * @brief Get transfer complete raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_tcri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TCRI_MSK) == (I2C_RIF_TCRI_MSK)); +} + +/** + * @brief Get receive buffer over threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxthri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXTHRI_MSK) == (I2C_RIF_RXTHRI_MSK)); +} + +/** + * @brief Get receive buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxudri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXUDRI_MSK) == (I2C_RIF_RXUDRI_MSK)); +} + +/** + * @brief Get receive buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxovri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXOVRI_MSK) == (I2C_RIF_RXOVRI_MSK)); +} + +/** + * @brief Get receive buffer full raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxfri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXFRI_MSK) == (I2C_RIF_RXFRI_MSK)); +} + +/** + * @brief Get transmit buffer under threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txthri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXTHRI_MSK) == (I2C_RIF_TXTHRI_MSK)); +} + +/** + * @brief Get transmit buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txudri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXUDRI_MSK) == (I2C_RIF_TXUDRI_MSK)); +} + +/** + * @brief Get transmit buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txovri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXOVRI_MSK) == (I2C_RIF_TXOVRI_MSK)); +} + +/** + * @brief Get transmit buffer empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txeri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXERI_MSK) == (I2C_RIF_TXERI_MSK)); +} + +/** + * @brief Set I2C ICR + * @note None + * @param I2Cx I2C Instance + * @param icr + * @retval None + */ +__STATIC_INLINE void md_i2c_set_icr(I2C_TypeDef *I2Cx, uint32_t icr) +{ + WRITE_REG(I2Cx->ICR, icr); +} + +/** + * @brief Clear SMBus alert raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_alertic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTIC_MSK); +} + +/** + * @brief Clear timeout raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_toutic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TOUTIC_MSK); +} + +/** + * @brief Clear PEC error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_peceic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECEIC_MSK); +} + +/** + * @brief Clear arbitration loss raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_arloic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOIC_MSK); +} + +/** + * @brief Clear bus error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_berric(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRIC_MSK); +} + +/** + * @brief Clear stop detection raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_stopic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPIC_MSK); +} + +/** + * @brief Clear NACK reception raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_nackic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKIC_MSK); +} + +/** + * @brief Clear address matched raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_addric(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRIC_MSK); +} + +/** + * @brief Clear transfer complete and reload raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_tcric(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TCRIC_MSK); +} + +/** + * @brief Clear transfer complete raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_tcic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TCIC_MSK); +} + +/** + * @brief Clear receive buffer over threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxthic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXTHIC_MSK); +} + +/** + * @brief Clear receive buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxudic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXUDIC_MSK); +} + +/** + * @brief Clear receive buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxovic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXOVIC_MSK); +} + +/** + * @brief Clear receive buffer full raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxfic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXFIC_MSK); +} + +/** + * @brief Clear transmit buffer under threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txthic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXTHIC_MSK); +} + +/** + * @brief Clear transmit buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txudic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXUDIC_MSK); +} + +/** + * @brief Clear transmit buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txovic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXOVIC_MSK); +} + +/** + * @brief Clear transmit buffer empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txeic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXEIC_MSK); +} + +/** + * @brief Get I2C IFM + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_ifm(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->IFM)); +} + +/** + * @brief Get SMBus alert interrupt flag massked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_alertfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ALERTFM_MSK) == (I2C_IFM_ALERTFM_MSK)); +} + +/** + * @brief Get timeout interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_toutfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TOUTFM_MSK) == (I2C_IFM_TOUTFM_MSK)); +} + +/** + * @brief Get PEC error interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_pecefm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_PECEFM_MSK) == (I2C_IFM_PECEFM_MSK)); +} + +/** + * @brief Get arbitration loss interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_arlofm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ARLOFM_MSK) == (I2C_IFM_ARLOFM_MSK)); +} + +/** + * @brief Get bus error interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_berrfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_BERRFM_MSK) == (I2C_IFM_BERRFM_MSK)); +} + +/** + * @brief Get stop detection interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_stopfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_STOPFM_MSK) == (I2C_IFM_STOPFM_MSK)); +} + +/** + * @brief Get NACK reception interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_nackfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_NACKFM_MSK) == (I2C_IFM_NACKFM_MSK)); +} + +/** + * @brief Get address matched interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_addrfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ADDRFM_MSK) == (I2C_IFM_ADDRFM_MSK)); +} + +/** + * @brief Get transfer complete and reload interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_tcrfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TCRFM_MSK) == (I2C_IFM_TCRFM_MSK)); +} + +/** + * @brief Get transfer complete interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_tcfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TCFM_MSK) == (I2C_IFM_TCFM_MSK)); +} + +/** + * @brief Get receive buffer over threshold interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxthfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXTHFM_MSK) == (I2C_IFM_RXTHFM_MSK)); +} + +/** + * @brief Get receive buffer underrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxudfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXUDFM_MSK) == (I2C_IFM_RXUDFM_MSK)); +} + +/** + * @brief Get receive buffer ovrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxovfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXOVFM_MSK) == (I2C_IFM_RXOVFM_MSK)); +} + +/** + * @brief Get receive buffer full interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxffm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXFFM_MSK) == (I2C_IFM_RXFFM_MSK)); +} + +/** + * @brief Get transmit buffer under threshold interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txthfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXTHFM_MSK) == (I2C_IFM_TXTHFM_MSK)); +} + +/** + * @brief Get transmit buffer underrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txudfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXUDFM_MSK) == (I2C_IFM_TXUDFM_MSK)); +} + +/** + * @brief Get transmit buffer ovrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txovfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXOVFM_MSK) == (I2C_IFM_TXOVFM_MSK)); +} + +/** + * @brief Get transmit buffer empty interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txefm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXEFM_MSK) == (I2C_IFM_TXEFM_MSK)); +} + +/** + * @} MD_I2C_Public_Macros + */ + + + + + + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_I2C_Public_Functions I2C Public Functions + * @{ + */ + +/** @defgroup MD_I2C_PF_Basic_Configuration I2C Configuration + * @{ + */ + +//ErrorStatus md_i2c_deinit(I2C_TypeDef *I2Cx); +ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct); +void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct); +void md_i2c_master_send(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf); +void md_i2c_master_rece(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf); +void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *txbuf); +void md_i2c_slave_rece(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *rxbuf); + +/** + * @} MD_I2C_PF_Init + */ + +/** + * @} MD_I2C_Public_Functions + */ + +#endif + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MD_I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_MD_I2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == I2C1) \ + || (__INSTANCE__ == I2C2) \ + || (__INSTANCE__ == I2C3)) + +#define IS_MD_I2C_TIMING(__VALUE__) ((__VALUE__ == CLK10kHz8M) \ + || (__VALUE__ == CLK100kHz8M)) \ + || (__VALUE__ == CLK400kHz8M)) \ + || (__VALUE__ == CLK500kHz8M)) \ + || (__VALUE__ == CLK10kHz16M)) \ + || (__VALUE__ == CLK100kHz16M)) \ + || (__VALUE__ == CLK400kHz16M)) \ + || (__VALUE__ == CLK1000kHz16M)) \ + || (__VALUE__ == CLK10kHz48M)) \ + || (__VALUE__ == CLK100kHz48M)) \ + || (__VALUE__ == CLK400kHz48M)) \ + || (__VALUE__ == CLK1000kHz48M)) + +#define IS_MD_I2C_ADDRSIZE(__VALUE__) ((__VALUE__ == MD_I2C_ADDRESSINGMODE_7BIT) \ + || (__VALUE__ == MD_I2C_ADDRESSINGMODE_10BIT)) + +#define IS_MD_I2C_ADDRESS1(__VALUE__) (__VALUE__ <= 0x000003FFU) +#define IS_MD_I2C_ADDRESS2(__VALUE__) (__VALUE__ <= (uint16_t)0x00FFU) + +#define IS_MD_I2C_DUALADDRESSMODE(__VALUE__) ((__VALUE__ == MD_I2C_DUALADDRESS_DISABLE) \ + || (__VALUE__ == MD_I2C_DUALADDRESS_ENABLE)) +#define IS_MD_I2C_ADDRESS2MASKS(__VALUE__) ((__VALUE__ == MD_I2C_ADDR2_NOMASK) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK01) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK02) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK03) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK04) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK05) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK06) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK07)) + +/** + * @} MD_I2C_Private_Macro + */ + +/** + * @} I2C + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h new file mode 100644 index 0000000000000000000000000000000000000000..1b9b6ff09b6907433f5be84ee04700f7acf1310e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h @@ -0,0 +1,5804 @@ +/** + ****************************************************************************** + * @file md_RCU.h + * @brief ES32F0271 RCU HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_RCU_H__ +#define __MD_RCU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_rcu.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (RCU) + +/** @defgroup RCU RCU + * @brief RCU micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/** @defgroup MD_RCU_Private_Constants RCU Private Constants + * @{ + */ + +#define __HOSC (8000000UL) +#define __HRC (4000000UL) +#define __LOSC ( 32768UL) +#define __LRC ( 32000UL) +#define __PLL1 (48000000UL) + +/** + * @} MD_RCU_Private_Constants + */ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Types RCU Public Init Type + * @{ + */ + +typedef struct +{ + uint32_t Mpre; /*! MCO clock prescaler */ + uint32_t Msw; /*! MCO clock output */ + uint32_t PllMul; /*! PLL multiplication factor */ + uint32_t PllSrc; /*! PLL clock source */ + uint32_t HoscDiv; /*! PLL base clock 4MHz HOSC clock prescale */ + uint32_t Ppre; /*! APB clock prescaler */ + uint32_t Hpre; /*! AHB clock prescaler */ + uint32_t Sw; /*! system clock */ + uint8_t SysClock;/*! system clock enable */ +} md_rcu_init_typedef; + +/** + * @} MD_RCU_Public_Types + */ +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Constants RCU Public Constants + * @{ + */ + +/** @defgroup MD_RCU_SWRDY_FLAG System clock switch ready flag + * @{ + */ +#define MD_RCU_SWRDY_NOT_READY (0x00000000UL) /** @brief System clock not ready */ +#define MD_RCU_SWRDY_READY (0x00000001UL) /** @brief System clock ready */ +/** + * @} MD_RCU_SWRDY_FLAG + */ + +/** @defgroup MD_RCU_CSSFLG_FLAG Clock Security System flag + * @{ + */ +#define MD_RCU_CSSFLG_NO_FAIL (0x00000000UL) /** @brief No clock security event caused by HOSC clock failure */ +#define MD_RCU_CSSFLG_FAIL (0x00000001UL) /** @brief Clock security event caused by HOSC clock failure */ +/** + * @} MD_RCU_CSSFLG_FLAG + */ + +/** @defgroup MD_RCU_PLL1_FLAG PLL1 clock ready flag + * @{ + */ +#define MD_RCU_PLL1_NOT_READY (0x00000000UL) /** @brief PLL1 not ready */ +#define MD_RCU_PLL1_READY (0x00000001UL) /** @brief PLL1 ready */ +/** + * @} MD_RCU_PLL1_FLAG + */ + +/** @defgroup MD_RCU_PLL0_FLAG PLL0 clock ready flag + * @{ + */ +#define MD_RCU_PLL0_NOT_READY (0x00000000UL) /** @brief PLL0 not ready */ +#define MD_RCU_PLL0_READY (0x00000001UL) /** @brief PLL0 ready */ +/** + * @} MD_RCU_PLL0_FLAG + */ + +/** @defgroup MD_RCU_LOSCRDY_FLAG LOSC clock ready flag + * @{ + */ +#define MD_RCU_LOSCRDY_NOT_READY (0x00000000UL) /** @brief LOSC oscillator not ready */ +#define MD_RCU_LOSCRDY_READY (0x00000001UL) /** @brief LOSC oscillator ready */ +/** + * @} MD_RCU_LOSCRDY_FLAG + */ + +/** @defgroup MD_RCU_LRCRDY_FLAG LRC clock ready flag + * @{ + */ +#define MD_RCU_LRCRDY_NOT_READY (0x00000000UL) /** @brief LRC oscillator not ready */ +#define MD_RCU_LRCRDY_READY (0x00000001UL) /** @brief LRC oscillator ready */ +/** + * @} MD_RCU_LRCRDY_FLAG + */ + +/** @defgroup MD_RCU_HOSCRDY_FLAG HOSC clock ready flag + * @{ + */ +#define MD_RCU_HOSCRDY_NOT_READY (0x00000000UL) /** @brief HOSC oscillator not ready */ +#define MD_RCU_HOSCRDY_READY (0x00000001UL) /** @brief HOSC oscillator ready */ +/** + * @} MD_RCU_HOSCRDY_FLAG + */ + +/** @defgroup MD_RCU_HRCRDY_FLAG HRC clock ready flag + * @{ + */ +#define MD_RCU_HRCRDY_NOT_READY (0x00000000UL) /** @brief HRC oscillator not ready */ +#define MD_RCU_HRCRDY_READY (0x00000001UL) /** @brief HRC oscillator ready */ +/** + * @} MD_RCU_HRCRDY_FLAG + */ + +/** @defgroup MD_RCU_MCO_OUTPUT Microcontroller clock output select + * @{ + */ +#define MD_RCU_MCO_DISABLE (0x00000000UL) /** @brief MCO output disabled, no clock on MCO */ +#define MD_RCU_MCO_LRC (0x00000001UL) /** @brief Internal low speed (LRC) oscillator clock selected */ +#define MD_RCU_MCO_LOSC (0x00000002UL) /** @brief External low speed (LOSC) oscillator clock selected */ +#define MD_RCU_MCO_HRC (0x00000003UL) /** @brief Internal high speed (HRC) oscillator clock selected */ +#define MD_RCU_MCO_HOSC (0x00000004UL) /** @brief External high speed (HOSC) oscillator clock selected */ +#define MD_RCU_MCO_PLL0 (0x00000005UL) /** @brief PLL0 clock selected */ +#define MD_RCU_MCO_PLL1 (0x00000006UL) /** @brief PLL1 clock selected */ +#define MD_RCU_MCO_SYSCLK (0x00000007UL) /** @brief System clock selected(SYSCLK) */ +#define MD_RCU_MCO_HCLK (0x00000008UL) /** @brief AHB clock selected(HCLK) */ +#define MD_RCU_MCO_PCLK (0x00000009UL) /** @brief APB clock selected(PCLK) */ +/** + * @} MD_RCU_MCO_OUTPUT + */ + +/** @defgroup MD_RCU_PLL_SRC PLL0/1 reference clock source + * @{ + */ +#define MD_RCU_PLL_SRC_HRC (0x00000000UL) /** @brief HRC selected as PLL0/1 reference clock */ +#define MD_RCU_PLL_SRC_HOSCDIV (0x00000001UL) /** @brief HOSC/HOSCDIV selected as PLL reference clock */ +/** + * @} MD_RCU_PLL_SRC + */ + +/** @defgroup MD_RCU_APB_CLK_DIV APB clock prescaler(PCLK) + * @{ + */ +#define MD_RCU_PPRE_HCLK_DIV_1 (0x00000000UL) /** @brief HCLK not divided */ +#define MD_RCU_PPRE_HCLK_DIV_2 (0x00000004UL) /** @brief HCLK divided by 2 */ +#define MD_RCU_PPRE_HCLK_DIV_4 (0x00000005UL) /** @brief HCLK divided by 4 */ +#define MD_RCU_PPRE_HCLK_DIV_8 (0x00000006UL) /** @brief HCLK divided by 8 */ +#define MD_RCU_PPRE_HCLK_DIV_16 (0x00000007UL) /** @brief HCLK divided by 16 */ +/** + * @} MD_RCU_APB_CLK_DIV + */ + +/** @defgroup MD_RCU_AHB_CLK_DIV AHB clock prescaler(HCLK) + * @{ + */ +#define MD_RCU_HPRE_SYSCLK_DIV_1 (0x00000000UL) /** @brief SYSCLK not divided */ +#define MD_RCU_HPRE_SYSCLK_DIV_2 (0x00000008UL) /** @brief SYSCLK divided by 2 */ +#define MD_RCU_HPRE_SYSCLK_DIV_4 (0x00000009UL) /** @brief SYSCLK divided by 4 */ +#define MD_RCU_HPRE_SYSCLK_DIV_8 (0x0000000AUL) /** @brief SYSCLK divided by 8 */ +#define MD_RCU_HPRE_SYSCLK_DIV_16 (0x0000000BUL) /** @brief SYSCLK divided by 16 */ +/** + * @} MD_RCU_AHB_CLK_DIV + */ + +/** @defgroup MD_RCU_SYS_CLK_SW System clock switch(SYSCLK) + * @{ + */ +#define MD_RCU_SYSCLK_HRC (0x00000000UL) /** @brief HRC selected as system clock */ +#define MD_RCU_SYSCLK_HOSC (0x00000001UL) /** @brief HOSC selected as system clock */ +#define MD_RCU_SYSCLK_LRC (0x00000002UL) /** @brief LRC selected as system clock */ +#define MD_RCU_SYSCLK_LOSC (0x00000003UL) /** @brief LOSC selected as system clock */ +#define MD_RCU_SYSCLK_PLL0 (0x00000004UL) /** @brief PLL0 selected as system clock */ +/** + * @} MD_RCU_SYS_CLK_SW + */ + +/** @defgroup MD_RCU_PSCK_I2S2CKSL SPI2/I2S2 External Clock Source Select + * @{ + */ +#define MD_RCU_PSCK_I2S2CKSL_DISABLE (0x00000000UL) /** @brief Disable External Clock (default value) */ +#define MD_RCU_PSCK_I2S2CKSL_I2SCLK1 (0x00000001UL) +#define MD_RCU_PSCK_I2S2CKSL_I2SCLK2 (0x00000002UL) +/** + * @} MD_RCU_PSCK_I2S2CKSL + */ + +/** @defgroup MD_RCU_PSCK_I2S1CKSL SPI1/I2S1 External Clock Source Select + * @{ + */ +#define MD_RCU_PSCK_I2S1CKSL_DISABLE (0x00000000UL) /** @brief Disable External Clock (default value) */ +#define MD_RCU_PSCK_I2S1CKSL_I2SCLK1 (0x00000001UL) +#define MD_RCU_PSCK_I2S1CKSL_I2SCLK2 (0x00000002UL) +/** + * @} MD_RCU_PSCK_I2S1CKSL + */ + + +/** + * @} MD_RCU_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Macros RCU Public Macros + * @{ + */ + +/** + * @brief Get System clock switch ready flag + * @note This bit is set by hardware to indicate that the system clock change is stable. + * When the CKCFG bit was set and finish configuartion process. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_SWRDY_NOT_READY + * @arg @ref MD_RCU_SWRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_swrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_SWRDY_MSK)>>RCU_CON_SWRDY_POS); +} +/** + * @brief Get Clock Security System flag + * @note This bit is reset by software by writing the CSSON bit. + * It is set by hardware in case of HOSC clock failure. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_CSSFLG_NO_FAIL + * @arg @ref MD_RCU_CSSFLG_FAIL + */ +__STATIC_INLINE uint32_t md_rcu_get_con_cssflg(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_CSSFLG_MSK)>>RCU_CON_CSSFLG_POS); +} +/** + * @brief Get PLL1 clock ready flag + * @note This bit is set by hardware to indicate that the PLL1 oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PLL1_NOT_READY + * @arg @ref MD_RCU_PLL1_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll1rdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL1RDY_MSK)>>RCU_CON_PLL1RDY_POS); +} +/** + * @brief Get PLL0 clock ready flag + * @note This bit is set by hardware to indicate that the PLL0 oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PLL0_NOT_READY + * @arg @ref MD_RCU_PLL0_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll0rdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL0RDY_MSK)>>RCU_CON_PLL0RDY_POS); +} +/** + * @brief Get LOSCRDY clock ready flag + * @note This bit is set by hardware to indicate that the LOSC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_LOSCRDY_NOT_READY + * @arg @ref MD_RCU_LOSCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_loscrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LOSCRDY_MSK)>>RCU_CON_LOSCRDY_POS); +} +/** + * @brief Get LRCRDY clock ready flag + * @note This bit is set by hardware to indicate that the LRC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_LRCRDY_NOT_READY + * @arg @ref MD_RCU_LRCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_lrcrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LRCRDY_MSK)>>RCU_CON_LRCRDY_POS); +} +/** + * @brief Get HOSCRDY clock ready flag + * @note This bit is set by hardware to indicate that the HOSC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HOSCRDY_NOT_READY + * @arg @ref MD_RCU_HOSCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hoscrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCRDY_MSK)>>RCU_CON_HOSCRDY_POS); +} +/** + * @brief Get HRCRDY clock ready flag + * @note This bit is set by hardware to indicate that the HRC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HRCRDY_NOT_READY + * @arg @ref MD_RCU_HRCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hrcrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRCRDY_MSK)>>RCU_CON_HRCRDY_POS); +} +/** + * @brief Clock security system enable(CSS) + * @note Set and cleared by software to enable the clock security system. + * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, + * and disabled by hardware if a HOSC clock failure is detected. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_csson(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_CSSON_MSK); +} +/** + * @brief Clock security system disable(CSS) + * @note Set and cleared by software to enable the clock security system. + * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, + * and disabled by hardware if a HOSC clock failure is detected. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_csson(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_CSSON_MSK); +} +/** + * @brief Get Clock security system (CSS) + * @note Set and cleared by software to enable the clock security system. + * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, + * and disabled by hardware if a HOSC clock failure is detected. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_csson(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_CSSON_MSK)>>RCU_CON_CSSON_POS); +} +/** + * @brief PLL1 enable bit(for USB PHY) + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_pll1on(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_PLL1ON_MSK); +} +/** + * @brief PLL1 disable bit(for USB PHY) + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_pll1on(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_PLL1ON_MSK); +} +/** + * @brief Get PLL1 bit(for USB PHY) + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll1on(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL1ON_MSK)>>RCU_CON_PLL1ON_POS); +} +/** + * @brief PLL0 enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_pll0on(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_PLL0ON_MSK); +} +/** + * @brief PLL0 disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_pll0on(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_PLL0ON_MSK); +} +/** + * @brief Get PLL0 bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll0on(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL0ON_MSK)>>RCU_CON_PLL0ON_POS); +} +/** + * @brief External low speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_loscon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_LOSCON_MSK); +} +/** + * @brief External low speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_loscon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_LOSCON_MSK); +} +/** + * @brief Get External low speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_loscon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LOSCON_MSK)>>RCU_CON_LOSCON_POS); +} +/** + * @brief Internal low speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_lrcon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_LRCON_MSK); +} +/** + * @brief Internal low speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_lrcon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_LRCON_MSK); +} +/** + * @brief Get Internal low speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_lrcon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LRCON_MSK)>>RCU_CON_LRCON_POS); +} +/** + * @brief External high speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_hoscon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HOSCON_MSK); +} +/** + * @brief External high speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_hoscon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HOSCON_MSK); +} +/** + * @brief Get External high speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hoscon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCON_MSK)>>RCU_CON_HOSCON_POS); +} +/** + * @brief Internal high speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_hrcon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HRCON_MSK); +} +/** + * @brief Internal high speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_hrcon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HRCON_MSK); +} +/** + * @brief Get Internal high speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hrcon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRCON_MSK)>>RCU_CON_HRCON_POS); +} + +/** @defgroup MD_RCU_CON_CSSON CSSON + * @brief Set Clock security system bit for md_rcu_set_con() function used + * @param csson This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_con_csson_fun(csson) (csson<CON, (csson|pll1on|pll0on|loscon|lrcon|hoscon|hrcon)); +} + +/** + * @brief Clock configuration set bit + * @note This bit is write-only. A read to this bit returns the value 0. + * If set is bit to high, start to configurate clock setting. + * When the clock configuration process was finished, this bit was clear to zero by self. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_ckcfg(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CFG, RCU_CFG_CKCFG_MSK); +} +/** + * @brief Set Microcontroller clock output prescaler + * @note Output Frequency = MCO/(MPRE+1) + * @param rcu RCU Instance + * @param mpre This parameter can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_mpre(RCU_TypeDef *rcu, uint32_t mpre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_MPRE_MSK, (mpre<CFG, RCU_CFG_MPRE_MSK)>>RCU_CFG_MPRE_POSS); +} +/** + * @brief Set Microcontroller clock output (MCO) + * @param rcu RCU Instance + * @param msw This parameter can be one of the following values: + * @arg @ref MD_RCU_MCO_DISABLE + * @arg @ref MD_RCU_MCO_LRC + * @arg @ref MD_RCU_MCO_LOSC + * @arg @ref MD_RCU_MCO_HRC + * @arg @ref MD_RCU_MCO_HOSC + * @arg @ref MD_RCU_MCO_PLL0 + * @arg @ref MD_RCU_MCO_PLL1 + * @arg @ref MD_RCU_MCO_SYSCLK + * @arg @ref MD_RCU_MCO_HCLK + * @arg @ref MD_RCU_MCO_PCLK + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_msw(RCU_TypeDef *rcu, uint32_t msw) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_MSW_MSK, (msw<CFG, RCU_CFG_MSW_MSK)>>RCU_CFG_MSW_POSS); +} +/** + * @brief Set PLL0 multiplication factor + * @note PLL0 output clock frequency is 4*(PLL0MUL+1)MHz + * @param rcu RCU Instance + * @param pllmul can be one of the following values: + * @arg Max Value 31 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_pllmul(RCU_TypeDef *rcu, uint32_t pllmul) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PLLMUL_MSK, (pllmul<CFG, RCU_CFG_PLLMUL_MSK)>>RCU_CFG_PLLMUL_POSS); +} +/** + * @brief Set PLL0/1 reference clock source + * @param rcu RCU Instance + * @param pllsrc This parameter can be one of the following values: + * @arg @ref MD_RCU_PLL_SRC_HRC + * @arg @ref MD_RCU_PLL_SRC_HOSCDIV + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_pllsrc(RCU_TypeDef *rcu, uint32_t pllsrc) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PLLSRC_MSK, (pllsrc<CFG, RCU_CFG_PLLSRC_MSK)>>RCU_CFG_PLLSRC_POS); +} +/** + * @brief Set HOSC clock division factor for PLL0/1 reference clock 4 MHz + * @note These bits are set and cleared by software to select HOSCDIV division factor. + * @note PLL_reference_clock (4 MHz) = HOSC / (HOSCDIV+1) + * @param rcu RCU Instance + * @param hoscdiv can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_hoscdiv(RCU_TypeDef *rcu, uint32_t hoscdiv) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_HOSCDIV_MSK, (hoscdiv<CFG, RCU_CFG_HOSCDIV_MSK)>>RCU_CFG_HOSCDIV_POSS); +} +/** + * @brief Set APB clock prescaler(PCLK) + * @param rcu RCU Instance + * @param ppre The retval can be one of the following values: + * @arg @ref MD_RCU_PPRE_HCLK_DIV_1 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_2 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_4 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_8 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_ppre(RCU_TypeDef *rcu, uint32_t ppre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PPRE_MSK, (ppre<CFG, RCU_CFG_PPRE_MSK)>>RCU_CFG_PPRE_POSS); +} +/** + * @brief Set AHB clock prescaler(HCLK) + * @param rcu RCU Instance + * @param hpre can be one of the following values: + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_1 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_2 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_4 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_8 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_hpre(RCU_TypeDef *rcu, uint32_t hpre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_HPRE_MSK, (hpre<CFG, RCU_CFG_HPRE_MSK)>>RCU_CFG_HPRE_POSS); +} +/** + * @brief Set System clock switch(SYSCLK) + * @param rcu RCU Instance + * @param sw can be one of the following values: + * @arg @ref MD_RCU_SYSCLK_HRC + * @arg @ref MD_RCU_SYSCLK_HOSC + * @arg @ref MD_RCU_SYSCLK_LRC + * @arg @ref MD_RCU_SYSCLK_LOSC + * @arg @ref MD_RCU_SYSCLK_PLL0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_sw(RCU_TypeDef *rcu, uint32_t sw) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_SW_MSK, (sw<CFG, RCU_CFG_SW_MSK)>>RCU_CFG_SW_POSS); +} +/** @defgroup MD_RCU_CFG_MPRE MPRE + * @brief Set Microcontroller clock output prescaler bit for md_rcu_set_cfg() function used + * @param mpre This parameter can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @{ + */ +#define md_rcu_set_cfg_mpre_fun(mpre) (mpre<CFG, (mpre|msw|pllmul|pllsrc|hoscdiv|ppre|hpre|sw)); +} + +/** + * @brief Set SPI2/I2S2 External Clock Source Select + * @param rcu RCU Instance + * @param i2s2ckdl This parameter can be one of the following values: + * @arg @ref MD_RCU_PSCK_I2S2CKSL_DISABLE + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK1 + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK2 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_psck_i2s2ckdl(RCU_TypeDef *rcu, uint32_t i2s2ckdl) +{ + MODIFY_REG(rcu->PSCK, RCU_PSCK_I2S2CKSL_MSK, (i2s2ckdl<PSCK, RCU_PSCK_I2S2CKSL_MSK)>>RCU_PSCK_I2S2CKSL_POSS); +} +/** + * @brief Set SPI1/I2S1 External Clock Source Select + * @param rcu RCU Instance + * @param i2s1ckdl This parameter can be one of the following values: + * @arg @ref MD_RCU_PSCK_I2S1CKSL_DISABLE + * @arg @ref MD_RCU_PSCK_I2S1CKSL_I2SCLK1 + * @arg @ref MD_RCU_PSCK_I2S1CKSL_I2SCLK2 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_psck_i2s1ckdl(RCU_TypeDef *rcu, uint32_t i2s1ckdl) +{ + MODIFY_REG(rcu->PSCK, RCU_PSCK_I2S1CKSL_MSK, (i2s1ckdl<PSCK, RCU_PSCK_I2S1CKSL_MSK)>>RCU_PSCK_I2S1CKSL_POSS); +} + +/** @defgroup MD_RCU_PSCK_I2S2CKSL_ I2S2CKSL + * @brief Set SPI2/I2S2 External Clock Source Select bit for md_rcu_set_psck() function used + * @param i2s2ckdl This parameter can be one of the following values: + * @arg @ref MD_RCU_PSCK_I2S2CKSL_DISABLE + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK1 + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK2 + * @{ + */ +#define md_rcu_set_psck_i2s2ckdl_fun(i2s2ckdl) (i2s2ckdl<PSCK, (i2s2ckdl|i2s1ckdl)); +} + +/** + * @brief GPIOD reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK); +} +/** + * @brief GPIOD reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK); +} +/** + * @brief Get GPIOD reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK)>>RCU_AHBRST_GPDEN_POS); +} +/** + * @brief GPIOC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK); +} +/** + * @brief GPIOC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK); +} +/** + * @brief Get GPIOC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK)>>RCU_AHBRST_GPCEN_POS); +} +/** + * @brief GPIOB reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK); +} +/** + * @brief GPIOB reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK); +} +/** + * @brief Get GPIOB reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK)>>RCU_AHBRST_GPBEN_POS); +} +/** + * @brief GPIOA reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK); +} +/** + * @brief GPIOA reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK); +} +/** + * @brief Get GPIOA reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK)>>RCU_AHBRST_GPAEN_POS); +} +/** + * @brief HDIV reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK); +} +/** + * @brief HDIV reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK); +} +/** + * @brief Get HDIV reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK)>>RCU_AHBRST_HDIVEN_POS); +} +/** + * @brief USB reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK); +} +/** + * @brief USB reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK); +} +/** + * @brief Get USB reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK)>>RCU_AHBRST_USBEN_POS); +} +/** + * @brief AES reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK); +} +/** + * @brief AES reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK); +} +/** + * @brief Get AES reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK)>>RCU_AHBRST_AESEN_POS); +} +/** + * @brief CRC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK); +} +/** + * @brief CRC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK); +} +/** + * @brief Get CRC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK)>>RCU_AHBRST_CRCEN_POS); +} +/** + * @brief RTC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK); +} +/** + * @brief RTC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK); +} +/** + * @brief Get RTC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK)>>RCU_AHBRST_RTCEN_POS); +} +/** + * @brief DMA1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK); +} +/** + * @brief DMA1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK); +} +/** + * @brief Get DMA1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK)>>RCU_AHBRST_DMA1EN_POS); +} + +/** @defgroup MD_RCU_AHBRST_GPDEN GPDEN + * @brief Set GPIOD reset request bit for md_rcu_set_ahbrst() function used + * @param gpden This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_ahbrst_gpden_fun(gpden) (gpden<AHBRST, (gpden|gpcen|gpben|gpaen|hdiven|usben|aesen|crcen|rtcen|dma1en)); +} + +/** + * @brief DAC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK); +} +/** + * @brief DAC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK); +} +/** + * @brief Get DAC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK)>>RCU_APB1RST_DACEN_POS); +} +/** + * @brief I2C2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_i2c2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK); +} +/** + * @brief I2C2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_i2c2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK); +} +/** + * @brief Get I2C2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_i2c2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK)>>RCU_APB1RST_I2C2EN_POS); +} +/** + * @brief I2C1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK); +} +/** + * @brief I2C1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK); +} +/** + * @brief Get I2C1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK)>>RCU_APB1RST_I2C1EN_POS); +} +/** + * @brief SUART2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK); +} +/** + * @brief SUART2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK); +} +/** + * @brief Get SUART2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK)>>RCU_APB1RST_SUART2EN_POS); +} +/** + * @brief SUART1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK); +} +/** + * @brief SUART1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK); +} +/** + * @brief Get SUART1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK)>>RCU_APB1RST_SUART1EN_POS); +} +/** + * @brief UART3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK); +} +/** + * @brief UART3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK); +} +/** + * @brief Get UART3 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK)>>RCU_APB1RST_UART3EN_POS); +} +/** + * @brief UART2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK); +} +/** + * @brief UART2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK); +} +/** + * @brief Get UART2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK)>>RCU_APB1RST_UART2EN_POS); +} +/** + * @brief SPI2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK); +} +/** + * @brief SPI2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK); +} +/** + * @brief Get SPI2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK)>>RCU_APB1RST_SPI2EN_POS); +} +/** + * @brief IWDT reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK); +} +/** + * @brief IWDT reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_iwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK); +} +/** + * @brief Get IWDT reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK)>>RCU_APB1RST_IWDTEN_POS); +} +/** + * @brief WWDT reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK); +} +/** + * @brief WWDT reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK); +} +/** + * @brief Get WWDT reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK)>>RCU_APB1RST_WWDTEN_POS); +} +/** + * @brief BS16T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK); +} +/** + * @brief BS16T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK)>>RCU_APB1RST_BS16T1EN_POS); +} +/** + * @brief GP16C4T3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK)>>RCU_APB1RST_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK)>>RCU_APB1RST_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK)>>RCU_APB1RST_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK)>>RCU_APB1RST_GP32C4T1EN_POS); +} + +/** @defgroup MD_RCU_APB1RST_DACEN DACEN + * @brief Set DAC reset request bit for md_rcu_set_apb1rst() function used + * @param dacen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb1rst_dacen_fun(dacen) (dacen<APB1RST, (dacen|i2c2en|i2c1en|suart2en|suart1en|uart3en|uart2en|spi2en|iwdten|wwdten| + bs16t1en|gp16c4t3en|gp16c4t2en|gp16c4t1en|gp32c4t1en)); +} + +/** + * @brief CMP reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK); +} +/** + * @brief CMP reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK); +} +/** + * @brief Get CMP reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK)>>RCU_APB2RST_CMPEN_POS); +} +/** + * @brief GP16C2T4 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK)>>RCU_APB2RST_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK)>>RCU_APB2RST_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK)>>RCU_APB2RST_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK)>>RCU_APB2RST_GP16C2T1EN_POS); +} +/** + * @brief UART1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK); +} +/** + * @brief UART1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK); +} +/** + * @brief Get UART1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK)>>RCU_APB2RST_UART1EN_POS); +} +/** + * @brief SPI1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK); +} +/** + * @brief SPI1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK); +} +/** + * @brief Get SPI1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK)>>RCU_APB2RST_SPI1EN_POS); +} +/** + * @brief AD16C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK)>>RCU_APB2RST_AD16C4T1EN_POS); +} +/** + * @brief ADC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK); +} +/** + * @brief ADC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK); +} +/** + * @brief Get ADC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK)>>RCU_APB2RST_ADCEN_POS); +} + +/** @defgroup MD_RCU_APB2RST_CMPEN CMPEN + * @brief Set CMP reset request bit for md_rcu_set_apb2rst() function used + * @param cmpen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb2rst_cmpen_fun(cmpen) (cmpen<APB2RST, (cmpen|gp16c2t4en|gp16c2t3en|gp16c2t2en|gp16c2t1en|uart1en|spi1en|ad16c4t1en|adcen)); +} + +/** + * @brief GPIOD clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK); +} +/** + * @brief GPIOD Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK); +} +/** + * @brief Get GPIOD Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK)>>RCU_AHBEN_GPDEN_POS); +} +/** + * @brief GPIOC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK); +} +/** + * @brief GPIOC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK); +} +/** + * @brief Get GPIOC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK)>>RCU_AHBEN_GPCEN_POS); +} +/** + * @brief GPIOB clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK); +} +/** + * @brief GPIOB Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK); +} +/** + * @brief Get GPIOB Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK)>>RCU_AHBEN_GPBEN_POS); +} +/** + * @brief GPIOA clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK); +} +/** + * @brief GPIOA Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK); +} +/** + * @brief Get GPIOA Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK)>>RCU_AHBEN_GPAEN_POS); +} +/** + * @brief HDIV clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK); +} +/** + * @brief HDIV Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK); +} +/** + * @brief Get HDIV Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK)>>RCU_AHBEN_HDIVEN_POS); +} +/** + * @brief USB clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK); +} +/** + * @brief USB Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK); +} +/** + * @brief Get USB Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK)>>RCU_AHBEN_USBEN_POS); +} +/** + * @brief AES clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK); +} +/** + * @brief AES Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK); +} +/** + * @brief Get AES Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK)>>RCU_AHBEN_AESEN_POS); +} +/** + * @brief CRC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK); +} +/** + * @brief CRC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK); +} +/** + * @brief Get CRC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK)>>RCU_AHBEN_CRCEN_POS); +} +/** + * @brief RTC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK); +} +/** + * @brief RTC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK); +} +/** + * @brief Get RTC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK)>>RCU_AHBEN_RTCEN_POS); +} +/** + * @brief DMA1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK); +} +/** + * @brief DMA1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK); +} +/** + * @brief Get DMA1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK)>>RCU_AHBEN_DMA1EN_POS); +} + +/** @defgroup MD_RCU_AHBEN_GPDEN GPDEN + * @brief Set GPIOD clock bit for md_rcu_set_ahben() function used + * @param gpden This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_ahben_gpden_fun(gpden) (gpden<AHBEN, (gpden|gpcen|gpben|gpaen|hdiven|usben|aesen|crcen|rtcen|dma1en)); +} + +/** + * @brief DAC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK); +} +/** + * @brief DAC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK); +} +/** + * @brief Get DAC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK)>>RCU_APB1EN_DACEN_POS); +} +/** + * @brief I2C2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_i2c2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK); +} +/** + * @brief I2C2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_i2c2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK); +} +/** + * @brief Get I2C2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_i2c2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK)>>RCU_APB1EN_I2C2EN_POS); +} +/** + * @brief I2C1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK); +} +/** + * @brief I2C1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK); +} +/** + * @brief Get I2C1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK)>>RCU_APB1EN_I2C1EN_POS); +} +/** + * @brief SUART2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK); +} +/** + * @brief SUART2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK); +} +/** + * @brief Get SUART2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK)>>RCU_APB1EN_SUART2EN_POS); +} +/** + * @brief SUART1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK); +} +/** + * @brief SUART1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK); +} +/** + * @brief Get SUART1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK)>>RCU_APB1EN_SUART1EN_POS); +} +/** + * @brief UART3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK); +} +/** + * @brief UART3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK); +} +/** + * @brief Get UART3 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK)>>RCU_APB1EN_UART3EN_POS); +} +/** + * @brief UART2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK); +} +/** + * @brief UART2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK); +} +/** + * @brief Get UART2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK)>>RCU_APB1EN_UART2EN_POS); +} +/** + * @brief SPI2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK); +} +/** + * @brief SPI2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK); +} +/** + * @brief Get SPI2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK)>>RCU_APB1EN_SPI2EN_POS); +} +/** + * @brief IWDT clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK); +} +/** + * @brief IWDT Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_iwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK); +} +/** + * @brief Get IWDT Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK)>>RCU_APB1EN_IWDTEN_POS); +} +/** + * @brief WWDT clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK); +} +/** + * @brief WWDT Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK); +} +/** + * @brief Get WWDT Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK)>>RCU_APB1EN_WWDTEN_POS); +} +/** + * @brief BS16T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK); +} +/** + * @brief BS16T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK)>>RCU_APB1EN_BS16T1EN_POS); +} +/** + * @brief GP16C4T3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK)>>RCU_APB1EN_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK)>>RCU_APB1EN_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK)>>RCU_APB1EN_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK)>>RCU_APB1EN_GP32C4T1EN_POS); +} + +/** @defgroup MD_RCU_APB1EN_DACEN DACEN + * @brief Set DAC clock bit for md_rcu_set_apb1en() function used + * @param dacen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb1en_dacen_fun(dacen) (dacen<APB1EN, (dacen|i2c2en|i2c1en|suart2en|suart1en|uart3en|uart2en|spi2en|iwdten|wwdten| + bs16t1en|gp16c4t3en|gp16c4t2en|gp16c4t1en|gp32c4t1en)); +} + +/** + * @brief CMP clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK); +} +/** + * @brief CMP Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK); +} +/** + * @brief Get CMP Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK)>>RCU_APB2EN_CMPEN_POS); +} +/** + * @brief GP16C2T4EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK)>>RCU_APB2EN_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK)>>RCU_APB2EN_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK)>>RCU_APB2EN_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK)>>RCU_APB2EN_GP16C2T1EN_POS); +} +/** + * @brief UART1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK); +} +/** + * @brief UART1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK); +} +/** + * @brief Get UART1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK)>>RCU_APB2EN_UART1EN_POS); +} +/** + * @brief SPI1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK); +} +/** + * @brief SPI1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK); +} +/** + * @brief Get SPI1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK)>>RCU_APB2EN_SPI1EN_POS); +} +/** + * @brief AD16C4T1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK)>>RCU_APB2EN_AD16C4T1EN_POS); +} +/** + * @brief ADCEN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK); +} +/** + * @brief ADCEN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK); +} +/** + * @brief Get ADCEN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK)>>RCU_APB2EN_ADCEN_POS); +} + +/** @defgroup MD_RCU_APB2EN_CMPEN CMPEN + * @brief Set CMP clock bit for md_rcu_set_apb2en() function used + * @param cmpen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb2en_cmpen_fun(cmpen) (cmpen<APB2EN, (cmpen|gp16c2t4en|gp16c2t3en|gp16c2t2en|gp16c2t1en|uart1en|spi1en|ad16c4t1en|adcen)); +} + + + + + + + + + + +/** + * @brief GPDEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK); +} +/** + * @brief GPDEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK); +} +/** + * @brief Get GPDEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK)>>RCU_AHBSL_GPDEN_POS); +} +/** + * @brief GPCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK); +} +/** + * @brief GPCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK); +} +/** + * @brief Get GPCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK)>>RCU_AHBSL_GPCEN_POS); +} +/** + * @brief GPBEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK); +} +/** + * @brief GPBEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK); +} +/** + * @brief Get GPBEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK)>>RCU_AHBSL_GPBEN_POS); +} +/** + * @brief GPAEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK); +} +/** + * @brief GPAEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK); +} +/** + * @brief Get GPAEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK)>>RCU_AHBSL_GPAEN_POS); +} +/** + * @brief HDIVEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK); +} +/** + * @brief HDIVEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK); +} +/** + * @brief Get HDIVEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK)>>RCU_AHBSL_HDIVEN_POS); +} +/** + * @brief USBEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK); +} +/** + * @brief USBEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK); +} +/** + * @brief Get USBEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK)>>RCU_AHBSL_USBEN_POS); +} +/** + * @brief AESEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK); +} +/** + * @brief AESEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK); +} +/** + * @brief Get AESEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK)>>RCU_AHBSL_AESEN_POS); +} +/** + * @brief CRCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK); +} +/** + * @brief CRCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK); +} +/** + * @brief Get CRCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK)>>RCU_AHBSL_CRCEN_POS); +} +/** + * @brief RTCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK); +} +/** + * @brief RTCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK); +} +/** + * @brief Get RTCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK)>>RCU_AHBSL_RTCEN_POS); +} +/** + * @brief DMA1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK); +} +/** + * @brief DMA1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK); +} +/** + * @brief Get DMA1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK)>>RCU_AHBSL_DMA1EN_POS); +} + +/** + * @brief DAC clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK); +} +/** + * @brief DAC clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK); +} +/** + * @brief Get DAC clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK)>>RCU_APB1SL_DACEN_POS); +} +/** + * @brief I2C2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_i2c2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK); +} +/** + * @brief I2C2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_i2c2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK); +} +/** + * @brief Get I2C2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_i2c2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK)>>RCU_APB1SL_I2C2EN_POS); +} +/** + * @brief I2C1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK); +} +/** + * @brief I2C1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK); +} +/** + * @brief Get I2C1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK)>>RCU_APB1SL_I2C1EN_POS); +} +/** + * @brief SUART2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK); +} +/** + * @brief SUART2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK); +} +/** + * @brief Get SUART2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK)>>RCU_APB1SL_SUART2EN_POS); +} +/** + * @brief SUART1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK); +} +/** + * @brief SUART1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK); +} +/** + * @brief Get SUART1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK)>>RCU_APB1SL_SUART1EN_POS); +} +/** + * @brief UART3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK); +} +/** + * @brief UART3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK); +} +/** + * @brief Get UART3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK)>>RCU_APB1SL_UART3EN_POS); +} +/** + * @brief UART2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK); +} +/** + * @brief UART2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK); +} +/** + * @brief Get UART2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK)>>RCU_APB1SL_UART2EN_POS); +} +/** + * @brief SPI2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK); +} +/** + * @brief SPI2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK); +} +/** + * @brief Get SPI2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK)>>RCU_APB1SL_SPI2EN_POS); +} +/** + * @brief IWDTEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK); +} +/** + * @brief IWDTEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_iwdgen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK); +} +/** + * @brief Get IWDTEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK)>>RCU_APB1SL_IWDTEN_POS); +} +/** + * @brief WWDTEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK); +} +/** + * @brief WWDTEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK); +} +/** + * @brief Get WWDTEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK)>>RCU_APB1SL_WWDTEN_POS); +} +/** + * @brief BS16T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK); +} +/** + * @brief BS16T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK)>>RCU_APB1SL_BS16T1EN_POS); +} +/** + * @brief GP16C4T3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK)>>RCU_APB1SL_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). +y*/ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK)>>RCU_APB1SL_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK)>>RCU_APB1SL_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK)>>RCU_APB1SL_GP32C4T1EN_POS); +} + +/** + * @brief CMP clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK); +} +/** + * @brief CMP clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK); +} +/** + * @brief Get CMP clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK)>>RCU_APB2SL_CMPEN_POS); +} +/** + * @brief GP16C2T4EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK)>>RCU_APB2SL_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK)>>RCU_APB2SL_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK)>>RCU_APB2SL_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK)>>RCU_APB2SL_GP16C2T1EN_POS); +} +/** + * @brief UART1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK); +} +/** + * @brief UART1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK); +} +/** + * @brief Get UART1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK)>>RCU_APB2SL_UART1EN_POS); +} +/** + * @brief SPI1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK); +} +/** + * @brief SPI1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK); +} +/** + * @brief Get SPI1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK)>>RCU_APB2SL_SPI1EN_POS); +} +/** + * @brief AD16C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK)>>RCU_APB2SL_AD16C4T1EN_POS); +} +/** + * @brief ADCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK); +} +/** + * @brief ADCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK); +} +/** + * @brief Get ADCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK)>>RCU_APB2SL_ADCEN_POS); +} + +/** + * @brief GPIOD clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK); +} +/** + * @brief GPIOD clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK); +} +/** + * @brief Get GPIOD clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK)>>RCU_AHBDSL_GPDEN_POS); +} +/** + * @brief GPIOC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK); +} +/** + * @brief GPIOC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK); +} +/** + * @brief Get GPIOC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK)>>RCU_AHBDSL_GPCEN_POS); +} +/** + * @brief GPIOB clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK); +} +/** + * @brief GPIOB clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK); +} +/** + * @brief Get GPIOB clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK)>>RCU_AHBDSL_GPBEN_POS); +} +/** + * @brief GPIOA clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK); +} +/** + * @brief GPIOA clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK); +} +/** + * @brief Get GPIOA clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK)>>RCU_AHBDSL_GPAEN_POS); +} +/** + * @brief HDIV clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK); +} +/** + * @brief HDIV clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK); +} +/** + * @brief Get HDIV clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK)>>RCU_AHBDSL_HDIVEN_POS); +} +/** + * @brief USB clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK); +} +/** + * @brief USB clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK); +} +/** + * @brief Get USB clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK)>>RCU_AHBDSL_USBEN_POS); +} +/** + * @brief AES clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK); +} +/** + * @brief AES clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK); +} +/** + * @brief Get AES clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK)>>RCU_AHBDSL_AESEN_POS); +} +/** + * @brief CRC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK); +} +/** + * @brief CRC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK); +} +/** + * @brief Get CRC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK)>>RCU_AHBDSL_CRCEN_POS); +} +/** + * @brief RTC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK); +} +/** + * @brief RTC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK); +} +/** + * @brief Get RTC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK)>>RCU_AHBDSL_RTCEN_POS); +} +/** + * @brief DMA1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK); +} +/** + * @brief DMA1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK); +} +/** + * @brief Get DMA1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK)>>RCU_AHBDSL_DMA1EN_POS); +} + +/** + * @brief DAC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK); +} +/** + * @brief DAC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK); +} +/** + * @brief Get DAC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK)>>RCU_APB1DSL_DACEN_POS); +} +/** + * @brief I2C2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_apb1dslen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK); +} +/** + * @brief I2C2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_apb1dslen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK); +} +/** + * @brief Get I2C2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_apb1dslen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK)>>RCU_APB1DSL_I2C2EN_POS); +} +/** + * @brief I2C1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK); +} +/** + * @brief I2C1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK); +} +/** + * @brief Get I2C1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK)>>RCU_APB1DSL_I2C1EN_POS); +} +/** + * @brief SUART2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK); +} +/** + * @brief SUART2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK); +} +/** + * @brief Get SUART2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK)>>RCU_APB1DSL_SUART2EN_POS); +} +/** + * @brief SUART1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK); +} +/** + * @brief SUART1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK); +} +/** + * @brief Get SUART1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK)>>RCU_APB1DSL_SUART1EN_POS); +} +/** + * @brief UART3 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK); +} +/** + * @brief UART3 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK); +} +/** + * @brief Get UART3 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK)>>RCU_APB1DSL_UART3EN_POS); +} +/** + * @brief UART2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK); +} +/** + * @brief UART2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK); +} +/** + * @brief Get UART2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK)>>RCU_APB1DSL_UART2EN_POS); +} +/** + * @brief SPI2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK); +} +/** + * @brief SPI2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK); +} +/** + * @brief Get SPI2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK)>>RCU_APB1DSL_SPI2EN_POS); +} +/** + * @brief IWDT clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK); +} +/** + * @brief IWDT clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_iwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK); +} +/** + * @brief Get IWDT clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK)>>RCU_APB1DSL_IWDTEN_POS); +} +/** + * @brief WWDT clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK); +} +/** + * @brief WWDT clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK); +} +/** + * @brief Get WWDT clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK)>>RCU_APB1DSL_WWDTEN_POS); +} +/** + * @brief BS16T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK); +} +/** + * @brief BS16T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK)>>RCU_APB1DSL_BS16T1EN_POS); +} +/** + * @brief GP16C4T3 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK)>>RCU_APB1DSL_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK)>>RCU_APB1DSL_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK)>>RCU_APB1DSL_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK)>>RCU_APB1DSL_GP32C4T1EN_POS); +} + +/** + * @brief CMP clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK); +} +/** + * @brief CMP clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK); +} +/** + * @brief Get CMP clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK)>>RCU_APB2DSL_CMPEN_POS); +} +/** + * @brief GP16C2T4 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK)>>RCU_APB2DSL_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK)>>RCU_APB2DSL_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK)>>RCU_APB2DSL_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK)>>RCU_APB2DSL_GP16C2T1EN_POS); +} +/** + * @brief UART1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK); +} +/** + * @brief UART1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK); +} +/** + * @brief Get UART1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK)>>RCU_APB2DSL_UART1EN_POS); +} +/** + * @brief SPI1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK); +} +/** + * @brief SPI1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK); +} +/** + * @brief Get SPI1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK)>>RCU_APB2DSL_SPI1EN_POS); +} +/** + * @brief AD16C4T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK)>>RCU_APB2DSL_AD16C4T1EN_POS); +} +/** + * @brief ADC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK); +} +/** + * @brief ADC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK); +} +/** + * @brief Get ADC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK)>>RCU_APB2DSL_ADCEN_POS); +} + +/** + * @} MD_RCU_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ + +/** @defgroup MD_RCU_PF_Basic_Configuration Basic Configuration + * @{ + */ +void md_rcu_init(void); +void md_rcu_init_set(RCU_TypeDef *, md_rcu_init_typedef *); +void md_rcu_pllreinit(uint8_t); +/** + * @} MD_RCU_PF_Basic_Configuration + */ + +/** + * @} MD_RCU_Public_Functions + */ + +#endif + +/** + * @} RCU + */ + +/** + * @} Micro_Driver + */ +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..4de23ae6289047d60cd0bbb71b4993641a5eaf74 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h @@ -0,0 +1,2785 @@ +/** + ****************************************************************************** + * @file md_RTC.h + * @brief ES32F0271 RTC HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_RTC_H__ +#define __MD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_rtc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (RTC) + +/** @defgroup RTC RTC + * @brief RTC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_RTC_PT_INIT RTC Public Init structures + * @{ + */ + +/** + * @brief MD RTC Init Structure definition + */ + + +/** + * @} MD_RTC_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_RTC_Public_Constants RTC Public Constants + * @{ + */ + +/** @defgroup MD_RTC_CON_MODE_ RTC Clock Calibration Mode + * @{ + */ +#define MD_RTC_CON_MODE_INCR (0x00000000UL) /** @brief Increase calibration value when match calibration cycle. */ +#define MD_RTC_CON_MODE_DECR (0X00000001UL) /** @brief DMA Decrease calibration value when match calibration cycle. */ +/** + * @} MD_RTC_CON_MODE_ + */ + +/** @defgroup MD_RTC_CON_CYCLE_ RTC Calibration Cycle Select + * @{ + */ +#define MD_RTC_CON_CYCLE_60S (0x00000000UL) /** @brief When enable Calibration Function, the calibrate cycle is 60s. */ +#define MD_RTC_CON_CYCLE_1S (0X00000001UL) /** @brief When enable Calibration Function, the calibrate cycle is 1s. */ +/** + * @} MD_RTC_CON_CYCLE_ + */ + +/** @defgroup MD_RTC_CON_CKSEL_ RTC Clock Source Selection + * @{ + */ +#define MD_RTC_CON_CKSEL_NO (0x00000000UL) /** @brief No clock */ +#define MD_RTC_CON_CKSEL_LOSC (0X00000001UL) /** @brief LOSC oscillator clock used as RTC clock */ +#define MD_RTC_CON_CKSEL_LRC (0x00000002UL) /** @brief LRC oscillator clock used as RTC clock */ +#define MD_RTC_CON_CKSEL_PLL (0X00000003UL) /** @brief PLL Reference clock source divided by 128 used as RTC clock */ +/** + * @} MD_RTC_CON_CKSEL_ + */ + +/** @defgroup MD_RTC_WKUP_WKSCAL RTC Wakeup Counter Scale Value + * @{ + */ +#define MD_RTC_WKUP_WKSCAL_DIV1 (0x00000000UL) /** @brief Divide 1, wakeup counter will count each second. */ +#define MD_RTC_WKUP_WKSCAL_DIV2 (0X00000001UL) /** @brief Divide 2, wakeup counter will count each 1/2 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV4 (0x00000002UL) /** @brief Divide 4, wakeup counter will count each 1/4 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV8 (0X00000003UL) /** @brief Divide 8, wakeup counter will count each 1/8 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV16 (0X00000004UL) /** @brief Divide 16, wakeup counter will count each 1/16 second. */ +/** + * @} MD_RTC_WKUP_WKSCAL + */ + +/** @defgroup MD_RTC_WKUP_WKSEL RTC Wakeup Counter Events Select + * @{ + */ +#define MD_RTC_WKUP_WKSEL_OFF (0x00000000UL) /** @brief OFF */ +#define MD_RTC_WKUP_WKSEL_RTC (0X00000001UL) /** @brief Start counter when RTC start. */ +#define MD_RTC_WKUP_WKSEL_SLEEP (0x00000002UL) /** @brief Start counter when receive sleep flag. */ +/** + * @} MD_RTC_WKUP_WKSEL + */ + +/** @defgroup MD_RTC_STAT_SYNDONE RTC Calendar Synchronization status + * @{ + */ +#define MD_RTC_STAT_SYNDONE_UNDER (0x00000000UL) /** @brief RTC is under Synchronization procedure */ +#define MD_RTC_STAT_SYNDONE_CMP (0X00000001UL) /** @brief RTC Synchronization procedure is Completed */ +/** + * @} MD_RTC_STAT_SYNDONE + */ + +/** @defgroup MD_RTC_BKEN_BKEN Read RTC Backup Register Enable + * @{ + */ +#define MD_RTC_BKEN_BKEN_CONTROL (0x00000000UL) /** @brief Read RTCTIME & RTCCAL From control register. */ +#define MD_RTC_BKEN_BKEN_BACKUP (0X00000001UL) /** @brief Read RTCTIME & RTCCAL From backup register. */ +/** + * @} MD_RTC_BKEN_BKEN + */ + +/** + * @} MD_RTC_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_RTC_Public_Macros RTC Public Macros + * @{ + */ + +/** + * @brief Set RTC Clock Calibration Mode + * @param rtc RTC Instance + * @param mode can be one of the following values: + * @arg @ref MD_RTC_CON_MODE_INCR + * @arg @ref MD_RTC_CON_MODE_DECR + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_mode(RTC_TypeDef *rtc, uint32_t mode) +{ + MODIFY_REG(rtc->CON, RTC_CON_MODE_MSK, (mode<CON, RTC_CON_MODE_MSK)>>RTC_CON_MODE_POS); +} +/** + * @brief Set RTC Clock Calibration Value + * @param rtc RTC Instance + * @param calval Max calibration value is CALV. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_calval(RTC_TypeDef *rtc, uint32_t calval) +{ + MODIFY_REG(rtc->CON, RTC_CON_CALVAL_MSK, (calval<CON, RTC_CON_CALVAL_MSK)>>RTC_CON_CALVAL_POSS); +} +/** + * @brief Set RTC Clock Counter Scale + * @param rtc RTC Instance + * @param scale Max divider of This counter is (SCALE+1). + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_scale(RTC_TypeDef *rtc, uint32_t scale) +{ + MODIFY_REG(rtc->CON, RTC_CON_SCALE_MSK, (scale<CON, RTC_CON_SCALE_MSK)>>RTC_CON_SCALE_POSS); +} +/** + * @brief Set RTC Clock Counter Prescale + * @param rtc RTC Instance + * @param pscale Max divider of This counter is (PSCALE+1). + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_pscale(RTC_TypeDef *rtc, uint32_t pscale) +{ + MODIFY_REG(rtc->CON, RTC_CON_PSCALE_MSK, (pscale<CON, RTC_CON_PSCALE_MSK)>>RTC_CON_PSCALE_POSS); +} +/** + * @brief Set RTC Calibration Cycle Select + * @param rtc RTC Instance + * @param cycle This parameter can be one of the following values: + * @arg @ref MD_RTC_CON_CYCLE_60S + * @arg @ref MD_RTC_CON_CYCLE_1S + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_cycle(RTC_TypeDef *rtc, uint32_t cycle) +{ + MODIFY_REG(rtc->CON, RTC_CON_CYCLE_MSK, (cycle<CON, RTC_CON_CYCLE_MSK)>>RTC_CON_CYCLE_POS); +} +/** + * @brief Set RTC Calibration Function Enable + * @param rtc RTC Instance + * @param calib This parameter can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_calib(RTC_TypeDef *rtc, uint32_t calib) +{ + MODIFY_REG(rtc->CON, RTC_CON_CALIB_MSK, (calib<CON, RTC_CON_CALIB_MSK)>>RTC_CON_CALIB_POS); +} +/** + * @brief Set RTC Clock Source Selection + * @param rtc RTC Instance + * @param cksel This parameter can be one of the following values: + * @arg @ref MD_RTC_CON_CKSEL_NO + * @arg @ref MD_RTC_CON_CKSEL_LOSC + * @arg @ref MD_RTC_CON_CKSEL_LRC + * @arg @ref MD_RTC_CON_CKSEL_PLL + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_cksel(RTC_TypeDef *rtc, uint32_t cksel) +{ + MODIFY_REG(rtc->CON, RTC_CON_CKSEL_MSK, (cksel<CON, RTC_CON_CKSEL_MSK)>>RTC_CON_CKSEL_POSS); +} +/** + * @brief Set RTC Counter Enable bit + * @param rtc RTC Instance + * @param rtcen This parameter can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_rtcen(RTC_TypeDef *rtc, uint32_t rtcen) +{ + MODIFY_REG(rtc->CON, RTC_CON_RTCEN_MSK, (rtcen<CON, RTC_CON_RTCEN_MSK)>>RTC_CON_RTCEN_POS); +} + +/** @defgroup MD_RTC_CON_MODE MODE + * @brief Set RTC Clock Calibration Mode bit for md_rtc_set_con() function used + * @param mode This parameter can be one of the following values: + * @arg @ref MD_RTC_CON_MODE_INCR + * @arg @ref MD_RTC_CON_MODE_DECR + * @{ + */ +#define md_rtc_set_con_mode_fun(mode) (mode<CON, (mode|calval|scale|pscale|cycle|calib|cksel|rtcen)); +} + + +/** + * @brief Set RTC Wakeup Counter Scale Value + * @param rtc RTC Instance + * @param wkscal This parameter can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV1 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV2 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV4 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV8 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV16 + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wkup_wkscal(RTC_TypeDef *rtc, uint32_t wkscal) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSCAL_MSK, (wkscal<WKUP, RTC_WKUP_WKSCAL_MSK)>>RTC_WKUP_WKSCAL_POSS); +} +/** + * @brief Set RTC Wakeup Counter Events Select + * @param rtc RTC Instance + * @param wksel This parameter can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSEL_OFF + * @arg @ref MD_RTC_WKUP_WKSEL_RTC + * @arg @ref MD_RTC_WKUP_WKSEL_SLEEP + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wkup_wksel(RTC_TypeDef *rtc, uint32_t wksel) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSEL_MSK, (wksel<WKUP, RTC_WKUP_WKSEL_MSK)>>RTC_WKUP_WKSEL_POSS); +} +/** + * @brief Set RTC Wakeup Counter setting value + * @param rtc RTC Instance + * @param wkcal Max value is WKCAL seconds + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wkup_wkcal(RTC_TypeDef *rtc, uint32_t wkcal) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKCAL_MSK, (wkcal<WKUP, RTC_WKUP_WKCAL_MSK)>>RTC_WKUP_WKCAL_POSS); +} + + +/** + * @brief Set Week Value + * @param rtc RTC Instance + * @param week value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_week(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_WEEK_MSK, (week<TIME, RTC_TIME_WEEK_MSK)>>RTC_TIME_WEEK_POSS); +} +/** + * @brief Set Hour Tens Value + * @param rtc RTC Instance + * @param hour_t Hour tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_hour_t(RTC_TypeDef *rtc, uint32_t hour_t) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_HOUR_T_MSK, (hour_t<TIME, RTC_TIME_HOUR_T_MSK)>>RTC_TIME_HOUR_T_POSS); +} +/** + * @brief Set Hour Units Value + * @param rtc RTC Instance + * @param hour_u Hour units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_hour_u(RTC_TypeDef *rtc, uint32_t hour_u) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_HOUR_U_MSK, (hour_u<TIME, RTC_TIME_HOUR_U_MSK)>>RTC_TIME_HOUR_U_POSS); +} +/** + * @brief Set Minute Tens Value + * @param rtc RTC Instance + * @param min_t Minute tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_min_t(RTC_TypeDef *rtc, uint32_t min_t) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_MIN_T_MSK, (min_t<TIME, RTC_TIME_MIN_T_MSK)>>RTC_TIME_MIN_T_POSS); +} +/** + * @brief Set Minute Units Value + * @param rtc RTC Instance + * @param min_u Minute units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_min_u(RTC_TypeDef *rtc, uint32_t min_u) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_MIN_U_MSK, (min_u<TIME, RTC_TIME_MIN_U_MSK)>>RTC_TIME_MIN_U_POSS); +} +/** + * @brief Set Second Tens Value + * @param rtc RTC Instance + * @param sec_t Second tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_sec_t(RTC_TypeDef *rtc, uint32_t sec_t) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_SEC_T_MSK, (sec_t<TIME, RTC_TIME_SEC_T_MSK)>>RTC_TIME_SEC_T_POSS); +} +/** + * @brief Set Second Units Value + * @param rtc RTC Instance + * @param sec_u Second units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_sec_u(RTC_TypeDef *rtc, uint32_t sec_u) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_SEC_U_MSK, (sec_u<TIME, RTC_TIME_SEC_U_MSK)>>RTC_TIME_SEC_U_POSS); +} + +/** @defgroup MD_RTC_TIME_WEEK WEEK + * @brief Set Week Value bit bit for md_rtc_set_time() function used + * @param week value in RTC timer, in BCD format. + * @{ + */ +#define md_rtc_set_time_week_fun(week) (week<TIME, (week|hour_t|hour_u|min_t|min_u|sec_t|sec_u)); +} + + + + + + + + + + +/** + * @brief Set Year Tens Value + * @param rtc RTC Instance + * @param year_t Year tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_year_t(RTC_TypeDef *rtc, uint32_t year_t) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_YEAR_T_MSK, (year_t<CAL, RTC_CAL_YEAR_T_MSK)>>RTC_CAL_YEAR_T_POSS); +} +/** + * @brief Set Year Units Value + * @param rtc RTC Instance + * @param year_u Year units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_year_u(RTC_TypeDef *rtc, uint32_t year_u) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_YEAR_U_MSK, (year_u<CAL, RTC_CAL_YEAR_U_MSK)>>RTC_CAL_YEAR_U_POSS); +} +/** + * @brief Set Month Tens Value + * @param rtc RTC Instance + * @param mon_t Month tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_mon_t(RTC_TypeDef *rtc, uint32_t mon_t) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_MON_T_MSK, (mon_t<CAL, RTC_CAL_MON_T_MSK)>>RTC_CAL_MON_T_POS); +} +/** + * @brief Set Month Units Value + * @param rtc RTC Instance + * @param mon_u Month units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_mon_u(RTC_TypeDef *rtc, uint32_t mon_u) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_MON_U_MSK, (mon_u<CAL, RTC_CAL_MON_U_MSK)>>RTC_CAL_MON_U_POSS); +} +/** + * @brief Set Date Tens Value + * @param rtc RTC Instance + * @param date_t Date tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_date_t(RTC_TypeDef *rtc, uint32_t date_t) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_DATE_T_MSK, (date_t<CAL, RTC_CAL_DATE_T_MSK)>>RTC_CAL_DATE_T_POSS); +} +/** + * @brief Set Date Units Value + * @param rtc RTC Instance + * @param date_u Date units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_date_u(RTC_TypeDef *rtc, uint32_t date_u) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_DATE_U_MSK, (date_u<CAL, RTC_CAL_DATE_U_MSK)>>RTC_CAL_DATE_U_POSS); +} + +/** + * @brief Set Alarm Week Value + * @param rtc RTC Instance + * @param week Alarm Week value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_week(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_WEEK_MSK, (week<ALTIME, RTC_ALTIME_WEEK_MSK)>>RTC_ALTIME_WEEK_POSS); +} +/** + * @brief Set Alarm Hour Tens Value + * @param rtc RTC Instance + * @param hour_t Alarm Hour tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_hour_t(RTC_TypeDef *rtc, uint32_t hour_t) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_HOUR_T_MSK, (hour_t<ALTIME, RTC_ALTIME_HOUR_T_MSK)>>RTC_ALTIME_HOUR_T_POSS); +} +/** + * @brief Set Alarm Hour Units Value + * @param rtc RTC Instance + * @param hour_u Alarm Hour units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_hour_u(RTC_TypeDef *rtc, uint32_t hour_u) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_HOUR_U_MSK, (hour_u<ALTIME, RTC_ALTIME_HOUR_U_MSK)>>RTC_ALTIME_HOUR_U_POSS); +} +/** + * @brief Set Alarm Minute Tens Value + * @param rtc RTC Instance + * @param min_t Alarm Minute tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_min_t(RTC_TypeDef *rtc, uint32_t min_t) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_MIN_T_MSK, (min_t<ALTIME, RTC_ALTIME_MIN_T_MSK)>>RTC_ALTIME_MIN_T_POSS); +} +/** + * @brief Set Alarm Minute Units Value + * @param rtc RTC Instance + * @param min_u Alarm Minute units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_min_u(RTC_TypeDef *rtc, uint32_t min_u) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_MIN_U_MSK, (min_u<ALTIME, RTC_ALTIME_MIN_U_MSK)>>RTC_ALTIME_MIN_U_POSS); +} +/** + * @brief Set Alarm Second Tens Value + * @param rtc RTC Instance + * @param sec_t Alarm Second tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_sec_t(RTC_TypeDef *rtc, uint32_t sec_t) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_SEC_T_MSK, (sec_t<ALTIME, RTC_ALTIME_SEC_T_MSK)>>RTC_ALTIME_SEC_T_POSS); +} +/** + * @brief Set Alarm Second Units Value + * @param rtc RTC Instance + * @param sec_u Alarm Second units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_sec_u(RTC_TypeDef *rtc, uint32_t sec_u) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_SEC_U_MSK, (sec_u<ALTIME, RTC_ALTIME_SEC_U_MSK)>>RTC_ALTIME_SEC_U_POSS); +} + +/** + * @brief Set Alarm Year Tens Value + * @param rtc RTC Instance + * @param year_t Alarm Year tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_year_t(RTC_TypeDef *rtc, uint32_t year_t) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_YEAR_T_MSK, (year_t<ALCAL, RTC_ALCAL_YEAR_T_MSK)>>RTC_ALCAL_YEAR_T_POSS); +} +/** + * @brief Set Alarm Year Units Value + * @param rtc RTC Instance + * @param year_u Alarm Year units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_year_u(RTC_TypeDef *rtc, uint32_t year_u) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_YEAR_U_MSK, (year_u<ALCAL, RTC_ALCAL_YEAR_U_MSK)>>RTC_ALCAL_YEAR_U_POSS); +} +/** + * @brief Set Alarm Month Tens Value + * @param rtc RTC Instance + * @param mon_t Alarm Month tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_mon_t(RTC_TypeDef *rtc, uint32_t mon_t) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_MON_T_MSK, (mon_t<ALCAL, RTC_ALCAL_MON_T_MSK)>>RTC_ALCAL_MON_T_POS); +} +/** + * @brief Set Alarm Month Units Value + * @param rtc RTC Instance + * @param mon_u Alarm Month units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_mon_u(RTC_TypeDef *rtc, uint32_t mon_u) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_MON_U_MSK, (mon_u<ALCAL, RTC_ALCAL_MON_U_MSK)>>RTC_ALCAL_MON_U_POSS); +} +/** + * @brief Set Alarm Date Tens Value + * @param rtc RTC Instance + * @param date_t Alarm Date tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_date_t(RTC_TypeDef *rtc, uint32_t date_t) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_DATE_T_MSK, (date_t<ALCAL, RTC_ALCAL_DATE_T_MSK)>>RTC_ALCAL_DATE_T_POSS); +} +/** + * @brief Set Alarm Date Units Value + * @param rtc RTC Instance + * @param date_u Alarm Date units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_date_u(RTC_TypeDef *rtc, uint32_t date_u) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_DATE_U_MSK, (date_u<ALCAL, RTC_ALCAL_DATE_U_MSK)>>RTC_ALCAL_DATE_U_POSS); +} + +/** + * @brief Set Year Alarm Function Enable + * @param rtc RTC Instance + * @param year can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_year(RTC_TypeDef *rtc, uint32_t year) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_YEAR_MSK, (year<ALEN, RTC_ALEN_YEAR_MSK)>>RTC_ALEN_YEAR_POS); +} +/** + * @brief Set Month Alarm Function Enable + * @param rtc RTC Instance + * @param month can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_month(RTC_TypeDef *rtc, uint32_t month) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_MONTH_MSK, (month<ALEN, RTC_ALEN_MONTH_MSK)>>RTC_ALEN_MONTH_POS); +} +/** + * @brief Set Date Alarm Function Enable + * @param rtc RTC Instance + * @param date can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_date(RTC_TypeDef *rtc, uint32_t date) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_DATE_MSK, (date<ALEN, RTC_ALEN_DATE_MSK)>>RTC_ALEN_DATE_POS); +} +/** + * @brief Set Week Alarm Function Enable + * @param rtc RTC Instance + * @param week can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_week(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_WEEK_MSK, (week<ALEN, RTC_ALEN_WEEK_MSK)>>RTC_ALEN_WEEK_POS); +} +/** + * @brief Set Hour Alarm Function Enable + * @param rtc RTC Instance + * @param hour can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_hour(RTC_TypeDef *rtc, uint32_t hour) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_HOUR_MSK, (hour<ALEN, RTC_ALEN_HOUR_MSK)>>RTC_ALEN_HOUR_POS); +} +/** + * @brief Set Minute Alarm Function Enable + * @param rtc RTC Instance + * @param min can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_min(RTC_TypeDef *rtc, uint32_t min) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_MIN_MSK, (min<ALEN, RTC_ALEN_MIN_MSK)>>RTC_ALEN_MIN_POS); +} +/** + * @brief Set Second Alarm Function Enable + * @param rtc RTC Instance + * @param sec can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_sec(RTC_TypeDef *rtc, uint32_t sec) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_SEC_MSK, (sec<ALEN, RTC_ALEN_SEC_MSK)>>RTC_ALEN_SEC_POS); +} + +/** + * @brief Set RTC Wakeup Counter Match Trigger Enable + * @param rtc RTC Instance + * @param wktm can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_wktm(RTC_TypeDef *rtc, uint32_t wktm) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_WKTM_MSK, (wktm<TRIG, RTC_TRIG_WKTM_MSK)>>RTC_TRIG_WKTM_POS); +} +/** + * @brief Set RTC 1 Hz Trigger Enable + * @param rtc RTC Instance + * @param f1hz can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_f1hz(RTC_TypeDef *rtc, uint32_t f1hz) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_F1HZ_MSK, (f1hz<TRIG, RTC_TRIG_F1HZ_MSK)>>RTC_TRIG_F1HZ_POS); +} +/** + * @brief Set RTC Year Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param ryear can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_ryear(RTC_TypeDef *rtc, uint32_t ryear) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RYEAR_MSK, (ryear<TRIG, RTC_TRIG_RYEAR_MSK)>>RTC_TRIG_RYEAR_POS); +} +/** + * @brief Set RTC Month Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rmon can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rmon(RTC_TypeDef *rtc, uint32_t rmon) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RMON_MSK, (rmon<TRIG, RTC_TRIG_RMON_MSK)>>RTC_TRIG_RMON_POS); +} +/** + * @brief Set RTC Date Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rdate can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rdate(RTC_TypeDef *rtc, uint32_t rdate) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RDATE_MSK, (rdate<TRIG, RTC_TRIG_RDATE_MSK)>>RTC_TRIG_RDATE_POS); +} +/** + * @brief Set RTC Week Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rweek can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rweek(RTC_TypeDef *rtc, uint32_t rweek) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RWEEK_MSK, (rweek<TRIG, RTC_TRIG_RWEEK_MSK)>>RTC_TRIG_RWEEK_POS); +} +/** + * @brief Set RTC Hour Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rhour can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rhour(RTC_TypeDef *rtc, uint32_t rhour) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RHOUR_MSK, (rhour<TRIG, RTC_TRIG_RHOUR_MSK)>>RTC_TRIG_RHOUR_POS); +} +/** + * @brief Set RTC Minute Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rmin can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rmin(RTC_TypeDef *rtc, uint32_t rmin) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RMIN_MSK, (rmin<TRIG, RTC_TRIG_RMIN_MSK)>>RTC_TRIG_RMIN_POS); +} +/** + * @brief Set RTC Second Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rsec can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rsec(RTC_TypeDef *rtc, uint32_t rsec) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RSEC_MSK, (rsec<TRIG, RTC_TRIG_RSEC_MSK)>>RTC_TRIG_RSEC_POS); +} +/** + * @brief Set RTC Match All Alarm Trigger Enable + * @param rtc RTC Instance + * @param amall can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_amall(RTC_TypeDef *rtc, uint32_t amall) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AMALL_MSK, (amall<TRIG, RTC_TRIG_AMALL_MSK)>>RTC_TRIG_AMALL_POS); +} +/** + * @brief Set RTC Match Year Alarm Trigger Enable + * @param rtc RTC Instance + * @param ayear can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_ayear(RTC_TypeDef *rtc, uint32_t ayear) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AYEAR_MSK, (ayear<TRIG, RTC_TRIG_AYEAR_MSK)>>RTC_TRIG_AYEAR_POS); +} +/** + * @brief Set RTC Match Month Alarm Trigger Enable + * @param rtc RTC Instance + * @param amon can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_amon(RTC_TypeDef *rtc, uint32_t amon) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AMON_MSK, (amon<TRIG, RTC_TRIG_AMON_MSK)>>RTC_TRIG_AMON_POS); +} +/** + * @brief Set RTC Match Date Alarm Trigger Enable + * @param rtc RTC Instance + * @param adate can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_adate(RTC_TypeDef *rtc, uint32_t adate) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_ADTAE_MSK, (adate<TRIG, RTC_TRIG_ADTAE_MSK)>>RTC_TRIG_ADTAE_POS); +} +/** + * @brief Set RTC Match Week Alarm Trigger Enable + * @param rtc RTC Instance + * @param aweek can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_aweek(RTC_TypeDef *rtc, uint32_t aweek) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AWEEK_MSK, (aweek<TRIG, RTC_TRIG_AWEEK_MSK)>>RTC_TRIG_AWEEK_POS); +} +/** + * @brief Set RTC Match Hour Alarm Trigger Enable + * @param rtc RTC Instance + * @param ahour can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_ahour(RTC_TypeDef *rtc, uint32_t ahour) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AHOUR_MSK, (ahour<TRIG, RTC_TRIG_AHOUR_MSK)>>RTC_TRIG_AHOUR_POS); +} +/** + * @brief Set RTC Match Minute Alarm Trigger Enable + * @param rtc RTC Instance + * @param amin can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_amin(RTC_TypeDef *rtc, uint32_t amin) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AMIN_MSK, (amin<TRIG, RTC_TRIG_AMIN_MSK)>>RTC_TRIG_AMIN_POS); +} +/** + * @brief Set RTC Match Second Alarm Trigger Enable + * @param rtc RTC Instance + * @param asec can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_asec(RTC_TypeDef *rtc, uint32_t asec) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_ASEC_MSK, (asec<TRIG, RTC_TRIG_ASEC_MSK)>>RTC_TRIG_ASEC_POS); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_wktm(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_WKTM_MSK); +} +/** + * @brief Set RTC 1 Hz Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_f1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_F1HZ_MSK); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_ryear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RYEAR_MSK); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rmon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RMON_MSK); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rdate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RDATE_MSK); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RWEEK_MSK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rhour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RHOUR_MSK); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rmin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RMIN_MSK); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rsec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RSEC_MSK); +} +/** + * @brief Set RTC Match All Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_amall(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMALL_MSK); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_ayear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AYEAR_MSK); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_amon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMON_MSK); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_adate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_ADTAE_MSK); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_aweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AWEEK_MSK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_ahour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AHOUR_MSK); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_amin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMIN_MSK); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_asec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_ASEC_MSK); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_wktm(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_WKTM_MSK); +} +/** + * @brief Set RTC 1 Hz Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_f1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_F1HZ_MSK); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_ryear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RYEAR_MSK); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rmon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RMON_MSK); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rdate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RDATE_MSK); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RWEEK_MSK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rhour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RHOUR_MSK); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rmin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RMIN_MSK); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rsec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RSEC_MSK); +} +/** + * @brief Set RTC Match All Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_amall(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMALL_MSK); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_ayear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AYEAR_MSK); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_amon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMON_MSK); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_adate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_ADTAE_MSK); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_aweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AWEEK_MSK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_ahour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AHOUR_MSK); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_amin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMIN_MSK); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_asec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_ASEC_MSK); +} + +/** + * @brief Get RTC Wakeup Counter Match Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_wktm(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_WKTM_MSK)>>RTC_IVS_WKTM_POS); +} +/** + * @brief Get RTC 1 Hz Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_f1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_F1HZ_MSK)>>RTC_IVS_F1HZ_POS); +} +/** + * @brief Get RTC Year Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_ryear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RYEAR_MSK)>>RTC_IVS_RYEAR_POS); +} +/** + * @brief Get RTC Month Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rmon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RMON_MSK)>>RTC_IVS_RMON_POS); +} +/** + * @brief Get RTC Date Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rdate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RDATE_MSK)>>RTC_IVS_RDATE_POS); +} +/** + * @brief Get RTC Week Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RWEEK_MSK)>>RTC_IVS_RWEEK_POS); +} +/** + * @brief Get RTC Hour Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rhour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RHOUR_MSK)>>RTC_IVS_RHOUR_POS); +} +/** + * @brief Get RTC Minute Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rmin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RMIN_MSK)>>RTC_IVS_RMIN_POS); +} +/** + * @brief Get RTC Second Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rsec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RSEC_MSK)>>RTC_IVS_RSEC_POS); +} +/** + * @brief Get RTC Match All Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_amall(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMALL_MSK)>>RTC_IVS_AMALL_POS); +} +/** + * @brief Get RTC Match Year Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_ayear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AYEAR_MSK)>>RTC_IVS_AYEAR_POS); +} +/** + * @brief Get RTC Match Month Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_amon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMON_MSK)>>RTC_IVS_AMON_POS); +} +/** + * @brief Get RTC Match Date Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_adate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_ADTAE_MSK)>>RTC_IVS_ADTAE_POS); +} +/** + * @brief Get RTC Match Week Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_aweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AWEEK_MSK)>>RTC_IVS_AWEEK_POS); +} +/** + * @brief Get RTC Match Hour Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_ahour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AHOUR_MSK)>>RTC_IVS_AHOUR_POS); +} +/** + * @brief Get RTC Match Minute Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_amin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMIN_MSK)>>RTC_IVS_AMIN_POS); +} +/** + * @brief Get RTC Match Second Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_asec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_ASEC_MSK)>>RTC_IVS_ASEC_POS); +} + +/** + * @brief Get RTC Wakeup Counter Match Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_wktm(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_WKTM_MSK)>>RTC_RIF_WKTM_POS); +} +/** + * @brief Get RTC 1 Hz Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_f1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_F1HZ_MSK)>>RTC_RIF_F1HZ_POS); +} +/** + * @brief Get RTC Year Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_ryear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RYEAR_MSK)>>RTC_RIF_RYEAR_POS); +} +/** + * @brief Get RTC Month Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rmon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RMON_MSK)>>RTC_RIF_RMON_POS); +} +/** + * @brief Get RTC Date Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rdate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RDATE_MSK)>>RTC_RIF_RDATE_POS); +} +/** + * @brief Get RTC Week Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RWEEK_MSK)>>RTC_RIF_RWEEK_POS); +} +/** + * @brief Get RTC Hour Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rhour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RHOUR_MSK)>>RTC_RIF_RHOUR_POS); +} +/** + * @brief Get RTC Minute Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rmin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RMIN_MSK)>>RTC_RIF_RMIN_POS); +} +/** + * @brief Get RTC Second Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rsec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RSEC_MSK)>>RTC_RIF_RSEC_POS); +} +/** + * @brief Get RTC Match All Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_amall(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMALL_MSK)>>RTC_RIF_AMALL_POS); +} +/** + * @brief Get RTC Match Year Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_ayear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AYEAR_MSK)>>RTC_RIF_AYEAR_POS); +} +/** + * @brief Get RTC Match Month Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_amon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMON_MSK)>>RTC_RIF_AMON_POS); +} +/** + * @brief Get RTC Match Date Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_adate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_ADTAE_MSK)>>RTC_RIF_ADTAE_POS); +} +/** + * @brief Get RTC Match Week Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_aweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AWEEK_MSK)>>RTC_RIF_AWEEK_POS); +} +/** + * @brief Get RTC Match Hour Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_ahour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AHOUR_MSK)>>RTC_RIF_AHOUR_POS); +} +/** + * @brief Get RTC Match Minute Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_amin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMIN_MSK)>>RTC_RIF_AMIN_POS); +} +/** + * @brief Get RTC Match Second Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_asec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_ASEC_MSK)>>RTC_RIF_ASEC_POS); +} + +/** + * @brief Get RTC Wakeup Counter Match Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_wktm(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_WKTM_MSK)>>RTC_IFM_WKTM_POS); +} +/** + * @brief Get RTC 1 Hz Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_f1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_F1HZ_MSK)>>RTC_IFM_F1HZ_POS); +} +/** + * @brief Get RTC Year Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_ryear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RYEAR_MSK)>>RTC_IFM_RYEAR_POS); +} +/** + * @brief Get RTC Month Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rmon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RMON_MSK)>>RTC_IFM_RMON_POS); +} +/** + * @brief Get RTC Date Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rdate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RDATE_MSK)>>RTC_IFM_RDATE_POS); +} +/** + * @brief Get RTC Week Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RWEEK_MSK)>>RTC_IFM_RWEEK_POS); +} +/** + * @brief Get RTC Hour Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rhour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RHOUR_MSK)>>RTC_IFM_RHOUR_POS); +} +/** + * @brief Get RTC Minute Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rmin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RMIN_MSK)>>RTC_IFM_RMIN_POS); +} +/** + * @brief Get RTC Second Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rsec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RSEC_MSK)>>RTC_IFM_RSEC_POS); +} +/** + * @brief Get RTC Match All Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_amall(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMALL_MSK)>>RTC_IFM_AMALL_POS); +} +/** + * @brief Get RTC Match Year Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_ayear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AYEAR_MSK)>>RTC_IFM_AYEAR_POS); +} +/** + * @brief Get RTC Match Month Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_amon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMON_MSK)>>RTC_IFM_AMON_POS); +} +/** + * @brief Get RTC Match Date Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_adate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_ADTAE_MSK)>>RTC_IFM_ADTAE_POS); +} +/** + * @brief Get RTC Match Week Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_aweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AWEEK_MSK)>>RTC_IFM_AWEEK_POS); +} +/** + * @brief Get RTC Match Hour Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_ahour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AHOUR_MSK)>>RTC_IFM_AHOUR_POS); +} +/** + * @brief Get RTC Match Minute Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_amin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMIN_MSK)>>RTC_IFM_AMIN_POS); +} +/** + * @brief Get RTC Match Second Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_asec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_ASEC_MSK)>>RTC_IFM_ASEC_POS); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_wktm(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_WKTM_MSK); +} +/** + * @brief Set RTC 1 Hz Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_f1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_F1HZ_MSK); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_ryear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RYEAR_MSK); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rmon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RMON_MSK); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rdate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RDATE_MSK); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RWEEK_MSK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rhour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RHOUR_MSK); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rmin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RMIN_MSK); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rsec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RSEC_MSK); +} +/** + * @brief Set RTC Match All Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_amall(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMALL_MSK); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_ayear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AYEAR_MSK); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_amon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMON_MSK); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_adate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_ADTAE_MSK); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_aweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AWEEK_MSK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_ahour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AHOUR_MSK); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_amin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMIN_MSK); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_asec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_ASEC_MSK); +} + +/** + * @brief Get RTC Calendar Synchronization status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_STAT_SYNDONE_UNDER + * @arg @ref MD_RTC_STAT_SYNDONE_CMP + */ +__STATIC_INLINE uint32_t md_rtc_get_stat_syndone(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->STAT, RTC_STAT_SYNDONE_MSK)>>RTC_STAT_SYNDONE_POS); +} +/** + * @brief Get RTC Calendar Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + * @note 0 = RTC calendar is not empty + * 1 = RTC calendar is empty + */ +__STATIC_INLINE uint32_t md_rtc_get_stat_empty(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->STAT, RTC_STAT_EMPTY_MSK)>>RTC_STAT_EMPTY_POS); +} + +/** + * @brief Set Read RTC Backup Register Enable bit + * @param rtc RTC Instance + * @param bken can be one of the following values: + * @arg @ref MD_RTC_BKEN_BKEN_CONTROL + * @arg @ref MD_RTC_BKEN_BKEN_BACKUP + * @retval None + */ +__STATIC_INLINE void md_rtc_set_bken_bken(RTC_TypeDef *rtc, uint32_t bken) +{ + MODIFY_REG(rtc->BKEN, RTC_BKEN_BKEN_MSK, (bken<BKEN, RTC_BKEN_BKEN_MSK)>>RTC_BKEN_BKEN_POS); +} + +/** + * @} MD_RTC_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** @defgroup MD_RTC_PF_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_RTC_PF_Basic_Configuration + */ + +/** @defgroup MD_RTC_PF_Data_Access Data Access + * @{ + */ + +/** + * @} MD_RTC_PF_Data_Access + */ + +/** @defgroup MD_RTC_PF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} MD_RTC_PF_Init + */ + +/** + * @} MD_RTC_Public_Functions + */ + +#endif + +/** + * @} RTC + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..74f01e6312de04f956ed7b4292496531c3c21183 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h @@ -0,0 +1,2523 @@ +/** + ****************************************************************************** + * @file md_spi.h + * @brief ES32F0271 SPI Head File. + * + * @version V1.00.01 + * @date 06/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SPI_H__ +#define __MD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_spi.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) + +/** @defgroup SPI SPI + * @brief SPI micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_SPI_Public_Types SPI Public Types + * @{ + */ + +/** @defgroup MD_SPI_PT_INIT SPI Public Init structure + * @{ + */ + +/** + * @brief SPI Init structure. + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref MD_SPI_PC_MODE. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_mstren().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref MD_SPI_PC_PHASE. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_cpha().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref MD_SPI_PC_POLARITY. + + This feature can be modified afterwards using unitary function @ref md_spi_get_con1_cpol().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref MD_SPI_PC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_baud().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref MD_SPI_PC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_lsbfirst().*/ + + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref MD_SPI_PC_TRANSFER_DIRECTION. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_bidimode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref MD_SPI_PC_FRAME_FORMAT. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_dlen().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref MD_SPI_PC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_ssout().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref MD_SPI_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions @ref md_spi_enable_con1_crcen() and @ref md_spi_disable_con1_crcen().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function.*/ + +} md_spi_inittypedef; + + + + +/** + * @} MD_SPI_PT_INIT + */ + +/** + * @} MD_SPI_Public_Types + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_SPI_Public_Constants SPI Public Constants + * @{ + */ + +/** @defgroup MD_SPI_PC_MODE SPI Operation Mode + * @{ + */ +#define MD_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +#define MD_SPI_MODE_MASTER (SPI_CON1_MSTREN_MSK) /*!< Master configuration */ +/** + * @} MD_SPI_PC_MODE + */ + +/** @defgroup MD_SPI_PC_PROTOCOL SPI Serial Protocol + * @{ + */ +#define MD_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define MD_SPI_PROTOCOL_TI (SPI_CON2_FRF_MSK) /*!< TI mode */ +/** + * @} MD_SPI_PC_PROTOCOL + */ + +/** @defgroup MD_SPI_PC_PHASE SPI Clock Phase + * @{ + */ +#define MD_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define MD_SPI_PHASE_2EDGE (SPI_CON1_CPHA_MSK) /*!< Second clock transition is the first data capture edge */ +/** + * @} MD_SPI_PC_PHASE + */ + +/** @defgroup MD_SPI_PC_POLARITY SPI Clock Polarity + * @{ + */ +#define MD_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define MD_SPI_POLARITY_HIGH (SPI_CON1_CPOL_MSK) /*!< Clock to 1 when idle */ +/** + * @} MD_SPI_PC_POLARITY + */ + +/** @defgroup MD_SPI_PC_BAUDRATEPRESCALER SPI Baud Rate Prescaler + * @{ + */ +#define MD_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV4 (0x1U<CON1, value); +} + +/** + * @brief Get SPI control register (SPIx_CON1) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_con1(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CON1)); +} + +/** + + * @brief Set SPI clock phase + * @note This bit should not be changed when communication is ongoing. \n + This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref MD_SPI_PHASE_1EDGE + * @arg @ref MD_SPI_PHASE_2EDGE + * @retval None + + */ +__STATIC_INLINE void md_spi_set_con1_cpha(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_CPHA_MSK, ClockPhase); +} + +/** + * @brief Get SPI clock phase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_PHASE_1EDGE + * @arg @ref MD_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t md_spi_get_con1_cpha(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_CPHA_MSK)>>SPI_CON1_CPHA_POS); +} + +/** + * @brief Set SPI clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref MD_SPI_POLARITY_LOW + * @arg @ref MD_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_cpol(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_CPOL_MSK, ClockPolarity); +} + +/** + * @brief Get SPI clock polarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_POLARITY_LOW + * @arg @ref MD_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t md_spi_get_con1_cpol(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_CPOL_MSK)>>SPI_CON1_CPOL_POS); +} + +/** + * @brief Set SPI master selection + * @note This bit should not be changed when communication is ongoing. + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref MD_SPI_MODE_MASTER + * @arg @ref MD_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_mstren(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_MSTREN_MSK, Mode); +} + +/** + * @brief Get SPI SPI operation mode (Master or Slave) + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_MODE_MASTER + * @arg @ref MD_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t md_spi_get_con1_mstren(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_MSTREN_MSK )>>SPI_CON1_MSTREN_POS); +} + +/** + * @brief Set SPI baud rate control + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_baud(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_BAUD_MSK, BaudRate); +} + +/** + * @brief Get SPI baud rate prescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_baud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BAUD_MSK)>>SPI_CON1_BAUD_POSS); +} + +/** + * @brief Enable SPI peripheral + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_spien(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_spien(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Check if SPI peripheral is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_spien(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK) == (SPI_CON1_SPIEN_MSK)); +} + +/** + * @brief Set SPI frame format + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref MD_SPI_LSB_FIRST + * @arg @ref MD_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_lsbfirst(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_LSBFST_MSK, BitOrder); +} + +/** + * @brief Get SPI transfer bit order + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_LSB_FIRST + * @arg @ref MD_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t md_spi_get_con1_lsbfirst(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_LSBFST_MSK)>>SPI_CON1_LSBFST_POS); +} + +/** + * @brief Set SPI Internal slave select + * @note This bit has an effect only when the SSEN bit is set. The value of this bit is forced onto the NSS pin. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg BIT_SET + * @arg BIT_RESET + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_ssout(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_SSOUT_MSK , value); +} + +/** + * @brief Get SPI Internal slave select + * @param SPIx SPI Instance + * @retval State of 1 or 0 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_ssout(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_SSOUT_MSK)>>SPI_CON1_SSOUT_POS); +} + +/** + * @brief Enable SPI software slave management + * @note When the SSEN bit is set, the NSS pin input is replaced with the value from the SSOUT bit. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_ssen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); +} + +/** + * @brief Disable SPI software slave management + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_ssen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); +} + +/** + * @brief Check if SPI peripheral is software slave management + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_ssen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK) == (SPI_CON1_SSEN_MSK)); +} + +/** + * @brief Set SPI receive only mode enable + * @note This bit enables simplex communication using a single unidirectional line to receive data exclusively. \n + Keep BIDEN bit clear when receive only mode is active.This bit is also useful in a multislave system \n + in which this particular slave is not accessed, the output from the accessed slave is not corrupted. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg BIT_SET + * @arg BIT_RESET + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_rxo(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_RXO_MSK , value); +} + +/** + * @brief Set SPI receive only mode enable + * @param SPIx SPI Instance + * @retval State of 1 or 0 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_rxo(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_RXO_MSK)>>SPI_CON1_RXO_POS); +} + +/** + * @brief Set data frame format + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref MD_SPI_FRAME_FORMAT_8BIT + * @arg @ref MD_SPI_FRAME_FORMAT_16BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_flen(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_FLEN_MSK, DataWidth); +} + +/** + * @brief Get data frame format + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_FRAME_FORMAT_8BIT + * @arg @ref MD_SPI_FRAME_FORMAT_16BIT + */ +__STATIC_INLINE uint32_t md_spi_get_con1_flen(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK)>>SPI_CON1_FLEN_POS); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DATA register. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg BIT_SET + * @arg BIT_RESET + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_crcnext(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_NXTCRC_MSK, value); +} + +/** + * @brief Get CRCNext to transfer CRC on the line + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval State of 1 or 0 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_crcnext(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_NXTCRC_MSK)>>SPI_CON1_NXTCRC_POS); +} + +/** + * @brief Enable SPI hardware CRC calculation + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_crcen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Disable SPI hardware CRC calculation + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_crcen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Check if hardware CRC calculation is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_crcen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK) == (SPI_CON1_CRCEN_MSK)); +} + +/** + * @brief Enable SPI Output enable in bidirectional mode + * @note Output enable in bidirectional mode. This bit combined with the BIDEN bit selects the direction of \n + transfer in bidirectional mode + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_bidoen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Disable Output enable in bidirectional mode + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_bidoen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Check if Output enable in bidirectional mode is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_bidoen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK) == (SPI_CON1_BIDOEN_MSK)); +} + +/** + * @brief Set Bidirectional data mode enable + * @note Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional \n + data line. Keep RXO bit clear when bidirectional mode is active. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_SPI_FULL_DUPLEX + * @arg @ref MD_SPI_HALF_DUPLEX + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_bidimode(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_BIDEN_MSK, value); +} + +/** + * @brief Get Bidirectional data mode enable + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow: + * @arg @ref MD_SPI_FULL_DUPLEX + * @arg @ref MD_SPI_HALF_DUPLEX + */ +__STATIC_INLINE uint32_t md_spi_get_con1_bidimode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK)>>SPI_CON1_BIDEN_POS); +} + + +/** + * @} MD_SPI_CON1 + */ + + + +/** @defgroup MD_SPI_CON2 SPI Control Register 2 + * @{ + */ + +/** + * @brief Set SPI control register 2 (SPIx_CON2) + * @param SPIx SPI Instance + * @param value The value write in SPIx_CON2 + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->CON2, value); +} + +/** + * @brief Get SPI control register 2(SPIx_CON2) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_con2(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CON2)); +} + + +/** + * @brief Enable Rx buffer DMA + * @note When this bit is set, a DMA request is generated whenever the RXTH flag is set. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_rxdmaen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Disable Rx buffer DMA + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_rxdmaen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Check if Rx buffer DMA is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_rxdmaen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK) == (SPI_CON2_RXDMA_MSK)); +} + +/** + * @brief Enable Tx buffer DMA enable + * @note When this bit is set, a DMA request is generated whenever the TXTH flag is set. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_txdmaen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Disable Tx buffer DMA enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_txdmaen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Check if Tx buffer DMA enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_txdmaen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK) == (SPI_CON2_TXDMA_MSK)); +} + +/** + * @brief Enable SS output enable + * @note SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot \n + work in a multimaster environment. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_ssoe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Disable SS output enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_ssoe(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Check if SS output enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_ssoe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK) == (SPI_CON2_NSSOE_MSK)); +} + +/** + * @brief Enable NSS pulse management + * @note This bit is used in master mode only. It allow the SPI to generate an NSS pulse between two consecutive \n + data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high \n + level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’.This bit should not be changed \n + when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_nssp(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); +} + +/** + * @brief Disable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_nssp(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); +} + +/** + * @brief Check if NSS pulse is enabled + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_nssp(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK) == (SPI_CON2_NSSP_MSK)); +} + +/** + * @brief Set frame format + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref MD_SPI_PROTOCOL_MOTOROLA + * @arg @ref MD_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2_frf(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_FRF_MSK, Standard); +} + +/** + * @brief Get frame format + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_PROTOCOL_MOTOROLA + * @arg @ref MD_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t md_spi_get_con2_frf(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON2, SPI_CON2_FRF_MSK)>>SPI_CON2_FRF_POS); +} + + +/** + * @brief Set transmit FIFO trigger threshold + * @note This is used to select the threshold level in the transmit FIFO at which the Transmit FIFO \n + trigger threshold flag is generated. + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_TX_FIFO_TH_0BIT + * @arg @ref MD_SPI_TX_FIFO_TH_2BIT + * @arg @ref MD_SPI_TX_FIFO_TH_4BIT + * @arg @ref MD_SPI_TX_FIFO_TH_8BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2_txfth(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_TXFTH_MSK, Threshold<CON2, SPI_CON2_TXFTH_MSK)>>SPI_CON2_TXFTH_POSS); +} + +/** + * @brief Set receive FIFO trigger threshold + * @note This is used to select the threshold level in the receiver FIFO at which the Receive FIFO \n + trigger threshold flag is generated. + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_RX_FIFO_TH_1BIT + * @arg @ref MD_SPI_RX_FIFO_TH_4BIT + * @arg @ref MD_SPI_RX_FIFO_TH_8BIT + * @arg @ref MD_SPI_RX_FIFO_TH_14BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2_rxfth(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_RXFTH_MSK, Threshold<CON2, SPI_CON2_RXFTH_MSK)>>SPI_CON2_RXFTH_POSS); +} + + +/** + * @} MD_SPI_CON2 + */ + +/** + * @defgroup MD_SPI_STAT SPI Status Register + * @{ + */ + + +/** + * @brief Get SPI status register(SPIx_STAT) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_stat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->STAT)); +} + +/** + * @brief Check if SPI transmit buffer empty is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txe(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXE_MSK)== (SPI_STAT_TXE_MSK)); +} + +/** + * @brief Check if SPI transmit buffer full is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txf(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXF_MSK)== (SPI_STAT_TXF_MSK)); +} + +/** + * @brief Check if SPI transmit buffer overflow is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txov(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXOV_MSK)== (SPI_STAT_TXOV_MSK)); +} + +/** + * @brief Check if SPI transmit buffer underflow is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXUD_MSK) == (SPI_STAT_TXUD_MSK)); +} + +/** + * @brief Check if SPI Tx FIFO level under threshold is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXTH_MSK) == (SPI_STAT_TXTH_MSK)); +} + +/** + * @brief Check if SPI receive buffer empty is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxe(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXE_MSK) == (SPI_STAT_RXE_MSK)); +} + +/** + * @brief Check if SPI receive buffer full is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxf(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXF_MSK)== (SPI_STAT_RXF_MSK)); +} + +/** + * @brief Get SPI receive buffer overflow + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxov(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON2, SPI_STAT_RXOV_MSK)== (SPI_STAT_RXOV_MSK)); +} + +/** + * @brief Check if SPI receive buffer underflow is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXUD_MSK)== (SPI_STAT_RXUD_MSK)); +} + +/** + * @brief Check if SPI Rx FIFO level over threshold is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXTH_MSK)== (SPI_STAT_RXTH_MSK)); +} + +/** + * @brief Check if SPI channel side is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_chside(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_CHSIDE_MSK)== (SPI_STAT_CHSIDE_MSK)); +} + +/** + * @brief Check if SPI busy flag is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_busy(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_BUSY_MSK)== (SPI_STAT_BUSY_MSK)); +} + +/** + * @brief Get SPI Tx FIFO level + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_stat_txflv(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXFLV_MSK) >> SPI_STAT_TXFLV_POSS); +} + +/** + * @brief Get SPI Rx FIFO level + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_stat_rxflv(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXFLV_MSK) >> SPI_STAT_RXFLV_POSS); +} + +/** + * @} MD_SPI_STAT + */ + + +/** @defgroup MD_SPI_DATA SPI Data Register + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t md_spi_recv_data8(SPI_TypeDef *SPIx) +{ + return (uint8_t)(READ_REG(SPIx->DATA)); +} + +/** + * @brief Read 16-Bits in the data register + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t md_spi_recv_data16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DATA)); +} + +/** + * @brief Write 8-Bits in the data register + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void md_spi_send_data8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + SPIx->DATA = (uint8_t)TxData; +} + +/** + * @brief Write 16-Bits in the data register + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void md_spi_send_data16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + SPIx->DATA = (uint16_t)TxData; +} + +/** + * @} MD_SPI_DATA + */ + +/** @defgroup MD_SPI_CRC SPI CRC Manangement + * @{ MD_SPI_CRC + */ + +/** + * @brief Set CRC polynmomial register (SPIx_CRCPLOY) + * @note When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently \n + received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is \n + calculated serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are \n + considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CON1 is cleared). CRC \n + calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a \n + 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based \n + on any CRC16 standard. + Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not \n + used in I2S mode. + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void md_spi_set_crcploy(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPOLY, (uint16_t)CRCPoly); +} + +/** + * @brief Get CRC polynmomial register (SPIx_CRCPLOY) + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t md_spi_get_crcploy(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPOLY)); +} + +/** + * @brief Get Rx CRC register + * @note When CRC calculation is enabled, the RxCRC[7:0] bits contain the computed CRC value of the subsequently \n + transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n + serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n + when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CON1 is cleared). CRC calculation is \n + done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n + format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n + Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n + in I2S mode. + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t md_spi_get_rxcrc(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRC)); +} + +/** + * @brief Get Tx CRC register + * @note When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently \n + transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n + serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n + when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CR1 is cleared). CRC calculation is \n + done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n + format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n + Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n + in I2S mode. + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t md_spi_get_txcrc(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRC)); +} + +/** + * @} MD_SPI_CRC + */ + + + +/** @defgroup MD_SPI_I2S I2S Configuration Management + * @{ + */ + + +/** @defgroup MD_SPI_I2SCFG I2S Configuration register + * @{ + */ + +/** + * @brief Set SPI I2S configuration register(SPIx_I2SCFG) + * @param SPIx SPI Instance + * @param value The value write in SPIx_I2SCFG + * @retval None + */ +__STATIC_INLINE void md_spi_set_I2SCFG(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->I2SCFG, value); +} + +/** + * @brief Get SPI I2S configuration register (SPIx_I2SCFG) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_I2SCFG(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->I2SCFG)); +} + +/** + * @brief Set channel legth(number of bits per audio channel) + * @note The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by \n + hardware whatever the value filled in. + Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT + * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_chlen(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CHLEN_MSK, value); +} + +/** + * @brief Get channel legth(number of bits per audio channel) + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return: + * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT + * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_chlen(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CHLEN_MSK)); +} + +/** + * @brief Set Data length to be transferred + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_DATA_LENGTH_16BIT + * @arg @ref MD_I2S_DATA_LENGTH_24BIT + * @arg @ref MD_I2S_DATA_LENGTH_32BIT + * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_datlen(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_DATLEN_MSK, value); +} + +/** + * @brief Get Data length to be transferred + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_I2S_DATA_LENGTH_16BIT + * @arg @ref MD_I2S_DATA_LENGTH_24BIT + * @arg @ref MD_I2S_DATA_LENGTH_32BIT + * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_datlen(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_DATLEN_MSK)>>SPI_I2SCFG_DATLEN_POSS); +} + +/** + * @brief Set Inactive state clock polarity + * @note Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used \n + in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD \n + and WS signals. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_POLARITY_LOW + * @arg @ref MD_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_ckpol(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CKPOL_MSK, value); +} + +/** + * @brief Get Inactive state clock polarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_POLARITY_LOW + * @arg @ref MD_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_ckpol(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CKPOL_MSK)>>SPI_I2SCFG_CKPOL_POS); +} + +/** + * @brief Set I2S standard selection + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_PHILIPS_STANDARD + * @arg @ref MD_I2S_MSB_STANDARD + * @arg @ref MD_I2S_LSB_STANDARD + * @arg @ref MD_I2S_PCM_STANDARD + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_i2sstd(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK, value); +} + +/** + * @brief Get I2S standard selection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_PHILIPS_STANDARD + * @arg @ref MD_I2S_MSB_STANDARD + * @arg @ref MD_I2S_LSB_STANDARD + * @arg @ref MD_I2S_PCM_STANDARD + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2sstd(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK)>>SPI_I2SCFG_I2SSTD_POSS); +} + +/** + * @brief Set PCM frame synchronization + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_FRAME_SYN_SHORT + * @arg @ref MD_I2S_FRAME_SYN_LONG + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_pcmsync(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK, value); +} + +/** + * @brief Get PCM frame synchronization + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_FRAME_SYN_SHORT + * @arg @ref MD_I2S_FRAME_SYN_LONG + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_pcmsync(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK)>>SPI_I2SCFG_PCMSYNC_POS); +} + +/** + * @brief Set I2S configuration mode + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_SLAVE_TX + * @arg @ref MD_I2S_SLAVE_RX + * @arg @ref MD_I2S_MASTER_TX + * @arg @ref MD_I2S_MASTER_RX + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_i2scfg(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, value); +} + +/** + * @brief Get I2S configuration mode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_SLAVE_TX + * @arg @ref MD_I2S_SLAVE_RX + * @arg @ref MD_I2S_MASTER_TX + * @arg @ref MD_I2S_MASTER_RX + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2scfg(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK)>>SPI_I2SCFG_I2SCFG_POSS); +} + +/** + * @brief Enable I2S enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_i2scfg_i2se(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Disable I2S enable + * @note When disabling the I2S, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_i2scfg_i2se(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Check if I2S enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_i2scfg_i2se(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK) == (SPI_I2SCFG_I2SE_MSK)); +} + +/** + * @brief Set I2S mode selection + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_MODE_SPI + * @arg @ref MD_I2S_MODE_I2S + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_i2smod(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK, value); +} + +/** + * @brief Get I2S mode selection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_MODE_SPI + * @arg @ref MD_I2S_MODE_I2S + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2smod(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK)>>SPI_I2SCFG_I2SMOD_POS); +} + + +/** + * @} MD_SPI_I2SCFG + */ + +/**@defgroup MD_SPI_I2SPR I2S Prescaler register + * @{ + */ + + + +/** + * @brief Set SPI I2S configuration register(SPIx_I2SPR) + * @param SPIx SPI Instance + * @param value The value write in SPIx_I2SPR + * @retval None + */ +__STATIC_INLINE void md_spi_set_I2SPR(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->I2SPR, value); +} + +/** + * @brief Get SPI I2S configuration register (SPIx_I2SPR) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_I2SPR(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->I2SPR)); +} + +/** + * @brief Set I2S linear prescaler + * @note I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. \n + Note: These bits should be configured when the I2S is disabled. \n + They are used only when the I2S is in master mode. They are not used in SPI mode. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg Max:255 + * @arg Min:2 + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr_i2sdiv(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV_MSK, value); +} + +/** + * @brief Get I2S linear prescaler + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg Max:255 + * @arg Min:2 + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr_i2sdiv(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV_MSK)>>SPI_I2SPR_I2SDIV_POSS); +} + +/** + * @brief Set Odd factor for the prescaler + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg MD_I2S_EVEN + * @arg MD_I2S_ODD + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr_odd(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD_MSK, value); +} + +/** + * @brief Get Odd factor for the prescaler + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg MD_I2S_EVEN + * @arg MD_I2S_ODD + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr_odd(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD_MSK)>>SPI_I2SPR_ODD_POS); +} + +/** + * @brief Master clock output enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_i2spr_mckoe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Master clock output disable + * @note When disabling the I2S, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_i2spr_mckoe(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Check if Master clock output enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_i2spr_mckoe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE_MSK) == (SPI_I2SPR_MCKOE_MSK)); +} + +/** + * @brief Set External I2S Clock Enable + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg MD_I2S_APB_CLOCK + * @arg MD_I2S_EXTERNAL_CLOCK + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr_extcken(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_EXTCKEN_MSK, value); +} + +/** + * @brief Get External I2S Clock Enable + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg MD_I2S_APB_CLOCK + * @arg MD_I2S_EXTERNAL_CLOCK + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr_extcken(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_EXTCKEN_MSK)>>SPI_I2SPR_EXTCKEN_POS); +} + + + + + + +/** + * @} MD_SPI_I2SPR + */ + + + +/** + * @} MD_SPI_I2S + */ + + +/** @defgroup MD_SPI_PF_Interrupt_Management SPI Interrupt Management + * @{ + */ + +/** @defgroup MD_SPI_IER SPI Interrupt Enable Register + * @{ + */ + + +/** + * @brief Frame format error interrupt enable + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_freie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_FREIE_MSK); +} + +/** + * @brief Mode fault interrupt enable + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_modfie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODFIE_MSK); +} + +/** + * @brief CRC error interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_crcerrie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCERRIE_MSK); +} + +/** + * @brief Receive buffer over threshold interrupt enable + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxthie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXTHIE_MSK); +} + +/** + * @brief Transmit buffer over threshold interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txthie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTHIE_MSK); +} + +/** + * @brief Receive buffer underrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxudie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXUDIE_MSK); +} + +/** + * @brief Transmit buffer underrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txudie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXUDIE_MSK); +} + +/** + * @brief Receive buffer overrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxovie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXOVIE_MSK); +} + +/** + * @brief Transmit buffer overrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txovie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXOVIE_MSK); +} + +/** + * @brief Receive buffer full interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxfie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXFIE_MSK); +} + +/** + * @brief Transmit buffer empty interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txeie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXEIE_MSK); +} + +/** + * @} MD_SPI_IER + */ + + +/** @defgroup MD_SPI_IDR SPI Interrupt Disable Register + * @{ + */ + +/** + * @brief Frame format error interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_freid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_FREID_MSK); +} + +/** + * @brief Mode fault interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_modfid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_MODFID_MSK); +} + +/** + * @brief CRC error interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_crcerrid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_CRCERRID_MSK); +} + +/** + * @brief Receive buffer under threshold interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxthid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXTHID_MSK); +} + +/** + * @brief Transmit buffer under threshold interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txthid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXTHID_MSK); +} + +/** + * @brief Receive buffer underrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxudid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXUDID_MSK); +} + +/** + * @brief Transmit buffer underrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txudid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXUDID_MSK); +} + +/** + * @brief Receive buffer overrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxovid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXOVID_MSK); +} + +/** + * @brief Transmit buffer overrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txovid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXOVID_MSK); +} + +/** + * @brief Receive buffer full interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxfid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXFID_MSK); +} + +/** + * @brief Transmit buffer empty interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txeid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXEID_MSK); +} + +/** + * @} MD_SPI_IDR + */ + +/** @defgroup MD_SPI_ICR SPI Interrupt Clear Status Register + * @{ + */ + +/** + * @brief Frame format error interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_freic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_FREIC_MSK); +} + +/** + * @brief Mode fault interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_modfic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_MODFIC_MSK); +} + +/** + * @brief CRC error interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_crcerric(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_CRCERRIC_MSK); +} + +/** + * @brief Receive buffer over threshold interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxthic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXTHIC_MSK); +} + +/** + * @brief Transmit buffer over threshold interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txthic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXTHIC_MSK); +} + +/** + * @brief Receive buffer underrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxudic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXUDIC_MSK); +} + +/** + * @brief Transmit buffer underrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txudic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXUDIC_MSK); +} + +/** + * @brief Receive buffer overrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxovic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXOVIC_MSK); +} + +/** + * @brief Transmit buffer overrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txovic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXOVIC_MSK); +} + +/** + * @brief Receive buffer full interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxfic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXFIC_MSK); +} + +/** + * @brief Transmit buffer empty interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txeic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXEIC_MSK); +} + +/** + * @} MD_SPI_ICR + */ + +/** @defgroup MD_SPI_IVS SPI Interrupt Valid Status Register + * @{ + */ + + +/** + * @brief Check if Frame format error interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_freiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_FREIV_MSK) == (SPI_IVS_FREIV_MSK)); +} + +/** + * @brief Check if Mode fault interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_modfiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_MODFIV_MSK) == (SPI_IVS_MODFIV_MSK)); +} + +/** + * @brief Check if CRC error interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_crcerriv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_CRCERRIV_MSK) == (SPI_IVS_CRCERRIV_MSK)); +} + +/** + * @brief Check if Receive buffer under threshold interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxthiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXTHIV_MSK) == (SPI_IVS_RXTHIV_MSK)); +} + +/** + * @brief Check if Transmit buffer under threshold interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txthiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXTHIV_MSK) == (SPI_IVS_TXTHIV_MSK)); +} + +/** + * @brief Check if Receive buffer under underrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxudiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXUDIV_MSK) == (SPI_IVS_RXUDIV_MSK)); +} + +/** + * @brief Check if Transmit buffer underrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txudiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXUDIV_MSK) == (SPI_IVS_TXUDIV_MSK)); +} + +/** + * @brief Check if Receive buffer overrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxoviv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXOVIV_MSK) == (SPI_IVS_RXOVIV_MSK)); +} + +/** + * @brief Check if Transmit buffer overrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_txoviv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXOVIV_MSK) == (SPI_IVS_TXOVIV_MSK)); +} + +/** + * @brief Check if Receive buffer full interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxfiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXFIV_MSK) == (SPI_IVS_RXFIV_MSK)); +} + +/** + * @brief Check if Transmit buffer empty interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_txeiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXEIV_MSK) == (SPI_IVS_TXEIV_MSK)); +} + + +/** + * @} MD_SPI_IVS + */ + + +/** @defgroup MD_SPI_RIF SPI Raw Interrupt Flag Status Register + * @{ + */ + +/** + * @brief Check if Transmit buffer empty interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txeri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXERI_MSK)==(SPI_RIF_TXERI_MSK)); +} + +/** + * @brief Check if Transmit buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txovri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXOVRI_MSK)==(SPI_RIF_TXOVRI_MSK)); +} + +/** + * @brief Check if Transmit buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txudri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXUDRI_MSK)==(SPI_RIF_TXUDRI_MSK)); +} + +/** + * @brief Check if Transmit buffer under threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txthri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXTHRI_MSK)==(SPI_RIF_TXTHRI_MSK)); +} + +/** + * @brief Check if Receive buffer full interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxfri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXFRI_MSK)==(SPI_RIF_RXFRI_MSK)); +} + +/** + * @brief Check if Receive buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxovri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXOVRI_MSK)==(SPI_RIF_RXOVRI_MSK)); +} + +/** + * @brief Check if Receive buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxudri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXUDRI_MSK)==(SPI_RIF_RXUDRI_MSK)); +} + +/** + * @brief Check if Receive buffer over threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxthri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXTHRI_MSK)==(SPI_RIF_RXTHRI_MSK)); +} + +/** + * @brief Check if CRC error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_crcerrri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_CRCERRRI_MSK)==(SPI_RIF_CRCERRRI_MSK)); +} + +/** + * @brief Check if Mode fault interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_modfri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_MODFRI_MSK)==(SPI_RIF_MODFRI_MSK)); +} + +/** + * @brief Check if Frame format error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_freri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_FRERI_MSK)==(SPI_RIF_FRERI_MSK)); +} + +/** + * @} MD_SPI_RIF + */ + +/** @defgroup MD_SPI_IFM SPI Interrupt Masked Flag Status Register + * @{ + */ + +/** + * @brief Check if Transmit buffer empty interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txefm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXEFM_MSK)==(SPI_IFM_TXEFM_MSK)); +} + +/** + * @brief Check if Transmit buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txovfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXOVFM_MSK)==(SPI_IFM_TXOVFM_MSK)); +} + +/** + * @brief Check if Transmit buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txudfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXUDFM_MSK)==(SPI_IFM_TXUDFM_MSK)); +} + +/** + * @brief Check if Transmit buffer under threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txthfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXTHFM_MSK)==(SPI_IFM_TXTHFM_MSK)); +} + +/** + * @brief Check if Receive buffer full interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxffm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXFFM_MSK)==(SPI_IFM_RXFFM_MSK)); +} + +/** + * @brief Check if Receive buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxovfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXOVFM_MSK)==(SPI_IFM_RXOVFM_MSK)); +} + +/** + * @brief Check if Receive buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxudfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXUDFM_MSK)==(SPI_IFM_RXUDFM_MSK)); +} + +/** + * @brief Check if Receive buffer over threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxthfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXTHFM_MSK)==(SPI_IFM_RXTHFM_MSK)); +} + +/** + * @brief Check if CRC error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_crcerrfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_CRCERRFM_MSK)==(SPI_IFM_CRCERRFM_MSK)); +} + +/** + * @brief Check if Mode fault interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_modffm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_MODFFM_MSK)==(SPI_IFM_MODFFM_MSK)); +} + +/** + * @brief Check if Frame format error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_frefm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_FREFM_MSK)==(SPI_IFM_FREFM_MSK)); +} + +/** + * @} MD_SPI_IFM + */ + + + +/** + * @} MD_SPI_PF_Interrupt_Management + */ + + + +/** + * @} MD_SPI_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_SPI_Public_Functions SPI Public Functions + * @{ + */ + + + + +/** @defgroup MD_SPI_PF_Init SPI Initialization and De-Initialization functions + * @{ + */ + +ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct); +void md_spi_struct_init(md_spi_inittypedef *SPI_InitStruct); +void SPISingleWr(SPI_TypeDef *SPIx, uint8_t data); +uint8_t SPISSingleRd(SPI_TypeDef *SPIx); +/** + * @} MD_SPI_PF_Init + */ + +/** + * @} MD_SPI_Public_Functions + */ + +/** + * @} SPI + */ + +#endif + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h new file mode 100644 index 0000000000000000000000000000000000000000..0da1bfc14d8d2055f2aefc37f63d8c70825a5693 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h @@ -0,0 +1,1249 @@ +/** + ****************************************************************************** + * @file md_SYSCFG.h + * @brief ES32F0271 SYSCFG HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SYSCFG_H__ +#define __MD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_syscfg.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (SYSCFG) + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_PT_INIT RCC Public Init structures + * @{ + */ + +/** + * @brief MD SYSCFG Init Structure definition + */ + + +/** + * @} MD_SYSCFG_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_Public_Constants SYSCFG Public Constants + * @{ + */ + +/** @defgroup MD_SYSCFG_REMAP_REALMOD_FLAG Current Memory mapping Status + * @{ + */ +#define MD_SYSCFG_REALMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_REALMOD_SYSTEM (0x00000001UL) /** @brief System Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_REALMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ +/** + * @} MD_SYSCFG_REMAP_REALMOD_FLAG + */ + +/** @defgroup MD_SYSCFG_REMAP_MEMMOD_FLAG Memory mapping selection bits + * @{ + */ +#define MD_SYSCFG_MEMMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_MEMMOD_SYSTEM (0x00000001UL) /** @brief System Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_MEMMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ +/** + * @} MD_SYSCFG_REMAP_MEMMOD_FLAG + */ + +/** @defgroup MD_SYSCFG_IRSEL_PLR_FLAG IR Polarity + * @{ + */ +#define MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 (0x00000000UL) /** @brief IR out = ~(SEL1 & SEL2) */ +#define MD_SYSCFG_PLR_SEL1_AND_SEL2 (0x00000001UL) /** @brief IR out = SEL1 & SEL2 */ +/** + * @} MD_SYSCFG_IRSEL_PLR_FLAG + */ + +/** @defgroup MD_SYSCFG_IRSEL_SEL2 IR Select 2 + * @{ + */ +#define MD_SYSCFG_SEL2_OFF (0x00000000UL) /** @brief 0000: OFF */ +#define MD_SYSCFG_SEL2_GP16C2T4_CH1 (0x00000001UL) /** @brief 0001: GP16C2T4_CH1 */ +#define MD_SYSCFG_SEL2_GP16C2T4_CH2 (0x00000002UL) /** @brief 0010: GP16C2T4_CH2 */ +#define MD_SYSCFG_SEL2_UART3_TX (0x00000003UL) /** @brief 0100: UART3_TX */ +#define MD_SYSCFG_SEL2_SUART2_TX (0x00000004UL) /** @brief 1000: SUART2_TX */ +/** + * @} MD_SYSCFG_IRSEL_SEL2 + */ + +/** @defgroup MD_SYSCFG_IRSEL_SEL1 IR Select 1 + * @{ + */ +#define MD_SYSCFG_SEL1_OFF (0x00000000UL) /** @brief 0000: OFF */ +#define MD_SYSCFG_SEL1_GP16C2T2_CH1 (0x00000001UL) /** @brief 0001: GP16C2T2_CH1 */ +#define MD_SYSCFG_SEL1_GP16C2T2_CH2 (0x00000002UL) /** @brief 0010: GP16C2T2_CH2 */ +#define MD_SYSCFG_SEL1_GP16C2T3_CH1 (0x00000003UL) /** @brief 0100: GP16C2T3_CH1 */ +#define MD_SYSCFG_SEL1_GP16C2T3_CH2 (0x00000004UL) /** @brief 1000: GP16C2T3_CH2 */ +/** + * @} MD_SYSCFG_IRSEL_SEL1 + */ + +/** @defgroup MD_SYSCFG_CFG_DBGH_EN DBG Halt enable bit + * @{ + */ +#define MD_SYSCFG_DBGH_EN_IWDT (0x00002000UL) +#define MD_SYSCFG_DBGH_EN_WWDT (0x00001000UL) +#define MD_SYSCFG_DBGH_EN_BS16T1 (0x00000200UL) +#define MD_SYSCFG_DBGH_EN_GP16C4T3 (0x00000100UL) +#define MD_SYSCFG_DBGH_EN_GP16C4T2 (0x00000080UL) +#define MD_SYSCFG_DBGH_EN_GP16C4T1 (0x00000040UL) +#define MD_SYSCFG_DBGH_EN_GP32C4T1 (0x00000020UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T4 (0x00000010UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T3 (0x00000008UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T2 (0x00000004UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T1 (0x00000002UL) +#define MD_SYSCFG_DBGH_EN_AD16C4T1 (0x00000001UL) +/** + * @} MD_SYSCFG_CFG_DBGH_EN + */ + +/** @defgroup MD_SYSCFG_CFG_VTST Voltage testing + * @{ + */ +#define MD_SYSCFG_VTST_LDO (0x00000000UL) /** @brief 00: LDO Buffer Voltage */ +#define MD_SYSCFG_VTST_BANDGAP_REF (0x00000001UL) /** @brief 01: BandGap Reference Voltage */ +#define MD_SYSCFG_VTST_LDO1V2 (0x00000002UL) /** @brief 10: LDO1V2 Voltage */ +#define MD_SYSCFG_VTST_LDO1V5 (0x00000003UL) /** @brief 11: LDO1V5 Voltage */ +/** + * @} MD_SYSCFG_CFG_VTST + */ + +/** @defgroup MD_SYSCFG_CFG_VRLS These bits are written by software to select the voltage reference level by the ADC/DAC + * @{ + */ +#define MD_SYSCFG_VRLS_1V5 (0x00000000UL) /** @brief 000: 1.5V */ +#define MD_SYSCFG_VRLS_2V (0x00000001UL) /** @brief 001: 2.0V */ +#define MD_SYSCFG_VRLS_2V5 (0x00000002UL) /** @brief 010: 2.5V */ +#define MD_SYSCFG_VRLS_3V (0x00000003UL) /** @brief 011: 3.0V */ +#define MD_SYSCFG_VRLS_3V5 (0x00000004UL) /** @brief 100: 3.5V */ +#define MD_SYSCFG_VRLS_4V (0x00000005UL) /** @brief 101: 4.0V */ +#define MD_SYSCFG_VRLS_4V5 (0x00000006UL) /** @brief 110: 4.5V */ +#define MD_SYSCFG_VRLS_5V (0x00000007UL) /** @brief 111: 5.0V(VDD5) */ +/** + * @} MD_SYSCFG_CFG_VRLS + */ + +/** @defgroup MD_SYSCFG_PWCON_PVLS These bits are written by software to select the voltage reference level by the ADC/DAC + * @{ + */ +#define MD_SYSCFG_PVLS_R1V9_F2V (0x00000000UL) /** @brief 0000: R-1.9V, F-2.0V */ +#define MD_SYSCFG_PVLS_R2V1_F2V2 (0x00000001UL) /** @brief 0001: R-2.1V, F-2.2V */ +#define MD_SYSCFG_PVLS_R2V3_F2V4 (0x00000002UL) /** @brief 0010: R-2.3V, F-2.4V */ +#define MD_SYSCFG_PVLS_R2V5_F2V6 (0x00000003UL) /** @brief 0011: R-2.5V, F-2.6V */ +#define MD_SYSCFG_PVLS_R2V7_F2V8 (0x00000004UL) /** @brief 0100: R-2.7V, F-2.8V */ +#define MD_SYSCFG_PVLS_R2V9_F3V (0x00000005UL) /** @brief 0101: R-2.9V, F-3.0V */ +#define MD_SYSCFG_PVLS_R3V1_F3V2 (0x00000006UL) /** @brief 0110: R-3.1V, F-3.2V */ +#define MD_SYSCFG_PVLS_R3V3_F3V4 (0x00000007UL) /** @brief 0111: R-3.3V, F-3.4V */ +#define MD_SYSCFG_PVLS_R3V5_F3V6 (0x00000008UL) /** @brief 1000: R-3.5V, F-3.6V */ +#define MD_SYSCFG_PVLS_R3V7_F3V8 (0x00000009UL) /** @brief 1001: R-3.7V, F-3.8V */ +#define MD_SYSCFG_PVLS_R3V9_F4V (0x0000000AUL) /** @brief 1010: R-3.9V, F-4.0V */ +#define MD_SYSCFG_PVLS_R4V1_F4V2 (0x0000000BUL) /** @brief 1011: R-4.1V, F-4.2V */ +#define MD_SYSCFG_PVLS_R4V3_F4V4 (0x0000000CUL) /** @brief 1100: R-4.3V, F-4.4V */ +#define MD_SYSCFG_PVLS_R4V5_F4V6 (0x0000000DUL) /** @brief 1101: R-4.5V, F-4.6V */ +#define MD_SYSCFG_PVLS_R4V7_F4V8 (0x0000000EUL) /** @brief 1110: R-4.7V, F-4.8V */ +#define MD_SYSCFG_PVLS_R4V9_F5V (0x0000000FUL) /** @brief 1111: R-4.9V, F-5.0V */ +/** + * @} MD_SYSCFG_PWCON_PVLS + */ + +/** @defgroup MD_SYSCFG_WKCON_LPLS Low Power Level Select + * @{ + */ +#define MD_SYSCFG_LPLS_LV0 (0x00000000UL) /** @brief 0 : Level 0, Sleep Mode (Normal) */ +#define MD_SYSCFG_LPLS_LV1 (0x00000001UL) /** @brief 1 : Level 1, Stop Mode (All Clock OFF) */ +#define MD_SYSCFG_LPLS_LV2 (0x00000002UL) /** @brief 2 : Level 2, Standby Mode (SRAM retention) */ +#define MD_SYSCFG_LPLS_LV3 (0x00000003UL) /** @brief 3 : Level 3, Low Power Mode (LDO off) */ +#define MD_SYSCFG_LPLS_LV4 (0x00000004UL) /** @brief 4 : Level 3, Ultra Low Power Mode(LDO off/BandGap off) */ +/** + * @} MD_SYSCFG_WKCON_LPLS + */ + +/** @defgroup MD_SYSCFG_WKCON_WKEG WKEGx:WKUPx pin edge sensitive type select + * @{ + */ +#define MD_SYSCFG_WKCON_WKEG_NRST (0x00000800UL) +#define MD_SYSCFG_WKCON_WKEG_PVD (0x00000400UL) +#define MD_SYSCFG_WKCON_WKEG_CMP0 (0x00000200UL) +#define MD_SYSCFG_WKCON_WKEG_RTC (0x00000100UL) +#define MD_SYSCFG_WKCON_WKEG_PIN7 (0x00000080UL) +#define MD_SYSCFG_WKCON_WKEG_PIN6 (0x00000040UL) +#define MD_SYSCFG_WKCON_WKEG_PIN5 (0x00000020UL) +#define MD_SYSCFG_WKCON_WKEG_PIN4 (0x00000010UL) +#define MD_SYSCFG_WKCON_WKEG_PIN3 (0x00000008UL) +#define MD_SYSCFG_WKCON_WKEG_PIN2 (0x00000004UL) +#define MD_SYSCFG_WKCON_WKEG_PIN1 (0x00000002UL) +#define MD_SYSCFG_WKCON_WKEG_PIN0 (0x00000001UL) +/** + * @} MD_SYSCFG_WKCON_WKEG + */ + +/** @defgroup MD_SYSCFG_WKCON_WKEN WKENx: Enable WKUPx pin or wakeup event + * @{ + */ +#define MD_SYSCFG_WKCON_WKEN_NRST (0x00000800UL) +#define MD_SYSCFG_WKCON_WKEN_PVD (0x00000400UL) +#define MD_SYSCFG_WKCON_WKEN_CMP0 (0x00000200UL) +#define MD_SYSCFG_WKCON_WKEN_RTC (0x00000100UL) +#define MD_SYSCFG_WKCON_WKEN_PIN7 (0x00000080UL) +#define MD_SYSCFG_WKCON_WKEN_PIN6 (0x00000040UL) +#define MD_SYSCFG_WKCON_WKEN_PIN5 (0x00000020UL) +#define MD_SYSCFG_WKCON_WKEN_PIN4 (0x00000010UL) +#define MD_SYSCFG_WKCON_WKEN_PIN3 (0x00000008UL) +#define MD_SYSCFG_WKCON_WKEN_PIN2 (0x00000004UL) +#define MD_SYSCFG_WKCON_WKEN_PIN1 (0x00000002UL) +#define MD_SYSCFG_WKCON_WKEN_PIN0 (0x00000001UL) +/** + * @} MD_SYSCFG_WKCON_WKEN + */ + +/** @defgroup MD_SYSCFG_WKSTAT_FG FGx: WKUPx pin or wakeup event flag + * @{ + */ +#define MD_SYSCFG_WKSTAT_FG_NRST (0x00000800UL) +#define MD_SYSCFG_WKSTAT_FG_PVD (0x00000400UL) +#define MD_SYSCFG_WKSTAT_FG_CMP0 (0x00000200UL) +#define MD_SYSCFG_WKSTAT_FG_RTC (0x00000100UL) +#define MD_SYSCFG_WKSTAT_FG_PIN7 (0x00000080UL) +#define MD_SYSCFG_WKSTAT_FG_PIN6 (0x00000040UL) +#define MD_SYSCFG_WKSTAT_FG_PIN5 (0x00000020UL) +#define MD_SYSCFG_WKSTAT_FG_PIN4 (0x00000010UL) +#define MD_SYSCFG_WKSTAT_FG_PIN3 (0x00000008UL) +#define MD_SYSCFG_WKSTAT_FG_PIN2 (0x00000004UL) +#define MD_SYSCFG_WKSTAT_FG_PIN1 (0x00000002UL) +#define MD_SYSCFG_WKSTAT_FG_PIN0 (0x00000001UL) +/** + * @} MD_SYSCFG_WKSTAT_FG + */ + +/** + * @} MD_SYSCFG_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ + +/** + * @brief Get Current Memory mapping Status + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_REALMOD_MAIN + * @arg @ref MD_SYSCFG_REALMOD_SYSTEM + * @arg @ref MD_SYSCFG_REALMOD_SRAM + */ +__STATIC_INLINE uint32_t md_syscfg_get_remap_REALMOD(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REALMOD_MSK)>>SYSCFG_REMAP_REALMOD_POSS); +} +/** + * @brief Set Remap Main Flash Base Address Selection + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on. + * @param syscfg SYSCFG Instance + * @param efbase This parameter can be one of the following values: + * @arg Max Value 15 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_remap_efbase(SYSCFG_TypeDef *syscfg, uint32_t efbase) +{ + MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_EFBASE_MSK, (efbase<REMAP, SYSCFG_REMAP_EFBASE_MSK)>>SYSCFG_REMAP_EFBASE_POSS); +} +/** + * @brief Set Memory mapping selection bits + * @param syscfg SYSCFG Instance + * @param memmod This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_MEMMOD_MAIN + * @arg @ref MD_SYSCFG_MEMMOD_SYSTEM + * @arg @ref MD_SYSCFG_MEMMOD_SRAM + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_remap_memmod(SYSCFG_TypeDef *syscfg, uint32_t memmod) +{ + MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_MEMMOD_MSK, (memmod<REMAP, SYSCFG_REMAP_MEMMOD_MSK)>>SYSCFG_REMAP_MEMMOD_POSS); +} +/** + * @brief Set Start Remap bit + * @note This bit set High to start remapping process, that will be auto clear when process was finish. + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_remap_remap(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP_MSK); +} +/** + * @brief Get Start Remap bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_remap_remap(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP_MSK)>>SYSCFG_REMAP_REMAP_POS); +} + +/** + * @brief Set IR Polarity + * @param syscfg SYSCFG Instance + * @param plr This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 + * @arg @ref MD_SYSCFG_PLR_SEL1_AND_SEL2 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel_plr(SYSCFG_TypeDef *syscfg, uint32_t plr) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_PLR_MSK, (plr<IRSEL, SYSCFG_IRSEL_PLR_MSK)>>SYSCFG_IRSEL_PLR_POS); +} +/** + * @brief Set IR Select 2 + * @param syscfg SYSCFG Instance + * @param sel2 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_SEL2_OFF + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH1 + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH2 + * @arg @ref MD_SYSCFG_SEL2_UART3_TX + * @arg @ref MD_SYSCFG_SEL2_SUART2_TX + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel_sel2(SYSCFG_TypeDef *syscfg, uint32_t sel2) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL2_MSK, (sel2<IRSEL, SYSCFG_IRSEL_SEL2_MSK)>>SYSCFG_IRSEL_SEL2_POSS); +} +/** + * @brief Set IR Select 1 + * @param syscfg SYSCFG Instance + * @param sel1 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_SEL1_OFF + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH2 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH2 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel_sel1(SYSCFG_TypeDef *syscfg, uint32_t sel1) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL1_MSK, (sel1<IRSEL, SYSCFG_IRSEL_SEL1_MSK)>>SYSCFG_IRSEL_SEL1_POSS); +} + +/** + * @brief Set DBG Halt enable bit + * @note 0: The counter clock is fed even if the core is halted + * 1: The counter clock is stopped when the core is halted + * @param syscfg SYSCFG Instance + * @param sel1 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_DBGH_EN_IWDT + * @arg @ref MD_SYSCFG_DBGH_EN_WWDT + * @arg @ref MD_SYSCFG_DBGH_EN_BS16T1 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T3 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T2 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T1 + * @arg @ref MD_SYSCFG_DBGH_EN_GP32C4T1 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T4 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T3 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T2 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T1 + * @arg @ref MD_SYSCFG_DBGH_EN_AD16C4T1 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg_dbgh_en(SYSCFG_TypeDef *syscfg, uint32_t sel1) +{ + MODIFY_REG(syscfg->CFG, SYSCFG_CFG_DBGH_EN_MSK, (sel1<CFG, SYSCFG_CFG_DBGH_EN_MSK)>>SYSCFG_CFG_DBGH_EN_POSS); +} +/** + * @brief PVD lock enable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_pvdlck(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK); +} +/** + * @brief PVD lock disable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_pvdlck(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK); +} +/** + * @brief Get PVD lock bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_pvdlck(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK)>>SYSCFG_CFG_PVD_LCK_POS); +} +/** + * @brief Clock security system lock enable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_csslck(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK); +} +/** + * @brief Clock security system lock enable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_csslck(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK); +} +/** + * @brief Clock security system lock enable bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_csslck(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK)>>SYSCFG_CFG_CSS_LCK_POS); +} +/** + * @brief Cortex-M0 LOCKUP bit enable bit + * @note This bit is set by software and cleared by a system reset. + * It can be use to enable and lock the connection of Cortex-M0 LOCKUP (Hardfault) output to AD16C4T/GP16C2T1-4 Break input. + * @note 1: Cortex-M0 LOCKUP output connected to AD16C4T/GP16C2T1/GP16C2T2/GP16C2T3/GP16C2T4 Break input + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_cpulck(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK); +} +/** + * @brief Cortex-M0 LOCKUP bit disable bit + * @note 0: Cortex-M0 LOCKUP output disconnected from AD16C4T / GP16C2T1-4 Break input + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_cpulck(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK); +} +/** + * @brief Get Cortex-M0 LOCKUP bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_cpulck(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK)>>SYSCFG_CFG_CPU_LCK_POS); +} +/** + * @brief Set Voltage testing, This bit is set and cleared by software. + * @param syscfg SYSCFG Instance + * @param vtst This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_VTST_LDO + * @arg @ref MD_SYSCFG_VTST_BANDGAP_REF + * @arg @ref MD_SYSCFG_VTST_LDO1V2 + * @arg @ref MD_SYSCFG_VTST_LDO1V5 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg_vtst(SYSCFG_TypeDef *syscfg, uint32_t vtst) +{ + MODIFY_REG(syscfg->CFG, SYSCFG_CFG_VTST_MSK, (vtst<CFG, SYSCFG_CFG_VTST_MSK)>>SYSCFG_CFG_VTST_POSS); +} +/** + * @brief Enable External NRST Pin reset request + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_nrstreq(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK); +} +/** + * @brief Disable External NRST Pin reset request + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_nrstreq(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK); +} +/** + * @brief External NRST Pin reset request + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_nrstreq(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK)>>SYSCFG_CFG_NRSTREQ_POS); +} +/** + * @brief ADC/DAC current generator enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_currgen(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK); +} +/** + * @brief ADC/DAC current generator disabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_currgen(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK); +} +/** + * @brief ADC/DAC current generator status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_currgen(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK)>>SYSCFG_CFG_CURRGEN_POS); +} +/** + * @brief Temperature sensor enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_tempen(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK); +} +/** + * @brief Temperature sensor disabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_tempen(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK); +} +/** + * @brief Get Temperature sensor status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_tempen(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK)>>SYSCFG_CFG_TEMPEN_POS); +} +/** + * @brief Voltage reference enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_vrefen(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK); +} +/** + * @brief Voltage reference disabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_vrefen(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK); +} +/** + * @brief Get Voltage reference status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_vrefen(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK)>>SYSCFG_CFG_VREFEN_POS); +} +/** + * @brief Set These bits are written by software to select the voltage reference level by the ADC/DAC: + * @param syscfg SYSCFG Instance + * @param vlrs This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_VRLS_1V5 + * @arg @ref MD_SYSCFG_VRLS_2V + * @arg @ref MD_SYSCFG_VRLS_2V5 + * @arg @ref MD_SYSCFG_VRLS_3V + * @arg @ref MD_SYSCFG_VRLS_3V5 + * @arg @ref MD_SYSCFG_VRLS_4V + * @arg @ref MD_SYSCFG_VRLS_4V5 + * @arg @ref MD_SYSCFG_VRLS_5V + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg_vlrs(SYSCFG_TypeDef *syscfg, uint32_t vlrs) +{ + MODIFY_REG(syscfg->CFG, SYSCFG_CFG_VRLS_MSK, (vlrs<CFG, SYSCFG_CFG_VRLS_MSK)>>SYSCFG_CFG_VRLS_POSS); +} + +/** + * @brief WKCON0-7 IO Setting Value LOCKED enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_pwcon_iolock(SYSCFG_TypeDef *syscfg) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_IOLOCK_MSK, (ENABLE<PWCON, SYSCFG_PWCON_IOLOCK_MSK, (DISABLE<PWCON, SYSCFG_PWCON_IOLOCK_MSK)>>SYSCFG_PWCON_IOLOCK_POS); +} +/** + * @brief Set BandGap Trimming Value + * @param syscfg SYSCFG Instance + * @param bgtrim This parameter can be one of the following values: + * @arg Max Value 15 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_bgtrim(SYSCFG_TypeDef *syscfg, uint32_t bgtrim) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_BGTRIM_MSK, (bgtrim<PWCON, SYSCFG_PWCON_BGTRIM_MSK)>>SYSCFG_PWCON_BGTRIM_POSS); +} +/** + * @brief HSI auto calibration result value LOCK + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_pwcon_hrclock(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK); +} +/** + * @brief HSI auto calibration result value unLOCK + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_pwcon_hrclock(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK); +} +/** + * @brief Get HSI auto calibration result value + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_pwcon_hrclock(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK)>>SYSCFG_PWCON_HRCLOCK_POS); +} +/** + * @brief Set HSI auto calibration result value + * @param syscfg SYSCFG Instance + * @param hsitrim This parameter can be one of the following values: + * @arg Max Value 255 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_hrctrim(SYSCFG_TypeDef *syscfg, uint32_t hsitrim) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_HRCTRIM_MSK, (hsitrim<PWCON, SYSCFG_PWCON_HRCTRIM_MSK)>>SYSCFG_PWCON_HRCTRIM_POSS); +} +/** + * @brief Set LSI Driver Select + * @param syscfg SYSCFG Instance + * @param loscdrv This parameter can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_loscdrv(SYSCFG_TypeDef *syscfg, uint32_t loscdrv) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_LOSCDRV_MSK, (loscdrv<PWCON, SYSCFG_PWCON_LOSCDRV_MSK)>>SYSCFG_PWCON_LOSCDRV_POSS); +} +/** + * @brief Power voltage detector(PVD) enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_pwcon_pvden(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK); +} +/** + * @brief Power voltage detector(PVD) disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_pwcon_pvden(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK); +} +/** + * @brief Get Power voltage detector(PVD) status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_pwcon_pvden(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK)>>SYSCFG_PWCON_PVDEN_POS); +} +/** + * @brief Set power voltage detector + * @note These bits are written by software to select the voltage threshold detected by the power voltage detector + * @param syscfg SYSCFG Instance + * @param pvls This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_PVLS_R1V9_F2V + * @arg @ref MD_SYSCFG_PVLS_R2V1_F2V2 + * @arg @ref MD_SYSCFG_PVLS_R2V3_F2V4 + * @arg @ref MD_SYSCFG_PVLS_R2V5_F2V6 + * @arg @ref MD_SYSCFG_PVLS_R2V7_F2V8 + * @arg @ref MD_SYSCFG_PVLS_R2V9_F3V + * @arg @ref MD_SYSCFG_PVLS_R3V1_F3V2 + * @arg @ref MD_SYSCFG_PVLS_R3V3_F3V4 + * @arg @ref MD_SYSCFG_PVLS_R3V5_F3V6 + * @arg @ref MD_SYSCFG_PVLS_R3V7_F3V8 + * @arg @ref MD_SYSCFG_PVLS_R3V9_F4V + * @arg @ref MD_SYSCFG_PVLS_R4V1_F4V2 + * @arg @ref MD_SYSCFG_PVLS_R4V3_F4V4 + * @arg @ref MD_SYSCFG_PVLS_R4V5_F4V6 + * @arg @ref MD_SYSCFG_PVLS_R4V7_F4V8 + * @arg @ref MD_SYSCFG_PVLS_R4V9_F5V + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_pvls(SYSCFG_TypeDef *syscfg, uint32_t pvls) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_PVLS_MSK, (pvls<PWCON, SYSCFG_PWCON_PVLS_MSK)>>SYSCFG_PWCON_PVLS_POSS); +} + +/** + * @brief Clear Wake Flag enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_wkcon_wkclr(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->WKCON, SYSCFG_WKCON_WKCLR_MSK); +} +/** + * @brief Set Low Power Level Select + * @param syscfg SYSCFG Instance + * @param lpls The parameter can be one of the following values: + * @arg @ref MD_SYSCFG_LPLS_LV0 + * @arg @ref MD_SYSCFG_LPLS_LV1 + * @arg @ref MD_SYSCFG_LPLS_LV2 + * @arg @ref MD_SYSCFG_LPLS_LV3 + * @arg @ref MD_SYSCFG_LPLS_LV4 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon_lpls(SYSCFG_TypeDef *syscfg, uint32_t lpls) +{ + MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_LPLS_MSK, (lpls<WKCON, SYSCFG_WKCON_LPLS_MSK)>>SYSCFG_WKCON_LPLS_POSS); +} +/** + * @brief Set WKUPx pin edge sensitive type select + * @note 0 : Falling Edge-sensitive (default) + * 1 : Rising Edge-sensitive + * @param syscfg SYSCFG Instance + * @param wkeg This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_WKCON_WKEG_NRST + * @arg @ref MD_SYSCFG_WKCON_WKEG_PVD + * @arg @ref MD_SYSCFG_WKCON_WKEG_CMP0 + * @arg @ref MD_SYSCFG_WKCON_WKEG_RTC + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN7 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN6 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN5 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN4 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN3 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN2 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN1 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon_wkeg(SYSCFG_TypeDef *syscfg, uint32_t wkeg) +{ + MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_WKEG_MSK, (wkeg<WKCON, SYSCFG_WKCON_WKEG_MSK)>>SYSCFG_WKCON_WKEG_POSS); +} + +/** + * @brief Set Enable WKUPx pin or wakeup event + * @note 0: WKUPx pin is used for general purpose I/Os. An event on the WKUPx pin does not wakeup the device from Standby mode. + * 1: WKUPx pin is used for wakeup from Standby mode. + * @param syscfg SYSCFG Instance + * @param wken This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_WKCON_WKEN_NRST + * @arg @ref MD_SYSCFG_WKCON_WKEN_PVD + * @arg @ref MD_SYSCFG_WKCON_WKEN_CMP0 + * @arg @ref MD_SYSCFG_WKCON_WKEN_RTC + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN7 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN6 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN5 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN4 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN3 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN2 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN1 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon_wken(SYSCFG_TypeDef *syscfg, uint32_t wken) +{ + MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_WKEN_MSK, (wken<WKCON, SYSCFG_WKCON_WKEN_MSK)>>SYSCFG_WKCON_WKEN_POSS); +} +/** + * @brief Set SYSCFG WCON register + * @param syscfg SYSCFG Instance + * @param uint32_t wcon + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon(SYSCFG_TypeDef *syscfg, uint32_t wcon) +{ + WRITE_REG(syscfg->WKCON, wcon); +} + +/** + * @brief Get Wakeup Flag + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_wkstat_flag(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->WKSTAT, SYSCFG_WKSTAT_FLAG_MSK)>>SYSCFG_WKSTAT_FLAG_POS); +} +/** + * @brief Get WKCON pin0 or wakeup event flag. + * @note When this bit was set to 1, a wakeup event occurs. + * @param syscfg SYSCFG Instance + * @retval State of bit. + * @arg @ref MD_SYSCFG_WKSTAT_FG_NRST + * @arg @ref MD_SYSCFG_WKSTAT_FG_PVD + * @arg @ref MD_SYSCFG_WKSTAT_FG_CMP0 + * @arg @ref MD_SYSCFG_WKSTAT_FG_RTC + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN7 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN6 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN5 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN4 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN3 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN2 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN1 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_wkstat_fg(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->WKSTAT, SYSCFG_WKSTAT_FG_MSK)>>SYSCFG_WKSTAT_FG_POSS); +} + + +/** + * @brief Set Backup Register 0. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg0 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg0(SYSCFG_TypeDef *syscfg, uint32_t bkreg0) +{ + MODIFY_REG(syscfg->BKREG0, SYSCFG_BKREG0_BKREG0_MSK, (bkreg0<BKREG0, SYSCFG_BKREG0_BKREG0_MSK)>>SYSCFG_BKREG0_BKREG0_POSS); +} + +/** + * @brief Set Backup Register 1. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg1 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg1(SYSCFG_TypeDef *syscfg, uint32_t bkreg1) +{ + MODIFY_REG(syscfg->BKREG1, SYSCFG_BKREG1_BKREG1_MSK, (bkreg1<BKREG1, SYSCFG_BKREG1_BKREG1_MSK)>>SYSCFG_BKREG1_BKREG1_POSS); +} + +/** + * @brief Set Backup Register 2. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg2 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg2(SYSCFG_TypeDef *syscfg, uint32_t bkreg2) +{ + MODIFY_REG(syscfg->BKREG2, SYSCFG_BKREG2_BKREG2_MSK, (bkreg2<BKREG2, SYSCFG_BKREG2_BKREG2_MSK)>>SYSCFG_BKREG2_BKREG2_POSS); +} + +/** + * @brief Set Backup Register 3. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg3 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg3(SYSCFG_TypeDef *syscfg, uint32_t bkreg3) +{ + MODIFY_REG(syscfg->BKREG3, SYSCFG_BKREG3_BKREG3_MSK, (bkreg3<BKREG3, SYSCFG_BKREG3_BKREG3_MSK)>>SYSCFG_BKREG3_BKREG3_POSS); +} + +/** + * @} MD_SYSCFG_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ + +/** @defgroup MD_SYSCFG_PF_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_SYSCFG_PF_Basic_Configuration + */ + +/** @defgroup MD_SYSCFG_PF_Data_Access Data Access + * @{ + */ + +/** + * @} MD_SYSCFG_PF_Data_Access + */ + +/** @defgroup MD_SYSCFG_PF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} MD_SYSCFG_PF_Init + */ + +/** + * @} MD_SYSCFG_Public_Functions + */ + +#endif + +/** + * @} SYSCFG + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h new file mode 100644 index 0000000000000000000000000000000000000000..f8570471e94ffc7d585f1de3e7d8293cbce7c2fb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h @@ -0,0 +1,433 @@ +/** + ****************************************************************************** + * @file md_TICK.h + * @brief ES32F0271 TICK HEAD File. + * + * @version V1.00.01 + * @date 11/20/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_TICK_H__ +#define __MD_TICK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_tick.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (TICK) + +/** @defgroup TICK TICK + * @brief TICK micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ + +/** + * @brief MD TICK Parameter Structure definition + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Constants TICK Public Constants + * @{ + */ + +/** + * @} MD_TICK_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Macros TICK Public Macros + * @{ + */ + +/** @defgroup MD_TICK_PM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_TICK_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define MD_TICK_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @brief Modify value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be written in the register + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_TICK_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +/** + * @brief Set bit value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be set in the register + * @retval None + */ +#define MD_TICK_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Clear bit value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be cleased in the register + * @retval None + */ +#define MD_TICK_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Read bit value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be read in the register + * @retval Register bit value + */ +#define MD_TICK_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @} MD_TICK_PM_WRITE_READ + */ + +/** @defgroup MD_TICK_Macro_Drivers TICK Public Macro Drivers + * @{ + */ + +/** + * @brief Set TICK CSR + * @param @arg Max Value 0x7 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_csr(uint32_t U32) +{ + MD_TICK_WRITEREG(TICK, CSR, U32); +} + +/** + * @brief Get TICK CSR + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x10007 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_csr(void) +{ + return (MD_TICK_READREG(TICK, CSR)); +} + +/** + * @brief Get TICK CSR Count Flag + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_is_active_csr_countflag(void) +{ + return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_COUNTFLAG_MSK)>>TICK_CSR_COUNTFLAG_POS); +} + +/** + * @brief Set TICK CSR Clock Source + * @param @arg Max Value 0x1 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_csr_clksource(uint32_t ClkSource) +{ + MD_TICK_MODIFYREG(TICK, CSR, TICK_CSR_CLKSOURCE_MSK, (ClkSource<>TICK_CSR_CLKSOURCE_POS); +} + +/** + * @brief Enable TICK CSR Tick Interrupt + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_enable_csr_tickint(void) +{ + MD_TICK_SET_BIT(TICK, CSR, TICK_CSR_TICKINT_MSK); +} + +/** + * @brief Disable TICK CSR Tick Interrupt + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_disable_csr_tickint(void) +{ + MD_TICK_CLEAR_BIT(TICK, CSR, TICK_CSR_TICKINT_MSK); +} + +/** + * @brief is TICK CSR Tick Interrupt Enabled + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_is_enabled_csr_tickint(void) +{ + return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_TICKINT_MSK)>>TICK_CSR_TICKINT_POS); +} + +/** + * @brief Enable TICK CSR Enable + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_enable_csr_enable(void) +{ + MD_TICK_SET_BIT(TICK, CSR, TICK_CSR_ENABLE_MSK); +} + +/** + * @brief Disable TICK CSR Enable + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_disable_csr_enable(void) +{ + MD_TICK_CLEAR_BIT(TICK, CSR, TICK_CSR_ENABLE_MSK); +} + +/** + * @brief is TICK CSR Enable Enabled + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_is_enabled_csr_enable(void) +{ + return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_ENABLE_MSK)>>TICK_CSR_ENABLE_POS); +} + +/** + * @brief Set TICK RVR + * @param @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_rvr(uint32_t U32) +{ + MD_TICK_WRITEREG(TICK, RVR, U32); +} + +/** + * @brief Get TICK RVR + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_rvr(void) +{ + return (MD_TICK_READREG(TICK, RVR)); +} + +/** + * @brief Set TICK RVR Reload + * @param @arg Max Value 0xfffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_rvr_reload(uint32_t Reload) +{ + MD_TICK_MODIFYREG(TICK, RVR, TICK_RVR_RELOAD_MSK, (Reload<>TICK_RVR_RELOAD_POSS); +} + +/** + * @brief Set TICK CVR + * @param @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_cvr(uint32_t U32) +{ + MD_TICK_WRITEREG(TICK, CVR, U32); +} + +/** + * @brief Get TICK CVR + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_cvr(void) +{ + return (MD_TICK_READREG(TICK, CVR)); +} + +/** + * @brief Set TICK CVR Current + * @param @arg Max Value 0xfffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_cvr_current(uint32_t Current) +{ + MD_TICK_MODIFYREG(TICK, CVR, TICK_CVR_CURRENT_MSK, (Current<>TICK_CVR_CURRENT_POSS); +} + +/** + * @brief Get TICK CALIB + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_calib(void) +{ + return (MD_TICK_READREG(TICK, CALIB)); +} + +/** + * @brief Get TICK CALIB NOREF + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_get_calib_noref(void) +{ + return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_NOREF_MSK)>>TICK_CALIB_NOREF_POS); +} + +/** + * @brief Get TICK CALIB SKEW + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_get_calib_skew(void) +{ + return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_SKEW_MSK)>>TICK_CALIB_SKEW_POS); +} + +/** + * @brief Get TICK CALIB 10ms Value + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xfffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_calib_tenms(void) +{ + return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_TENMS_MSK)>>TICK_CALIB_TENMS_POSS); +} + + +/** + * @} MD_TICK_Macro_Drivers + */ + +/** + * @} MD_TICK_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Functions TICK Public Functions + * @{ + */ +void md_tick_init(void); +uint32_t md_tick_get_mscnt(void); +uint32_t md_tick_get_100uscnt(void); +uint32_t md_tick_get_10uscnt(void); +void md_tick_waitms(uint8_t Unit, uint16_t msCnt); +void md_tick_wait100us(uint16_t Unit, uint16_t usCnt); +void md_tick_wait10us(uint16_t Unit, uint16_t usCnt); +/** + * @} MD_TICK_Public_Functions + */ + +#endif + +/** + * @} TICK + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..e638ab0a7a42502f0c50784d5bd83e04f7fd2ab4 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h @@ -0,0 +1,2874 @@ +/** + ****************************************************************************** + * @file md_UART.h + * @brief ES32F0271 UART Header File. + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_UART_H__ +#define __MD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_uart.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (UART1) | defined (UART2) | defined (UART3) | defined (SUART1) | defined (SUART2) + +/** @defgroup UART UART + * @brief UART micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_UART_Public_Types UART Public Init Type + * @{ + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.*/ + + uint32_t BitOrder; /*!< Specifies the MSB of data bits will be transmitted or received first. + This parameter can be a value of @ref MD_UART_LCON_MSB_FIRST.*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref MD_UART_LCON_PS_EVEN.*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref MD_UART_LCON_STOP_1.*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref MD_UART_LCON_DLS_8.*/ + +} md_uart_init_typedef; + +/** + * @} MD_UART_Public_Types + */ + +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_UART_Public_Constants UART Public Constants + * @{ + */ + +/** @defgroup UART_BAUDRATE UART Baudrate Definitation + * @{ + */ +#define MD_UART_BAUDRATE_1200 (1200U) /* baud rate=1200 bps */ +#define MD_UART_BAUDRATE_2400 (2400U) /* baud rate=2400 bps */ +#define MD_UART_BAUDRATE_4800 (4800U) /* baud rate=4800 bps */ +#define MD_UART_BAUDRATE_9600 (9600U) /* baud rate=9600 bps */ +#define MD_UART_BAUDRATE_19200 (19200U) /* baud rate=19200 bps */ +#define MD_UART_BAUDRATE_38400 (38400U) /* baud rate=38400 bps */ +#define MD_UART_BAUDRATE_57600 (57600U) /* baud rate=57600 bps */ +#define MD_UART_BAUDRATE_115200 (115200U) /* baud rate=115200 bps */ +#define MD_UART_BAUDRATE_230400 (230400U) /* baud rate=230400 bps */ +#define MD_UART_BAUDRATE_460800 (460800U) /* baud rate=460800 bps */ +#define MD_UART_BAUDRATE_512000 (512000U) /* baud rate=512000 bps */ +#define MD_UART_BAUDRATE_921600 (921600U) /* baud rate=921600 bps */ +/** + * @} UART_BAUDRATE UART Baudrate Definitation + */ + +/** @defgroup UART_LCON UART_LCON Register + * @{ + */ +#define MD_UART_LCON_MSB_FIRST (1U) /** @brief data Most significant bit first */ +#define MD_UART_LCON_LSB_FIRST (0U) /** @brief data Least significant bit first */ +#define MD_UART_LCON_PS_EVEN (1U) /** @brief data Even parity bit selection */ +#define MD_UART_LCON_PS_ODD (0U) /** @brief data Odd parity bit selection */ +#define MD_UART_LCON_STOP_2 (1U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_STOP_1 (0U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_DLS_8 (0U) /** @brief data Date length 8 */ +#define MD_UART_LCON_DLS_7 (1U) /** @brief data Date length 7 */ +#define MD_UART_LCON_DLS_6 (2U) /** @brief data Date length 6 */ +#define MD_UART_LCON_DLS_5 (3U) /** @brief data Date length 5 */ +/** + * @} UART_LCON UART_LCON Register + */ + +/** @defgroup UART_MCON UART_MCON Register + * @{ + */ +#define MD_UART_MCON_ABRMOD_0 (0U) /** @brief data Receiver DMA disable */ +#define MD_UART_MCON_ABRMOD_1 (1U) /** @brief data Repeat auto-baud rate detection after timeout enable */ +#define MD_UART_MCON_ABRMOD_2 (2U) /** @brief data Repeat auto-baud rate detection after timeout disable */ +#define MD_UART_MCON_RTSSET_LOW (1U) /** @brief data RTSn set control bit RTSn level is 0 */ +#define MD_UART_MCON_RTSSET_HIGH (0U) /** @brief data RTSn set control bit RTSn level is 1 */ +/** + * @} UART_MCON UART_MCON Register + */ + +/** @defgroup UART_MCON UART_MCON Register + * @{ + */ +#define MD_UART_RS485_AADINV_LOW (0U) /** @brief data Low : Transfering data, High: Idle */ +#define MD_UART_RS485_AADINV_HIGH (1U) /** @brief data High: Transfering data, Low : Idle */ +/** + * @} UART_MCON UART_MCON Register + */ + +/** @defgroup UART_FCON UART_FCON Register + * @{ + */ +#define MD_UART_FCON_TXTH_0 (0U) /** @brief data Transmit FIFO trigger threshold: FIFO empty */ +#define MD_UART_FCON_TXTH_2 (1U) /** @brief data Transmit FIFO trigger threshold: 2 characters in the FIFO */ +#define MD_UART_FCON_TXTH_4 (2U) /** @brief data Transmit FIFO trigger threshold: 4 characters in the FIFO */ +#define MD_UART_FCON_TXTH_8 (3U) /** @brief data Transmit FIFO trigger threshold: 8 characters in the FIFO */ +#define MD_UART_FCON_TFRST (1U) /** @brief data Transmitter FIFO reset */ +#define MD_UART_FCON_RXTH_1 (0U) /** @brief data Receive FIFO trigger threshold: 1 character in the FIFO */ +#define MD_UART_FCON_RXTH_4 (1U) /** @brief data Receive FIFO trigger threshold: 4 characters in the FIFO */ +#define MD_UART_FCON_RXTH_8 (2U) /** @brief data Receive FIFO trigger threshold: 8 characters in the FIFO */ +#define MD_UART_FCON_RXTH_14 (3U) /** @brief data Receive FIFO trigger threshold: 14 characters in the FIFO */ +#define MD_UART_FCON_RFRST (1U) /** @brief data Receive FIFO reset */ +/** + * @} UART_FCON UART_FCON Register + */ + +/** + * @} MD_UART_Public_Constants UART Public Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_UART_Public_Macros UART Public Macros + * @{ + */ + +/** + * @brief Read Receiver Buffer Register + * @note Contains the received data character. + * The RXBR register provides the parallel interface between the + * input shift register and the internal bus. + * When receiving with the parity enabled, the value read in the + * MSB bit is the received parity bit. + * @param UARTx UART Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t md_uart_get_rxbuf(UART_TypeDef *UARTx) +{ + return (uint16_t) ((READ_REG(UARTx->RXBUF))>>UART_RXBUF_RXBUF_POSS); +} + +/** + * @brief Write Transmit buffer register + * @note Contains the data character to be transmitted. + * The TXBR register provides the parallel interface between the + * internal bus and the output shift register. + * When transmitting with the parity enabled the value written in + * the MSB (bit 7 or bit 8 depending on the data length) has no + * effect because it is replaced by the parity. + * @param UARTx UART Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void md_uart_send_txbuf(UART_TypeDef *UARTx, uint8_t TxData) +{ + WRITE_REG (UARTx->TXBUF, (uint8_t)TxData); +} + +/** + * @brief Set UARTx Baud rate register. + * @note This bits can only be written when the UART is disabled. + * (RXEN and TXEN=0 in the LCR register). + * @param UARTx UART Instance. + * @param UART buad rate value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_brr(UART_TypeDef *UARTx, uint32_t baudrate) +{ + WRITE_REG(UARTx->BRR, baudrate); +} + +/** + * @brief Get UARTx baud rate. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval UARTx Baudrate. + */ +__STATIC_INLINE uint32_t md_uart_get_brr(UART_TypeDef *UARTx) +{ + return (uint32_t) (READ_REG(UARTx->BRR)>>UART_BRR_BRR_POSS); +} + +/** + * @brief UARTx Transmitter enable. + * @note This bit enables the transmitter. It is set and cleared by + * software. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_txen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); +} + +/** + * @brief UARTx Transmitter disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_txen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); +} + +/** + * @brief Check if UART Transmitter is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_tx(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXEN_MSK) == (UART_LCON_TXEN_MSK)); +} + +/** + * @brief UARTx Receiver enable + * @note This bit enables the receiver. It is set and cleared by software. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lcon_rxen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); +} + +/** + * @brief UARTx Receiver Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_lcon_rxen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); +} + +/** + * @brief Check if UARTx Receiver is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_rxen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXEN_MSK) == (UART_LCON_RXEN_MSK)); +} + +/** + * @brief UARTx Debounce Enable. + * @note This bit enables the debounce. It is set and cleared by software. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_decen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); +} + +/** + * @brief UART Debounce Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_dbcen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); +} + +/** + * @brief Check if UART Debounce is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_dbcen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK) == (UART_LCON_DBCEN_MSK)); +} + +/** + * @brief Enable UARTx Break control bit. + * @note This is used to cause a break condition to be transmitted to the + * receiving device. The serial data output (Tx) is forced to the + * Spacing State (logic 0). + * This bit can only be written when the UART is disabled. + * (RXENand TXEN=0). + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lcon_break(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); +} + +/** + * @brief Disable UARTx Break control bit. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_break(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); +} + +/** + * @brief Check if UARTx Break control bit is enabled. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_break(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_BREAK_MSK) == (UART_LCON_BREAK_MSK)); +} + +/** + * @brief UARTx Swap TX/RX pins. + * @note This allows to work in the case of a cross-wired connection to another UART. + * This bit can only be written when the UART is disabled (RXEN and TXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_swap(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); +} + +/** + * @brief UARTx Swap TX/RX pins disabl. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_disable_lcon_swap(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); +} + +/** + * @brief Check if UART Swap TX/RX pins is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_swap(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_SWAP_MSK) == (UART_LCON_SWAP_MSK)); +} + +/** + * @brief UARTx TX pin active level inversion. + * @note This allows the use of an external inverter on the TX line. + * This bit can only be written when the UART is disabled (RXEN and TXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_txinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); +} + +/** + * @brief UARTx TX pin active level inversion disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_txinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); +} + +/** + * @brief Check if UARTx TX pin active level is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_txinv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXINV_MSK) == (UART_LCON_TXINV_MSK)); +} + +/** + * @brief UARTx RX pin active level inversion. + * @note This allows the use of an external inverter on the RX line. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_rxinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief UARTx RX pin active level inversion disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_rxinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief Check if UART RX pin active level is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_rxinv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXINV_MSK) == (UART_LCON_RXINV_MSK)); +} + +/** + * @brief UARTx Binary data inversion. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * The parity bit is also inverted. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_datainv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief UARTx Binary data inverted disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_datainv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief Check if UARTx Binary data is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_datainv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DATAINV_MSK) == (UART_LCON_DATAINV_MSK)); +} + +/** + * @brief Set UARTx Most significant bit first. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param msb This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_LSB_FIRST + * @arg @ref MD_UART_LCON_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_msb(UART_TypeDef *UARTx, uint32_t msb) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_MSB_MSK, msb<LCON, UART_LCON_MSB_MSK))>>UART_LCON_MSB_POS); +} + +/** + * @brief UARTx Parity bit selection. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param parity This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_PS_ODD + * @arg @ref MD_UART_LCON_PS_EVEN + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_ps(UART_TypeDef *UARTx, uint32_t parity) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_PS_MSK, parity<LCON, UART_LCON_PS_MSK))>>UART_LCON_PS_POS); +} + +/** + * @brief UARTx Parity enable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_pe(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_PE_MSK); +} + +/** + * @brief UARTx Parity disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_pe(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_PE_MSK); +} + +/** + * @brief Check if UARTx Parity is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_pe(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_PE_MSK) == (UART_LCON_PE_MSK)); +} + +/** + * @brief Set UARTx Stop bit. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance. + * @param stop This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_STOP_1 + * @arg @ref MD_UART_LCON_STOP_2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_stop(UART_TypeDef *UARTx, uint32_t stop) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_STOP_MSK, stop<LCON, UART_LCON_STOP_MSK))>>UART_LCON_STOP_POS); +} + +/** + * @brief UARTx Date length selection. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param width This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_DLS_8 + * @arg @ref MD_UART_LCON_DLS_7 + * @arg @ref MD_UART_LCON_DLS_6 + * @arg @ref MD_UART_LCON_DLS_5 + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_dls(UART_TypeDef *UARTx, uint32_t width) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_DLS_MSK, width<LCON, UART_LCON_DLS_MSK))>>UART_LCON_DLS_POSS); +} + +/** + * @brief UARTx Transmitter DMA enable. + * @note This bit is set and cleared by software. This bit enables the DMA transmitter. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_txdmaen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); +} + +/** + * @brief UARTx Transmitter DMA enable disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_txdmaen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); +} + +/** + * @brief Check if UARTx Transmitter DMA is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_txdmaen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK) == (UART_MCON_TXDMAEN_MSK)); +} + +/** + * @brief UARTx Receiver DMA enable. + * @note This bit is set and cleared by software. This bit enables the DMA Receiver. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_rxdmaen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); +} + +/** + * @brief UARTx Receiver DMA disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_rxdmaen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); +} + +/** + * @brief Check if UARTx UARTx Receiver DMA is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_rxdmaen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK) == (UART_MCON_RXDMAEN_MSK)); +} + +/** + * @brief UARTx Auto baud rate detection repeat enable. + * @note This bit is set to enable baud rate detection repeat one more time + * after the first failure of auto-baud rate detection. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_abrrept(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_MCON_ABRREPT_MSK); +} + +/** + * @brief UARTx Auto baud rate detection repeat disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_abrrept(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_MCON_ABRREPT_MSK); +} + +/** + * @brief Check if UARTx Auto baud rate detection repeat is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_abrrept(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABRREPT_MSK) == (UART_MCON_ABRREPT_MSK)); +} + +/** + * @brief Set UARTx Auto baud rate mode. + * @note MD_UART_MCON_ABRMOD_0: Mode 0 detect falling edge to second falling edge (detect 2 Bps). + * MD_UART_MCON_ABRMOD_1: Mode 1 detect falling edge to first rising edge (detect 1 Bps). + * MD_UART_MCON_ABRMOD_2: Mode 2 detect falling edge to first rising edge (detect 2 Bps). + * @param UARTx UART Instance. + * @param mode This parameter can be one of the following values: + * @arg @ref MD_UART_MCON_ABRMOD_0 + * @arg @ref MD_UART_MCON_ABRMOD_1 + * @arg @ref MD_UART_MCON_ABRMOD_2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_mcon_abrmod(UART_TypeDef *UARTx, uint32_t mode) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_ABRMOD_MSK, mode<MCON, UART_MCON_ABRMOD_MSK))>>UART_MCON_ABRMOD_POSS); +} + +/** + * @brief UARTx Auto baud rate enable. + * @note This bit is set by software and cleared by hardware after the + * auto-baud rate finish. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_abren(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_MCON_ABREN_MSK); +} + +/** + * @brief UARTx Auto baud rate disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_abren(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_MCON_ABREN_MSK); +} + +/** + * @brief Check if UARTx Auto baud rate is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_abren(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABREN_MSK) == (UART_MCON_ABREN_MSK)); +} + +/** + * @brief UARTx break request enable. + * @note This bit is set by software and automatically cleared by + * hardware in the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_bkreq(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); +} + +/** + * @brief UARTx break request disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_bkreq(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); +} + +/** + * @brief Check if UARTx break request is enabled + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_bkreq(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK) == (UART_MCON_BKREQ_MSK)); +} + +/** + * @brief UARTx Half-duplex enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_hden(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); +} + +/** + * @brief UARTx Half-duplex disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_hden(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); +} + +/** + * @brief Check if UARTx Half-duplex is enabled. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_hden(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_HDEN_MSK) == (UART_MCON_HDEN_MSK)); +} + +/** + * @brief UARTx IrDA mode enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_iren(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_IREN_MSK); +} + +/** + * @brief UARTx IrDA mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_iren(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_IREN_MSK); +} + +/** + * @brief Check if UARTx IrDA mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_iren(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_IREN_MSK) == (UART_MCON_IREN_MSK)); +} + +/** + * @brief UARTx Auto flow control enable. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_mcon_afcen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); +} + +/** + * @brief UARTx Auto flow control disable. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_mcon_afcen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); +} + +/** + * @brief Check if Auto flow control is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_afcen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK) == (UART_MCON_AFCEN_MSK)); +} + +/** + * @brief Set UARTx RTSn set control bit. + * @note If Auto flow control disable, user can control RTSn output level by this bit. + * MD_UART_MCON_RTSSET_LOW : RTSn level is 0 + * MD_UART_MCON_RTSSET_HIGH: RTSn level is 1 + * @param UARTx UART Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_UART_MCON_RTSSET_LOW + * @arg @ref MD_UART_MCON_RTSSET_HIGH + * @retval None + */ +__STATIC_INLINE void md_uart_set_mcon_rtsset(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_RTSSET_MSK, level<MCON, UART_MCON_RTSSET_MSK))>>UART_MCON_RTSSET_POS); +} + +/** + * @brief UARTx LoopBack enable. + * @note This is used to put the UART into a diagnostic mode for test purpose. + * If operating in UART mode, data on the TXD line is held high, + * while serial data output is looped back to the RXD line, internally. + * In this mode, all the interrupts are fully functional. + * If operating in infrared mode, data on the TXD with IrDA line is held low, + * while serial data output is inverted and looped back to the RXD line. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_lpbken(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); +} + +/** + * @brief UARTx LoopBack disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_lpbken(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); +} + +/** + * @brief Check if UARTx LoopBack is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lpbken(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK) == (UART_MCON_LPBKEN_MSK)); +} + +/** + * @brief Set UARTx Delay value. + * @note Contains a direction control RTSn Delay value. This register + * works in conjunction with an 8-bit counter in terms of number of + * DIVISOR bit duration. + * @param UARTx UART Instance. + * @param UARTx Delay value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rs485_dly(UART_TypeDef *UARTx, uint32_t delay) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_DLY_MSK, delay<RS485, UART_RS485_DLY_MSK))>>UART_RS485_DLY_POSS); +} + +/** + * @brief Set UARTx Address match value. + * @param UARTx UART Instance. + * @param UARTx Address match value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_addr(UART_TypeDef *UARTx, uint32_t address) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_ADDR_MSK, address<RS485, UART_RS485_ADDR_MSK))>>UART_RS485_ADDR_POSS); +} + +/** + * @brief Set UARTx Automatic address detection invert. + * @note This bit retains the DE(RTSn) polarity direction control signal on pin. + * @param UARTx UART Instance. + * @param aadinv can be one of the following value: + * @arg @ref MD_UART_RS485_AADINV_LOW (Low : Transfering data, High: Idle) + * @arg @ref MD_UART_RS485_AADINV_HIGH (High: Transfering data, Low : Idle) + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_aadinv(UART_TypeDef *UARTx, uint32_t aadinv) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_AADINV_MSK, aadinv<RS485, UART_RS485_AADINV_MSK))>>UART_RS485_AADINV_POS); +} + +/** + * @brief UARTx Automatic address detection auto-control enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rs485_aadacen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); +} + +/** + * @brief UARTx Automatic address detection auto-control disable + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rs485_aadacen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); +} + +/** + * @brief Check if UARTx Automatic address detection auto-control is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aadacen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK) == (UART_RS485_AADACEN_MSK)); +} + +/** + * @brief UARTx Automatic address detection normal mode enable. + * @note Note that it can be active with RS-485 AAD operation mode. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rs485_aadnen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); +} + +/** + * @brief UARTx Automatic address detection normal mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rs485_aadnen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); +} + +/** + * @brief Check if Automatic address detection normal mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aadnen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK) == (UART_RS485_AADNEN_MSK)); +} + +/** + * @brief UARTx Automatic address detection operation mode enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rs485_aaden(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); +} + +/** + * @brief UARTx Automatic address detection operation mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rs485_aaden(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); +} + +/** + * @brief Check if UARTx Automatic address detection operation mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aaden(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADEN_MSK) == (UART_RS485_AADEN_MSK)); +} + +/** + * @brief Set UARTx Block Length (Only UART). + * @note This bit-field gives the Block length in Smartcard T=1 + * Reception. Its value equals the number of information + * characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. + * This bit-field can be used also in other modes. In this case, the + * Block length counter is reset when RXEN=0 (receiver disabled). + * @param UARTx UART Instance. + * @param Block Length. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_blen(UART_TypeDef *UARTx, uint32_t blocklength) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_BLEN_MSK, blocklength<SCARD, UART_SCARD_BLEN_MSK))>>UART_SCARD_BLEN_POSS); +} + +/** + * @brief Set UARTx Guard time value(Only UART). + * @param UARTx UART Instance. + * @param Guard time value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_gt(UART_TypeDef *UARTx, uint32_t guardtime) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_GT_MSK, guardtime<SCARD, UART_SCARD_GT_MSK))>>UART_SCARD_GT_POSS); +} + +/** + * @brief Set UARTx Prescaler value (Only UART). + * @note In IrDA Low-power and normal IrDA mode: + * Used for programming the prescaler for dividing the UART + * source clock to achieve the low-power frequency. + * The source clock is divided by the value given in the register (8 + * significant bits) + * In Smartcard mode: + * Used for programming the prescaler for dividing the UART + * source clock to provide the Smartcard clock. + * The value given in the register (5 significant bits) is multiplied by + * 2 to give the division factor of the source clock frequency. + * @param UARTx UART Instance. + * @param Prescaler value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_scard_psc(UART_TypeDef *UARTx, uint32_t prescaler) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_PSC_MSK, prescaler<SCARD, UART_SCARD_PSC_MSK))>>UART_SCARD_PSC_POSS); +} + +/** + * @brief Set UARTx Smartcard auto-retry count (Only UART). + * @note This bit-field specifies the number of retries in transmit and + * receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic + * retransmission retries, before generating a transmission error + * (FE bit set). + * In reception mode, it specifies the number or erroneous + * reception trials, before generating a reception error (RXNE and + * PE bits set). + * @param UARTx UART Instance. + * @param smartcard auto-retry count Min_Value=0x00 Max_Value=0x07. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_sccnt(UART_TypeDef *UARTx, uint32_t count) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_SCCNT_MSK, count<SCARD, UART_SCARD_SCCNT_MSK))>>UART_SCARD_SCCNT_POSS); +} + +/** + * @brief Smartcard clock enable(Only UART). + * @note This bit allows the user to enable the SCK pin. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_sclken(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); +} + +/** + * @brief Smartcard clock disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_sclken(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); +} + +/** + * @brief Check if Smartcard clock is enable. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_sclken(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK) == (UART_SCARD_SCLKEN_MSK)); +} + +/** + * @brief Smartcard NACK enable(Only UART). + * @note This bit allows the user to enable nack detection. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_scnack(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); +} + +/** + * @brief Smartcard NACK disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_scnack(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); +} + +/** + * @brief Check if Smartcard NACK is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_scnack(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK) == (UART_SCARD_SCNACK_MSK)); +} + +/** + * @brief Smartcard mode enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_scen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); +} + +/** + * @brief Smartcard mode disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_scen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); +} + +/** + * @brief Check if Smartcard mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_scen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK) == (UART_SCARD_SCEN_MSK)); +} + +/** + * @brief Enable LIN mode break request. + * @note This bit is set by software and automatically cleared by + * hardware in the next clock cycle. + * Writing 1 to this bit sets request to send a BREAK on the line, as + * soon as the transmit machine is available. + * It generates 13 bits rate low pulse in Lin mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lin_linbkreq(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); +} + +/** + * @brief Disable LIN mode break request. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_linbkreq(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); +} + +/** + * @brief Check if LIN break is enabled + * @param None + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_linbkreq(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK) == (UART_LIN_LINBKREQ_MSK)); +} + +/** + * @brief UARTx LIN mode enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lin_linen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); +} + +/** + * @brief UART LIN mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lin_linen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); +} + +/** + * @brief Check if UARTx LIN mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lin_linen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LIN, UART_LIN_LINEN_MSK) == (UART_LIN_LINEN_MSK)); +} + +/** + * @brief UARTx receive timeout enable. + * @note When this feature is enabled, the RTOIF flag in the UART_RIF + * register is set if the RX line is idle (no reception) for the duration + * programmed in the RTOR (receiver timeout register). + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rtor_rtoen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); +} + +/** + * @brief UARTx receive timeout disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rtor_rtoen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); +} + +/** + * @brief Check if UARTx receive timeout is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rtor_rtoen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK) == (UART_RTOR_RTOEN_MSK)); +} + +/** + * @brief Set UARTx receiver timeout value. + * @note This bit-field gives the Receiver timeout value in terms of number of bit duration. + * In standard mode: + * the RTOF flag is set if, after the last received character, + * no new start bit is detected for more than the RTO value. + * In Smartcard mode: + * this value is used to implement the CWT and BWT. See Smartcard section for more details. + * In this case, the timeout measurement is done starting from the Stop Bit of the last + * received character. + * @param UARTx UART Instance. + * @param timeout UART timeout value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rtor_rto(UART_TypeDef *UARTx, uint32_t timeout) +{ + MODIFY_REG(UARTx->RTOR, UART_RTOR_RTO_MSK, timeout<RTOR, UART_RTOR_RTO_MSK))>>UART_RTOR_RTO_POSS); +} + +/** + * @brief Set UARTx Transmit FIFO level. + * @note This is used to indicate the number of data entries in the Transmit FIFO. + * It's value from 0 to 16. + * @param UARTx UART Instance. + * @param Value between Min_Data=0x00 and Max_Data=0x010. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_txfl(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_TXFL_MSK, level<FCON, UART_FCON_TXFL_MSK))>>UART_FCON_TXFL_POSS); +} + +/** + * @brief Set UARTx Transmit FIFO trigger threshold. + * @note This is used to select the threshold level in the transmit FIFO at + * which the Transmit FIFO trigger threshold flag is generated. + * @param UARTx UART Instance + * @param level This parameter can be one of the following values: + * @arg @ref MD_UART_FCON_TXTH_0 + * @arg @ref MD_UART_FCON_TXTH_2 + * @arg @ref MD_UART_FCON_TXTH_4 + * @arg @ref MD_UART_FCON_TXTH_8 + * @retval None + */ +__STATIC_INLINE void md_uart_set_fcon_txth(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_TXTH_MSK, level<FCON, UART_FCON_TXTH_MSK))>>UART_FCON_TXTH_POSS); +} + +/** + * @brief Transmit FIFO reset. + * @note When FIFO is set, all the byte in the transmit FIFO are cleared + * and treats the FIFO as empty. Note that this bit will return to 0 in + * the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_tfrst(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->FCON, UART_FCON_TFRST_MSK); +} + +/** + * @brief Set UARTx Receive FIFO level. + * @note This bit is set by hardware. This is used to indicate the number + * of data entries in the Receive FIFO. It's value from 0 to 16. + * @param UARTx UART Instance. + * @param Value between Min_Data=0x00 and Max_Data=0x010. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_rxfl(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_RXFL_MSK, level<FCON, UART_FCON_RXFL_MSK))>>UART_FCON_TXFL_POSS); +} + +/** + * @brief Set UARTx Receive FIFO trigger threshold. + * @note This is used to select the threshold level in the receiver FIFO at + * which the Receive FIFO trigger threshold flag is generated. + * @param UARTx UART Instance. + * @param level This parameter can be one of the following values: + * @arg @ref MD_UART_FCON_RXTH_1 + * @arg @ref MD_UART_FCON_RXTH_4 + * @arg @ref MD_UART_FCON_RXTH_8 + * @arg @ref MD_UART_FCON_RXTH_14 + * @retval None + */ +__STATIC_INLINE void md_uart_set_fcon_rxth(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_RXTH_MSK, level<FCON, UART_FCON_RXTH_MSK))>>UART_FCON_RXTH_POSS); +} + +/** + * @brief Receive FIFO reset + * @note When FIFO is set, all the byte in the receiver FIFO are cleared + * and treats the FIFO as empty. Note that this bit will return to 0 in + * the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_rfrst(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->FCON, UART_FCON_RFRST_MSK); +} + +/** + * @brief Check if Transmit FIFO overrun error. + * @note This bit is set and cleared by hardware Tx line start transmit + * data. An overrun error occurs when the FIFO is full and a new + * character write at the Transmit. The data in the FIFO is retained + * and the data in the TXBR register is lost. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFOERR_MSK) == (UART_STAT_TFOERR_MSK)); +} + +/** + * @brief Check if Transmit FIFO full. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer full. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFFULL_MSK) == (UART_STAT_TFFULL_MSK)); +} + +/** + * @brief Check if Transmit FIFO empty. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFEMPTY_MSK) == (UART_STAT_TFEMPTY_MSK)); +} + +/** + * @brief Check if Transmit FIFO trigger threshold flag. + * @note This bit is set and cleared by hardware when transmit FIFO + * arrived threshold level in the FCR register. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFTH_MSK) == (UART_STAT_TFTH_MSK)); +} + +/** + * @brief Check if Transmit shift register busy. + * @note This bit is cleared by hardware. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tsbsy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TSBUSY_MSK) == (UART_STAT_TSBUSY_MSK)); +} + +/** + * @brief Check if Receive FIFO underrun error. + * @note This bit is set and cleared by hardware when receive a new + * data. An underrun error occurs when the FIFO is empty at the + * receive. The data in the FIFO is read 0 in the RXBR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFUERR_MSK) == (UART_STAT_RFUERR_MSK)); +} + +/** + * @brief Check if Receive FIFO overrun error. + * @note This bit is set and cleared by hardware when read data in the + * RXBR register. An overrun error occurs when the FIFO is full + * and a new character arrives at the receiver. The data in the + * FIFO is retained and the data in the RXBR register is lost. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFOERR_MSK) == (UART_STAT_RFOERR_MSK)); +} + +/** + * @brief Check if Receive FIFO full. + * @note This bit is set and cleared by hardware when the RX FIFO is no + * longer full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFFULL_MSK) == (UART_STAT_RFFULL_MSK)); +} + +/** + * @brief Check if Receive FIFO empty. + * @note This bit is cleared when the RX FIFO is no longer empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFEMPTY_MSK) == (UART_STAT_RFEMPTY_MSK)); +} + +/** + * @brief Check if Receive FIFO trigger threshold flag. + * @note This bit is set and cleared by hardware when receive FIFO + * arrived threshold level in the FCR register. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFTH_MSK) == (UART_STAT_RFTH_MSK)); +} + +/** + * @brief Check if Receive shiftregister busy. + * @note This bit is set and cleared by hardware. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rsbsy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RSBUSY_MSK) == (UART_STAT_RSBUSY_MSK)); +} + +/** + * @brief Get UARTx Clear to send status. + * @note This bit is the complement of CTSn. When CTSn is asserted, it + * is an indication that the modem or data set is ready to exchange + * data with UART. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_get_stat_ctssta(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_CTSSTA_MSK)>>UART_STAT_CTSSTA_POS); +} + +/** + * @brief Check if Break error. + * @note This bit is used to indicate the detection of a break sequence on + * the serial input data. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_bkerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_BKERR_MSK) == (UART_STAT_BKERR_MSK)); +} + +/** + * @brief Check if Framing Error. + * @note When the received characters stop bit is a logic 0(i.e. the + * receiver did not have a valid stop bit), a framing error occurs. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_ferr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_FERR_MSK) == (UART_STAT_FERR_MSK)); +} + +/** + * @brief Check if Parity Error. + * @note When the receive character does not have correct parity + * information and is suspect, a parity error occurs. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_perr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_PERR_MSK) == (UART_STAT_PERR_MSK)); +} + +/** + * @brief Transmit FIFO overrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tfover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFOVER_MSK); +} + +/** + * @brief Transmit FIFO empty interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFEMPTY_MSK); +} + +/** + * @brief Transmit FIFO trigger threshold interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFTH_MSK); +} + +/** + * @brief Transmission byte complete enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TBC_MSK); +} + +/** + * @brief Receive FIFO underrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFUERR_MSK); +} + +/** + * @brief Receive FIFO overrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFOERR_MSK); +} + +/** + * @brief Receive FIFO full interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rffull(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFFULL_MSK); +} + +/** + * @brief Receive FIFO trigger threshold interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFTH_MSK); +} + +/** + * @brief Bit Noise detection enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_NOISE_MSK); +} + +/** + * @brief End of block interrupt enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_EOB_MSK); +} + +/** + * @brief LINBK: LIN break detection interrupt enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_LINBK_MSK); +} + +/** + * @brief Address match interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ADDRM_MSK); +} + +/** + * @brief Receiver Timeout interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXTO_MSK); +} + +/** + * @brief Delta CTS status interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_DCTS_MSK); +} + +/** + * @brief Auto-Baud rate detection Timeout interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABTO_MSK); +} + +/** + * @brief Auto-Baud rate detection End interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABEND_MSK); +} + +/** + * @brief Receiver byte error interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXBERR_MSK); +} + +/** + * @brief Transmit FIFO overrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tfover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFOVER_MSK); +} + +/** + * @brief Transmit FIFO empty interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFEMPTY_MSK); +} + +/** + * @brief Transmit FIFO trigger threshold interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFTH_MSK); +} + +/** + * @brief Transmission byte complete interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TBC_MSK); +} + +/** + * @brief Receive FIFO underrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFUERR_MSK); +} + +/** + * @brief Receive FIFO overrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFOERR_MSK); +} + +/** + * @brief Receive FIFO full interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rffull(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFFULL_MSK); +} + +/** + * @brief Receive FIFO trigger threshold interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFTH_MSK); +} + +/** + * @brief Bit Noise detection disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_NOISE_MSK); +} + +/** + * @brief End of block interrupt disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_EOB_MSK); +} + +/** + * @brief LIN break detection interrupt disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_LINBK_MSK); +} + +/** + * @brief Address match interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ADDRM_MSK); +} + +/** + * @brief Receiver Timeout interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXTO_MSK); +} + +/** + * @brief Delta CTS status interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_DCTS_MSK); +} + +/** + * @brief Auto-Baud rate detection Timeout interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABTO_MSK); +} + +/** + * @brief Auto-Baud rate detection End interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABEND_MSK); +} + +/** + * @brief Receiver byte error interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXBERR_MSK); +} + +/** + * @brief Check if Tx FIFO overrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFOVER_MSK) == (UART_IVS_TFOVER_MSK)); +} + +/** + * @brief Check if Tx FIFO empty interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFEMPTY_MSK) == (UART_IVS_TFEMPTY_MSK)); +} + +/** + * @brief Check if Tx FIFO trigger threshold interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFTH_MSK) == (UART_IVS_TFTH_MSK)); +} + +/** + * @brief Check if Tx complete interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TBC_MSK) == (UART_IVS_TBC_MSK)); +} + +/** + * @brief Check if Rx FIFO underrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFUERR_MSK) == (UART_IVS_RFUERR_MSK)); +} + +/** + * @brief Check if Rx FIFO overrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFOERR_MSK) == (UART_IVS_RFOERR_MSK)); +} + +/** + * @brief Check if Rx FIFO full interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFFULL_MSK) == (UART_IVS_RFFULL_MSK)); +} + +/** + * @brief Check if Rx FIFO trigger threshold interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFTH_MSK) == (UART_IVS_RFTH_MSK)); +} + +/** + * @brief Check if noise detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_NOISE_MSK) == (UART_IVS_NOISE_MSK)); +} + +/** + * @brief Check if end of block detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_EOB_MSK) == (UART_IVS_EOB_MSK)); +} + +/** + * @brief Check if LIN break detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_LINBK_MSK) == (UART_IVS_LINBK_MSK)); +} + +/** + * @brief Check if address match interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ADDRM_MSK) == (UART_IVS_ADDRM_MSK)); +} + +/** + * @brief Check if RX timeout interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXTO_MSK) == (UART_IVS_RXTO_MSK)); +} + +/** + * @brief Check if delta CTS status interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_DCTS_MSK) == (UART_IVS_DCTS_MSK)); +} + +/** + * @brief Check if auto-baud rate detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABTO_MSK) == (UART_IVS_ABTO_MSK)); +} + +/** + * @brief Check if auto-baud rate detection end interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABEND_MSK) == (UART_IVS_ABEND_MSK)); +} + +/** + * @brief Check if RX byte error interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXBERR_MSK) == (UART_IVS_RXBERR_MSK)); +} + +/** + * @brief Get Transmit FIFO overrun interrupt flag. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character write at the Transmit. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFOVER_MSK) == (UART_RIF_TFOVER_MSK)); +} + +/** + * @brief Get Transmit FIFO empty interrupt flag. + * @note This bit is set by hardware when transmit FIFO is empty from + * have data to empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_txempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFEMPTY_MSK) == (UART_RIF_TFEMPTY_MSK)); +} + +/** + * @brief Get Transmit FIFO trigger threshold interrupt flag + * @note This bit is set by hardware when transmit FIFO arrived + * threshold level in the FCR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFTH_MSK) == (UART_RIF_TFTH_MSK)); +} + +/** + * @brief Get Transmission byte complete interrupt flag. + * @note This bit is set by hardware when transmission byte complete. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TBC_MSK) == (UART_RIF_TBC_MSK)); +} + +/** + * @brief Get Receive FIFO underrun interrupt flag + * @note This bit is set by hardware when an underrun error occurs that + * the FIFO is empty and a new character read at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFUERR_MSK) == (UART_RIF_RFUERR_MSK)); +} + +/** + * @brief Get Receive FIFO overrun interrupt flag. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character arrive at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFOERR_MSK) == (UART_RIF_RFOERR_MSK)); +} + +/** + * @brief Get Receive FIFO full interrupt flag. + * @note This bit is set by hardware when receive FIFO is full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFFULL_MSK) == (UART_RIF_RFFULL_MSK)); +} + +/** + * @brief Get Receive FIFO trigger threshold interrupt flag. + * @note This bit is set by hardware when receive FIFO arrived threshold + * level in the FCR register. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFTH_MSK) == (UART_RIF_RFTH_MSK)); +} + +/** + * @brief Get Bit Noise detection interrupt flag. + * @note This bit is set by hardware when START bit Noise is detected. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_NOISE_MSK) == (UART_RIF_NOISE_MSK)); +} + +/** + * @brief Get End of block interrupt flag(Only UART). + * @note This bit is set by hardware when blcok length value equals the + * number of data byte. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_EOB_MSK) == (UART_RIF_EOB_MSK)); +} + +/** + * @brief Get LIN break detection interrupt flag(Only UART). + * @note This bit is set by hardware when lin break is detected. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_LINBK_MSK) == (UART_RIF_LINBK_MSK)); +} + +/** + * @brief Get Address match interrupt flag. + * @note This bit is set by hardware when the data in the RXBR register + * defined by ADD[7:0] in the RS485 register is received. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ADDRM_MSK) == (UART_RIF_ADDRM_MSK)); +} + +/** + * @brief Get Receiver Timeout interrupt flag. + * @note This bit is set by hardware when the timeout value, + * programmed in the RTOR register has lapsed, without any + * communication. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXTO_MSK) == (UART_RIF_RXTO_MSK)); +} + +/** + * @brief Get Delta CTS status interrupt flag. + * @note This bit is set by hardware when the CTS input toggles. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_DCTS_MSK) == (UART_RIF_DCTS_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection timeout interrupt flag. + * @note This bit is set by hardware when the baud rate detection timeout. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABTO_MSK) == (UART_RIF_ABTO_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection end interrupt flag. + * @note This bit is set by hardware when the baud rate detection end. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABEND_MSK) == (UART_RIF_ABEND_MSK)); +} + +/** + * @brief Get Receiver byte error flag. + * @note This bit is set by hardware when a parity error or frame error + * occurs in receiver. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXBERR_MSK) == (UART_RIF_RXBERR_MSK)); +} + +/** + * @brief Get Transmit FIFO overrun interrupt flag masked. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character write at the Transmit. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TFOVER_MSK) == (UART_IFM_TFOVER_MSK)); +} + +/** + * @brief Get Transmit FIFO empty interrupt flag masked. + * @note This bit is set by hardware when transmit FIFO is empty from + * have data to empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_txempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TFEMPTY_MSK) == (UART_IFM_TFEMPTY_MSK)); +} + +/** + * @brief Get Transmit FIFO trigger threshold interrupt flag masked. + * @note This bit is set by hardware when transmit FIFO arrived + * threshold level in the FCR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TFTH_MSK) == (UART_IFM_TFTH_MSK)); +} + +/** + * @brief Get Transmission byte complete interrupt flag masked. + * @note This bit is set by hardware when transmission byte complete. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TBC_MSK) == (UART_IFM_TBC_MSK)); +} + +/** + * @brief Get Receive FIFO underrun interrupt flag masked. + * @note This bit is set by hardware when an underrun error occurs that + * the FIFO is empty and a new character read at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFUERR_MSK) == (UART_IFM_RFUERR_MSK)); +} + +/** + * @brief Get Receive FIFO overrun interrupt flag masked. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character arrive at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFOERR_MSK) == (UART_IFM_RFOERR_MSK)); +} + +/** + * @brief Get Receive FIFO full interrupt flag masked. + * @note This bit is set by hardware when receive FIFO is full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFFULL_MSK) == (UART_IFM_RFFULL_MSK)); +} + +/** + * @brief Get Receive FIFO trigger threshold interrupt flag masked. + * @note This bit is set by hardware when receive FIFO arrived threshold + * level in the FCR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFTH_MSK) == (UART_IFM_RFTH_MSK)); +} + +/** + * @brief Get Bit Noise detection interrupt flag masked. + * @note This bit is set by hardware when START bit Noise is detected. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_NOISE_MSK) == (UART_IFM_NOISE_MSK)); +} + +/** + * @brief Get End of block interrupt flag masked(Only UART). + * @note This bit is set by hardware when block length value equals the + * number of data byte. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_EOB_MSK) == (UART_IFM_EOB_MSK)); +} + +/** + * @brief Get LIN break detection interrupt flag masked(Only UART). + * @note This bit is set by hardware when lin break is detected. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_LINBK_MSK) == (UART_IFM_LINBK_MSK)); +} + +/** + * @brief Get Address match interrupt flag masked. + * @note This bit is set by hardware when the data in the RXBR register + * defined by ADD[7:0] in the RS485 register is received. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_ADDRM_MSK) == (UART_IFM_ADDRM_MSK)); +} + +/** + * @brief Get Receiver Timeout interrupt flag masked. + * @note This bit is set by hardware when the timeout value, + * programmed in the RTOR register has lapsed, without any + * communication. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RXTO_MSK) == (UART_IFM_RXTO_MSK)); +} + +/** + * @brief Get Delta CTS status interrupt flag masked. + * @note This bit is set by hardware when the CTS input toggles. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_RIF_DCTS_MSK) == (UART_IFM_DCTS_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection timeout interrupt flag masked. + * @note This bit is set by hardware when the baud rate detection timeout. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_ABTO_MSK) == (UART_IFM_ABTO_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection end interrupt flag masked. + * @note This bit is set by hardware when the baud rate detection end. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_ABEND_MSK) == (UART_IFM_ABEND_MSK)); +} + +/** + * @brief Get Receiver byte error interrupt flag masked. + * @note This bit is set by hardware when a parity error, frame error or + * break error occurs in receiver. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RXBERR_MSK) == (UART_IFM_RXBERR_MSK)); +} + +/** + * @brief Transmit FIFO overrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_txover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFOVER_MSK); +} + +/** + * @brief Transmit FIFO empty interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_txempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFEMPTY_MSK); +} + +/** + * @brief Transmit FIFO trigger threshold interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_tfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFTH_MSK); +} + +/** + * @brief Transmission byte complete interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TBC_MSK); +} + +/** + * @brief Receive FIFO underrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFUERR_MSK); +} + +/** + * @brief Receive FIFO overrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFOERR_MSK); +} + +/** + * @brief Receive FIFO full interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rffull(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFFULL_MSK); +} + +/** + * @brief Receive FIFO trigger threshold interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFTH_MSK); +} + +/** + * @brief Bit Noise detection interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_NOISE_MSK); +} + +/** + * @brief End of block interrupt flag clear(Only UART). + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_EOB_MSK); +} + +/** + * @brief LIN break detection interrupt flag clear(Only UART). + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_LINBK_MSK); +} + +/** + * @brief Address match interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ADDRM_MSK); +} + +/** + * @brief Receiver Timeout interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXTO_MSK); +} + +/** + * @brief Delta CTS status interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_DCTS_MSK); +} + +/** + * @brief Auto-Baud rate detection timeout interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABTO_MSK); +} + +/** + * @brief Auto-Baud rate detection end interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABEND_MSK); +} + +/** + * @brief Receiver byte error interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXBERR_MSK); +} + +/** + * @} MD_UART_Public_Macros UART Public Macros + */ + +/* Public functions -----------------------------------------------------------*/ +void md_uart_set_baudrate (UART_TypeDef *UARTx, uint32_t baudrate); +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct); +void md_uart_send (UART_TypeDef *UARTx, uint8_t ch); +uint8_t md_uart_recv (UART_TypeDef *UARTx); +uint32_t md_uart_get_baudrate (UART_TypeDef *UARTx); + +/** + * @} UART + */ + +#endif + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..f2f1a86a2980284e9bd70cea93ee5e0dccbd6965 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file md_wwdt.h + * @brief ES32F0271 WWDT HEAD File. + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_WWDT_H__ +#define __MD_WWDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_wwdt.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (WWDT) +/** @defgroup WWDT WWDT + * @brief WWDT micro driver + * @{ + */ + +/* Public Init Structure ------------------------------------------------------*/ +/** @defgroup MD_WWDT_PT_INIT WWDT Public Init Structure + * @brief WWDT Init Structure. + * @{ + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDT. + This parameter can be a value of @ref WWDT_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDT window value to be compared to the downcounter. + This parameter must be a number a minimum, 0x40 and a maximum, 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDT free-running downcounter value. + This parameter must be a number between a minimum, 0x40 and a maximum, 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDT Early Wakeup Interupt is enable or not. + This parameter can be a value of @ref WWDT_EWI_Mode */ + +} md_wwdt_inittypedef; +/** + * @} MD_WWDT_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_WWDT_PUBLIC_CONSTANTS WWDT Public Constants + * @{ + */ + +/** @defgroup MD_WWDT_Prescaler WWDT Prescaler + * @{ + */ +#define WWDT_PRESCALER_1 0x00000000U /*!< WWDT counter clock = (PCLK1/4096)/1 */ +#define WWDT_PRESCALER_2 1U<CON, Reg_Value); +} + +/** + * @brief Get the WWDT_CON value + * @note None. + * @param WWD WWDT Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_wwdt_get_con(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_REG(WWD->CON)); +} + +/** + * @brief WWDT WDG Enable + * @note This bit is set by software and only cleared by hardware after a reset. + * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_con_wdga(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->CON, WWDT_CON_WDGA_MSK); +} + +/** + * @brief Indicate if WWDT WDG is enabled + * @note This bit is set by software and only cleared by hardware after a reset. + * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_enabled_wdga(WWDT_TypeDef *WWD) +{ + return (uint32_t)(READ_BIT(WWD->CON, WWDT_CON_WDGA_MSK) == (WWDT_CON_WDGA_MSK)); +} + +/** + * @brief Set WWDT T 7-bit counter + * @note These bits contain the value of the watchdog counter. + * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. + * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), + * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. + * @param WWD WWDT Instance + * @param counter is a 7-bit number + * @arg Max Value 0x7F + * @arg Min Value 0x40 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_con_t(WWDT_TypeDef *WWD, uint32_t counter) +{ + MODIFY_REG(WWD->CON, WWDT_CON_T_MSK, counter); +} + +/** + * @brief Get WWDT T 7-bit counter + * @note These bits contain the value of the watchdog counter. + * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. + * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), + * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. + * @param WWD WWDT Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x7F + * @arg Min Value 0x40 + */ +__STATIC_INLINE uint32_t md_wwdt_get_con_t(WWDT_TypeDef *WWD) +{ + return (READ_BIT(WWD->CON, WWDT_CON_T_MSK)>>WWDT_CON_T_POSS); +} + +/** + * @brief Set the WWDT_CFG value + * @note None. + * @param WWD WWDT Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg(WWDT_TypeDef *WWD, uint32_t Reg_Value) +{ + WRITE_REG(WWD->CFG, Reg_Value); +} + +/** + * @brief Get the WWDT_CFG value + * @note None. + * @param WWD WWDT Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_REG(WWD->CFG)); +} + +/** + * @brief Set WWDT WDGTB 2-bit prescaler value + * @note The time base of the prescaler can be modified as follows: + * 00: CK Counter Clock (PCLK div 4096) div 1 + * 01: CK Counter Clock (PCLK div 4096) div 2 + * 10: CK Counter Clock (PCLK div 4096) div 4 + * 11: CK Counter Clock (PCLK div 4096) div 8 + * @param WWD WWDT Instance + * @param prescaler is a 2-bit number + * @arg @ref WWDT_PRESCALER_1 + * @arg @ref WWDT_PRESCALER_2 + * @arg @ref WWDT_PRESCALER_4 + * @arg @ref WWDT_PRESCALER_8 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg_wdgtb(WWDT_TypeDef *WWD, uint32_t prescaler) +{ + MODIFY_REG(WWD->CFG, WWDT_CFG_WDGTB_MSK, prescaler); +} + +/** + * @brief Get WWDT WDGTB 2-bit prescaler value + * @note The time base of the prescaler can be modified as follows: + 00: CK Counter Clock (PCLK div 4096) div 1 + 01: CK Counter Clock (PCLK div 4096) div 2 + 10: CK Counter Clock (PCLK div 4096) div 4 + 11: CK Counter Clock (PCLK div 4096) div 8 + * @param WWD WWDT Instance + * @retval The retval can be one of the following values: + * @arg @ref WWDT_PRESCALER_1 + * @arg @ref WWDT_PRESCALER_2 + * @arg @ref WWDT_PRESCALER_4 + * @arg @ref WWDT_PRESCALER_8 + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg_wdgtb(WWDT_TypeDef *WWD) +{ + return (READ_BIT(WWD->CFG, WWDT_CFG_WDGTB_MSK)>>WWDT_CFG_WDGTB_POSS); +} + +/** + * @brief Set WWDT W 7-bit window + * @note These bits contain the window value to be compared to the downcounter. + * @param WWD WWDT Instance + * @param window is a 7-bit number + * @arg Max Value 0x7F + * @arg Min Value 0x40 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg_w(WWDT_TypeDef *WWD, uint32_t window) +{ + MODIFY_REG(WWD->CFG, WWDT_CFG_W_MSK, window); +} + +/** + * @brief Get WWDT W 7-bit window + * @note These bits contain the window value to be compared to the downcounter. + * @param WWD WWDT Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x7F + * @arg Min Value 0x40 + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg_w(WWDT_TypeDef *WWD) +{ + return (READ_BIT(WWD->CFG, WWDT_CFG_W_MSK)>>WWDT_CFG_W_POSS); +} + +/** + * @brief WWDT Early wakeup interrupt Enable + * @note A write of 1 in IER to enable this interrupt. + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_ier_ewis(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->IER, WWDT_IER_EWIS_MSK); +} + +/** + * @brief WWDT Early wakeup interrupt Disable + * @note A write of 1 in IDR to disable this interrupt. + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_disable_idr_ewis(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->IDR, WWDT_IDR_EWIS_MSK); +} + +/** + * @brief Indicate if WWDT EWI is enabled + * @note To check EWI enable or not. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_enabled_ivs_ewis(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_BIT(WWD->IVS, WWDT_IVS_EWIS_MSK) == (WWDT_IVS_EWIS_MSK)); +} + +/** + * @brief Get the early wakeup interrupt flag status + * @note This bit is set by hardware when the counter has reached the value 0x40. + It can be cleared by software by writing 1 in WWDT_ICR. This bit is + also set if the interrupt is not enabled. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_active_rif_ewif(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_BIT(WWD->RIF, WWDT_RIF_EWIF_MSK) == (WWDT_RIF_EWIF_MSK)); +} + +/** + * @brief Get the early wakeup interrupt flag masked status + * @note This bit is set by hardware when the counter has reached the value 0x40 + and the interrupt is enabled. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_active_ifm_ewim(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_BIT(WWD->IFM, WWDT_IFM_EWIM_MSK) == (WWDT_IFM_EWIM_MSK)); +} + +/** + * @brief Clear the early wakeup interrupt flag + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_clear_icr_ewic(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->ICR, WWDT_ICR_EWIC_MSK); +} + +/** + * @} MD_WWDT_Public_Macros + */ + +/** @defgroup MD_WWDT_PF_Init WWDT Init Function + * @{ + */ +void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct); +/** + * @} MD_WWDT_PF_Init + */ + +#endif + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup MD_WWDT_Private_Macros WWDG Private Macros + * @{ + */ +#define IS_MD_WWDT_ALL_INSTANCE(__INSTANCE__) (__INSTANCE__ == WWDT) + +#define IS_MD_WWDT_PRESCALER(__VALUE__) (((__VALUE__) == WWDT_PRESCALER_1) \ + || ((__VALUE__) == WWDT_PRESCALER_2) \ + || ((__VALUE__) == WWDT_PRESCALER_4) \ + || ((__VALUE__) == WWDT_PRESCALER_8)) + +#define IS_MD_WWDT_WINDOW(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) + +#define IS_MD_WWDT_COUNTER(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) + +#define IS_MD_WWDT_EWI_MODE(__VALUE__) (((__VALUE__) == WWDT_EWI_ENABLE) \ + || ((__VALUE__) == WWDT_EWI_DISABLE)) +/** + * @} MD_WWDT_Private_Macros + */ + +/** + * @} WWDT + */ +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h new file mode 100644 index 0000000000000000000000000000000000000000..5fee2e973e81058f50820544c7793ccc47fa15e8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h @@ -0,0 +1,728 @@ +/** + ************************************************************************************** + * @file usb_lowlayer_api.h + * @brief USB library lower layer api + * @data 11/9/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Includes-------------------------------------------------------------------*/ +#include "stdint.h" +#include + +#ifndef __USB_LOWLAYER_API_H__ +#define __USB_LOWLAYER_API_H__ + + +/** + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public constants -----------------------------------------------------------*/ + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_int_enable() and +// md_usb_hosdev_int_disable() as the ui32Flags parameter, and are returned from +// md_usb_hosdev_int_status(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_int_enable() +// and md_usb_hosdev_endpoint_int_disable() as the ui32Flags parameter, and +// are returned from md_usb_hosdev_endpoint_int_status(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hos_speed_get() 0r +// md_usb_dev_speed_get(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hosdev_endpoint_status(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error +// (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the +// specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a +// device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device +// (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a +// device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a +// device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous +// transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to +// a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data +// to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before +// Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_endpoint_config_set() and +// md_usb_dev_endpoint_config_set() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DUAL_BUFFERING 0x00000008 // Dual buffering enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for +// high-speed Bulk and Interrupt +// endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_pwr_config() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_hos_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_dev_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// md_usb_lpm_link_state_get() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_lpm_int_enable() +// or md_usb_lpm_int_disable() functions or are returned from the md_usb_lpm_status() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_clock_enable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the md_usb_ulpi_config() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// md_usb_hos_endpoint_config_set() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_fifo_config_set() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_data_send() +// as the ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for +// endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint +// 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint +// 0) + +//***************************************************************************** +// +// The following are values are returned by the md_usb_hosdev_mode_get() function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host +// mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in +// Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not +// set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of +// the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of +// the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Channel configuration values. +// +//***************************************************************************** +#define DMA_DST_INC_8 0x00000000 +#define DMA_DST_INC_16 0x40000000 +#define DMA_DST_INC_32 0x80000000 +#define DMA_DST_INC_NONE 0xc0000000 +#define DMA_SRC_INC_8 0x00000000 +#define DMA_SRC_INC_16 0x04000000 +#define DMA_SRC_INC_32 0x08000000 +#define DMA_SRC_INC_NONE 0x0c000000 +#define DMA_SIZE_8 0x00000000 +#define DMA_SIZE_16 0x11000000 +#define DMA_SIZE_32 0x22000000 +#define DMA_DST_PROT_PRIV 0x00200000 +#define DMA_SRC_PROT_PRIV 0x00040000 +#define DMA_ARB_1 0x00000000 +#define DMA_ARB_2 0x00004000 +#define DMA_ARB_4 0x00008000 +#define DMA_ARB_8 0x0000c000 +#define DMA_ARB_16 0x00010000 +#define DMA_ARB_32 0x00014000 +#define DMA_ARB_64 0x00018000 +#define DMA_ARB_128 0x0001c000 +#define DMA_ARB_256 0x00020000 +#define DMA_ARB_512 0x00024000 +#define DMA_ARB_1024 0x00028000 +#define DMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_int_enable() and md_usb_dma_channel_int_status() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_status() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_mode_config() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +//***************************************************************************** +// +// Flags that can be passed to DMAChannelAttributeEnable(), +// DMAChannelAttributeDisable(), and returned from DMAChannelAttributeGet(). +// +//***************************************************************************** +#define DMA_ATTR_USEBURST 0x00000001 +#define DMA_ATTR_ALTSELECT 0x00000002 +#define DMA_ATTR_HIGH_PRIORITY 0x00000004 +#define DMA_ATTR_REQMASK 0x00000008 +#define DMA_ATTR_ALL 0x0000000F + +/* Public functions -----------------------------------------------------------*/ +/** + * @{ SYSTEM API. + */ +extern void md_usb_system_int_disable(void); +extern void md_usb_system_int_enable(void); +extern void md_usb_re_config(bool Device); /* Weak defination */ +extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ +extern void md_usb_systic_disable(void); +extern void md_usb_controller_reset(void); +extern void md_usb_controller_enable(void); +extern void md_usb_controller_disable(void); +extern void md_usb_clk_phy_enable(void); +extern void md_usb_clk_phy_disable(void); +extern uint32_t md_usb_nvic_number_get(void); +extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ +extern void md_usb_nvic_enable(void); +extern void md_usb_nvic_disable(void); +/** + * @} SYSTEM API. + */ + +/** + * @{ USB basic API. + */ +/* Host Mode */ +extern void md_usb_hos_reset(bool bStart); +extern void md_usb_hos_resume(bool bStart); +extern void md_usb_hos_suspend(void); +extern void md_usb_hos_request_status(void); +extern void md_usb_hos_request_in(uint32_t ui32Endpoint); +extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); +extern uint32_t md_usb_hos_speed_get(void); +extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +/* Device Mode */ +extern void md_usb_dev_addr_set(uint8_t ui32Address); +extern uint8_t md_usb_dev_addr_get(void); +extern void md_usb_dev_connect(void); +extern void md_usb_dev_disconnect(void); +extern uint32_t md_usb_dev_speed_get(void); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_frame_get(void); +extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_int_status(void); +extern uint32_t md_usb_hosdev_mode_get(void); +/* otg Mode */ +extern void md_usb_otg_session_request(bool bStart); +extern void md_usb_force_host_mode(void); +extern void md_usb_force_device_mode(void); +extern void md_usb_force_otg_mode(void); +extern void md_usb_mode_config(uint32_t ui32Mode); +/** + * @} USB basic API. + */ + +/** + * @{ USB endpoint API. + */ +/* Host Mode */ +extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); +extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, + bool bDataToggle, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, + bool bEnable); +/* Device Mode */ +extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); +extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, + uint8_t *pui8Data, + uint32_t ui32Size); +extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); +extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_endpoint_int_status(void); +extern uint32_t md_usb_endpoint_number_get(void); +/** + * @} USB endpoint API. + */ + +/** + * @{ USB FIFO API. + */ +extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); +extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, + uint32_t ui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); +/** + * @} USB FIFO API. + */ + +/** + * @{ USB PWR API.it is not supported by es32f0271. + */ +extern void md_usb_hos_pwr_disable(void); +extern void md_usb_hos_pwr_enable(void); +extern void md_usb_hos_pwr_config(uint32_t ui32Flags); +extern void md_usb_hos_pwrfault_disable(void); +extern void md_usb_hos_pwrfault_enable(void); +/** + * @} USB PWR API. + */ + +/** + * @{ USB LPM API.it is not supported by es32f0271. + */ +extern void md_usb_hos_lpm_send(uint32_t ui32Address, + uint32_t uiEndpoint); +extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, + uint32_t ui32Config); +extern bool md_usb_lpm_remotewake_is_enabled(void); +extern void md_usb_hos_lpm_resume(void); +extern void md_usb_dev_lpm_remotewake(void); +extern void md_usb_dev_lpm_config(uint32_t ui32Config); +extern void md_usb_dev_lpm_enable(void); +extern void md_usb_dev_lpm_disable(void); +extern uint32_t md_usb_lpm_link_state_get(void); +extern uint32_t md_usb_lpm_endpoint_get(void); +extern uint32_t md_usb_lpm_status(void); +extern void md_usb_lpm_int_disable(uint32_t ui32Ints); +extern void md_usb_lpm_int_enable(uint32_t ui32Ints); +/** + * @} USB LPM API. + */ + +/** + * @{ USB ULPI API.it is not supported by es32f0271. + */ +extern void md_usb_ulpi_config(uint32_t ui32Config); +extern void md_usb_ulpi_enable(void); +extern void md_usb_ulpi_disable(void); +extern uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg); +extern void md_usb_ulpi_reg_write(uint8_t ui8Reg, + uint8_t ui8Data); +/** + * @} USB ULPI API. + */ + +/** + * @{ USB DMA API.it is not supported by es32f0271. + */ +extern void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_config(uint32_t ui32Channel, + uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_address_set(uint32_t ui32Channel, + void *pvAddress); +extern void *md_usb_dma_channel_address_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_count_set(uint32_t ui32Count, + uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_int_status(void); +extern void md_usb_dma_channel_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_status(uint32_t ui32Channel); +extern void md_usb_dma_channel_status_clear(uint32_t ui32Channel, + uint32_t ui32Status); +/** + * @} USB DMA API. + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html new file mode 100644 index 0000000000000000000000000000000000000000..de5a1aada3ce5ba777e37769174f013d1ba49a80 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html @@ -0,0 +1,17 @@ + + + + +ReleaseNote +

ES32F0271 MD Release Note

+

V1.00 2019-1-4

+

初版发布

+

V1.01 2019-5-7

+

1.修改USB MD库相关接口

+

V1.03 2019-09-23

+
    +
  1. 增加ADC校準函數
    2. + +
+ + \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..d8571b0912eec9f0450b874fa185d5d04f46cf13 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file md_adc.c + * @brief ES32F0271 ADC Source File. + * + * @version V1.00.01 + * @data 7/01/2019 + * @author Taipei AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + + +/* Includes -------------------------------------------------------------------*/ +#include "md_adc.h" +#include "md_syscfg.h" +#include + + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup ADC ADC + * @brief ADC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +#define Reference_V1 1 //First reference point +#define Reference_V2 2 //Second reference point + +double Ideal_V1; +double Ideal_V2; +double Reference_V1_ADCValue ; +double Reference_V2_ADCValue ; + +/* Private function prototypes ------------------------------------------------*/ +void (*md_adc_SS0_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_ss0_mux0_mux0, + md_adc_set_ss0_mux0_mux1, + md_adc_set_ss0_mux0_mux2, + md_adc_set_ss0_mux0_mux3, + md_adc_set_ss0_mux0_mux4, + md_adc_set_ss0_mux0_mux5, + md_adc_set_ss0_mux0_mux6, + md_adc_set_ss0_mux0_mux7, + md_adc_set_ss0_mux1_mux8, + md_adc_set_ss0_mux1_mux9, + md_adc_set_ss0_mux1_mux10, + md_adc_set_ss0_mux1_mux11, + md_adc_set_ss0_mux1_mux12, + md_adc_set_ss0_mux1_mux13, + md_adc_set_ss0_mux1_mux14, + md_adc_set_ss0_mux1_mux15 +}; + +void (*md_adc_SS1_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_ss0_mux0_mux0, + md_adc_set_ss0_mux0_mux1, + md_adc_set_ss0_mux0_mux2, + md_adc_set_ss0_mux0_mux3, + md_adc_set_ss0_mux0_mux4, + md_adc_set_ss0_mux0_mux5, + md_adc_set_ss0_mux0_mux6, + md_adc_set_ss0_mux0_mux7, +}; + +void (*md_adc_SS2_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_ss0_mux0_mux0, + md_adc_set_ss0_mux0_mux1, + md_adc_set_ss0_mux0_mux2, + md_adc_set_ss0_mux0_mux3, +}; + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup ADC_PUB_FUNC ADC Public Functions + * @brief ADC Public Functions + * @{ + */ +/** + * @brief ADC Initialization Function. + * @param ADC Instance. + * @param channel + * @retval None + */ +void md_adc_init(ADC_TypeDef *ADCx, md_adc_inittypedef *ADC_InitStruct, uint8_t *channel) +{ + uint8_t i = 0; + + md_syscfg_enable_cfg_currgen(SYSCFG); + md_syscfg_set_cfg_vlrs(SYSCFG, ADC_InitStruct->VRLS); + md_syscfg_enable_cfg_vrefen(SYSCFG); + + if (ADC_InitStruct->SSx == 0) + { + md_adc_set_ss0_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss0_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + + for (i = 0; i < 16; i++) + md_adc_SS0_sample[i](ADC, channel[i]); + + md_adc_enable_ier_ss0ie(ADC); + md_adc_set_ss0_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss0_end_ie15(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss0en(ADC); + } + else if (ADC_InitStruct->SSx == 1) + { + md_adc_set_ss1_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss1_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + for (i = 0; i < 8; i++) + md_adc_SS1_sample[i](ADC, channel[i]); + + md_adc_enable_ier_ss1ie(ADC); + md_adc_set_ss1_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss1_end_ie7(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss1en(ADC); + } + else if (ADC_InitStruct->SSx == 2) + { + md_adc_set_ss2_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss2_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + for (i = 0; i < 4; i++) + md_adc_SS2_sample[i](ADC, channel[i]); + + md_adc_enable_ier_ss2ie(ADC); + md_adc_set_ss2_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss2_end_ie3(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss2en(ADC); + } + else + { + md_adc_set_ss3_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss3_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + MODIFY_REG(ADC->SS3_MUX0, ADC_SS3_MUX0_MUX0_MSK, MD_ADC_SS_MUX_ADIN8 << ADC_SS3_MUX0_MUX0_POSS); + + md_adc_enable_ier_ss3ie(ADC); + md_adc_set_ss3_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss3_end_ie0(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss3en(ADC); + } +} + + +/** + * @brief Get the ADC calibration offset data + * @param vref: reference v + * @param vdd: external v + * @param offset: Get Offset + * @param coefficient: Get Coefficient + * @retval None + */ +void md_adc_calibration_data(double vdd, double vref,double *offset,double *coefficient) +{ + Ideal_V1 = Reference_V1 / vref * 4096; + Ideal_V2 = Reference_V2 / vref * 4096; + if (vdd == 5 && vref == 5) + { + if ((FC->ADCTRIM_VDD5V_VREF5V >> 24) == 0xA5) + { + Reference_V1_ADCValue = FC->ADCTRIM_VDD5V_VREF5V & 0xFFF; + Reference_V2_ADCValue = (FC->ADCTRIM_VDD5V_VREF5V >> 12) & 0xFFF; + } + } + else if (vdd == 3.3 && vref == 3.3) + { + if ((FC->ADCTRIM_VDD3V3_VREF3V3 >> 24) == 0xA5) + { + Reference_V1_ADCValue = FC->ADCTRIM_VDD3V3_VREF3V3 & 0xFFF; + Reference_V2_ADCValue = (FC->ADCTRIM_VDD3V3_VREF3V3 >> 12) & 0xFFF; + } + } + else if ((vdd == 5 && vref == 2.5) || (vdd == 3.3 && vref == 2.5)) + { + if ((FC->ADCTRIM_VDD5V_VREF2V5 >> 24) == 0xA5) + { + Reference_V1_ADCValue = FC->ADCTRIM_VDD5V_VREF2V5 & 0xFFF; + Reference_V2_ADCValue = (FC->ADCTRIM_VDD5V_VREF2V5 >> 12) & 0xFFF; + } + } + else + { + + } + +// Reference_V1_ADCValue = 115 ; +// Reference_V2_ADCValue = 365 ; + + printf("Ideal_V1:%.2f\r\n", Ideal_V1); + printf("Ideal_V2:%.2f\r\n", Ideal_V2); + printf("Reference_V1_ADCValue:%.2f\r\n", Reference_V1_ADCValue); + printf("Reference_V2_ADCValue:%.2f\r\n", Reference_V2_ADCValue); + + *offset = (Reference_V2 * Reference_V1_ADCValue - Reference_V1 * Reference_V2_ADCValue) / (Reference_V2 - Reference_V1); + printf("Offset=%.2f\r\n", *offset); + *coefficient = Ideal_V1 / (Reference_V1_ADCValue - *offset); + printf("Coefficient=%.2f\r\n", *coefficient); +} + +/** + * @brief Get the ADC fixed data + * @param SSx: Sequence SSx + * @param offset:input offset + * @param coefficient: input coefficient + * @param calibration :get calibration result + * @retval None + */ + +void md_adc_get_data(uint8_t SSx,double offset,double coefficient, uint16_t *calibration) +{ + uint16_t i, data, s_times; + double calibration_value = 0; + + if (SSx == 0) + s_times = 16; + else if (SSx == 1) + s_times = 8; + else if (SSx == 2) + s_times = 4; + else + s_times = 1; + + for (i = 0; i < s_times; i++) + { + if(SSx == 0) + data = md_adc_get_ss0_data(ADC); + else if(SSx == 1) + data = md_adc_get_ss1_data(ADC); + else if(SSx == 2) + data = md_adc_get_ss2_data(ADC); + else + data = md_adc_get_ss3_data(ADC); + if(data >= 4095) + data = 4095; + printf("data = %4d\r\n",data); + calibration_value = (data - offset) * coefficient; + if (calibration_value >= 4095) + calibration_value = 4095; + *calibration++=(uint16_t)calibration_value; + } +} +/** + * @} ADC_PUB_FUNC ADC Public Functions + */ + +/** + * @} ADC + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c new file mode 100644 index 0000000000000000000000000000000000000000..ce5d644209d90e0dceec35a37771905c72a81eb8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file md_fc.c + * @brief ES32F0271 FC Source File. + * + * @version V1.00.01 + * @date day/mon/year + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_syscfg.h" +#include "md_fc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (FC) + +/** @defgroup FC FC + * @brief FC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Private constants ----------------------------------------------------------*/ +/** @defgroup MD_FC_Private_Constants FC Private Constants + * @{ + */ + +#define REMAPDATA_BASE (( uint32_t)0x00000000) /* FLASH Main (64K Bytes) */ +#define REMAPINFO_BASE (( uint32_t)0x00000000) /* FLASH Info ( 6K Bytes) - Boot Loader Memory */ + +#define EFOPT_PAGE6_OFFSET (MD_FC_PC_EF_IPAGESZ*6) +#define EFOPT_PAGE7_OFFSET (MD_FC_PC_EF_IPAGESZ*7) +#define EFOPT_PL1_OFFSET (MD_FC_PC_EF_IPAGESZ*7+0x0) +#define EFOPT_PL2_OFFSET (MD_FC_PC_EF_IPAGESZ*6+0x28) +#define EFOPT_REMAP_OFFSET (MD_FC_PC_EF_IPAGESZ*7+0x8) + +/** + * @} MD_FC_Private_Constants + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Functions FC Public Functions + * @{ + */ + +/** + * @brief FC main erase. + * @note To prevent unexpected code branch, the main erase function must specify a dedicated main erase ID + * @param MEraseID Key for main erase, must be 0xA5A5AA55 + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Main flash erased + * - ERROR: Main erase ID mismatch + */ +ErrorStatus md_fc_merase(uint32_t MEraseID) +{ + ErrorStatus status = ERROR; + + /* Check the ID */ + if (MEraseID != MD_FC_PC_EF_MERASEID) + return status; + + /* Write MERASE to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_MACRO_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Sector Erase + * @note To prevent unexpected code branch, the page erase function must specify the complement start address + * @param pSErasePara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Specified page address erased + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_serase(md_fc_ControlTypeDef *pSErasePara) +{ + ErrorStatus status = ERROR; + + /* Check the start address and complement of start address*/ + if (pSErasePara->SAddr & pSErasePara->SAddrC) + return status; + + /* Write sector address to PA*/ + md_fc_set_pa_prog_addr(pSErasePara->SAddr); + /* Write SERASE to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_SECTOR_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Program + * @note To prevent unexpected code branch, the page program function must specify the complement start address + * @param pProgramPara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Data in data buffer programed to specified page address + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara) +{ + ErrorStatus status = ERROR; + uint16_t BCnt; + + md_fc_set_pa_pcnt(pProgramPara->BCnt); + md_fc_set_pa_prog_addr(pProgramPara->SAddr); + BCnt = pProgramPara->BCnt; + BCnt >>= 3; + + while (BCnt--) + { + /* Check the start address and complement of start address*/ + if (pProgramPara->SAddr & pProgramPara->SAddrC) + return status; + + /* Write lower 32bit program data to PLD*/ + md_fc_set_pld(*pProgramPara->pU32Buf++); + /* Write higher 32bit program data to PHD*/ + md_fc_set_phd(*pProgramPara->pU32Buf++); + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + } + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Read + * @param pReadPara Pointer to structure md_fc_ControlTypeDef + * @retval Always return SUCCESS + * - Data in specified page address read to data buffer + */ +ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara) +{ + ErrorStatus status = SUCCESS; + uint32_t *EFAddr; + uint16_t BCnt; + + if (md_syscfg_get_remap_memmod(SYSCFG) == MD_SYSCFG_MEMMOD_MAIN) /* Reamp from Main */ + EFAddr = (uint32_t *)(REMAPDATA_BASE + pReadPara->SAddr); + else + EFAddr = (uint32_t *)(FLASH_BASE + pReadPara->SAddr); + + BCnt = pReadPara->BCnt; + BCnt >>= 2; + + while (BCnt--) + *pReadPara->pU32Buf++ = *EFAddr++; + + return status; +} + +/** + * @brief FC Update Protect Level 1 Setting + * @param pUpdPL1Para Pointer to structure md_fc_UpdProtTypeDdef + * @retval Always return SUCCESS + */ +ErrorStatus md_fc_updprotl1(md_fc_UpdProtTypeDef *pUpdPL1Para) +{ + ErrorStatus status = SUCCESS; + uint32_t EFProtL1L, EFProtL1H; + + EFProtL1L = FC->OP_PRT1L; + EFProtL1H = FC->OP_PRT1H; + + if ((EFProtL1L == 0xffffffffUL) && (EFProtL1H == 0xffffffffUL)) /* First Time to Set Level1 */ + { + /* Write offset address to PA*/ + md_fc_set_pa_prog_addr(EFOPT_PL1_OFFSET); + md_fc_enable_pa_ifren(); + /* Write lower 32bit update data to PLD*/ + md_fc_set_pld(pUpdPL1Para->UpdateL); + /* Write higher 32bit update data to PHD*/ + md_fc_set_phd(pUpdPL1Para->UpdateH); + + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + } + else + { + /* Write lower 32bit clear data to PLD*/ + md_fc_set_pld(pUpdPL1Para->ClearL); + /* Write higher 32bit clear data to PHD*/ + md_fc_set_phd(pUpdPL1Para->ClearH); + + /* Write lower 32bit data to UPL*/ + md_fc_set_upl(pUpdPL1Para->UpdateL); + /* Write higher 32bit data to UPH*/ + md_fc_set_uph(pUpdPL1Para->UpdateH); + + /* Write UPDPL1 to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_UPDATE_LV1_PROTECT); + } + + return status; +} + +/** + * @brief FC Update Protect Level 2 Setting + * @param pUpdPL2Para Pointer to structure md_fc_UpdProtTypeDdef + * @retval Always return SUCCESS + */ +ErrorStatus md_fc_updprotl2(md_fc_UpdProtTypeDef *pUpdPL2Para) +{ + ErrorStatus status = SUCCESS; + uint32_t EFProtL2L, EFProtL2H; + + EFProtL2L = FC->OP_PRT2L; + EFProtL2H = FC->OP_PRT2H; + + if ((EFProtL2L == 0xffffffffUL) && (EFProtL2H == 0xffffffffUL)) /* First Time to Set Level2 */ + { + /* Write offset address to PA*/ + md_fc_set_pa_prog_addr(EFOPT_PL2_OFFSET); + md_fc_enable_pa_ifren(); + /* Write lower 32bit update data to PLD*/ + md_fc_set_pld(pUpdPL2Para->UpdateL); + /* Write higher 32bit update data to PHD*/ + md_fc_set_phd(pUpdPL2Para->UpdateH); + + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + } + else + { + /* Write lower 32bit clear data to PLD*/ + md_fc_set_pld(pUpdPL2Para->ClearL); + /* Write higher 32bit clear data to PHD*/ + md_fc_set_phd(pUpdPL2Para->ClearH); + + /* Write lower 32bit data to UPL*/ + md_fc_set_upl(pUpdPL2Para->UpdateL); + /* Write higher 32bit data to UPH*/ + md_fc_set_uph(pUpdPL2Para->UpdateH); + + /* Write UPDPL2 to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_UPDATE_LV2_PROTECT); + } + + return status; +} + +/** + * @brief FC Update Remap Option + * @param UpdRemap New remap setting value (remap address=valus(0x0~0xf)*0x1000, 0x10=BootLoader) + * @retval Always return SUCCESS + */ +ErrorStatus md_fc_updremap(uint8_t UpdRemap) +{ + ErrorStatus status = SUCCESS; + + /* Write sector address to PA*/ + md_fc_enable_pa_ifren(); + md_fc_set_pa_prog_addr(EFOPT_PAGE7_OFFSET); + /* Write SERASE to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_SECTOR_ERASE); + /* Write remap offset address to PA*/ + md_fc_set_pa_prog_addr(EFOPT_REMAP_OFFSET); + md_fc_enable_pa_ifren(); + /* Write lower 32bit remap data to PLD*/ + md_fc_set_pld(0xffffff00UL | UpdRemap); + /* Write higher 32bit remap data to PHD*/ + md_fc_set_phd(0xffffffffUL); + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + + return status; +} + +/** + * @} MD_FC_Public_Functions + */ + +/** + * @} FC + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..0fa1126bab3d2b47582e0fe5d13eb2398213c9cb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file md_gpio.c + * @brief ES32F0271 GPIO Source File. + * + * @version V1.00.01 + * @data day/mon/year + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_gpio.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) + +/** @defgroup GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup MD_GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_MD_GPIO_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == GPIOA) \ + || (__INSTANCE__ == GPIOB)) \ +|| (__INSTANCE__ == GPIOC)) \ +|| (__INSTANCE__ == GPIOD)) + +#define IS_MD_GPIO_PIN(__VALUE__) (((__VALUE__) == MD_GPIO_PIN_0) \ + || ((__VALUE__) == MD_GPIO_PIN_1) \ + || ((__VALUE__) == MD_GPIO_PIN_2) \ + || ((__VALUE__) == MD_GPIO_PIN_3) \ + || ((__VALUE__) == MD_GPIO_PIN_4) \ + || ((__VALUE__) == MD_GPIO_PIN_5) \ + || ((__VALUE__) == MD_GPIO_PIN_6) \ + || ((__VALUE__) == MD_GPIO_PIN_7) \ + || ((__VALUE__) == MD_GPIO_PIN_8) \ + || ((__VALUE__) == MD_GPIO_PIN_9) \ + || ((__VALUE__) == MD_GPIO_PIN_10) \ + || ((__VALUE__) == MD_GPIO_PIN_11) \ + || ((__VALUE__) == MD_GPIO_PIN_12) \ + || ((__VALUE__) == MD_GPIO_PIN_13) \ + || ((__VALUE__) == MD_GPIO_PIN_14) \ + || ((__VALUE__) == MD_GPIO_PIN_15)) \ + +#define IS_MD_GPIO_MODE(__VALUE__) (((__VALUE__) == MD_GPIO_MODE_INPUT) \ + || ((__VALUE__) == MD_GPIO_MODE_OUTPUT) \ + || ((__VALUE__) == MD_GPIO_MODE_FUNCTION) \ + || ((__VALUE__) == MD_GPIO_MODE_ANALOG)) + +#define IS_MD_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == MD_GPIO_OUTPUT_PUSHPULL) \ + || ((__VALUE__) == MD_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_MD_GPIO_PULL(__VALUE__) (((__VALUE__) == MD_GPIO_PULL_FLOATING) \ + || ((__VALUE__) == MD_GPIO_PULL_UP) \ + || ((__VALUE__) == MD_GPIO_PULL_DOWN) + +#define IS_MD_GPIO_DS(__VALUE__) (((__VALUE__) == MD_GPIO_DS_8mA) \ + || ((__VALUE__) == MD_GPIO_DS_16mA)) + +#define IS_MD_GPIO_FUNCTION(__VALUE__) (((__VALUE__) == MD_GPIO_AF0) \ + || ((__VALUE__) == MD_GPIO_AF1) \ + || ((__VALUE__) == MD_GPIO_AF2) \ + || ((__VALUE__) == MD_GPIO_AF3) \ + || ((__VALUE__) == MD_GPIO_AF4) \ + || ((__VALUE__) == MD_GPIO_AF5) \ + || ((__VALUE__) == MD_GPIO_AF6) \ + || ((__VALUE__) == MD_GPIO_AF7)) + +#define IS_MD_GPIO_IST(__VALUE__) (((__VALUE__) == MD_GPIO_IST_TTL) \ + || ((__VALUE__) == MD_GPIO_IST_CMOS)) + +/** + * @} MD_GPIO_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @addtogroup MD_GPIO_PF_Init GPIO Public Init Functions + * @{ + */ + +/** + * @brief De-initialize the GPIO registers to their default reset values. + * @param GPIOx GPIO Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: GPIO registers are not de-initialized + */ +ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force reset of GPIO clock */ + if (GPIOx == GPIOA) + { + md_rcu_enable_ahbrst_gpaen(RCU); + } + else if (GPIOx == GPIOB) + { + md_rcu_enable_ahbrst_gpben(RCU); + } + else if (GPIOx == GPIOC) + { + md_rcu_enable_ahbrst_gpcen(RCU); + } + else /* if(GPIOx==GPIOD) */ + { + md_rcu_enable_ahbrst_gpden(RCU); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief Initialize the GPIO registers according to the specified parameters in GPIO_InitStruct. + * @note As some bits in GPIO configuration registers can only be written when the GPIO is disabled (GPIO_CR1_SPE bit =0), + * GPIO IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param GPIOx GPIO Instance + * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the GPIO Instance GPIOx*/ + assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); + + /* Check the GPIO parameters from GPIO_InitStruct*/ + assert_param(IS_MD_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_MD_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_MD_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + assert_param(IS_MD_GPIO_PULL(GPIO_InitStruct->Pull)); + assert_param(IS_MD_GPIO_DS(GPIO_InitStruct->OutDrive)); + assert_param(IS_MD_GPIO_FUNCTION(GPIO_InitStruct->Function)); + + if (POSITION_VAL(GPIO_InitStruct->Pin) <= 7) + { + md_gpio_set_function0_7(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); + } + else + { + md_gpio_set_function8_15(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); + } + + md_gpio_set_mode(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Mode); + md_gpio_set_output_type(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + md_gpio_set_pull(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Pull); + md_gpio_set_ds(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutDrive); + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_gpio_inittypedef field to default value. + * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure + * whose fields will be set to default values. + * @retval None + */ +void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct) +{ + /* Set GPIO_InitStruct fields to default values */ + GPIO_InitStruct->Function = MD_GPIO_AF0; + GPIO_InitStruct->Mode = MD_GPIO_MODE_ANALOG; + GPIO_InitStruct->OutDrive = MD_GPIO_DS_8mA; + GPIO_InitStruct->OutputType = MD_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = MD_GPIO_PULL_FLOATING; + GPIO_InitStruct->Pin = MD_GPIO_PIN_ALL; +} + +/** + * @} MD_GPIO_PF_Init + */ + +/** + * @} MD_GPIO_Public_Functions + */ + +/** + * @} GPIO + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..e2dab7dc57ad99e2b39faf375025aab336c1aa8c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c @@ -0,0 +1,245 @@ +/** + ****************************************************************************** + * @file md_i2c.c + * @brief ES32F0271 I2C Source File. + * + * @version V1.00.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_i2c.h" +#include "md_rcu.h" +#include +#include "stdint.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. + * @param I2Cx I2C Instance + * @param I2C_InitStruct pointer to a @ref md_i2c_inittypedef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct) +{ + ErrorStatus status = ERROR; + uint8_t pllmulnow; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_MD_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_MD_I2C_TIMING(I2C_InitStruct->Timing)); + assert_param(IS_MD_I2C_ADDRSIZE(I2C_InitStruct->AddrSize)); + assert_param(IS_MD_I2C_ADDRESS1(I2C_InitStruct->Address1)); + assert_param(IS_MD_I2C_DUALADDRESSMODE(I2C_InitStruct->DualAddressMode)); + assert_param(IS_MD_I2C_ADDRESS2(I2C_InitStruct->Address2)); + assert_param(IS_MD_I2C_ADDRESS2MASKS(I2C_InitStruct->Address2Masks)); + /* Check the PLL clock, if not corrt, modify it */ + pllmulnow = md_rcu_get_cfg_pllmul(RCU); + + if (pllmulnow != (uint8_t)((I2C_InitStruct->Timing) >> 28)) + { + md_rcu_pllreinit((uint8_t)((I2C_InitStruct->Timing) >> 28)); + } + + md_i2c_disable_con1_pe(I2Cx); + md_i2c_set_timingr_presc(I2Cx, ((I2C_InitStruct->Timing) >> 24) & 0xF); + md_i2c_set_timingr_scll(I2Cx, ((I2C_InitStruct->Timing) >> 16) & 0xFF); + md_i2c_set_timingr_sclh(I2Cx, ((I2C_InitStruct->Timing) >> 8) & 0xFF); + md_i2c_set_timingr_sdadel(I2Cx, ((I2C_InitStruct->Timing) >> 4) & 0xF); + md_i2c_set_timingr_scldel(I2Cx, (I2C_InitStruct->Timing) & 0xF); + md_i2c_enable_con1_pe(I2Cx); + + md_i2c_disable_addr1_oa1en(I2Cx); + md_i2c_set_addr1_oa1(I2Cx, I2C_InitStruct->Address1); + + if (I2C_InitStruct->AddrSize == MD_I2C_OA1_10BIT) + md_i2c_set_addr1_oa1mode(I2Cx, MD_I2C_OA1_10BIT); + else + md_i2c_set_addr1_oa1mode(I2Cx, MD_I2C_OA1_7BIT); + + md_i2c_enable_addr1_oa1en(I2Cx); + + if (I2C_InitStruct->DualAddressMode == MD_I2C_DUALADDRESS_ENABLE) + { + md_i2c_disable_addr2_oa2en(I2Cx); + md_i2c_set_addr2_oa2mask(I2Cx, I2C_InitStruct->Address2Masks); + md_i2c_set_addr2_oa2(I2Cx, I2C_InitStruct->Address2); + md_i2c_enable_addr2_oa2en(I2Cx); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_i2c_inittypedef field to default value. + * @param UART_InitStruct pointer to a @ref md_i2c_inittypedef structure + * whose fields will be set to default values. + * @retval None + */ +void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct) +{ + /* Set UART_InitStruct fields to default values */ + I2C_InitStruct->Timing = CLK100kHz48M; + I2C_InitStruct->AddrSize = MD_I2C_ADDRESSINGMODE_7BIT; + I2C_InitStruct->Address1 = 0x50 << 1; + I2C_InitStruct->DualAddressMode = MD_I2C_DUALADDRESS_DISABLE; + I2C_InitStruct->Address2 = 0x70 << 1; + I2C_InitStruct->Address2Masks = MD_I2C_ADDR2_NOMASK; +} + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_master_send(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf) +{ + uint8_t index; + + /* Config Device(slave) address */ + if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_10BIT); + else + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_7BIT); + + md_i2c_set_con2_sadd(I2Cx, DevAddr); + md_i2c_set_con2_nbytes(I2Cx, Nbyte); + md_i2c_set_fcon_txfrst(I2Cx, MD_I2C_TXFIFO_RESET); + md_i2c_set_con2_rd_wrn(I2Cx, MD_I2C_MASTER_WRITE); + md_i2c_set_con2_reload(I2Cx, MD_I2C_NORELOAD_MODE); + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_set_con2_autoend(I2Cx, MD_I2C_AUTOEND_MODE); + + if (Nbyte <= 8) + { + for (index = 0; index < Nbyte; index++) + md_i2c_send(I2Cx, *txbuf++); + + Nbyte = 0; + } + else + { + for (index = 0; index < 8; index++) + md_i2c_send(I2Cx, *txbuf++); + + Nbyte -= 8; + } + + /* Start the I2C communication */ + md_i2c_set_con2_start(I2Cx, MD_I2C_START_GENERATION); + + while (Nbyte > 0) + { + while (md_i2c_is_active_stat_txf(I2Cx)); + + md_i2c_send(I2Cx, *txbuf++); + Nbyte--; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be received + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_master_rece(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf) +{ + /* Config Device(slave) address */ + if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_10BIT); + else + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_7BIT); + + md_i2c_set_con2_sadd(I2Cx, DevAddr); + md_i2c_set_con2_nbytes(I2Cx, Nbyte); + md_i2c_set_fcon_rxfrst(I2Cx, MD_I2C_RXFIFO_RESET); + md_i2c_set_con2_rd_wrn(I2Cx, MD_I2C_MASTER_READ); + md_i2c_set_con2_reload(I2Cx, MD_I2C_NORELOAD_MODE); + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_set_con2_autoend(I2Cx, MD_I2C_AUTOEND_MODE); + /* Start the I2C communication */ + md_i2c_set_con2_start(I2Cx, MD_I2C_START_GENERATION); + + while (Nbyte > 0) + { + /* Wait Rx FIFO non-empty */ + while (md_i2c_is_active_stat_rxe(I2Cx)); + + *rxbuf++ = md_i2c_recv(I2Cx); + Nbyte--; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted, not for NBYTES + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *txbuf) +{ + md_i2c_set_fcon_txfrst(I2Cx, MD_I2C_TXFIFO_RESET); + + while (!(md_i2c_is_active_stat_busy(I2Cx))); + + while (Num > 0) + { + while (md_i2c_is_active_stat_txf(I2Cx)); + + md_i2c_send(I2Cx, *txbuf++); + Num--; + } +} + +/** + * @brief Receives in slave mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted, not for NBYTES + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_slave_rece(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *rxbuf) +{ + md_i2c_set_fcon_rxfrst(I2Cx, MD_I2C_RXFIFO_RESET); + + while (!(md_i2c_is_active_stat_busy(I2Cx))); + + while (Num > 0) + { + while (md_i2c_is_active_stat_rxe(I2Cx)); + + *rxbuf++ = md_i2c_recv(I2Cx); + Num--; + } +} + +/** + * @} Micro_Driver + */ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c new file mode 100644 index 0000000000000000000000000000000000000000..99ac22cf91bb4fc692980a72cff3bd70378bcea5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c @@ -0,0 +1,378 @@ +/** + ****************************************************************************** + * @file md_rcu.c + * @brief ES32F0271 RCU Source File. + * + * @version V1.00.01 + * @data 6/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_fc.h" +#include "system_es32f027x.h" + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup RCU RCU + * @brief RCU micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup MD_RCU_Private_Macros RCU Private Macros + * @{ + */ + + +/** + * @} MD_RCU_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ + +/** @addtogroup MD_RCU_PF_Init RCU Public Init Functions + * @{ + */ + +/** + * @brief + * @param + * @retval None + */ +void md_rcu_init(void) +{ + uint8_t pllmux; + + md_fc_set_con_wait(3); + + md_rcu_set_cfg_mpre(RCU, 0UL); + md_rcu_set_cfg_msw(RCU, MD_RCU_MCO_DISABLE); + md_rcu_set_cfg_pllmul(RCU, 12 - 1); + md_rcu_set_cfg_pllsrc(RCU, MD_RCU_PLL_SRC_HRC); + md_rcu_set_cfg_hoscdiv(RCU, 2 - 1); + md_rcu_set_cfg_ppre(RCU, MD_RCU_PPRE_HCLK_DIV_1); + md_rcu_set_cfg_hpre(RCU, MD_RCU_HPRE_SYSCLK_DIV_1); + md_rcu_set_cfg_sw(RCU, MD_RCU_SYSCLK_PLL0); + + md_rcu_disable_con_csson(RCU); + md_rcu_disable_con_pll1on(RCU); + md_rcu_enable_con_pll0on(RCU); + md_rcu_disable_con_loscon(RCU); + md_rcu_disable_con_lrcon(RCU); + md_rcu_disable_con_hoscon(RCU); + md_rcu_enable_con_hrcon(RCU); + + md_rcu_set_cfg_ckcfg(RCU); + + /* while(md_rcu_get_con_hoscrdy(RCU)==0) {} */ + + /* while(md_rcu_get_con_pll0rdy(RCU)==0) {} */ + + + if (RCU->CON & RCU_CON_HRCON_MSK) /* if HRC enbale */ + while (md_rcu_get_con_hrcrdy(RCU) == 0); /* Wait for HRCRDY = 1 (HRC is ready)*/ + + + if (RCU->CON & RCU_CON_HOSCON_MSK) /* if HOSC enbale */ + while (md_rcu_get_con_hoscrdy(RCU) == 0); /* Wait for HOSCRDY = 1 (HOSC is ready)*/ + + + if (RCU->CON & RCU_CON_LRCON_MSK) /* if LRC enbale */ + while (md_rcu_get_con_lrcrdy(RCU) == 0); /* Wait for LRCRDY = 1 (LRC is ready)*/ + + + if (RCU->CON & RCU_CON_LOSCON_MSK) /* if LOSC enbale */ + while (md_rcu_get_con_loscrdy(RCU) == 0); /* Wait for LOSCRDY = 1 (LOSC is ready)*/ + + if (RCU->CON & RCU_CON_PLL0ON_MSK) /* if PLL enbale */ + while (md_rcu_get_con_pll0rdy(RCU) == 0); /* Wait for PLLRDY = 1 (PLL is ready)*/ + + + + /* PLL Reference Clock Source*/ + if (md_rcu_get_cfg_pllsrc(RCU)) + PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(RCU) + 1)); + else + PLL0Frequency = (uint32_t)(__HRC); + + /* System Frequency */ + switch (md_rcu_get_cfg_sw(RCU)) /* System clock switch(SYSCLK) */ + { + case 0: /*================= HRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HRC); + break; + + case 1: /*================= HOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HOSC); + break; + + case 2: /*================= LRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LRC); + break; + + case 3: /*================= LOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LOSC); + break; + + case 4: /*================= PLL selected as system clock*/ + pllmux = md_rcu_get_cfg_pllmul(RCU) + 1; + + if (pllmux >= 18) pllmux = 18; + + SystemCoreClock = (uint32_t)(PLL0Frequency * pllmux); + break; + + default: + SystemCoreClock = (uint32_t)(__HRC); + break; + } + + /* Core Frequency */ + if (md_rcu_get_cfg_hpre(RCU)) + SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(RCU) & 0x07) + 1); + else + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + SystemFrequency_AHBClk = SystemFrequency_SysClk; + + /* APB Frequency */ + if (md_rcu_get_cfg_ppre(RCU)) + SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(RCU) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_SysClk; + + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_con_wait(3); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_con_wait(2); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_con_wait(1); + else + md_fc_set_con_wait(0); +} + +void md_rcu_init_set(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) +{ + uint8_t pllmux; + + md_fc_set_con_wait(3); + + md_rcu_set_cfg_mpre(rcu, RCU_InitStruct->Mpre); + md_rcu_set_cfg_msw(rcu, RCU_InitStruct->Msw); + md_rcu_set_cfg_pllmul(rcu, (RCU_InitStruct->PllMul) - 1); + md_rcu_set_cfg_pllsrc(rcu, RCU_InitStruct->PllSrc); + md_rcu_set_cfg_hoscdiv(rcu, (RCU_InitStruct->HoscDiv) - 1); + md_rcu_set_cfg_ppre(rcu, RCU_InitStruct->Ppre); + md_rcu_set_cfg_hpre(rcu, RCU_InitStruct->Hpre); + md_rcu_set_cfg_sw(rcu, RCU_InitStruct->Sw); + + if(RCU_InitStruct->SysClock & RCU_CON_CSSON_MSK) + md_rcu_enable_con_csson(rcu); + else + md_rcu_disable_con_csson(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_PLL1ON_MSK) + md_rcu_enable_con_pll1on(rcu); + else + md_rcu_disable_con_pll1on(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_PLL0ON_MSK) + md_rcu_enable_con_pll0on(rcu); + else + md_rcu_disable_con_pll0on(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_LOSCON_MSK) + md_rcu_enable_con_loscon(rcu); + else + md_rcu_disable_con_loscon(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_LRCON_MSK) + md_rcu_enable_con_lrcon(rcu); + else + md_rcu_disable_con_lrcon(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_HOSCON_MSK) + md_rcu_enable_con_hoscon(rcu); + else + md_rcu_disable_con_hoscon(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_HRCON_MSK) + md_rcu_enable_con_hrcon(rcu); + else + md_rcu_disable_con_hrcon(rcu); + + md_rcu_set_cfg_ckcfg(rcu); + + /* while(md_rcu_get_con_hoscrdy(RCU)==0) {} */ + + /* while(md_rcu_get_con_pll0rdy(RCU)==0) {} */ + + + if (RCU->CON & RCU_CON_HRCON_MSK) /* if HRC enbale */ + while (md_rcu_get_con_hrcrdy(rcu) == 0); /* Wait for HRCRDY = 1 (HRC is ready)*/ + + + if (RCU->CON & RCU_CON_HOSCON_MSK) /* if HOSC enbale */ + while (md_rcu_get_con_hoscrdy(rcu) == 0); /* Wait for HOSCRDY = 1 (HOSC is ready)*/ + + + if (RCU->CON & RCU_CON_LRCON_MSK) /* if LRC enbale */ + while (md_rcu_get_con_lrcrdy(rcu) == 0); /* Wait for LRCRDY = 1 (LRC is ready)*/ + + + if (RCU->CON & RCU_CON_LOSCON_MSK) /* if LOSC enbale */ + while (md_rcu_get_con_loscrdy(rcu) == 0); /* Wait for LOSCRDY = 1 (LOSC is ready)*/ + + if (RCU->CON & RCU_CON_PLL0ON_MSK) /* if PLL enbale */ + while (md_rcu_get_con_pll0rdy(rcu) == 0); /* Wait for PLLRDY = 1 (PLL is ready)*/ + + + + /* PLL Reference Clock Source*/ + if (md_rcu_get_cfg_pllsrc(rcu)) + PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(rcu) + 1)); + else + PLL0Frequency = (uint32_t)(__HRC); + + /* System Frequency */ + switch (md_rcu_get_cfg_sw(rcu)) /* System clock switch(SYSCLK) */ + { + case 0: /*================= HRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HRC); + break; + + case 1: /*================= HOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HOSC); + break; + + case 2: /*================= LRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LRC); + break; + + case 3: /*================= LOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LOSC); + break; + + case 4: /*================= PLL selected as system clock*/ + pllmux = md_rcu_get_cfg_pllmul(rcu) + 1; + + if (pllmux >= 18) pllmux = 18; + + SystemCoreClock = (uint32_t)(PLL0Frequency * pllmux); + break; + + default: + SystemCoreClock = (uint32_t)(__HRC); + break; + } + + /* Core Frequency */ + if (md_rcu_get_cfg_hpre(rcu)) + SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(rcu) & 0x07) + 1); + else + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + SystemFrequency_AHBClk = SystemFrequency_SysClk; + + /* APB Frequency */ + if (md_rcu_get_cfg_ppre(rcu)) + SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(rcu) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_SysClk; + + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_con_wait(3); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_con_wait(2); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_con_wait(1); + else + md_fc_set_con_wait(0); +} + + +/** + * @brief + * @param + * @retval None + */ +void md_rcu_pllreinit(uint8_t pllmul) +{ + md_rcu_set_cfg_pllmul(RCU, pllmul); + md_rcu_set_cfg_ckcfg(RCU); + + /* PLL Reference Clock Source */ + if (md_rcu_get_cfg_pllsrc(RCU)) + PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(RCU) + 1)); + else + PLL0Frequency = (uint32_t)(__HRC); + + SystemCoreClock = (uint32_t)(PLL0Frequency * (pllmul + 1)); + + /* Core Frequency */ + if (md_rcu_get_cfg_hpre(RCU)) + SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(RCU) & 0x07) + 1); + else + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + SystemFrequency_AHBClk = SystemFrequency_SysClk; + + /* APB Frequency */ + if (md_rcu_get_cfg_ppre(RCU)) + SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(RCU) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_SysClk; + + md_fc_set_con_wait(3); + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_con_wait(3); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_con_wait(2); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_con_wait(1); + else + md_fc_set_con_wait(0); +} + +/** + * @} MD_RCU_PF_Init + */ + +/** + * @} MD_RCU_Public_Functions + */ + +/** + * @} RCU + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..c29bb54be6bb7d3f5b2a3fe7f903ef647b04f2f2 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file md_spi.c + * @brief ES32F0271 I2C Source File. + * + * @version V1.00.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_spi.h" +#include "md_rcu.h" +#include +#include "stdint.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. + * @note The parameters in md_spi_init should be expected values. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_initStruct pointer to a @ref SPI_initStruct structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +void md_spi_struct_init(md_spi_inittypedef *SPI_initStruct) +{ + SPI_initStruct->Mode = MD_SPI_MODE_MASTER; + SPI_initStruct->ClockPhase = MD_SPI_PHASE_1EDGE; + SPI_initStruct->ClockPolarity = MD_SPI_POLARITY_LOW; + SPI_initStruct->BaudRate = MD_SPI_BAUDRATEPRESCALER_DIV256; + SPI_initStruct->BitOrder = MD_SPI_MSB_FIRST; + SPI_initStruct->TransferDirection = MD_SPI_FULL_DUPLEX; + SPI_initStruct->DataWidth = MD_SPI_FRAME_FORMAT_8BIT; + SPI_initStruct->CRCCalculation = MD_SPI_CRCCALCULATION_DISABLE; + SPI_initStruct->CRCPoly = 0x7; + SPI_initStruct->NSS = MD_SPI_NSS_HARD; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. + * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_initStruct pointer to a @ref SPI_initStruct structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + + md_spi_disable_con1_spien(SPIx); + + md_spi_set_con1_mstren(SPIx, SPI_InitStruct->Mode); + md_spi_set_con1_cpha(SPIx, SPI_InitStruct->ClockPhase); + md_spi_set_con1_cpol(SPIx, SPI_InitStruct->ClockPolarity); + md_spi_set_con1_baud(SPIx, SPI_InitStruct->BaudRate); + md_spi_set_con1_lsbfirst(SPIx, SPI_InitStruct->BitOrder); + md_spi_set_con1_bidimode(SPIx, SPI_InitStruct->TransferDirection); + md_spi_set_con1_ssout(SPIx, SPI_InitStruct->NSS); + md_spi_enable_con2_ssoe(SPIx); + + md_spi_enable_con1_spien(SPIx); + + status = SUCCESS; + + return status; +} + +/** + * @brief use to receive single one byte data. + * @note SPI Slave receive data + * @param SPIx SPI Instance + */ +uint8_t SPISSingleRd(SPI_TypeDef *SPIx) +{ + while (md_spi_is_active_flag_stat_rxe(SPIx)); + + return (md_spi_recv_data8(SPIx)); +} + + +/** + * @brief use to send single one byte data. + * @note SPI receive data + * @param SPIx SPI Instance + * @param data SPI send one byte data. + */ +void SPISingleWr(SPI_TypeDef *SPIx, uint8_t data) +{ + while (md_spi_is_active_flag_stat_txf(SPIx)); + + md_spi_send_data8(SPIx, data); +} + +/** + * @} Micro_Driver + */ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c new file mode 100644 index 0000000000000000000000000000000000000000..f1420c6eb3c39a20fb22fcf415eb9346c752b1a1 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file md_tick.c + * @brief ES32F0271 TICK Source File. + * + * @version V1.00.01 + * @date day/mon/year + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_tick.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (TICK) + +/** @addtogroup TICK TICK + * @brief TICK micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Private function prototypes ------------------------------------------------*/ + +#define HDIVON 0 + +/* Private variables ----------------------------------------------------------*/ +/** @defgroup MD_TICK_Private_Variables TICK Private Variables + * @{ + */ +static uint32_t TICKms; +static uint32_t TICK100us; +static uint32_t TICK10us; + +/** + * @} MD_TICK_Private_Variables + */ +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Functions TICK Public Functions + * @{ + */ + +/** + * @brief Tick Initialization + * @note This function set the maximun load and enable TICK counter + * @note This function also calculate ms, 100us ans 10us counter + * @param None + * @retval None + */ +void md_tick_init(void) +{ +#if HDIVON + HDIV->DIVIDEND = SystemFrequency_SysClk; + HDIV->DIVISOR = 1000; + TICKms = HDIV->QUOTIENT; + HDIV->DIVISOR = 10000; + TICK100us = HDIV->QUOTIENT; + HDIV->DIVISOR = 100000; + TICK10us = HDIV->QUOTIENT; +#else + TICKms = SystemFrequency_SysClk / 1000; + TICK100us = SystemFrequency_SysClk / 10000; + TICK10us = SystemFrequency_SysClk / 100000; +#endif + + md_tick_set_rvr_reload((1 << 24) - 1); /* Maximun ReLoad */ + md_tick_set_cvr_current(0); /* Reset CVR */ + md_tick_set_csr_clksource(1); /* MCU Clock */ + md_tick_enable_csr_enable(); /* Counter Enable */ +} + +/** + * @brief Retrive the TICK counter and converted to millisecond + * @param None + * @retval The ms value converted by TICK counter + */ +uint32_t md_tick_get_mscnt(void) +{ +#if HDIVON + HDIV->DIVIDEND = md_tick_get_cvr_current(); + HDIV->DIVISOR = TICKms; + return (HDIV->QUOTIENT); +#else + return (md_tick_get_cvr_current() / TICKms); +#endif +} + +/** + * @brief Retrive the TICK counter and converted to 100 microseconds + * @param None + * @retval The 100 microseconds value converted by TICK counter + */ +uint32_t md_tick_get_100uscnt(void) +{ +#if HDIVON + HDIV->DIVIDEND = md_tick_get_cvr_current(); + HDIV->DIVISOR = TICK100us; + return (HDIV->QUOTIENT); +#else + return (md_tick_get_cvr_current() / TICK100us); +#endif +} + +/** + * @brief Retrive the TICK counter and converted to 10 microseconds + * @param None + * @retval The 10 microseconds value converted by TICK counter + */ +uint32_t md_tick_get_10uscnt(void) +{ +#if HDIVON + HDIV->DIVIDEND = md_tick_get_cvr_current(); + HDIV->DIVISOR = TICK10us; + return (HDIV->QUOTIENT); +#else + return (md_tick_get_cvr_current() / TICK10us); +#endif +} + +/** + * @brief Delay based on milliseconds + * @param Unit The number of ms in one delay period + * @param msCnt The counter of delay period + * @etVal None + */ +void md_tick_waitms(uint8_t Unit, uint16_t msCnt) +{ + uint32_t mstime; + + mstime = (1 << 24) - (Unit * TICKms); + + while (msCnt--) + { + md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ + + while (md_tick_get_cvr_current() > mstime); + } +} + +/** + * @brief Delay based on 100 microseconds + * @param Unit The number of 100 microseconds in one delay period + * @param msCnt The counter of delay period + * @etVal None + */ +void md_tick_wait100us(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK100us); + + while (usCnt--) + { + md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ + + while (md_tick_get_cvr_current() > ustime); + } +} + +/** + * @brief Delay based on 10 microseconds + * @param Unit The number of 10 microseconds in one delay period + * @param msCnt The counter of delay period + * @etVal None + */ +void md_tick_wait10us(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK10us); + + while (usCnt--) + { + md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ + + while (md_tick_get_cvr_current() > ustime); + } +} + + +/** + * @} MD_TICK_Public_Functions + */ + +/** + * @} TICK + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..5ec9ccf3af433c3a431c17d2b853d7ba9186c821 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file md_uart.c + * @brief ES32F0271 UART Source File. + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft AE Team + * @note UART Public Functions + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_es32f027x.h" +#include "md_uart.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief UART micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup UART_PUB_FUNC UART Public Functions + * @brief UART Public Functions + * @{ + */ +/** + * @brief Set UART1 baudrate. + * @param UARTx UART Instance. + * @param Baudrate + * @retval None. + */ +void md_uart_set_baudrate(UART_TypeDef *UARTx, uint32_t baudrate) +{ + uint32_t brr; + brr = ((SystemFrequency_APBClk + (baudrate >> 1)) / baudrate); + md_uart_set_brr(UARTx, brr); +} + +/** + * @brief UART Initialization + * @param UART Init Structure + * @retval None + */ +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct) +{ + /* Check the UART_InitStruct */ + assert_param((UART_InitStruct != NULL)); + + md_uart_set_baudrate(UARTx, MD_UART_BAUDRATE_115200); + md_uart_disable_lcon_txen(UARTx); + md_uart_disable_lcon_rxen(UARTx); + md_uart_set_lcon_dls(UARTx, UART_InitStruct->DataWidth); + md_uart_set_lcon_stop(UARTx, UART_InitStruct->StopBits); + md_uart_set_lcon_ps(UARTx, UART_InitStruct->Parity); + md_uart_enable_lcon_pe(UARTx); + md_uart_set_fcon_tfrst(UARTx); + md_uart_set_fcon_rfrst(UARTx); + md_uart_enable_lcon_txen(UARTx); + md_uart_enable_lcon_rxen(UARTx); +} + +/** + * @brief UART1 send character + * @param Character + * @retval None + */ +void md_uart_send(UART_TypeDef *UARTx, uint8_t ch) +{ + while (md_uart_is_active_flag_stat_tffull(UARTx)); // Tx FIFO full + + md_uart_send_txbuf(UART1, ch); // Sent byte +} + +/** + * @brief UART1 receive character. + * @param UART_TypeDef *UARTx. + * @retval unsigned char. + */ +uint8_t md_uart_recv(UART_TypeDef *UARTx) +{ + while (md_uart_is_active_flag_stat_rfempty(UART1)); // Rx FIFO empty + + return (md_uart_get_rxbuf(UART1)); +} + +/** + * @brief Get UARTx baudrate. + * @param UART_TypeDef *UARTx. + * @retval Baudrate. + */ +uint32_t md_uart_get_baudrate(UART_TypeDef *UARTx) +{ + uint32_t brr, baudrate; + + brr = md_uart_get_brr(UARTx); + baudrate = SystemFrequency_APBClk / brr; + return baudrate; +} + + +/** + * @} UART_PUB_FUNC UART Public Functions + */ + +/** + * @} UART + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..b3ae9ce6d590ebdbb55254e57fcf4aa60fc623b5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c @@ -0,0 +1,3804 @@ +/** + ************************************************************************************** + * @file md_usb.c + * @brief USB Source File of MD Library. + * @data 03/12/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Incudes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "stdint.h" +#include +#include "usblib\drivers\usb_lowlayer_api.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (USB) + +/** @defgroup USB USB + * @brief USB micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +#define INTERRUPT_MASK_HOST 0x7e +#define INTERRUPT_MASK_DEV 0x6f + +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup USB_MD_Public_Functions USB Public Functions + * @{ + */ + +/** @addtogroup USB_MD_PF_SYS USB Public System Functions + * @{ + */ + +/** + * @brief Mask all interrupts except NMI and Hardfault. + * @param None. + * @retval None. + */ +void md_usb_system_int_disable(void) +{ + __set_PRIMASK(1); +} + +/** + * @brief Enable all interrupts. + * @param None. + * @retval None. + */ +void md_usb_system_int_enable(void) +{ + __set_PRIMASK(0); +} + +/** + * @brief Reconfig USB. + * + * This config USB clock to xx MHz as the default configuration. + * If user want to change the clock,just redefine the + * md_usb_re_config() function. + * @param Device Chose device is in device mode or host mode. + * @retval None. + */ +__weak void md_usb_re_config(bool Device) +{ + // + // Config FIFO size of endpoint 0. + // No configuration required for ES32F0271. + // + + // + // For ES32F0271,full-speed is supported in device mode, + // Both full-speeed and low-speed is supported in host mode. + // + if (Device == true) + { + // + // DP pin pull up, in full-speed mode. + // + USB->DPDMCTRL |= (0X01 << USB_DPDMCTL_DPPUD_POSS); + + // + // Enable CID hardware control. + // + USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; + } + else + { + // + // DM\DP pin pull down, in host mode. + // Connect USN PHY power. + // + USB->DPDMCTRL = (0X02 << USB_DPDMCTL_DPPUD_POSS) | + (0X02 << USB_DPDMCTL_DMPUD_POSS) | + (USB_DPDMCTL_PHYPWREN_MSK); + // + // Enable CID hardware control. + // + USB->SWCID &= ~USB_SWCID_HOST_MSK; + + // + // Enable CID hardware control. + // + USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; + } +} + +/** + * @brief Delay ticks ms. + * @param ticks The delay ticks. + * @retval None. + */ +__weak void md_usb_system_delayms(uint32_t ticks) +{ + +} + +/** + * @brief Disable systic. + * @param None. + * @retval None. + */ +void md_usb_systic_disable(void) +{ + SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk); +} + +/** + * @brief Reset colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_controller_reset(void) +{ + RCU->AHBRST |= RCU_AHBRST_USBEN_MSK; + RCU->AHBRST &= ~RCU_AHBRST_USBEN_MSK; +} + +/** + * @brief Enable colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_controller_enable(void) +{ + RCU->AHBEN |= RCU_AHBEN_USBEN_MSK; +} + +/** + * @brief Disable colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_controller_disable(void) +{ + RCU->AHBEN &= ~RCU_AHBEN_USBEN_MSK; +} + +/** + * @brief Enable phy colck of USB controller. + * + * This function enables clock of USB.To use USB,first, + * open its clock,then enable USB peripheral by clock + * clock manage peripheral. + * + * @param None. + * @retval None. + */ +void md_usb_clk_phy_enable(void) +{ + // + // Make sure the PLL1 has not been enabled. + // + if ((RCU->CON & RCU_CON_PLL1RDY_MSK) + && (RCU->CON & RCU_CON_PLL1ON_MSK)) + { + return; + } + + // + //Open PLL1 and wait it is ready. + // + RCU->CON |= RCU_CON_PLL1ON_MSK; + + while ((RCU->CON & RCU_CON_PLL1RDY_MSK) == 0); +} + +/** + * @brief Disable phy colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_clk_phy_disable(void) +{ + // + // Close PLL1. + // + RCU->CON &= ~RCU_CON_PLL1ON_MSK; +} + +/** + * @brief Get the USB interrupt number of NVIC. + * @param None. + * @retval None. + */ +uint32_t md_usb_nvic_number_get(void) +{ + return (uint32_t)USB_IRQn; +} + +/** + * @brief Config the USB interrupt of NVIC. + * @note The default priority is 1. + * @param None. + * @retval None. + */ +__weak void md_usb_nvic_config(uint32_t NvicNum) +{ + NVIC_SetPriority((IRQn_Type)NvicNum, 1); +} + +/** + * @brief Enable the USB interrupt of NVIC. + * @param None. + * @retval None. + */ +void md_usb_nvic_enable(void) +{ + NVIC_EnableIRQ((IRQn_Type)USB_IRQn); +} + +/** + * @brief Disable the USB interrupt of NVIC. + * @param None. + * @retval None. + */ +void md_usb_nvic_disable(void) +{ + NVIC_DisableIRQ((IRQn_Type)USB_IRQn); +} + +/** + * @} USB_MD_PF_SYS + */ + +/** @addtogroup USB_MD_PF_BASIC USB Public Basic Functions + * @{ + */ + +/** + * @brief Handles the USB bus reset condition. + * + * When this function is called with the \e bStart parameter set to \b true, + * this function causes the start of a reset condition on the USB bus. + * The caller must then delay at least 20ms before calling this function + * again with the \e bStart parameter set to \b false. + * + * @param bStart specifies whether to start or stop signaling reset on the USB + * bus. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_reset(bool bStart) +{ + // + // Send a reset signal to the bus. + // + if (bStart) + { + USB->POWER |= USB_POWER_RESET_MSK; + } + else + { + USB->POWER &= ~USB_POWER_RESET_MSK; + } +} + +/** + * @brief Handles the USB bus resume condition. + * + * When in device mode, this function brings the USB controller out of the + * suspend state. This call must first be made with the \e bStart parameter + * set to \b true to start resume signaling. The device application must + * then delay at least 10ms but not more than 15ms before calling this + * function with the \e bStart parameter set to \b false. + * + * When in host mode, this function signals devices to leave the suspend + * state. This call must first be made with the \e bStart parameter set to + * \b true to start resume signaling. The host application must then delay + * at least 20ms before calling this function with the \e bStart parameter set + * to \b false. This action causes the controller to complete the resume + * signaling on the USB bus. + * + * @param bStart specifies if the USB controller is entering or leaving the + * resume signaling state. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_resume(bool bStart) +{ + // + // Send a resume signal to the bus. + // + if (bStart) + { + USB->POWER |= USB_POWER_RESUME_MSK; + } + else + { + USB->POWER &= ~USB_POWER_RESUME_MSK; + } +} + +/** + * @brief Puts the USB bus in a suspended state. + * + * When used in host mode, this function puts the USB bus in the suspended + * state. + * + * @note This function must only be called in host mode. + * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, + * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. + */ +void md_usb_hos_suspend(void) +{ + // + // Send the suspend signaling to the USB bus. + // + USB->POWER |= USB_POWER_SUSPEND_MSK; +} + +/** + * @brief Issues a request for a status IN transaction on endpoint zero. + * + * This function is used to cause a request for a status IN transaction from + * a device on endpoint zero. This function can only be used with endpoint + * zero as that is the only control endpoint that supports this ability. This + * function is used to complete the last phase of a control transaction to a + * device and an interrupt is signaled when the status packet has been + * received. + * + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_request_status(void) +{ + // + // Set the request for a status IN transaction. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_REQPKT_MSK | USB_CSR0L_TXCSRL_STATUSPKT_MSK; +} + +/** + * @brief Schedules a request for an IN transaction on an endpoint in host mode. + * + * This function schedules a request for an IN transaction. When the USB + * device being communicated with responds with the data, the data can be + * retrieved by calling md_usb_hosdev_endpoint_data_get() or via a DMA + * transfer. + * + * @note This function must only be called in host mode and only for IN + * endpoints. + * @param ui32Endpoint is the endpoint to access. + * @retval None. + */ +void md_usb_hos_request_in(uint32_t ui32Endpoint) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + if (ui32Endpoint == USB_EP_0) + { + // + // Set the request for an IN transaction. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_REQPKT_MSK; + } + else + { + // + // Set the request for an IN transaction. + // + USB->RXCSR1 |= USB_RXCSRL_REQPKT_MSK; + } +} + +/** + * @brief Clears a scheduled IN transaction for an endpoint in host mode. + * + * This function clears a previously scheduled IN transaction if it is still + * pending. This function is used to safely disable any scheduled IN + * transactions if the endpoint specified by \e ui32Endpoint is reconfigured + * for communications with other devices. + * + * @note This function must only be called in host mode and only for IN + * endpoints. + * @param ui32Endpoint is the endpoint to access. + * @retval None. + */ +void md_usb_hos_request_in_clear(uint32_t ui32Endpoint) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Set the request for an IN transaction. + // For es32f0271,setup packet is only supported by endpoint0. + // + USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_REQPKT_MSK; +} + +/** + * @brief Returns the current speed of the USB device connected. + * + * This function returns the current speed of the USB bus in host mode. + * + * @note This function must only be called in host mode. + * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, + * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. + */ +uint32_t md_usb_hos_speed_get(void) +{ + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if (USB->DEVCTRL & USB_DEVCTRL_FSDEV_MSK) + { + return (USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if (USB->DEVCTRL & USB_DEVCTRL_LSDEV_MSK) + { + return (USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return (USB_UNDEF_SPEED); +} + +/** + * @brief Gets the current functional device address for an endpoint. + * + * This function returns the current functional address that an endpoint is + * using to communicate with a device. The \e ui32Flags parameter determines + * if the IN or OUT endpoint's device address is returned. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @note This function must only be called in host mode. + * @retval Returns the current function address being used by an endpoint. + */ +uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Because es32f0271 can not read device function address, + // the return value can always be 0. + // + + // + // See if the transmit or receive address is returned. + // + if (ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return (USB->FADDR); + } + else + { + // + // Return this endpoint's receive address. + // + return (USB->FADDR); + } +} + +/** + * @brief Sets the functional address for the device that is connected to an + * endpoint in host mode. + * + * This function configures the functional address for a device that is using + * this endpoint for communication. This \e ui32Addr parameter is the address + * of the target device that this endpoint is communicating with. The + * \e ui32Flags parameter indicates if the IN or OUT endpoint is set. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @param ui32Addr is the functional address for the controller to use for + * this endpoint. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + +// USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // See if the transmit or receive address is set. + // + if (ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + USB->FADDR = ui32Addr; + } + else + { + // + // Set the receive address. + // + USB->FADDR = ui32Addr; + } +} + +/** + * @brief Gets the current device hub address for this endpoint. + * + * This function returns the current hub address that an endpoint is using + * to communicate with a device. The \e ui32Flags parameter determines if the + * device address for the IN or OUT endpoint is returned. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @note This function must only be called in host mode. + * @retval None. + */ +uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // es32f0271 does not support + // + return 0; +} + +/** + * @brief Sets the hub address for the device that is connected to an endpoint. + * + * This function configures the hub address for a device that is using this + * endpoint for communication. The \e ui32Flags parameter determines if the + * device address for the IN or the OUT endpoint is configured by this call + * and sets the speed of the downstream device. Valid values are one of + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with + * \b USB_EP_SPEED_LOW. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @param ui32Addr is the hub address and port for the device using this + * endpoint. The hub address must be defined in bits 0 through 6 with the + * port number in bits 8 through 14. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags) +{ + // + // es32f0271 does not support + // +} + +/** + * @brief Get USB address. + * @param None. + * @retval USB address. + */ +uint8_t md_usb_dev_addr_get(void) +{ + return (USB->FADDR); +} + +/** + * @brief Set USB address. + * @param ui8Address USB address. + * @retval None. + */ +void md_usb_dev_addr_set(uint8_t ui8Address) +{ + USB->FADDR = ui8Address; +} + +/** + * @brief USB soft connect. + * @param None. + * @retval None. + */ +void md_usb_dev_connect(void) +{ + // + // Enable connection to the USB bus. + // + USB->DPDMCTRL |= USB_DPDMCTL_PHYPWREN_MSK; +} + +/** + * @brief USB soft disconnect. + * @param None. + * @retval None. + */ +void md_usb_dev_disconnect(void) +{ + // + // Disable connection to the USB bus. + // + USB->DPDMCTRL &= ~USB_DPDMCTL_PHYPWREN_MSK; +} + +/** + * @brief Returns the current speed of the USB device connected. + * + * This function returns the current speed of the USB bus in device mode. + * + * @note This function must only be called in device mode. + * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, + * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. + */ +uint32_t md_usb_dev_speed_get(void) +{ + if (USB->DPDMCTRL & USB_DPDMCTL_DPPUD_MSK) + return USB_FULL_SPEED; + else if (USB->DPDMCTRL & USB_DPDMCTL_DMPUD_MSK) + return USB_LOW_SPEED; + + return USB_UNDEF_SPEED; +} + +/** + * @brief Gets the current frame number. + * + * This function returns the last frame number received. + * + * @param None. + * @retval The last frame number received. + */ +uint32_t md_usb_hosdev_frame_get(void) +{ + uint8_t temp = USB->FRAME1 & 0xff; + return (temp | (uint32_t)((USB->FRAME2 & 0x07) << 8)); +} + +/** + * @brief Disables control interrupts on a specified USB controller. + * + * This function disables the control interrupts for the USB controller + * specified by the \e ui32Base parameter. The \e ui32Flags parameter + * specifies which control interrupts to disable. The flags passed in the + * \e ui32Flags parameters must be the definitions that start with + * \b USB_INTCTRL_* and not any other \b USB_INT flags. + * + * @param ui32IntFlags specifies which control interrupts to disable. + * @retval None. + */ +void md_usb_hosdev_int_disable(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + assert_param((ui32IntFlags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if (ui32IntFlags & USB_INTCTRL_STATUS) + { + USB->IDR &= ~(ui32IntFlags & USB_INTCTRL_STATUS); + } +} + +/** + * @brief Enables control interrupts on a specified USB controller. + * + * This function Enables the control interrupts for the USB controller + * specified by the \e ui32Base parameter. The \e ui32Flags parameter + * specifies which control interrupts to disable. The flags passed in the + * \e ui32Flags parameters must be the definitions that start with + * \b USB_INTCTRL_* and not any other \b USB_INT flags. + * + * @param ui32IntFlags specifies which control interrupts to Enable. + * @retval None. + */ +void md_usb_hosdev_int_enable(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + assert_param((ui32IntFlags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if (ui32IntFlags & USB_INTCTRL_STATUS) + { + USB->IER |= ui32IntFlags & USB_INTCTRL_STATUS; + } +} + +/** + * @brief Returns the control interrupt status on a specified USB controller. + * + * This function reads control interrupt status for a USB controller. This + * call returns the current status for control interrupts only, the endpoint + * interrupt status is retrieved by calling md_usb_hosdev_endpoint_int_status(). + * The bit values returned are compared against the \b USB_INTCTRL_* values. + * + * The following are the meanings of all \b USB_INCTRL_ flags and the modes + * for which they are valid. These values apply to any calls to + * md_usb_hosdev_int_status(), md_usb_hosdev_int_enable(), + * and md_usb_hosdev_int_disable(). + * Some of these flags are only valid in the following modes as indicated in + * the parentheses: Host, Device, and OTG. + * + * - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. + * - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). + * - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable + * (OTG Only). + * - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) + * - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) + * - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) + * - \b USB_INTCTRL_SOF - Start of Frame Detected. + * - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past + * the end of a frame (Host Only) + * - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) + * - \b USB_INTCTRL_RESUME - Resume signaling detected. + * - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device + * Only) + * - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed + * (OTG Only) + * - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) + * + * @param ui32IntFlags specifies which control interrupts to Enable. + * @note This call clears the source of all of the control status interrupts. + * @retval Returns the status of the control interrupts for a USB controller. + */ +uint32_t md_usb_hosdev_int_status(void) +{ + uint32_t ui32Status; + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = USB->RIF & 0x7F; + + // + // Clear all the general interrupt status. + // + USB->ICR = 0xff; + + // + // Return the combined interrupt status. + // + return (ui32Status); +} + +/** + * @brief Returns the current operating mode of the controller. + * + * This function returns the current operating mode on USB controllers with + * OTG or Dual mode functionality. + * + * For OTG controllers: + * + * The function returns one of the following values on OTG controllers: + * + * \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode + * on the A-side of the cable. + * + * \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode + * on the A-side of the cable. + * + * \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode + * on the B-side of the cable. + * + * \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode + * on the B-side of the cable. If an OTG session request is started with no + * cable in place, this mode is the default. + * + * \b USB_OTG_MODE_NONE indicates that the controller is not attempting to + * determine its role in the system. + * + * For Dual Mode controllers: + * + * The function returns one of the following values: + * + * \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. + * + * \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. + * + * \b USB_DUAL_MODE_NONE indicates that the controller is not active as + * either a host or device. + * + * @param None. + * @retval Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, + * \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, + * \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or + * \b USB_DUAL_MODE_NONE. + */ +uint32_t md_usb_hosdev_mode_get(void) +{ + // + // It will not be called for es32f0271,because OTG is not supported. + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return (USB->DEVCTRL & (USB_DEVCTRL_HOST_MSK | USB_DEVCTRL_SESSION_MSK)); +} + +/** + * @brief Starts or ends a session. + * + * This function is used in OTG mode to start a session request or end a + * session. If the \e bStart parameter is set to \b true, then this function + * starts a session and if it is \b false it ends a session. + * + * @param bStart specifies if this call starts or ends a session. + * @retval None. + */ +void md_usb_otg_session_request(bool bStart) +{ + // + // Start or end the session as directed. + // + if (bStart) + { + USB->DEVCTRL |= USB_DEVCTRL_SESSION_MSK; + } + else + { + USB->DEVCTRL &= ~USB_DEVCTRL_SESSION_MSK; + } +} + +/** + * @brief Change the mode of the USB controller to host. + * + * This function changes the mode of the USB controller to host mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +void md_usb_force_host_mode(void) +{ + unsigned int i; + // + // Force host mode. + // + USB->SWCID &= ~USB_SWCID_HOST_MSK; + USB->SWCID |= USB_SWCID_CIDCTRL_MSK; + USB->DEVCTRL = USB_DEVCTRL_HOSTREQ_MSK; + + i = 20; + + while ((!(USB->DEVCTRL & USB_DEVCTRL_HOST_MSK)) && (i != 0)) + { + i--; + } +} + +/** + * @brief Change the mode of the USB controller to device. + * + * This function changes the mode of the USB controller to device mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +void md_usb_force_device_mode(void) +{ + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of device mode. + // + USB->SWCID |= USB_SWCID_HOST_MSK; + USB->SWCID |= USB_SWCID_CIDCTRL_MSK; +} + +/** + * @brief Change the mode of the USB controller to OTG. + * + * This function changes the mode of the USB controller to OTG mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +void md_usb_force_otg_mode(void) +{ + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of OTG mode. + // + USB->SWCID |= USB_SWCID_HOST_MSK; + USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; +} + +/** + * @brief Change the operating mode of the USB controller. + * + * This function changes the operating modes of the USB controller. When + * operating in full OTG mode, the USB controller uses the VBUS and ID pins to + * detect mode and voltage changes. While these pins are primarily used in + * OTG mode, they can also affect the operation of host and device modes. In + * device mode, the USB controller can be configured to monitor or ignore + * VBUS. Monitoring VBUS allows the controller to determine if it has been + * disconnected from the host. In host mode, the USB controller uses the + * VBUS pin to detect loss of VBUS caused by excessive power draw due to a + * drop in the VBUS voltage. This call takes the place of + * md_usb_force_host_mode(),md_usb_force_device_mode(), + * and md_usb_force_otg_mode(). + * The \e ui32Mode value should be one of the following values: + * + * - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are + * used by the controller. + * - \b USB_MODE_HOST enables operating only as a host with no monitoring of + * VBUS or ID pins. + * - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of + * VBUS pin. This configuration enables detection of VBUS droop while still + * forcing host mode. + * - \b USB_MODE_DEVICE enables operating only as a device with no monitoring + * of VBUS or ID pins. + * - \b USB_MODE_DEVICE_VBUS enables operating only as a device with + * monitoring of VBUS pin. This configuration enables disconnect detection + * while still forcing device mode. + * + * @note Some of the options above are not available on some ES32 devices. + * Please check the data sheet to determine if the USB controller supports a + * particular mode. + * @param ui32Mode specifies the operating mode of the USB OTG pins. + * @retval None. + */ +void md_usb_mode_config(uint32_t ui32Mode) +{ + // + // It is not supported by es32f0271. + // +} + +/** + * @} USB_MD_PF_BASIC + */ + +/** @addtogroup USB_MD_PF_ENDPOINT USB Public Endpoint Functions + * @{ + */ + +/** + * @brief Sets the base configuration for a host endpoint. + * + * This function sets the basic configuration for the transmit or receive + * portion of an endpoint in host mode. The \e ui32Flags parameter determines + * some of the configuration while the other parameters provide the rest. The + * \e ui32Flags parameter determines whether this is an IN endpoint + * (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint + * (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed + * endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint + * (\b USB_EP_SPEED_LOW). + * + * The \b USB_EP_MODE_ flags control the type of the endpoint. + * - \b USB_EP_MODE_CTRL is a control endpoint. + * - \b USB_EP_MODE_ISOC is an isochronous endpoint. + * - \b USB_EP_MODE_BULK is a bulk endpoint. + * - \b USB_EP_MODE_INT is an interrupt endpoint. + * + * The \e ui32NAKPollInterval parameter has different meanings based on the + * \b USB_EP_MODE value and whether or not this call is being made for + * endpoint zero or another endpoint. For endpoint zero or any Bulk + * endpoints, this value always indicates the number of frames to allow a + * device to NAK before considering it a timeout. If this endpoint is an + * isochronous or interrupt endpoint, this value is the polling interval for + * this endpoint. + * + * For interrupt endpoints, the polling interval is the number of frames + * between interrupt IN requests to an endpoint and has a range of 1 to 255. + * For isochronous endpoints this value represents a polling interval of + * 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the + * \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) + * frames before issuing a time out. + * + * There are two special time out values that can be specified when setting + * the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is + * the maximum value that can be passed in this variable. The other is + * \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the + * number of NAKs. + * + * The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the + * endpoint data FIFOs. The choice of the DMA mode depends on how the DMA + * controller is configured and how it is being used. See the ``Using USB + * with the DMA Controller'' or the ''Using the integrated USB DMA + * Controller'' section for more information on DMA configuration depending + * on the type of DMA that is supported by the USB controller. + * + * When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit + * is specified to cause the transmission of data on the USB bus to start + * as soon as the number of bytes specified by \e ui32MaxPayload has been + * written into the OUT FIFO for this endpoint. + * + * When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST + * bit can be specified to trigger the request for more data once the FIFO has + * been drained enough to fit \e ui32MaxPayload bytes. The + * \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag + * automatically once the data has been read from the FIFO. If this option is + * not used, this flag must be manually cleared via a call to + * md_usb_dev_endpoint_status_clear() or md_usb_hos_endpoint_status_clear(). + * + * For interrupt endpoints in low or full speed mode, the polling interval + * (\e ui32NAKPollInterval) is the number of frames between interrupt IN + * requests to an endpoint and has a range of 1 to 255. For interrupt + * endpoints in high speed mode the polling interval is + * 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests + * to an endpoint and has a range of 1 to 16. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are the status bits that are cleared. + * @param ui32MaxPacketSize is the maximum payload for this endpoint. + * @param ui32NAKPollInterval is the either the NAK timeout limit or the + * polling interval, depending on the type of endpoint. + * @param ui32TargetEndpoint is the endpoint that the host endpoint is + * targeting. + * @param ui32Flags are used to configure other endpoint settings. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)ui32NAKPollInterval; + + // + // Set the transfer type information. + // + + // + // Set the speed of this endpoint. + // + if (ui32Flags & USB_EP_SPEED_HIGH) + { + // + // es32f0271 does not support high sepeed + // + } + else if (ui32Flags & USB_EP_SPEED_FULL) + { + } + else + { + } + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if (ui32Flags & USB_EP_SPEED_HIGH) + { + // + // es32f0271 does not support high sepeed + // + } + else if (ui32Flags & USB_EP_SPEED_FULL) + { + + } + else + { + + } + + // + // Set the protocol for the device using this endpoint. + // + switch (ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= 0x20; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= 0x10; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= 0x30; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= 0x00; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if (ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + USB->TXTYPE = ui32Register; + + // + // Set the NAK timeout or polling interval. + // + USB->NAKLIMIT0_TXINTERVAL = ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + USB->TXMAXP = ui32MaxPacketSize; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if (ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_CSR0H_TXCSRH_AUTOSET_MSK; + } + +// // +// // Configure the DMA Mode. +// // +// if(ui32Flags & USB_EP_DMA_MODE_1) +// { +// ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; +// } +// else if(ui32Flags & USB_EP_DMA_MODE_0) +// { +// ui32Register |= USB_TXCSRH1_DMAEN; +// } + + // + // Write out the transmit control value. + // + USB->CSR0H_TXCSRH = (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + USB->RXTYPE = ui32Register; + + // + // Set the NAK timeout or polling interval. + // + USB->RXINTERVAL = ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + USB->RXMAXP = ui32MaxPacketSize; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if (ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH_AUTOCLR_MSK; + } + + // + // Allow auto generation of DMA requests. + // + if (ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH_AUTOREQ_MSK; + } + +// // +// // Configure the DMA Mode. +// // +// if(ui32Flags & USB_EP_DMA_MODE_1) +// { +// ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; +// } +// else if(ui32Flags & USB_EP_DMA_MODE_0) +// { +// ui32Register |= USB_RXCSRH1_DMAEN; +// } + + // + // Write out the receive control value. + // + USB->RXCSR2 = (uint8_t)ui32Register; + + +// USB->RXFIFO1=0x18; //Start Address=0x18 +// USB->RXFIFO2=(3<<5); //Size=64, No Double-Packet Buffering +// USB->RXCSR1|=USB_RXCSRL_FLUSH_MSK; //Flush FIFO + } + } +} + +/** + * @brief Acknowledge that data was read from the specified endpoint's FIFO in host mode. + * + * This function acknowledges that the data was read from the endpoint's FIFO. + * This call is used if processing is required between reading the data and + * acknowledging that the data has been read. + * @param ui32Endpoint is the endpoint to access. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Clear RxPktRdy. + // + if (ui32Endpoint == USB_EP_0) + { + USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_RXRDY_MSK; + } + else + { + USB->RXCSR1 &= ~(USB_RXCSRL_RXRDY_MSK); + } +} + +/** + * @brief Sets the value data toggle on an endpoint in host mode. + * + * This function is used to force the state of the data toggle in host mode. + * If the value passed in the \e bDataToggle parameter is \b false, then the + * data toggle is set to the DATA0 state, and if it is \b true it is set to + * the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or + * \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The + * \e ui32Flags parameter is ignored for endpoint zero. + * @param ui32Endpoint is the endpoint to access. + * @param bDataToggle specifies whether to set the state to DATA0 or DATA1. + * @param ui32Flags specifies whether to set the IN or OUT endpoint. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + // + // It is not supported by es32f0271. + // + UNUSED(ui32Endpoint); + UNUSED(bDataToggle); + UNUSED(ui32Flags); +} + +/** + * @brief Clears the status bits in this endpoint in host mode. + * + * This function clears the status of any bits that are passed in the + * \e ui32Flags parameter. The \e ui32Flags parameter can take the value + * returned from the md_usb_hosdev_endpoint_status() call. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are the status bits that are cleared. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Clear the specified flags for the endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + USB->CSR0L_TXCSRL &= ~(ui32Flags & 0xff); + } + else + { + USB->CSR0L_TXCSRL &= ~(ui32Flags & 0xff); + USB->RXCSR1 &= ~((ui32Flags >> 16) & 0xff); + } +} + +/** + * @brief Changes the speed of the connection for a host endpoint. + * + * This function sets the USB speed for an IN or OUT endpoint in host mode. + * The \e ui32Flags parameter specifies the speed using one of the following + * values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH. + * The \e ui32Flags parameter also specifies which direction is set by + * adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT. + * All other flags are ignored. This function is typically only used for + * endpoint 0, but could be used with other endpoints as well. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are used to configure other endpoint settings. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // For es32f0271,we can not config endpoint speed. + // + UNUSED(ui32Endpoint); + UNUSED(ui32Flags); +} + +/** + * @brief Enables or disables ping tokens for an endpoint using high-speed control + * transfers in host mode. + * + * This function configures the USB controller to either send or not send ping + * tokens during the data and status phase of high speed control transfers. + * The only supported value for \e ui32Endpoint is \b USB_EP_0 because all + * control transfers are handled using this endpoint. If the \e bEnable is + * \b true then ping tokens are enabled, if \b false then ping tokens are + * disabled. This must be used if the controller must support + * communications with devices that do not support ping tokens in high speed + * mode. + * @param ui32Endpoint specifies the endpoint to enable/disable ping tokens. + * @param bEnable specifies whether enable or disable ping tokens. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, + bool bEnable) +{ + // + // It is not supported by es32f0271. + // + UNUSED(ui32Endpoint); + UNUSED(bEnable); +} + +/** + * @brief USB endpoint configuration. + * + * This function sets the basic configuration for an endpoint in device mode. + * Endpoint zero does not have a dynamic configuration, so this function + * must not be called for endpoint zero. The \e ui32Flags parameter + * determines some of the configuration while the other parameters provide the + * rest. + * + * When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be + * specified to cause the automatic transmission of data on the USB bus as + * soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for + * this endpoint. This option is commonly used with DMA as no interaction + * is required to start the transmission of data. + * + * The \b USB_EP_MODE_ flags define what the type is for the specified endpoint. + * USB_EP_MODE_CTRL is a control endpoint. + * USB_EP_MODE_ISOC is an isochronous endpoint. + * USB_EP_MODE_BULK is a bulk endpoint. + * USB_EP_MODE_INT is an interrupt endpoint. + * + * When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is + * specified to trigger the request for more data once the FIFO has been + * drained enough to receive \e ui32MaxPacketSize more bytes of data. Also + * for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the + * data packet ready flag automatically once the data has been read from the + * FIFO. If this option is not used, this flag must be manually cleared via a + * call to md_usb_dev_endpoint_status_clear(). Both of these settings can be + * used to remove the need for extra calls when using the controller with DMA. + * + * @param ui32Endpoint The USB endpoint. + * @param ui32MaxPacketSize is the maximum packet size for this endpoint. + * @param ui32Flags are used to configure other endpoint settings. + * @retval None. + */ +void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if (ui32Flags & USB_EP_DEV_IN) /*IN*/ + { + // + // Set the max packet size. + // + USB->TXMAXP = ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if (ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_CSR0H_TXCSRH_AUTOSET_MSK; + } + + // + // Configure the DMA mode. + // + /* es32f0271 does not support DMA */ + + // + // Enable isochronous mode if requested. + // + if ((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_CSR0H_TXCSRH_ISO_MSK; + } + + // + // Write the transmit control value. + // + USB->CSR0H_TXCSRH = (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + USB->CSR0L_TXCSRL = USB_CSR0L_TXCSRL_CLRDATAT_MSK; + } + else /*OUT*/ + { + // + // Set the MaxPacketSize. + // + USB->RXMAXP = ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if (ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH_AUTOCLR_MSK; + } + +// // +// // Configure the DMA mode. +// // + +// // +// // If requested, disable NYET responses for high-speed bulk and +// // interrupt endpoints. +// // + /*es32f0271 does not support*/ + + // + // Enable isochronous mode if requested. + // + if ((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH_ISO_MSK; + } + + // + // Write the receive control value. + // + USB->RXCSR2 = ui32Register; + + // + // Reset the Data toggle to zero. + // + USB->RXCSR1 = USB_RXCSRL_CLRDT_MSK; + } +} + +/** + * @brief Gets the current configuration for an endpoint. + * + * This function returns the basic configuration for an endpoint in device + * mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are + * equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed + * to md_usb_dev_endpoint_config_get() for this endpoint. + * + * @note This function must only be called in device mode. + * @param ui32Endpoint is the endpoint to access. + * @param pui32MaxPacketSize is a pointer which is written with the maximum + * packet size for this endpoint. + * @param pui32Flags is a pointer which is written with the current endpoint + * settings. On entry to the function, this pointer must contain either + * \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT + * endpoint is to be queried. + * @retval None. + */ +void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if (*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)USB->TXMAXP; + + // + // Get the current transmit control register value.` + // + ui32Register = (uint32_t)(USB->CSR0H_TXCSRH); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if (ui32Register & USB_CSR0H_TXCSRH_AUTOSET_MSK) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + + // + // Are we in isochronous mode? + // + if (ui32Register & USB_CSR0H_TXCSRH_ISO_MSK) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)USB->RXMAXP; + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)(USB->RXCSR2); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if (ui32Register & USB_RXCSRH_AUTOCLR_MSK) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + + // + // Are we in isochronous mode? + // + if (ui32Register & USB_RXCSRH_ISO_MSK) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } +} + +/** + * @brief Acknowledge that data was read from the specified endpoint's FIFO in device + * mode. + * + * This function acknowledges that the data was read from the endpoint's FIFO. + * The \e bIsLastPacket parameter is set to a \b true value if this is the + * last in a series of data packets on endpoint zero. The \e bIsLastPacket + * parameter is not used for endpoints other than endpoint zero. This call + * can be used if processing is required between reading the data and + * acknowledging that the data has been read. + * @param ui32Endpoint is the endpoint to access. + * @param bIsLastPacket indicates if this packet is the last one. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine which endpoint is being acked. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + USB->CSR0L_TXCSRL = USB_CSR0L_TXCSRL_RXRDYC_MSK | (bIsLastPacket ? USB_CSR0L_TXCSRL_DATAEND_MSK : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + USB->RXCSR1 &= ~USB_RXCSRL_RXRDY_MSK; + } +} + +/** + * @brief Stalls the specified endpoint in device mode. + * + * This function causes the endpoint number passed in to go into a stall + * condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the + * stall is issued on the IN portion of this endpoint. If the \e ui32Flags + * parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion + * of this endpoint. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies whether to stall the IN or OUT endpoint. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine how to stall this endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_RXRDYC_MSK | USB_CSR0L_TXCSRL_STALL_MSK; + } + else if (ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_STALL_MSK; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + USB->RXCSR1 |= USB_RXCSRL_STALL_MSK; + } +} + +/** + * @brief Clears the stall condition on the specified endpoint in device mode. + * + * This function causes the endpoint number passed in to exit the stall + * condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the + * stall is cleared on the IN portion of this endpoint. If the \e ui32Flags + * parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT + * portion of this endpoint. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies whether to stall the IN or OUT endpoint. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine how to clear the stall on this endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_STALLED_MSK; + } + else if (ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + USB->CSR0L_TXCSRL &= ~(USB_CSR0L_TXCSRL_SENTSTALL_MSK | USB_CSR0L_TXCSRL_SENDSTALL_MSK); + + // + // Reset the data toggle. + // + /* @yuzr es32f0271 can not realize */ + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_CLRDATAT_MSK; + } + else + { + // + // Clear the stall on an OUT endpoint. + // +// HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= +// ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + USB->RXCSR1 &= ~(USB_RXCSRL_STALL_MSK | USB_RXCSRL_STALLED_MSK); + + // + // Reset the data toggle. + // + USB->RXCSR1 |= USB_RXCSRL_CLRDT_MSK; + } +} + +/** + * @brief Clears the status bits in this endpoint in device mode. + * + * This function clears the status of any bits that are passed in the + * \e ui32Flags parameter. The \e ui32Flags parameter can take the value + * returned from the USBEndpointStatus() call. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are the status bits that are cleared. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if (ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_RXRDYC_MSK; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if (ui32Flags & USB_DEV_EP0_SETUP_END) + { + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_SETENDC_MSK; + } + + // + // Clear the Sent Stall status flag. + // + if (ui32Flags & USB_DEV_EP0_SENT_STALL) + { + USB->CSR0L_TXCSRL &= ~(USB_CSR0L_TXCSRL_STALLED_MSK); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + USB->CSR0L_TXCSRL &= ~(ui32Flags & (USB_CSR0L_TXCSRL_STALL_MSK | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + USB->RXCSR1 &= ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> 16); + } +} + +/** + * @brief Determines the number of bytes of data available in a specified endpoint's + * FIFO. + * + * This function returns the number of bytes of data currently available in the + * FIFO for the specified receive (OUT) endpoint. It may be used prior to calling + * md_usb_hosdev_endpoint_data_get() to determine the size of buffer required to + * hold the newly-received packet. + * @param ui32Endpoint is the endpoint to access. + * @retval This call returns the number of bytes available in a specified endpoint + * FIFO. + */ +uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint) +{ + uint8_t temp; //use to clear warning in IAR system + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Is there a packet ready in the FIFO? + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_RXRDY_MSK) + { + // + // Return the byte count in the FIFO. + // + return (uint32_t)(USB->RXCOUNT1); + } + + return (0); + } + else + { + // + // Is there a packet ready in the FIFO? + // + if (USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) + { + // + // Return the byte count in the FIFO. + // + temp = USB->RXCOUNT1; + return (uint32_t)(temp | USB->RXCOUNT2 << 8); + } + + return (0); + } +} + +/** + * @brief Retrieves data from the specified endpoint's FIFO. + * + * This function returns the data from the FIFO for the specified endpoint. + * The \e pui32Size parameter indicates the size of the buffer passed in + * the \e pui32Data parameter. The data in the \e pui32Size parameter is + * changed to match the amount of data returned in the \e pui8Data parameter. + * If a zero-byte packet is received, this call does not return an error but + * instead just returns a zero in the \e pui32Size parameter. The only error + * case occurs when there is no data packet available. + * @param ui32Endpoint is the endpoint to access. + * @param pui8Data is a pointer to the data area used to return the data from + * the FIFO. + * @param pui32Size is initially the size of the buffer passed into this call + * via the \e pui8Data parameter. It is set to the amount of data returned in + * the buffer. + * @retval This call returns 0, or -1 if no packet was received. + */ +int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, + uint8_t *pui8Data, + uint32_t *pui32Size) +{ + uint32_t ui32ByteCount, ui32FIFO; + uint8_t temp; //use to clear warning in IAR system + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if (ui32Endpoint == USB_EP_0) + { + if ((USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_RXRDY_MSK) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return (-1); + } + } + else + { + if ((USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return (-1); + } + } + + // + // Get the byte count in the FIFO. + // + if (ui32Endpoint == USB_EP_0) + { + ui32ByteCount = (uint32_t)(USB->RXCOUNT1); + } + else + { + temp = USB->RXCOUNT1; + ui32ByteCount = (uint32_t)(temp | (USB->RXCOUNT2 << 8)); + } + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = (uint32_t)(&USB->EP0FIFO) + 4 * (uint32_t)USBEPToIndex(ui32Endpoint); + + // + // Read the data out of the FIFO. + // + for (; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = *((volatile uint8_t *)(ui32FIFO)); + } + + // + // Success. + // + return (0); +} + +/** + * @brief Puts data into the specified endpoint's FIFO. + * + * This function puts the data from the \e pui8Data parameter into the FIFO + * for this endpoint. If a packet is already pending for transmission, then + * this call does not put any of the data into the FIFO and returns -1. Care + * must be taken to not write more data than can fit into the FIFO + * allocated by the call to md_usb_dev_endpoint_config_set(). + * @param ui32Endpoint is the endpoint to access. + * @param pui8Data is a pointer to the data area used as the source for the + * data to put into the FIFO. + * @param ui32Size is the amount of data to put into the FIFO. + * @retval This call returns 0 on success, or -1 to indicate that the FIFO + * is in use and cannot be written. + */ +int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if (ui32Endpoint == USB_EP_0) + { + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXRDY_MSK) + return (-1); + } + else + { + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) + return (-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = (uint32_t)(&USB->EP0FIFO) + 4 * (uint32_t)USBEPToIndex(ui32Endpoint); + + // + // Write the data to the FIFO. + // + for (; ui32Size > 0; ui32Size--) + { + *((volatile uint8_t *)(ui32FIFO)) = *pui8Data++; + } + + // + // Success. + // + return (0); +} + +/** + * @brief Starts the transfer of data from an endpoint's FIFO. + * + * This function starts the transfer of data from the FIFO for a specified + * endpoint. This function is called if the \b USB_EP_AUTO_SET bit was + * not enabled for the endpoint. Setting the \e ui32TransType parameter + * allows the appropriate signaling on the USB bus for the type of transaction + * being requested. The \e ui32TransType parameter must be one of the + * following: + * + * - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. + * - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. + * - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a + * sequence of IN transactions. + * \b USB_TRANS_SETUP for setup transactions on endpoint zero. + * \b USB_TRANS_STATUS for status results on endpoint zero. + * @param ui32Endpoint is the endpoint to access. + * @param ui32TransType is set to indicate what type of data is being sent. + * @retval This call returns 0 on success, or -1 if a transmission is already + * in progress. + */ +int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXRDY_MSK) + { + return (-1); + } + + ui32TxPktRdy = ui32TransType & 0xff; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) + { + return (-1); + } + + ui32TxPktRdy = (ui32TransType >> 8) & 0xff; + } + + // + // Set TxPktRdy in order to send the data. + // + USB->CSR0L_TXCSRL = ui32TxPktRdy; + + // + // Success. + // + return (0); +} + +/** + * @brief Forces a flush of an endpoint's FIFO. + * + * This function forces the USB controller to flush out the data in the FIFO. + * The function can be called with either host or device controllers and + * requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, + * \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies if the IN or OUT endpoint is accessed. + * @retval None. + */ +void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_CLRDATAT_MSK; + } + else + { + USB->RXCSR1 |= USB_RXCSRL_CLRDT_MSK; + } +} + +/** + * @brief Sets the number of packets to request when transferring multiple bulk + * packets. + * + * This function sets the number of consecutive bulk packets to request + * when transferring multiple bulk packets with DMA. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Count is the number of packets to request. + * @retval None. + */ +void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + /* It's not supported by es32f0271 */ +} + +/** + * @brief Returns the current status of an endpoint. + * + * This function returns the status of a specified endpoint. If any of these + * status bits must be cleared, then the md_usb_dev_endpoint_status_clear() or the + * md_usb_hos_endpoint_status_clear() functions must be called. + * + * The following are the status flags for host mode: + * + * - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint. + * - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. + * - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. + * - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN + * endpoint in Isochronous mode. + * - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than + * the specified timeout period. + * - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN + * endpoint. + * - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. + * - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. + * - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than + * the specified timeout period. + * - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT + * request. + * - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. + * - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this + * OUT endpoint. + * - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. + * - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not + * completed. + * - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the + * specified timeout period. + * - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on + * endpoint zero. + * - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an + * IN transaction. + * - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN + * transaction. + * + * The following are the status flags for device mode: + * + * - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. + * - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT + * endpoint. + * - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. + * - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. + * - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT + * endpoint's FIFO. + * - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. + * - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. + * - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no + * data was ready. + * - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. + * - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not + * completed. + * - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End + * condition was sent. + * - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. + * - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not + * completed. + * - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint + * zero's OUT FIFO. + * + * @param The current status flags for the endpoint depending on mode. + * @retval None. + */ +uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = USB->CSR0L_TXCSRL; + + // + // Get the RX portion of the endpoint status. + // Return zero if ui32Endpoint is equal to USB_EP_0. + // + ui32Status |= (((ui32Endpoint == USB_EP_0) ? 0x00 : USB->RXCSR1) << 16); + + // + // Return the endpoint status. + // + return (ui32Status); +} + +/** + * @brief Disables endpoint interrupts on a specified USB controller. + * + * This function disables endpoint interrupts for the USB controller specified + * by the \e ui32Base parameter. The \e ui32Flags parameter specifies which + * endpoint interrupts to disable. The flags passed in the \e ui32Flags + * parameters must be the definitions that start with \b USB_INTEP_* and not + * any other \b USB_INT flags. + * @param ui32IntFlags specifies which endpoint interrupts to disable. + * @retval None. + */ +void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags) +{ + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + USB->TXIER &= + ~(ui32IntFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + USB->RXIER &= + ~((ui32IntFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> 16); +} + +/** + * @brief Enable endpoint interrupts on a specified USB controller. + * + * This function Enable endpoint interrupts for the USB controller specified + * by the \e ui32Base parameter. The \e ui32Flags parameter specifies which + * endpoint interrupts to disable. The flags passed in the \e ui32Flags + * parameters must be the definitions that start with \b USB_INTEP_* and not + * any other \b USB_INT flags. + * @param ui32IntFlags specifies which endpoint interrupts to Enable. + * @retval None. + */ +void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags) +{ + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + USB->TXIER |= + ui32IntFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + USB->RXIER |= + ((ui32IntFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> 16); +} + +/** + * @brief Returns the endpoint interrupt status on a specified USB controller. + * + * This function reads endpoint interrupt status for a USB controller. This + * call returns the current status for endpoint interrupts only, the control + * interrupt status is retrieved by calling md_usb_hosdev_int_status(). The bit + * values returned are compared against the \b USB_INTEP_* values. + * These values are grouped into classes for \b USB_INTEP_HOST_* and + * \b USB_INTEP_DEV_* values to handle both host and device modes with all + * endpoints. + * @param None. + * @note This call clears the source of all of the endpoint interrupts. + * @retval Returns the status of the endpoint interrupts for a USB controller. + */ +uint32_t md_usb_hosdev_endpoint_int_status(void) +{ + uint32_t ui32Status; + + // + // Get the transmit interrupt status. + // + ui32Status = USB->TXRIF; + ui32Status |= (USB->RXRIF << 16); + + // + // Clear the transmit interrupt status. + // + USB->TXICR = 0xff; + USB->RXICR = 0xff; + + // + // Return the combined interrupt status. + // + return (ui32Status); +} + +/** + * @brief Change the mode of the USB controller to OTG. + * + * This function changes the mode of the USB controller to OTG mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +uint32_t md_usb_endpoint_number_get(void) +{ + return 13; +} + +/** + * @} USB_MD_PF_ENDPOINT + */ + +/** @addtogroup USB_MD_PF_FIFO USB Public FIFO Functions + * @{ + */ + +/** + * @brief Returns the absolute FIFO address for a specified endpoint. + * + * This function returns the actual physical address of the FIFO. This + * address is needed when the USB is going to be used with the DMA + * controller and the source or destination address must be set to the + * physical FIFO address for a specified endpoint. This function can also be + * used to provide the physical address to manually read data from an + * endpoints FIFO. + * + * @param ui32Endpoint specifies which endpoint's FIFO address to return. + * @retval None. + */ +uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint) +{ + return (uint32_t)((uint32_t)(&USB->EP0FIFO) + ((uint32_t)USBEPToIndex(ui32Endpoint) << 2)); +} + +/** + * @brief Returns the FIFO configuration for an endpoint. + * + * This function returns the starting address and size of the FIFO for a + * specified endpoint. Endpoint zero does not have a dynamically configurable + * FIFO, so this function must not be called for endpoint zero. The + * \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must + * be read. If in host mode, the \e ui32Flags parameter must be + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the + * \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or + * \b USB_EP_DEV_IN. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32FIFOAddress is the starting address for the FIFO. + * @param ui32FIFOSize is the size of the FIFO specified by one of the + * USB_FIFO_SZ_ values. + * @param ui32Flags specifies what information to set in the FIFO + * configuration. + * @retval None. + */ +void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags) +{ + uint8_t temp; //use to clear warning in IAR system + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // See if the transmit or receive FIFO is being configured. + // + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + temp = USB->TXFIFO1 & 0xff; + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (temp | ((USB->TXFIFO2 & 0x0f) << 8)) << 3; + *pui32FIFOSize = (USB->TXFIFO2 & 0xe0) >> USB_TXFIFO2_MAXPKTSIZE_POSS; + } + else + { + temp = USB->RXFIFO1 & 0xff; + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (temp | ((USB->TXFIFO2 & 0x0f) << 8)) << 3; + + *pui32FIFOSize = (USB->RXFIFO2 & 0xe0) >> USB_RXFIFO2_MAXPKTSIZE_POSS; + } +} + +/** + * @brief Sets the FIFO configuration for an endpoint. + * + * This function configures the starting FIFO RAM address and size of the FIFO + * for a specified endpoint. Endpoint zero does not have a dynamically + * configurable FIFO, so this function must not be called for endpoint zero. + * The \e ui32FIFOSize parameter must be one of the values in the + * \b USB_FIFO_SZ_ values. + * + * The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly + * indicates the starting address in the USB controller's FIFO RAM. For + * example, a value of 64 indicates that the FIFO starts 64 bytes into + * the USB controller's FIFO memory. The \e ui32Flags value specifies whether + * the endpoint's OUT or IN FIFO must be configured. If in host mode, use + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use + * \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32FIFOAddress is the starting address for the FIFO. + * @param ui32FIFOSize is the size of the FIFO specified by one of the + * USB_FIFO_SZ_ values. + * @param ui32Flags specifies what information to set in the FIFO + * configuration. + * @retval None. + */ +void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, + uint32_t ui32FIFOSize, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // See if the transmit or receive FIFO is being configured. + // + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + USB->TXFIFO1 = (uint8_t)((ui32FIFOAddress & 0xffff) >> 3); + + USB->TXFIFO2 = (uint8_t)((((ui32FIFOAddress & 0xffff) >> 3 >> 8) & 0x0f) + | (ui32FIFOSize) << USB_TXFIFO2_MAXPKTSIZE_POSS); + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_FLUSHFIFO_MSK; + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + USB->RXFIFO1 = (uint8_t)((ui32FIFOAddress & 0xffff) >> 3); + + USB->RXFIFO2 = (uint8_t)((((ui32FIFOAddress & 0xffff) >> 3 >> 8) & 0x0f) + | (ui32FIFOSize) << USB_RXFIFO2_MAXPKTSIZE_POSS); + USB->RXCSR1 |= USB_RXCSRL_FLUSH_MSK; + } +} + +/** + * @brief Forces a flush of an endpoint's FIFO. + * + * This function forces the USB controller to flush out the data in the FIFO. + * The function can be called with either host or device controllers and + * requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, + * \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies if the IN or OUT endpoint is accessed. + * @retval None. + */ +void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if ((USB->CSR0L_TXCSRL + & (USB_CSR0L_TXCSRL_TXRDY_MSK | USB_CSR0L_TXCSRL_RXRDY_MSK)) != 0) + { + // + // Hit the Flush FIFO bit. + // + USB->CSR0H_TXCSRH |= USB_CSR0H_TXCSRH_FLUSH_MSK; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) + { + // + // Hit the Flush FIFO bit. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_FLUSHFIFO_MSK; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if (USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) + { + // + // Hit the Flush FIFO bit. + // + USB->RXCSR1 |= USB_RXCSRL_FLUSH_MSK; + } + } + } +} + +/** + * @} USB_MD_PF_FIFO + */ + + +/** @addtogroup USB_MD_PF_EXPWR USB Public External Power Functions + * @{ + */ + +// +// The following pwr function is not supported by es32f0271 +// +/** + * @brief Disables the external power pin. + * + * This function disables the USBnEPEN signal, which disables an external + * power supply in host mode operation. + * + * @note This function must only be called in host mode. + * @retval None. + */ +__weak void md_usb_hos_pwr_disable(void) +{ +} + +/** + * @brief Enable the external power pin. + * + * This function disables the USBnEPEN signal, which disables an external + * power supply in host mode operation. + * + * @note This function must only be called in host mode. + * @retval None. + */ +__weak void md_usb_hos_pwr_enable(void) +{ + // + // Although Vbus is not supported by es32f0271,we provide Vbus + // from outside. + // + +} + +/** + * @brief Sets the configuration for USB power fault. + * + * This function controls how the USB controller uses its external power + * control pins (USBnPFLT and USBnEPEN). The flags specify the power + * fault level sensitivity, the power fault action, and the power enable level + * and source. + * + * One of the following can be selected as the power fault level sensitivity: + * + * - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin + * being driven low. + * - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin + * being driven high. + * + * One of the following can be selected as the power fault action: + * + * - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault + * detected. + * - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a + * power fault. + * - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a + * power fault. + * - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a + * power fault. + * + * One of the following can be selected as the power enable level and source: + * + * - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller + * when USBHostPwrEnable() is called. + * - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB + * controller when USBHostPwrEnable() is + * called. + * - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller + * automatically if USBOTGSessionRequest() has + * enabled a session. + * - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB + * controller automatically if + * USBOTGSessionRequest() has enabled a + * session. + * + * When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be + * addded to ignore small, short drops in VBUS level caused by high power + * consumption. This feature is mainly used to avoid causing VBUS errors + * caused by devices with high in-rush current. + * + * @note This function must only be called on microcontrollers that support + * host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and + * \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that + * support OTG operation. + * @retval None. + */ +void md_usb_hos_pwr_config(uint32_t ui32Flags) +{ +} + +/** + * @brief Disable power fault detection. + * + * This function enables power fault detection in the USB controller. If the + * USBnPFLT pin is not in use, this function must not be used. + * + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_pwrfault_disable(void) +{ +} + +/** + * @brief Enable power fault detection. + * + * This function enables power fault detection in the USB controller. If the + * USBnPFLT pin is not in use, this function must not be used. + * + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_pwrfault_enable(void) +{ +} + +/** + * @} USB_MD_PF_EXPWR + */ + +/** @addtogroup USB_MD_PF_LPM USB Public LPM Functions + * @{ + */ + +// +// LPM is not supported by es32f0271 +// + +/** + * @brief Sends an LPM request to a device at a specified address and endpoint number. + * + * This function sends an LPM request to a connected device in host mode. + * The \e ui32Address parameter specifies the device address and has a range + * of values from 1 to 127. The \e ui32Endpoint parameter specifies the + * endpoint on the device to which to send the LPM request and must be one of + * the \b USB_EP_* values. The function returns before the LPM request is + * sent, requiring the caller to poll the md_usb_lpm_status() function or wait + * for an interrupt to signal completion of the LPM transaction. This + * function must only be called after the md_usb_hos_lpm_config() has configured + * the LPM transaction settings. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Address is the target device address for the LPM request. + * @param ui32Endpoint is the target endpoint for the LPM request. + * @retval None. + */ +void md_usb_hos_lpm_send(uint32_t ui32Address, + uint32_t uiEndpoint) +{ +} + +/** + * @brief Sets the global configuration for all LPM requests. + * + * This function sets the global configuration options for LPM transactions + * and must be called at least once before ever calling md_usb_hos_lpm_send(). The + * \e ui32ResumeTime specifies the length of time that the host drives resume + * signaling on the bus in microseconds. The valid values + * for \e ui32ResumeTime are from 50us to 1175us in 75us increments. The + * remaining configuration is specified by the \e ui32Config parameter and + * includes the following options: + * + * - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from + * the LPM state. + * - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included + * in the configuration. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Address is the target device address for the LPM request. + * @param ui32Endpoint is the target endpoint for the LPM request. + * @retval None. + */ +void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, + uint32_t ui32Config) +{ +} + +/** + * @brief Returns if remote wake is currently enabled. + * + * This function returns the current state of the remote wake setting for host + * or device mode operation. If the controller is acting as a host this + * returns the current setting that is sent to devices when LPM requests are + * sent to a device. If the controller is in device mode, this function + * returns the state of the last LPM request sent from the host and indicates + * if the host enabled remote wakeup. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The \b true if remote wake is enabled or \b false if it is not. + */ +bool md_usb_lpm_remotewake_is_enabled(void) +{ + return 0; +} + +/** + * @brief Initiates resume signaling to wake a device from LPM suspend mode. + * + * In host mode, this function initiates resume signaling to wake a device + * that has entered an LPM-triggered low power mode. This LPM-triggered low + * power mode is entered when the md_usb_hos_lpm_send() is called to put a specific + * device into a low power state. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_hos_lpm_resume(void) +{ +} + +/** + * @brief Initiates remote wake signaling to request the device to leave LPM + * suspend mode. + * + * This function initiates remote wake signaling to request that the host + * wake a device that has entered an LPM-triggered low power mode. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_dev_lpm_remotewake(void) +{ +} + +/** + * @brief Configures the USB device mode response to LPM requests. + * + * This function sets the global configuration options for LPM + * transactions in device mode and must be called before ever calling + * md_usb_dev_lpm_enable() to set the configuration for LPM transactions. The + * configuration options in device mode are specified in the \e ui32Config + * parameter and include one of the following: + * + * - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM + * transactions. + * - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM + * and extended transactions. + * - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to + * extended transactions, but not LPM transactions. + * + * The \e ui32Config option can also optionally include the + * \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all + * transactions other than an LPM transaction once the USB controller is in + * LPM suspend mode. If this value is not included in the \e ui32Config + * parameter, the USB controller does not respond in suspend mode. + * + * The USB controller does not enter LPM suspend mode until the application + * calls the md_usb_dev_lpm_enable() function. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Config is the combination of configuration options for LPM + * transactions in device mode. + * @retval None. + */ +void md_usb_dev_lpm_config(uint32_t ui32Config) +{ +} + +/** + * @brief Enables the USB controller to respond to LPM suspend requests. + * + * This function is used to automatically respond to an LPM sleep request from + * the USB host controller. If there is no data pending in any transmit + * FIFOs, then the USB controller acknowledges the packet and enters the + * LPM L1 state and generates the \b USB_INTLPM_ACK interrupt. If the USB + * controller has pending transmit data in at least one FIFO, then the USB + * controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or + * \b USB_INTLPM_NYET depending on if data is pending in receive or transmit + * FIFOs. A call to md_usb_dev_lpm_enable() is required after every + * LPM resume event to re-enable LPM mode. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_dev_lpm_enable(void) +{ +} + +/** + * @brief Disables the USB controller to respond to LPM suspend requests. + * + * This function disables the USB controller from responding to LPM + * transactions. When the device enters LPM L1 mode, the USB controller + * automatically disables responding to further LPM transactions. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_dev_lpm_disable(void) +{ +} + +/** + * @brief Returns the current link state setting. + * + * This function returns the current link state setting for the USB + * controller. When the controller is operating as a host, this link + * state is sent with an LPM request. When the controller is acting + * as a device, this link state was received by the last LPM transaction + * whether it was acknowledged or stalled because the requested + * LPM mode is not supported. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The current LPM link state. + */ +uint32_t md_usb_lpm_link_state_get(void) +{ + return 0; +} + +/** + * @brief Returns the current LPM endpoint value. + * + * This function returns the current LPM endpoint value. The meaning of the + * value depends on the mode of operation of the USB controller. When in + * device mode, the value returned is the endpoint that received the last + * LPM transaction. When in host mode this is the endpoint that was last + * sent an LPM transaction, or the endpoint that is configured to be sent when + * the LPM transaction is triggered. The value returned is in the + * \b USB_EP_[0-7] value and a direct endpoint index. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The last endpoint to receive an LPM request in device mode or the + * endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7] + * values. + */ +uint32_t md_usb_lpm_endpoint_get(void) +{ + return 0; +} + +/** + * @brief Returns the current LPM interrupt status. + * + * This function returns the current LPM interrupt status for the USB + * controller. + * + * The valid interrupt status bits when the USB controller is acting as a host + * are the following: + * + * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM + * transaction. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout + * occurred or there were bit errors in the response for three attempts. + * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. + * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM + * transaction. + * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. + * + * The valid interrupt status bits when the USB controller is acting as a + * device are the following: + * + * - \b USB_INTLPM_ERROR an LPM transaction was received that has an + * unsupported link state field. The transaction was stalled, but the + * requested link state can still be read using the md_usb_lpm_link_state_get() + * function. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM + * transaction with a NYET because data was still in the transmit FIFOs. + * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and + * is now in the LPM suspend mode. + * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction + * with a NYET because LPM transactions are not yet enabled by a call to + * md_usb_dev_lpm_enable(). + * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM + * transaction. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The \b true if remote wake is enabled or \b false if it is not. + */ +uint32_t md_usb_lpm_status(void) +{ + return 0; +} + +/** + * @brief Enables LPM interrupts. + * + * This function enables a set of LPM interrupts so that they can trigger a + * USB interrupt. The \e ui32Ints parameter specifies which of the + * \b USB_INTLPM_* to enable. + * + * The valid interrupt status bits when the USB controller is acting as a host + * are the following: + * + * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM + * transaction. + * - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power + * state. + * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout + * occurred or there were bit errors in the response for three attempts. + * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. + * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM + * transaction. + * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. + * + * The valid interrupt status bits when the USB controller is acting as a + * device are the following: + * + * - \b USB_INTLPM_ERROR an LPM transaction was received that has an + * unsupported link state field. The transaction was stalled, but the + * requested link state can still be read using the md_usb_lpm_link_state_get() + * function. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM + * transaction with a NYET because data was still in the transmit FIFOs. + * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and + * is now in the LPM suspend mode. + * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction + * with a NYET because LPM transactions are not yet enabled by a call to + * md_usb_dev_lpm_enable(). + * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM + * transaction. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Ints specifies which LPM interrupts to enable. + * @retval None. + */ +void md_usb_lpm_int_enable(uint32_t ui32Ints) +{ +} + +/** + * @brief Disables LPM interrupts. + * + * This function disables the LPM interrupts specified in the \e ui32Ints + * parameter, preventing them from triggering a USB interrupt. + * + * The valid interrupt status bits when the USB controller is acting as a host + * are the following: + * + * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM + * transaction. + * - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power + * state. + * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout + * occurred or there were bit errors in the response for three attempts. + * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. + * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM + * transaction. + * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. + * + * The valid interrupt status bits when the USB controller is acting as a + * device are the following: + * + * - \b USB_INTLPM_ERROR an LPM transaction was received that has an + * unsupported link state field. The transaction was stalled, but the + * requested link state can still be read using the md_usb_lpm_link_state_get() + * function. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM + * transaction with a NYET because data was still in the transmit FIFOs. + * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and + * is now in the LPM suspend mode. + * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction + * with a NYET because LPM transactions are not yet enabled by a call to + * md_usb_dev_lpm_enable(). + * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM + * transaction. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Ints specifies which LPM interrupts to disable. + * @retval None. + */ +void md_usb_lpm_int_disable(uint32_t ui32Ints) +{ +} + +/** + * @} USB_MD_PF_LPM + */ + +/** @addtogroup USB_MD_PF_ULPI USB Public ULPI Functions + * @{ + */ + +// +// ULPI is not supported by es32f0271 +// + +/** + * @brief Configures the USB controller's ULPI function. + * + * This function is used to configure the USB controller's ULPI function. + * The configuration options are set in the \e ui32Config parameter and are a + * logical OR of the following values: + * + * - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS + * signaling. + * - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external + * VBUS over-current condition. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param ui32Config contains the configuration options. + * @retval None. + */ +void md_usb_ulpi_config(uint32_t ui32Config) +{ +} + +/** + * @brief Enables the USB controller's ULPI function. + * + * This function enables the USB controller's ULPI function and must be + * called before attempting to access an external ULPI-connected USB PHY. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param None. + * @retval None. + */ +void md_usb_ulpi_enable(void) +{ +} + +/** + * @brief Disables the USB controller's ULPI function. + * + * This function Disables the USB controller's ULPI function and must be + * called before attempting to access an external ULPI-connected USB PHY. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param None. + * @retval None. + */ +void md_usb_ulpi_disable(void) +{ +} + +/** + * @brief Disables the USB controller's ULPI function. + * + * This function Disables the USB controller's ULPI function and must be + * called before attempting to access an external ULPI-connected USB PHY. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param None. + * @retval None. + */ +uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg) +{ + return 0; +} + +/** + * @brief Writes a value to a register on an external ULPI-connected USB PHY. + * + * This function writes the register address specified in the \e ui8Reg + * parameter with the value specified in the \e ui8Data parameter using the + * ULPI function. This function is blocking and only returns when the + * write access completes. The function does not return if there is not a + * ULPI-connected USB PHY present. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param ui8Reg specifies the register address to write. + * @param ui8Data specifies the data to write. + * @retval None. + */ +void md_usb_ulpi_reg_write(uint8_t ui8Reg, + uint8_t ui8Data) +{ +} + +/** + * @} USB_MD_PF_ULPI + */ + +/** @addtogroup USB_MD_PF_DMA USB Public DMA Functions + * @{ + */ + +// +// USB DMA is not supported by es32f0271 +// + +/** + * @brief Sets the DMA channel to use for a specified endpoint. + * + * This function is used to configure which DMA channel to use with a specified + * endpoint. Receive DMA channels can only be used with receive endpoints + * and transmit DMA channels can only be used with transmit endpoints. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint specifies which endpoint's FIFO address to return. + * @param ui32Channel specifies which DMA channel to use for which endpoint. + * @retval None. + */ +void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Enable DMA on a specified endpoint. + * + * This function enables DMA on a specified endpoint and configures the mode + * according to the values in the \e ui32Flags parameter. The \e ui32Flags + * parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this + * function is called the only DMA or error interrupts are generated by the + * USB controller. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies which direction and what mode to use when + * enabling DMA. + * @retval None. + */ +void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Disable DMA on a specified endpoint. + * + * This function disables DMA on a specified endpoint to allow non-DMA USB + * transactions to generate interrupts normally. The \e ui32Flags parameter + * must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies which direction to disable. + * @retval None. + */ +void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Configure the DMA settings for an endpoint. + * + * This function configures the DMA settings for a specified endpoint without + * changing other options that may already be configured. In order for the + * DMA transfer to be enabled, the md_usb_dma_endpoint_enable() function must be + * called before starting the DMA transfer. The configuration + * options are passed in the \e ui32Config parameter and can have the values + * described below. + * + * One of the following values to specify direction: + * - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with + * DMA transfers from memory to the USB controller. + * - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with + * DMA transfers from the USB controller to memory. + * + * One of the following values: + * - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for + * transfers that do not span multiple packets or when interrupts are + * required for each packet. + * - \b USB_EP_DMA_MODE_1 - This setting is typically used for + * transfers that span multiple packets and do not require interrupts + * between packets. + * + * Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: + * - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers + * to automatically be sent when a full packet is loaded into a FIFO. + * This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go + * out when the FIFO becomes full and the DMA has more data to send. + * + * Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: + * - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA + * transfers to automatically be acknowledged as they are received. This is + * needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to + * be received and acknowledged when the FIFO is emptied by the DMA + * transfer. + * + * Values only used with \b USB_EP_HOST_IN: + * - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA + * transfers to automatically request a new IN transaction when the + * previous transfer has emptied the FIFO. This is typically used in + * conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers + * can continue without interrupting the main processor. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Config specifies the configuration options for an endpoint. + * @retval None. + */ +void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, uint32_t ui32Config) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Host out or device in. + // + if ((ui32Config & USB_EP_HOST_OUT) && (ui32Config & USB_EP_AUTO_SET)) + { + USB->CSR0H_TXCSRH |= USB_CSR0H_TXCSRH_AUTOSET_MSK; + } + else + { + if (ui32Config & USB_EP_AUTO_REQUEST) + { + USB->RXCSR2 |= USB_RXCSRH_AUTOREQ_MSK; + } + + if (ui32Config & USB_EP_AUTO_CLEAR) + { + USB->RXCSR2 |= USB_RXCSRH_AUTOCLR_MSK; + } + } +} + +/** + * @brief Assigns and configures an endpoint to a specified integrated USB DMA + * channel. + * + * This function assigns an endpoint and configures the settings for a + * USB DMA channel. The \e ui32Endpoint parameter is one of the + * \b USB_EP_* values and the \e ui32Channel value is a zero-based index of + * the DMA channel to configure. The \e ui32Config parameter is a combination + * of the \b USB_DMA_CFG_* values using the following guidelines. + * + * Use one of the following to set the DMA burst mode: + * - \b USB_DMA_CFG_BURST_NONE disables bursting. + * - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words. + * - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words. + * - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words. + * + * Use one of the following to set the DMA mode: + * - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is + * being sent via DMA and triggers one completion interrupt per packet. + * - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being + * sent via DMA and triggers one completion interrupt per transfer. + * + * Use one of the following to set the direction of the transfer: + * - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a + * memory location. + * - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a + * memory location. + * + * The following two optional settings allow an application to immediately + * enable the DMA transfer and/or DMA interrupts when configuring the DMA + * channel: + * - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so + * that an added call to md_usb_dma_channel_int_enable() is not necessary. + * - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added + * call to md_usb_dma_channel_enable() is not necessary. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @param ui32Endpoint is the endpoint to assign to the USB DMA channel. + * @param ui32Config is used to specify the configuration of the USB DMA channel. + * @retval None. + */ +void md_usb_dma_channel_config(uint32_t ui32Channel, + uint32_t ui32Endpoint, uint32_t ui32Config) +{ + // + // It is not supported by es32f0271 + // +} + +/** + * @brief Sets the source or destination address for an integrated USB DMA transfer + * on a specified channel. + * + * This function sets the source or destination address for the USB DMA + * channel number specified in the \e ui32Channel parameter. The + * \e ui32Channel value is a zero-based index of the USB DMA channel. The + * \e pvAddress parameter is a source address if the transfer type for the DMA + * channel is transmit and a destination address if the transfer type is + * receive. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @param pvAddress specifies the source or destination address for the USB + * DMA transfer. + * @retval None. + */ +void md_usb_dma_channel_address_set(uint32_t ui32Channel, + void *pvAddress) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Returns the source or destination address for the specified integrated USB + * DMA channel. + * + * This function returns the DMA address for the channel number specified + * in the \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the DMA channel to query. This function must not be used on + * devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion() + * function. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @retval The current DMA address for a USB DMA channel. + */ +void *md_usb_dma_channel_address_get(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Sets the transfer count for an integrated USB DMA channel. + * + * This function sets the USB DMA transfer count in bytes for the channel + * number specified in the \e ui32Channel parameter. The \e ui32Channel + * value is a zero-based index of the DMA channel. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Count specifies the number of bytes to transfer. + * @param ui32Channel specifies which DMA channel to access. + * @retval None. + */ +void md_usb_dma_channel_count_set(uint32_t ui32Count, + uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Returns the transfer count for an integrated USB DMA channel. + * + * This function returns the USB DMA transfer count in bytes for the channel + * number specified in the \e ui32Channel parameter. The \e ui32Channel value + * is a zero-based index of the DMA channel to query. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @retval The current count for a USB DMA channel. + */ +uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Returns the available number of integrated USB DMA channels. + * + * This function returns the total number of DMA channels available when using + * the integrated USB DMA controller. This function returns 0 if the + * integrated controller is not present. + * + * @note The number of integrated USB DMA channels or zero if the + * integrated USB DMA controller is not present. + * @param None. + * @retval The number of integrated USB DMA channels or zero if the + * integrated USB DMA controller is not present. + */ +uint32_t md_usb_dma_channel_number(void) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Enable interrupts for a specified integrated USB DMA channel. + * + * This function enables the USB DMA channel interrupt based on the + * \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the USB DMA channel. Once enabled, the md_usb_dma_channel_int_status() + * function returns if a DMA channel has generated an interrupt. + * + * @note The number of integrated USB DMA channels or zero if the + * integrated USB DMA controller is not present. + * @param ui32Channel specifies which DMA channel interrupt to enable. + * @retval None. + */ +void md_usb_dma_channel_int_enable(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // +} + +/** + * @brief Return the current status of the integrated USB DMA interrupts. + * + * This function returns the current bit-mapped interrupt status for all USB + * DMA channel interrupt sources. Calling this function automatically clears + * all currently pending USB DMA interrupts. + * + * @param None. + * @retval None. + */ +uint32_t md_usb_dma_channel_int_status(void) +{ + return 0; +} + +/** + * @brief Enables USB DMA for a specified channel. + * + * This function enables the USB DMA channel passed in the \e ui32Channel + * parameter. The \e ui32Channel value is a zero-based index of the USB DMA + * channel. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller. + * @param ui32Channel specifies the USB DMA channel to enable. + * @retval None. + */ +void md_usb_dma_channel_enable(uint32_t ui32Channel) +{ + // + // DMA1 will be used by es32f0271 + // + SET_BIT(*(&DMA1->CSR0 + 4 * ui32Channel), DMA_CSR0_CHEN_MSK); +} + +/** + * @brief Disables USB DMA for a specified channel. + * + * This function Disables the USB DMA channel passed in the \e ui32Channel + * parameter. The \e ui32Channel value is a zero-based index of the USB DMA + * channel. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller. + * @param ui32Channel specifies the USB DMA channel to Disable. + * @retval None. + */ +void md_usb_dma_channel_disable(uint32_t ui32Channel) +{ + // + // DMA1 will be used by es32f0271 + // + CLEAR_BIT(*(&DMA1->CSR0 + 4 * ui32Channel), DMA_CSR0_CHEN_MSK); +} + +/** + * @brief Check if the USB channel is enabled. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller. + * @param ui32Channel specifies the USB DMA channel. + * @retval Return 1 if the channel is enabled. + */ +uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel) +{ + if (*((uint32_t *)(&DMA1->CSR0 + ui32Channel * 4)) & DMA_CSR0_CHEN_MSK) + return 1; + + return 0; +} + +/** + * @brief Returns the current status for an integrated USB DMA channel. + * + * This function returns the current status for the USB DMA channel specified + * by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the USB DMA channel to query. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies the USB DMA channel to Disable. + * @retval Returns zero or \b USB_DMACTL0_ERR if there is a pending error + * condition on a DMA channel. + */ +uint32_t md_usb_dma_channel_status(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Clears the integrated USB DMA status for a specified channel. + * + * This function clears the USB DMA channel status for the channel specified + * by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the USB DMA channel to query. The \e ui32Status parameter + * specifies the status bits to clear and must be the valid values that are + * returned from a call to the md_usb_dma_channel_status() function. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies the USB DMA channel to Disable. + * @retval None. + */ +void md_usb_dma_channel_status_clear(uint32_t ui32Channel, + uint32_t ui32Status) +{ + // + // It is not supported by es32f0271 + // +} + +/** + * @} USB_MD_PF_DMA + */ + +/** + * @} USB_MD_Public_Functions + */ + +/** + * @} USB + */ + +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF MAIN.C****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..fdba390e172e688d9ddb0cb4acb7c82d3a5b8a9b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * @file md_wwdt.c + * @brief ES32F0271 WWDT Source File. + * + * @version V1.00.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_wwdt.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (WWDT) + +/** @defgroup WWDT WWDT + * @brief WWDT micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ +/** + * @brief De-initialize the GPIO registers to their default reset values. + * @param GPIOx GPIO Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: GPIO registers are not de-initialized + */ +void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_MD_WWDT_ALL_INSTANCE(WWD)); + assert_param(IS_MD_WWDT_PRESCALER(WWDT_InitStruct->Prescaler)); + assert_param(IS_MD_WWDT_WINDOW(WWDT_InitStruct->Window)); + assert_param(IS_MD_WWDT_COUNTER(WWDT_InitStruct->Counter)); + assert_param(IS_MD_WWDT_EWI_MODE(WWDT_InitStruct->EWIMode)); + + if (WWDT_InitStruct->EWIMode == WWDT_EWI_ENABLE) + md_wwdt_enable_ier_ewis(WWD); + else + md_wwdt_disable_idr_ewis(WWD); + + md_wwdt_set_con_t(WWD, WWDT_InitStruct->Counter); + md_wwdt_set_cfg_wdgtb(WWD, WWDT_InitStruct->Prescaler); + md_wwdt_set_cfg_w(WWD, WWDT_InitStruct->Window); + md_wwdt_enable_con_wdga(WWD); +} + + + + + + + + + + + +/** + * @} GPIO + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/SConscript b/bsp/essemi/es32f0271/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..00008f5fca116c0de9fb7f71ecf1407921c6a66a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/SConscript @@ -0,0 +1,32 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = [] + +src += Glob('ES32F027x_MD_StdPeriph_Driver/Source/*.c') + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/gcc/startup_es32f027x.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s'] + +src = src + ['CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c'] + +path = [cwd + '/CMSIS/Device/EastSoft/ES32F0271/Include', + cwd + '/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271', + cwd + '/CMSIS/Device/EastSoft/ES32F0271/System', + cwd + '/CMSIS/Include', + cwd + '/', + cwd + '/ES32F027x_MD_StdPeriph_Driver/Include'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h b/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h new file mode 100644 index 0000000000000000000000000000000000000000..3d6a812bf64fa1302f7119e4e4a4cac5ccc397c2 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h @@ -0,0 +1,41 @@ +/** + ************************************************************************************** + * @file type.h + * @brief Common types and macros. + * @data 12/21/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +//***************************************************************************** +// +// Macros for hardware access. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h b/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h new file mode 100644 index 0000000000000000000000000000000000000000..5fee2e973e81058f50820544c7793ccc47fa15e8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h @@ -0,0 +1,728 @@ +/** + ************************************************************************************** + * @file usb_lowlayer_api.h + * @brief USB library lower layer api + * @data 11/9/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Includes-------------------------------------------------------------------*/ +#include "stdint.h" +#include + +#ifndef __USB_LOWLAYER_API_H__ +#define __USB_LOWLAYER_API_H__ + + +/** + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public constants -----------------------------------------------------------*/ + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_int_enable() and +// md_usb_hosdev_int_disable() as the ui32Flags parameter, and are returned from +// md_usb_hosdev_int_status(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_int_enable() +// and md_usb_hosdev_endpoint_int_disable() as the ui32Flags parameter, and +// are returned from md_usb_hosdev_endpoint_int_status(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hos_speed_get() 0r +// md_usb_dev_speed_get(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hosdev_endpoint_status(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error +// (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the +// specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a +// device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device +// (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a +// device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a +// device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous +// transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to +// a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data +// to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before +// Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_endpoint_config_set() and +// md_usb_dev_endpoint_config_set() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DUAL_BUFFERING 0x00000008 // Dual buffering enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for +// high-speed Bulk and Interrupt +// endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_pwr_config() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_hos_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_dev_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// md_usb_lpm_link_state_get() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_lpm_int_enable() +// or md_usb_lpm_int_disable() functions or are returned from the md_usb_lpm_status() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_clock_enable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the md_usb_ulpi_config() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// md_usb_hos_endpoint_config_set() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_fifo_config_set() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_data_send() +// as the ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for +// endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint +// 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint +// 0) + +//***************************************************************************** +// +// The following are values are returned by the md_usb_hosdev_mode_get() function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host +// mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in +// Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not +// set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of +// the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of +// the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Channel configuration values. +// +//***************************************************************************** +#define DMA_DST_INC_8 0x00000000 +#define DMA_DST_INC_16 0x40000000 +#define DMA_DST_INC_32 0x80000000 +#define DMA_DST_INC_NONE 0xc0000000 +#define DMA_SRC_INC_8 0x00000000 +#define DMA_SRC_INC_16 0x04000000 +#define DMA_SRC_INC_32 0x08000000 +#define DMA_SRC_INC_NONE 0x0c000000 +#define DMA_SIZE_8 0x00000000 +#define DMA_SIZE_16 0x11000000 +#define DMA_SIZE_32 0x22000000 +#define DMA_DST_PROT_PRIV 0x00200000 +#define DMA_SRC_PROT_PRIV 0x00040000 +#define DMA_ARB_1 0x00000000 +#define DMA_ARB_2 0x00004000 +#define DMA_ARB_4 0x00008000 +#define DMA_ARB_8 0x0000c000 +#define DMA_ARB_16 0x00010000 +#define DMA_ARB_32 0x00014000 +#define DMA_ARB_64 0x00018000 +#define DMA_ARB_128 0x0001c000 +#define DMA_ARB_256 0x00020000 +#define DMA_ARB_512 0x00024000 +#define DMA_ARB_1024 0x00028000 +#define DMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_int_enable() and md_usb_dma_channel_int_status() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_status() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_mode_config() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +//***************************************************************************** +// +// Flags that can be passed to DMAChannelAttributeEnable(), +// DMAChannelAttributeDisable(), and returned from DMAChannelAttributeGet(). +// +//***************************************************************************** +#define DMA_ATTR_USEBURST 0x00000001 +#define DMA_ATTR_ALTSELECT 0x00000002 +#define DMA_ATTR_HIGH_PRIORITY 0x00000004 +#define DMA_ATTR_REQMASK 0x00000008 +#define DMA_ATTR_ALL 0x0000000F + +/* Public functions -----------------------------------------------------------*/ +/** + * @{ SYSTEM API. + */ +extern void md_usb_system_int_disable(void); +extern void md_usb_system_int_enable(void); +extern void md_usb_re_config(bool Device); /* Weak defination */ +extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ +extern void md_usb_systic_disable(void); +extern void md_usb_controller_reset(void); +extern void md_usb_controller_enable(void); +extern void md_usb_controller_disable(void); +extern void md_usb_clk_phy_enable(void); +extern void md_usb_clk_phy_disable(void); +extern uint32_t md_usb_nvic_number_get(void); +extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ +extern void md_usb_nvic_enable(void); +extern void md_usb_nvic_disable(void); +/** + * @} SYSTEM API. + */ + +/** + * @{ USB basic API. + */ +/* Host Mode */ +extern void md_usb_hos_reset(bool bStart); +extern void md_usb_hos_resume(bool bStart); +extern void md_usb_hos_suspend(void); +extern void md_usb_hos_request_status(void); +extern void md_usb_hos_request_in(uint32_t ui32Endpoint); +extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); +extern uint32_t md_usb_hos_speed_get(void); +extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +/* Device Mode */ +extern void md_usb_dev_addr_set(uint8_t ui32Address); +extern uint8_t md_usb_dev_addr_get(void); +extern void md_usb_dev_connect(void); +extern void md_usb_dev_disconnect(void); +extern uint32_t md_usb_dev_speed_get(void); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_frame_get(void); +extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_int_status(void); +extern uint32_t md_usb_hosdev_mode_get(void); +/* otg Mode */ +extern void md_usb_otg_session_request(bool bStart); +extern void md_usb_force_host_mode(void); +extern void md_usb_force_device_mode(void); +extern void md_usb_force_otg_mode(void); +extern void md_usb_mode_config(uint32_t ui32Mode); +/** + * @} USB basic API. + */ + +/** + * @{ USB endpoint API. + */ +/* Host Mode */ +extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); +extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, + bool bDataToggle, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, + bool bEnable); +/* Device Mode */ +extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); +extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, + uint8_t *pui8Data, + uint32_t ui32Size); +extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); +extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_endpoint_int_status(void); +extern uint32_t md_usb_endpoint_number_get(void); +/** + * @} USB endpoint API. + */ + +/** + * @{ USB FIFO API. + */ +extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); +extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, + uint32_t ui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); +/** + * @} USB FIFO API. + */ + +/** + * @{ USB PWR API.it is not supported by es32f0271. + */ +extern void md_usb_hos_pwr_disable(void); +extern void md_usb_hos_pwr_enable(void); +extern void md_usb_hos_pwr_config(uint32_t ui32Flags); +extern void md_usb_hos_pwrfault_disable(void); +extern void md_usb_hos_pwrfault_enable(void); +/** + * @} USB PWR API. + */ + +/** + * @{ USB LPM API.it is not supported by es32f0271. + */ +extern void md_usb_hos_lpm_send(uint32_t ui32Address, + uint32_t uiEndpoint); +extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, + uint32_t ui32Config); +extern bool md_usb_lpm_remotewake_is_enabled(void); +extern void md_usb_hos_lpm_resume(void); +extern void md_usb_dev_lpm_remotewake(void); +extern void md_usb_dev_lpm_config(uint32_t ui32Config); +extern void md_usb_dev_lpm_enable(void); +extern void md_usb_dev_lpm_disable(void); +extern uint32_t md_usb_lpm_link_state_get(void); +extern uint32_t md_usb_lpm_endpoint_get(void); +extern uint32_t md_usb_lpm_status(void); +extern void md_usb_lpm_int_disable(uint32_t ui32Ints); +extern void md_usb_lpm_int_enable(uint32_t ui32Ints); +/** + * @} USB LPM API. + */ + +/** + * @{ USB ULPI API.it is not supported by es32f0271. + */ +extern void md_usb_ulpi_config(uint32_t ui32Config); +extern void md_usb_ulpi_enable(void); +extern void md_usb_ulpi_disable(void); +extern uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg); +extern void md_usb_ulpi_reg_write(uint8_t ui8Reg, + uint8_t ui8Data); +/** + * @} USB ULPI API. + */ + +/** + * @{ USB DMA API.it is not supported by es32f0271. + */ +extern void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_config(uint32_t ui32Channel, + uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_address_set(uint32_t ui32Channel, + void *pvAddress); +extern void *md_usb_dma_channel_address_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_count_set(uint32_t ui32Count, + uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_int_status(void); +extern void md_usb_dma_channel_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_status(uint32_t ui32Channel); +extern void md_usb_dma_channel_status_clear(uint32_t ui32Channel, + uint32_t ui32Status); +/** + * @} USB DMA API. + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/project.uvoptx b/bsp/essemi/es32f0271/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..bd379df962cc044c682312fc6471414d42319ba1 --- /dev/null +++ b/bsp/essemi/es32f0271/project.uvoptx @@ -0,0 +1,797 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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+ + + + + + + + + Kernel + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 1 + 9 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 1 + 10 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 1 + 11 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 1 + 12 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 1 + 13 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 1 + 14 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Applications + 0 + 0 + 0 + 0 + + 2 + 15 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 3 + 16 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 4 + 19 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_adc.c + md_adc.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_fc.c + md_fc.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_gpio.c + md_gpio.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_i2c.c + md_i2c.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_rcu.c + md_rcu.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_spi.c + md_spi.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_tick.c + md_tick.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_uart.c + md_uart.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_usb.c + md_usb.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_wwdt.c + md_wwdt.c + 0 + 0 + + + 4 + 29 + 2 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\ES32F0271\Startup\keil\startup_es32f027x.s + startup_es32f027x.s + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\ES32F0271\System\system_es32f027x.c + system_es32f027x.c + 0 + 0 + + + + + cpu + 0 + 0 + 0 + 0 + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 5 + 35 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + diff --git a/bsp/essemi/es32f0271/project.uvprojx b/bsp/essemi/es32f0271/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..664a6e8f023a63bbed15617419d66874992fe7f8 --- /dev/null +++ b/bsp/essemi/es32f0271/project.uvprojx @@ -0,0 +1,662 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ES32F0271LT + Eastsoft + Eastsoft.ES32_DFP.1.0.4 + http://www.essemi.com + IRAM(0x20000000,0x00002000) IROM(0x00000000,0x00010000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F0271 -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM)) + 0 + $$Device:ES32F0271LT$Device\Include\es32f027x.h + + + + + + + + + + $$Device:ES32F0271LT$SVD\es32f027x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F0271\Include;libraries\CMSIS\Device\EastSoft\ES32F0271\Include\ES32F0271;libraries\CMSIS\Device\EastSoft\ES32F0271\System;libraries\CMSIS\Include;libraries;libraries\ES32F027x_MD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + md_adc.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_adc.c + + + md_fc.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_fc.c + + + md_gpio.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_gpio.c + + + md_i2c.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_i2c.c + + + md_rcu.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_rcu.c + + + md_spi.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_spi.c + + + md_tick.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_tick.c + + + md_uart.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_uart.c + + + md_usb.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_usb.c + + + md_wwdt.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_wwdt.c + + + startup_es32f027x.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F0271\Startup\keil\startup_es32f027x.s + + + system_es32f027x.c + 1 + libraries\CMSIS\Device\EastSoft\ES32F0271\System\system_es32f027x.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + + + + + + + + + + diff --git a/bsp/essemi/es32f0271/rtconfig.h b/bsp/essemi/es32f0271/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..4a0cf3306a074e2f9f2ccc1c0a89debfbf6fc3ca --- /dev/null +++ b/bsp/essemi/es32f0271/rtconfig.h @@ -0,0 +1,183 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40002 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 256 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_ES32F0271LT + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +/* PIN Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART1 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* HWtimer Drivers */ + + +/* PWM Drivers */ + + +/* RTC Drivers */ + + +/* ADC Drivers */ + + +/* Onboard Peripheral Drivers */ + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/essemi/es32f0271/rtconfig.py b/bsp/essemi/es32f0271/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..eb371bf3a7199a3b5530611d6fb7f0dc26bf5600 --- /dev/null +++ b/bsp/essemi/es32f0271/rtconfig.py @@ -0,0 +1,135 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH = 'arm' +CPU = 'cortex-m0' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': # not support gcc yet + PLATFORM = 'gcc' + EXEC_PATH = 'C:/GCC' + +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +elif CROSS_TOOL == 'iar': # not support iar yet + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/essemi/es32f0271/template.uvoptx b/bsp/essemi/es32f0271/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..bb8cce6ff239433f865a076c0a65468edf11b7e5 --- /dev/null +++ b/bsp/essemi/es32f0271/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0ES32F0271 -FL010000 -FS00 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ES32F0271.FLM -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/essemi/es32f0271/template.uvprojx b/bsp/essemi/es32f0271/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..ce19e112f525126e07269fab57b4f661434b4b02 --- /dev/null +++ b/bsp/essemi/es32f0271/template.uvprojx @@ -0,0 +1,389 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
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