- 07 11月, 2019 1 次提交
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由 Zhan Liu 提交于
This reverts commit 385857ad. Reason for revert: Root cause of this issue is found. The workaround is not needed anymore. Signed-off-by: NZhan Liu <zhan.liu@amd.com> Reviewed-by: NHersen Wu <hersenxs.wu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 10月, 2019 1 次提交
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由 Zhan liu 提交于
[Why] This patch is for fixing Navi14 HDMI display pink screen issue. [How] Call stream->link->link_enc->funcs->setup twice. This is setting the DIG_MODE to the correct value after having been overridden by the call to transmitter control. Signed-off-by: NZhan Liu <zhan.liu@amd.com> Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 24 8月, 2019 1 次提交
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由 Su Sung Chung 提交于
[Why] Disable_audio_stream gets enum option as a paramenter which will decide if we free acquired resources or not. However checks for the option is guarded by the other condition which check if audio stream is getting diabled more than once. With both conditions combined, if we attempt to disable audio stream twice in a row, first with keep and second with free as an option, we will never free any resources, which will make system think there is audio endpoint connected even after we plug out the device [How] Get rid of option as parameter to disable_audio_stream and move the part of the code that free acquired resources to outside where to keep or to free resources is actually determined Signed-off-by: NSu Sung Chung <Su.Chung@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 8月, 2019 2 次提交
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由 YueHaibing 提交于
Remove duplicated include. Reported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NYueHaibing <yuehaibing@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nathan Chancellor 提交于
When building arm32 allyesconfig: ld.lld: error: undefined symbol: __aeabi_uldivmod >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a time_taken_in_ns is of type unsigned long long so we need to use div_u64 to avoid this error. Fixes: b5b1f455 ("drm/amd/display: Enable type C hotplug") Reported-by: NRandy Dunlap <rdunlap@infradead.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NNathan Chancellor <natechancellor@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 8月, 2019 5 次提交
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由 Wenjing Liu 提交于
[why] During detection link training if a display is disconnected, the current code will retry 3 times of link training on disconnected link before giving up. [how] Before each retry check for HPD status, only retry verify link cap when HPD is still high. Also put a 10ms delay between each retry to improve the chance of success. Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NAbdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why and How] We want to change where timing is done for alt mode. Some of the commented out #ifs are needed for DCN20 so we enable them for that case. Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nikola Cornij 提交于
[why] At the time DIG FE is connected to its BE, the clocks in OTG are enabled and PHY will also be set up. When DSC has to be used to fit the stream into the available bandwidth, without DSC being set DIG could get exposed to the higer bandwidth it (or link) could handle. This causes the HW to "reject" video enable setup (the register shows that video enable was attempted, but the status bit shows it as disabled). [how] - Separate DSC setup into DSC register config and DSC PPS SDP setup - Move most of the DSC setup (register config) to before dcn10_link_encoder_connect_dig_be_to_fe() is called - Set up DSC PPS SDP after DIG FE is connected to its BE. This is because setting DSC PPS SDP before that has no effect. Signed-off-by: NNikola Cornij <nikola.cornij@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Martin Leung 提交于
[Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes [How] Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/ Pixel clock. This is part 2 of 2 for seamless boot NV10 Signed-off-by: NMartin Leung <martin.leung@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 David Galiffi 提交于
[WHY] We require a method to perform synchronous link training. [HOW] Sync LT is broken into 3 basic steps. "Begin" starts the state machine, and resets "preferred" link settings. "Attempt" will attempt to train the link with a given set of training parameters. "End" stops the state machine, and will optionally disable the link phy. Between "Begin" and "End" DPCD:600h must not be set to "2" (D3:Powered Down). Between "Begin" and "End", there may be multiple "Attempts" with different training parameters. Signed-off-by: NDavid Galiffi <david.galiffi@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 7月, 2019 15 次提交
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由 Eric Yang 提交于
[Why] Previously assume eDP sink present if connector present. Do not need to enforce this restriction. Fix issue where driver attempt to read link setting even though no edp connected. {How] Only read link setting after reading connection status. Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Zhan Liu 提交于
[Why] For boards that support eDP but do not have a physical eDP display connected an ASSERT will be thrown. This is not a critical failure and shouldn't be treated as such. [How] Drop the assertion. Signed-off-by: NZhan Liu <zhan.liu@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nikola Cornij 提交于
[why] Right now we FEC_READY is set only before the final link training, i.e. at mode set time. This means FEC_READY won't be set when doing link training as a response to HPD. It also fails UCD400 FEC test in DP compliance. [how] Move FEC_READY setup to link training. Signed-off-by: NNikola Cornij <nikola.cornij@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NAbdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Bernstein 提交于
Use helper to determine if HDMI signal when processing avmute. Signed-off-by: NEric Bernstein <eric.bernstein@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Harry Wentland 提交于
[Why] link_stream is never NULL here as we've dereferenced it a couple lines before and have done so for a couple months now. [How] - Drop the NULL check. - Initialize where we know link_stream is non-NULL Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Zi Yu Liao 提交于
[why] When the system is going into suspend, set_backlight gets called after the eDP got blanked. Since smooth brightness is enabled, the driver will make a call into the DMCU to ramp the brightness. The DMCU would try to enable ABM to do so. But since the display is blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to get stuck at 1, which results in a dead lock in the DMCU firmware. [how] Disable brightness ramping when the eDP display is blanked. Signed-off-by: NZi Yu Liao <ziyu.liao@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Derek Lai 提交于
[Why] When launch D10.2, driver will write DPCD 0x107 with 0x00 [How] Read MAX_DOWNSPREAD (0x0003h) then keep in current link settings Signed-off-by: NDerek Lai <Derek.Lai@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
This change adds EMP packet programming for enabling dsc with hdmi. The packets are structured according to VESA HDMI 2.1x r2 spec, section 10.10.2.2. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Samson Tam 提交于
[Why] Fixes issue when we have a display connected using a passive dongle and then emulate over it using a DP connection at 1 x 1.62 Ghz. System hangs because register bus returns back 0xFFFFFFFF for all register reads after setting register DIG_BE_CNTL in dcn10_link_encoder_connect_dig_be_to_fe(). Hang occurs later when trying to do a register read. [How] At the start of the emulation, dc_link_set_preferred_link_settings() and dp_retrain_link_dp_test() is called, even though it is connected using a passive dongle. Add an extra condition in dp_retrain_link_dp_test() to check for link->dongle_max_pix_clk > 0. This is the only way we know if the connection is using passive dongle so we don't retrain DP. Signed-off-by: NSamson Tam <Samson.Tam@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 David Galiffi 提交于
[WHY] To add support for OS requirement to set preferred link training parameters. [HOW] Create new structure of dp link training overrides. During link training processes, these values should be used instead of the default training parameters. Signed-off-by: NDavid Galiffi <David.Galiffi@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] Previously assume eDP sink present if connector present. Do not need to enforce this restriction. Fix issue where driver attempt to read link setting even though no edp connected. {How] Only read link setting after reading connection status. Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Zhan Liu 提交于
[Why] For boards that support eDP but do not have a physical eDP display connected an ASSERT will be thrown. This is not a critical failure and shouldn't be treated as such. [How] Drop the assertion. Signed-off-by: NZhan Liu <zhan.liu@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Zi Yu Liao 提交于
[why] When the system is going into suspend, set_backlight gets called after the eDP got blanked. Since smooth brightness is enabled, the driver will make a call into the DMCU to ramp the brightness. The DMCU would try to enable ABM to do so. But since the display is blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to get stuck at 1, which results in a dead lock in the DMCU firmware. [how] Disable brightness ramping when the eDP display is blanked. Signed-off-by: NZi Yu Liao <ziyu.liao@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Derek Lai 提交于
[Why] When launch D10.2, driver will write DPCD 0x107 with 0x00 [How] Read MAX_DOWNSPREAD (0x0003h) then keep in current link settings Signed-off-by: NDerek Lai <Derek.Lai@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Samson Tam 提交于
[Why] Fixes issue when we have a display connected using a passive dongle and then emulate over it using a DP connection at 1 x 1.62 Ghz. System hangs because register bus returns back 0xFFFFFFFF for all register reads after setting register DIG_BE_CNTL in dcn10_link_encoder_connect_dig_be_to_fe(). Hang occurs later when trying to do a register read. [How] At the start of the emulation, dc_link_set_preferred_link_settings() and dp_retrain_link_dp_test() is called, even though it is connected using a passive dongle. Add an extra condition in dp_retrain_link_dp_test() to check for link->dongle_max_pix_clk > 0. This is the only way we know if the connection is using passive dongle so we don't retrain DP. Signed-off-by: NSamson Tam <Samson.Tam@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 7月, 2019 1 次提交
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由 Arnd Bergmann 提交于
On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6a ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e5 ("drm/amd/display: update calculated bounding box logic for NV") Acked-by: NSlava Abramov <slava.abramov@amd.com> Tested-by: NSlava Abramov <slava.abramov@amd.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 6月, 2019 1 次提交
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由 Alex Deucher 提交于
We may need to sleep for up to 80ms (8ms per each of up to 10 loop iterations): /* First DPCD read after VDD ON can fail if the particular board * does not have HPD pin wired correctly. So if DPCD read fails, * which it should never happen, retry a few times. Target worst * case scenario of 80 ms. */ Switch udelay to msleep to avoid limits on arm. Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 6月, 2019 6 次提交
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由 Wenjing Liu 提交于
[why] dsc adjustment is allowed via stream update sequence. dsc enablement is only allowed via commit stream sequence. with the current unified dsc set function, it is hard to determine which sequence it is called by. The solution is to decouple dsc adjustment out of enablement sequence so we can handle them separately. [how] decouple dsc adjustment out of enablement. Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[why] The current policy will always enable DSC to 12 bpp regardless of if the current bandwidth is enough for MST displays. This logic is not optimal because user will get lower quality output if DSC compression is enabled. This change to is to implement a DSC MST bandwidth fair share algorithm so we will dynamically decide if DSC is needed and what quality (target bpp) is needed to fairly destribute the MST bandwidth in one MST topology. This will allow user to see the most optimal image quality with the given bandwidth. [how] We will start with lowest bandwidth possible and run a Max-Min fairness algorithm to fairly distribute the available bandwidth. If there is still remaining bandwidth, we will try to fit the timing without DSC compression. Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Acked-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nikola Cornij 提交于
[why] Currently link bandwidth is calculated in various places using the same multi-step formula. Doing this in one common place makes sure the same formula will indeed be applied to all link bandwidth calculations. It also makes it possible to apply link-setting-specific adjustments that affect effective link bandwidth. [how] Replace all implementations of link bandwidth calculation with a call to a function. Signed-off-by: NNikola Cornij <nikola.cornij@amd.com> Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Chris Park 提交于
[Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by: NChris Park <Chris.Park@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Harry Wentland 提交于
Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Harry Wentland 提交于
Core DC changes for DCN2. Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 6月, 2019 4 次提交
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由 Samson Tam 提交于
[Why] Found issue in EDID Emulation where if we connect a display using a passive HDMI-DP dongle, disconnect it and then try to emulate a display using DP, we could not see 4K modes. This was because on a disconnect, dongle_max_pix_clk was still set so when we emulate using DP, in dc_link_validate_mode_timing(), it would think we were still using a dongle and limit the modes we support. [How] In dc_link_detect(), set dongle_max_pix_clk to 0 when we detect a hotplug out ( if new_connection_type = dc_connection_none ). Signed-off-by: NSamson Tam <Samson.Tam@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jordan Lazare 提交于
[Why] VBios sometimes reports incorrect object type as encoder instead of connector [How] Change error message to debug message Signed-off-by: NJordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Chris Park 提交于
These are no longer needed, Also added RESERVED bits. Signed-off-by: NChris Park <Chris.Park@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: NHarry Wentland <Harry.Wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
[Why] HPD not going to be high if Panel VDD is off And all AUX transaction will fail :( [How] 1. Power on VDD before attempting detection if it isn't already on 2. Improve the robustness by having a retry mechanism on the first DPCD read after VDD on. If a particular board always holds HPD high incorrectly, the AUX access may fail, so we can retry in those scenarios. This change would only improve logic since it prevents AUX failure leading to bad resolution on internal panel. 3. We should never need to re-detect internal panel, so logic is re-arranged a bit to skip earlier. Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 11 6月, 2019 1 次提交
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由 Sam Ravnborg 提交于
Drop use of the deprecated drmP.h header from atom.h Fix fallout in various files. Signed-off-by: NSam Ravnborg <sam@ravnborg.org> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-6-sam@ravnborg.org
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- 31 5月, 2019 2 次提交
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由 Chris Park 提交于
[Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by: NChris Park <Chris.Park@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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