- 09 4月, 2013 26 次提交
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由 Philipp Zabel 提交于
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Reviewed-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NMarek Vasut <marex@denx.de> Reviewed-by: NPavel Machek <pavel@ucw.cz> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
Also, link SRC to IPU via phandle. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Reviewed-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NMarek Vasut <marex@denx.de> Reviewed-by: NPavel Machek <pavel@ucw.cz> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Reviewed-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NMarek Vasut <marex@denx.de> Reviewed-by: NPavel Machek <pavel@ucw.cz> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Steffen Trumtrar 提交于
Add ldb device tree node and clock lookups. Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Gwenhael Goavec-Merou 提交于
The APF27Dev is a docking board for an APF27 SOM Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Gwenhael Goavec-Merou 提交于
Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The i.MX6 already has a devicetree node for the GPT, but not yet has the clocks. Add them. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The GPT is the GPT timer found on i.MX SoCs. This patch adds the devicetree node for it. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The GPT is the GPT timer found on i.MX SoCs. This patch adds the devicetree node for it. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The GPT is the GPT timer found on i.MX SoCs. Since this is the first user of the AIPS2 this patch also adds it. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The GPT is the GPT timer found on i.MX SoCs. This adds the missing GPT devicetree nodes. Also fixup the watchdog register map size along the way. it's 0x1000, not 0x4000. This didn't hurt before as the region was not occupied by another device, but now overlaps with the GPT. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance task for the clock devices easier. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Tested-by: NMarkus Pargmann <mpa@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Gwenhael Goavec-Merou 提交于
Add a second pinctrl group of pins for i2c2. Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Gwenhael Goavec-Merou 提交于
Add ecspi2 group of pins for imx51. Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Gwenhael Goavec-Merou 提交于
The APF51Dev is a docking board for an APF51 SOM Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sean Cross 提交于
Allow AUD3 to be used as audio output from the audmux block. Signed-off-by: NSean Cross <xobs@kosagi.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sean Cross 提交于
Add groups to allow i2c2 and i2c3 to be used on imx6q. Signed-off-by: NSean Cross <xobs@kosagi.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sean Cross 提交于
Add a group of pins to allow ecspi3 to be used on imx6q. Signed-off-by: NSean Cross <xobs@kosagi.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NDong Aisheng <dong.aisheng@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Shawn Guo 提交于
Replace /include/ (dtc) with #include (C pre-processor) for all imx DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as pinctrl settings. Use of those features will increase the readability of the device tree files. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Peter Chen 提交于
Add USB support for imx6q sabresd board Signed-off-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Dirk Behme 提交于
Add ARM Cortex A9 Performance Monitor Unit (PMU) support. On i.MX6 a combined interrupt on hardware line #126 is used (i.MX6 TRM: Performance Unit interrupt). For more details see Documentation/devicetree/bindings/arm/pmu.txt Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 06 4月, 2013 1 次提交
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由 Stephen Warren 提交于
The recent dtc+cpp support allows header files and C pre-processor defines/macros to be used when compiling device tree files. These headers will typically define various constants that are part of the device tree bindings. The original patch which set up the dtc+cpp include path only considered using those headers from device tree files. However, most are also useful for kernel code which needs to interpret the device tree. In both the DT files and the kernel, I'd like to include the DT-related headers in the same way, for example, <dt-bindings/gpio/tegra-gpio.h>. That will simplify any text which discusses the DT header locations. Creating a <dt-bindings/> for kernel source to use is as simple as placing files into include/dt-bindings/. However, when compiling DT files, the include path should be restricted so that only the dt-bindings path is available; arbitrary kernel headers shouldn't be exposed. For this reason, create a specific include directory for use by dtc+cpp, and symlink dt-bindings from there to the actual location of include/dt-bindings/. For want of a better location, place this "include chroot" into the existing dts/ directory. arch/*/boot/dts/include/dt-bindings -> ../../../../../include/dt-bindings Some headers used by device tree files may not be useful to the kernel; they may be used simply to aid in constructing the DT file (e.g. macros to create a node), but not define any information that the kernel needs to share. These may be placed directly into arch/*/boot/dts/ along with the DT files themselves. Acked-by: NMichal Marek <mmarek@suse.cz> Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 23 3月, 2013 1 次提交
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由 Laxman Dewangan 提交于
Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 13 3月, 2013 2 次提交
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由 Richard Genoud 提交于
There was only chip enable and readdy/busy pins for the nand controller. This add the rest of the pins. pinctrl_nand_16bits contains the specific muxes for 16 bits NANDs. Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Richard Genoud 提交于
Comments on NAND pins where inverted. Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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- 12 3月, 2013 2 次提交
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由 Arnd Bergmann 提交于
The ab8500 device is a child of the prcmu device, which is a memory mapped bus device, whose children are addressable using physical memory addresses, not using mailboxes, so a mailbox number in the ab8500 node cannot be parsed by DT. Nothing uses this number, since it was only introduced as part of the failed attempt to clean up prcmu mailbox handling, and we can simply remove it. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Padmavathi Venna 提交于
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on SOCFPGA platform. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 09 3月, 2013 8 次提交
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由 Thomas Petazzoni 提交于
The orion5x-lacie-ethernet-disk-mini-v2.dts file was using "marvell-orion5x-88f5182" as a compatible string, while it should have been "marvell,orion5x-88f5182". Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
There is no need to have a #address-cells property in the MPIC Device Tree node, and more than that, having it confuses the of_irq_map_raw() logic, which will be used by the Marvell PCIe driver. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Heikki Krogerus 提交于
Setting the reg-io-width to 1 byte represents more accurate description of the HW. This will fix an issue where UART driver causes kernel panic during bootup. Gregory CLEMENT traced the issue to autoconfig() in 8250.c, where the existence of FIFO is checked from UART_IIR register. The register is now read as 32-bit value as the reg-io-width is set to 4-bytes. The retuned value seems to contain bogus data for bits 31:8, causing the issue. Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jean-Francois Moine 提交于
The commit: 48be9ac9 ARM: Dove: split legacy and DT setup removed the RTC initialization. This patch re-enables the RTC via the DT. Signed-off-by: NJean-François Moine <moinejf@free.fr> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Florian Fainelli 提交于
This patch modifies the Armada 370 Reference Design DTS file to enable support for the two USB ports found on this board. Signed-off-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the driver clk_prepare_enable() this clock, otherwise there is a danger the SoC will lockup when accessing RTC registers with the clock disabled. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
The kirkwood SoC GPIO cores use the runit clock. Add code to clk_prepare_enable() runit, otherwise there is a danger of locking up the SoC by accessing the GPIO registers when runit clock is not ticking. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jason Cooper 提交于
When DT support for kirkwood was first introduced, there was no clock infrastructure. As a result, we had to manually pass the clock-frequency to the driver from the device node. Unfortunately, on kirkwood, with minimal config or all module configs, clock-frequency breaks booting because of_serial doesn't consume the gate_clk when clock-frequency is defined. The end result on kirkwood is that runit gets gated, and then the boot fails when the kernel tries to write to the serial port. Fix the issue by removing the clock-frequency parameter from all kirkwood dts files. Booted on dreamplug without earlyprintk and successfully logged in via ttyS0. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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