- 30 4月, 2019 1 次提交
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由 Stefan Agner 提交于
In every other instance where mrc is used the coprocessor operand is prefix with p (e.g. p15). Use the p prefix in this case too. This fixes a build issue when using LLVM's integrated assembler: arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for instruction mrc 15, 0, r3, cr0, cr0, 5 ^ arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID ^ Signed-off-by: NStefan Agner <stefan@agner.ch> Acked-by: NNicolas Pitre <nico@fluxnic.net> Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
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- 22 11月, 2014 1 次提交
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由 Thomas Petazzoni 提交于
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and ll_disable_coherency() are used on Armada XP to control the coherency fabric. However, they make the assumption that the coherency fabric is always available, which is currently a correct assumption but will no longer be true with a followup commit that disables the usage of the coherency fabric when the conditions are not met to use it. Therefore, this commit modifies those functions so that they check the return value of ll_get_coherency_base(), and if the return value is 0, they simply return without configuring anything in the coherency fabric. The ll_get_coherency_base() function is also modified to properly return 0 when the function is called with the MMU disabled. In this case, it normally returns the physical address of the coherency fabric, but we now check if the virtual address is 0, and if that's case, return a physical address of 0 to indicate that the coherency fabric is not enabled. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.8+ Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 18 7月, 2014 1 次提交
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由 Russell King 提交于
ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: NWill Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: NShawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 5月, 2014 4 次提交
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由 Thomas Petazzoni 提交于
In the refactoring of the coherency fabric assembly code, a function called ll_get_cpuid() was created to factorize common logic between functions adding CPU to the SMP coherency group, enabling and disabling the coherency. However, the name of the function is highly misleading: ll_get_cpuid() makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1 for CPU1, etc. In fact, this is not at all what this function returns: it returns a CPU mask for the current CPU, usable for the coherency fabric configuration and control registers. Therefore this commit renames this function to ll_get_coherency_cpumask(), and adds additional comments on top of the function to explain in more details what it does, and also how the endianess issue is handled. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-5-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
This commit makes no functional change, it only improves a bit the various code comments in mach-mvebu/coherency_ll.S, by fixing a few typos and adding a few more details. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-4-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
This commit does not make any functional change, it only fixes the indentation of a few assembly instructions in arch/arm/mach-mvebu/coherency_ll.S. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-3-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
As part of the introduction of the cpuidle support for Armada XP, the coherency code was significantly reworked, especially in the coherency_ll.S file. However, when the ll_get_cpuid function was created, the big-endian specific code that switches the endianess of the register was not updated properly. This patch fixes this code, and therefore makes big endian systems bootable again. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 2e8a5942 ("ARM: mvebu: Split low level functions to manipulate HW coherency") Reported-by: NKevin Hilman <khilman@linaro.org> Cc: Kevin Hilman <khilman@linaro.org> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 09 5月, 2014 4 次提交
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由 Gregory CLEMENT 提交于
When going to deep idle we need to disable the SoC snooping (aka hardware coherency support). Playing with the coherency fabric requires to use assembly code to be sure that the compiler doesn't reorder the instructions nor do wrong optimization. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
Actually enabling coherency and adding a CPU on a SMP group are two different operations which can be done separately. This patch splits this in two functions. Moreover as they use common pattern, this patch also creates local low level functions (ll_get_coherency_base and ll_get_cpuid) to be used by the exposed functions (ll_add_cpu_to_smp_group and ll_enable_coherency) Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
ll_set_cpu_coherent is always used on the current CPU, so instead of passing the CPU id as argument, ll_set_cpu_coherent() can find it by itself. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.comAcked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
In order to be able to deal with the MMU enabled and the MMU disabled cases, the base address of the coherency registers was passed to the function. The address by itself was not interesting as it can't change for a given SoC, the only thing we need is to have a distinction between the physical or the virtual address. This patch add a check of the MMU bit to choose the accurate address, then the calling function doesn't have to pass this information. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 20 10月, 2013 1 次提交
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由 Ben Dooks 提交于
Add indication we can run these cores in BE mode, and ensure that the secondary CPU is set to big-endian mode in the initialisation code as the initial code runs little-endian. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NJason Cooper <jason@lakedaemon.net>
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- 28 5月, 2013 1 次提交
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由 Nadav Haklai 提交于
When adding CPU to the SMP group and enabling the coherency on this CPU we must protect the register access. The previous implementation claims to be atomic but doesn't provide any protection against parallel access to the coherency fabric control and configuration registers. This patch fixes this by using the ldrex and strex mechanism. This method should be used in all accesses to those registers. [gregory.clement@free-electrons.com: fixed the commit's topic] Signed-off-by: NNadav Haklai <nadavh@marvell.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 21 11月, 2012 1 次提交
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由 Gregory CLEMENT 提交于
The Armada 370 and Armada XP SOCs have a coherency fabric unit which is responsible for ensuring hardware coherency between all CPUs and between CPUs and I/O masters. This patch provides the basic support needed for SMP. Signed-off-by: NYehuda Yitschak <yehuday@marvell.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: NWill Deacon <will.deacon@arm.com>
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