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体验新版 GitCode,发现更多精彩内容 >>
提交
c6ad7b7d
编写于
6月 20, 2005
作者:
M
Maciej W. Rozycki
提交者:
Ralf Baechle
10月 29, 2005
浏览文件
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浏览文件
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电子邮件补丁
差异文件
Use macros for the RM7k cp0.config bits instead of magic numbers.
Minor clean-ups. Signed-off-by:
N
Ralf Baechle
<
ralf@linux-mips.org
>
上级
8a185d14
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
16 addition
and
11 deletion
+16
-11
arch/mips/mm/sc-rm7k.c
arch/mips/mm/sc-rm7k.c
+9
-9
include/asm-mips/mipsregs.h
include/asm-mips/mipsregs.h
+7
-2
未找到文件。
arch/mips/mm/sc-rm7k.c
浏览文件 @
c6ad7b7d
...
...
@@ -103,7 +103,7 @@ static __init void __rm7k_sc_enable(void)
{
int
i
;
set_c0_config
(
R7K_CONF_SE
);
set_c0_config
(
R
M
7K_CONF_SE
);
write_c0_taglo
(
0
);
write_c0_taghi
(
0
);
...
...
@@ -122,16 +122,16 @@ static __init void __rm7k_sc_enable(void)
static
__init
void
rm7k_sc_enable
(
void
)
{
if
(
read_c0_config
()
&
R7K_CONF_SE
)
if
(
read_c0_config
()
&
R
M
7K_CONF_SE
)
return
;
printk
(
KERN_INFO
"Enabling secondary cache..."
);
printk
(
KERN_INFO
"Enabling secondary cache...
\n
"
);
run_uncached
(
__rm7k_sc_enable
);
}
static
void
rm7k_sc_disable
(
void
)
{
clear_c0_config
(
R7K_CONF_SE
);
clear_c0_config
(
R
M
7K_CONF_SE
);
}
struct
bcache_ops
rm7k_sc_ops
=
{
...
...
@@ -145,19 +145,19 @@ void __init rm7k_sc_init(void)
{
unsigned
int
config
=
read_c0_config
();
if
((
config
>>
31
)
&
1
)
/* Bit 31 set -> no S-Cache */
if
((
config
&
RM7K_CONF_SC
))
return
;
printk
(
KERN_INFO
"Secondary cache size %dK, linesize %d bytes.
\n
"
,
(
scache_size
>>
10
),
sc_lsize
);
if
(
!
(
config
&
R7K_CONF_SE
))
if
(
!
(
config
&
R
M
7K_CONF_SE
))
rm7k_sc_enable
();
/*
* While we're at it let's deal with the tertiary cache.
*/
if
(
!
(
(
config
>>
17
)
&
1
))
{
if
(
!
(
config
&
RM7K_CONF_TC
))
{
/*
* We can't enable the L3 cache yet. There may be board-specific
...
...
@@ -170,9 +170,9 @@ void __init rm7k_sc_init(void)
* to probe it.
*/
printk
(
KERN_INFO
"Tertiary cache present, %s enabled
\n
"
,
config
&
(
1
<<
12
)
?
"already"
:
"not (yet)"
);
(
config
&
RM7K_CONF_TE
)
?
"already"
:
"not (yet)"
);
if
((
config
>>
12
)
&
1
)
if
((
config
&
RM7K_CONF_TE
)
)
rm7k_tcache_enabled
=
1
;
}
...
...
include/asm-mips/mipsregs.h
浏览文件 @
c6ad7b7d
...
...
@@ -425,6 +425,7 @@
#define CONF_SM (_ULCAST_(1) << 16)
#define CONF_SC (_ULCAST_(1) << 17)
#define CONF_EW (_ULCAST_(3) << 18)
#define CONF_SB (_ULCAST_(3) << 22)
#define CONF_EP (_ULCAST_(15)<< 24)
#define CONF_EC (_ULCAST_(7) << 28)
#define CONF_CM (_ULCAST_(1) << 31)
...
...
@@ -432,14 +433,18 @@
/* Bits specific to the R4xx0. */
#define R4K_CONF_SW (_ULCAST_(1) << 20)
#define R4K_CONF_SS (_ULCAST_(1) << 21)
#define R4K_CONF_SB (_ULCAST_(3) << 22)
/* Bits specific to the R5000. */
#define R5K_CONF_SE (_ULCAST_(1) << 12)
#define R5K_CONF_SS (_ULCAST_(3) << 20)
/* Bits specific to the RM7000. */
#define R7K_CONF_SE (_ULCAST_(1) << 3)
#define RM7K_CONF_SE (_ULCAST_(1) << 3)
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
/* Bits specific to the R10000. */
#define R10K_CONF_DN (_ULCAST_(3) << 3)
...
...
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