diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d88f910384285ce34d6e7128a1c93e35ed0d0cbd..eccaa79cb4a9d97f36ebcdab1226616153e24a17 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -255,26 +255,6 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	return phy == PHY_A;
 }
 
-static bool verify_wa14011224835(struct drm_i915_private *i915)
-{
-	u32 grccode, val;
-	bool ret = true;
-
-	grccode = REG_FIELD_GET(GRCCODE,
-				intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A)));
-	val = REG_FIELD_PREP(IREF_RCAL_ORD, grccode);
-	ret &= check_phy_reg(i915, PHY_B, ICL_PORT_COMP_DW2(PHY_B),
-			     IREF_RCAL_ORD, val);
-
-	grccode = REG_FIELD_GET(GRCCODE_LDO,
-				intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A)));
-	val = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode);
-	ret &= check_phy_reg(i915, PHY_B, ICL_PORT_COMP_DW2(PHY_B),
-			     IREF_RCAL_ORD, val);
-
-	return ret;
-}
-
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 				       enum phy phy)
 {
@@ -315,11 +295,6 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
-	/* Wa_14011224835:rkl[a0..b0] */
-	if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) &&
-	    phy == PHY_B)
-		ret &= verify_wa14011224835(dev_priv);
-
 	return ret;
 }
 
@@ -375,26 +350,6 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
 }
 
-static void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915)
-{
-	u32 grccode, val;
-
-	wait_for_us(intel_de_read(i915, ICL_PORT_COMP_DW3(PHY_A)) &
-		    FIRST_COMP_DONE, 100);
-
-	grccode = REG_FIELD_GET(GRCCODE,
-				intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A)));
-	val = REG_FIELD_PREP(IREF_RCAL_ORD, grccode);
-	intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD,
-		     val | IREF_RCAL_ORD_EN);
-
-	grccode = REG_FIELD_GET(GRCCODE_LDO,
-				intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A)));
-	val = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode);
-	intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV,
-		     val | RCOMPCODEOVEN_LDO_SYNC);
-}
-
 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 {
 	enum phy phy;
@@ -460,11 +415,6 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
 		val |= CL_POWER_DOWN_ENABLE;
 		intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
-
-		if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) &&
-		    phy == PHY_B)
-			/* Wa_14011224835:rkl[a0..b0] */
-			rkl_combo_phy_b_init_wa(dev_priv);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5eae593ee784fe03dd0f620c59002e2b08a48bd4..2b403df03404f5cda376afabbdcb7ca93e1775f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1911,16 +1911,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
 #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
-#define   COMP_INIT			REG_BIT(31)
-#define   GRCCODE_LDO			REG_GENMASK(7, 0)
+#define   COMP_INIT			(1 << 31)
 
 #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
 #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
 
-#define ICL_PORT_COMP_DW2(phy)		_MMIO(_ICL_PORT_COMP_DW(2, phy))
-#define   IREF_RCAL_ORD_EN		REG_BIT(7)
-#define   IREF_RCAL_ORD			REG_GENMASK(6, 0)
-
 #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
 #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
 #define   PROCESS_INFO_DOT_0		(0 << 26)
@@ -1933,12 +1928,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   VOLTAGE_INFO_1_05V		(2 << 24)
 #define   VOLTAGE_INFO_MASK		(3 << 24)
 #define   VOLTAGE_INFO_SHIFT		24
-#define   FIRST_COMP_DONE		REG_BIT(22)
-
-#define ICL_PORT_COMP_DW6(phy)		_MMIO(_ICL_PORT_COMP_DW(6, phy))
-#define   GRCCODE			REG_GENMASK(30, 24)
-#define   RCOMPCODEOVEN_LDO_SYNC	REG_BIT(23)
-#define   RCOMPCODE_LD_CAP_OV		REG_GENMASK(22, 16)
 
 #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
 #define   IREFGEN			(1 << 24)