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323dcac5
编写于
6月 23, 2011
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau: rename nv40_mpeg to nv31_mpeg
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
9698b9a6
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
29 addition
and
29 deletion
+29
-29
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/Makefile
+1
-1
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_drv.h
+2
-2
drivers/gpu/drm/nouveau/nouveau_state.c
drivers/gpu/drm/nouveau/nouveau_state.c
+1
-1
drivers/gpu/drm/nouveau/nv31_mpeg.c
drivers/gpu/drm/nouveau/nv31_mpeg.c
+25
-25
未找到文件。
drivers/gpu/drm/nouveau/Makefile
浏览文件 @
323dcac5
...
...
@@ -21,7 +21,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
nv40_grctx.o nv50_grctx.o nvc0_grctx.o
\
nv84_crypt.o
\
nva3_copy.o nvc0_copy.o
\
nv
40
_mpeg.o nv50_mpeg.o
\
nv
31
_mpeg.o nv50_mpeg.o
\
nv04_instmem.o nv50_instmem.o nvc0_instmem.o
\
nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o
\
nv50_cursor.o nv50_display.o
\
...
...
drivers/gpu/drm/nouveau/nouveau_drv.h
浏览文件 @
323dcac5
...
...
@@ -1195,8 +1195,8 @@ extern int nva3_copy_create(struct drm_device *dev);
/* nvc0_copy.c */
extern
int
nvc0_copy_create
(
struct
drm_device
*
dev
,
int
engine
);
/* nv
40
_mpeg.c */
extern
int
nv
40
_mpeg_create
(
struct
drm_device
*
dev
);
/* nv
31
_mpeg.c */
extern
int
nv
31
_mpeg_create
(
struct
drm_device
*
dev
);
/* nv50_mpeg.c */
extern
int
nv50_mpeg_create
(
struct
drm_device
*
dev
);
...
...
drivers/gpu/drm/nouveau/nouveau_state.c
浏览文件 @
323dcac5
...
...
@@ -634,7 +634,7 @@ nouveau_card_init(struct drm_device *dev)
}
if
(
dev_priv
->
card_type
==
NV_40
)
nv
40
_mpeg_create
(
dev
);
nv
31
_mpeg_create
(
dev
);
else
if
(
dev_priv
->
card_type
==
NV_50
&&
(
dev_priv
->
chipset
<
0x98
||
dev_priv
->
chipset
==
0xa0
))
...
...
drivers/gpu/drm/nouveau/nv
40
_mpeg.c
→
drivers/gpu/drm/nouveau/nv
31
_mpeg.c
浏览文件 @
323dcac5
...
...
@@ -26,7 +26,7 @@
#include "nouveau_drv.h"
#include "nouveau_ramht.h"
struct
nv
40
_mpeg_engine
{
struct
nv
31
_mpeg_engine
{
struct
nouveau_exec_engine
base
;
};
...
...
@@ -81,7 +81,7 @@ nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
}
static
int
nv
40
_mpeg_object_new
(
struct
nouveau_channel
*
chan
,
int
engine
,
nv
31
_mpeg_object_new
(
struct
nouveau_channel
*
chan
,
int
engine
,
u32
handle
,
u16
class
)
{
struct
drm_device
*
dev
=
chan
->
dev
;
...
...
@@ -103,10 +103,10 @@ nv40_mpeg_object_new(struct nouveau_channel *chan, int engine,
}
static
int
nv
40
_mpeg_init
(
struct
drm_device
*
dev
,
int
engine
)
nv
31
_mpeg_init
(
struct
drm_device
*
dev
,
int
engine
)
{
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
struct
nv
40
_mpeg_engine
*
pmpeg
=
nv_engine
(
dev
,
engine
);
struct
nv
31
_mpeg_engine
*
pmpeg
=
nv_engine
(
dev
,
engine
);
int
i
;
/* VPE init */
...
...
@@ -137,7 +137,7 @@ nv40_mpeg_init(struct drm_device *dev, int engine)
}
static
int
nv
40
_mpeg_fini
(
struct
drm_device
*
dev
,
int
engine
,
bool
suspend
)
nv
31
_mpeg_fini
(
struct
drm_device
*
dev
,
int
engine
,
bool
suspend
)
{
/*XXX: context save? */
nv_mask
(
dev
,
0x00b32c
,
0x00000001
,
0x00000000
);
...
...
@@ -146,7 +146,7 @@ nv40_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
}
static
int
nv
40
_mpeg_mthd_dma
(
struct
nouveau_channel
*
chan
,
u32
class
,
u32
mthd
,
u32
data
)
nv
31
_mpeg_mthd_dma
(
struct
nouveau_channel
*
chan
,
u32
class
,
u32
mthd
,
u32
data
)
{
struct
drm_device
*
dev
=
chan
->
dev
;
u32
inst
=
data
<<
4
;
...
...
@@ -184,7 +184,7 @@ nv40_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
}
static
int
nv
40
_mpeg_isr_chid
(
struct
drm_device
*
dev
,
u32
inst
)
nv
31
_mpeg_isr_chid
(
struct
drm_device
*
dev
,
u32
inst
)
{
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
struct
nouveau_gpuobj
*
ctx
;
...
...
@@ -205,7 +205,7 @@ nv40_mpeg_isr_chid(struct drm_device *dev, u32 inst)
}
static
void
nv
40
_vpe_set_tile_region
(
struct
drm_device
*
dev
,
int
i
)
nv
31
_vpe_set_tile_region
(
struct
drm_device
*
dev
,
int
i
)
{
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
struct
nouveau_tile_reg
*
tile
=
&
dev_priv
->
tile
.
reg
[
i
];
...
...
@@ -216,10 +216,10 @@ nv40_vpe_set_tile_region(struct drm_device *dev, int i)
}
static
void
nv
40
_mpeg_isr
(
struct
drm_device
*
dev
)
nv
31
_mpeg_isr
(
struct
drm_device
*
dev
)
{
u32
inst
=
(
nv_rd32
(
dev
,
0x00b318
)
&
0x000fffff
)
<<
4
;
u32
chid
=
nv
40
_mpeg_isr_chid
(
dev
,
inst
);
u32
chid
=
nv
31
_mpeg_isr_chid
(
dev
,
inst
);
u32
stat
=
nv_rd32
(
dev
,
0x00b100
);
u32
type
=
nv_rd32
(
dev
,
0x00b230
);
u32
mthd
=
nv_rd32
(
dev
,
0x00b234
);
...
...
@@ -249,10 +249,10 @@ nv40_mpeg_isr(struct drm_device *dev)
}
static
void
nv
40
_vpe_isr
(
struct
drm_device
*
dev
)
nv
31
_vpe_isr
(
struct
drm_device
*
dev
)
{
if
(
nv_rd32
(
dev
,
0x00b100
))
nv
40
_mpeg_isr
(
dev
);
nv
31
_mpeg_isr
(
dev
);
if
(
nv_rd32
(
dev
,
0x00b800
))
{
u32
stat
=
nv_rd32
(
dev
,
0x00b800
);
...
...
@@ -262,9 +262,9 @@ nv40_vpe_isr(struct drm_device *dev)
}
static
void
nv
40
_mpeg_destroy
(
struct
drm_device
*
dev
,
int
engine
)
nv
31
_mpeg_destroy
(
struct
drm_device
*
dev
,
int
engine
)
{
struct
nv
40
_mpeg_engine
*
pmpeg
=
nv_engine
(
dev
,
engine
);
struct
nv
31
_mpeg_engine
*
pmpeg
=
nv_engine
(
dev
,
engine
);
nouveau_irq_unregister
(
dev
,
0
);
...
...
@@ -273,34 +273,34 @@ nv40_mpeg_destroy(struct drm_device *dev, int engine)
}
int
nv
40
_mpeg_create
(
struct
drm_device
*
dev
)
nv
31
_mpeg_create
(
struct
drm_device
*
dev
)
{
struct
nv
40
_mpeg_engine
*
pmpeg
;
struct
nv
31
_mpeg_engine
*
pmpeg
;
pmpeg
=
kzalloc
(
sizeof
(
*
pmpeg
),
GFP_KERNEL
);
if
(
!
pmpeg
)
return
-
ENOMEM
;
pmpeg
->
base
.
destroy
=
nv
40
_mpeg_destroy
;
pmpeg
->
base
.
init
=
nv
40
_mpeg_init
;
pmpeg
->
base
.
fini
=
nv
40
_mpeg_fini
;
pmpeg
->
base
.
destroy
=
nv
31
_mpeg_destroy
;
pmpeg
->
base
.
init
=
nv
31
_mpeg_init
;
pmpeg
->
base
.
fini
=
nv
31
_mpeg_fini
;
pmpeg
->
base
.
context_new
=
nv40_mpeg_context_new
;
pmpeg
->
base
.
context_del
=
nv40_mpeg_context_del
;
pmpeg
->
base
.
object_new
=
nv
40
_mpeg_object_new
;
pmpeg
->
base
.
object_new
=
nv
31
_mpeg_object_new
;
/* ISR vector, PMC_ENABLE bit, and TILE regs are shared between
* all VPE engines, for this driver's purposes the PMPEG engine
* will be treated as the "master" and handle the global VPE
* bits too
*/
pmpeg
->
base
.
set_tile_region
=
nv
40
_vpe_set_tile_region
;
nouveau_irq_register
(
dev
,
0
,
nv
40
_vpe_isr
);
pmpeg
->
base
.
set_tile_region
=
nv
31
_vpe_set_tile_region
;
nouveau_irq_register
(
dev
,
0
,
nv
31
_vpe_isr
);
NVOBJ_ENGINE_ADD
(
dev
,
MPEG
,
&
pmpeg
->
base
);
NVOBJ_CLASS
(
dev
,
0x3174
,
MPEG
);
NVOBJ_MTHD
(
dev
,
0x3174
,
0x0190
,
nv
40
_mpeg_mthd_dma
);
NVOBJ_MTHD
(
dev
,
0x3174
,
0x01a0
,
nv
40
_mpeg_mthd_dma
);
NVOBJ_MTHD
(
dev
,
0x3174
,
0x01b0
,
nv
40
_mpeg_mthd_dma
);
NVOBJ_MTHD
(
dev
,
0x3174
,
0x0190
,
nv
31
_mpeg_mthd_dma
);
NVOBJ_MTHD
(
dev
,
0x3174
,
0x01a0
,
nv
31
_mpeg_mthd_dma
);
NVOBJ_MTHD
(
dev
,
0x3174
,
0x01b0
,
nv
31
_mpeg_mthd_dma
);
#if 0
NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
...
...
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