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02cf2119
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02cf2119
编写于
10月 01, 2005
作者:
R
Ralf Baechle
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Cleanup the mess in cpu_cache_init.
Signed-off-by:
N
Ralf Baechle
<
ralf@linux-mips.org
>
上级
942d042d
变更
12
显示空白变更内容
内联
并排
Showing
12 changed file
with
102 addition
and
88 deletion
+102
-88
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/cpu-probe.c
+18
-7
arch/mips/mm/c-r3k.c
arch/mips/mm/c-r3k.c
+1
-1
arch/mips/mm/c-r4k.c
arch/mips/mm/c-r4k.c
+1
-1
arch/mips/mm/c-sb1.c
arch/mips/mm/c-sb1.c
+1
-1
arch/mips/mm/c-tx39.c
arch/mips/mm/c-tx39.c
+1
-1
arch/mips/mm/cache.c
arch/mips/mm/cache.c
+40
-50
include/asm-mips/cpu-features.h
include/asm-mips/cpu-features.h
+13
-2
include/asm-mips/cpu.h
include/asm-mips/cpu.h
+21
-19
include/asm-mips/mach-ip22/cpu-feature-overrides.h
include/asm-mips/mach-ip22/cpu-feature-overrides.h
+1
-1
include/asm-mips/mach-mips/cpu-feature-overrides.h
include/asm-mips/mach-mips/cpu-feature-overrides.h
+2
-2
include/asm-mips/mach-rm200/cpu-feature-overrides.h
include/asm-mips/mach-rm200/cpu-feature-overrides.h
+1
-1
include/asm-mips/mach-sim/cpu-feature-overrides.h
include/asm-mips/mach-sim/cpu-feature-overrides.h
+2
-2
未找到文件。
arch/mips/kernel/cpu-probe.c
浏览文件 @
02cf2119
...
@@ -191,7 +191,7 @@ static inline int __cpu_has_fpu(void)
...
@@ -191,7 +191,7 @@ static inline int __cpu_has_fpu(void)
return
((
cpu_get_fpu_id
()
&
0xff00
)
!=
FPIR_IMP_NONE
);
return
((
cpu_get_fpu_id
()
&
0xff00
)
!=
FPIR_IMP_NONE
);
}
}
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K
TLB
\
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K
_CACHE
\
| MIPS_CPU_COUNTER)
| MIPS_CPU_COUNTER)
static
inline
void
cpu_probe_legacy
(
struct
cpuinfo_mips
*
c
)
static
inline
void
cpu_probe_legacy
(
struct
cpuinfo_mips
*
c
)
...
@@ -200,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
...
@@ -200,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
case
PRID_IMP_R2000
:
case
PRID_IMP_R2000
:
c
->
cputype
=
CPU_R2000
;
c
->
cputype
=
CPU_R2000
;
c
->
isa_level
=
MIPS_CPU_ISA_I
;
c
->
isa_level
=
MIPS_CPU_ISA_I
;
c
->
options
=
MIPS_CPU_TLB
|
MIPS_CPU_NOFPUEX
;
c
->
options
=
MIPS_CPU_TLB
|
MIPS_CPU_3K_CACHE
|
MIPS_CPU_NOFPUEX
;
if
(
__cpu_has_fpu
())
if
(
__cpu_has_fpu
())
c
->
options
|=
MIPS_CPU_FPU
;
c
->
options
|=
MIPS_CPU_FPU
;
c
->
tlbsize
=
64
;
c
->
tlbsize
=
64
;
...
@@ -214,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
...
@@ -214,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
else
else
c
->
cputype
=
CPU_R3000
;
c
->
cputype
=
CPU_R3000
;
c
->
isa_level
=
MIPS_CPU_ISA_I
;
c
->
isa_level
=
MIPS_CPU_ISA_I
;
c
->
options
=
MIPS_CPU_TLB
|
MIPS_CPU_NOFPUEX
;
c
->
options
=
MIPS_CPU_TLB
|
MIPS_CPU_3K_CACHE
|
MIPS_CPU_NOFPUEX
;
if
(
__cpu_has_fpu
())
if
(
__cpu_has_fpu
())
c
->
options
|=
MIPS_CPU_FPU
;
c
->
options
|=
MIPS_CPU_FPU
;
c
->
tlbsize
=
64
;
c
->
tlbsize
=
64
;
...
@@ -297,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
...
@@ -297,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
#endif
#endif
case
PRID_IMP_TX39
:
case
PRID_IMP_TX39
:
c
->
isa_level
=
MIPS_CPU_ISA_I
;
c
->
isa_level
=
MIPS_CPU_ISA_I
;
c
->
options
=
MIPS_CPU_TLB
;
c
->
options
=
MIPS_CPU_TLB
|
MIPS_CPU_TX39_CACHE
;
if
((
c
->
processor_id
&
0xf0
)
==
(
PRID_REV_TX3927
&
0xf0
))
{
if
((
c
->
processor_id
&
0xf0
)
==
(
PRID_REV_TX3927
&
0xf0
))
{
c
->
cputype
=
CPU_TX3927
;
c
->
cputype
=
CPU_TX3927
;
...
@@ -441,7 +443,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
...
@@ -441,7 +443,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
config0
=
read_c0_config
();
config0
=
read_c0_config
();
if
(((
config0
&
MIPS_CONF_MT
)
>>
7
)
==
1
)
if
(((
config0
&
MIPS_CONF_MT
)
>>
7
)
==
1
)
c
->
options
|=
MIPS_CPU_TLB
|
MIPS_CPU_4KTLB
;
c
->
options
|=
MIPS_CPU_TLB
;
isa
=
(
config0
&
MIPS_CONF_AT
)
>>
13
;
isa
=
(
config0
&
MIPS_CONF_AT
)
>>
13
;
switch
(
isa
)
{
switch
(
isa
)
{
case
0
:
case
0
:
...
@@ -516,8 +518,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
...
@@ -516,8 +518,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
static
inline
void
decode_configs
(
struct
cpuinfo_mips
*
c
)
static
inline
void
decode_configs
(
struct
cpuinfo_mips
*
c
)
{
{
/* MIPS32 or MIPS64 compliant CPU. */
/* MIPS32 or MIPS64 compliant CPU. */
c
->
options
=
MIPS_CPU_4KEX
|
MIPS_CPU_
COUNTER
|
MIPS_CPU_DIVEC
|
c
->
options
=
MIPS_CPU_4KEX
|
MIPS_CPU_
4K_CACHE
|
MIPS_CPU_COUNTER
|
MIPS_CPU_LLSC
|
MIPS_CPU_MCHECK
;
MIPS_CPU_DIVEC
|
MIPS_CPU_LLSC
|
MIPS_CPU_MCHECK
;
c
->
scache
.
flags
=
MIPS_CACHE_NOT_PRESENT
;
c
->
scache
.
flags
=
MIPS_CACHE_NOT_PRESENT
;
...
@@ -603,6 +605,15 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
...
@@ -603,6 +605,15 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
static
inline
void
cpu_probe_sibyte
(
struct
cpuinfo_mips
*
c
)
static
inline
void
cpu_probe_sibyte
(
struct
cpuinfo_mips
*
c
)
{
{
decode_configs
(
c
);
decode_configs
(
c
);
/*
* For historical reasons the SB1 comes with it's own variant of
* cache code which eventually will be folded into c-r4k.c. Until
* then we pretend it's got it's own cache architecture.
*/
c
->
options
&=
MIPS_CPU_4K_CACHE
;
c
->
options
|=
MIPS_CPU_SB1_CACHE
;
switch
(
c
->
processor_id
&
0xff00
)
{
switch
(
c
->
processor_id
&
0xff00
)
{
case
PRID_IMP_SB1
:
case
PRID_IMP_SB1
:
c
->
cputype
=
CPU_SB1
;
c
->
cputype
=
CPU_SB1
;
...
...
arch/mips/mm/c-r3k.c
浏览文件 @
02cf2119
...
@@ -319,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
...
@@ -319,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
r3k_flush_dcache_range
(
start
,
start
+
size
);
r3k_flush_dcache_range
(
start
,
start
+
size
);
}
}
void
__init
ld_mmu_r23000
(
void
)
void
__init
r3k_cache_init
(
void
)
{
{
extern
void
build_clear_page
(
void
);
extern
void
build_clear_page
(
void
);
extern
void
build_copy_page
(
void
);
extern
void
build_copy_page
(
void
);
...
...
arch/mips/mm/c-r4k.c
浏览文件 @
02cf2119
...
@@ -1221,7 +1221,7 @@ static inline void coherency_setup(void)
...
@@ -1221,7 +1221,7 @@ static inline void coherency_setup(void)
}
}
}
}
void
__init
ld_mmu_r4xx0
(
void
)
void
__init
r4k_cache_init
(
void
)
{
{
extern
void
build_clear_page
(
void
);
extern
void
build_clear_page
(
void
);
extern
void
build_copy_page
(
void
);
extern
void
build_copy_page
(
void
);
...
...
arch/mips/mm/c-sb1.c
浏览文件 @
02cf2119
...
@@ -496,7 +496,7 @@ static __init void probe_cache_sizes(void)
...
@@ -496,7 +496,7 @@ static __init void probe_cache_sizes(void)
* memory management function pointers, as well as initialize
* memory management function pointers, as well as initialize
* the caches and tlbs
* the caches and tlbs
*/
*/
void
ld_mmu_sb1
(
void
)
void
sb1_cache_init
(
void
)
{
{
extern
char
except_vec2_sb1
;
extern
char
except_vec2_sb1
;
extern
char
handle_vec2_sb1
;
extern
char
handle_vec2_sb1
;
...
...
arch/mips/mm/c-tx39.c
浏览文件 @
02cf2119
...
@@ -410,7 +410,7 @@ static __init void tx39_probe_cache(void)
...
@@ -410,7 +410,7 @@ static __init void tx39_probe_cache(void)
}
}
}
}
void
__init
ld_mmu_tx39
(
void
)
void
__init
tx39_cache_init
(
void
)
{
{
extern
void
build_clear_page
(
void
);
extern
void
build_clear_page
(
void
);
extern
void
build_copy_page
(
void
);
extern
void
build_copy_page
(
void
);
...
...
arch/mips/mm/cache.c
浏览文件 @
02cf2119
...
@@ -104,58 +104,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
...
@@ -104,58 +104,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
}
}
}
}
extern
void
ld_mmu_r23000
(
void
);
#define __weak __attribute__((weak))
extern
void
ld_mmu_r4xx0
(
void
);
extern
void
ld_mmu_tx39
(
void
);
static
char
cache_panic
[]
__initdata
=
"Yeee, unsupported cache architecture."
;
extern
void
ld_mmu_r6000
(
void
);
extern
void
ld_mmu_tfp
(
void
);
extern
void
ld_mmu_andes
(
void
);
extern
void
ld_mmu_sb1
(
void
);
void
__init
cpu_cache_init
(
void
)
void
__init
cpu_cache_init
(
void
)
{
{
if
(
cpu_has_4ktlb
)
{
if
(
cpu_has_3k_cache
)
{
#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
extern
void
__weak
r3k_cache_init
(
void
);
defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
r3k_cache_init
();
defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \
return
;
defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \
}
defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
if
(
cpu_has_6k_cache
)
{
ld_mmu_r4xx0
();
extern
void
__weak
r6k_cache_init
(
void
);
#endif
}
else
switch
(
current_cpu_data
.
cputype
)
{
r6k_cache_init
();
#ifdef CONFIG_CPU_R3000
return
;
case
CPU_R2000
:
case
CPU_R3000
:
case
CPU_R3000A
:
case
CPU_R3081E
:
ld_mmu_r23000
();
break
;
#endif
#ifdef CONFIG_CPU_TX39XX
case
CPU_TX3912
:
case
CPU_TX3922
:
case
CPU_TX3927
:
ld_mmu_tx39
();
break
;
#endif
#ifdef CONFIG_CPU_R10000
case
CPU_R10000
:
case
CPU_R12000
:
ld_mmu_r4xx0
();
break
;
#endif
#ifdef CONFIG_CPU_SB1
case
CPU_SB1
:
ld_mmu_sb1
();
break
;
#endif
case
CPU_R8000
:
panic
(
"R8000 is unsupported"
);
break
;
default:
panic
(
"Yeee, unsupported cache architecture."
);
}
}
if
(
cpu_has_4k_cache
)
{
extern
void
__weak
r4k_cache_init
(
void
);
r4k_cache_init
();
return
;
}
if
(
cpu_has_8k_cache
)
{
extern
void
__weak
r8k_cache_init
(
void
);
r8k_cache_init
();
return
;
}
if
(
cpu_has_tx39_cache
)
{
extern
void
__weak
tx39_cache_init
(
void
);
tx39_cache_init
();
return
;
}
if
(
cpu_has_sb1_cache
)
{
extern
void
__weak
sb1_cache_init
(
void
);
sb1_cache_init
();
return
;
}
panic
(
cache_panic
);
}
}
include/asm-mips/cpu-features.h
浏览文件 @
02cf2119
...
@@ -25,8 +25,19 @@
...
@@ -25,8 +25,19 @@
#ifndef cpu_has_4kex
#ifndef cpu_has_4kex
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#endif
#ifndef cpu_has_4ktlb
#ifndef cpu_has_3k_cache
#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_sb1_cache
#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
#endif
#endif
#ifndef cpu_has_fpu
#ifndef cpu_has_fpu
#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
...
...
include/asm-mips/cpu.h
浏览文件 @
02cf2119
...
@@ -217,25 +217,27 @@
...
@@ -217,25 +217,27 @@
* CPU Option encodings
* CPU Option encodings
*/
*/
#define MIPS_CPU_TLB 0x00000001
/* CPU has TLB */
#define MIPS_CPU_TLB 0x00000001
/* CPU has TLB */
/* Leave a spare bit for variant MMU types... */
#define MIPS_CPU_4KEX 0x00000002
/* "R4K" exception model */
#define MIPS_CPU_4KEX 0x00000004
/* "R4K" exception model */
#define MIPS_CPU_3K_CACHE 0x00000004
/* R3000-style caches */
#define MIPS_CPU_4KTLB 0x00000008
/* "R4K" TLB handler */
#define MIPS_CPU_4K_CACHE 0x00000008
/* R4000-style caches */
#define MIPS_CPU_FPU 0x00000010
/* CPU has FPU */
#define MIPS_CPU_TX39_CACHE 0x00000010
/* TX3900-style caches */
#define MIPS_CPU_32FPR 0x00000020
/* 32 dbl. prec. FP registers */
#define MIPS_CPU_SB1_CACHE 0x00000020
/* SB1-style caches */
#define MIPS_CPU_COUNTER 0x00000040
/* Cycle count/compare */
#define MIPS_CPU_FPU 0x00000040
/* CPU has FPU */
#define MIPS_CPU_WATCH 0x00000080
/* watchpoint registers */
#define MIPS_CPU_32FPR 0x00000080
/* 32 dbl. prec. FP registers */
#define MIPS_CPU_DIVEC 0x00000200
/* dedicated interrupt vector */
#define MIPS_CPU_COUNTER 0x00000100
/* Cycle count/compare */
#define MIPS_CPU_VCE 0x00000400
/* virt. coherence conflict possible */
#define MIPS_CPU_WATCH 0x00000200
/* watchpoint registers */
#define MIPS_CPU_CACHE_CDEX_P 0x00000800
/* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_DIVEC 0x00000400
/* dedicated interrupt vector */
#define MIPS_CPU_CACHE_CDEX_S 0x00001000
/* ... same for seconary cache ... */
#define MIPS_CPU_VCE 0x00000800
/* virt. coherence conflict possible */
#define MIPS_CPU_MCHECK 0x00002000
/* Machine check exception */
#define MIPS_CPU_CACHE_CDEX_P 0x00001000
/* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_EJTAG 0x00004000
/* EJTAG exception */
#define MIPS_CPU_CACHE_CDEX_S 0x00002000
/* ... same for seconary cache ... */
#define MIPS_CPU_NOFPUEX 0x00008000
/* no FPU exception */
#define MIPS_CPU_MCHECK 0x00004000
/* Machine check exception */
#define MIPS_CPU_LLSC 0x00010000
/* CPU has ll/sc instructions */
#define MIPS_CPU_EJTAG 0x00008000
/* EJTAG exception */
#define MIPS_CPU_SUBSET_CACHES 0x00020000
/* P-cache subset enforced */
#define MIPS_CPU_NOFPUEX 0x00010000
/* no FPU exception */
#define MIPS_CPU_PREFETCH 0x00040000
/* CPU has usable prefetch */
#define MIPS_CPU_LLSC 0x00020000
/* CPU has ll/sc instructions */
#define MIPS_CPU_VINT 0x00080000
/* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_SUBSET_CACHES 0x00040000
/* P-cache subset enforced */
#define MIPS_CPU_VEIC 0x00100000
/* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_PREFETCH 0x00080000
/* CPU has usable prefetch */
#define MIPS_CPU_VINT 0x00100000
/* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00200000
/* CPU supports MIPSR2 external interrupt controller mode */
/*
/*
* CPU ASE encodings
* CPU ASE encodings
...
...
include/asm-mips/mach-ip22/cpu-feature-overrides.h
浏览文件 @
02cf2119
...
@@ -13,7 +13,7 @@
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@@ -13,7 +13,7 @@
*/
*/
#define cpu_has_tlb 1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kex 1
#define cpu_has_4k
tlb
1
#define cpu_has_4k
cache
1
#define cpu_has_fpu 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
#define cpu_has_counter 1
...
...
include/asm-mips/mach-mips/cpu-feature-overrides.h
浏览文件 @
02cf2119
...
@@ -17,7 +17,7 @@
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@@ -17,7 +17,7 @@
#ifdef CONFIG_CPU_MIPS32_R1
#ifdef CONFIG_CPU_MIPS32_R1
#define cpu_has_tlb 1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kex 1
#define cpu_has_4k
tlb
1
#define cpu_has_4k
cache
1
/* #define cpu_has_fpu ? */
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
#define cpu_has_counter 1
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@@ -43,7 +43,7 @@
...
@@ -43,7 +43,7 @@
#ifdef CONFIG_CPU_MIPS64_R1
#ifdef CONFIG_CPU_MIPS64_R1
#define cpu_has_tlb 1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kex 1
#define cpu_has_4k
tlb
1
#define cpu_has_4k
cache
1
/* #define cpu_has_fpu ? */
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
#define cpu_has_counter 1
...
...
include/asm-mips/mach-rm200/cpu-feature-overrides.h
浏览文件 @
02cf2119
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
#define cpu_has_tlb 1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kex 1
#define cpu_has_4k
tlb
1
#define cpu_has_4k
cache
1
#define cpu_has_fpu 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
#define cpu_has_counter 1
...
...
include/asm-mips/mach-sim/cpu-feature-overrides.h
浏览文件 @
02cf2119
...
@@ -16,7 +16,7 @@
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@@ -16,7 +16,7 @@
#ifdef CONFIG_CPU_MIPS32
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kex 1
#define cpu_has_4k
tlb
1
#define cpu_has_4k
cache
1
#define cpu_has_fpu 0
#define cpu_has_fpu 0
/* #define cpu_has_32fpr ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
#define cpu_has_counter 1
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@@ -41,7 +41,7 @@
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@@ -41,7 +41,7 @@
#ifdef CONFIG_CPU_MIPS64
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kex 1
#define cpu_has_4k
tlb
1
#define cpu_has_4k
cache
1
/* #define cpu_has_fpu ? */
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
#define cpu_has_counter 1
...
...
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