• M
    MIPS: mm: page: Add MIPS R6 support · d2e6d30a
    Markos Chandras 提交于
    The MIPS R6 pref instruction only has 9 bits for the immediate
    field so skip the micro-assembler PREF instruction if the offset
    does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is
    no longer valid in MIPS R6, so we change the default for all MIPS R6
    processors to bit 5 (Pref_StoreStreamed).
    Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
    d2e6d30a
page.c 18.9 KB