diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36.h new file mode 100644 index 0000000000000000000000000000000000000000..f9d299eb552f98a93ed66ff6470802e826ffdf09 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36.h @@ -0,0 +1,62734 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b220118 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S36 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-04-12) +** Initial version based on RM DraftF +** - rev. 1.1 (2021-08-04) +** Initial version based on RM DraftG +** +** ################################################################### +*/ + +/*! + * @file LPC55S36.h + * @version 1.1 + * @date 2021-08-04 + * @brief CMSIS Peripheral Access Layer for LPC55S36 + * + * CMSIS Peripheral Access Layer for LPC55S36 + */ + +#ifndef _LPC55S36_H_ +#define _LPC55S36_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 136 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + ADC1_IRQn = 23, /**< ADC1 */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + DMIC_IRQn = 25, /**< Digital microphone and DMIC subsystem */ + HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + EZH_ARCH_B0_IRQn = 30, /**< EZH interrupt */ + WAKEUP_IRQn = 31, /**< Wakeup interrupt */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + FlexSPI0_IRQn = 39, /**< FlexSPI interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + Reserved58_IRQn = 42, /**< Reserved interrupt */ + CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ + CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ + SPI_FILTER_IRQn = 45, /**< SPI Filter interrupt */ + Reserved62_IRQn = 46, /**< Reserved interrupt */ + Reserved63_IRQn = 47, /**< Reserved interrupt */ + Reserved64_IRQn = 48, /**< Reserved interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT00 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT01 interrupt */ + Freqme_IRQn = 52, /**< frequency measure interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + CSS_IRQn = 54, /**< SHA interrupt */ + PKC_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + POWERQUAD_IRQn = 57, /**< PowerQuad interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59, /**< LSPI_HS interrupt */ + CDOG_IRQn = 60, /**< CodeWDG interrupt */ + Reserved77_IRQn = 61, /**< Reserved interrupt */ + I3C0_IRQn = 62, /**< I3C interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + CSS_IRQ1_IRQn = 65, /**< CSS_IRQ1 */ + Tamper_IRQn = 66, /**< Tamper */ + Reserved83_IRQn = 67, /**< Reserved interrupt */ + Reserved84_IRQn = 68, /**< Reserved interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Reserved87_IRQn = 71, /**< Reserved interrupt */ + Reserved88_IRQn = 72, /**< Reserved interrupt */ + Reserved89_IRQn = 73, /**< Reserved interrupt */ + DAC0_IRQn = 74, /**< dac0 interrupt */ + DAC1_IRQn = 75, /**< dac1 interrupt */ + DAC2_IRQn = 76, /**< dac2 interrupt */ + HSCMP0_IRQn = 77, /**< hscmp0 interrupt */ + HSCMP1_IRQn = 78, /**< hscmp1 interrupt */ + HSCMP2_IRQn = 79, /**< hscmp2 interrupt */ + FLEXPWM0_CAPTURE_IRQn = 80, /**< flexpwm0_capture interrupt */ + FLEXPWM0_FAULT_IRQn = 81, /**< flexpwm0_fault interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 82, /**< flexpwm0_reload_error interrupt */ + FLEXPWM0_COMPARE0_IRQn = 83, /**< flexpwm0_compare0 interrupt */ + FLEXPWM0_RELOAD0_IRQn = 84, /**< flexpwm0_reload0 interrupt */ + FLEXPWM0_COMPARE1_IRQn = 85, /**< flexpwm0_compare1 interrupt */ + FLEXPWM0_RELOAD1_IRQn = 86, /**< flexpwm0_reload1 interrupt */ + FLEXPWM0_COMPARE2_IRQn = 87, /**< flexpwm0_compare2 interrupt */ + FLEXPWM0_RELOAD2_IRQn = 88, /**< flexpwm0_reload2 interrupt */ + FLEXPWM0_COMPARE3_IRQn = 89, /**< flexpwm0_compare3 interrupt */ + FLEXPWM0_RELOAD3_IRQn = 90, /**< flexpwm0_reload3 interrupt */ + FLEXPWM1_CAPTURE_IRQn = 91, /**< flexpwm1_capture interrupt */ + FLEXPWM1_FAULT_IRQn = 92, /**< flexpwm1_fault interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 93, /**< flexpwm1_reload_error interrupt */ + FLEXPWM1_COMPARE0_IRQn = 94, /**< flexpwm1_compare0 interrupt */ + FLEXPWM1_RELOAD0_IRQn = 95, /**< flexpwm1_reload0 interrupt */ + FLEXPWM1_COMPARE1_IRQn = 96, /**< flexpwm1_compare1 interrupt */ + FLEXPWM1_RELOAD1_IRQn = 97, /**< flexpwm1_reload1 interrupt */ + FLEXPWM1_COMPARE2_IRQn = 98, /**< flexpwm1_compare2 interrupt */ + FLEXPWM1_RELOAD2_IRQn = 99, /**< flexpwm1_reload2 interrupt */ + FLEXPWM1_COMPARE3_IRQn = 100, /**< flexpwm1_compare3 interrupt */ + FLEXPWM1_RELOAD3_IRQn = 101, /**< flexpwm1_reload3 interrupt */ + ENC0_COMPARE_IRQn = 102, /**< enc0_compare interrupt */ + ENC0_HOME_IRQn = 103, /**< enc0_home interrupt */ + ENC0_WDG_IRQn = 104, /**< enc0_wdg interrupt */ + ENC0_IDX_IRQn = 105, /**< enc0_idx interrupt */ + ENC1_COMPARE_IRQn = 106, /**< enc1_compare interrupt */ + ENC1_HOME_IRQn = 107, /**< enc1_home interrupt */ + ENC1_WDG_IRQn = 108, /**< enc1_wdg interrupt */ + ENC1_IDX_IRQn = 109, /**< enc1_idx interrupt */ + ITRC0_IRQn = 110, /**< itrc0 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + CSSV2_ERR_IRQn = 112, /**< cssv2_err interrupt */ + PKC_ERR_IRQn = 113, /**< pkc_err interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved131_IRQn = 115, /**< Reserved interrupt */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + FLASH_IRQn = 118, /**< flash interrupt */ + RAM_PARITY_ECC_ERR_IRQn = 119 /**< ram_parity_ecc_err interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S36.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestFLEXSPIRX = 0U, /**< FlexSPI RX */ + kDma1RequestUnusedDMARequest0 = 0U, /**< Unused DMA request 0 */ + kDma0RequestFLEXSPITX = 1U, /**< FlexSPI TX */ + kDma1RequestUnusedDMARequest1 = 1U, /**< Unused DMA request 1 */ + kDma0RequestHSSPIRX = 2U, /**< HS_SPI RX(Flexcomm Interface 8 RX) */ + kDma1RequestHSLSPIRX = 2U, /**< High Speed SPI RX( */ + kDma0RequestHSSPITX = 3U, /**< HS_SPI TX(Flexcomm Interface 8 TX) */ + kDma1RequestHSLSPITX = 3U, /**< High Speed SPI TX( */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma1RequestDmic0Ch0 = 10U, /**< DMIC0 CH0 */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma1RequestDmic0Ch1 = 11U, /**< DMIC0 CH1 */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma1RequestI3c0Rx = 12U, /**< I3C0 RX */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma1RequestI3c0Tx = 13U, /**< I3C0 TX */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma1RequestFLEXSPIRX = 14U, /**< FlexSpi RX */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma1RequestFLEXSPITX = 15U, /**< FlexSpi TX */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestDAC0 = 20U, /**< DAC0 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ + kDma0RequestDMIC0CH0 = 23U, /**< DMIC0 channel0 */ + kDma0RequestDMIC0CH1 = 24U, /**< DMIC0 channel1 */ + kDma0RequestI3C0RX = 25U, /**< I3C0 RX */ + kDma0RequestI3C0TX = 26U, /**< I3C0 TX */ + kDma0RequestADC1FIFO0 = 27U, /**< ADC1 FIFO 0 */ + kDma0RequestADC1FIFO1 = 28U, /**< ADC1 FIFO 1 */ + kDma0RequestDAC1 = 29U, /**< DAC1 */ + kDma0RequestDAC2 = 30U, /**< DAC2 */ + kDma0RequestUnusedDMARequest31 = 31U, /**< Unused DMA request 31 */ + kDma0RequestUnusedDMARequest32 = 32U, /**< Unused DMA request 32 */ + kDma0RequestUnusedDMARequest33 = 33U, /**< Unused DMA request 33 */ + kDma0RequestUnusedDMARequest34 = 34U, /**< Unused DMA request 34 */ + kDma0RequestUnusedDMARequest35 = 35U, /**< Unused DMA request 35 */ + kDma0RequestUnassignedDMARequest36 = 36U, /**< Unassigned DMA request 36(but required for FlexPWM0_req_capt0) */ + kDma0RequestUnassignedDMARequest37 = 37U, /**< Unassigned DMA request 37(but required for FlexPWM0_req_capt1) */ + kDma0RequestUnassignedDMARequest38 = 38U, /**< Unassigned DMA request 38(but required for FlexPWM0_req_capt2) */ + kDma0RequestUnassignedDMARequest39 = 39U, /**< Unassigned DMA request 39(but required for FlexPWM0_req_capt3) */ + kDma0RequestUnassignedDMARequest40 = 40U, /**< Unassigned DMA request 40(but required for FlexPWM0_req_val0) */ + kDma0RequestUnassignedDMARequest41 = 41U, /**< Unassigned DMA request 41(but required for FlexPWM0_req_val1) */ + kDma0RequestUnassignedDMARequest42 = 42U, /**< Unassigned DMA request 42(but required for FlexPWM0_req_val2) */ + kDma0RequestUnassignedDMARequest43 = 43U, /**< Unassigned DMA request 43(but required for FlexPWM0_req_val3) */ + kDma0RequestUnassignedDMARequest44 = 44U, /**< Unassigned DMA request 44(but required for FlexPWM1_req_capt0) */ + kDma0RequestUnassignedDMARequest45 = 45U, /**< Unassigned DMA request 45(but required for FlexPWM1_req_capt1) */ + kDma0RequestUnassignedDMARequest46 = 46U, /**< Unassigned DMA request 46(but required for FlexPWM1_req_capt2) */ + kDma0RequestUnassignedDMARequest47 = 47U, /**< Unassigned DMA request 47(but required for FlexPWM1_req_capt3) */ + kDma0RequestUnassignedDMARequest48 = 48U, /**< Unassigned DMA request 48(but required for FlexPWM1_req_val0) */ + kDma0RequestUnassignedDMARequest49 = 49U, /**< Unassigned DMA request 49(but required for FlexPWM1_req_val1) */ + kDma0RequestUnassignedDMARequest50 = 50U, /**< Unassigned DMA request 50(but required for FlexPWM1_req_val2) */ + kDma0RequestUnassignedDMARequest51 = 51U, /**< Unassigned DMA request 51(but required for FlexPWM1_req_val3) */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_4[48]; + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_5[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_6[136]; + __IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_7[196]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_9[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number + */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number + */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number + */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low power mode. + * 0b1..ADC is disabled in low power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..Trigger completion interrupts are disabled. + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b0x..Low power setting. + * 0b1x..High power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay + */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay + */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0001..Trigger 0 has been interrupted by a high priority exception. + * 0b0010..Trigger 1 has been interrupted by a high priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b00..Set to highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level + * 0b11..Set to lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select + */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (4U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter + */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection + */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value + */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result + */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) + +#define ADC_CMDL_ALTB_ADCH_MASK (0x1F0000U) +#define ADC_CMDL_ALTB_ADCH_SHIFT (16U) +/*! ALTB_ADCH - Alternate Channel B Input channel select + * 0b00000..Select CH0B + * 0b00001..Select CH1B + * 0b00010..Select CH2B + * 0b00011..Select CH3B + * 0b00100-0b11101..Select corresponding channel CHnB + * 0b11110..Select CH30B + * 0b11111..Select CH31B + */ +#define ADC_CMDL_ALTB_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK) + +#define ADC_CMDL_ALTBEN_MASK (0x200000U) +#define ADC_CMDL_ALTBEN_SHIFT (21U) +/*! ALTBEN - Alternate Channel B Select Enable + * 0b0..ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH settings. + * 0b1..ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs selected by ALTB_ADCH setting. + */ +#define ADC_CMDL_ALTBEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. + * 0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. + * 0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. + * 0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. + * 0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. + * 0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. + * 0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. + */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. + */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (15U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result + */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 initiated this conversion. + * 0b01..Trigger source 1 initiated this conversion. + * 0b10-0b10..Corresponding trigger source initiated this conversion. + * 0b11..Trigger source 3 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element + */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element + */ +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x500B1000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x400B1000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x400B1000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Control and Status, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running Oscillator (FRO) Control, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running Oscillator (FRO) Status, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors & DCDC interrupt control, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupt status, offset: 0x34 */ + uint8_t RESERVED_3[120]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + uint8_t RESERVED_4[60]; + __IO uint32_t OSC_TESTBUS; /**< Oscillators Analog Macrobloc ACBUS and DCBUS control, offset: 0xF0 */ + uint8_t RESERVED_5[4]; + __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Control and Status */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status + * 0b0..Not in power down mode. + * 0b1..In power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status + * 0b0..No error + * 0b1..At least one error occurred + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_MASK (0x10000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_SHIFT (16U) +/*! FLASH_ECC_ERROR_FLAG - Flash ECC Error Flag + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running Oscillator (FRO) Control */ +/*! @{ */ + +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..Disable the 12 MHz clock. + * 0b1..Enable the 12 MHz clock. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_FREQ_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_FREQ_TRIM_SHIFT (16U) +/*! FREQ_TRIM - Frequency trim. + */ +#define ANACTRL_FRO192M_CTRL_FREQ_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_FREQ_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_FREQ_TRIM_MASK) + +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If USBCLKADJ bit is set and the USB peripheral is enabled for full speed device + * mode, the USB block will provide FRO clock adjustments to synchronize the frequency to the host + * clock using the SOF packets. + */ +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - USBCLKADJ mode trim change + */ +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control + * 0b0..Disable the 96 MHz clock. + * 0b1..Enable the 96 MHz clock. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + */ +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running Oscillator (FRO) Status */ +/*! @{ */ + +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid. + * 0b0..No output clock available + * 0b1..Output clock is available + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). + */ +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ + +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ +/*! @{ */ + +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - XO in slave mode. + */ +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Allows XO32M to be configured in bypass mode. + * 0b0..XO bypass is disabled. + * 0b1..XO bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..Disable the oscillator. + * 0b1..Enable the oscillator. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status */ +/*! @{ */ + +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Crystal Oscillator Ready + * 0b0..Frequency is not yet stable. + * 0b1..Frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors & DCDC interrupt control */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_SHIFT (0U) +/*! BODVDDMAIN_INT_ENABLE - BOD VDDMAIN interrupt control. + * 0b0..Disable the interrupt. + * 0b1..Enable the interrupt. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_SHIFT (1U) +/*! BODVDDMAIN_INT_CLEAR - BOD VDDMAIN interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..Disable the interrupt. + * 0b1..Enable the interrupt. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..Disable the interrupt. + * 0b1..Enable the interrupt. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupt status */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_SHIFT (0U) +/*! BODVDDMAIN_STATUS - BOD VDDMAIN Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_SHIFT (1U) +/*! BODVDDMAIN_INT_STATUS - BOD VDDMAIN Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_SHIFT (2U) +/*! BODVDDMAIN_VAL - BOD VDDMAIN power status + * 0b0..Below the threshold. + * 0b1..Above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - BOD CORE power status + * 0b0..Below the threshold. + * 0b1..Above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - DCDC power status + * 0b0..Below the target. + * 0b1..Above the target. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ + +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. + */ +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. + */ +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name OSC_TESTBUS - Oscillators Analog Macrobloc ACBUS and DCBUS control */ +/*! @{ */ + +#define ANACTRL_OSC_TESTBUS_ACBUS_MASK (0x3FU) +#define ANACTRL_OSC_TESTBUS_ACBUS_SHIFT (0U) +/*! ACBUS - Alternate current BUS + */ +#define ANACTRL_OSC_TESTBUS_ACBUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_OSC_TESTBUS_ACBUS_SHIFT)) & ANACTRL_OSC_TESTBUS_ACBUS_MASK) + +#define ANACTRL_OSC_TESTBUS_DCBUS_MASK (0x3F0000U) +#define ANACTRL_OSC_TESTBUS_DCBUS_SHIFT (16U) +/*! DCBUS - Direct current BUS + */ +#define ANACTRL_OSC_TESTBUS_DCBUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_OSC_TESTBUS_DCBUS_SHIFT)) & ANACTRL_OSC_TESTBUS_DCBUS_MASK) +/*! @} */ + +/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ +/*! @{ */ + +#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) +#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) +/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. + * 0b00..High speed Crystal oscillator output to ADC is disabled. + * 0b01..High speed Crystal oscillator output to ADC is enable. + */ +#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ + +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) + +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) + +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) + +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) + +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) + +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) + +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) + +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ + +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) + +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) + +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) + +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) + +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) + +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) + +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) + +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AOI0 base address */ + #define AOI0_BASE (0x500C7000u) + /** Peripheral AOI0 base address */ + #define AOI0_BASE_NS (0x400C7000u) + /** Peripheral AOI0 base pointer */ + #define AOI0 ((AOI_Type *)AOI0_BASE) + /** Peripheral AOI0 base pointer */ + #define AOI0_NS ((AOI_Type *)AOI0_BASE_NS) + /** Peripheral AOI1 base address */ + #define AOI1_BASE (0x500C8000u) + /** Peripheral AOI1 base address */ + #define AOI1_BASE_NS (0x400C8000u) + /** Peripheral AOI1 base pointer */ + #define AOI1 ((AOI_Type *)AOI1_BASE) + /** Peripheral AOI1 base pointer */ + #define AOI1_NS ((AOI_Type *)AOI1_BASE_NS) + /** Array initializer of AOI peripheral base addresses */ + #define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } + /** Array initializer of AOI peripheral base pointers */ + #define AOI_BASE_PTRS { AOI0, AOI1 } + /** Array initializer of AOI peripheral base addresses */ + #define AOI_BASE_ADDRS_NS { AOI0_BASE_NS, AOI1_BASE_NS } + /** Array initializer of AOI peripheral base pointers */ + #define AOI_BASE_PTRS_NS { AOI0_NS, AOI1_NS } +#else + /** Peripheral AOI0 base address */ + #define AOI0_BASE (0x400C7000u) + /** Peripheral AOI0 base pointer */ + #define AOI0 ((AOI_Type *)AOI0_BASE) + /** Peripheral AOI1 base address */ + #define AOI1_BASE (0x400C8000u) + /** Peripheral AOI1 base pointer */ + #define AOI1 ((AOI_Type *)AOI1_BASE) + /** Array initializer of AOI peripheral base addresses */ + #define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } + /** Array initializer of AOI peripheral base pointers */ + #define AOI_BASE_PTRS { AOI0, AOI1 } +#endif + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CACHE64_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer + * @{ + */ + +/** CACHE64_CTRL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CCR; /**< Cache control register, offset: 0x800 */ + __IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ + __IO uint32_t CSAR; /**< Cache search address register, offset: 0x808 */ + __IO uint32_t CCVR; /**< Cache read/write value register, offset: 0x80C */ +} CACHE64_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- CACHE64_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks + * @{ + */ + +/*! @name CCR - Cache control register */ +/*! @{ */ + +#define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) +#define CACHE64_CTRL_CCR_ENCACHE_SHIFT (0U) +/*! ENCACHE - Cache enable + * 0b0..Cache disabled + * 0b1..Cache enabled + */ +#define CACHE64_CTRL_CCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK) + +#define CACHE64_CTRL_CCR_ENWRBUF_MASK (0x2U) +#define CACHE64_CTRL_CCR_ENWRBUF_SHIFT (1U) +/*! ENWRBUF - Enable Write Buffer + * 0b0..Write buffer disabled + * 0b1..Write buffer enabled + */ +#define CACHE64_CTRL_CCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK) + +#define CACHE64_CTRL_CCR_INVW0_MASK (0x1000000U) +#define CACHE64_CTRL_CCR_INVW0_SHIFT (24U) +/*! INVW0 - Invalidate Way 0 + * 0b0..No operation + * 0b1..When setting the GO bit, invalidate all lines in way 0. + */ +#define CACHE64_CTRL_CCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK) + +#define CACHE64_CTRL_CCR_PUSHW0_MASK (0x2000000U) +#define CACHE64_CTRL_CCR_PUSHW0_SHIFT (25U) +/*! PUSHW0 - Push Way 0 + * 0b0..No operation + * 0b1..When setting the GO bit, push all modified lines in way 0 + */ +#define CACHE64_CTRL_CCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK) + +#define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) +#define CACHE64_CTRL_CCR_INVW1_SHIFT (26U) +/*! INVW1 - Invalidate Way 1 + * 0b0..No operation + * 0b1..When setting the GO bit, invalidate all lines in way 1 + */ +#define CACHE64_CTRL_CCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK) + +#define CACHE64_CTRL_CCR_PUSHW1_MASK (0x8000000U) +#define CACHE64_CTRL_CCR_PUSHW1_SHIFT (27U) +/*! PUSHW1 - Push Way 1 + * 0b0..No operation + * 0b1..When setting the GO bit, push all modified lines in way 1 + */ +#define CACHE64_CTRL_CCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK) + +#define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) +#define CACHE64_CTRL_CCR_GO_SHIFT (31U) +/*! GO - Initiate Cache Command + * 0b0..Write: no effect. Read: no cache command active. + * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. + */ +#define CACHE64_CTRL_CCR_GO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK) +/*! @} */ + +/*! @name CLCR - Cache line control register */ +/*! @{ */ + +#define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) +#define CACHE64_CTRL_CLCR_LGO_SHIFT (0U) +/*! LGO - Initiate Cache Line Command + * 0b0..Write: no effect. Read: no line command active. + * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. + */ +#define CACHE64_CTRL_CLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK) + +#define CACHE64_CTRL_CLCR_CACHEADDR_MASK (0x3FFCU) +#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT (2U) +/*! CACHEADDR - Cache address + */ +#define CACHE64_CTRL_CLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK) + +#define CACHE64_CTRL_CLCR_WSEL_MASK (0x4000U) +#define CACHE64_CTRL_CLCR_WSEL_SHIFT (14U) +/*! WSEL - Way select + * 0b0..Way 0 + * 0b1..Way 1 + */ +#define CACHE64_CTRL_CLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK) + +#define CACHE64_CTRL_CLCR_TDSEL_MASK (0x10000U) +#define CACHE64_CTRL_CLCR_TDSEL_SHIFT (16U) +/*! TDSEL - Tag/Data Select + * 0b0..Data + * 0b1..Tag + */ +#define CACHE64_CTRL_CLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK) + +#define CACHE64_CTRL_CLCR_LCIVB_MASK (0x100000U) +#define CACHE64_CTRL_CLCR_LCIVB_SHIFT (20U) +/*! LCIVB - Line Command Initial Valid Bit + */ +#define CACHE64_CTRL_CLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK) + +#define CACHE64_CTRL_CLCR_LCIMB_MASK (0x200000U) +#define CACHE64_CTRL_CLCR_LCIMB_SHIFT (21U) +/*! LCIMB - Line Command Initial Modified Bit + */ +#define CACHE64_CTRL_CLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK) + +#define CACHE64_CTRL_CLCR_LCWAY_MASK (0x400000U) +#define CACHE64_CTRL_CLCR_LCWAY_SHIFT (22U) +/*! LCWAY - Line Command Way + */ +#define CACHE64_CTRL_CLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK) + +#define CACHE64_CTRL_CLCR_LCMD_MASK (0x3000000U) +#define CACHE64_CTRL_CLCR_LCMD_SHIFT (24U) +/*! LCMD - Line Command + * 0b00..Search and read or write + * 0b01..Invalidate + * 0b10..Push + * 0b11..Clear + */ +#define CACHE64_CTRL_CLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK) + +#define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) +#define CACHE64_CTRL_CLCR_LADSEL_SHIFT (26U) +/*! LADSEL - Line Address Select + * 0b0..Cache address + * 0b1..Physical address + */ +#define CACHE64_CTRL_CLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK) + +#define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) +#define CACHE64_CTRL_CLCR_LACC_SHIFT (27U) +/*! LACC - Line access type + * 0b0..Read + * 0b1..Write + */ +#define CACHE64_CTRL_CLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK) +/*! @} */ + +/*! @name CSAR - Cache search address register */ +/*! @{ */ + +#define CACHE64_CTRL_CSAR_LGO_MASK (0x1U) +#define CACHE64_CTRL_CSAR_LGO_SHIFT (0U) +/*! LGO - Initiate Cache Line Command + * 0b0..Write: no effect. Read: no line command active. + * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. + */ +#define CACHE64_CTRL_CSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK) + +#define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) +#define CACHE64_CTRL_CSAR_PHYADDR_SHIFT (1U) +/*! PHYADDR - Physical Address + */ +#define CACHE64_CTRL_CSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK) +/*! @} */ + +/*! @name CCVR - Cache read/write value register */ +/*! @{ */ + +#define CACHE64_CTRL_CCVR_DATA_MASK (0xFFFFFFFFU) +#define CACHE64_CTRL_CCVR_DATA_SHIFT (0U) +/*! DATA - Cache read/write Data + */ +#define CACHE64_CTRL_CCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CACHE64_CTRL_Register_Masks */ + + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5002E000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4002E000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4002E000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x08000000u } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x28000000u } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x08000000u } +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x08000000u } +#endif +/* Backward compatibility */ + + +/*! + * @} + */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CACHE64_POLSEL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer + * @{ + */ + +/** CACHE64_POLSEL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t REG0_TOP; /**< Region 0 Top Boundary, offset: 0x14 */ + __IO uint32_t REG1_TOP; /**< Region 1 Top Boundary, offset: 0x18 */ + __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ +} CACHE64_POLSEL_Type; + +/* ---------------------------------------------------------------------------- + -- CACHE64_POLSEL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks + * @{ + */ + +/*! @name REG0_TOP - Region 0 Top Boundary */ +/*! @{ */ + +#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK (0x7FFFC00U) +#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) +/*! REG0_TOP - Upper limit of Region 0 + */ +#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK) +/*! @} */ + +/*! @name REG1_TOP - Region 1 Top Boundary */ +/*! @{ */ + +#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK (0x7FFFC00U) +#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT (10U) +/*! REG1_TOP - Upper limit of Region 1 + */ +#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK) +/*! @} */ + +/*! @name POLSEL - Policy Select */ +/*! @{ */ + +#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK (0x3U) +#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT (0U) +/*! REG0_POLICY - Policy Select for Region 0 + * 0b00..Non-cache + * 0b01..Write-thru + * 0b10..Write-back + * 0b11..Invalid + */ +#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK) + +#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK (0xCU) +#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT (2U) +/*! REG1_POLICY - Policy Select for Region 0 + * 0b00..Non-cache + * 0b01..Write-thru + * 0b10..Write-back + * 0b11..Invalid + */ +#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK) + +#define CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK (0x30U) +#define CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT (4U) +/*! REG02_POLICY - Policy Select for Region 0 + * 0b00..Non-cache + * 0b01..Write-thru + * 0b10..Write-back + * 0b11..Invalid + */ +#define CACHE64_POLSEL_POLSEL_REG02_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CACHE64_POLSEL_Register_Masks */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5002E000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4002E000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4002E000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/*! + * @} + */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t DBTP; /**< Data Bit Timing and Prescaler, offset: 0xC */ + __IO uint32_t TEST; /**< Test, offset: 0x10 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CCCR; /**< CC Control, offset: 0x18 */ + __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler, offset: 0x1C */ + __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ + __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ + __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ + __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ + uint8_t RESERVED_2[16]; + __I uint32_t ECR; /**< Error Counter, offset: 0x40 */ + __I uint32_t PSR; /**< Protocol Status, offset: 0x44 */ + __IO uint32_t TDCR; /**< Transmitter Delay Compensator, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t IR; /**< Interrupt, offset: 0x50 */ + __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ + __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ + __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ + uint8_t RESERVED_4[32]; + __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ + __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ + __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ + uint8_t RESERVED_5[4]; + __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ + __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ + __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ + __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ + __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ + __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ + __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ + __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ + __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ + __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ + __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ + __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ + __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ + __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ + __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ + __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ + __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ + __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ + __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ + __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ + __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ + __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ + uint8_t RESERVED_6[8]; + __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ + __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ + __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ + uint8_t RESERVED_7[260]; + __IO uint32_t MRBA; /**< Message RAM Base Address, offset: 0x200 */ + uint8_t RESERVED_8[508]; + __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ + uint8_t RESERVED_9[508]; + __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name DBTP - Data Bit Timing and Prescaler */ +/*! @{ */ + +#define CAN_DBTP_DSJW_MASK (0xFU) +#define CAN_DBTP_DSJW_SHIFT (0U) +/*! DSJW - Data (Re)Synchronization Jump Width + */ +#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) + +#define CAN_DBTP_DTSEG2_MASK (0xF0U) +#define CAN_DBTP_DTSEG2_SHIFT (4U) +/*! DTSEG2 - Data Time Segment After Sample Point + */ +#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) + +#define CAN_DBTP_DTSEG1_MASK (0x1F00U) +#define CAN_DBTP_DTSEG1_SHIFT (8U) +/*! DTSEG1 - Data Time Segment Before Sample Point + */ +#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) + +#define CAN_DBTP_DBRP_MASK (0x1F0000U) +#define CAN_DBTP_DBRP_SHIFT (16U) +/*! DBRP - Data Bit Rate Prescaler + */ +#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) + +#define CAN_DBTP_TDC_MASK (0x800000U) +#define CAN_DBTP_TDC_SHIFT (23U) +/*! TDC - Transmitter Delay Compensation + * 0b0..Transmitter delay compensation disabled + * 0b1..Transmitter delay compensation enabled + */ +#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) +/*! @} */ + +/*! @name TEST - Test */ +/*! @{ */ + +#define CAN_TEST_LBCK_MASK (0x10U) +#define CAN_TEST_LBCK_SHIFT (4U) +/*! LBCK - Loop Back Mode + * 0b0..Loop back mode is disabled. + * 0b1..Loop back mode is enabled. + */ +#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) + +#define CAN_TEST_TX_MASK (0x60U) +#define CAN_TEST_TX_SHIFT (5U) +/*! TX - Control of Transmit Pin + * 0b00..Loop back mode is disabled. + * 0b01..The sample point can be monitored at the CAN_TXD. + * 0b10..CAN_TXD pin is driven LOW/dominant. + * 0b11..CAN_TXD is driven HIGH/recessive. + */ +#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) + +#define CAN_TEST_RX_MASK (0x80U) +#define CAN_TEST_RX_SHIFT (7U) +/*! RX - Monitors the Actual Value of the CAN_RXD + * 0b0..The CAN bus is dominant (CAN_RXD = 0). + * 0b1..The CAN bus is recessive (CAN_RXD = 1). + */ +#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) +/*! @} */ + +/*! @name CCCR - CC Control */ +/*! @{ */ + +#define CAN_CCCR_INIT_MASK (0x1U) +#define CAN_CCCR_INIT_SHIFT (0U) +/*! INIT - Initialization + * 0b0..Normal operation + * 0b1..Initialization is started + */ +#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) + +#define CAN_CCCR_CCE_MASK (0x2U) +#define CAN_CCCR_CCE_SHIFT (1U) +/*! CCE - Configuration Change Enable + * 0b0..No write access. The CPU has no write access to the protected configuration registers. + * 0b1..Write access. The CPU has write access to the protected configuration registers. + */ +#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) + +#define CAN_CCCR_ASM_MASK (0x4U) +#define CAN_CCCR_ASM_SHIFT (2U) +/*! ASM - Restricted Operational Mode + * 0b0..Normal CAN operation + * 0b1..Restricted operation mode active + */ +#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) + +#define CAN_CCCR_CSA_MASK (0x8U) +#define CAN_CCCR_CSA_SHIFT (3U) +/*! CSA - Clock Stop Acknowledge + * 0b0..No clock stop acknowledged. + * 0b1..MCAN may be set in Power Down mode by stopping the internal MCAN clocks. + */ +#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) + +#define CAN_CCCR_CSR_MASK (0x10U) +#define CAN_CCCR_CSR_SHIFT (4U) +/*! CSR - Clock Stop Request + * 0b0..No clock stop is requested. + * 0b1..Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending + * transfer requests have been completed and the CAN bus reaches idle. + */ +#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) + +#define CAN_CCCR_MON_MASK (0x20U) +#define CAN_CCCR_MON_SHIFT (5U) +/*! MON - Bus Monitoring Mode + * 0b0..Bus Monitoring mode is disabled. + * 0b1..Bus Monitoring mode is enabled. + */ +#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) + +#define CAN_CCCR_DAR_MASK (0x40U) +#define CAN_CCCR_DAR_SHIFT (6U) +/*! DAR - Disable Automatic Retransmission + * 0b0..Automatic retransmission of messages not transmitted successfully enabled. + * 0b1..Automatic retransmission disabled. + */ +#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) + +#define CAN_CCCR_TEST_MASK (0x80U) +#define CAN_CCCR_TEST_SHIFT (7U) +/*! TEST - Test Mode Enable + * 0b0..Normal operation + * 0b1..Test mode enabled + */ +#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) + +#define CAN_CCCR_FDOE_MASK (0x100U) +#define CAN_CCCR_FDOE_SHIFT (8U) +/*! FDOE - CAN FD Operation Enable + * 0b0..CAN FD operation is disabled. + * 0b1..CAN FD operation is enabled. + */ +#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) + +#define CAN_CCCR_BRSE_MASK (0x200U) +#define CAN_CCCR_BRSE_SHIFT (9U) +/*! BRSE - Bit Rate Switching Enable + * 0b0..Bit rate switching for transmissions is disabled. + * 0b1..Bit rate switching for transmission is enabled. + */ +#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) + +#define CAN_CCCR_PXHD_MASK (0x1000U) +#define CAN_CCCR_PXHD_SHIFT (12U) +/*! PXHD - Protocol Exception Handling Disable + * 0b0..Protocol exception handling is enabled. + * 0b1..Protocol exception handling is disabled. + */ +#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) + +#define CAN_CCCR_EFBI_MASK (0x2000U) +#define CAN_CCCR_EFBI_SHIFT (13U) +/*! EFBI - Edge Filtering During Bus Integration + * 0b0..Edge filtering is disabled. + * 0b1..Two consecutive dominant quanta required to detect an edge for hard synchronization. + */ +#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) + +#define CAN_CCCR_TXP_MASK (0x4000U) +#define CAN_CCCR_TXP_SHIFT (14U) +/*! TXP - Transmit Pause + * 0b0..Transmit pause is disabled. + * 0b1..Transmit pause is enabled. + */ +#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) + +#define CAN_CCCR_NISO_MASK (0x8000U) +#define CAN_CCCR_NISO_SHIFT (15U) +/*! NISO - Non ISO Operation + * 0b0..CAN FD frame format will follow according to ISO11898-1. + * 0b1..CAN FD frame format will follow according to Bosch CAN FD Specification V1.0. + */ +#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) +/*! @} */ + +/*! @name NBTP - Nominal Bit Timing and Prescaler */ +/*! @{ */ + +#define CAN_NBTP_NTSEG2_MASK (0x7FU) +#define CAN_NBTP_NTSEG2_SHIFT (0U) +/*! NTSEG2 - Nominal Time Segment After Sample Point + */ +#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) + +#define CAN_NBTP_NTSEG1_MASK (0xFF00U) +#define CAN_NBTP_NTSEG1_SHIFT (8U) +/*! NTSEG1 - Nominal Time Segment Before Sample Point + */ +#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) + +#define CAN_NBTP_NBRP_MASK (0x1FF0000U) +#define CAN_NBTP_NBRP_SHIFT (16U) +/*! NBRP - Nominal Bit Rate Prescaler + */ +#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) + +#define CAN_NBTP_NSJW_MASK (0xFE000000U) +#define CAN_NBTP_NSJW_SHIFT (25U) +/*! NSJW - Nominal (Re)Synchronization Jump Width + */ +#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) +/*! @} */ + +/*! @name TSCC - Timestamp Counter Configuration */ +/*! @{ */ + +#define CAN_TSCC_TSS_MASK (0x3U) +#define CAN_TSCC_TSS_SHIFT (0U) +/*! TSS - Timestamp Select + * 0b00, 0b11..Timestamp counter value static at 0x0000 + * 0b01..Timestamp counter value incremented according to TCP bits + * 0b10..External timestamp counter value used + */ +#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) + +#define CAN_TSCC_TCP_MASK (0xF0000U) +#define CAN_TSCC_TCP_SHIFT (16U) +/*! TCP - Timestamp Counter Prescaler + */ +#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) +/*! @} */ + +/*! @name TSCV - Timestamp Counter Value */ +/*! @{ */ + +#define CAN_TSCV_TSC_MASK (0xFFFFU) +#define CAN_TSCV_TSC_SHIFT (0U) +/*! TSC - Timestamp Counter + */ +#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) +/*! @} */ + +/*! @name TOCC - Timeout Counter Configuration */ +/*! @{ */ + +#define CAN_TOCC_ETOC_MASK (0x1U) +#define CAN_TOCC_ETOC_SHIFT (0U) +/*! ETOC - Enable Timeout Counter + * 0b0..Timeout counter is disabled. + * 0b1..Timeout counter is enabled. + */ +#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) + +#define CAN_TOCC_TOS_MASK (0x6U) +#define CAN_TOCC_TOS_SHIFT (1U) +/*! TOS - Timeout Select + * 0b00..Continuous operation + * 0b01..Timeout is controlled by Tx event FIFO. + * 0b10..Timeout is controlled by Rx FIFO 0. + * 0b11..Timeout is controlled by Rx FIFO 1. + */ +#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) + +#define CAN_TOCC_TOP_MASK (0xFFFF0000U) +#define CAN_TOCC_TOP_SHIFT (16U) +/*! TOP - Timeout Period + */ +#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) +/*! @} */ + +/*! @name TOCV - Timeout Counter Value */ +/*! @{ */ + +#define CAN_TOCV_TOC_MASK (0xFFFFU) +#define CAN_TOCV_TOC_SHIFT (0U) +/*! TOC - Timeout Counter + */ +#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TEC_MASK (0xFFU) +#define CAN_ECR_TEC_SHIFT (0U) +/*! TEC - Transmit Error Counter + */ +#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) + +#define CAN_ECR_REC_MASK (0x7F00U) +#define CAN_ECR_REC_SHIFT (8U) +/*! REC - Receive Error Counter + */ +#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) + +#define CAN_ECR_RP_MASK (0x8000U) +#define CAN_ECR_RP_SHIFT (15U) +/*! RP - Receive Error Passive + * 0b0..Below error level. The receive counter is below the error passive level of 128. + * 0b1..At error level. The receive counter has reached the error passive level of 128. + */ +#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) + +#define CAN_ECR_CEL_MASK (0xFF0000U) +#define CAN_ECR_CEL_SHIFT (16U) +/*! CEL - CAN Error Logging + */ +#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) +/*! @} */ + +/*! @name PSR - Protocol Status */ +/*! @{ */ + +#define CAN_PSR_LEC_MASK (0x7U) +#define CAN_PSR_LEC_SHIFT (0U) +/*! LEC - Last Error Code + * 0b000..No error: No error has occurred since the LEC bits has been reset by successful reception or transmission. + * 0b001..Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where not allowed. + * 0b010..Form error: A fixed format part of a received frame has the wrong format. + * 0b011..AckError: The message transmitted by the MCAN was not acknowledged by another node. + * 0b100..Bit1Error: During the transmission of a message (with the exception of the arbitration field), the + * device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + * 0b101..Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload + * flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the + * monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 + * recessive bits has been monitored. This enables the CPU to monitor the processing of the Bus_Off recovery + * sequence (indicating the bus is not stuck at dominant or continuously disturbed). + * 0b110..CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does + * not match with the CRC calculated from the received data. + * 0b111..NoChange: Any read access to the protocol status register re-initializes the LEC bits to 0x7. When the + * LEC equals the value 0x7, no CAN bus event was detected since the last CPU read access to the protocol + * status register. + */ +#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) + +#define CAN_PSR_ACT_MASK (0x18U) +#define CAN_PSR_ACT_SHIFT (3U) +/*! ACT - Activity + * 0b00..Synchronizing - node is synchronizing on CAN communication. + * 0b01..Idle - node is neither receiver nor transmitter. + * 0b10..Receiver - node is operating as receiver. + * 0b11..Transmitter - node is operating as transmitter. + */ +#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) + +#define CAN_PSR_EP_MASK (0x20U) +#define CAN_PSR_EP_SHIFT (5U) +/*! EP - Error Passive + * 0b0..The MCAN is in Error_Active state. It normally takes part in bus communication and sends an active error + * flag when an error has been detected. + * 0b1..The MCAN is in the Error_Passive state. + */ +#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) + +#define CAN_PSR_EW_MASK (0x40U) +#define CAN_PSR_EW_SHIFT (6U) +/*! EW - Warning Status + * 0b0..Both error counters are below the Error_Warning limit of 96. + * 0b1..At least one of error counter has reached the Error_Warning limit of 96. + */ +#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) + +#define CAN_PSR_BO_MASK (0x80U) +#define CAN_PSR_BO_SHIFT (7U) +/*! BO - Bus Off Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) + +#define CAN_PSR_DLEC_MASK (0x700U) +#define CAN_PSR_DLEC_SHIFT (8U) +/*! DLEC - Data Phase Last Error Code + */ +#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) + +#define CAN_PSR_RESI_MASK (0x800U) +#define CAN_PSR_RESI_SHIFT (11U) +/*! RESI - ESI Flag of the Last Received CAN FD Message + * 0b0..Last received CAN FD message did not have its ESI flag set. + * 0b1..Last received CAN FD message had its ESI flag set. + */ +#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) + +#define CAN_PSR_RBRS_MASK (0x1000U) +#define CAN_PSR_RBRS_SHIFT (12U) +/*! RBRS - BRS Flag of Last Received CAN FD Message + * 0b0..Last received CAN FD message did not have its BRS flag set. + * 0b1..Last received CAN FD message had its BRS flag set. + */ +#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) + +#define CAN_PSR_RFDF_MASK (0x2000U) +#define CAN_PSR_RFDF_SHIFT (13U) +/*! RFDF - Received a CAN FD Message + * 0b0..No CAN FD message received since the last CPU reset. + * 0b1..Message in CAN FD format with FDF flag set has been received. + */ +#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) + +#define CAN_PSR_PXE_MASK (0x4000U) +#define CAN_PSR_PXE_SHIFT (14U) +/*! PXE - Protocol Exception Event + * 0b0..No protocol exception event occurred since last read access. + * 0b1..Protocol exception event occurred. + */ +#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) + +#define CAN_PSR_TDCV_MASK (0x7F0000U) +#define CAN_PSR_TDCV_SHIFT (16U) +/*! TDCV - Transmitter Delay Compensation Value + */ +#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) +/*! @} */ + +/*! @name TDCR - Transmitter Delay Compensator */ +/*! @{ */ + +#define CAN_TDCR_TDCF_MASK (0x7FU) +#define CAN_TDCR_TDCF_SHIFT (0U) +/*! TDCF - Transmitter Delay Compensation Filter Window Length + */ +#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) + +#define CAN_TDCR_TDCO_MASK (0x7F00U) +#define CAN_TDCR_TDCO_SHIFT (8U) +/*! TDCO - Transmitter Delay Compensation Offset + */ +#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) +/*! @} */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CAN_IR_RF0N_MASK (0x1U) +#define CAN_IR_RF0N_SHIFT (0U) +/*! RF0N - Rx FIFO 0 New Message + * 0b0..No new message written to Rx FIFO 0. + * 0b1..New message written to Rx FIFO 0. + */ +#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) + +#define CAN_IR_RF0W_MASK (0x2U) +#define CAN_IR_RF0W_SHIFT (1U) +/*! RF0W - Rx FIFO 0 Watermark Reached + * 0b0..Rx FIFO 0 fill level below watermark. + * 0b1..Rx FIFO 0 fill level reached watermark. + */ +#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) + +#define CAN_IR_RF0F_MASK (0x4U) +#define CAN_IR_RF0F_SHIFT (2U) +/*! RF0F - Rx FIFO 0 Full + * 0b0..Rx FIFO 0 not full. + * 0b1..Rx FIFO 0 full. + */ +#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) + +#define CAN_IR_RF0L_MASK (0x8U) +#define CAN_IR_RF0L_SHIFT (3U) +/*! RF0L - Rx FIFO 0 Message Lost + * 0b0..No Rx FIFO 0 message lost. + * 0b1..Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + */ +#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) + +#define CAN_IR_RF1N_MASK (0x10U) +#define CAN_IR_RF1N_SHIFT (4U) +/*! RF1N - Rx FIFO 1 New Message + * 0b0..No new message written to Rx FIFO 1. + * 0b1..New message written to Rx FIFO 1. + */ +#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) + +#define CAN_IR_RF1W_MASK (0x20U) +#define CAN_IR_RF1W_SHIFT (5U) +/*! RF1W - Rx FIFO 1 Watermark Reached + * 0b0..Rx FIFO 1 fill level below watermark. + * 0b1..Rx FIFO 1 fill level reached watermark. + */ +#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) + +#define CAN_IR_RF1F_MASK (0x40U) +#define CAN_IR_RF1F_SHIFT (6U) +/*! RF1F - Rx FIFO 1 Full + * 0b0..Rx FIFO 1 not full. + * 0b1..Rx FIFO 1 full. + */ +#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) + +#define CAN_IR_RF1L_MASK (0x80U) +#define CAN_IR_RF1L_SHIFT (7U) +/*! RF1L - Rx FIFO 1 Message Lost + * 0b0..No Rx FIFO 1 message lost. + * 0b1..Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. + */ +#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) + +#define CAN_IR_HPM_MASK (0x100U) +#define CAN_IR_HPM_SHIFT (8U) +/*! HPM - High Priority Message + * 0b0..No high priority message received. + * 0b1..High priority message received. + */ +#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) + +#define CAN_IR_TC_MASK (0x200U) +#define CAN_IR_TC_SHIFT (9U) +/*! TC - Transmission Completed + * 0b0..No transmission completed. + * 0b1..Transmission completed. + */ +#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) + +#define CAN_IR_TCF_MASK (0x400U) +#define CAN_IR_TCF_SHIFT (10U) +/*! TCF - Transmission Cancellation Finished + * 0b0..No transmission cancellation finished. + * 0b1..Transmission cancellation finished. + */ +#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) + +#define CAN_IR_TFE_MASK (0x800U) +#define CAN_IR_TFE_SHIFT (11U) +/*! TFE - Tx FIFO Empty + * 0b0..Tx FIFO non-empty. + * 0b1..Tx FIFO empty. + */ +#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) + +#define CAN_IR_TEFN_MASK (0x1000U) +#define CAN_IR_TEFN_SHIFT (12U) +/*! TEFN - Tx Event FIFO New Entry + * 0b0..Tx event FIFO unchanged. + * 0b1..Tx Handler wrote Tx event FIFO element. + */ +#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) + +#define CAN_IR_TEFW_MASK (0x2000U) +#define CAN_IR_TEFW_SHIFT (13U) +/*! TEFW - Tx Event FIFO Watermark Reached + * 0b0..Tx event FIFO fill level below watermark. + * 0b1..Tx event FIFO fill level reached watermark. + */ +#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) + +#define CAN_IR_TEFF_MASK (0x4000U) +#define CAN_IR_TEFF_SHIFT (14U) +/*! TEFF - Tx Event FIFO Full + * 0b0..Tx event FIFO not full. + * 0b1..Tx event FIFO full. + */ +#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) + +#define CAN_IR_TEFL_MASK (0x8000U) +#define CAN_IR_TEFL_SHIFT (15U) +/*! TEFL - Tx Event FIFO Element Lost + * 0b0..No Tx event FIFO element lost. + * 0b1..Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zero. + */ +#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) + +#define CAN_IR_TSW_MASK (0x10000U) +#define CAN_IR_TSW_SHIFT (16U) +/*! TSW - Timestamp Wraparound + * 0b0..No timestamp counter wraparound. + * 0b1..Timestamp counter wrapped around. + */ +#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) + +#define CAN_IR_MRAF_MASK (0x20000U) +#define CAN_IR_MRAF_SHIFT (17U) +/*! MRAF - Message RAM Access Failure + * 0b0..No message RAM access failure occurred. + * 0b1..Message RAM access failure occurred. + */ +#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) + +#define CAN_IR_TOO_MASK (0x40000U) +#define CAN_IR_TOO_SHIFT (18U) +/*! TOO - Timeout Occurred + * 0b0..No timeout. + * 0b1..Timeout reached. + */ +#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) + +#define CAN_IR_DRX_MASK (0x80000U) +#define CAN_IR_DRX_SHIFT (19U) +/*! DRX - Message Stored in Dedicated Rx Buffer + * 0b0..No Rx buffer updated. + * 0b1..At least one received message stored into an Rx buffer. + */ +#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) + +#define CAN_IR_BEC_MASK (0x100000U) +#define CAN_IR_BEC_SHIFT (20U) +/*! BEC - Bit Error Corrected + * 0b0..No bit error detected when reading from message RAM. + * 0b1..Bit error detected and corrected (example, ECC). + */ +#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) + +#define CAN_IR_BEU_MASK (0x200000U) +#define CAN_IR_BEU_SHIFT (21U) +/*! BEU - Bit Error Uncorrected + * 0b0..No bit error detected when reading from message RAM. + * 0b1..Bit error detected, uncorrected (example, parity logic). + */ +#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) + +#define CAN_IR_ELO_MASK (0x400000U) +#define CAN_IR_ELO_SHIFT (22U) +/*! ELO - Error Logging Overflow + * 0b0..CAN error logging counter did not overflow. + * 0b1..Overflow of CAN error logging counter occurred. + */ +#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) + +#define CAN_IR_EP_MASK (0x800000U) +#define CAN_IR_EP_SHIFT (23U) +/*! EP - Error Passive + * 0b0..Error_Passive status unchanged. + * 0b1..Error_Passive status changed. + */ +#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) + +#define CAN_IR_EW_MASK (0x1000000U) +#define CAN_IR_EW_SHIFT (24U) +/*! EW - Warning Status + * 0b0..Error_Warning status unchanged. + * 0b1..Error_Warning status changed. + */ +#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) + +#define CAN_IR_BO_MASK (0x2000000U) +#define CAN_IR_BO_SHIFT (25U) +/*! BO - Bus_Off Status + * 0b0..Bus_Off status unchanged. + * 0b1..Bus_Off status changed. + */ +#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) + +#define CAN_IR_WDI_MASK (0x4000000U) +#define CAN_IR_WDI_SHIFT (26U) +/*! WDI - Watchdog Interrupt + * 0b0..No message RAM watchdog event occurred. + * 0b1..Message RAM watchdog event due to missing READY. + */ +#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) + +#define CAN_IR_PEA_MASK (0x8000000U) +#define CAN_IR_PEA_SHIFT (27U) +/*! PEA - Protocol Error in Arbitration Phase + * 0b0..No protocol error in arbitration phase. + * 0b1..Protocol error in arbitration phase detected. + */ +#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) + +#define CAN_IR_PED_MASK (0x10000000U) +#define CAN_IR_PED_SHIFT (28U) +/*! PED - Protocol Error in Data Phase + * 0b0..No protocol error in data phase. + * 0b1..Protocol error in data phase detected. + */ +#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) + +#define CAN_IR_ARA_MASK (0x20000000U) +#define CAN_IR_ARA_SHIFT (29U) +/*! ARA - Access to Reserved Address + * 0b0..No access to reserved address occurred. + * 0b1..Access to reserved address occurred. + */ +#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable */ +/*! @{ */ + +#define CAN_IE_RF0NE_MASK (0x1U) +#define CAN_IE_RF0NE_SHIFT (0U) +/*! RF0NE - Rx FIFO 0 New Message Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) + +#define CAN_IE_RF0WE_MASK (0x2U) +#define CAN_IE_RF0WE_SHIFT (1U) +/*! RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) + +#define CAN_IE_RF0FE_MASK (0x4U) +#define CAN_IE_RF0FE_SHIFT (2U) +/*! RF0FE - Rx FIFO 0 Full Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) + +#define CAN_IE_RF0LE_MASK (0x8U) +#define CAN_IE_RF0LE_SHIFT (3U) +/*! RF0LE - Rx FIFO 0 Message Lost Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) + +#define CAN_IE_RF1NE_MASK (0x10U) +#define CAN_IE_RF1NE_SHIFT (4U) +/*! RF1NE - Rx FIFO 1 New Message Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) + +#define CAN_IE_RF1WE_MASK (0x20U) +#define CAN_IE_RF1WE_SHIFT (5U) +/*! RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) + +#define CAN_IE_RF1FE_MASK (0x40U) +#define CAN_IE_RF1FE_SHIFT (6U) +/*! RF1FE - Rx FIFO 1 Full Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) + +#define CAN_IE_RF1LE_MASK (0x80U) +#define CAN_IE_RF1LE_SHIFT (7U) +/*! RF1LE - Rx FIFO 1 Message Lost Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) + +#define CAN_IE_HPME_MASK (0x100U) +#define CAN_IE_HPME_SHIFT (8U) +/*! HPME - High Priority Message Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) + +#define CAN_IE_TCE_MASK (0x200U) +#define CAN_IE_TCE_SHIFT (9U) +/*! TCE - Transmission Completed Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) + +#define CAN_IE_TCFE_MASK (0x400U) +#define CAN_IE_TCFE_SHIFT (10U) +/*! TCFE - Transmission Cancellation Finished Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) + +#define CAN_IE_TFEE_MASK (0x800U) +#define CAN_IE_TFEE_SHIFT (11U) +/*! TFEE - Tx FIFO Empty Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) + +#define CAN_IE_TEFNE_MASK (0x1000U) +#define CAN_IE_TEFNE_SHIFT (12U) +/*! TEFNE - Tx Event FIFO New Entry Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) + +#define CAN_IE_TEFWE_MASK (0x2000U) +#define CAN_IE_TEFWE_SHIFT (13U) +/*! TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) + +#define CAN_IE_TEFFE_MASK (0x4000U) +#define CAN_IE_TEFFE_SHIFT (14U) +/*! TEFFE - Tx Event FIFO Full Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) + +#define CAN_IE_TEFLE_MASK (0x8000U) +#define CAN_IE_TEFLE_SHIFT (15U) +/*! TEFLE - Tx Event FIFO Element Lost Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) + +#define CAN_IE_TSWE_MASK (0x10000U) +#define CAN_IE_TSWE_SHIFT (16U) +/*! TSWE - Timestamp Wraparound Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) + +#define CAN_IE_MRAFE_MASK (0x20000U) +#define CAN_IE_MRAFE_SHIFT (17U) +/*! MRAFE - Message RAM Access Failure Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) + +#define CAN_IE_TOOE_MASK (0x40000U) +#define CAN_IE_TOOE_SHIFT (18U) +/*! TOOE - Timeout Occurred Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) + +#define CAN_IE_DRXE_MASK (0x80000U) +#define CAN_IE_DRXE_SHIFT (19U) +/*! DRXE - Message Stored in Dedicated Rx Buffer Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) + +#define CAN_IE_BECE_MASK (0x100000U) +#define CAN_IE_BECE_SHIFT (20U) +/*! BECE - Bit Error Corrected Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) + +#define CAN_IE_BEUE_MASK (0x200000U) +#define CAN_IE_BEUE_SHIFT (21U) +/*! BEUE - Bit Error Uncorrected Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) + +#define CAN_IE_ELOE_MASK (0x400000U) +#define CAN_IE_ELOE_SHIFT (22U) +/*! ELOE - Error Logging Overflow Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) + +#define CAN_IE_EPE_MASK (0x800000U) +#define CAN_IE_EPE_SHIFT (23U) +/*! EPE - Error Passive Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) + +#define CAN_IE_EWE_MASK (0x1000000U) +#define CAN_IE_EWE_SHIFT (24U) +/*! EWE - Warning Status Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) + +#define CAN_IE_BOE_MASK (0x2000000U) +#define CAN_IE_BOE_SHIFT (25U) +/*! BOE - Bus_Off Status Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) + +#define CAN_IE_WDIE_MASK (0x4000000U) +#define CAN_IE_WDIE_SHIFT (26U) +/*! WDIE - Watchdog Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) + +#define CAN_IE_PEAE_MASK (0x8000000U) +#define CAN_IE_PEAE_SHIFT (27U) +/*! PEAE - Protocol Error in Arbitration Phase Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) + +#define CAN_IE_PEDE_MASK (0x10000000U) +#define CAN_IE_PEDE_SHIFT (28U) +/*! PEDE - Protocol Error in Data Phase Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) + +#define CAN_IE_ARAE_MASK (0x20000000U) +#define CAN_IE_ARAE_SHIFT (29U) +/*! ARAE - Access to Reserved Address Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) +/*! @} */ + +/*! @name ILS - Interrupt Line Select */ +/*! @{ */ + +#define CAN_ILS_RF0NL_MASK (0x1U) +#define CAN_ILS_RF0NL_SHIFT (0U) +/*! RF0NL - Rx FIFO 0 New Message Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) + +#define CAN_ILS_RF0WL_MASK (0x2U) +#define CAN_ILS_RF0WL_SHIFT (1U) +/*! RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) + +#define CAN_ILS_RF0FL_MASK (0x4U) +#define CAN_ILS_RF0FL_SHIFT (2U) +/*! RF0FL - Rx FIFO 0 Full Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) + +#define CAN_ILS_RF0LL_MASK (0x8U) +#define CAN_ILS_RF0LL_SHIFT (3U) +/*! RF0LL - Rx FIFO 0 Message Lost Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) + +#define CAN_ILS_RF1NL_MASK (0x10U) +#define CAN_ILS_RF1NL_SHIFT (4U) +/*! RF1NL - Rx FIFO 1 New Message Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) + +#define CAN_ILS_RF1WL_MASK (0x20U) +#define CAN_ILS_RF1WL_SHIFT (5U) +/*! RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) + +#define CAN_ILS_RF1FL_MASK (0x40U) +#define CAN_ILS_RF1FL_SHIFT (6U) +/*! RF1FL - Rx FIFO 1 Full Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) + +#define CAN_ILS_RF1LL_MASK (0x80U) +#define CAN_ILS_RF1LL_SHIFT (7U) +/*! RF1LL - Rx FIFO 1 Message Lost Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) + +#define CAN_ILS_HPML_MASK (0x100U) +#define CAN_ILS_HPML_SHIFT (8U) +/*! HPML - High Priority Message Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) + +#define CAN_ILS_TCL_MASK (0x200U) +#define CAN_ILS_TCL_SHIFT (9U) +/*! TCL - Transmission Completed Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) + +#define CAN_ILS_TCFL_MASK (0x400U) +#define CAN_ILS_TCFL_SHIFT (10U) +/*! TCFL - Transmission Cancellation Finished Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) + +#define CAN_ILS_TFEL_MASK (0x800U) +#define CAN_ILS_TFEL_SHIFT (11U) +/*! TFEL - Tx FIFO Empty Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) + +#define CAN_ILS_TEFNL_MASK (0x1000U) +#define CAN_ILS_TEFNL_SHIFT (12U) +/*! TEFNL - Tx Event FIFO New Entry Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) + +#define CAN_ILS_TEFWL_MASK (0x2000U) +#define CAN_ILS_TEFWL_SHIFT (13U) +/*! TEFWL - Tx Event FIFO Watermark Reached Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) + +#define CAN_ILS_TEFFL_MASK (0x4000U) +#define CAN_ILS_TEFFL_SHIFT (14U) +/*! TEFFL - Tx Event FIFO Full Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) + +#define CAN_ILS_TEFLL_MASK (0x8000U) +#define CAN_ILS_TEFLL_SHIFT (15U) +/*! TEFLL - Tx Event FIFO Element Lost Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) + +#define CAN_ILS_TSWL_MASK (0x10000U) +#define CAN_ILS_TSWL_SHIFT (16U) +/*! TSWL - Timestamp Wraparound Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) + +#define CAN_ILS_MRAFL_MASK (0x20000U) +#define CAN_ILS_MRAFL_SHIFT (17U) +/*! MRAFL - Message RAM Access Failure Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) + +#define CAN_ILS_TOOL_MASK (0x40000U) +#define CAN_ILS_TOOL_SHIFT (18U) +/*! TOOL - Timeout Occurred Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) + +#define CAN_ILS_DRXL_MASK (0x80000U) +#define CAN_ILS_DRXL_SHIFT (19U) +/*! DRXL - Message Stored in Dedicated Rx Buffer Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) + +#define CAN_ILS_BECL_MASK (0x100000U) +#define CAN_ILS_BECL_SHIFT (20U) +/*! BECL - Bit Error Corrected Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) + +#define CAN_ILS_BEUL_MASK (0x200000U) +#define CAN_ILS_BEUL_SHIFT (21U) +/*! BEUL - Bit Error Uncorrected Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) + +#define CAN_ILS_ELOL_MASK (0x400000U) +#define CAN_ILS_ELOL_SHIFT (22U) +/*! ELOL - Error Logging Overflow Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) + +#define CAN_ILS_EPL_MASK (0x800000U) +#define CAN_ILS_EPL_SHIFT (23U) +/*! EPL - Error Passive Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) + +#define CAN_ILS_EWL_MASK (0x1000000U) +#define CAN_ILS_EWL_SHIFT (24U) +/*! EWL - Warning Status Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) + +#define CAN_ILS_BOL_MASK (0x2000000U) +#define CAN_ILS_BOL_SHIFT (25U) +/*! BOL - Bus_Off Status Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) + +#define CAN_ILS_WDIL_MASK (0x4000000U) +#define CAN_ILS_WDIL_SHIFT (26U) +/*! WDIL - Watchdog Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) + +#define CAN_ILS_PEAL_MASK (0x8000000U) +#define CAN_ILS_PEAL_SHIFT (27U) +/*! PEAL - Protocol Error in Arbitration Phase Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) + +#define CAN_ILS_PEDL_MASK (0x10000000U) +#define CAN_ILS_PEDL_SHIFT (28U) +/*! PEDL - Protocol Error in Data Phase Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) + +#define CAN_ILS_ARAL_MASK (0x20000000U) +#define CAN_ILS_ARAL_SHIFT (29U) +/*! ARAL - Access to Reserved Address Interrupt Line + * 0b0..Interrupt assigned to interrupt line MCANx_INT0 + * 0b1..Interrupt assigned to interrupt line MCANx_INT1 + */ +#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) +/*! @} */ + +/*! @name ILE - Interrupt Line Enable */ +/*! @{ */ + +#define CAN_ILE_EINT0_MASK (0x1U) +#define CAN_ILE_EINT0_SHIFT (0U) +/*! EINT0 - Enable Interrupt Line 0 + * 0b0..Interrupt line to MCANx_INT0 is disabled. + * 0b1..Interrupt line to MCANx_INT0 is enabled. + */ +#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) + +#define CAN_ILE_EINT1_MASK (0x2U) +#define CAN_ILE_EINT1_SHIFT (1U) +/*! EINT1 - Enable Interrupt Line 1 + * 0b0..Interrupt line to MCANx_INT1 is disabled. + * 0b1..Interrupt line to MCANx_INT1 is enabled. + */ +#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) +/*! @} */ + +/*! @name GFC - Global Filter Configuration */ +/*! @{ */ + +#define CAN_GFC_RRFE_MASK (0x1U) +#define CAN_GFC_RRFE_SHIFT (0U) +/*! RRFE - Reject Remote Frames Extended + * 0b0..Filter remote frames with 29-bit extended IDs + * 0b1..Reject all remote frames with 29-bit extended IDs + */ +#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) + +#define CAN_GFC_RRFS_MASK (0x2U) +#define CAN_GFC_RRFS_SHIFT (1U) +/*! RRFS - Reject Remote Frames Standard + * 0b0..Filter remote frames with 11-bit standard IDs + * 0b1..Reject all remote frames with 11-bit standard IDs + */ +#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) + +#define CAN_GFC_ANFE_MASK (0xCU) +#define CAN_GFC_ANFE_SHIFT (2U) +/*! ANFE - Accept Non-matching Frames Extended + * 0b00..Accept in Rx FIFO 0 + * 0b01..Accept in Rx FIFO 1 + * 0b10, 0b11..Reject + */ +#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) + +#define CAN_GFC_ANFS_MASK (0x30U) +#define CAN_GFC_ANFS_SHIFT (4U) +/*! ANFS - Accept Non-matching Frames Standard + * 0b00..Accept in Rx FIFO 0 + * 0b01..Accept in Rx FIFO 1 + * 0b10, 0b11..Reject + */ +#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) +/*! @} */ + +/*! @name SIDFC - Standard ID Filter Configuration */ +/*! @{ */ + +#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) +#define CAN_SIDFC_FLSSA_SHIFT (2U) +/*! FLSSA - Filter List Standard Start Address + */ +#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) + +#define CAN_SIDFC_LSS_MASK (0xFF0000U) +#define CAN_SIDFC_LSS_SHIFT (16U) +/*! LSS - List Size Standard + */ +#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) +/*! @} */ + +/*! @name XIDFC - Extended ID Filter Configuration */ +/*! @{ */ + +#define CAN_XIDFC_FLESA_MASK (0xFFFCU) +#define CAN_XIDFC_FLESA_SHIFT (2U) +/*! FLESA - Filter List Extended Start Address + */ +#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) + +#define CAN_XIDFC_LSE_MASK (0xFF0000U) +#define CAN_XIDFC_LSE_SHIFT (16U) +/*! LSE - List Size Extended + */ +#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) +/*! @} */ + +/*! @name XIDAM - Extended ID AND Mask */ +/*! @{ */ + +#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) +#define CAN_XIDAM_EIDM_SHIFT (0U) +/*! EIDM - Extended ID Mask + */ +#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) +/*! @} */ + +/*! @name HPMS - High Priority Message Status */ +/*! @{ */ + +#define CAN_HPMS_BIDX_MASK (0x3FU) +#define CAN_HPMS_BIDX_SHIFT (0U) +/*! BIDX - Buffer Index + */ +#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) + +#define CAN_HPMS_MSI_MASK (0xC0U) +#define CAN_HPMS_MSI_SHIFT (6U) +/*! MSI - Message Storage Indicator + * 0b00..No FIFO selected + * 0b01..FIFO message lost + * 0b10..Message stored in FIFO 0 + * 0b11..Message stored in FIFO 1 + */ +#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) + +#define CAN_HPMS_FIDX_MASK (0x7F00U) +#define CAN_HPMS_FIDX_SHIFT (8U) +/*! FIDX - Filter Index + */ +#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) + +#define CAN_HPMS_FLST_MASK (0x8000U) +#define CAN_HPMS_FLST_SHIFT (15U) +/*! FLST - Filter List + * 0b0..Standard filter list + * 0b1..Extended filter list + */ +#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) +/*! @} */ + +/*! @name NDAT1 - New Data 1 */ +/*! @{ */ + +#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) +#define CAN_NDAT1_ND_SHIFT (0U) +/*! ND - New Data + */ +#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) +/*! @} */ + +/*! @name NDAT2 - New Data 2 */ +/*! @{ */ + +#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) +#define CAN_NDAT2_ND_SHIFT (0U) +/*! ND - New Data + */ +#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) +/*! @} */ + +/*! @name RXF0C - Rx FIFO 0 Configuration */ +/*! @{ */ + +#define CAN_RXF0C_F0SA_MASK (0xFFFCU) +#define CAN_RXF0C_F0SA_SHIFT (2U) +/*! F0SA - Rx FIFO 0 Start Address + */ +#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) + +#define CAN_RXF0C_F0S_MASK (0x7F0000U) +#define CAN_RXF0C_F0S_SHIFT (16U) +/*! F0S - Rx FIFO 0 Size + */ +#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) + +#define CAN_RXF0C_F0WM_MASK (0x7F000000U) +#define CAN_RXF0C_F0WM_SHIFT (24U) +/*! F0WM - Rx FIFO 0 Watermark + */ +#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) + +#define CAN_RXF0C_F0OM_MASK (0x80000000U) +#define CAN_RXF0C_F0OM_SHIFT (31U) +/*! F0OM - FIFO 0 Operation Mode + * 0b0..FIFO 0 blocking mode + * 0b1..FIFO 0 overwrite mode + */ +#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) +/*! @} */ + +/*! @name RXF0S - Rx FIFO 0 Status */ +/*! @{ */ + +#define CAN_RXF0S_F0FL_MASK (0x7FU) +#define CAN_RXF0S_F0FL_SHIFT (0U) +/*! F0FL - Rx FIFO 0 Fill Level + */ +#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) + +#define CAN_RXF0S_F0GI_MASK (0x3F00U) +#define CAN_RXF0S_F0GI_SHIFT (8U) +/*! F0GI - Rx FIFO 0 Get Index + */ +#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) + +#define CAN_RXF0S_F0PI_MASK (0x3F0000U) +#define CAN_RXF0S_F0PI_SHIFT (16U) +/*! F0PI - Rx FIFO 0 Put Index + */ +#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) + +#define CAN_RXF0S_F0F_MASK (0x1000000U) +#define CAN_RXF0S_F0F_SHIFT (24U) +/*! F0F - Rx FIFO 0 Full + * 0b0..Rx FIFO 0 not full + * 0b1..Rx FIFO 0 full + */ +#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) + +#define CAN_RXF0S_RF0L_MASK (0x2000000U) +#define CAN_RXF0S_RF0L_SHIFT (25U) +/*! RF0L - Rx FIFO 0 Message Lost + */ +#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) +/*! @} */ + +/*! @name RXF0A - Rx FIFO 0 Acknowledge */ +/*! @{ */ + +#define CAN_RXF0A_F0AI_MASK (0x3FU) +#define CAN_RXF0A_F0AI_SHIFT (0U) +/*! F0AI - Rx FIFO 0 Acknowledge Index + */ +#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) +/*! @} */ + +/*! @name RXBC - Rx Buffer Configuration */ +/*! @{ */ + +#define CAN_RXBC_RBSA_MASK (0xFFFCU) +#define CAN_RXBC_RBSA_SHIFT (2U) +/*! RBSA - Rx Buffer Start Address + */ +#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) +/*! @} */ + +/*! @name RXF1C - Rx FIFO 1 Configuration */ +/*! @{ */ + +#define CAN_RXF1C_F1SA_MASK (0xFFFCU) +#define CAN_RXF1C_F1SA_SHIFT (2U) +/*! F1SA - Rx FIFO 1 Start Address + */ +#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) + +#define CAN_RXF1C_F1S_MASK (0x7F0000U) +#define CAN_RXF1C_F1S_SHIFT (16U) +/*! F1S - Rx FIFO 1 Size + */ +#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) + +#define CAN_RXF1C_F1WM_MASK (0x7F000000U) +#define CAN_RXF1C_F1WM_SHIFT (24U) +/*! F1WM - Rx FIFO 1 Watermark + */ +#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) + +#define CAN_RXF1C_F1OM_MASK (0x80000000U) +#define CAN_RXF1C_F1OM_SHIFT (31U) +/*! F1OM - FIFO 1 Operation Mode + * 0b0..FIFO 1 blocking mode + * 0b1..FIFO 1 overwrite mode + */ +#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) +/*! @} */ + +/*! @name RXF1S - Rx FIFO 1 Status */ +/*! @{ */ + +#define CAN_RXF1S_F1FL_MASK (0x7FU) +#define CAN_RXF1S_F1FL_SHIFT (0U) +/*! F1FL - Rx FIFO 1 Fill Level + */ +#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) + +#define CAN_RXF1S_F1GI_MASK (0x3F00U) +#define CAN_RXF1S_F1GI_SHIFT (8U) +/*! F1GI - Rx FIFO 1 Get Index + */ +#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) + +#define CAN_RXF1S_F1PI_MASK (0x3F0000U) +#define CAN_RXF1S_F1PI_SHIFT (16U) +/*! F1PI - Rx FIFO 1 Put Index + */ +#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) + +#define CAN_RXF1S_F1F_MASK (0x1000000U) +#define CAN_RXF1S_F1F_SHIFT (24U) +/*! F1F - Rx FIFO 1 Full + * 0b0..Rx FIFO 1 not full + * 0b1..Rx FIFO 1 full + */ +#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) + +#define CAN_RXF1S_RF1L_MASK (0x2000000U) +#define CAN_RXF1S_RF1L_SHIFT (25U) +/*! RF1L - Rx FIFO 1 message lost. + * 0b0..No Rx FIFO 1 message lost. + * 0b1..Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. + */ +#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) +/*! @} */ + +/*! @name RXF1A - Rx FIFO 1 Acknowledge */ +/*! @{ */ + +#define CAN_RXF1A_F1AI_MASK (0x3FU) +#define CAN_RXF1A_F1AI_SHIFT (0U) +/*! F1AI - Rx FIFO 1 Acknowledge Index + */ +#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) +/*! @} */ + +/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ +/*! @{ */ + +#define CAN_RXESC_F0DS_MASK (0x7U) +#define CAN_RXESC_F0DS_SHIFT (0U) +/*! F0DS - Rx FIFO 0 Data Field Size + * 0b000..8 byte data field + * 0b001..12 byte data field + * 0b010..16 byte data field + * 0b011..20 byte data field + * 0b100..24 byte data field + * 0b101..32 byte data field + * 0b110..48 byte data field + * 0b111..64 byte data field + */ +#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) + +#define CAN_RXESC_F1DS_MASK (0x70U) +#define CAN_RXESC_F1DS_SHIFT (4U) +/*! F1DS - Rx FIFO 1 Data Field Size + * 0b000..8 byte data field + * 0b001..12 byte data field + * 0b010..16 byte data field + * 0b011..20 byte data field + * 0b100..24 byte data field + * 0b101..32 byte data field + * 0b110..48 byte data field + * 0b111..64 byte data field + */ +#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) + +#define CAN_RXESC_RBDS_MASK (0x700U) +#define CAN_RXESC_RBDS_SHIFT (8U) +/*! RBDS - Rx Buffer Data Field Size + * 0b000..8 byte data field + * 0b001..12 byte data field + * 0b010..16 byte data field + * 0b011..20 byte data field + * 0b100..24 byte data field + * 0b101..32 byte data field + * 0b110..48 byte data field + * 0b111..64 byte data field + */ +#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) +/*! @} */ + +/*! @name TXBC - Tx Buffer Configuration */ +/*! @{ */ + +#define CAN_TXBC_TBSA_MASK (0xFFFCU) +#define CAN_TXBC_TBSA_SHIFT (2U) +/*! TBSA - Tx Buffers Start Address + */ +#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) + +#define CAN_TXBC_NDTB_MASK (0x3F0000U) +#define CAN_TXBC_NDTB_SHIFT (16U) +/*! NDTB - Number of Dedicated Transmit Buffers + */ +#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) + +#define CAN_TXBC_TFQS_MASK (0x3F000000U) +#define CAN_TXBC_TFQS_SHIFT (24U) +/*! TFQS - Transmit FIFO/Queue Size + */ +#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) + +#define CAN_TXBC_TFQM_MASK (0x40000000U) +#define CAN_TXBC_TFQM_SHIFT (30U) +/*! TFQM - Tx FIFO/Queue Mode + * 0b0..Tx FIFO operation + * 0b1..Tx queue operation + */ +#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) +/*! @} */ + +/*! @name TXFQS - Tx FIFO/Queue Status */ +/*! @{ */ + +#define CAN_TXFQS_TFGI_MASK (0x1F00U) +#define CAN_TXFQS_TFGI_SHIFT (8U) +/*! TFGI - Tx FIFO Get Index + */ +#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) + +#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) +#define CAN_TXFQS_TFQPI_SHIFT (16U) +/*! TFQPI - Tx FIFO/Queue Put Index + */ +#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) + +#define CAN_TXFQS_TFQF_MASK (0x200000U) +#define CAN_TXFQS_TFQF_SHIFT (21U) +/*! TFQF - Tx FIFO/Queue Full + * 0b0..Tx FIFO/Queue not full + * 0b1..Tx FIFO/Queue full + */ +#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) +/*! @} */ + +/*! @name TXESC - Tx Buffer Element Size Configuration */ +/*! @{ */ + +#define CAN_TXESC_TBDS_MASK (0x7U) +#define CAN_TXESC_TBDS_SHIFT (0U) +/*! TBDS - Tx Buffer Data Field Size + * 0b000..8 byte data field + * 0b001..12 byte data field + * 0b010..16 byte data field + * 0b011..20 byte data field + * 0b100..24 byte data field + * 0b101..32 byte data field + * 0b110..48 byte data field + * 0b111..64 byte data field + */ +#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) +/*! @} */ + +/*! @name TXBRP - Tx Buffer Request Pending */ +/*! @{ */ + +#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) +#define CAN_TXBRP_TRP_SHIFT (0U) +/*! TRP - Transmission Request Pending + */ +#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) +/*! @} */ + +/*! @name TXBAR - Tx Buffer Add Request */ +/*! @{ */ + +#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) +#define CAN_TXBAR_AR_SHIFT (0U) +/*! AR - Add Request + */ +#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) +/*! @} */ + +/*! @name TXBCR - Tx Buffer Cancellation Request */ +/*! @{ */ + +#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) +#define CAN_TXBCR_CR_SHIFT (0U) +/*! CR - Cancellation Request + */ +#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) +/*! @} */ + +/*! @name TXBTO - Tx Buffer Transmission Occurred */ +/*! @{ */ + +#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) +#define CAN_TXBTO_TO_SHIFT (0U) +/*! TO - Transmission Occurred + */ +#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) +/*! @} */ + +/*! @name TXBCF - Tx Buffer Cancellation Finished */ +/*! @{ */ + +#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) +#define CAN_TXBCF_TO_SHIFT (0U) +/*! TO - Cancellation Finished + */ +#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) +/*! @} */ + +/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ +/*! @{ */ + +#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) +#define CAN_TXBTIE_TIE_SHIFT (0U) +/*! TIE - Transmission Interrupt Enable + */ +#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) +/*! @} */ + +/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ +/*! @{ */ + +#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) +#define CAN_TXBCIE_CFIE_SHIFT (0U) +/*! CFIE - Cancellation Finished Interrupt Enable + */ +#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) +/*! @} */ + +/*! @name TXEFC - Tx Event FIFO Configuration */ +/*! @{ */ + +#define CAN_TXEFC_EFSA_MASK (0xFFFCU) +#define CAN_TXEFC_EFSA_SHIFT (2U) +/*! EFSA - Event FIFO Start Address + */ +#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) + +#define CAN_TXEFC_EFS_MASK (0x3F0000U) +#define CAN_TXEFC_EFS_SHIFT (16U) +/*! EFS - Event FIFO Size + */ +#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) + +#define CAN_TXEFC_EFWM_MASK (0x3F000000U) +#define CAN_TXEFC_EFWM_SHIFT (24U) +/*! EFWM - Event FIFO Watermark + */ +#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) +/*! @} */ + +/*! @name TXEFS - Tx Event FIFO Status */ +/*! @{ */ + +#define CAN_TXEFS_EFFL_MASK (0x3FU) +#define CAN_TXEFS_EFFL_SHIFT (0U) +/*! EFFL - Event FIFO Fill Level + */ +#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) + +#define CAN_TXEFS_EFGI_MASK (0x1F00U) +#define CAN_TXEFS_EFGI_SHIFT (8U) +/*! EFGI - Event FIFO Get Index + */ +#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) + +#define CAN_TXEFS_EFPI_MASK (0x3F0000U) +#define CAN_TXEFS_EFPI_SHIFT (16U) +/*! EFPI - Event FIFO Put Index + */ +#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) + +#define CAN_TXEFS_EFF_MASK (0x1000000U) +#define CAN_TXEFS_EFF_SHIFT (24U) +/*! EFF - Event FIFO Full + * 0b0..Tx event FIFO not full + * 0b1..Tx event FIFO full + */ +#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) + +#define CAN_TXEFS_TEFL_MASK (0x2000000U) +#define CAN_TXEFS_TEFL_SHIFT (25U) +/*! TEFL - Tx Event FIFO Element Lost + * 0b0..No Tx event FIFO element lost. + * 0b1..Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zero. + */ +#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) +/*! @} */ + +/*! @name TXEFA - Tx Event FIFO Acknowledge */ +/*! @{ */ + +#define CAN_TXEFA_EFAI_MASK (0x1FU) +#define CAN_TXEFA_EFAI_SHIFT (0U) +/*! EFAI - Event FIFO Acknowledge Index + */ +#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) +/*! @} */ + +/*! @name MRBA - Message RAM Base Address */ +/*! @{ */ + +#define CAN_MRBA_BA_MASK (0xFFFF0000U) +#define CAN_MRBA_BA_SHIFT (16U) +/*! BA - Base Address for the message RAM in the chip memory map. + */ +#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) +/*! @} */ + +/*! @name ETSCC - External Timestamp Counter Configuration */ +/*! @{ */ + +#define CAN_ETSCC_ETCP_MASK (0x7FFU) +#define CAN_ETSCC_ETCP_SHIFT (0U) +/*! ETCP - External Timestamp Prescaler Value + */ +#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) + +#define CAN_ETSCC_ETCE_MASK (0x80000000U) +#define CAN_ETSCC_ETCE_SHIFT (31U) +/*! ETCE - External Timestamp Counter Enable + * 0b0..External timestamp counter is disabled + * 0b1..External timestamp counter is enabled + */ +#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) +/*! @} */ + +/*! @name ETSCV - External Timestamp Counter Value */ +/*! @{ */ + +#define CAN_ETSCV_ETSC_MASK (0xFFFFU) +#define CAN_ETSCV_ETSC_SHIFT (0U) +/*! ETSC - External Timestamp Counter + */ +#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x5009D000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x4009D000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x4009D000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer reload, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer, offset: 0x8 */ + __I uint32_t SECURE_COUNTER; /**< Secure Counter, offset: 0xC */ + __I uint32_t STATUS; /**< Status 1, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage, offset: 0x1C */ + __O uint32_t START; /**< START Command, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command, offset: 0x48 */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer reload */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value + */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer + */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name SECURE_COUNTER - Secure Counter */ +/*! @{ */ + +#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) +#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) +/*! SECCNT - Secure Counter + */ +#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults since the last POR + */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR + */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults since the last POR + */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State + */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults since the last POR + */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults since the last POR + */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults since the last POR + */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage + */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command + */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command + */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command + */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value + */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 + */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 + */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 + */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command */ +/*! @{ */ + +#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) +#define CDOG_SUB_S0B_SHIFT (0U) +/*! S0B - Subtract Write Value + */ +#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command */ +/*! @{ */ + +#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_S1B_SHIFT (0U) +/*! S1B - Subtract 1 + */ +#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 + */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 + */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG base address */ + #define CDOG_BASE (0x500A1000u) + /** Peripheral CDOG base address */ + #define CDOG_BASE_NS (0x400A1000u) + /** Peripheral CDOG base pointer */ + #define CDOG ((CDOG_Type *)CDOG_BASE) + /** Peripheral CDOG base pointer */ + #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG_NS } +#else + /** Peripheral CDOG base address */ + #define CDOG_BASE (0x400A1000u) + /** Peripheral CDOG base pointer */ + #define CDOG ((CDOG_Type *)CDOG_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG_IRQn } + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< CRC DATA register, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - CRC DATA register */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - CRC Low Lower Byte + */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - CRC Low Upper Byte + */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - CRC High Lower Byte + */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - CRC High Upper Byte + */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - CRC Polynomial register */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Polynominal Half-word + */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Polynominal Half-word + */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16-bit CRC protocol. + * 0b1..32-bit CRC protocol. + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write CRC DATA register As Seed + * 0b0..Writes to the CRC DATA register are data values. + * 0b1..Writes to the CRC DATA register are seed values. + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read Of CRC DATA register + * 0b0..No XOR on reading. + * 0b1..Invert or complement the read value of the CRC DATA register. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Type Of Transpose For Read + * 0b00..No transposition. + * 0b01..Bits in bytes are transposed; bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Type Of Transpose For Writes + * 0b00..No transposition. + * 0b01..Bits in bytes are transposed; bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - CRC Control register */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16-bit CRC protocol. + * 0b1..32-bit CRC protocol. + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write CRC DATA register As Seed + * 0b0..Writes to the CRC DATA register are data values. + * 0b1..Writes to the CRC DATA register are seed values. + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read Of CRC DATA register + * 0b0..No XOR on reading. + * 0b1..Invert or complement the read value of the CRC DATA register. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Type Of Transpose For Read + * 0b00..No transposition. + * 0b01..Bits in bytes are transposed; bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Type Of Transpose For Writes + * 0b00..No transposition. + * 0b01..Bits in bytes are transposed; bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed; no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x50095000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x40095000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x40095000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSS_Peripheral_Access_Layer CSS Peripheral Access Layer + * @{ + */ + +/** CSS - Register Layout Typedef */ +typedef struct { + __I uint32_t CSS_STATUS; /**< Status register, offset: 0x0 */ + __IO uint32_t CSS_CTRL; /**< CSS Control register, offset: 0x4 */ + __IO uint32_t CSS_CMDCFG0; /**< CSS command configuration register, offset: 0x8 */ + __IO uint32_t CSS_CFG; /**< CSS configuration register, offset: 0xC */ + __IO uint32_t CSS_KIDX0; /**< Keystore index 0 - for commands that access a single key, offset: 0x10 */ + __IO uint32_t CSS_KIDX1; /**< Keystore index 1 - for commands that access 2 keys, offset: 0x14 */ + __IO uint32_t CSS_KPROPIN; /**< key properties request, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSS_DMA_SRC0; /**< CSS DMA Source 0, offset: 0x20 */ + __IO uint32_t CSS_DMA_SRC0_LEN; /**< CSS DMA Source 0 length, offset: 0x24 */ + __IO uint32_t CSS_DMA_SRC1; /**< CSS DMA Source 1, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSS_DMA_SRC2; /**< CSS DMA Source 2, offset: 0x30 */ + __IO uint32_t CSS_DMA_SRC2_LEN; /**< CSS DMA Source 2 length, offset: 0x34 */ + __IO uint32_t CSS_DMA_RES0; /**< CSS DMA Result 0, offset: 0x38 */ + __IO uint32_t CSS_DMA_RES0_LEN; /**< CSS DMA Result 0 Size, offset: 0x3C */ + __IO uint32_t CSS_INT_ENABLE; /**< Interrupt enable, offset: 0x40 */ + __O uint32_t CSS_INT_STATUS_CLR; /**< Interrupt status clear, offset: 0x44 */ + __O uint32_t CSS_INT_STATUS_SET; /**< Interrupt status set, offset: 0x48 */ + __I uint32_t CSS_ERR_STATUS; /**< Status register, offset: 0x4C */ + __O uint32_t CSS_ERR_STATUS_CLR; /**< Interrupt status clear, offset: 0x50 */ + __I uint32_t CSS_VERSION; /**< CSS Version, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __I uint32_t CSS_PRNG_DATOUT; /**< PRNG SW read out register, offset: 0x5C */ + __I uint32_t CSS_GDET_EVTCNT; /**< CSS GDET Event Counter, offset: 0x60 */ + __O uint32_t CSS_GDET_EVTCNT_CLR; /**< CSS GDET Event Counter Clear, offset: 0x64 */ + uint8_t RESERVED_3[152]; + __I uint32_t CSS_SHA2_STATUS; /**< CSS SHA2 Status Register, offset: 0x100 */ + __IO uint32_t CSS_SHA2_CTRL; /**< SHA2 Control register, offset: 0x104 */ + __IO uint32_t CSS_SHA2_DIN; /**< CSS SHA_DATA IN Register 0, offset: 0x108 */ + __I uint32_t CSS_SHA2_DOUT0; /**< CSS CSS_SHA_DATA Out Register 0, offset: 0x10C */ + __I uint32_t CSS_SHA2_DOUT1; /**< CSS SHA_DATA Out Register 1, offset: 0x110 */ + __I uint32_t CSS_SHA2_DOUT2; /**< CSS SHA_DATA Out Register 2, offset: 0x114 */ + __I uint32_t CSS_SHA2_DOUT3; /**< CSS SHA_DATA Out Register 3, offset: 0x118 */ + __I uint32_t CSS_SHA2_DOUT4; /**< CSS SHA_DATA Out Register 4, offset: 0x11C */ + __I uint32_t CSS_SHA2_DOUT5; /**< CSS SHA_DATA Out Register 5, offset: 0x120 */ + __I uint32_t CSS_SHA2_DOUT6; /**< CSS SHA_DATA Out Register 6, offset: 0x124 */ + __I uint32_t CSS_SHA2_DOUT7; /**< CSS SHA_DATA Out Register 7, offset: 0x128 */ + __I uint32_t CSS_SHA2_DOUT8; /**< CSS CSS_SHA_DATA Out Register 8, offset: 0x12C */ + __I uint32_t CSS_SHA2_DOUT9; /**< CSS SHA_DATA Out Register 9, offset: 0x130 */ + __I uint32_t CSS_SHA2_DOUT10; /**< CSS SHA_DATA Out Register 10, offset: 0x134 */ + __I uint32_t CSS_SHA2_DOUT11; /**< CSS SHA_DATA Out Register 11, offset: 0x138 */ + __I uint32_t CSS_SHA2_DOUT12; /**< CSS SHA_DATA Out Register 12, offset: 0x13C */ + __I uint32_t CSS_SHA2_DOUT13; /**< CSS SHA_DATA Out Register 13, offset: 0x140 */ + __I uint32_t CSS_SHA2_DOUT14; /**< CSS SHA_DATA Out Register 14, offset: 0x144 */ + __I uint32_t CSS_SHA2_DOUT15; /**< CSS SHA_DATA Out Register 15, offset: 0x148 */ + uint8_t RESERVED_4[4]; + __I uint32_t CSS_KS0; /**< Status register, offset: 0x150 */ + __I uint32_t CSS_KS1; /**< Status register, offset: 0x154 */ + __I uint32_t CSS_KS2; /**< Status register, offset: 0x158 */ + __I uint32_t CSS_KS3; /**< Status register, offset: 0x15C */ + __I uint32_t CSS_KS4; /**< Status register, offset: 0x160 */ + __I uint32_t CSS_KS5; /**< Status register, offset: 0x164 */ + __I uint32_t CSS_KS6; /**< Status register, offset: 0x168 */ + __I uint32_t CSS_KS7; /**< Status register, offset: 0x16C */ + __I uint32_t CSS_KS8; /**< Status register, offset: 0x170 */ + __I uint32_t CSS_KS9; /**< Status register, offset: 0x174 */ + __I uint32_t CSS_KS10; /**< Status register, offset: 0x178 */ + __I uint32_t CSS_KS11; /**< Status register, offset: 0x17C */ + __I uint32_t CSS_KS12; /**< Status register, offset: 0x180 */ + __I uint32_t CSS_KS13; /**< Status register, offset: 0x184 */ + __I uint32_t CSS_KS14; /**< Status register, offset: 0x188 */ + __I uint32_t CSS_KS15; /**< Status register, offset: 0x18C */ + __I uint32_t CSS_KS16; /**< Status register, offset: 0x190 */ + __I uint32_t CSS_KS17; /**< Status register, offset: 0x194 */ + __I uint32_t CSS_KS18; /**< Status register, offset: 0x198 */ + __I uint32_t CSS_KS19; /**< Status register, offset: 0x19C */ +} CSS_Type; + +/* ---------------------------------------------------------------------------- + -- CSS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSS_Register_Masks CSS Register Masks + * @{ + */ + +/*! @name CSS_STATUS - Status register */ +/*! @{ */ + +#define CSS_CSS_STATUS_css_busy_MASK (0x1U) +#define CSS_CSS_STATUS_css_busy_SHIFT (0U) +/*! css_busy - High to indicate the CSS is executing a Crypto Sequence + */ +#define CSS_CSS_STATUS_css_busy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_busy_SHIFT)) & CSS_CSS_STATUS_css_busy_MASK) + +#define CSS_CSS_STATUS_css_irq_MASK (0x2U) +#define CSS_CSS_STATUS_css_irq_SHIFT (1U) +/*! css_irq - High to indicate the CSS has an active interrupt + */ +#define CSS_CSS_STATUS_css_irq(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_irq_SHIFT)) & CSS_CSS_STATUS_css_irq_MASK) + +#define CSS_CSS_STATUS_css_err_MASK (0x4U) +#define CSS_CSS_STATUS_css_err_SHIFT (2U) +/*! css_err - High to indicate the CSS has detected an internal error + */ +#define CSS_CSS_STATUS_css_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_err_SHIFT)) & CSS_CSS_STATUS_css_err_MASK) + +#define CSS_CSS_STATUS_prng_rdy_MASK (0x8U) +#define CSS_CSS_STATUS_prng_rdy_SHIFT (3U) +/*! prng_rdy - High to indicate the internal PRNG is ready. SFR + */ +#define CSS_CSS_STATUS_prng_rdy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_prng_rdy_SHIFT)) & CSS_CSS_STATUS_prng_rdy_MASK) + +#define CSS_CSS_STATUS_ecdsa_vfy_status_MASK (0x30U) +#define CSS_CSS_STATUS_ecdsa_vfy_status_SHIFT (4U) +/*! ecdsa_vfy_status - Signature Verify Result Status + */ +#define CSS_CSS_STATUS_ecdsa_vfy_status(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_ecdsa_vfy_status_SHIFT)) & CSS_CSS_STATUS_ecdsa_vfy_status_MASK) + +#define CSS_CSS_STATUS_pprot_MASK (0xC0U) +#define CSS_CSS_STATUS_pprot_SHIFT (6U) +/*! pprot - Current command privilege level + */ +#define CSS_CSS_STATUS_pprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_pprot_SHIFT)) & CSS_CSS_STATUS_pprot_MASK) + +#define CSS_CSS_STATUS_drbg_ent_lvl_MASK (0x300U) +#define CSS_CSS_STATUS_drbg_ent_lvl_SHIFT (8U) +/*! drbg_ent_lvl - Entropy quality of the current DRBG instance. This value + */ +#define CSS_CSS_STATUS_drbg_ent_lvl(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_drbg_ent_lvl_SHIFT)) & CSS_CSS_STATUS_drbg_ent_lvl_MASK) + +#define CSS_CSS_STATUS_dtrng_busy_MASK (0x400U) +#define CSS_CSS_STATUS_dtrng_busy_SHIFT (10U) +/*! dtrng_busy - When set, it indicates the DTRNG is gathering entropy + */ +#define CSS_CSS_STATUS_dtrng_busy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_dtrng_busy_SHIFT)) & CSS_CSS_STATUS_dtrng_busy_MASK) + +#define CSS_CSS_STATUS_gdet_irq_pos_MASK (0x800U) +#define CSS_CSS_STATUS_gdet_irq_pos_SHIFT (11U) +/*! gdet_irq_pos - IRQ for GDET has detected a negative glitch: active high irq + */ +#define CSS_CSS_STATUS_gdet_irq_pos(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_gdet_irq_pos_SHIFT)) & CSS_CSS_STATUS_gdet_irq_pos_MASK) + +#define CSS_CSS_STATUS_gdet_irq_neg_MASK (0x1000U) +#define CSS_CSS_STATUS_gdet_irq_neg_SHIFT (12U) +/*! gdet_irq_neg - IRQ for GDET has detected a positive glitch: active high irq + */ +#define CSS_CSS_STATUS_gdet_irq_neg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_gdet_irq_neg_SHIFT)) & CSS_CSS_STATUS_gdet_irq_neg_MASK) + +#define CSS_CSS_STATUS_status_rsvd_MASK (0xFFFFE000U) +#define CSS_CSS_STATUS_status_rsvd_SHIFT (13U) +/*! status_rsvd - reserved + */ +#define CSS_CSS_STATUS_status_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_status_rsvd_SHIFT)) & CSS_CSS_STATUS_status_rsvd_MASK) +/*! @} */ + +/*! @name CSS_CTRL - CSS Control register */ +/*! @{ */ + +#define CSS_CSS_CTRL_css_en_MASK (0x1U) +#define CSS_CSS_CTRL_css_en_SHIFT (0U) +/*! css_en - CSS enable 0=CSS disabled, 1= CSS is enabled + */ +#define CSS_CSS_CTRL_css_en(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_en_SHIFT)) & CSS_CSS_CTRL_css_en_MASK) + +#define CSS_CSS_CTRL_css_start_MASK (0x2U) +#define CSS_CSS_CTRL_css_start_SHIFT (1U) +/*! css_start - Write to 1 to start a CSS Operation + */ +#define CSS_CSS_CTRL_css_start(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_start_SHIFT)) & CSS_CSS_CTRL_css_start_MASK) + +#define CSS_CSS_CTRL_css_reset_MASK (0x4U) +#define CSS_CSS_CTRL_css_reset_SHIFT (2U) +/*! css_reset - Write to 1 to perform a CSS synchronous Reset + */ +#define CSS_CSS_CTRL_css_reset(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_reset_SHIFT)) & CSS_CSS_CTRL_css_reset_MASK) + +#define CSS_CSS_CTRL_css_cmd_MASK (0xF8U) +#define CSS_CSS_CTRL_css_cmd_SHIFT (3U) +/*! css_cmd - CSS Command Field: List of Valid commands: + */ +#define CSS_CSS_CTRL_css_cmd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_cmd_SHIFT)) & CSS_CSS_CTRL_css_cmd_MASK) + +#define CSS_CSS_CTRL_byte_order_MASK (0x100U) +#define CSS_CSS_CTRL_byte_order_SHIFT (8U) +/*! byte_order - Defines Endianness - 1: BigEndian, 0: Little Endian + */ +#define CSS_CSS_CTRL_byte_order(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_byte_order_SHIFT)) & CSS_CSS_CTRL_byte_order_MASK) + +#define CSS_CSS_CTRL_ctrl_rfu_MASK (0xFFFFFE00U) +#define CSS_CSS_CTRL_ctrl_rfu_SHIFT (9U) +/*! ctrl_rfu - reserved + */ +#define CSS_CSS_CTRL_ctrl_rfu(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_ctrl_rfu_SHIFT)) & CSS_CSS_CTRL_ctrl_rfu_MASK) +/*! @} */ + +/*! @name CSS_CMDCFG0 - CSS command configuration register */ +/*! @{ */ + +#define CSS_CSS_CMDCFG0_cmdcfg0_MASK (0xFFFFFFFFU) +#define CSS_CSS_CMDCFG0_cmdcfg0_SHIFT (0U) +/*! cmdcfg0 - refer to reference manual for assignment of this field + */ +#define CSS_CSS_CMDCFG0_cmdcfg0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CMDCFG0_cmdcfg0_SHIFT)) & CSS_CSS_CMDCFG0_cmdcfg0_MASK) +/*! @} */ + +/*! @name CSS_CFG - CSS configuration register */ +/*! @{ */ + +#define CSS_CSS_CFG_cfg_rsvd0_MASK (0xFFFFU) +#define CSS_CSS_CFG_cfg_rsvd0_SHIFT (0U) +/*! cfg_rsvd0 - reserved + */ +#define CSS_CSS_CFG_cfg_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_cfg_rsvd0_SHIFT)) & CSS_CSS_CFG_cfg_rsvd0_MASK) + +#define CSS_CSS_CFG_adctrl_MASK (0x3FF0000U) +#define CSS_CSS_CFG_adctrl_SHIFT (16U) +/*! adctrl - maximum aes start delay + */ +#define CSS_CSS_CFG_adctrl(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_adctrl_SHIFT)) & CSS_CSS_CFG_adctrl_MASK) + +#define CSS_CSS_CFG_cfg_rsvd1_MASK (0x7C000000U) +#define CSS_CSS_CFG_cfg_rsvd1_SHIFT (26U) +/*! cfg_rsvd1 - reserved + */ +#define CSS_CSS_CFG_cfg_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_cfg_rsvd1_SHIFT)) & CSS_CSS_CFG_cfg_rsvd1_MASK) + +#define CSS_CSS_CFG_sha2_direct_MASK (0x80000000U) +#define CSS_CSS_CFG_sha2_direct_SHIFT (31U) +/*! sha2_direct - 1=enable sha2 direct mode: direct access from external + */ +#define CSS_CSS_CFG_sha2_direct(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_sha2_direct_SHIFT)) & CSS_CSS_CFG_sha2_direct_MASK) +/*! @} */ + +/*! @name CSS_KIDX0 - Keystore index 0 - for commands that access a single key */ +/*! @{ */ + +#define CSS_CSS_KIDX0_kidx0_MASK (0x7FU) +#define CSS_CSS_KIDX0_kidx0_SHIFT (0U) +/*! kidx0 - keystore is indexed as an array of 128 bit key slots + */ +#define CSS_CSS_KIDX0_kidx0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX0_kidx0_SHIFT)) & CSS_CSS_KIDX0_kidx0_MASK) + +#define CSS_CSS_KIDX0_kidx0_rsvd_MASK (0xFFFFFF80U) +#define CSS_CSS_KIDX0_kidx0_rsvd_SHIFT (7U) +/*! kidx0_rsvd - reserved + */ +#define CSS_CSS_KIDX0_kidx0_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX0_kidx0_rsvd_SHIFT)) & CSS_CSS_KIDX0_kidx0_rsvd_MASK) +/*! @} */ + +/*! @name CSS_KIDX1 - Keystore index 1 - for commands that access 2 keys */ +/*! @{ */ + +#define CSS_CSS_KIDX1_kidx1_MASK (0x7FU) +#define CSS_CSS_KIDX1_kidx1_SHIFT (0U) +/*! kidx1 - keystore is indexed as an array of 128 bit key slots + */ +#define CSS_CSS_KIDX1_kidx1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX1_kidx1_SHIFT)) & CSS_CSS_KIDX1_kidx1_MASK) + +#define CSS_CSS_KIDX1_kidx1_rsvd_MASK (0xFFFFFF80U) +#define CSS_CSS_KIDX1_kidx1_rsvd_SHIFT (7U) +/*! kidx1_rsvd - reserved + */ +#define CSS_CSS_KIDX1_kidx1_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX1_kidx1_rsvd_SHIFT)) & CSS_CSS_KIDX1_kidx1_rsvd_MASK) +/*! @} */ + +/*! @name CSS_KPROPIN - key properties request */ +/*! @{ */ + +#define CSS_CSS_KPROPIN_kpropin_MASK (0xFFFFFFFFU) +#define CSS_CSS_KPROPIN_kpropin_SHIFT (0U) +/*! kpropin - for commands that create a key - requested properties + */ +#define CSS_CSS_KPROPIN_kpropin(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KPROPIN_kpropin_SHIFT)) & CSS_CSS_KPROPIN_kpropin_MASK) +/*! @} */ + +/*! @name CSS_DMA_SRC0 - CSS DMA Source 0 */ +/*! @{ */ + +#define CSS_CSS_DMA_SRC0_addr_src0_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_SRC0_addr_src0_SHIFT (0U) +/*! addr_src0 - defines the System address of the start of the + */ +#define CSS_CSS_DMA_SRC0_addr_src0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC0_addr_src0_SHIFT)) & CSS_CSS_DMA_SRC0_addr_src0_MASK) +/*! @} */ + +/*! @name CSS_DMA_SRC0_LEN - CSS DMA Source 0 length */ +/*! @{ */ + +#define CSS_CSS_DMA_SRC0_LEN_size_src0_len_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_SRC0_LEN_size_src0_len_SHIFT (0U) +/*! size_src0_len - Size in bytes of the data to be transferred from + */ +#define CSS_CSS_DMA_SRC0_LEN_size_src0_len(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC0_LEN_size_src0_len_SHIFT)) & CSS_CSS_DMA_SRC0_LEN_size_src0_len_MASK) +/*! @} */ + +/*! @name CSS_DMA_SRC1 - CSS DMA Source 1 */ +/*! @{ */ + +#define CSS_CSS_DMA_SRC1_addr_src1_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_SRC1_addr_src1_SHIFT (0U) +/*! addr_src1 - defines the System address of the start of the + */ +#define CSS_CSS_DMA_SRC1_addr_src1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC1_addr_src1_SHIFT)) & CSS_CSS_DMA_SRC1_addr_src1_MASK) +/*! @} */ + +/*! @name CSS_DMA_SRC2 - CSS DMA Source 2 */ +/*! @{ */ + +#define CSS_CSS_DMA_SRC2_addr_src2_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_SRC2_addr_src2_SHIFT (0U) +/*! addr_src2 - defines the System address of the start of the + */ +#define CSS_CSS_DMA_SRC2_addr_src2(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC2_addr_src2_SHIFT)) & CSS_CSS_DMA_SRC2_addr_src2_MASK) +/*! @} */ + +/*! @name CSS_DMA_SRC2_LEN - CSS DMA Source 2 length */ +/*! @{ */ + +#define CSS_CSS_DMA_SRC2_LEN_size_src2_len_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_SRC2_LEN_size_src2_len_SHIFT (0U) +/*! size_src2_len - Size in bytes of the data to be transferred from + */ +#define CSS_CSS_DMA_SRC2_LEN_size_src2_len(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC2_LEN_size_src2_len_SHIFT)) & CSS_CSS_DMA_SRC2_LEN_size_src2_len_MASK) +/*! @} */ + +/*! @name CSS_DMA_RES0 - CSS DMA Result 0 */ +/*! @{ */ + +#define CSS_CSS_DMA_RES0_addr_res0_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_RES0_addr_res0_SHIFT (0U) +/*! addr_res0 - defines the System Start address of where the result + */ +#define CSS_CSS_DMA_RES0_addr_res0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_RES0_addr_res0_SHIFT)) & CSS_CSS_DMA_RES0_addr_res0_MASK) +/*! @} */ + +/*! @name CSS_DMA_RES0_LEN - CSS DMA Result 0 Size */ +/*! @{ */ + +#define CSS_CSS_DMA_RES0_LEN_size_res0_len_MASK (0xFFFFFFFFU) +#define CSS_CSS_DMA_RES0_LEN_size_res0_len_SHIFT (0U) +/*! size_res0_len - Size in bytes of the data to be transferred to + */ +#define CSS_CSS_DMA_RES0_LEN_size_res0_len(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_RES0_LEN_size_res0_len_SHIFT)) & CSS_CSS_DMA_RES0_LEN_size_res0_len_MASK) +/*! @} */ + +/*! @name CSS_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define CSS_CSS_INT_ENABLE_int_en_MASK (0x1U) +#define CSS_CSS_INT_ENABLE_int_en_SHIFT (0U) +/*! int_en - Interrupt enable bit + */ +#define CSS_CSS_INT_ENABLE_int_en(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_int_en_SHIFT)) & CSS_CSS_INT_ENABLE_int_en_MASK) + +#define CSS_CSS_INT_ENABLE_gdet_int_en_MASK (0x2U) +#define CSS_CSS_INT_ENABLE_gdet_int_en_SHIFT (1U) +/*! gdet_int_en - GDET Interrupt enable bit + */ +#define CSS_CSS_INT_ENABLE_gdet_int_en(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_gdet_int_en_SHIFT)) & CSS_CSS_INT_ENABLE_gdet_int_en_MASK) + +#define CSS_CSS_INT_ENABLE_int_ena_rsvd_MASK (0xFFFFFFFCU) +#define CSS_CSS_INT_ENABLE_int_ena_rsvd_SHIFT (2U) +/*! int_ena_rsvd - reserved + */ +#define CSS_CSS_INT_ENABLE_int_ena_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_int_ena_rsvd_SHIFT)) & CSS_CSS_INT_ENABLE_int_ena_rsvd_MASK) +/*! @} */ + +/*! @name CSS_INT_STATUS_CLR - Interrupt status clear */ +/*! @{ */ + +#define CSS_CSS_INT_STATUS_CLR_int_clr_MASK (0x1U) +#define CSS_CSS_INT_STATUS_CLR_int_clr_SHIFT (0U) +/*! int_clr - Interrupt status clear + */ +#define CSS_CSS_INT_STATUS_CLR_int_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_int_clr_SHIFT)) & CSS_CSS_INT_STATUS_CLR_int_clr_MASK) + +#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr_MASK (0x2U) +#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr_SHIFT (1U) +/*! gdet_int_clr - GDET Interrupt status clear + */ +#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_gdet_int_clr_SHIFT)) & CSS_CSS_INT_STATUS_CLR_gdet_int_clr_MASK) + +#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_MASK (0xFFFFFFFCU) +#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_SHIFT (2U) +/*! int_stsc_rsvd - reserved + */ +#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_SHIFT)) & CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_MASK) +/*! @} */ + +/*! @name CSS_INT_STATUS_SET - Interrupt status set */ +/*! @{ */ + +#define CSS_CSS_INT_STATUS_SET_int_set_MASK (0x1U) +#define CSS_CSS_INT_STATUS_SET_int_set_SHIFT (0U) +/*! int_set - Set interrupt by software + */ +#define CSS_CSS_INT_STATUS_SET_int_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_int_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_int_set_MASK) + +#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_MASK (0x2U) +#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_SHIFT (1U) +/*! gdet_int_neg_set - Set GDET interrupt by software + */ +#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_MASK) + +#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_MASK (0x4U) +#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_SHIFT (2U) +/*! gdet_int_pos_set - Set GDET interrupt by software + */ +#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_MASK) + +#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd_MASK (0xFFFFFFF8U) +#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd_SHIFT (3U) +/*! int_stss_rsvd - reserved + */ +#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_int_stss_rsvd_SHIFT)) & CSS_CSS_INT_STATUS_SET_int_stss_rsvd_MASK) +/*! @} */ + +/*! @name CSS_ERR_STATUS - Status register */ +/*! @{ */ + +#define CSS_CSS_ERR_STATUS_bus_err_MASK (0x1U) +#define CSS_CSS_ERR_STATUS_bus_err_SHIFT (0U) +/*! bus_err - Bus access error: public or private bus + */ +#define CSS_CSS_ERR_STATUS_bus_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_bus_err_SHIFT)) & CSS_CSS_ERR_STATUS_bus_err_MASK) + +#define CSS_CSS_ERR_STATUS_opn_err_MASK (0x2U) +#define CSS_CSS_ERR_STATUS_opn_err_SHIFT (1U) +/*! opn_err - Operational error: + */ +#define CSS_CSS_ERR_STATUS_opn_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_opn_err_SHIFT)) & CSS_CSS_ERR_STATUS_opn_err_MASK) + +#define CSS_CSS_ERR_STATUS_alg_err_MASK (0x4U) +#define CSS_CSS_ERR_STATUS_alg_err_SHIFT (2U) +/*! alg_err - Algorithm error: An internal algorithm has + */ +#define CSS_CSS_ERR_STATUS_alg_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_alg_err_SHIFT)) & CSS_CSS_ERR_STATUS_alg_err_MASK) + +#define CSS_CSS_ERR_STATUS_itg_err_MASK (0x8U) +#define CSS_CSS_ERR_STATUS_itg_err_SHIFT (3U) +/*! itg_err - Data integrity error: + */ +#define CSS_CSS_ERR_STATUS_itg_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_itg_err_SHIFT)) & CSS_CSS_ERR_STATUS_itg_err_MASK) + +#define CSS_CSS_ERR_STATUS_flt_err_MASK (0x10U) +#define CSS_CSS_ERR_STATUS_flt_err_SHIFT (4U) +/*! flt_err - Hardware fault error: Attempt to change the value + */ +#define CSS_CSS_ERR_STATUS_flt_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_flt_err_SHIFT)) & CSS_CSS_ERR_STATUS_flt_err_MASK) + +#define CSS_CSS_ERR_STATUS_prng_err_MASK (0x20U) +#define CSS_CSS_ERR_STATUS_prng_err_SHIFT (5U) +/*! prng_err - User Read of CSS_PRNG_DATOUT when CSS_STATUS.PRNG_RDY + */ +#define CSS_CSS_ERR_STATUS_prng_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_prng_err_SHIFT)) & CSS_CSS_ERR_STATUS_prng_err_MASK) + +#define CSS_CSS_ERR_STATUS_err_lvl_MASK (0xC0U) +#define CSS_CSS_ERR_STATUS_err_lvl_SHIFT (6U) +/*! err_lvl - Indicates Error Level which has been triggerer. 0, 1 ,2 + */ +#define CSS_CSS_ERR_STATUS_err_lvl(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_err_lvl_SHIFT)) & CSS_CSS_ERR_STATUS_err_lvl_MASK) + +#define CSS_CSS_ERR_STATUS_dtrng_err_MASK (0x100U) +#define CSS_CSS_ERR_STATUS_dtrng_err_SHIFT (8U) +/*! dtrng_err - DTRNG unable to gather entropy with the current + */ +#define CSS_CSS_ERR_STATUS_dtrng_err(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_dtrng_err_SHIFT)) & CSS_CSS_ERR_STATUS_dtrng_err_MASK) + +#define CSS_CSS_ERR_STATUS_err_stat_rsvd_MASK (0xFFFFFE00U) +#define CSS_CSS_ERR_STATUS_err_stat_rsvd_SHIFT (9U) +/*! err_stat_rsvd - reserved + */ +#define CSS_CSS_ERR_STATUS_err_stat_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_err_stat_rsvd_SHIFT)) & CSS_CSS_ERR_STATUS_err_stat_rsvd_MASK) +/*! @} */ + +/*! @name CSS_ERR_STATUS_CLR - Interrupt status clear */ +/*! @{ */ + +#define CSS_CSS_ERR_STATUS_CLR_err_clr_MASK (0x1U) +#define CSS_CSS_ERR_STATUS_CLR_err_clr_SHIFT (0U) +/*! err_clr - 1=clear CSS error status bits and exit CSS error state + */ +#define CSS_CSS_ERR_STATUS_CLR_err_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_CLR_err_clr_SHIFT)) & CSS_CSS_ERR_STATUS_CLR_err_clr_MASK) + +#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_MASK (0xFFFFFFFEU) +#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_SHIFT (1U) +/*! err_stsc_rsvd - reserved + */ +#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_SHIFT)) & CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_MASK) +/*! @} */ + +/*! @name CSS_VERSION - CSS Version */ +/*! @{ */ + +#define CSS_CSS_VERSION_z_MASK (0xFU) +#define CSS_CSS_VERSION_z_SHIFT (0U) +/*! z - extended revision version: possible values 0-9 + */ +#define CSS_CSS_VERSION_z(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_z_SHIFT)) & CSS_CSS_VERSION_z_MASK) + +#define CSS_CSS_VERSION_y2_MASK (0xF0U) +#define CSS_CSS_VERSION_y2_SHIFT (4U) +/*! y2 - minor release versino digit0: possible values 0-9 + */ +#define CSS_CSS_VERSION_y2(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_y2_SHIFT)) & CSS_CSS_VERSION_y2_MASK) + +#define CSS_CSS_VERSION_y1_MASK (0xF00U) +#define CSS_CSS_VERSION_y1_SHIFT (8U) +/*! y1 - minor release version digit1: possible values 0-9 + */ +#define CSS_CSS_VERSION_y1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_y1_SHIFT)) & CSS_CSS_VERSION_y1_MASK) + +#define CSS_CSS_VERSION_x_MASK (0xF000U) +#define CSS_CSS_VERSION_x_SHIFT (12U) +/*! x - major release version: possible values 1-9 + */ +#define CSS_CSS_VERSION_x(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_x_SHIFT)) & CSS_CSS_VERSION_x_MASK) + +#define CSS_CSS_VERSION_version_rsvd_MASK (0xFFFF0000U) +#define CSS_CSS_VERSION_version_rsvd_SHIFT (16U) +/*! version_rsvd - reserved + */ +#define CSS_CSS_VERSION_version_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_version_rsvd_SHIFT)) & CSS_CSS_VERSION_version_rsvd_MASK) +/*! @} */ + +/*! @name CSS_PRNG_DATOUT - PRNG SW read out register */ +/*! @{ */ + +#define CSS_CSS_PRNG_DATOUT_prng_datout_MASK (0xFFFFFFFFU) +#define CSS_CSS_PRNG_DATOUT_prng_datout_SHIFT (0U) +/*! prng_datout - 32-bit wide pseudo-random number + */ +#define CSS_CSS_PRNG_DATOUT_prng_datout(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_PRNG_DATOUT_prng_datout_SHIFT)) & CSS_CSS_PRNG_DATOUT_prng_datout_MASK) +/*! @} */ + +/*! @name CSS_GDET_EVTCNT - CSS GDET Event Counter */ +/*! @{ */ + +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_MASK (0xFFU) +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_SHIFT (0U) +/*! gdet_evtcnt - Number of glitch event recorded + */ +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_MASK) + +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_MASK (0x100U) +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_SHIFT (8U) +/*! gdet_evtcnt_clr_done - The GDET event counter has been cleared + */ +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_MASK) + +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_MASK (0xFFFFFE00U) +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_SHIFT (9U) +/*! gdet_evtcnt_rsvd - reserved + */ +#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_MASK) +/*! @} */ + +/*! @name CSS_GDET_EVTCNT_CLR - CSS GDET Event Counter Clear */ +/*! @{ */ + +#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_MASK (0x1U) +#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_SHIFT (0U) +/*! gdet_evtcnt_clr - 1=clear GDET event counter clear + */ +#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_SHIFT)) & CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_MASK) + +#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_MASK (0xFFFFFFFEU) +#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_SHIFT (1U) +/*! gdet_evtcnt_clr_rsvd - reserved + */ +#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_SHIFT)) & CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_MASK) +/*! @} */ + +/*! @name CSS_SHA2_STATUS - CSS SHA2 Status Register */ +/*! @{ */ + +#define CSS_CSS_SHA2_STATUS_sha2_busy_MASK (0x1U) +#define CSS_CSS_SHA2_STATUS_sha2_busy_SHIFT (0U) +/*! sha2_busy - SHA2 busy/idle status for sha direct + */ +#define CSS_CSS_SHA2_STATUS_sha2_busy(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_STATUS_sha2_busy_SHIFT)) & CSS_CSS_SHA2_STATUS_sha2_busy_MASK) + +#define CSS_CSS_SHA2_STATUS_status_rsvd1_MASK (0xFFFFFFFEU) +#define CSS_CSS_SHA2_STATUS_status_rsvd1_SHIFT (1U) +/*! status_rsvd1 - reserved + */ +#define CSS_CSS_SHA2_STATUS_status_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_STATUS_status_rsvd1_SHIFT)) & CSS_CSS_SHA2_STATUS_status_rsvd1_MASK) +/*! @} */ + +/*! @name CSS_SHA2_CTRL - SHA2 Control register */ +/*! @{ */ + +#define CSS_CSS_SHA2_CTRL_sha2_start_MASK (0x1U) +#define CSS_CSS_SHA2_CTRL_sha2_start_SHIFT (0U) +/*! sha2_start - Write to 1 to Init the SHA2 Module + */ +#define CSS_CSS_SHA2_CTRL_sha2_start(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_start_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_start_MASK) + +#define CSS_CSS_SHA2_CTRL_sha2_rst_MASK (0x2U) +#define CSS_CSS_SHA2_CTRL_sha2_rst_SHIFT (1U) +/*! sha2_rst - Write to 1 to Reset a SHA2 operation + */ +#define CSS_CSS_SHA2_CTRL_sha2_rst(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_rst_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_rst_MASK) + +#define CSS_CSS_SHA2_CTRL_sha2_init_MASK (0x4U) +#define CSS_CSS_SHA2_CTRL_sha2_init_SHIFT (2U) +/*! sha2_init - Write to 1 to Init the SHA2 Kernel + */ +#define CSS_CSS_SHA2_CTRL_sha2_init(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_init_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_init_MASK) + +#define CSS_CSS_SHA2_CTRL_sha2_load_MASK (0x8U) +#define CSS_CSS_SHA2_CTRL_sha2_load_SHIFT (3U) +/*! sha2_load - Write to 1 to Load the SHA2 Kernel + */ +#define CSS_CSS_SHA2_CTRL_sha2_load(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_load_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_load_MASK) + +#define CSS_CSS_SHA2_CTRL_sha2_mode_MASK (0x30U) +#define CSS_CSS_SHA2_CTRL_sha2_mode_SHIFT (4U) +/*! sha2_mode - SHA2 MODE: + */ +#define CSS_CSS_SHA2_CTRL_sha2_mode(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_mode_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_mode_MASK) + +#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1_MASK (0x1C0U) +#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1_SHIFT (6U) +/*! ctrl_rsvd1 - r-eserved + */ +#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_ctrl_rsvd1_SHIFT)) & CSS_CSS_SHA2_CTRL_ctrl_rsvd1_MASK) + +#define CSS_CSS_SHA2_CTRL_sha2_byte_order_MASK (0x200U) +#define CSS_CSS_SHA2_CTRL_sha2_byte_order_SHIFT (9U) +/*! sha2_byte_order - Write to 1 to Reverse byte endianess + */ +#define CSS_CSS_SHA2_CTRL_sha2_byte_order(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_byte_order_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_byte_order_MASK) + +#define CSS_CSS_SHA2_CTRL_ctrl_rsvd_MASK (0xFFFFFC00U) +#define CSS_CSS_SHA2_CTRL_ctrl_rsvd_SHIFT (10U) +/*! ctrl_rsvd - r-eserved + */ +#define CSS_CSS_SHA2_CTRL_ctrl_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_ctrl_rsvd_SHIFT)) & CSS_CSS_SHA2_CTRL_ctrl_rsvd_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DIN - CSS SHA_DATA IN Register 0 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DIN_sha_datin_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DIN_sha_datin_SHIFT (0U) +/*! sha_datin - Output CSS_SHA_DATIN from CSS Application being executed + */ +#define CSS_CSS_SHA2_DIN_sha_datin(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DIN_sha_datin_SHIFT)) & CSS_CSS_SHA2_DIN_sha_datin_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT0 - CSS CSS_SHA_DATA Out Register 0 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT0_sha_data0_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT0_sha_data0_SHIFT (0U) +/*! sha_data0 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT0_sha_data0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT0_sha_data0_SHIFT)) & CSS_CSS_SHA2_DOUT0_sha_data0_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT1 - CSS SHA_DATA Out Register 1 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT1_sha_data1_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT1_sha_data1_SHIFT (0U) +/*! sha_data1 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT1_sha_data1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT1_sha_data1_SHIFT)) & CSS_CSS_SHA2_DOUT1_sha_data1_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT2 - CSS SHA_DATA Out Register 2 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT2_sha_data2_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT2_sha_data2_SHIFT (0U) +/*! sha_data2 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT2_sha_data2(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT2_sha_data2_SHIFT)) & CSS_CSS_SHA2_DOUT2_sha_data2_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT3 - CSS SHA_DATA Out Register 3 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT3_sha_data3_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT3_sha_data3_SHIFT (0U) +/*! sha_data3 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT3_sha_data3(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT3_sha_data3_SHIFT)) & CSS_CSS_SHA2_DOUT3_sha_data3_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT4 - CSS SHA_DATA Out Register 4 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT4_sha_data4_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT4_sha_data4_SHIFT (0U) +/*! sha_data4 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT4_sha_data4(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT4_sha_data4_SHIFT)) & CSS_CSS_SHA2_DOUT4_sha_data4_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT5 - CSS SHA_DATA Out Register 5 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT5_sha_data5_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT5_sha_data5_SHIFT (0U) +/*! sha_data5 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT5_sha_data5(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT5_sha_data5_SHIFT)) & CSS_CSS_SHA2_DOUT5_sha_data5_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT6 - CSS SHA_DATA Out Register 6 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT6_sha_data6_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT6_sha_data6_SHIFT (0U) +/*! sha_data6 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT6_sha_data6(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT6_sha_data6_SHIFT)) & CSS_CSS_SHA2_DOUT6_sha_data6_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT7 - CSS SHA_DATA Out Register 7 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT7_sha_data7_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT7_sha_data7_SHIFT (0U) +/*! sha_data7 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT7_sha_data7(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT7_sha_data7_SHIFT)) & CSS_CSS_SHA2_DOUT7_sha_data7_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT8 - CSS CSS_SHA_DATA Out Register 8 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT8_sha_data8_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT8_sha_data8_SHIFT (0U) +/*! sha_data8 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT8_sha_data8(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT8_sha_data8_SHIFT)) & CSS_CSS_SHA2_DOUT8_sha_data8_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT9 - CSS SHA_DATA Out Register 9 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT9_sha_data9_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT9_sha_data9_SHIFT (0U) +/*! sha_data9 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT9_sha_data9(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT9_sha_data9_SHIFT)) & CSS_CSS_SHA2_DOUT9_sha_data9_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT10 - CSS SHA_DATA Out Register 10 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT10_sha_data10_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT10_sha_data10_SHIFT (0U) +/*! sha_data10 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT10_sha_data10(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT10_sha_data10_SHIFT)) & CSS_CSS_SHA2_DOUT10_sha_data10_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT11 - CSS SHA_DATA Out Register 11 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT11_sha_data11_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT11_sha_data11_SHIFT (0U) +/*! sha_data11 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT11_sha_data11(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT11_sha_data11_SHIFT)) & CSS_CSS_SHA2_DOUT11_sha_data11_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT12 - CSS SHA_DATA Out Register 12 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT12_sha_data12_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT12_sha_data12_SHIFT (0U) +/*! sha_data12 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT12_sha_data12(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT12_sha_data12_SHIFT)) & CSS_CSS_SHA2_DOUT12_sha_data12_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT13 - CSS SHA_DATA Out Register 13 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT13_sha_data13_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT13_sha_data13_SHIFT (0U) +/*! sha_data13 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT13_sha_data13(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT13_sha_data13_SHIFT)) & CSS_CSS_SHA2_DOUT13_sha_data13_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT14 - CSS SHA_DATA Out Register 14 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT14_sha_data14_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT14_sha_data14_SHIFT (0U) +/*! sha_data14 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT14_sha_data14(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT14_sha_data14_SHIFT)) & CSS_CSS_SHA2_DOUT14_sha_data14_MASK) +/*! @} */ + +/*! @name CSS_SHA2_DOUT15 - CSS SHA_DATA Out Register 15 */ +/*! @{ */ + +#define CSS_CSS_SHA2_DOUT15_sha_data15_MASK (0xFFFFFFFFU) +#define CSS_CSS_SHA2_DOUT15_sha_data15_SHIFT (0U) +/*! sha_data15 - Output SHA_DATA from CSS Application being executed + */ +#define CSS_CSS_SHA2_DOUT15_sha_data15(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT15_sha_data15_SHIFT)) & CSS_CSS_SHA2_DOUT15_sha_data15_MASK) +/*! @} */ + +/*! @name CSS_KS0 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS0_ks0_ksize_MASK (0x1U) +#define CSS_CSS_KS0_ks0_ksize_SHIFT (0U) +/*! ks0_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS0_ks0_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ksize_SHIFT)) & CSS_CSS_KS0_ks0_ksize_MASK) + +#define CSS_CSS_KS0_ks0_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS0_ks0_rsvd0_SHIFT (1U) +/*! ks0_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS0_ks0_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_rsvd0_SHIFT)) & CSS_CSS_KS0_ks0_rsvd0_MASK) + +#define CSS_CSS_KS0_ks0_kact_MASK (0x20U) +#define CSS_CSS_KS0_ks0_kact_SHIFT (5U) +/*! ks0_kact - Key is active + */ +#define CSS_CSS_KS0_ks0_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_kact_SHIFT)) & CSS_CSS_KS0_ks0_kact_MASK) + +#define CSS_CSS_KS0_ks0_kbase_MASK (0x40U) +#define CSS_CSS_KS0_ks0_kbase_SHIFT (6U) +/*! ks0_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS0_ks0_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_kbase_SHIFT)) & CSS_CSS_KS0_ks0_kbase_MASK) + +#define CSS_CSS_KS0_ks0_fgp_MASK (0x80U) +#define CSS_CSS_KS0_ks0_fgp_SHIFT (7U) +/*! ks0_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS0_ks0_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_fgp_SHIFT)) & CSS_CSS_KS0_ks0_fgp_MASK) + +#define CSS_CSS_KS0_ks0_frtn_MASK (0x100U) +#define CSS_CSS_KS0_ks0_frtn_SHIFT (8U) +/*! ks0_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS0_ks0_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_frtn_SHIFT)) & CSS_CSS_KS0_ks0_frtn_MASK) + +#define CSS_CSS_KS0_ks0_fhwo_MASK (0x200U) +#define CSS_CSS_KS0_ks0_fhwo_SHIFT (9U) +/*! ks0_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS0_ks0_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_fhwo_SHIFT)) & CSS_CSS_KS0_ks0_fhwo_MASK) + +#define CSS_CSS_KS0_ks0_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS0_ks0_rsvd1_SHIFT (10U) +/*! ks0_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS0_ks0_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_rsvd1_SHIFT)) & CSS_CSS_KS0_ks0_rsvd1_MASK) + +#define CSS_CSS_KS0_ks0_ucmac_MASK (0x2000U) +#define CSS_CSS_KS0_ks0_ucmac_SHIFT (13U) +/*! ks0_ucmac - CMAC key + */ +#define CSS_CSS_KS0_ks0_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ucmac_SHIFT)) & CSS_CSS_KS0_ks0_ucmac_MASK) + +#define CSS_CSS_KS0_ks0_uksk_MASK (0x4000U) +#define CSS_CSS_KS0_ks0_uksk_SHIFT (14U) +/*! ks0_uksk - KSK key + */ +#define CSS_CSS_KS0_ks0_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uksk_SHIFT)) & CSS_CSS_KS0_ks0_uksk_MASK) + +#define CSS_CSS_KS0_ks0_urtf_MASK (0x8000U) +#define CSS_CSS_KS0_ks0_urtf_SHIFT (15U) +/*! ks0_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS0_ks0_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_urtf_SHIFT)) & CSS_CSS_KS0_ks0_urtf_MASK) + +#define CSS_CSS_KS0_ks0_uckdf_MASK (0x10000U) +#define CSS_CSS_KS0_ks0_uckdf_SHIFT (16U) +/*! ks0_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS0_ks0_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uckdf_SHIFT)) & CSS_CSS_KS0_ks0_uckdf_MASK) + +#define CSS_CSS_KS0_ks0_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS0_ks0_uhkdf_SHIFT (17U) +/*! ks0_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS0_ks0_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhkdf_SHIFT)) & CSS_CSS_KS0_ks0_uhkdf_MASK) + +#define CSS_CSS_KS0_ks0_uecsg_MASK (0x40000U) +#define CSS_CSS_KS0_ks0_uecsg_SHIFT (18U) +/*! ks0_uecsg - Ecc signing key + */ +#define CSS_CSS_KS0_ks0_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uecsg_SHIFT)) & CSS_CSS_KS0_ks0_uecsg_MASK) + +#define CSS_CSS_KS0_ks0_uecdh_MASK (0x80000U) +#define CSS_CSS_KS0_ks0_uecdh_SHIFT (19U) +/*! ks0_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS0_ks0_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uecdh_SHIFT)) & CSS_CSS_KS0_ks0_uecdh_MASK) + +#define CSS_CSS_KS0_ks0_uaes_MASK (0x100000U) +#define CSS_CSS_KS0_ks0_uaes_SHIFT (20U) +/*! ks0_uaes - Aes key + */ +#define CSS_CSS_KS0_ks0_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uaes_SHIFT)) & CSS_CSS_KS0_ks0_uaes_MASK) + +#define CSS_CSS_KS0_ks0_uhmac_MASK (0x200000U) +#define CSS_CSS_KS0_ks0_uhmac_SHIFT (21U) +/*! ks0_uhmac - Hmac key + */ +#define CSS_CSS_KS0_ks0_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhmac_SHIFT)) & CSS_CSS_KS0_ks0_uhmac_MASK) + +#define CSS_CSS_KS0_ks0_ukwk_MASK (0x400000U) +#define CSS_CSS_KS0_ks0_ukwk_SHIFT (22U) +/*! ks0_ukwk - Key wrapping key + */ +#define CSS_CSS_KS0_ks0_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukwk_SHIFT)) & CSS_CSS_KS0_ks0_ukwk_MASK) + +#define CSS_CSS_KS0_ks0_ukuok_MASK (0x800000U) +#define CSS_CSS_KS0_ks0_ukuok_SHIFT (23U) +/*! ks0_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS0_ks0_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukuok_SHIFT)) & CSS_CSS_KS0_ks0_ukuok_MASK) + +#define CSS_CSS_KS0_ks0_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS0_ks0_utlspms_SHIFT (24U) +/*! ks0_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS0_ks0_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_utlspms_SHIFT)) & CSS_CSS_KS0_ks0_utlspms_MASK) + +#define CSS_CSS_KS0_ks0_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS0_ks0_utlsms_SHIFT (25U) +/*! ks0_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS0_ks0_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_utlsms_SHIFT)) & CSS_CSS_KS0_ks0_utlsms_MASK) + +#define CSS_CSS_KS0_ks0_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS0_ks0_ukgsrc_SHIFT (26U) +/*! ks0_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS0_ks0_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukgsrc_SHIFT)) & CSS_CSS_KS0_ks0_ukgsrc_MASK) + +#define CSS_CSS_KS0_ks0_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS0_ks0_uhwo_SHIFT (27U) +/*! ks0_uhwo - Hardware out key + */ +#define CSS_CSS_KS0_ks0_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhwo_SHIFT)) & CSS_CSS_KS0_ks0_uhwo_MASK) + +#define CSS_CSS_KS0_ks0_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS0_ks0_uwrpok_SHIFT (28U) +/*! ks0_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS0_ks0_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uwrpok_SHIFT)) & CSS_CSS_KS0_ks0_uwrpok_MASK) + +#define CSS_CSS_KS0_ks0_uduk_MASK (0x20000000U) +#define CSS_CSS_KS0_ks0_uduk_SHIFT (29U) +/*! ks0_uduk - Device Unique Key + */ +#define CSS_CSS_KS0_ks0_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uduk_SHIFT)) & CSS_CSS_KS0_ks0_uduk_MASK) + +#define CSS_CSS_KS0_ks0_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS0_ks0_upprot_SHIFT (30U) +/*! ks0_upprot - Priviledge level + */ +#define CSS_CSS_KS0_ks0_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_upprot_SHIFT)) & CSS_CSS_KS0_ks0_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS1 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS1_ks1_ksize_MASK (0x1U) +#define CSS_CSS_KS1_ks1_ksize_SHIFT (0U) +/*! ks1_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS1_ks1_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ksize_SHIFT)) & CSS_CSS_KS1_ks1_ksize_MASK) + +#define CSS_CSS_KS1_ks1_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS1_ks1_rsvd0_SHIFT (1U) +/*! ks1_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS1_ks1_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_rsvd0_SHIFT)) & CSS_CSS_KS1_ks1_rsvd0_MASK) + +#define CSS_CSS_KS1_ks1_kact_MASK (0x20U) +#define CSS_CSS_KS1_ks1_kact_SHIFT (5U) +/*! ks1_kact - Key is active + */ +#define CSS_CSS_KS1_ks1_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_kact_SHIFT)) & CSS_CSS_KS1_ks1_kact_MASK) + +#define CSS_CSS_KS1_ks1_kbase_MASK (0x40U) +#define CSS_CSS_KS1_ks1_kbase_SHIFT (6U) +/*! ks1_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS1_ks1_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_kbase_SHIFT)) & CSS_CSS_KS1_ks1_kbase_MASK) + +#define CSS_CSS_KS1_ks1_fgp_MASK (0x80U) +#define CSS_CSS_KS1_ks1_fgp_SHIFT (7U) +/*! ks1_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS1_ks1_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_fgp_SHIFT)) & CSS_CSS_KS1_ks1_fgp_MASK) + +#define CSS_CSS_KS1_ks1_frtn_MASK (0x100U) +#define CSS_CSS_KS1_ks1_frtn_SHIFT (8U) +/*! ks1_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS1_ks1_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_frtn_SHIFT)) & CSS_CSS_KS1_ks1_frtn_MASK) + +#define CSS_CSS_KS1_ks1_fhwo_MASK (0x200U) +#define CSS_CSS_KS1_ks1_fhwo_SHIFT (9U) +/*! ks1_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS1_ks1_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_fhwo_SHIFT)) & CSS_CSS_KS1_ks1_fhwo_MASK) + +#define CSS_CSS_KS1_ks1_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS1_ks1_rsvd1_SHIFT (10U) +/*! ks1_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS1_ks1_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_rsvd1_SHIFT)) & CSS_CSS_KS1_ks1_rsvd1_MASK) + +#define CSS_CSS_KS1_ks1_ucmac_MASK (0x2000U) +#define CSS_CSS_KS1_ks1_ucmac_SHIFT (13U) +/*! ks1_ucmac - CMAC key + */ +#define CSS_CSS_KS1_ks1_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ucmac_SHIFT)) & CSS_CSS_KS1_ks1_ucmac_MASK) + +#define CSS_CSS_KS1_ks1_uksk_MASK (0x4000U) +#define CSS_CSS_KS1_ks1_uksk_SHIFT (14U) +/*! ks1_uksk - KSK key + */ +#define CSS_CSS_KS1_ks1_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uksk_SHIFT)) & CSS_CSS_KS1_ks1_uksk_MASK) + +#define CSS_CSS_KS1_ks1_urtf_MASK (0x8000U) +#define CSS_CSS_KS1_ks1_urtf_SHIFT (15U) +/*! ks1_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS1_ks1_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_urtf_SHIFT)) & CSS_CSS_KS1_ks1_urtf_MASK) + +#define CSS_CSS_KS1_ks1_uckdf_MASK (0x10000U) +#define CSS_CSS_KS1_ks1_uckdf_SHIFT (16U) +/*! ks1_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS1_ks1_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uckdf_SHIFT)) & CSS_CSS_KS1_ks1_uckdf_MASK) + +#define CSS_CSS_KS1_ks1_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS1_ks1_uhkdf_SHIFT (17U) +/*! ks1_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS1_ks1_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhkdf_SHIFT)) & CSS_CSS_KS1_ks1_uhkdf_MASK) + +#define CSS_CSS_KS1_ks1_uecsg_MASK (0x40000U) +#define CSS_CSS_KS1_ks1_uecsg_SHIFT (18U) +/*! ks1_uecsg - Ecc signing key + */ +#define CSS_CSS_KS1_ks1_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uecsg_SHIFT)) & CSS_CSS_KS1_ks1_uecsg_MASK) + +#define CSS_CSS_KS1_ks1_uecdh_MASK (0x80000U) +#define CSS_CSS_KS1_ks1_uecdh_SHIFT (19U) +/*! ks1_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS1_ks1_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uecdh_SHIFT)) & CSS_CSS_KS1_ks1_uecdh_MASK) + +#define CSS_CSS_KS1_ks1_uaes_MASK (0x100000U) +#define CSS_CSS_KS1_ks1_uaes_SHIFT (20U) +/*! ks1_uaes - Aes key + */ +#define CSS_CSS_KS1_ks1_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uaes_SHIFT)) & CSS_CSS_KS1_ks1_uaes_MASK) + +#define CSS_CSS_KS1_ks1_uhmac_MASK (0x200000U) +#define CSS_CSS_KS1_ks1_uhmac_SHIFT (21U) +/*! ks1_uhmac - Hmac key + */ +#define CSS_CSS_KS1_ks1_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhmac_SHIFT)) & CSS_CSS_KS1_ks1_uhmac_MASK) + +#define CSS_CSS_KS1_ks1_ukwk_MASK (0x400000U) +#define CSS_CSS_KS1_ks1_ukwk_SHIFT (22U) +/*! ks1_ukwk - Key wrapping key + */ +#define CSS_CSS_KS1_ks1_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukwk_SHIFT)) & CSS_CSS_KS1_ks1_ukwk_MASK) + +#define CSS_CSS_KS1_ks1_ukuok_MASK (0x800000U) +#define CSS_CSS_KS1_ks1_ukuok_SHIFT (23U) +/*! ks1_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS1_ks1_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukuok_SHIFT)) & CSS_CSS_KS1_ks1_ukuok_MASK) + +#define CSS_CSS_KS1_ks1_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS1_ks1_utlspms_SHIFT (24U) +/*! ks1_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS1_ks1_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_utlspms_SHIFT)) & CSS_CSS_KS1_ks1_utlspms_MASK) + +#define CSS_CSS_KS1_ks1_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS1_ks1_utlsms_SHIFT (25U) +/*! ks1_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS1_ks1_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_utlsms_SHIFT)) & CSS_CSS_KS1_ks1_utlsms_MASK) + +#define CSS_CSS_KS1_ks1_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS1_ks1_ukgsrc_SHIFT (26U) +/*! ks1_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS1_ks1_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukgsrc_SHIFT)) & CSS_CSS_KS1_ks1_ukgsrc_MASK) + +#define CSS_CSS_KS1_ks1_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS1_ks1_uhwo_SHIFT (27U) +/*! ks1_uhwo - Hardware out key + */ +#define CSS_CSS_KS1_ks1_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhwo_SHIFT)) & CSS_CSS_KS1_ks1_uhwo_MASK) + +#define CSS_CSS_KS1_ks1_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS1_ks1_uwrpok_SHIFT (28U) +/*! ks1_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS1_ks1_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uwrpok_SHIFT)) & CSS_CSS_KS1_ks1_uwrpok_MASK) + +#define CSS_CSS_KS1_ks1_uduk_MASK (0x20000000U) +#define CSS_CSS_KS1_ks1_uduk_SHIFT (29U) +/*! ks1_uduk - Device Unique Key + */ +#define CSS_CSS_KS1_ks1_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uduk_SHIFT)) & CSS_CSS_KS1_ks1_uduk_MASK) + +#define CSS_CSS_KS1_ks1_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS1_ks1_upprot_SHIFT (30U) +/*! ks1_upprot - Priviledge level + */ +#define CSS_CSS_KS1_ks1_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_upprot_SHIFT)) & CSS_CSS_KS1_ks1_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS2 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS2_ks2_ksize_MASK (0x1U) +#define CSS_CSS_KS2_ks2_ksize_SHIFT (0U) +/*! ks2_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS2_ks2_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ksize_SHIFT)) & CSS_CSS_KS2_ks2_ksize_MASK) + +#define CSS_CSS_KS2_ks2_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS2_ks2_rsvd0_SHIFT (1U) +/*! ks2_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS2_ks2_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_rsvd0_SHIFT)) & CSS_CSS_KS2_ks2_rsvd0_MASK) + +#define CSS_CSS_KS2_ks2_kact_MASK (0x20U) +#define CSS_CSS_KS2_ks2_kact_SHIFT (5U) +/*! ks2_kact - Key is active + */ +#define CSS_CSS_KS2_ks2_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_kact_SHIFT)) & CSS_CSS_KS2_ks2_kact_MASK) + +#define CSS_CSS_KS2_ks2_kbase_MASK (0x40U) +#define CSS_CSS_KS2_ks2_kbase_SHIFT (6U) +/*! ks2_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS2_ks2_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_kbase_SHIFT)) & CSS_CSS_KS2_ks2_kbase_MASK) + +#define CSS_CSS_KS2_ks2_fgp_MASK (0x80U) +#define CSS_CSS_KS2_ks2_fgp_SHIFT (7U) +/*! ks2_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS2_ks2_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_fgp_SHIFT)) & CSS_CSS_KS2_ks2_fgp_MASK) + +#define CSS_CSS_KS2_ks2_frtn_MASK (0x100U) +#define CSS_CSS_KS2_ks2_frtn_SHIFT (8U) +/*! ks2_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS2_ks2_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_frtn_SHIFT)) & CSS_CSS_KS2_ks2_frtn_MASK) + +#define CSS_CSS_KS2_ks2_fhwo_MASK (0x200U) +#define CSS_CSS_KS2_ks2_fhwo_SHIFT (9U) +/*! ks2_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS2_ks2_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_fhwo_SHIFT)) & CSS_CSS_KS2_ks2_fhwo_MASK) + +#define CSS_CSS_KS2_ks2_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS2_ks2_rsvd1_SHIFT (10U) +/*! ks2_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS2_ks2_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_rsvd1_SHIFT)) & CSS_CSS_KS2_ks2_rsvd1_MASK) + +#define CSS_CSS_KS2_ks2_ucmac_MASK (0x2000U) +#define CSS_CSS_KS2_ks2_ucmac_SHIFT (13U) +/*! ks2_ucmac - CMAC key + */ +#define CSS_CSS_KS2_ks2_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ucmac_SHIFT)) & CSS_CSS_KS2_ks2_ucmac_MASK) + +#define CSS_CSS_KS2_ks2_uksk_MASK (0x4000U) +#define CSS_CSS_KS2_ks2_uksk_SHIFT (14U) +/*! ks2_uksk - KSK key + */ +#define CSS_CSS_KS2_ks2_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uksk_SHIFT)) & CSS_CSS_KS2_ks2_uksk_MASK) + +#define CSS_CSS_KS2_ks2_urtf_MASK (0x8000U) +#define CSS_CSS_KS2_ks2_urtf_SHIFT (15U) +/*! ks2_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS2_ks2_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_urtf_SHIFT)) & CSS_CSS_KS2_ks2_urtf_MASK) + +#define CSS_CSS_KS2_ks2_uckdf_MASK (0x10000U) +#define CSS_CSS_KS2_ks2_uckdf_SHIFT (16U) +/*! ks2_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS2_ks2_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uckdf_SHIFT)) & CSS_CSS_KS2_ks2_uckdf_MASK) + +#define CSS_CSS_KS2_ks2_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS2_ks2_uhkdf_SHIFT (17U) +/*! ks2_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS2_ks2_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhkdf_SHIFT)) & CSS_CSS_KS2_ks2_uhkdf_MASK) + +#define CSS_CSS_KS2_ks2_uecsg_MASK (0x40000U) +#define CSS_CSS_KS2_ks2_uecsg_SHIFT (18U) +/*! ks2_uecsg - Ecc signing key + */ +#define CSS_CSS_KS2_ks2_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uecsg_SHIFT)) & CSS_CSS_KS2_ks2_uecsg_MASK) + +#define CSS_CSS_KS2_ks2_uecdh_MASK (0x80000U) +#define CSS_CSS_KS2_ks2_uecdh_SHIFT (19U) +/*! ks2_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS2_ks2_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uecdh_SHIFT)) & CSS_CSS_KS2_ks2_uecdh_MASK) + +#define CSS_CSS_KS2_ks2_uaes_MASK (0x100000U) +#define CSS_CSS_KS2_ks2_uaes_SHIFT (20U) +/*! ks2_uaes - Aes key + */ +#define CSS_CSS_KS2_ks2_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uaes_SHIFT)) & CSS_CSS_KS2_ks2_uaes_MASK) + +#define CSS_CSS_KS2_ks2_uhmac_MASK (0x200000U) +#define CSS_CSS_KS2_ks2_uhmac_SHIFT (21U) +/*! ks2_uhmac - Hmac key + */ +#define CSS_CSS_KS2_ks2_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhmac_SHIFT)) & CSS_CSS_KS2_ks2_uhmac_MASK) + +#define CSS_CSS_KS2_ks2_ukwk_MASK (0x400000U) +#define CSS_CSS_KS2_ks2_ukwk_SHIFT (22U) +/*! ks2_ukwk - Key wrapping key + */ +#define CSS_CSS_KS2_ks2_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukwk_SHIFT)) & CSS_CSS_KS2_ks2_ukwk_MASK) + +#define CSS_CSS_KS2_ks2_ukuok_MASK (0x800000U) +#define CSS_CSS_KS2_ks2_ukuok_SHIFT (23U) +/*! ks2_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS2_ks2_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukuok_SHIFT)) & CSS_CSS_KS2_ks2_ukuok_MASK) + +#define CSS_CSS_KS2_ks2_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS2_ks2_utlspms_SHIFT (24U) +/*! ks2_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS2_ks2_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_utlspms_SHIFT)) & CSS_CSS_KS2_ks2_utlspms_MASK) + +#define CSS_CSS_KS2_ks2_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS2_ks2_utlsms_SHIFT (25U) +/*! ks2_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS2_ks2_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_utlsms_SHIFT)) & CSS_CSS_KS2_ks2_utlsms_MASK) + +#define CSS_CSS_KS2_ks2_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS2_ks2_ukgsrc_SHIFT (26U) +/*! ks2_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS2_ks2_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukgsrc_SHIFT)) & CSS_CSS_KS2_ks2_ukgsrc_MASK) + +#define CSS_CSS_KS2_ks2_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS2_ks2_uhwo_SHIFT (27U) +/*! ks2_uhwo - Hardware out key + */ +#define CSS_CSS_KS2_ks2_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhwo_SHIFT)) & CSS_CSS_KS2_ks2_uhwo_MASK) + +#define CSS_CSS_KS2_ks2_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS2_ks2_uwrpok_SHIFT (28U) +/*! ks2_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS2_ks2_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uwrpok_SHIFT)) & CSS_CSS_KS2_ks2_uwrpok_MASK) + +#define CSS_CSS_KS2_ks2_uduk_MASK (0x20000000U) +#define CSS_CSS_KS2_ks2_uduk_SHIFT (29U) +/*! ks2_uduk - Device Unique Key + */ +#define CSS_CSS_KS2_ks2_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uduk_SHIFT)) & CSS_CSS_KS2_ks2_uduk_MASK) + +#define CSS_CSS_KS2_ks2_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS2_ks2_upprot_SHIFT (30U) +/*! ks2_upprot - Priviledge level + */ +#define CSS_CSS_KS2_ks2_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_upprot_SHIFT)) & CSS_CSS_KS2_ks2_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS3 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS3_ks3_ksize_MASK (0x1U) +#define CSS_CSS_KS3_ks3_ksize_SHIFT (0U) +/*! ks3_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS3_ks3_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ksize_SHIFT)) & CSS_CSS_KS3_ks3_ksize_MASK) + +#define CSS_CSS_KS3_ks3_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS3_ks3_rsvd0_SHIFT (1U) +/*! ks3_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS3_ks3_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_rsvd0_SHIFT)) & CSS_CSS_KS3_ks3_rsvd0_MASK) + +#define CSS_CSS_KS3_ks3_kact_MASK (0x20U) +#define CSS_CSS_KS3_ks3_kact_SHIFT (5U) +/*! ks3_kact - Key is active + */ +#define CSS_CSS_KS3_ks3_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_kact_SHIFT)) & CSS_CSS_KS3_ks3_kact_MASK) + +#define CSS_CSS_KS3_ks3_kbase_MASK (0x40U) +#define CSS_CSS_KS3_ks3_kbase_SHIFT (6U) +/*! ks3_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS3_ks3_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_kbase_SHIFT)) & CSS_CSS_KS3_ks3_kbase_MASK) + +#define CSS_CSS_KS3_ks3_fgp_MASK (0x80U) +#define CSS_CSS_KS3_ks3_fgp_SHIFT (7U) +/*! ks3_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS3_ks3_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_fgp_SHIFT)) & CSS_CSS_KS3_ks3_fgp_MASK) + +#define CSS_CSS_KS3_ks3_frtn_MASK (0x100U) +#define CSS_CSS_KS3_ks3_frtn_SHIFT (8U) +/*! ks3_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS3_ks3_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_frtn_SHIFT)) & CSS_CSS_KS3_ks3_frtn_MASK) + +#define CSS_CSS_KS3_ks3_fhwo_MASK (0x200U) +#define CSS_CSS_KS3_ks3_fhwo_SHIFT (9U) +/*! ks3_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS3_ks3_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_fhwo_SHIFT)) & CSS_CSS_KS3_ks3_fhwo_MASK) + +#define CSS_CSS_KS3_ks3_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS3_ks3_rsvd1_SHIFT (10U) +/*! ks3_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS3_ks3_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_rsvd1_SHIFT)) & CSS_CSS_KS3_ks3_rsvd1_MASK) + +#define CSS_CSS_KS3_ks3_ucmac_MASK (0x2000U) +#define CSS_CSS_KS3_ks3_ucmac_SHIFT (13U) +/*! ks3_ucmac - CMAC key + */ +#define CSS_CSS_KS3_ks3_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ucmac_SHIFT)) & CSS_CSS_KS3_ks3_ucmac_MASK) + +#define CSS_CSS_KS3_ks3_uksk_MASK (0x4000U) +#define CSS_CSS_KS3_ks3_uksk_SHIFT (14U) +/*! ks3_uksk - KSK key + */ +#define CSS_CSS_KS3_ks3_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uksk_SHIFT)) & CSS_CSS_KS3_ks3_uksk_MASK) + +#define CSS_CSS_KS3_ks3_urtf_MASK (0x8000U) +#define CSS_CSS_KS3_ks3_urtf_SHIFT (15U) +/*! ks3_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS3_ks3_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_urtf_SHIFT)) & CSS_CSS_KS3_ks3_urtf_MASK) + +#define CSS_CSS_KS3_ks3_uckdf_MASK (0x10000U) +#define CSS_CSS_KS3_ks3_uckdf_SHIFT (16U) +/*! ks3_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS3_ks3_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uckdf_SHIFT)) & CSS_CSS_KS3_ks3_uckdf_MASK) + +#define CSS_CSS_KS3_ks3_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS3_ks3_uhkdf_SHIFT (17U) +/*! ks3_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS3_ks3_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhkdf_SHIFT)) & CSS_CSS_KS3_ks3_uhkdf_MASK) + +#define CSS_CSS_KS3_ks3_uecsg_MASK (0x40000U) +#define CSS_CSS_KS3_ks3_uecsg_SHIFT (18U) +/*! ks3_uecsg - Ecc signing key + */ +#define CSS_CSS_KS3_ks3_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uecsg_SHIFT)) & CSS_CSS_KS3_ks3_uecsg_MASK) + +#define CSS_CSS_KS3_ks3_uecdh_MASK (0x80000U) +#define CSS_CSS_KS3_ks3_uecdh_SHIFT (19U) +/*! ks3_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS3_ks3_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uecdh_SHIFT)) & CSS_CSS_KS3_ks3_uecdh_MASK) + +#define CSS_CSS_KS3_ks3_uaes_MASK (0x100000U) +#define CSS_CSS_KS3_ks3_uaes_SHIFT (20U) +/*! ks3_uaes - Aes key + */ +#define CSS_CSS_KS3_ks3_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uaes_SHIFT)) & CSS_CSS_KS3_ks3_uaes_MASK) + +#define CSS_CSS_KS3_ks3_uhmac_MASK (0x200000U) +#define CSS_CSS_KS3_ks3_uhmac_SHIFT (21U) +/*! ks3_uhmac - Hmac key + */ +#define CSS_CSS_KS3_ks3_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhmac_SHIFT)) & CSS_CSS_KS3_ks3_uhmac_MASK) + +#define CSS_CSS_KS3_ks3_ukwk_MASK (0x400000U) +#define CSS_CSS_KS3_ks3_ukwk_SHIFT (22U) +/*! ks3_ukwk - Key wrapping key + */ +#define CSS_CSS_KS3_ks3_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukwk_SHIFT)) & CSS_CSS_KS3_ks3_ukwk_MASK) + +#define CSS_CSS_KS3_ks3_ukuok_MASK (0x800000U) +#define CSS_CSS_KS3_ks3_ukuok_SHIFT (23U) +/*! ks3_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS3_ks3_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukuok_SHIFT)) & CSS_CSS_KS3_ks3_ukuok_MASK) + +#define CSS_CSS_KS3_ks3_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS3_ks3_utlspms_SHIFT (24U) +/*! ks3_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS3_ks3_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_utlspms_SHIFT)) & CSS_CSS_KS3_ks3_utlspms_MASK) + +#define CSS_CSS_KS3_ks3_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS3_ks3_utlsms_SHIFT (25U) +/*! ks3_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS3_ks3_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_utlsms_SHIFT)) & CSS_CSS_KS3_ks3_utlsms_MASK) + +#define CSS_CSS_KS3_ks3_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS3_ks3_ukgsrc_SHIFT (26U) +/*! ks3_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS3_ks3_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukgsrc_SHIFT)) & CSS_CSS_KS3_ks3_ukgsrc_MASK) + +#define CSS_CSS_KS3_ks3_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS3_ks3_uhwo_SHIFT (27U) +/*! ks3_uhwo - Hardware out key + */ +#define CSS_CSS_KS3_ks3_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhwo_SHIFT)) & CSS_CSS_KS3_ks3_uhwo_MASK) + +#define CSS_CSS_KS3_ks3_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS3_ks3_uwrpok_SHIFT (28U) +/*! ks3_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS3_ks3_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uwrpok_SHIFT)) & CSS_CSS_KS3_ks3_uwrpok_MASK) + +#define CSS_CSS_KS3_ks3_uduk_MASK (0x20000000U) +#define CSS_CSS_KS3_ks3_uduk_SHIFT (29U) +/*! ks3_uduk - Device Unique Key + */ +#define CSS_CSS_KS3_ks3_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uduk_SHIFT)) & CSS_CSS_KS3_ks3_uduk_MASK) + +#define CSS_CSS_KS3_ks3_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS3_ks3_upprot_SHIFT (30U) +/*! ks3_upprot - Priviledge level + */ +#define CSS_CSS_KS3_ks3_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_upprot_SHIFT)) & CSS_CSS_KS3_ks3_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS4 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS4_ks4_ksize_MASK (0x1U) +#define CSS_CSS_KS4_ks4_ksize_SHIFT (0U) +/*! ks4_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS4_ks4_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ksize_SHIFT)) & CSS_CSS_KS4_ks4_ksize_MASK) + +#define CSS_CSS_KS4_ks4_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS4_ks4_rsvd0_SHIFT (1U) +/*! ks4_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS4_ks4_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_rsvd0_SHIFT)) & CSS_CSS_KS4_ks4_rsvd0_MASK) + +#define CSS_CSS_KS4_ks4_kact_MASK (0x20U) +#define CSS_CSS_KS4_ks4_kact_SHIFT (5U) +/*! ks4_kact - Key is active + */ +#define CSS_CSS_KS4_ks4_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_kact_SHIFT)) & CSS_CSS_KS4_ks4_kact_MASK) + +#define CSS_CSS_KS4_ks4_kbase_MASK (0x40U) +#define CSS_CSS_KS4_ks4_kbase_SHIFT (6U) +/*! ks4_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS4_ks4_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_kbase_SHIFT)) & CSS_CSS_KS4_ks4_kbase_MASK) + +#define CSS_CSS_KS4_ks4_fgp_MASK (0x80U) +#define CSS_CSS_KS4_ks4_fgp_SHIFT (7U) +/*! ks4_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS4_ks4_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_fgp_SHIFT)) & CSS_CSS_KS4_ks4_fgp_MASK) + +#define CSS_CSS_KS4_ks4_frtn_MASK (0x100U) +#define CSS_CSS_KS4_ks4_frtn_SHIFT (8U) +/*! ks4_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS4_ks4_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_frtn_SHIFT)) & CSS_CSS_KS4_ks4_frtn_MASK) + +#define CSS_CSS_KS4_ks4_fhwo_MASK (0x200U) +#define CSS_CSS_KS4_ks4_fhwo_SHIFT (9U) +/*! ks4_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS4_ks4_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_fhwo_SHIFT)) & CSS_CSS_KS4_ks4_fhwo_MASK) + +#define CSS_CSS_KS4_ks4_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS4_ks4_rsvd1_SHIFT (10U) +/*! ks4_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS4_ks4_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_rsvd1_SHIFT)) & CSS_CSS_KS4_ks4_rsvd1_MASK) + +#define CSS_CSS_KS4_ks4_ucmac_MASK (0x2000U) +#define CSS_CSS_KS4_ks4_ucmac_SHIFT (13U) +/*! ks4_ucmac - CMAC key + */ +#define CSS_CSS_KS4_ks4_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ucmac_SHIFT)) & CSS_CSS_KS4_ks4_ucmac_MASK) + +#define CSS_CSS_KS4_ks4_uksk_MASK (0x4000U) +#define CSS_CSS_KS4_ks4_uksk_SHIFT (14U) +/*! ks4_uksk - KSK key + */ +#define CSS_CSS_KS4_ks4_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uksk_SHIFT)) & CSS_CSS_KS4_ks4_uksk_MASK) + +#define CSS_CSS_KS4_ks4_urtf_MASK (0x8000U) +#define CSS_CSS_KS4_ks4_urtf_SHIFT (15U) +/*! ks4_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS4_ks4_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_urtf_SHIFT)) & CSS_CSS_KS4_ks4_urtf_MASK) + +#define CSS_CSS_KS4_ks4_uckdf_MASK (0x10000U) +#define CSS_CSS_KS4_ks4_uckdf_SHIFT (16U) +/*! ks4_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS4_ks4_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uckdf_SHIFT)) & CSS_CSS_KS4_ks4_uckdf_MASK) + +#define CSS_CSS_KS4_ks4_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS4_ks4_uhkdf_SHIFT (17U) +/*! ks4_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS4_ks4_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhkdf_SHIFT)) & CSS_CSS_KS4_ks4_uhkdf_MASK) + +#define CSS_CSS_KS4_ks4_uecsg_MASK (0x40000U) +#define CSS_CSS_KS4_ks4_uecsg_SHIFT (18U) +/*! ks4_uecsg - Ecc signing key + */ +#define CSS_CSS_KS4_ks4_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uecsg_SHIFT)) & CSS_CSS_KS4_ks4_uecsg_MASK) + +#define CSS_CSS_KS4_ks4_uecdh_MASK (0x80000U) +#define CSS_CSS_KS4_ks4_uecdh_SHIFT (19U) +/*! ks4_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS4_ks4_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uecdh_SHIFT)) & CSS_CSS_KS4_ks4_uecdh_MASK) + +#define CSS_CSS_KS4_ks4_uaes_MASK (0x100000U) +#define CSS_CSS_KS4_ks4_uaes_SHIFT (20U) +/*! ks4_uaes - Aes key + */ +#define CSS_CSS_KS4_ks4_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uaes_SHIFT)) & CSS_CSS_KS4_ks4_uaes_MASK) + +#define CSS_CSS_KS4_ks4_uhmac_MASK (0x200000U) +#define CSS_CSS_KS4_ks4_uhmac_SHIFT (21U) +/*! ks4_uhmac - Hmac key + */ +#define CSS_CSS_KS4_ks4_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhmac_SHIFT)) & CSS_CSS_KS4_ks4_uhmac_MASK) + +#define CSS_CSS_KS4_ks4_ukwk_MASK (0x400000U) +#define CSS_CSS_KS4_ks4_ukwk_SHIFT (22U) +/*! ks4_ukwk - Key wrapping key + */ +#define CSS_CSS_KS4_ks4_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukwk_SHIFT)) & CSS_CSS_KS4_ks4_ukwk_MASK) + +#define CSS_CSS_KS4_ks4_ukuok_MASK (0x800000U) +#define CSS_CSS_KS4_ks4_ukuok_SHIFT (23U) +/*! ks4_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS4_ks4_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukuok_SHIFT)) & CSS_CSS_KS4_ks4_ukuok_MASK) + +#define CSS_CSS_KS4_ks4_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS4_ks4_utlspms_SHIFT (24U) +/*! ks4_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS4_ks4_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_utlspms_SHIFT)) & CSS_CSS_KS4_ks4_utlspms_MASK) + +#define CSS_CSS_KS4_ks4_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS4_ks4_utlsms_SHIFT (25U) +/*! ks4_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS4_ks4_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_utlsms_SHIFT)) & CSS_CSS_KS4_ks4_utlsms_MASK) + +#define CSS_CSS_KS4_ks4_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS4_ks4_ukgsrc_SHIFT (26U) +/*! ks4_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS4_ks4_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukgsrc_SHIFT)) & CSS_CSS_KS4_ks4_ukgsrc_MASK) + +#define CSS_CSS_KS4_ks4_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS4_ks4_uhwo_SHIFT (27U) +/*! ks4_uhwo - Hardware out key + */ +#define CSS_CSS_KS4_ks4_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhwo_SHIFT)) & CSS_CSS_KS4_ks4_uhwo_MASK) + +#define CSS_CSS_KS4_ks4_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS4_ks4_uwrpok_SHIFT (28U) +/*! ks4_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS4_ks4_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uwrpok_SHIFT)) & CSS_CSS_KS4_ks4_uwrpok_MASK) + +#define CSS_CSS_KS4_ks4_uduk_MASK (0x20000000U) +#define CSS_CSS_KS4_ks4_uduk_SHIFT (29U) +/*! ks4_uduk - Device Unique Key + */ +#define CSS_CSS_KS4_ks4_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uduk_SHIFT)) & CSS_CSS_KS4_ks4_uduk_MASK) + +#define CSS_CSS_KS4_ks4_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS4_ks4_upprot_SHIFT (30U) +/*! ks4_upprot - Priviledge level + */ +#define CSS_CSS_KS4_ks4_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_upprot_SHIFT)) & CSS_CSS_KS4_ks4_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS5 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS5_ks5_ksize_MASK (0x1U) +#define CSS_CSS_KS5_ks5_ksize_SHIFT (0U) +/*! ks5_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS5_ks5_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ksize_SHIFT)) & CSS_CSS_KS5_ks5_ksize_MASK) + +#define CSS_CSS_KS5_ks5_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS5_ks5_rsvd0_SHIFT (1U) +/*! ks5_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS5_ks5_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_rsvd0_SHIFT)) & CSS_CSS_KS5_ks5_rsvd0_MASK) + +#define CSS_CSS_KS5_ks5_kact_MASK (0x20U) +#define CSS_CSS_KS5_ks5_kact_SHIFT (5U) +/*! ks5_kact - Key is active + */ +#define CSS_CSS_KS5_ks5_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_kact_SHIFT)) & CSS_CSS_KS5_ks5_kact_MASK) + +#define CSS_CSS_KS5_ks5_kbase_MASK (0x40U) +#define CSS_CSS_KS5_ks5_kbase_SHIFT (6U) +/*! ks5_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS5_ks5_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_kbase_SHIFT)) & CSS_CSS_KS5_ks5_kbase_MASK) + +#define CSS_CSS_KS5_ks5_fgp_MASK (0x80U) +#define CSS_CSS_KS5_ks5_fgp_SHIFT (7U) +/*! ks5_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS5_ks5_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_fgp_SHIFT)) & CSS_CSS_KS5_ks5_fgp_MASK) + +#define CSS_CSS_KS5_ks5_frtn_MASK (0x100U) +#define CSS_CSS_KS5_ks5_frtn_SHIFT (8U) +/*! ks5_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS5_ks5_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_frtn_SHIFT)) & CSS_CSS_KS5_ks5_frtn_MASK) + +#define CSS_CSS_KS5_ks5_fhwo_MASK (0x200U) +#define CSS_CSS_KS5_ks5_fhwo_SHIFT (9U) +/*! ks5_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS5_ks5_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_fhwo_SHIFT)) & CSS_CSS_KS5_ks5_fhwo_MASK) + +#define CSS_CSS_KS5_ks5_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS5_ks5_rsvd1_SHIFT (10U) +/*! ks5_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS5_ks5_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_rsvd1_SHIFT)) & CSS_CSS_KS5_ks5_rsvd1_MASK) + +#define CSS_CSS_KS5_ks5_ucmac_MASK (0x2000U) +#define CSS_CSS_KS5_ks5_ucmac_SHIFT (13U) +/*! ks5_ucmac - CMAC key + */ +#define CSS_CSS_KS5_ks5_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ucmac_SHIFT)) & CSS_CSS_KS5_ks5_ucmac_MASK) + +#define CSS_CSS_KS5_ks5_uksk_MASK (0x4000U) +#define CSS_CSS_KS5_ks5_uksk_SHIFT (14U) +/*! ks5_uksk - KSK key + */ +#define CSS_CSS_KS5_ks5_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uksk_SHIFT)) & CSS_CSS_KS5_ks5_uksk_MASK) + +#define CSS_CSS_KS5_ks5_urtf_MASK (0x8000U) +#define CSS_CSS_KS5_ks5_urtf_SHIFT (15U) +/*! ks5_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS5_ks5_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_urtf_SHIFT)) & CSS_CSS_KS5_ks5_urtf_MASK) + +#define CSS_CSS_KS5_ks5_uckdf_MASK (0x10000U) +#define CSS_CSS_KS5_ks5_uckdf_SHIFT (16U) +/*! ks5_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS5_ks5_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uckdf_SHIFT)) & CSS_CSS_KS5_ks5_uckdf_MASK) + +#define CSS_CSS_KS5_ks5_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS5_ks5_uhkdf_SHIFT (17U) +/*! ks5_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS5_ks5_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhkdf_SHIFT)) & CSS_CSS_KS5_ks5_uhkdf_MASK) + +#define CSS_CSS_KS5_ks5_uecsg_MASK (0x40000U) +#define CSS_CSS_KS5_ks5_uecsg_SHIFT (18U) +/*! ks5_uecsg - Ecc signing key + */ +#define CSS_CSS_KS5_ks5_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uecsg_SHIFT)) & CSS_CSS_KS5_ks5_uecsg_MASK) + +#define CSS_CSS_KS5_ks5_uecdh_MASK (0x80000U) +#define CSS_CSS_KS5_ks5_uecdh_SHIFT (19U) +/*! ks5_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS5_ks5_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uecdh_SHIFT)) & CSS_CSS_KS5_ks5_uecdh_MASK) + +#define CSS_CSS_KS5_ks5_uaes_MASK (0x100000U) +#define CSS_CSS_KS5_ks5_uaes_SHIFT (20U) +/*! ks5_uaes - Aes key + */ +#define CSS_CSS_KS5_ks5_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uaes_SHIFT)) & CSS_CSS_KS5_ks5_uaes_MASK) + +#define CSS_CSS_KS5_ks5_uhmac_MASK (0x200000U) +#define CSS_CSS_KS5_ks5_uhmac_SHIFT (21U) +/*! ks5_uhmac - Hmac key + */ +#define CSS_CSS_KS5_ks5_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhmac_SHIFT)) & CSS_CSS_KS5_ks5_uhmac_MASK) + +#define CSS_CSS_KS5_ks5_ukwk_MASK (0x400000U) +#define CSS_CSS_KS5_ks5_ukwk_SHIFT (22U) +/*! ks5_ukwk - Key wrapping key + */ +#define CSS_CSS_KS5_ks5_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukwk_SHIFT)) & CSS_CSS_KS5_ks5_ukwk_MASK) + +#define CSS_CSS_KS5_ks5_ukuok_MASK (0x800000U) +#define CSS_CSS_KS5_ks5_ukuok_SHIFT (23U) +/*! ks5_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS5_ks5_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukuok_SHIFT)) & CSS_CSS_KS5_ks5_ukuok_MASK) + +#define CSS_CSS_KS5_ks5_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS5_ks5_utlspms_SHIFT (24U) +/*! ks5_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS5_ks5_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_utlspms_SHIFT)) & CSS_CSS_KS5_ks5_utlspms_MASK) + +#define CSS_CSS_KS5_ks5_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS5_ks5_utlsms_SHIFT (25U) +/*! ks5_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS5_ks5_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_utlsms_SHIFT)) & CSS_CSS_KS5_ks5_utlsms_MASK) + +#define CSS_CSS_KS5_ks5_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS5_ks5_ukgsrc_SHIFT (26U) +/*! ks5_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS5_ks5_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukgsrc_SHIFT)) & CSS_CSS_KS5_ks5_ukgsrc_MASK) + +#define CSS_CSS_KS5_ks5_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS5_ks5_uhwo_SHIFT (27U) +/*! ks5_uhwo - Hardware out key + */ +#define CSS_CSS_KS5_ks5_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhwo_SHIFT)) & CSS_CSS_KS5_ks5_uhwo_MASK) + +#define CSS_CSS_KS5_ks5_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS5_ks5_uwrpok_SHIFT (28U) +/*! ks5_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS5_ks5_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uwrpok_SHIFT)) & CSS_CSS_KS5_ks5_uwrpok_MASK) + +#define CSS_CSS_KS5_ks5_uduk_MASK (0x20000000U) +#define CSS_CSS_KS5_ks5_uduk_SHIFT (29U) +/*! ks5_uduk - Device Unique Key + */ +#define CSS_CSS_KS5_ks5_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uduk_SHIFT)) & CSS_CSS_KS5_ks5_uduk_MASK) + +#define CSS_CSS_KS5_ks5_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS5_ks5_upprot_SHIFT (30U) +/*! ks5_upprot - Priviledge level + */ +#define CSS_CSS_KS5_ks5_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_upprot_SHIFT)) & CSS_CSS_KS5_ks5_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS6 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS6_ks6_ksize_MASK (0x1U) +#define CSS_CSS_KS6_ks6_ksize_SHIFT (0U) +/*! ks6_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS6_ks6_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ksize_SHIFT)) & CSS_CSS_KS6_ks6_ksize_MASK) + +#define CSS_CSS_KS6_ks6_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS6_ks6_rsvd0_SHIFT (1U) +/*! ks6_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS6_ks6_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_rsvd0_SHIFT)) & CSS_CSS_KS6_ks6_rsvd0_MASK) + +#define CSS_CSS_KS6_ks6_kact_MASK (0x20U) +#define CSS_CSS_KS6_ks6_kact_SHIFT (5U) +/*! ks6_kact - Key is active + */ +#define CSS_CSS_KS6_ks6_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_kact_SHIFT)) & CSS_CSS_KS6_ks6_kact_MASK) + +#define CSS_CSS_KS6_ks6_kbase_MASK (0x40U) +#define CSS_CSS_KS6_ks6_kbase_SHIFT (6U) +/*! ks6_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS6_ks6_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_kbase_SHIFT)) & CSS_CSS_KS6_ks6_kbase_MASK) + +#define CSS_CSS_KS6_ks6_fgp_MASK (0x80U) +#define CSS_CSS_KS6_ks6_fgp_SHIFT (7U) +/*! ks6_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS6_ks6_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_fgp_SHIFT)) & CSS_CSS_KS6_ks6_fgp_MASK) + +#define CSS_CSS_KS6_ks6_frtn_MASK (0x100U) +#define CSS_CSS_KS6_ks6_frtn_SHIFT (8U) +/*! ks6_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS6_ks6_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_frtn_SHIFT)) & CSS_CSS_KS6_ks6_frtn_MASK) + +#define CSS_CSS_KS6_ks6_fhwo_MASK (0x200U) +#define CSS_CSS_KS6_ks6_fhwo_SHIFT (9U) +/*! ks6_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS6_ks6_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_fhwo_SHIFT)) & CSS_CSS_KS6_ks6_fhwo_MASK) + +#define CSS_CSS_KS6_ks6_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS6_ks6_rsvd1_SHIFT (10U) +/*! ks6_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS6_ks6_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_rsvd1_SHIFT)) & CSS_CSS_KS6_ks6_rsvd1_MASK) + +#define CSS_CSS_KS6_ks6_ucmac_MASK (0x2000U) +#define CSS_CSS_KS6_ks6_ucmac_SHIFT (13U) +/*! ks6_ucmac - CMAC key + */ +#define CSS_CSS_KS6_ks6_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ucmac_SHIFT)) & CSS_CSS_KS6_ks6_ucmac_MASK) + +#define CSS_CSS_KS6_ks6_uksk_MASK (0x4000U) +#define CSS_CSS_KS6_ks6_uksk_SHIFT (14U) +/*! ks6_uksk - KSK key + */ +#define CSS_CSS_KS6_ks6_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uksk_SHIFT)) & CSS_CSS_KS6_ks6_uksk_MASK) + +#define CSS_CSS_KS6_ks6_urtf_MASK (0x8000U) +#define CSS_CSS_KS6_ks6_urtf_SHIFT (15U) +/*! ks6_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS6_ks6_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_urtf_SHIFT)) & CSS_CSS_KS6_ks6_urtf_MASK) + +#define CSS_CSS_KS6_ks6_uckdf_MASK (0x10000U) +#define CSS_CSS_KS6_ks6_uckdf_SHIFT (16U) +/*! ks6_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS6_ks6_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uckdf_SHIFT)) & CSS_CSS_KS6_ks6_uckdf_MASK) + +#define CSS_CSS_KS6_ks6_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS6_ks6_uhkdf_SHIFT (17U) +/*! ks6_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS6_ks6_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhkdf_SHIFT)) & CSS_CSS_KS6_ks6_uhkdf_MASK) + +#define CSS_CSS_KS6_ks6_uecsg_MASK (0x40000U) +#define CSS_CSS_KS6_ks6_uecsg_SHIFT (18U) +/*! ks6_uecsg - Ecc signing key + */ +#define CSS_CSS_KS6_ks6_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uecsg_SHIFT)) & CSS_CSS_KS6_ks6_uecsg_MASK) + +#define CSS_CSS_KS6_ks6_uecdh_MASK (0x80000U) +#define CSS_CSS_KS6_ks6_uecdh_SHIFT (19U) +/*! ks6_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS6_ks6_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uecdh_SHIFT)) & CSS_CSS_KS6_ks6_uecdh_MASK) + +#define CSS_CSS_KS6_ks6_uaes_MASK (0x100000U) +#define CSS_CSS_KS6_ks6_uaes_SHIFT (20U) +/*! ks6_uaes - Aes key + */ +#define CSS_CSS_KS6_ks6_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uaes_SHIFT)) & CSS_CSS_KS6_ks6_uaes_MASK) + +#define CSS_CSS_KS6_ks6_uhmac_MASK (0x200000U) +#define CSS_CSS_KS6_ks6_uhmac_SHIFT (21U) +/*! ks6_uhmac - Hmac key + */ +#define CSS_CSS_KS6_ks6_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhmac_SHIFT)) & CSS_CSS_KS6_ks6_uhmac_MASK) + +#define CSS_CSS_KS6_ks6_ukwk_MASK (0x400000U) +#define CSS_CSS_KS6_ks6_ukwk_SHIFT (22U) +/*! ks6_ukwk - Key wrapping key + */ +#define CSS_CSS_KS6_ks6_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukwk_SHIFT)) & CSS_CSS_KS6_ks6_ukwk_MASK) + +#define CSS_CSS_KS6_ks6_ukuok_MASK (0x800000U) +#define CSS_CSS_KS6_ks6_ukuok_SHIFT (23U) +/*! ks6_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS6_ks6_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukuok_SHIFT)) & CSS_CSS_KS6_ks6_ukuok_MASK) + +#define CSS_CSS_KS6_ks6_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS6_ks6_utlspms_SHIFT (24U) +/*! ks6_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS6_ks6_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_utlspms_SHIFT)) & CSS_CSS_KS6_ks6_utlspms_MASK) + +#define CSS_CSS_KS6_ks6_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS6_ks6_utlsms_SHIFT (25U) +/*! ks6_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS6_ks6_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_utlsms_SHIFT)) & CSS_CSS_KS6_ks6_utlsms_MASK) + +#define CSS_CSS_KS6_ks6_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS6_ks6_ukgsrc_SHIFT (26U) +/*! ks6_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS6_ks6_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukgsrc_SHIFT)) & CSS_CSS_KS6_ks6_ukgsrc_MASK) + +#define CSS_CSS_KS6_ks6_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS6_ks6_uhwo_SHIFT (27U) +/*! ks6_uhwo - Hardware out key + */ +#define CSS_CSS_KS6_ks6_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhwo_SHIFT)) & CSS_CSS_KS6_ks6_uhwo_MASK) + +#define CSS_CSS_KS6_ks6_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS6_ks6_uwrpok_SHIFT (28U) +/*! ks6_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS6_ks6_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uwrpok_SHIFT)) & CSS_CSS_KS6_ks6_uwrpok_MASK) + +#define CSS_CSS_KS6_ks6_uduk_MASK (0x20000000U) +#define CSS_CSS_KS6_ks6_uduk_SHIFT (29U) +/*! ks6_uduk - Device Unique Key + */ +#define CSS_CSS_KS6_ks6_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uduk_SHIFT)) & CSS_CSS_KS6_ks6_uduk_MASK) + +#define CSS_CSS_KS6_ks6_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS6_ks6_upprot_SHIFT (30U) +/*! ks6_upprot - Priviledge level + */ +#define CSS_CSS_KS6_ks6_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_upprot_SHIFT)) & CSS_CSS_KS6_ks6_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS7 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS7_ks7_ksize_MASK (0x1U) +#define CSS_CSS_KS7_ks7_ksize_SHIFT (0U) +/*! ks7_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS7_ks7_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ksize_SHIFT)) & CSS_CSS_KS7_ks7_ksize_MASK) + +#define CSS_CSS_KS7_ks7_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS7_ks7_rsvd0_SHIFT (1U) +/*! ks7_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS7_ks7_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_rsvd0_SHIFT)) & CSS_CSS_KS7_ks7_rsvd0_MASK) + +#define CSS_CSS_KS7_ks7_kact_MASK (0x20U) +#define CSS_CSS_KS7_ks7_kact_SHIFT (5U) +/*! ks7_kact - Key is active + */ +#define CSS_CSS_KS7_ks7_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_kact_SHIFT)) & CSS_CSS_KS7_ks7_kact_MASK) + +#define CSS_CSS_KS7_ks7_kbase_MASK (0x40U) +#define CSS_CSS_KS7_ks7_kbase_SHIFT (6U) +/*! ks7_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS7_ks7_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_kbase_SHIFT)) & CSS_CSS_KS7_ks7_kbase_MASK) + +#define CSS_CSS_KS7_ks7_fgp_MASK (0x80U) +#define CSS_CSS_KS7_ks7_fgp_SHIFT (7U) +/*! ks7_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS7_ks7_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_fgp_SHIFT)) & CSS_CSS_KS7_ks7_fgp_MASK) + +#define CSS_CSS_KS7_ks7_frtn_MASK (0x100U) +#define CSS_CSS_KS7_ks7_frtn_SHIFT (8U) +/*! ks7_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS7_ks7_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_frtn_SHIFT)) & CSS_CSS_KS7_ks7_frtn_MASK) + +#define CSS_CSS_KS7_ks7_fhwo_MASK (0x200U) +#define CSS_CSS_KS7_ks7_fhwo_SHIFT (9U) +/*! ks7_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS7_ks7_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_fhwo_SHIFT)) & CSS_CSS_KS7_ks7_fhwo_MASK) + +#define CSS_CSS_KS7_ks7_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS7_ks7_rsvd1_SHIFT (10U) +/*! ks7_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS7_ks7_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_rsvd1_SHIFT)) & CSS_CSS_KS7_ks7_rsvd1_MASK) + +#define CSS_CSS_KS7_ks7_ucmac_MASK (0x2000U) +#define CSS_CSS_KS7_ks7_ucmac_SHIFT (13U) +/*! ks7_ucmac - CMAC key + */ +#define CSS_CSS_KS7_ks7_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ucmac_SHIFT)) & CSS_CSS_KS7_ks7_ucmac_MASK) + +#define CSS_CSS_KS7_ks7_uksk_MASK (0x4000U) +#define CSS_CSS_KS7_ks7_uksk_SHIFT (14U) +/*! ks7_uksk - KSK key + */ +#define CSS_CSS_KS7_ks7_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uksk_SHIFT)) & CSS_CSS_KS7_ks7_uksk_MASK) + +#define CSS_CSS_KS7_ks7_urtf_MASK (0x8000U) +#define CSS_CSS_KS7_ks7_urtf_SHIFT (15U) +/*! ks7_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS7_ks7_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_urtf_SHIFT)) & CSS_CSS_KS7_ks7_urtf_MASK) + +#define CSS_CSS_KS7_ks7_uckdf_MASK (0x10000U) +#define CSS_CSS_KS7_ks7_uckdf_SHIFT (16U) +/*! ks7_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS7_ks7_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uckdf_SHIFT)) & CSS_CSS_KS7_ks7_uckdf_MASK) + +#define CSS_CSS_KS7_ks7_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS7_ks7_uhkdf_SHIFT (17U) +/*! ks7_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS7_ks7_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhkdf_SHIFT)) & CSS_CSS_KS7_ks7_uhkdf_MASK) + +#define CSS_CSS_KS7_ks7_uecsg_MASK (0x40000U) +#define CSS_CSS_KS7_ks7_uecsg_SHIFT (18U) +/*! ks7_uecsg - Ecc signing key + */ +#define CSS_CSS_KS7_ks7_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uecsg_SHIFT)) & CSS_CSS_KS7_ks7_uecsg_MASK) + +#define CSS_CSS_KS7_ks7_uecdh_MASK (0x80000U) +#define CSS_CSS_KS7_ks7_uecdh_SHIFT (19U) +/*! ks7_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS7_ks7_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uecdh_SHIFT)) & CSS_CSS_KS7_ks7_uecdh_MASK) + +#define CSS_CSS_KS7_ks7_uaes_MASK (0x100000U) +#define CSS_CSS_KS7_ks7_uaes_SHIFT (20U) +/*! ks7_uaes - Aes key + */ +#define CSS_CSS_KS7_ks7_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uaes_SHIFT)) & CSS_CSS_KS7_ks7_uaes_MASK) + +#define CSS_CSS_KS7_ks7_uhmac_MASK (0x200000U) +#define CSS_CSS_KS7_ks7_uhmac_SHIFT (21U) +/*! ks7_uhmac - Hmac key + */ +#define CSS_CSS_KS7_ks7_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhmac_SHIFT)) & CSS_CSS_KS7_ks7_uhmac_MASK) + +#define CSS_CSS_KS7_ks7_ukwk_MASK (0x400000U) +#define CSS_CSS_KS7_ks7_ukwk_SHIFT (22U) +/*! ks7_ukwk - Key wrapping key + */ +#define CSS_CSS_KS7_ks7_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukwk_SHIFT)) & CSS_CSS_KS7_ks7_ukwk_MASK) + +#define CSS_CSS_KS7_ks7_ukuok_MASK (0x800000U) +#define CSS_CSS_KS7_ks7_ukuok_SHIFT (23U) +/*! ks7_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS7_ks7_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukuok_SHIFT)) & CSS_CSS_KS7_ks7_ukuok_MASK) + +#define CSS_CSS_KS7_ks7_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS7_ks7_utlspms_SHIFT (24U) +/*! ks7_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS7_ks7_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_utlspms_SHIFT)) & CSS_CSS_KS7_ks7_utlspms_MASK) + +#define CSS_CSS_KS7_ks7_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS7_ks7_utlsms_SHIFT (25U) +/*! ks7_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS7_ks7_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_utlsms_SHIFT)) & CSS_CSS_KS7_ks7_utlsms_MASK) + +#define CSS_CSS_KS7_ks7_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS7_ks7_ukgsrc_SHIFT (26U) +/*! ks7_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS7_ks7_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukgsrc_SHIFT)) & CSS_CSS_KS7_ks7_ukgsrc_MASK) + +#define CSS_CSS_KS7_ks7_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS7_ks7_uhwo_SHIFT (27U) +/*! ks7_uhwo - Hardware out key + */ +#define CSS_CSS_KS7_ks7_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhwo_SHIFT)) & CSS_CSS_KS7_ks7_uhwo_MASK) + +#define CSS_CSS_KS7_ks7_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS7_ks7_uwrpok_SHIFT (28U) +/*! ks7_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS7_ks7_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uwrpok_SHIFT)) & CSS_CSS_KS7_ks7_uwrpok_MASK) + +#define CSS_CSS_KS7_ks7_uduk_MASK (0x20000000U) +#define CSS_CSS_KS7_ks7_uduk_SHIFT (29U) +/*! ks7_uduk - Device Unique Key + */ +#define CSS_CSS_KS7_ks7_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uduk_SHIFT)) & CSS_CSS_KS7_ks7_uduk_MASK) + +#define CSS_CSS_KS7_ks7_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS7_ks7_upprot_SHIFT (30U) +/*! ks7_upprot - Priviledge level + */ +#define CSS_CSS_KS7_ks7_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_upprot_SHIFT)) & CSS_CSS_KS7_ks7_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS8 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS8_ks8_ksize_MASK (0x1U) +#define CSS_CSS_KS8_ks8_ksize_SHIFT (0U) +/*! ks8_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS8_ks8_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ksize_SHIFT)) & CSS_CSS_KS8_ks8_ksize_MASK) + +#define CSS_CSS_KS8_ks8_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS8_ks8_rsvd0_SHIFT (1U) +/*! ks8_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS8_ks8_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_rsvd0_SHIFT)) & CSS_CSS_KS8_ks8_rsvd0_MASK) + +#define CSS_CSS_KS8_ks8_kact_MASK (0x20U) +#define CSS_CSS_KS8_ks8_kact_SHIFT (5U) +/*! ks8_kact - Key is active + */ +#define CSS_CSS_KS8_ks8_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_kact_SHIFT)) & CSS_CSS_KS8_ks8_kact_MASK) + +#define CSS_CSS_KS8_ks8_kbase_MASK (0x40U) +#define CSS_CSS_KS8_ks8_kbase_SHIFT (6U) +/*! ks8_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS8_ks8_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_kbase_SHIFT)) & CSS_CSS_KS8_ks8_kbase_MASK) + +#define CSS_CSS_KS8_ks8_fgp_MASK (0x80U) +#define CSS_CSS_KS8_ks8_fgp_SHIFT (7U) +/*! ks8_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS8_ks8_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_fgp_SHIFT)) & CSS_CSS_KS8_ks8_fgp_MASK) + +#define CSS_CSS_KS8_ks8_frtn_MASK (0x100U) +#define CSS_CSS_KS8_ks8_frtn_SHIFT (8U) +/*! ks8_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS8_ks8_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_frtn_SHIFT)) & CSS_CSS_KS8_ks8_frtn_MASK) + +#define CSS_CSS_KS8_ks8_fhwo_MASK (0x200U) +#define CSS_CSS_KS8_ks8_fhwo_SHIFT (9U) +/*! ks8_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS8_ks8_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_fhwo_SHIFT)) & CSS_CSS_KS8_ks8_fhwo_MASK) + +#define CSS_CSS_KS8_ks8_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS8_ks8_rsvd1_SHIFT (10U) +/*! ks8_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS8_ks8_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_rsvd1_SHIFT)) & CSS_CSS_KS8_ks8_rsvd1_MASK) + +#define CSS_CSS_KS8_ks8_ucmac_MASK (0x2000U) +#define CSS_CSS_KS8_ks8_ucmac_SHIFT (13U) +/*! ks8_ucmac - CMAC key + */ +#define CSS_CSS_KS8_ks8_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ucmac_SHIFT)) & CSS_CSS_KS8_ks8_ucmac_MASK) + +#define CSS_CSS_KS8_ks8_uksk_MASK (0x4000U) +#define CSS_CSS_KS8_ks8_uksk_SHIFT (14U) +/*! ks8_uksk - KSK key + */ +#define CSS_CSS_KS8_ks8_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uksk_SHIFT)) & CSS_CSS_KS8_ks8_uksk_MASK) + +#define CSS_CSS_KS8_ks8_urtf_MASK (0x8000U) +#define CSS_CSS_KS8_ks8_urtf_SHIFT (15U) +/*! ks8_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS8_ks8_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_urtf_SHIFT)) & CSS_CSS_KS8_ks8_urtf_MASK) + +#define CSS_CSS_KS8_ks8_uckdf_MASK (0x10000U) +#define CSS_CSS_KS8_ks8_uckdf_SHIFT (16U) +/*! ks8_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS8_ks8_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uckdf_SHIFT)) & CSS_CSS_KS8_ks8_uckdf_MASK) + +#define CSS_CSS_KS8_ks8_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS8_ks8_uhkdf_SHIFT (17U) +/*! ks8_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS8_ks8_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhkdf_SHIFT)) & CSS_CSS_KS8_ks8_uhkdf_MASK) + +#define CSS_CSS_KS8_ks8_uecsg_MASK (0x40000U) +#define CSS_CSS_KS8_ks8_uecsg_SHIFT (18U) +/*! ks8_uecsg - Ecc signing key + */ +#define CSS_CSS_KS8_ks8_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uecsg_SHIFT)) & CSS_CSS_KS8_ks8_uecsg_MASK) + +#define CSS_CSS_KS8_ks8_uecdh_MASK (0x80000U) +#define CSS_CSS_KS8_ks8_uecdh_SHIFT (19U) +/*! ks8_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS8_ks8_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uecdh_SHIFT)) & CSS_CSS_KS8_ks8_uecdh_MASK) + +#define CSS_CSS_KS8_ks8_uaes_MASK (0x100000U) +#define CSS_CSS_KS8_ks8_uaes_SHIFT (20U) +/*! ks8_uaes - Aes key + */ +#define CSS_CSS_KS8_ks8_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uaes_SHIFT)) & CSS_CSS_KS8_ks8_uaes_MASK) + +#define CSS_CSS_KS8_ks8_uhmac_MASK (0x200000U) +#define CSS_CSS_KS8_ks8_uhmac_SHIFT (21U) +/*! ks8_uhmac - Hmac key + */ +#define CSS_CSS_KS8_ks8_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhmac_SHIFT)) & CSS_CSS_KS8_ks8_uhmac_MASK) + +#define CSS_CSS_KS8_ks8_ukwk_MASK (0x400000U) +#define CSS_CSS_KS8_ks8_ukwk_SHIFT (22U) +/*! ks8_ukwk - Key wrapping key + */ +#define CSS_CSS_KS8_ks8_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukwk_SHIFT)) & CSS_CSS_KS8_ks8_ukwk_MASK) + +#define CSS_CSS_KS8_ks8_ukuok_MASK (0x800000U) +#define CSS_CSS_KS8_ks8_ukuok_SHIFT (23U) +/*! ks8_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS8_ks8_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukuok_SHIFT)) & CSS_CSS_KS8_ks8_ukuok_MASK) + +#define CSS_CSS_KS8_ks8_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS8_ks8_utlspms_SHIFT (24U) +/*! ks8_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS8_ks8_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_utlspms_SHIFT)) & CSS_CSS_KS8_ks8_utlspms_MASK) + +#define CSS_CSS_KS8_ks8_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS8_ks8_utlsms_SHIFT (25U) +/*! ks8_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS8_ks8_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_utlsms_SHIFT)) & CSS_CSS_KS8_ks8_utlsms_MASK) + +#define CSS_CSS_KS8_ks8_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS8_ks8_ukgsrc_SHIFT (26U) +/*! ks8_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS8_ks8_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukgsrc_SHIFT)) & CSS_CSS_KS8_ks8_ukgsrc_MASK) + +#define CSS_CSS_KS8_ks8_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS8_ks8_uhwo_SHIFT (27U) +/*! ks8_uhwo - Hardware out key + */ +#define CSS_CSS_KS8_ks8_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhwo_SHIFT)) & CSS_CSS_KS8_ks8_uhwo_MASK) + +#define CSS_CSS_KS8_ks8_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS8_ks8_uwrpok_SHIFT (28U) +/*! ks8_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS8_ks8_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uwrpok_SHIFT)) & CSS_CSS_KS8_ks8_uwrpok_MASK) + +#define CSS_CSS_KS8_ks8_uduk_MASK (0x20000000U) +#define CSS_CSS_KS8_ks8_uduk_SHIFT (29U) +/*! ks8_uduk - Device Unique Key + */ +#define CSS_CSS_KS8_ks8_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uduk_SHIFT)) & CSS_CSS_KS8_ks8_uduk_MASK) + +#define CSS_CSS_KS8_ks8_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS8_ks8_upprot_SHIFT (30U) +/*! ks8_upprot - Priviledge level + */ +#define CSS_CSS_KS8_ks8_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_upprot_SHIFT)) & CSS_CSS_KS8_ks8_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS9 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS9_ks9_ksize_MASK (0x1U) +#define CSS_CSS_KS9_ks9_ksize_SHIFT (0U) +/*! ks9_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS9_ks9_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ksize_SHIFT)) & CSS_CSS_KS9_ks9_ksize_MASK) + +#define CSS_CSS_KS9_ks9_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS9_ks9_rsvd0_SHIFT (1U) +/*! ks9_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS9_ks9_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_rsvd0_SHIFT)) & CSS_CSS_KS9_ks9_rsvd0_MASK) + +#define CSS_CSS_KS9_ks9_kact_MASK (0x20U) +#define CSS_CSS_KS9_ks9_kact_SHIFT (5U) +/*! ks9_kact - Key is active + */ +#define CSS_CSS_KS9_ks9_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_kact_SHIFT)) & CSS_CSS_KS9_ks9_kact_MASK) + +#define CSS_CSS_KS9_ks9_kbase_MASK (0x40U) +#define CSS_CSS_KS9_ks9_kbase_SHIFT (6U) +/*! ks9_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS9_ks9_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_kbase_SHIFT)) & CSS_CSS_KS9_ks9_kbase_MASK) + +#define CSS_CSS_KS9_ks9_fgp_MASK (0x80U) +#define CSS_CSS_KS9_ks9_fgp_SHIFT (7U) +/*! ks9_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS9_ks9_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_fgp_SHIFT)) & CSS_CSS_KS9_ks9_fgp_MASK) + +#define CSS_CSS_KS9_ks9_frtn_MASK (0x100U) +#define CSS_CSS_KS9_ks9_frtn_SHIFT (8U) +/*! ks9_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS9_ks9_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_frtn_SHIFT)) & CSS_CSS_KS9_ks9_frtn_MASK) + +#define CSS_CSS_KS9_ks9_fhwo_MASK (0x200U) +#define CSS_CSS_KS9_ks9_fhwo_SHIFT (9U) +/*! ks9_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS9_ks9_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_fhwo_SHIFT)) & CSS_CSS_KS9_ks9_fhwo_MASK) + +#define CSS_CSS_KS9_ks9_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS9_ks9_rsvd1_SHIFT (10U) +/*! ks9_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS9_ks9_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_rsvd1_SHIFT)) & CSS_CSS_KS9_ks9_rsvd1_MASK) + +#define CSS_CSS_KS9_ks9_ucmac_MASK (0x2000U) +#define CSS_CSS_KS9_ks9_ucmac_SHIFT (13U) +/*! ks9_ucmac - CMAC key + */ +#define CSS_CSS_KS9_ks9_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ucmac_SHIFT)) & CSS_CSS_KS9_ks9_ucmac_MASK) + +#define CSS_CSS_KS9_ks9_uksk_MASK (0x4000U) +#define CSS_CSS_KS9_ks9_uksk_SHIFT (14U) +/*! ks9_uksk - KSK key + */ +#define CSS_CSS_KS9_ks9_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uksk_SHIFT)) & CSS_CSS_KS9_ks9_uksk_MASK) + +#define CSS_CSS_KS9_ks9_urtf_MASK (0x8000U) +#define CSS_CSS_KS9_ks9_urtf_SHIFT (15U) +/*! ks9_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS9_ks9_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_urtf_SHIFT)) & CSS_CSS_KS9_ks9_urtf_MASK) + +#define CSS_CSS_KS9_ks9_uckdf_MASK (0x10000U) +#define CSS_CSS_KS9_ks9_uckdf_SHIFT (16U) +/*! ks9_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS9_ks9_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uckdf_SHIFT)) & CSS_CSS_KS9_ks9_uckdf_MASK) + +#define CSS_CSS_KS9_ks9_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS9_ks9_uhkdf_SHIFT (17U) +/*! ks9_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS9_ks9_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhkdf_SHIFT)) & CSS_CSS_KS9_ks9_uhkdf_MASK) + +#define CSS_CSS_KS9_ks9_uecsg_MASK (0x40000U) +#define CSS_CSS_KS9_ks9_uecsg_SHIFT (18U) +/*! ks9_uecsg - Ecc signing key + */ +#define CSS_CSS_KS9_ks9_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uecsg_SHIFT)) & CSS_CSS_KS9_ks9_uecsg_MASK) + +#define CSS_CSS_KS9_ks9_uecdh_MASK (0x80000U) +#define CSS_CSS_KS9_ks9_uecdh_SHIFT (19U) +/*! ks9_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS9_ks9_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uecdh_SHIFT)) & CSS_CSS_KS9_ks9_uecdh_MASK) + +#define CSS_CSS_KS9_ks9_uaes_MASK (0x100000U) +#define CSS_CSS_KS9_ks9_uaes_SHIFT (20U) +/*! ks9_uaes - Aes key + */ +#define CSS_CSS_KS9_ks9_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uaes_SHIFT)) & CSS_CSS_KS9_ks9_uaes_MASK) + +#define CSS_CSS_KS9_ks9_uhmac_MASK (0x200000U) +#define CSS_CSS_KS9_ks9_uhmac_SHIFT (21U) +/*! ks9_uhmac - Hmac key + */ +#define CSS_CSS_KS9_ks9_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhmac_SHIFT)) & CSS_CSS_KS9_ks9_uhmac_MASK) + +#define CSS_CSS_KS9_ks9_ukwk_MASK (0x400000U) +#define CSS_CSS_KS9_ks9_ukwk_SHIFT (22U) +/*! ks9_ukwk - Key wrapping key + */ +#define CSS_CSS_KS9_ks9_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukwk_SHIFT)) & CSS_CSS_KS9_ks9_ukwk_MASK) + +#define CSS_CSS_KS9_ks9_ukuok_MASK (0x800000U) +#define CSS_CSS_KS9_ks9_ukuok_SHIFT (23U) +/*! ks9_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS9_ks9_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukuok_SHIFT)) & CSS_CSS_KS9_ks9_ukuok_MASK) + +#define CSS_CSS_KS9_ks9_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS9_ks9_utlspms_SHIFT (24U) +/*! ks9_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS9_ks9_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_utlspms_SHIFT)) & CSS_CSS_KS9_ks9_utlspms_MASK) + +#define CSS_CSS_KS9_ks9_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS9_ks9_utlsms_SHIFT (25U) +/*! ks9_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS9_ks9_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_utlsms_SHIFT)) & CSS_CSS_KS9_ks9_utlsms_MASK) + +#define CSS_CSS_KS9_ks9_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS9_ks9_ukgsrc_SHIFT (26U) +/*! ks9_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS9_ks9_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukgsrc_SHIFT)) & CSS_CSS_KS9_ks9_ukgsrc_MASK) + +#define CSS_CSS_KS9_ks9_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS9_ks9_uhwo_SHIFT (27U) +/*! ks9_uhwo - Hardware out key + */ +#define CSS_CSS_KS9_ks9_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhwo_SHIFT)) & CSS_CSS_KS9_ks9_uhwo_MASK) + +#define CSS_CSS_KS9_ks9_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS9_ks9_uwrpok_SHIFT (28U) +/*! ks9_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS9_ks9_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uwrpok_SHIFT)) & CSS_CSS_KS9_ks9_uwrpok_MASK) + +#define CSS_CSS_KS9_ks9_uduk_MASK (0x20000000U) +#define CSS_CSS_KS9_ks9_uduk_SHIFT (29U) +/*! ks9_uduk - Device Unique Key + */ +#define CSS_CSS_KS9_ks9_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uduk_SHIFT)) & CSS_CSS_KS9_ks9_uduk_MASK) + +#define CSS_CSS_KS9_ks9_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS9_ks9_upprot_SHIFT (30U) +/*! ks9_upprot - Priviledge level + */ +#define CSS_CSS_KS9_ks9_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_upprot_SHIFT)) & CSS_CSS_KS9_ks9_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS10 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS10_ks10_ksize_MASK (0x1U) +#define CSS_CSS_KS10_ks10_ksize_SHIFT (0U) +/*! ks10_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS10_ks10_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ksize_SHIFT)) & CSS_CSS_KS10_ks10_ksize_MASK) + +#define CSS_CSS_KS10_ks10_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS10_ks10_rsvd0_SHIFT (1U) +/*! ks10_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS10_ks10_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_rsvd0_SHIFT)) & CSS_CSS_KS10_ks10_rsvd0_MASK) + +#define CSS_CSS_KS10_ks10_kact_MASK (0x20U) +#define CSS_CSS_KS10_ks10_kact_SHIFT (5U) +/*! ks10_kact - Key is active + */ +#define CSS_CSS_KS10_ks10_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_kact_SHIFT)) & CSS_CSS_KS10_ks10_kact_MASK) + +#define CSS_CSS_KS10_ks10_kbase_MASK (0x40U) +#define CSS_CSS_KS10_ks10_kbase_SHIFT (6U) +/*! ks10_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS10_ks10_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_kbase_SHIFT)) & CSS_CSS_KS10_ks10_kbase_MASK) + +#define CSS_CSS_KS10_ks10_fgp_MASK (0x80U) +#define CSS_CSS_KS10_ks10_fgp_SHIFT (7U) +/*! ks10_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS10_ks10_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_fgp_SHIFT)) & CSS_CSS_KS10_ks10_fgp_MASK) + +#define CSS_CSS_KS10_ks10_frtn_MASK (0x100U) +#define CSS_CSS_KS10_ks10_frtn_SHIFT (8U) +/*! ks10_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS10_ks10_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_frtn_SHIFT)) & CSS_CSS_KS10_ks10_frtn_MASK) + +#define CSS_CSS_KS10_ks10_fhwo_MASK (0x200U) +#define CSS_CSS_KS10_ks10_fhwo_SHIFT (9U) +/*! ks10_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS10_ks10_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_fhwo_SHIFT)) & CSS_CSS_KS10_ks10_fhwo_MASK) + +#define CSS_CSS_KS10_ks10_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS10_ks10_rsvd1_SHIFT (10U) +/*! ks10_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS10_ks10_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_rsvd1_SHIFT)) & CSS_CSS_KS10_ks10_rsvd1_MASK) + +#define CSS_CSS_KS10_ks10_ucmac_MASK (0x2000U) +#define CSS_CSS_KS10_ks10_ucmac_SHIFT (13U) +/*! ks10_ucmac - CMAC key + */ +#define CSS_CSS_KS10_ks10_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ucmac_SHIFT)) & CSS_CSS_KS10_ks10_ucmac_MASK) + +#define CSS_CSS_KS10_ks10_uksk_MASK (0x4000U) +#define CSS_CSS_KS10_ks10_uksk_SHIFT (14U) +/*! ks10_uksk - KSK key + */ +#define CSS_CSS_KS10_ks10_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uksk_SHIFT)) & CSS_CSS_KS10_ks10_uksk_MASK) + +#define CSS_CSS_KS10_ks10_urtf_MASK (0x8000U) +#define CSS_CSS_KS10_ks10_urtf_SHIFT (15U) +/*! ks10_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS10_ks10_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_urtf_SHIFT)) & CSS_CSS_KS10_ks10_urtf_MASK) + +#define CSS_CSS_KS10_ks10_uckdf_MASK (0x10000U) +#define CSS_CSS_KS10_ks10_uckdf_SHIFT (16U) +/*! ks10_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS10_ks10_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uckdf_SHIFT)) & CSS_CSS_KS10_ks10_uckdf_MASK) + +#define CSS_CSS_KS10_ks10_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS10_ks10_uhkdf_SHIFT (17U) +/*! ks10_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS10_ks10_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhkdf_SHIFT)) & CSS_CSS_KS10_ks10_uhkdf_MASK) + +#define CSS_CSS_KS10_ks10_uecsg_MASK (0x40000U) +#define CSS_CSS_KS10_ks10_uecsg_SHIFT (18U) +/*! ks10_uecsg - Ecc signing key + */ +#define CSS_CSS_KS10_ks10_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uecsg_SHIFT)) & CSS_CSS_KS10_ks10_uecsg_MASK) + +#define CSS_CSS_KS10_ks10_uecdh_MASK (0x80000U) +#define CSS_CSS_KS10_ks10_uecdh_SHIFT (19U) +/*! ks10_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS10_ks10_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uecdh_SHIFT)) & CSS_CSS_KS10_ks10_uecdh_MASK) + +#define CSS_CSS_KS10_ks10_uaes_MASK (0x100000U) +#define CSS_CSS_KS10_ks10_uaes_SHIFT (20U) +/*! ks10_uaes - Aes key + */ +#define CSS_CSS_KS10_ks10_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uaes_SHIFT)) & CSS_CSS_KS10_ks10_uaes_MASK) + +#define CSS_CSS_KS10_ks10_uhmac_MASK (0x200000U) +#define CSS_CSS_KS10_ks10_uhmac_SHIFT (21U) +/*! ks10_uhmac - Hmac key + */ +#define CSS_CSS_KS10_ks10_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhmac_SHIFT)) & CSS_CSS_KS10_ks10_uhmac_MASK) + +#define CSS_CSS_KS10_ks10_ukwk_MASK (0x400000U) +#define CSS_CSS_KS10_ks10_ukwk_SHIFT (22U) +/*! ks10_ukwk - Key wrapping key + */ +#define CSS_CSS_KS10_ks10_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukwk_SHIFT)) & CSS_CSS_KS10_ks10_ukwk_MASK) + +#define CSS_CSS_KS10_ks10_ukuok_MASK (0x800000U) +#define CSS_CSS_KS10_ks10_ukuok_SHIFT (23U) +/*! ks10_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS10_ks10_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukuok_SHIFT)) & CSS_CSS_KS10_ks10_ukuok_MASK) + +#define CSS_CSS_KS10_ks10_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS10_ks10_utlspms_SHIFT (24U) +/*! ks10_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS10_ks10_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_utlspms_SHIFT)) & CSS_CSS_KS10_ks10_utlspms_MASK) + +#define CSS_CSS_KS10_ks10_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS10_ks10_utlsms_SHIFT (25U) +/*! ks10_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS10_ks10_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_utlsms_SHIFT)) & CSS_CSS_KS10_ks10_utlsms_MASK) + +#define CSS_CSS_KS10_ks10_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS10_ks10_ukgsrc_SHIFT (26U) +/*! ks10_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS10_ks10_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukgsrc_SHIFT)) & CSS_CSS_KS10_ks10_ukgsrc_MASK) + +#define CSS_CSS_KS10_ks10_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS10_ks10_uhwo_SHIFT (27U) +/*! ks10_uhwo - Hardware out key + */ +#define CSS_CSS_KS10_ks10_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhwo_SHIFT)) & CSS_CSS_KS10_ks10_uhwo_MASK) + +#define CSS_CSS_KS10_ks10_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS10_ks10_uwrpok_SHIFT (28U) +/*! ks10_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS10_ks10_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uwrpok_SHIFT)) & CSS_CSS_KS10_ks10_uwrpok_MASK) + +#define CSS_CSS_KS10_ks10_uduk_MASK (0x20000000U) +#define CSS_CSS_KS10_ks10_uduk_SHIFT (29U) +/*! ks10_uduk - Device Unique Key + */ +#define CSS_CSS_KS10_ks10_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uduk_SHIFT)) & CSS_CSS_KS10_ks10_uduk_MASK) + +#define CSS_CSS_KS10_ks10_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS10_ks10_upprot_SHIFT (30U) +/*! ks10_upprot - Priviledge level + */ +#define CSS_CSS_KS10_ks10_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_upprot_SHIFT)) & CSS_CSS_KS10_ks10_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS11 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS11_ks11_ksize_MASK (0x1U) +#define CSS_CSS_KS11_ks11_ksize_SHIFT (0U) +/*! ks11_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS11_ks11_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ksize_SHIFT)) & CSS_CSS_KS11_ks11_ksize_MASK) + +#define CSS_CSS_KS11_ks11_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS11_ks11_rsvd0_SHIFT (1U) +/*! ks11_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS11_ks11_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_rsvd0_SHIFT)) & CSS_CSS_KS11_ks11_rsvd0_MASK) + +#define CSS_CSS_KS11_ks11_kact_MASK (0x20U) +#define CSS_CSS_KS11_ks11_kact_SHIFT (5U) +/*! ks11_kact - Key is active + */ +#define CSS_CSS_KS11_ks11_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_kact_SHIFT)) & CSS_CSS_KS11_ks11_kact_MASK) + +#define CSS_CSS_KS11_ks11_kbase_MASK (0x40U) +#define CSS_CSS_KS11_ks11_kbase_SHIFT (6U) +/*! ks11_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS11_ks11_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_kbase_SHIFT)) & CSS_CSS_KS11_ks11_kbase_MASK) + +#define CSS_CSS_KS11_ks11_fgp_MASK (0x80U) +#define CSS_CSS_KS11_ks11_fgp_SHIFT (7U) +/*! ks11_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS11_ks11_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_fgp_SHIFT)) & CSS_CSS_KS11_ks11_fgp_MASK) + +#define CSS_CSS_KS11_ks11_frtn_MASK (0x100U) +#define CSS_CSS_KS11_ks11_frtn_SHIFT (8U) +/*! ks11_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS11_ks11_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_frtn_SHIFT)) & CSS_CSS_KS11_ks11_frtn_MASK) + +#define CSS_CSS_KS11_ks11_fhwo_MASK (0x200U) +#define CSS_CSS_KS11_ks11_fhwo_SHIFT (9U) +/*! ks11_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS11_ks11_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_fhwo_SHIFT)) & CSS_CSS_KS11_ks11_fhwo_MASK) + +#define CSS_CSS_KS11_ks11_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS11_ks11_rsvd1_SHIFT (10U) +/*! ks11_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS11_ks11_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_rsvd1_SHIFT)) & CSS_CSS_KS11_ks11_rsvd1_MASK) + +#define CSS_CSS_KS11_ks11_ucmac_MASK (0x2000U) +#define CSS_CSS_KS11_ks11_ucmac_SHIFT (13U) +/*! ks11_ucmac - CMAC key + */ +#define CSS_CSS_KS11_ks11_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ucmac_SHIFT)) & CSS_CSS_KS11_ks11_ucmac_MASK) + +#define CSS_CSS_KS11_ks11_uksk_MASK (0x4000U) +#define CSS_CSS_KS11_ks11_uksk_SHIFT (14U) +/*! ks11_uksk - KSK key + */ +#define CSS_CSS_KS11_ks11_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uksk_SHIFT)) & CSS_CSS_KS11_ks11_uksk_MASK) + +#define CSS_CSS_KS11_ks11_urtf_MASK (0x8000U) +#define CSS_CSS_KS11_ks11_urtf_SHIFT (15U) +/*! ks11_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS11_ks11_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_urtf_SHIFT)) & CSS_CSS_KS11_ks11_urtf_MASK) + +#define CSS_CSS_KS11_ks11_uckdf_MASK (0x10000U) +#define CSS_CSS_KS11_ks11_uckdf_SHIFT (16U) +/*! ks11_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS11_ks11_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uckdf_SHIFT)) & CSS_CSS_KS11_ks11_uckdf_MASK) + +#define CSS_CSS_KS11_ks11_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS11_ks11_uhkdf_SHIFT (17U) +/*! ks11_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS11_ks11_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhkdf_SHIFT)) & CSS_CSS_KS11_ks11_uhkdf_MASK) + +#define CSS_CSS_KS11_ks11_uecsg_MASK (0x40000U) +#define CSS_CSS_KS11_ks11_uecsg_SHIFT (18U) +/*! ks11_uecsg - Ecc signing key + */ +#define CSS_CSS_KS11_ks11_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uecsg_SHIFT)) & CSS_CSS_KS11_ks11_uecsg_MASK) + +#define CSS_CSS_KS11_ks11_uecdh_MASK (0x80000U) +#define CSS_CSS_KS11_ks11_uecdh_SHIFT (19U) +/*! ks11_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS11_ks11_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uecdh_SHIFT)) & CSS_CSS_KS11_ks11_uecdh_MASK) + +#define CSS_CSS_KS11_ks11_uaes_MASK (0x100000U) +#define CSS_CSS_KS11_ks11_uaes_SHIFT (20U) +/*! ks11_uaes - Aes key + */ +#define CSS_CSS_KS11_ks11_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uaes_SHIFT)) & CSS_CSS_KS11_ks11_uaes_MASK) + +#define CSS_CSS_KS11_ks11_uhmac_MASK (0x200000U) +#define CSS_CSS_KS11_ks11_uhmac_SHIFT (21U) +/*! ks11_uhmac - Hmac key + */ +#define CSS_CSS_KS11_ks11_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhmac_SHIFT)) & CSS_CSS_KS11_ks11_uhmac_MASK) + +#define CSS_CSS_KS11_ks11_ukwk_MASK (0x400000U) +#define CSS_CSS_KS11_ks11_ukwk_SHIFT (22U) +/*! ks11_ukwk - Key wrapping key + */ +#define CSS_CSS_KS11_ks11_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukwk_SHIFT)) & CSS_CSS_KS11_ks11_ukwk_MASK) + +#define CSS_CSS_KS11_ks11_ukuok_MASK (0x800000U) +#define CSS_CSS_KS11_ks11_ukuok_SHIFT (23U) +/*! ks11_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS11_ks11_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukuok_SHIFT)) & CSS_CSS_KS11_ks11_ukuok_MASK) + +#define CSS_CSS_KS11_ks11_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS11_ks11_utlspms_SHIFT (24U) +/*! ks11_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS11_ks11_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_utlspms_SHIFT)) & CSS_CSS_KS11_ks11_utlspms_MASK) + +#define CSS_CSS_KS11_ks11_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS11_ks11_utlsms_SHIFT (25U) +/*! ks11_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS11_ks11_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_utlsms_SHIFT)) & CSS_CSS_KS11_ks11_utlsms_MASK) + +#define CSS_CSS_KS11_ks11_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS11_ks11_ukgsrc_SHIFT (26U) +/*! ks11_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS11_ks11_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukgsrc_SHIFT)) & CSS_CSS_KS11_ks11_ukgsrc_MASK) + +#define CSS_CSS_KS11_ks11_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS11_ks11_uhwo_SHIFT (27U) +/*! ks11_uhwo - Hardware out key + */ +#define CSS_CSS_KS11_ks11_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhwo_SHIFT)) & CSS_CSS_KS11_ks11_uhwo_MASK) + +#define CSS_CSS_KS11_ks11_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS11_ks11_uwrpok_SHIFT (28U) +/*! ks11_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS11_ks11_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uwrpok_SHIFT)) & CSS_CSS_KS11_ks11_uwrpok_MASK) + +#define CSS_CSS_KS11_ks11_uduk_MASK (0x20000000U) +#define CSS_CSS_KS11_ks11_uduk_SHIFT (29U) +/*! ks11_uduk - Device Unique Key + */ +#define CSS_CSS_KS11_ks11_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uduk_SHIFT)) & CSS_CSS_KS11_ks11_uduk_MASK) + +#define CSS_CSS_KS11_ks11_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS11_ks11_upprot_SHIFT (30U) +/*! ks11_upprot - Priviledge level + */ +#define CSS_CSS_KS11_ks11_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_upprot_SHIFT)) & CSS_CSS_KS11_ks11_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS12 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS12_ks12_ksize_MASK (0x1U) +#define CSS_CSS_KS12_ks12_ksize_SHIFT (0U) +/*! ks12_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS12_ks12_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ksize_SHIFT)) & CSS_CSS_KS12_ks12_ksize_MASK) + +#define CSS_CSS_KS12_ks12_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS12_ks12_rsvd0_SHIFT (1U) +/*! ks12_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS12_ks12_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_rsvd0_SHIFT)) & CSS_CSS_KS12_ks12_rsvd0_MASK) + +#define CSS_CSS_KS12_ks12_kact_MASK (0x20U) +#define CSS_CSS_KS12_ks12_kact_SHIFT (5U) +/*! ks12_kact - Key is active + */ +#define CSS_CSS_KS12_ks12_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_kact_SHIFT)) & CSS_CSS_KS12_ks12_kact_MASK) + +#define CSS_CSS_KS12_ks12_kbase_MASK (0x40U) +#define CSS_CSS_KS12_ks12_kbase_SHIFT (6U) +/*! ks12_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS12_ks12_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_kbase_SHIFT)) & CSS_CSS_KS12_ks12_kbase_MASK) + +#define CSS_CSS_KS12_ks12_fgp_MASK (0x80U) +#define CSS_CSS_KS12_ks12_fgp_SHIFT (7U) +/*! ks12_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS12_ks12_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_fgp_SHIFT)) & CSS_CSS_KS12_ks12_fgp_MASK) + +#define CSS_CSS_KS12_ks12_frtn_MASK (0x100U) +#define CSS_CSS_KS12_ks12_frtn_SHIFT (8U) +/*! ks12_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS12_ks12_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_frtn_SHIFT)) & CSS_CSS_KS12_ks12_frtn_MASK) + +#define CSS_CSS_KS12_ks12_fhwo_MASK (0x200U) +#define CSS_CSS_KS12_ks12_fhwo_SHIFT (9U) +/*! ks12_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS12_ks12_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_fhwo_SHIFT)) & CSS_CSS_KS12_ks12_fhwo_MASK) + +#define CSS_CSS_KS12_ks12_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS12_ks12_rsvd1_SHIFT (10U) +/*! ks12_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS12_ks12_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_rsvd1_SHIFT)) & CSS_CSS_KS12_ks12_rsvd1_MASK) + +#define CSS_CSS_KS12_ks12_ucmac_MASK (0x2000U) +#define CSS_CSS_KS12_ks12_ucmac_SHIFT (13U) +/*! ks12_ucmac - CMAC key + */ +#define CSS_CSS_KS12_ks12_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ucmac_SHIFT)) & CSS_CSS_KS12_ks12_ucmac_MASK) + +#define CSS_CSS_KS12_ks12_uksk_MASK (0x4000U) +#define CSS_CSS_KS12_ks12_uksk_SHIFT (14U) +/*! ks12_uksk - KSK key + */ +#define CSS_CSS_KS12_ks12_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uksk_SHIFT)) & CSS_CSS_KS12_ks12_uksk_MASK) + +#define CSS_CSS_KS12_ks12_urtf_MASK (0x8000U) +#define CSS_CSS_KS12_ks12_urtf_SHIFT (15U) +/*! ks12_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS12_ks12_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_urtf_SHIFT)) & CSS_CSS_KS12_ks12_urtf_MASK) + +#define CSS_CSS_KS12_ks12_uckdf_MASK (0x10000U) +#define CSS_CSS_KS12_ks12_uckdf_SHIFT (16U) +/*! ks12_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS12_ks12_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uckdf_SHIFT)) & CSS_CSS_KS12_ks12_uckdf_MASK) + +#define CSS_CSS_KS12_ks12_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS12_ks12_uhkdf_SHIFT (17U) +/*! ks12_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS12_ks12_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhkdf_SHIFT)) & CSS_CSS_KS12_ks12_uhkdf_MASK) + +#define CSS_CSS_KS12_ks12_uecsg_MASK (0x40000U) +#define CSS_CSS_KS12_ks12_uecsg_SHIFT (18U) +/*! ks12_uecsg - Ecc signing key + */ +#define CSS_CSS_KS12_ks12_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uecsg_SHIFT)) & CSS_CSS_KS12_ks12_uecsg_MASK) + +#define CSS_CSS_KS12_ks12_uecdh_MASK (0x80000U) +#define CSS_CSS_KS12_ks12_uecdh_SHIFT (19U) +/*! ks12_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS12_ks12_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uecdh_SHIFT)) & CSS_CSS_KS12_ks12_uecdh_MASK) + +#define CSS_CSS_KS12_ks12_uaes_MASK (0x100000U) +#define CSS_CSS_KS12_ks12_uaes_SHIFT (20U) +/*! ks12_uaes - Aes key + */ +#define CSS_CSS_KS12_ks12_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uaes_SHIFT)) & CSS_CSS_KS12_ks12_uaes_MASK) + +#define CSS_CSS_KS12_ks12_uhmac_MASK (0x200000U) +#define CSS_CSS_KS12_ks12_uhmac_SHIFT (21U) +/*! ks12_uhmac - Hmac key + */ +#define CSS_CSS_KS12_ks12_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhmac_SHIFT)) & CSS_CSS_KS12_ks12_uhmac_MASK) + +#define CSS_CSS_KS12_ks12_ukwk_MASK (0x400000U) +#define CSS_CSS_KS12_ks12_ukwk_SHIFT (22U) +/*! ks12_ukwk - Key wrapping key + */ +#define CSS_CSS_KS12_ks12_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukwk_SHIFT)) & CSS_CSS_KS12_ks12_ukwk_MASK) + +#define CSS_CSS_KS12_ks12_ukuok_MASK (0x800000U) +#define CSS_CSS_KS12_ks12_ukuok_SHIFT (23U) +/*! ks12_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS12_ks12_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukuok_SHIFT)) & CSS_CSS_KS12_ks12_ukuok_MASK) + +#define CSS_CSS_KS12_ks12_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS12_ks12_utlspms_SHIFT (24U) +/*! ks12_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS12_ks12_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_utlspms_SHIFT)) & CSS_CSS_KS12_ks12_utlspms_MASK) + +#define CSS_CSS_KS12_ks12_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS12_ks12_utlsms_SHIFT (25U) +/*! ks12_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS12_ks12_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_utlsms_SHIFT)) & CSS_CSS_KS12_ks12_utlsms_MASK) + +#define CSS_CSS_KS12_ks12_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS12_ks12_ukgsrc_SHIFT (26U) +/*! ks12_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS12_ks12_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukgsrc_SHIFT)) & CSS_CSS_KS12_ks12_ukgsrc_MASK) + +#define CSS_CSS_KS12_ks12_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS12_ks12_uhwo_SHIFT (27U) +/*! ks12_uhwo - Hardware out key + */ +#define CSS_CSS_KS12_ks12_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhwo_SHIFT)) & CSS_CSS_KS12_ks12_uhwo_MASK) + +#define CSS_CSS_KS12_ks12_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS12_ks12_uwrpok_SHIFT (28U) +/*! ks12_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS12_ks12_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uwrpok_SHIFT)) & CSS_CSS_KS12_ks12_uwrpok_MASK) + +#define CSS_CSS_KS12_ks12_uduk_MASK (0x20000000U) +#define CSS_CSS_KS12_ks12_uduk_SHIFT (29U) +/*! ks12_uduk - Device Unique Key + */ +#define CSS_CSS_KS12_ks12_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uduk_SHIFT)) & CSS_CSS_KS12_ks12_uduk_MASK) + +#define CSS_CSS_KS12_ks12_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS12_ks12_upprot_SHIFT (30U) +/*! ks12_upprot - Priviledge level + */ +#define CSS_CSS_KS12_ks12_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_upprot_SHIFT)) & CSS_CSS_KS12_ks12_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS13 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS13_ks13_ksize_MASK (0x1U) +#define CSS_CSS_KS13_ks13_ksize_SHIFT (0U) +/*! ks13_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS13_ks13_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ksize_SHIFT)) & CSS_CSS_KS13_ks13_ksize_MASK) + +#define CSS_CSS_KS13_ks13_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS13_ks13_rsvd0_SHIFT (1U) +/*! ks13_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS13_ks13_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_rsvd0_SHIFT)) & CSS_CSS_KS13_ks13_rsvd0_MASK) + +#define CSS_CSS_KS13_ks13_kact_MASK (0x20U) +#define CSS_CSS_KS13_ks13_kact_SHIFT (5U) +/*! ks13_kact - Key is active + */ +#define CSS_CSS_KS13_ks13_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_kact_SHIFT)) & CSS_CSS_KS13_ks13_kact_MASK) + +#define CSS_CSS_KS13_ks13_kbase_MASK (0x40U) +#define CSS_CSS_KS13_ks13_kbase_SHIFT (6U) +/*! ks13_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS13_ks13_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_kbase_SHIFT)) & CSS_CSS_KS13_ks13_kbase_MASK) + +#define CSS_CSS_KS13_ks13_fgp_MASK (0x80U) +#define CSS_CSS_KS13_ks13_fgp_SHIFT (7U) +/*! ks13_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS13_ks13_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_fgp_SHIFT)) & CSS_CSS_KS13_ks13_fgp_MASK) + +#define CSS_CSS_KS13_ks13_frtn_MASK (0x100U) +#define CSS_CSS_KS13_ks13_frtn_SHIFT (8U) +/*! ks13_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS13_ks13_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_frtn_SHIFT)) & CSS_CSS_KS13_ks13_frtn_MASK) + +#define CSS_CSS_KS13_ks13_fhwo_MASK (0x200U) +#define CSS_CSS_KS13_ks13_fhwo_SHIFT (9U) +/*! ks13_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS13_ks13_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_fhwo_SHIFT)) & CSS_CSS_KS13_ks13_fhwo_MASK) + +#define CSS_CSS_KS13_ks13_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS13_ks13_rsvd1_SHIFT (10U) +/*! ks13_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS13_ks13_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_rsvd1_SHIFT)) & CSS_CSS_KS13_ks13_rsvd1_MASK) + +#define CSS_CSS_KS13_ks13_ucmac_MASK (0x2000U) +#define CSS_CSS_KS13_ks13_ucmac_SHIFT (13U) +/*! ks13_ucmac - CMAC key + */ +#define CSS_CSS_KS13_ks13_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ucmac_SHIFT)) & CSS_CSS_KS13_ks13_ucmac_MASK) + +#define CSS_CSS_KS13_ks13_uksk_MASK (0x4000U) +#define CSS_CSS_KS13_ks13_uksk_SHIFT (14U) +/*! ks13_uksk - KSK key + */ +#define CSS_CSS_KS13_ks13_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uksk_SHIFT)) & CSS_CSS_KS13_ks13_uksk_MASK) + +#define CSS_CSS_KS13_ks13_urtf_MASK (0x8000U) +#define CSS_CSS_KS13_ks13_urtf_SHIFT (15U) +/*! ks13_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS13_ks13_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_urtf_SHIFT)) & CSS_CSS_KS13_ks13_urtf_MASK) + +#define CSS_CSS_KS13_ks13_uckdf_MASK (0x10000U) +#define CSS_CSS_KS13_ks13_uckdf_SHIFT (16U) +/*! ks13_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS13_ks13_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uckdf_SHIFT)) & CSS_CSS_KS13_ks13_uckdf_MASK) + +#define CSS_CSS_KS13_ks13_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS13_ks13_uhkdf_SHIFT (17U) +/*! ks13_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS13_ks13_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhkdf_SHIFT)) & CSS_CSS_KS13_ks13_uhkdf_MASK) + +#define CSS_CSS_KS13_ks13_uecsg_MASK (0x40000U) +#define CSS_CSS_KS13_ks13_uecsg_SHIFT (18U) +/*! ks13_uecsg - Ecc signing key + */ +#define CSS_CSS_KS13_ks13_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uecsg_SHIFT)) & CSS_CSS_KS13_ks13_uecsg_MASK) + +#define CSS_CSS_KS13_ks13_uecdh_MASK (0x80000U) +#define CSS_CSS_KS13_ks13_uecdh_SHIFT (19U) +/*! ks13_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS13_ks13_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uecdh_SHIFT)) & CSS_CSS_KS13_ks13_uecdh_MASK) + +#define CSS_CSS_KS13_ks13_uaes_MASK (0x100000U) +#define CSS_CSS_KS13_ks13_uaes_SHIFT (20U) +/*! ks13_uaes - Aes key + */ +#define CSS_CSS_KS13_ks13_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uaes_SHIFT)) & CSS_CSS_KS13_ks13_uaes_MASK) + +#define CSS_CSS_KS13_ks13_uhmac_MASK (0x200000U) +#define CSS_CSS_KS13_ks13_uhmac_SHIFT (21U) +/*! ks13_uhmac - Hmac key + */ +#define CSS_CSS_KS13_ks13_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhmac_SHIFT)) & CSS_CSS_KS13_ks13_uhmac_MASK) + +#define CSS_CSS_KS13_ks13_ukwk_MASK (0x400000U) +#define CSS_CSS_KS13_ks13_ukwk_SHIFT (22U) +/*! ks13_ukwk - Key wrapping key + */ +#define CSS_CSS_KS13_ks13_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukwk_SHIFT)) & CSS_CSS_KS13_ks13_ukwk_MASK) + +#define CSS_CSS_KS13_ks13_ukuok_MASK (0x800000U) +#define CSS_CSS_KS13_ks13_ukuok_SHIFT (23U) +/*! ks13_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS13_ks13_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukuok_SHIFT)) & CSS_CSS_KS13_ks13_ukuok_MASK) + +#define CSS_CSS_KS13_ks13_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS13_ks13_utlspms_SHIFT (24U) +/*! ks13_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS13_ks13_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_utlspms_SHIFT)) & CSS_CSS_KS13_ks13_utlspms_MASK) + +#define CSS_CSS_KS13_ks13_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS13_ks13_utlsms_SHIFT (25U) +/*! ks13_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS13_ks13_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_utlsms_SHIFT)) & CSS_CSS_KS13_ks13_utlsms_MASK) + +#define CSS_CSS_KS13_ks13_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS13_ks13_ukgsrc_SHIFT (26U) +/*! ks13_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS13_ks13_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukgsrc_SHIFT)) & CSS_CSS_KS13_ks13_ukgsrc_MASK) + +#define CSS_CSS_KS13_ks13_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS13_ks13_uhwo_SHIFT (27U) +/*! ks13_uhwo - Hardware out key + */ +#define CSS_CSS_KS13_ks13_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhwo_SHIFT)) & CSS_CSS_KS13_ks13_uhwo_MASK) + +#define CSS_CSS_KS13_ks13_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS13_ks13_uwrpok_SHIFT (28U) +/*! ks13_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS13_ks13_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uwrpok_SHIFT)) & CSS_CSS_KS13_ks13_uwrpok_MASK) + +#define CSS_CSS_KS13_ks13_uduk_MASK (0x20000000U) +#define CSS_CSS_KS13_ks13_uduk_SHIFT (29U) +/*! ks13_uduk - Device Unique Key + */ +#define CSS_CSS_KS13_ks13_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uduk_SHIFT)) & CSS_CSS_KS13_ks13_uduk_MASK) + +#define CSS_CSS_KS13_ks13_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS13_ks13_upprot_SHIFT (30U) +/*! ks13_upprot - Priviledge level + */ +#define CSS_CSS_KS13_ks13_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_upprot_SHIFT)) & CSS_CSS_KS13_ks13_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS14 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS14_ks14_ksize_MASK (0x1U) +#define CSS_CSS_KS14_ks14_ksize_SHIFT (0U) +/*! ks14_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS14_ks14_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ksize_SHIFT)) & CSS_CSS_KS14_ks14_ksize_MASK) + +#define CSS_CSS_KS14_ks14_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS14_ks14_rsvd0_SHIFT (1U) +/*! ks14_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS14_ks14_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_rsvd0_SHIFT)) & CSS_CSS_KS14_ks14_rsvd0_MASK) + +#define CSS_CSS_KS14_ks14_kact_MASK (0x20U) +#define CSS_CSS_KS14_ks14_kact_SHIFT (5U) +/*! ks14_kact - Key is active + */ +#define CSS_CSS_KS14_ks14_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_kact_SHIFT)) & CSS_CSS_KS14_ks14_kact_MASK) + +#define CSS_CSS_KS14_ks14_kbase_MASK (0x40U) +#define CSS_CSS_KS14_ks14_kbase_SHIFT (6U) +/*! ks14_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS14_ks14_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_kbase_SHIFT)) & CSS_CSS_KS14_ks14_kbase_MASK) + +#define CSS_CSS_KS14_ks14_fgp_MASK (0x80U) +#define CSS_CSS_KS14_ks14_fgp_SHIFT (7U) +/*! ks14_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS14_ks14_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_fgp_SHIFT)) & CSS_CSS_KS14_ks14_fgp_MASK) + +#define CSS_CSS_KS14_ks14_frtn_MASK (0x100U) +#define CSS_CSS_KS14_ks14_frtn_SHIFT (8U) +/*! ks14_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS14_ks14_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_frtn_SHIFT)) & CSS_CSS_KS14_ks14_frtn_MASK) + +#define CSS_CSS_KS14_ks14_fhwo_MASK (0x200U) +#define CSS_CSS_KS14_ks14_fhwo_SHIFT (9U) +/*! ks14_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS14_ks14_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_fhwo_SHIFT)) & CSS_CSS_KS14_ks14_fhwo_MASK) + +#define CSS_CSS_KS14_ks14_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS14_ks14_rsvd1_SHIFT (10U) +/*! ks14_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS14_ks14_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_rsvd1_SHIFT)) & CSS_CSS_KS14_ks14_rsvd1_MASK) + +#define CSS_CSS_KS14_ks14_ucmac_MASK (0x2000U) +#define CSS_CSS_KS14_ks14_ucmac_SHIFT (13U) +/*! ks14_ucmac - CMAC key + */ +#define CSS_CSS_KS14_ks14_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ucmac_SHIFT)) & CSS_CSS_KS14_ks14_ucmac_MASK) + +#define CSS_CSS_KS14_ks14_uksk_MASK (0x4000U) +#define CSS_CSS_KS14_ks14_uksk_SHIFT (14U) +/*! ks14_uksk - KSK key + */ +#define CSS_CSS_KS14_ks14_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uksk_SHIFT)) & CSS_CSS_KS14_ks14_uksk_MASK) + +#define CSS_CSS_KS14_ks14_urtf_MASK (0x8000U) +#define CSS_CSS_KS14_ks14_urtf_SHIFT (15U) +/*! ks14_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS14_ks14_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_urtf_SHIFT)) & CSS_CSS_KS14_ks14_urtf_MASK) + +#define CSS_CSS_KS14_ks14_uckdf_MASK (0x10000U) +#define CSS_CSS_KS14_ks14_uckdf_SHIFT (16U) +/*! ks14_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS14_ks14_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uckdf_SHIFT)) & CSS_CSS_KS14_ks14_uckdf_MASK) + +#define CSS_CSS_KS14_ks14_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS14_ks14_uhkdf_SHIFT (17U) +/*! ks14_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS14_ks14_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhkdf_SHIFT)) & CSS_CSS_KS14_ks14_uhkdf_MASK) + +#define CSS_CSS_KS14_ks14_uecsg_MASK (0x40000U) +#define CSS_CSS_KS14_ks14_uecsg_SHIFT (18U) +/*! ks14_uecsg - Ecc signing key + */ +#define CSS_CSS_KS14_ks14_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uecsg_SHIFT)) & CSS_CSS_KS14_ks14_uecsg_MASK) + +#define CSS_CSS_KS14_ks14_uecdh_MASK (0x80000U) +#define CSS_CSS_KS14_ks14_uecdh_SHIFT (19U) +/*! ks14_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS14_ks14_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uecdh_SHIFT)) & CSS_CSS_KS14_ks14_uecdh_MASK) + +#define CSS_CSS_KS14_ks14_uaes_MASK (0x100000U) +#define CSS_CSS_KS14_ks14_uaes_SHIFT (20U) +/*! ks14_uaes - Aes key + */ +#define CSS_CSS_KS14_ks14_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uaes_SHIFT)) & CSS_CSS_KS14_ks14_uaes_MASK) + +#define CSS_CSS_KS14_ks14_uhmac_MASK (0x200000U) +#define CSS_CSS_KS14_ks14_uhmac_SHIFT (21U) +/*! ks14_uhmac - Hmac key + */ +#define CSS_CSS_KS14_ks14_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhmac_SHIFT)) & CSS_CSS_KS14_ks14_uhmac_MASK) + +#define CSS_CSS_KS14_ks14_ukwk_MASK (0x400000U) +#define CSS_CSS_KS14_ks14_ukwk_SHIFT (22U) +/*! ks14_ukwk - Key wrapping key + */ +#define CSS_CSS_KS14_ks14_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukwk_SHIFT)) & CSS_CSS_KS14_ks14_ukwk_MASK) + +#define CSS_CSS_KS14_ks14_ukuok_MASK (0x800000U) +#define CSS_CSS_KS14_ks14_ukuok_SHIFT (23U) +/*! ks14_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS14_ks14_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukuok_SHIFT)) & CSS_CSS_KS14_ks14_ukuok_MASK) + +#define CSS_CSS_KS14_ks14_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS14_ks14_utlspms_SHIFT (24U) +/*! ks14_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS14_ks14_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_utlspms_SHIFT)) & CSS_CSS_KS14_ks14_utlspms_MASK) + +#define CSS_CSS_KS14_ks14_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS14_ks14_utlsms_SHIFT (25U) +/*! ks14_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS14_ks14_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_utlsms_SHIFT)) & CSS_CSS_KS14_ks14_utlsms_MASK) + +#define CSS_CSS_KS14_ks14_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS14_ks14_ukgsrc_SHIFT (26U) +/*! ks14_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS14_ks14_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukgsrc_SHIFT)) & CSS_CSS_KS14_ks14_ukgsrc_MASK) + +#define CSS_CSS_KS14_ks14_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS14_ks14_uhwo_SHIFT (27U) +/*! ks14_uhwo - Hardware out key + */ +#define CSS_CSS_KS14_ks14_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhwo_SHIFT)) & CSS_CSS_KS14_ks14_uhwo_MASK) + +#define CSS_CSS_KS14_ks14_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS14_ks14_uwrpok_SHIFT (28U) +/*! ks14_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS14_ks14_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uwrpok_SHIFT)) & CSS_CSS_KS14_ks14_uwrpok_MASK) + +#define CSS_CSS_KS14_ks14_uduk_MASK (0x20000000U) +#define CSS_CSS_KS14_ks14_uduk_SHIFT (29U) +/*! ks14_uduk - Device Unique Key + */ +#define CSS_CSS_KS14_ks14_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uduk_SHIFT)) & CSS_CSS_KS14_ks14_uduk_MASK) + +#define CSS_CSS_KS14_ks14_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS14_ks14_upprot_SHIFT (30U) +/*! ks14_upprot - Priviledge level + */ +#define CSS_CSS_KS14_ks14_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_upprot_SHIFT)) & CSS_CSS_KS14_ks14_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS15 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS15_ks15_ksize_MASK (0x1U) +#define CSS_CSS_KS15_ks15_ksize_SHIFT (0U) +/*! ks15_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS15_ks15_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ksize_SHIFT)) & CSS_CSS_KS15_ks15_ksize_MASK) + +#define CSS_CSS_KS15_ks15_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS15_ks15_rsvd0_SHIFT (1U) +/*! ks15_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS15_ks15_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_rsvd0_SHIFT)) & CSS_CSS_KS15_ks15_rsvd0_MASK) + +#define CSS_CSS_KS15_ks15_kact_MASK (0x20U) +#define CSS_CSS_KS15_ks15_kact_SHIFT (5U) +/*! ks15_kact - Key is active + */ +#define CSS_CSS_KS15_ks15_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_kact_SHIFT)) & CSS_CSS_KS15_ks15_kact_MASK) + +#define CSS_CSS_KS15_ks15_kbase_MASK (0x40U) +#define CSS_CSS_KS15_ks15_kbase_SHIFT (6U) +/*! ks15_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS15_ks15_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_kbase_SHIFT)) & CSS_CSS_KS15_ks15_kbase_MASK) + +#define CSS_CSS_KS15_ks15_fgp_MASK (0x80U) +#define CSS_CSS_KS15_ks15_fgp_SHIFT (7U) +/*! ks15_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS15_ks15_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_fgp_SHIFT)) & CSS_CSS_KS15_ks15_fgp_MASK) + +#define CSS_CSS_KS15_ks15_frtn_MASK (0x100U) +#define CSS_CSS_KS15_ks15_frtn_SHIFT (8U) +/*! ks15_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS15_ks15_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_frtn_SHIFT)) & CSS_CSS_KS15_ks15_frtn_MASK) + +#define CSS_CSS_KS15_ks15_fhwo_MASK (0x200U) +#define CSS_CSS_KS15_ks15_fhwo_SHIFT (9U) +/*! ks15_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS15_ks15_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_fhwo_SHIFT)) & CSS_CSS_KS15_ks15_fhwo_MASK) + +#define CSS_CSS_KS15_ks15_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS15_ks15_rsvd1_SHIFT (10U) +/*! ks15_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS15_ks15_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_rsvd1_SHIFT)) & CSS_CSS_KS15_ks15_rsvd1_MASK) + +#define CSS_CSS_KS15_ks15_ucmac_MASK (0x2000U) +#define CSS_CSS_KS15_ks15_ucmac_SHIFT (13U) +/*! ks15_ucmac - CMAC key + */ +#define CSS_CSS_KS15_ks15_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ucmac_SHIFT)) & CSS_CSS_KS15_ks15_ucmac_MASK) + +#define CSS_CSS_KS15_ks15_uksk_MASK (0x4000U) +#define CSS_CSS_KS15_ks15_uksk_SHIFT (14U) +/*! ks15_uksk - KSK key + */ +#define CSS_CSS_KS15_ks15_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uksk_SHIFT)) & CSS_CSS_KS15_ks15_uksk_MASK) + +#define CSS_CSS_KS15_ks15_urtf_MASK (0x8000U) +#define CSS_CSS_KS15_ks15_urtf_SHIFT (15U) +/*! ks15_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS15_ks15_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_urtf_SHIFT)) & CSS_CSS_KS15_ks15_urtf_MASK) + +#define CSS_CSS_KS15_ks15_uckdf_MASK (0x10000U) +#define CSS_CSS_KS15_ks15_uckdf_SHIFT (16U) +/*! ks15_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS15_ks15_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uckdf_SHIFT)) & CSS_CSS_KS15_ks15_uckdf_MASK) + +#define CSS_CSS_KS15_ks15_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS15_ks15_uhkdf_SHIFT (17U) +/*! ks15_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS15_ks15_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhkdf_SHIFT)) & CSS_CSS_KS15_ks15_uhkdf_MASK) + +#define CSS_CSS_KS15_ks15_uecsg_MASK (0x40000U) +#define CSS_CSS_KS15_ks15_uecsg_SHIFT (18U) +/*! ks15_uecsg - Ecc signing key + */ +#define CSS_CSS_KS15_ks15_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uecsg_SHIFT)) & CSS_CSS_KS15_ks15_uecsg_MASK) + +#define CSS_CSS_KS15_ks15_uecdh_MASK (0x80000U) +#define CSS_CSS_KS15_ks15_uecdh_SHIFT (19U) +/*! ks15_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS15_ks15_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uecdh_SHIFT)) & CSS_CSS_KS15_ks15_uecdh_MASK) + +#define CSS_CSS_KS15_ks15_uaes_MASK (0x100000U) +#define CSS_CSS_KS15_ks15_uaes_SHIFT (20U) +/*! ks15_uaes - Aes key + */ +#define CSS_CSS_KS15_ks15_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uaes_SHIFT)) & CSS_CSS_KS15_ks15_uaes_MASK) + +#define CSS_CSS_KS15_ks15_uhmac_MASK (0x200000U) +#define CSS_CSS_KS15_ks15_uhmac_SHIFT (21U) +/*! ks15_uhmac - Hmac key + */ +#define CSS_CSS_KS15_ks15_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhmac_SHIFT)) & CSS_CSS_KS15_ks15_uhmac_MASK) + +#define CSS_CSS_KS15_ks15_ukwk_MASK (0x400000U) +#define CSS_CSS_KS15_ks15_ukwk_SHIFT (22U) +/*! ks15_ukwk - Key wrapping key + */ +#define CSS_CSS_KS15_ks15_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukwk_SHIFT)) & CSS_CSS_KS15_ks15_ukwk_MASK) + +#define CSS_CSS_KS15_ks15_ukuok_MASK (0x800000U) +#define CSS_CSS_KS15_ks15_ukuok_SHIFT (23U) +/*! ks15_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS15_ks15_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukuok_SHIFT)) & CSS_CSS_KS15_ks15_ukuok_MASK) + +#define CSS_CSS_KS15_ks15_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS15_ks15_utlspms_SHIFT (24U) +/*! ks15_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS15_ks15_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_utlspms_SHIFT)) & CSS_CSS_KS15_ks15_utlspms_MASK) + +#define CSS_CSS_KS15_ks15_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS15_ks15_utlsms_SHIFT (25U) +/*! ks15_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS15_ks15_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_utlsms_SHIFT)) & CSS_CSS_KS15_ks15_utlsms_MASK) + +#define CSS_CSS_KS15_ks15_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS15_ks15_ukgsrc_SHIFT (26U) +/*! ks15_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS15_ks15_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukgsrc_SHIFT)) & CSS_CSS_KS15_ks15_ukgsrc_MASK) + +#define CSS_CSS_KS15_ks15_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS15_ks15_uhwo_SHIFT (27U) +/*! ks15_uhwo - Hardware out key + */ +#define CSS_CSS_KS15_ks15_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhwo_SHIFT)) & CSS_CSS_KS15_ks15_uhwo_MASK) + +#define CSS_CSS_KS15_ks15_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS15_ks15_uwrpok_SHIFT (28U) +/*! ks15_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS15_ks15_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uwrpok_SHIFT)) & CSS_CSS_KS15_ks15_uwrpok_MASK) + +#define CSS_CSS_KS15_ks15_uduk_MASK (0x20000000U) +#define CSS_CSS_KS15_ks15_uduk_SHIFT (29U) +/*! ks15_uduk - Device Unique Key + */ +#define CSS_CSS_KS15_ks15_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uduk_SHIFT)) & CSS_CSS_KS15_ks15_uduk_MASK) + +#define CSS_CSS_KS15_ks15_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS15_ks15_upprot_SHIFT (30U) +/*! ks15_upprot - Priviledge level + */ +#define CSS_CSS_KS15_ks15_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_upprot_SHIFT)) & CSS_CSS_KS15_ks15_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS16 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS16_ks16_ksize_MASK (0x1U) +#define CSS_CSS_KS16_ks16_ksize_SHIFT (0U) +/*! ks16_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS16_ks16_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ksize_SHIFT)) & CSS_CSS_KS16_ks16_ksize_MASK) + +#define CSS_CSS_KS16_ks16_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS16_ks16_rsvd0_SHIFT (1U) +/*! ks16_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS16_ks16_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_rsvd0_SHIFT)) & CSS_CSS_KS16_ks16_rsvd0_MASK) + +#define CSS_CSS_KS16_ks16_kact_MASK (0x20U) +#define CSS_CSS_KS16_ks16_kact_SHIFT (5U) +/*! ks16_kact - Key is active + */ +#define CSS_CSS_KS16_ks16_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_kact_SHIFT)) & CSS_CSS_KS16_ks16_kact_MASK) + +#define CSS_CSS_KS16_ks16_kbase_MASK (0x40U) +#define CSS_CSS_KS16_ks16_kbase_SHIFT (6U) +/*! ks16_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS16_ks16_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_kbase_SHIFT)) & CSS_CSS_KS16_ks16_kbase_MASK) + +#define CSS_CSS_KS16_ks16_fgp_MASK (0x80U) +#define CSS_CSS_KS16_ks16_fgp_SHIFT (7U) +/*! ks16_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS16_ks16_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_fgp_SHIFT)) & CSS_CSS_KS16_ks16_fgp_MASK) + +#define CSS_CSS_KS16_ks16_frtn_MASK (0x100U) +#define CSS_CSS_KS16_ks16_frtn_SHIFT (8U) +/*! ks16_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS16_ks16_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_frtn_SHIFT)) & CSS_CSS_KS16_ks16_frtn_MASK) + +#define CSS_CSS_KS16_ks16_fhwo_MASK (0x200U) +#define CSS_CSS_KS16_ks16_fhwo_SHIFT (9U) +/*! ks16_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS16_ks16_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_fhwo_SHIFT)) & CSS_CSS_KS16_ks16_fhwo_MASK) + +#define CSS_CSS_KS16_ks16_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS16_ks16_rsvd1_SHIFT (10U) +/*! ks16_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS16_ks16_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_rsvd1_SHIFT)) & CSS_CSS_KS16_ks16_rsvd1_MASK) + +#define CSS_CSS_KS16_ks16_ucmac_MASK (0x2000U) +#define CSS_CSS_KS16_ks16_ucmac_SHIFT (13U) +/*! ks16_ucmac - CMAC key + */ +#define CSS_CSS_KS16_ks16_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ucmac_SHIFT)) & CSS_CSS_KS16_ks16_ucmac_MASK) + +#define CSS_CSS_KS16_ks16_uksk_MASK (0x4000U) +#define CSS_CSS_KS16_ks16_uksk_SHIFT (14U) +/*! ks16_uksk - KSK key + */ +#define CSS_CSS_KS16_ks16_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uksk_SHIFT)) & CSS_CSS_KS16_ks16_uksk_MASK) + +#define CSS_CSS_KS16_ks16_urtf_MASK (0x8000U) +#define CSS_CSS_KS16_ks16_urtf_SHIFT (15U) +/*! ks16_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS16_ks16_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_urtf_SHIFT)) & CSS_CSS_KS16_ks16_urtf_MASK) + +#define CSS_CSS_KS16_ks16_uckdf_MASK (0x10000U) +#define CSS_CSS_KS16_ks16_uckdf_SHIFT (16U) +/*! ks16_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS16_ks16_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uckdf_SHIFT)) & CSS_CSS_KS16_ks16_uckdf_MASK) + +#define CSS_CSS_KS16_ks16_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS16_ks16_uhkdf_SHIFT (17U) +/*! ks16_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS16_ks16_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhkdf_SHIFT)) & CSS_CSS_KS16_ks16_uhkdf_MASK) + +#define CSS_CSS_KS16_ks16_uecsg_MASK (0x40000U) +#define CSS_CSS_KS16_ks16_uecsg_SHIFT (18U) +/*! ks16_uecsg - Ecc signing key + */ +#define CSS_CSS_KS16_ks16_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uecsg_SHIFT)) & CSS_CSS_KS16_ks16_uecsg_MASK) + +#define CSS_CSS_KS16_ks16_uecdh_MASK (0x80000U) +#define CSS_CSS_KS16_ks16_uecdh_SHIFT (19U) +/*! ks16_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS16_ks16_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uecdh_SHIFT)) & CSS_CSS_KS16_ks16_uecdh_MASK) + +#define CSS_CSS_KS16_ks16_uaes_MASK (0x100000U) +#define CSS_CSS_KS16_ks16_uaes_SHIFT (20U) +/*! ks16_uaes - Aes key + */ +#define CSS_CSS_KS16_ks16_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uaes_SHIFT)) & CSS_CSS_KS16_ks16_uaes_MASK) + +#define CSS_CSS_KS16_ks16_uhmac_MASK (0x200000U) +#define CSS_CSS_KS16_ks16_uhmac_SHIFT (21U) +/*! ks16_uhmac - Hmac key + */ +#define CSS_CSS_KS16_ks16_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhmac_SHIFT)) & CSS_CSS_KS16_ks16_uhmac_MASK) + +#define CSS_CSS_KS16_ks16_ukwk_MASK (0x400000U) +#define CSS_CSS_KS16_ks16_ukwk_SHIFT (22U) +/*! ks16_ukwk - Key wrapping key + */ +#define CSS_CSS_KS16_ks16_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukwk_SHIFT)) & CSS_CSS_KS16_ks16_ukwk_MASK) + +#define CSS_CSS_KS16_ks16_ukuok_MASK (0x800000U) +#define CSS_CSS_KS16_ks16_ukuok_SHIFT (23U) +/*! ks16_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS16_ks16_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukuok_SHIFT)) & CSS_CSS_KS16_ks16_ukuok_MASK) + +#define CSS_CSS_KS16_ks16_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS16_ks16_utlspms_SHIFT (24U) +/*! ks16_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS16_ks16_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_utlspms_SHIFT)) & CSS_CSS_KS16_ks16_utlspms_MASK) + +#define CSS_CSS_KS16_ks16_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS16_ks16_utlsms_SHIFT (25U) +/*! ks16_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS16_ks16_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_utlsms_SHIFT)) & CSS_CSS_KS16_ks16_utlsms_MASK) + +#define CSS_CSS_KS16_ks16_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS16_ks16_ukgsrc_SHIFT (26U) +/*! ks16_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS16_ks16_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukgsrc_SHIFT)) & CSS_CSS_KS16_ks16_ukgsrc_MASK) + +#define CSS_CSS_KS16_ks16_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS16_ks16_uhwo_SHIFT (27U) +/*! ks16_uhwo - Hardware out key + */ +#define CSS_CSS_KS16_ks16_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhwo_SHIFT)) & CSS_CSS_KS16_ks16_uhwo_MASK) + +#define CSS_CSS_KS16_ks16_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS16_ks16_uwrpok_SHIFT (28U) +/*! ks16_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS16_ks16_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uwrpok_SHIFT)) & CSS_CSS_KS16_ks16_uwrpok_MASK) + +#define CSS_CSS_KS16_ks16_uduk_MASK (0x20000000U) +#define CSS_CSS_KS16_ks16_uduk_SHIFT (29U) +/*! ks16_uduk - Device Unique Key + */ +#define CSS_CSS_KS16_ks16_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uduk_SHIFT)) & CSS_CSS_KS16_ks16_uduk_MASK) + +#define CSS_CSS_KS16_ks16_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS16_ks16_upprot_SHIFT (30U) +/*! ks16_upprot - Priviledge level + */ +#define CSS_CSS_KS16_ks16_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_upprot_SHIFT)) & CSS_CSS_KS16_ks16_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS17 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS17_ks17_ksize_MASK (0x1U) +#define CSS_CSS_KS17_ks17_ksize_SHIFT (0U) +/*! ks17_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS17_ks17_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ksize_SHIFT)) & CSS_CSS_KS17_ks17_ksize_MASK) + +#define CSS_CSS_KS17_ks17_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS17_ks17_rsvd0_SHIFT (1U) +/*! ks17_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS17_ks17_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_rsvd0_SHIFT)) & CSS_CSS_KS17_ks17_rsvd0_MASK) + +#define CSS_CSS_KS17_ks17_kact_MASK (0x20U) +#define CSS_CSS_KS17_ks17_kact_SHIFT (5U) +/*! ks17_kact - Key is active + */ +#define CSS_CSS_KS17_ks17_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_kact_SHIFT)) & CSS_CSS_KS17_ks17_kact_MASK) + +#define CSS_CSS_KS17_ks17_kbase_MASK (0x40U) +#define CSS_CSS_KS17_ks17_kbase_SHIFT (6U) +/*! ks17_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS17_ks17_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_kbase_SHIFT)) & CSS_CSS_KS17_ks17_kbase_MASK) + +#define CSS_CSS_KS17_ks17_fgp_MASK (0x80U) +#define CSS_CSS_KS17_ks17_fgp_SHIFT (7U) +/*! ks17_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS17_ks17_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_fgp_SHIFT)) & CSS_CSS_KS17_ks17_fgp_MASK) + +#define CSS_CSS_KS17_ks17_frtn_MASK (0x100U) +#define CSS_CSS_KS17_ks17_frtn_SHIFT (8U) +/*! ks17_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS17_ks17_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_frtn_SHIFT)) & CSS_CSS_KS17_ks17_frtn_MASK) + +#define CSS_CSS_KS17_ks17_fhwo_MASK (0x200U) +#define CSS_CSS_KS17_ks17_fhwo_SHIFT (9U) +/*! ks17_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS17_ks17_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_fhwo_SHIFT)) & CSS_CSS_KS17_ks17_fhwo_MASK) + +#define CSS_CSS_KS17_ks17_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS17_ks17_rsvd1_SHIFT (10U) +/*! ks17_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS17_ks17_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_rsvd1_SHIFT)) & CSS_CSS_KS17_ks17_rsvd1_MASK) + +#define CSS_CSS_KS17_ks17_ucmac_MASK (0x2000U) +#define CSS_CSS_KS17_ks17_ucmac_SHIFT (13U) +/*! ks17_ucmac - CMAC key + */ +#define CSS_CSS_KS17_ks17_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ucmac_SHIFT)) & CSS_CSS_KS17_ks17_ucmac_MASK) + +#define CSS_CSS_KS17_ks17_uksk_MASK (0x4000U) +#define CSS_CSS_KS17_ks17_uksk_SHIFT (14U) +/*! ks17_uksk - KSK key + */ +#define CSS_CSS_KS17_ks17_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uksk_SHIFT)) & CSS_CSS_KS17_ks17_uksk_MASK) + +#define CSS_CSS_KS17_ks17_urtf_MASK (0x8000U) +#define CSS_CSS_KS17_ks17_urtf_SHIFT (15U) +/*! ks17_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS17_ks17_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_urtf_SHIFT)) & CSS_CSS_KS17_ks17_urtf_MASK) + +#define CSS_CSS_KS17_ks17_uckdf_MASK (0x10000U) +#define CSS_CSS_KS17_ks17_uckdf_SHIFT (16U) +/*! ks17_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS17_ks17_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uckdf_SHIFT)) & CSS_CSS_KS17_ks17_uckdf_MASK) + +#define CSS_CSS_KS17_ks17_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS17_ks17_uhkdf_SHIFT (17U) +/*! ks17_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS17_ks17_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhkdf_SHIFT)) & CSS_CSS_KS17_ks17_uhkdf_MASK) + +#define CSS_CSS_KS17_ks17_uecsg_MASK (0x40000U) +#define CSS_CSS_KS17_ks17_uecsg_SHIFT (18U) +/*! ks17_uecsg - Ecc signing key + */ +#define CSS_CSS_KS17_ks17_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uecsg_SHIFT)) & CSS_CSS_KS17_ks17_uecsg_MASK) + +#define CSS_CSS_KS17_ks17_uecdh_MASK (0x80000U) +#define CSS_CSS_KS17_ks17_uecdh_SHIFT (19U) +/*! ks17_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS17_ks17_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uecdh_SHIFT)) & CSS_CSS_KS17_ks17_uecdh_MASK) + +#define CSS_CSS_KS17_ks17_uaes_MASK (0x100000U) +#define CSS_CSS_KS17_ks17_uaes_SHIFT (20U) +/*! ks17_uaes - Aes key + */ +#define CSS_CSS_KS17_ks17_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uaes_SHIFT)) & CSS_CSS_KS17_ks17_uaes_MASK) + +#define CSS_CSS_KS17_ks17_uhmac_MASK (0x200000U) +#define CSS_CSS_KS17_ks17_uhmac_SHIFT (21U) +/*! ks17_uhmac - Hmac key + */ +#define CSS_CSS_KS17_ks17_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhmac_SHIFT)) & CSS_CSS_KS17_ks17_uhmac_MASK) + +#define CSS_CSS_KS17_ks17_ukwk_MASK (0x400000U) +#define CSS_CSS_KS17_ks17_ukwk_SHIFT (22U) +/*! ks17_ukwk - Key wrapping key + */ +#define CSS_CSS_KS17_ks17_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukwk_SHIFT)) & CSS_CSS_KS17_ks17_ukwk_MASK) + +#define CSS_CSS_KS17_ks17_ukuok_MASK (0x800000U) +#define CSS_CSS_KS17_ks17_ukuok_SHIFT (23U) +/*! ks17_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS17_ks17_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukuok_SHIFT)) & CSS_CSS_KS17_ks17_ukuok_MASK) + +#define CSS_CSS_KS17_ks17_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS17_ks17_utlspms_SHIFT (24U) +/*! ks17_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS17_ks17_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_utlspms_SHIFT)) & CSS_CSS_KS17_ks17_utlspms_MASK) + +#define CSS_CSS_KS17_ks17_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS17_ks17_utlsms_SHIFT (25U) +/*! ks17_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS17_ks17_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_utlsms_SHIFT)) & CSS_CSS_KS17_ks17_utlsms_MASK) + +#define CSS_CSS_KS17_ks17_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS17_ks17_ukgsrc_SHIFT (26U) +/*! ks17_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS17_ks17_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukgsrc_SHIFT)) & CSS_CSS_KS17_ks17_ukgsrc_MASK) + +#define CSS_CSS_KS17_ks17_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS17_ks17_uhwo_SHIFT (27U) +/*! ks17_uhwo - Hardware out key + */ +#define CSS_CSS_KS17_ks17_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhwo_SHIFT)) & CSS_CSS_KS17_ks17_uhwo_MASK) + +#define CSS_CSS_KS17_ks17_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS17_ks17_uwrpok_SHIFT (28U) +/*! ks17_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS17_ks17_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uwrpok_SHIFT)) & CSS_CSS_KS17_ks17_uwrpok_MASK) + +#define CSS_CSS_KS17_ks17_uduk_MASK (0x20000000U) +#define CSS_CSS_KS17_ks17_uduk_SHIFT (29U) +/*! ks17_uduk - Device Unique Key + */ +#define CSS_CSS_KS17_ks17_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uduk_SHIFT)) & CSS_CSS_KS17_ks17_uduk_MASK) + +#define CSS_CSS_KS17_ks17_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS17_ks17_upprot_SHIFT (30U) +/*! ks17_upprot - Priviledge level + */ +#define CSS_CSS_KS17_ks17_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_upprot_SHIFT)) & CSS_CSS_KS17_ks17_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS18 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS18_ks18_ksize_MASK (0x1U) +#define CSS_CSS_KS18_ks18_ksize_SHIFT (0U) +/*! ks18_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS18_ks18_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ksize_SHIFT)) & CSS_CSS_KS18_ks18_ksize_MASK) + +#define CSS_CSS_KS18_ks18_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS18_ks18_rsvd0_SHIFT (1U) +/*! ks18_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS18_ks18_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_rsvd0_SHIFT)) & CSS_CSS_KS18_ks18_rsvd0_MASK) + +#define CSS_CSS_KS18_ks18_kact_MASK (0x20U) +#define CSS_CSS_KS18_ks18_kact_SHIFT (5U) +/*! ks18_kact - Key is active + */ +#define CSS_CSS_KS18_ks18_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_kact_SHIFT)) & CSS_CSS_KS18_ks18_kact_MASK) + +#define CSS_CSS_KS18_ks18_kbase_MASK (0x40U) +#define CSS_CSS_KS18_ks18_kbase_SHIFT (6U) +/*! ks18_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS18_ks18_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_kbase_SHIFT)) & CSS_CSS_KS18_ks18_kbase_MASK) + +#define CSS_CSS_KS18_ks18_fgp_MASK (0x80U) +#define CSS_CSS_KS18_ks18_fgp_SHIFT (7U) +/*! ks18_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS18_ks18_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_fgp_SHIFT)) & CSS_CSS_KS18_ks18_fgp_MASK) + +#define CSS_CSS_KS18_ks18_frtn_MASK (0x100U) +#define CSS_CSS_KS18_ks18_frtn_SHIFT (8U) +/*! ks18_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS18_ks18_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_frtn_SHIFT)) & CSS_CSS_KS18_ks18_frtn_MASK) + +#define CSS_CSS_KS18_ks18_fhwo_MASK (0x200U) +#define CSS_CSS_KS18_ks18_fhwo_SHIFT (9U) +/*! ks18_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS18_ks18_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_fhwo_SHIFT)) & CSS_CSS_KS18_ks18_fhwo_MASK) + +#define CSS_CSS_KS18_ks18_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS18_ks18_rsvd1_SHIFT (10U) +/*! ks18_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS18_ks18_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_rsvd1_SHIFT)) & CSS_CSS_KS18_ks18_rsvd1_MASK) + +#define CSS_CSS_KS18_ks18_ucmac_MASK (0x2000U) +#define CSS_CSS_KS18_ks18_ucmac_SHIFT (13U) +/*! ks18_ucmac - CMAC key + */ +#define CSS_CSS_KS18_ks18_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ucmac_SHIFT)) & CSS_CSS_KS18_ks18_ucmac_MASK) + +#define CSS_CSS_KS18_ks18_uksk_MASK (0x4000U) +#define CSS_CSS_KS18_ks18_uksk_SHIFT (14U) +/*! ks18_uksk - KSK key + */ +#define CSS_CSS_KS18_ks18_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uksk_SHIFT)) & CSS_CSS_KS18_ks18_uksk_MASK) + +#define CSS_CSS_KS18_ks18_urtf_MASK (0x8000U) +#define CSS_CSS_KS18_ks18_urtf_SHIFT (15U) +/*! ks18_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS18_ks18_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_urtf_SHIFT)) & CSS_CSS_KS18_ks18_urtf_MASK) + +#define CSS_CSS_KS18_ks18_uckdf_MASK (0x10000U) +#define CSS_CSS_KS18_ks18_uckdf_SHIFT (16U) +/*! ks18_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS18_ks18_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uckdf_SHIFT)) & CSS_CSS_KS18_ks18_uckdf_MASK) + +#define CSS_CSS_KS18_ks18_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS18_ks18_uhkdf_SHIFT (17U) +/*! ks18_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS18_ks18_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhkdf_SHIFT)) & CSS_CSS_KS18_ks18_uhkdf_MASK) + +#define CSS_CSS_KS18_ks18_uecsg_MASK (0x40000U) +#define CSS_CSS_KS18_ks18_uecsg_SHIFT (18U) +/*! ks18_uecsg - Ecc signing key + */ +#define CSS_CSS_KS18_ks18_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uecsg_SHIFT)) & CSS_CSS_KS18_ks18_uecsg_MASK) + +#define CSS_CSS_KS18_ks18_uecdh_MASK (0x80000U) +#define CSS_CSS_KS18_ks18_uecdh_SHIFT (19U) +/*! ks18_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS18_ks18_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uecdh_SHIFT)) & CSS_CSS_KS18_ks18_uecdh_MASK) + +#define CSS_CSS_KS18_ks18_uaes_MASK (0x100000U) +#define CSS_CSS_KS18_ks18_uaes_SHIFT (20U) +/*! ks18_uaes - Aes key + */ +#define CSS_CSS_KS18_ks18_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uaes_SHIFT)) & CSS_CSS_KS18_ks18_uaes_MASK) + +#define CSS_CSS_KS18_ks18_uhmac_MASK (0x200000U) +#define CSS_CSS_KS18_ks18_uhmac_SHIFT (21U) +/*! ks18_uhmac - Hmac key + */ +#define CSS_CSS_KS18_ks18_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhmac_SHIFT)) & CSS_CSS_KS18_ks18_uhmac_MASK) + +#define CSS_CSS_KS18_ks18_ukwk_MASK (0x400000U) +#define CSS_CSS_KS18_ks18_ukwk_SHIFT (22U) +/*! ks18_ukwk - Key wrapping key + */ +#define CSS_CSS_KS18_ks18_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukwk_SHIFT)) & CSS_CSS_KS18_ks18_ukwk_MASK) + +#define CSS_CSS_KS18_ks18_ukuok_MASK (0x800000U) +#define CSS_CSS_KS18_ks18_ukuok_SHIFT (23U) +/*! ks18_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS18_ks18_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukuok_SHIFT)) & CSS_CSS_KS18_ks18_ukuok_MASK) + +#define CSS_CSS_KS18_ks18_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS18_ks18_utlspms_SHIFT (24U) +/*! ks18_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS18_ks18_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_utlspms_SHIFT)) & CSS_CSS_KS18_ks18_utlspms_MASK) + +#define CSS_CSS_KS18_ks18_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS18_ks18_utlsms_SHIFT (25U) +/*! ks18_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS18_ks18_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_utlsms_SHIFT)) & CSS_CSS_KS18_ks18_utlsms_MASK) + +#define CSS_CSS_KS18_ks18_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS18_ks18_ukgsrc_SHIFT (26U) +/*! ks18_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS18_ks18_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukgsrc_SHIFT)) & CSS_CSS_KS18_ks18_ukgsrc_MASK) + +#define CSS_CSS_KS18_ks18_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS18_ks18_uhwo_SHIFT (27U) +/*! ks18_uhwo - Hardware out key + */ +#define CSS_CSS_KS18_ks18_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhwo_SHIFT)) & CSS_CSS_KS18_ks18_uhwo_MASK) + +#define CSS_CSS_KS18_ks18_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS18_ks18_uwrpok_SHIFT (28U) +/*! ks18_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS18_ks18_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uwrpok_SHIFT)) & CSS_CSS_KS18_ks18_uwrpok_MASK) + +#define CSS_CSS_KS18_ks18_uduk_MASK (0x20000000U) +#define CSS_CSS_KS18_ks18_uduk_SHIFT (29U) +/*! ks18_uduk - Device Unique Key + */ +#define CSS_CSS_KS18_ks18_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uduk_SHIFT)) & CSS_CSS_KS18_ks18_uduk_MASK) + +#define CSS_CSS_KS18_ks18_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS18_ks18_upprot_SHIFT (30U) +/*! ks18_upprot - Priviledge level + */ +#define CSS_CSS_KS18_ks18_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_upprot_SHIFT)) & CSS_CSS_KS18_ks18_upprot_MASK) +/*! @} */ + +/*! @name CSS_KS19 - Status register */ +/*! @{ */ + +#define CSS_CSS_KS19_ks19_ksize_MASK (0x1U) +#define CSS_CSS_KS19_ks19_ksize_SHIFT (0U) +/*! ks19_ksize - Key size: 0-128, 1-256 + */ +#define CSS_CSS_KS19_ks19_ksize(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ksize_SHIFT)) & CSS_CSS_KS19_ks19_ksize_MASK) + +#define CSS_CSS_KS19_ks19_rsvd0_MASK (0x1EU) +#define CSS_CSS_KS19_ks19_rsvd0_SHIFT (1U) +/*! ks19_rsvd0 - Reserved 0 + */ +#define CSS_CSS_KS19_ks19_rsvd0(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_rsvd0_SHIFT)) & CSS_CSS_KS19_ks19_rsvd0_MASK) + +#define CSS_CSS_KS19_ks19_kact_MASK (0x20U) +#define CSS_CSS_KS19_ks19_kact_SHIFT (5U) +/*! ks19_kact - Key is active + */ +#define CSS_CSS_KS19_ks19_kact(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_kact_SHIFT)) & CSS_CSS_KS19_ks19_kact_MASK) + +#define CSS_CSS_KS19_ks19_kbase_MASK (0x40U) +#define CSS_CSS_KS19_ks19_kbase_SHIFT (6U) +/*! ks19_kbase - First slot in a multislot key + */ +#define CSS_CSS_KS19_ks19_kbase(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_kbase_SHIFT)) & CSS_CSS_KS19_ks19_kbase_MASK) + +#define CSS_CSS_KS19_ks19_fgp_MASK (0x80U) +#define CSS_CSS_KS19_ks19_fgp_SHIFT (7U) +/*! ks19_fgp - Hardware Feature General Purpose + */ +#define CSS_CSS_KS19_ks19_fgp(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_fgp_SHIFT)) & CSS_CSS_KS19_ks19_fgp_MASK) + +#define CSS_CSS_KS19_ks19_frtn_MASK (0x100U) +#define CSS_CSS_KS19_ks19_frtn_SHIFT (8U) +/*! ks19_frtn - Hardware Feature Retention + */ +#define CSS_CSS_KS19_ks19_frtn(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_frtn_SHIFT)) & CSS_CSS_KS19_ks19_frtn_MASK) + +#define CSS_CSS_KS19_ks19_fhwo_MASK (0x200U) +#define CSS_CSS_KS19_ks19_fhwo_SHIFT (9U) +/*! ks19_fhwo - Hardware Feature Output + */ +#define CSS_CSS_KS19_ks19_fhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_fhwo_SHIFT)) & CSS_CSS_KS19_ks19_fhwo_MASK) + +#define CSS_CSS_KS19_ks19_rsvd1_MASK (0x1C00U) +#define CSS_CSS_KS19_ks19_rsvd1_SHIFT (10U) +/*! ks19_rsvd1 - Reserved 1 + */ +#define CSS_CSS_KS19_ks19_rsvd1(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_rsvd1_SHIFT)) & CSS_CSS_KS19_ks19_rsvd1_MASK) + +#define CSS_CSS_KS19_ks19_ucmac_MASK (0x2000U) +#define CSS_CSS_KS19_ks19_ucmac_SHIFT (13U) +/*! ks19_ucmac - CMAC key + */ +#define CSS_CSS_KS19_ks19_ucmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ucmac_SHIFT)) & CSS_CSS_KS19_ks19_ucmac_MASK) + +#define CSS_CSS_KS19_ks19_uksk_MASK (0x4000U) +#define CSS_CSS_KS19_ks19_uksk_SHIFT (14U) +/*! ks19_uksk - KSK key + */ +#define CSS_CSS_KS19_ks19_uksk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uksk_SHIFT)) & CSS_CSS_KS19_ks19_uksk_MASK) + +#define CSS_CSS_KS19_ks19_urtf_MASK (0x8000U) +#define CSS_CSS_KS19_ks19_urtf_SHIFT (15U) +/*! ks19_urtf - Real Time Fingerprint key + */ +#define CSS_CSS_KS19_ks19_urtf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_urtf_SHIFT)) & CSS_CSS_KS19_ks19_urtf_MASK) + +#define CSS_CSS_KS19_ks19_uckdf_MASK (0x10000U) +#define CSS_CSS_KS19_ks19_uckdf_SHIFT (16U) +/*! ks19_uckdf - Derivation key for CKDF command + */ +#define CSS_CSS_KS19_ks19_uckdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uckdf_SHIFT)) & CSS_CSS_KS19_ks19_uckdf_MASK) + +#define CSS_CSS_KS19_ks19_uhkdf_MASK (0x20000U) +#define CSS_CSS_KS19_ks19_uhkdf_SHIFT (17U) +/*! ks19_uhkdf - Derivation key for HKDF command + */ +#define CSS_CSS_KS19_ks19_uhkdf(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhkdf_SHIFT)) & CSS_CSS_KS19_ks19_uhkdf_MASK) + +#define CSS_CSS_KS19_ks19_uecsg_MASK (0x40000U) +#define CSS_CSS_KS19_ks19_uecsg_SHIFT (18U) +/*! ks19_uecsg - Ecc signing key + */ +#define CSS_CSS_KS19_ks19_uecsg(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uecsg_SHIFT)) & CSS_CSS_KS19_ks19_uecsg_MASK) + +#define CSS_CSS_KS19_ks19_uecdh_MASK (0x80000U) +#define CSS_CSS_KS19_ks19_uecdh_SHIFT (19U) +/*! ks19_uecdh - Ecc diffie hellman key + */ +#define CSS_CSS_KS19_ks19_uecdh(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uecdh_SHIFT)) & CSS_CSS_KS19_ks19_uecdh_MASK) + +#define CSS_CSS_KS19_ks19_uaes_MASK (0x100000U) +#define CSS_CSS_KS19_ks19_uaes_SHIFT (20U) +/*! ks19_uaes - Aes key + */ +#define CSS_CSS_KS19_ks19_uaes(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uaes_SHIFT)) & CSS_CSS_KS19_ks19_uaes_MASK) + +#define CSS_CSS_KS19_ks19_uhmac_MASK (0x200000U) +#define CSS_CSS_KS19_ks19_uhmac_SHIFT (21U) +/*! ks19_uhmac - Hmac key + */ +#define CSS_CSS_KS19_ks19_uhmac(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhmac_SHIFT)) & CSS_CSS_KS19_ks19_uhmac_MASK) + +#define CSS_CSS_KS19_ks19_ukwk_MASK (0x400000U) +#define CSS_CSS_KS19_ks19_ukwk_SHIFT (22U) +/*! ks19_ukwk - Key wrapping key + */ +#define CSS_CSS_KS19_ks19_ukwk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukwk_SHIFT)) & CSS_CSS_KS19_ks19_ukwk_MASK) + +#define CSS_CSS_KS19_ks19_ukuok_MASK (0x800000U) +#define CSS_CSS_KS19_ks19_ukuok_SHIFT (23U) +/*! ks19_ukuok - Key unwrapping key + */ +#define CSS_CSS_KS19_ks19_ukuok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukuok_SHIFT)) & CSS_CSS_KS19_ks19_ukuok_MASK) + +#define CSS_CSS_KS19_ks19_utlspms_MASK (0x1000000U) +#define CSS_CSS_KS19_ks19_utlspms_SHIFT (24U) +/*! ks19_utlspms - TLS Pre Master Secret + */ +#define CSS_CSS_KS19_ks19_utlspms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_utlspms_SHIFT)) & CSS_CSS_KS19_ks19_utlspms_MASK) + +#define CSS_CSS_KS19_ks19_utlsms_MASK (0x2000000U) +#define CSS_CSS_KS19_ks19_utlsms_SHIFT (25U) +/*! ks19_utlsms - TLS Master Secret + */ +#define CSS_CSS_KS19_ks19_utlsms(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_utlsms_SHIFT)) & CSS_CSS_KS19_ks19_utlsms_MASK) + +#define CSS_CSS_KS19_ks19_ukgsrc_MASK (0x4000000U) +#define CSS_CSS_KS19_ks19_ukgsrc_SHIFT (26U) +/*! ks19_ukgsrc - Supply KEYGEN source + */ +#define CSS_CSS_KS19_ks19_ukgsrc(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukgsrc_SHIFT)) & CSS_CSS_KS19_ks19_ukgsrc_MASK) + +#define CSS_CSS_KS19_ks19_uhwo_MASK (0x8000000U) +#define CSS_CSS_KS19_ks19_uhwo_SHIFT (27U) +/*! ks19_uhwo - Hardware out key + */ +#define CSS_CSS_KS19_ks19_uhwo(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhwo_SHIFT)) & CSS_CSS_KS19_ks19_uhwo_MASK) + +#define CSS_CSS_KS19_ks19_uwrpok_MASK (0x10000000U) +#define CSS_CSS_KS19_ks19_uwrpok_SHIFT (28U) +/*! ks19_uwrpok - Ok to wrap key + */ +#define CSS_CSS_KS19_ks19_uwrpok(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uwrpok_SHIFT)) & CSS_CSS_KS19_ks19_uwrpok_MASK) + +#define CSS_CSS_KS19_ks19_uduk_MASK (0x20000000U) +#define CSS_CSS_KS19_ks19_uduk_SHIFT (29U) +/*! ks19_uduk - Device Unique Key + */ +#define CSS_CSS_KS19_ks19_uduk(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uduk_SHIFT)) & CSS_CSS_KS19_ks19_uduk_MASK) + +#define CSS_CSS_KS19_ks19_upprot_MASK (0xC0000000U) +#define CSS_CSS_KS19_ks19_upprot_SHIFT (30U) +/*! ks19_upprot - Priviledge level + */ +#define CSS_CSS_KS19_ks19_upprot(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_upprot_SHIFT)) & CSS_CSS_KS19_ks19_upprot_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSS_Register_Masks */ + + +/* CSS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CSS base address */ + #define CSS_BASE (0x50030000u) + /** Peripheral CSS base address */ + #define CSS_BASE_NS (0x40030000u) + /** Peripheral CSS base pointer */ + #define CSS ((CSS_Type *)CSS_BASE) + /** Peripheral CSS base pointer */ + #define CSS_NS ((CSS_Type *)CSS_BASE_NS) + /** Array initializer of CSS peripheral base addresses */ + #define CSS_BASE_ADDRS { CSS_BASE } + /** Array initializer of CSS peripheral base pointers */ + #define CSS_BASE_PTRS { CSS } + /** Array initializer of CSS peripheral base addresses */ + #define CSS_BASE_ADDRS_NS { CSS_BASE_NS } + /** Array initializer of CSS peripheral base pointers */ + #define CSS_BASE_PTRS_NS { CSS_NS } +#else + /** Peripheral CSS base address */ + #define CSS_BASE (0x40030000u) + /** Peripheral CSS base pointer */ + #define CSS ((CSS_Type *)CSS_BASE) + /** Array initializer of CSS peripheral base addresses */ + #define CSS_BASE_ADDRS { CSS_BASE } + /** Array initializer of CSS peripheral base pointers */ + #define CSS_BASE_PTRS { CSS } +#endif + +/*! + * @} + */ /* end of group CSS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register, offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register, offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0 + */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1 + */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2 + */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3 + */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event + */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event + */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event + */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event + */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable + * 0b0..Disabled. The counters are disabled + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. When the timer is enabled by an external + * trigger or globally enabled by the external global start enable register, the CEN bit will automatically be + * set to 1 + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset + * 0b0..Disabled. Do nothing + * 0b1..Enabled + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Not allowed + * 0b1..Allow input global_enable=1 action to take effect + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Not allowed + * 0b1..Allow input trigger_enable=1 action to take effect + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value + */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale reload value + */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value + */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value + */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value + */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Do Nothing + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out) + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out) + * 0b11..Toggle. Toggle the corresponding External Match bit/output + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Do Nothing + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out) + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out) + * 0b11..Toggle. Toggle the corresponding External Match bit/output + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Do Nothing + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out) + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out) + * 0b11..Toggle. Toggle the corresponding External Match bit/output + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Do Nothing + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out) + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out) + * 0b11..Toggle. Toggle the corresponding External Match bit/output + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - The Count Control Register (CTCR) is used to select between Timer and Counter mode, and + * in Counter mode to select the pin and edge(s) for counting. + * 0b00..Timer Mode + * 0b01..Counter Mode rising edge + * 0b10..Counter Mode falling edge + * 0b11..Counter Mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0. CAPn[0] for CTIMERn + * 0b01..Channel 1. CAPn[1] for CTIMERn + * 0b10..Channel 2. CAPn[2] for CTIMERn + * 0b11..Channel 3. CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set) + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set) + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set) + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set) + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set) + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set) + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel 0 + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0 + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0 + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel 1 + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1 + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1 + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel 2 + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2 + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2 + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel 3. It is recommended to use match channel 3 to set the PWM cycle + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3 + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3 + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer counter match shadow value + */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DEBUGGER_MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGGER_MAILBOX_Peripheral_Access_Layer DEBUGGER_MAILBOX Peripheral Access Layer + * @{ + */ + +/** DEBUGGER_MAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and status word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DEBUGGER_MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DEBUGGER_MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGGER_MAILBOX_Register_Masks DEBUGGER_MAILBOX Register Masks + * @{ + */ + +/*! @name CSW - Command and status word */ +/*! @{ */ + +#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Re-synchronization Request + * 0b0..No Request + * 0b1..Request for re-synchronization + */ +#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No Request Pending + * 0b1..Request for Re-synchronization Pending + */ +#define DEBUGGER_MAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK) + +#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debug Overrun Error + * 0b0..No Debug Overrun error + * 0b1..Debug Overrun Error. A debug overrun occurred. + */ +#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No AHB Overrun Error + * 0b1..AHB Overrun Error. An AHB overrun occurred. + */ +#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset + */ +#define DEBUGGER_MAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK) + +#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request + */ +#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value + */ +#define DEBUGGER_MAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DEBUGGER_MAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DEBUGGER_MAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - Return Value + */ +#define DEBUGGER_MAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_RETURN_RET_SHIFT)) & DEBUGGER_MAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DEBUGGER_MAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DEBUGGER_MAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification Value + */ +#define DEBUGGER_MAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_ID_ID_SHIFT)) & DEBUGGER_MAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DEBUGGER_MAILBOX_Register_Masks */ + + +/* DEBUGGER_MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DEBUGGER_MAILBOX0 base address */ + #define DEBUGGER_MAILBOX0_BASE (0x5009C000u) + /** Peripheral DEBUGGER_MAILBOX0 base address */ + #define DEBUGGER_MAILBOX0_BASE_NS (0x4009C000u) + /** Peripheral DEBUGGER_MAILBOX0 base pointer */ + #define DEBUGGER_MAILBOX0 ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE) + /** Peripheral DEBUGGER_MAILBOX0 base pointer */ + #define DEBUGGER_MAILBOX0_NS ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE_NS) + /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */ + #define DEBUGGER_MAILBOX_BASE_ADDRS { DEBUGGER_MAILBOX0_BASE } + /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */ + #define DEBUGGER_MAILBOX_BASE_PTRS { DEBUGGER_MAILBOX0 } + /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */ + #define DEBUGGER_MAILBOX_BASE_ADDRS_NS { DEBUGGER_MAILBOX0_BASE_NS } + /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */ + #define DEBUGGER_MAILBOX_BASE_PTRS_NS { DEBUGGER_MAILBOX0_NS } +#else + /** Peripheral DEBUGGER_MAILBOX0 base address */ + #define DEBUGGER_MAILBOX0_BASE (0x4009C000u) + /** Peripheral DEBUGGER_MAILBOX0 base pointer */ + #define DEBUGGER_MAILBOX0 ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE) + /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */ + #define DEBUGGER_MAILBOX_BASE_ADDRS { DEBUGGER_MAILBOX0_BASE } + /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */ + #define DEBUGGER_MAILBOX_BASE_PTRS { DEBUGGER_MAILBOX0 } +#endif + +/*! + * @} + */ /* end of group DEBUGGER_MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control, offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status, offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table, offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x60 */ + __IO uint32_t ENABLESET; /**< Channel Enable read and set for all DMA channels, array offset: 0x20, array step: 0x60 */ + __IO uint32_t ENABLESET1; /**< Channel Enable read and set for all DMA channels, array offset: 0x24, array step: 0x60 */ + __IO uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels, array offset: 0x28, array step: 0x60 */ + __IO uint32_t ENABLECLR1; /**< Channel Enable Clear for all DMA channels, array offset: 0x2C, array step: 0x60 */ + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels, array offset: 0x30, array step: 0x60 */ + __I uint32_t ACTIVE1; /**< Channel Active status for all DMA channels, array offset: 0x34, array step: 0x60 */ + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels, array offset: 0x38, array step: 0x60 */ + __I uint32_t BUSY1; /**< Channel Busy status for all DMA channels, array offset: 0x3C, array step: 0x60 */ + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels, array offset: 0x40, array step: 0x60 */ + __IO uint32_t ERRINT1; /**< Error Interrupt status for all DMA channels, array offset: 0x44, array step: 0x60 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x48, array step: 0x60 */ + __IO uint32_t INTENSET1; /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x4C, array step: 0x60 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels, array offset: 0x50, array step: 0x60 */ + __O uint32_t INTENCLR1; /**< Interrupt Enable Clear for all DMA channels, array offset: 0x54, array step: 0x60 */ + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels, array offset: 0x58, array step: 0x60 */ + __IO uint32_t INTA1; /**< Interrupt A status for all DMA channels, array offset: 0x5C, array step: 0x60 */ + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels, array offset: 0x60, array step: 0x60 */ + __IO uint32_t INTB1; /**< Interrupt B status for all DMA channels, array offset: 0x64, array step: 0x60 */ + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels, array offset: 0x68, array step: 0x60 */ + __O uint32_t SETVALID1; /**< Set ValidPending control bits for all DMA channels, array offset: 0x6C, array step: 0x60 */ + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels, array offset: 0x70, array step: 0x60 */ + __O uint32_t SETTRIG1; /**< Set Trigger control bits for all DMA channels, array offset: 0x74, array step: 0x60 */ + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels, array offset: 0x78, array step: 0x60 */ + __O uint32_t ABORT1; /**< Channel Abort control for all DMA channels, array offset: 0x7C, array step: 0x60 */ + } COMMON[1]; + uint8_t RESERVED_1[896]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel, array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel, array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel, array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[52]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control */ +/*! @{ */ + +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..DMA controller is disabled. + * 0b1..Enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status */ +/*! @{ */ + +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..No enabled interrupts are pending. + * 0b1..At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..No error interrupts are pending. + * 0b1..At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table */ +/*! @{ */ + +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFF00U) /* Merged from fields with different position or width, of widths (22, 24), largest definition used */ +#define DMA_SRAMBASE_OFFSET_SHIFT (8U) +/*! OFFSET - Offset + */ +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) /* Merged from fields with different position or width, of widths (22, 24), largest definition used */ +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and set for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) +#define DMA_COMMON_ENABLESET_ENABLE0_SHIFT (0U) +/*! ENABLE0 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE1_MASK (0x2U) +#define DMA_COMMON_ENABLESET_ENABLE1_SHIFT (1U) +/*! ENABLE1 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE1_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE1_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE2_MASK (0x4U) +#define DMA_COMMON_ENABLESET_ENABLE2_SHIFT (2U) +/*! ENABLE2 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE2_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE2_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE3_MASK (0x8U) +#define DMA_COMMON_ENABLESET_ENABLE3_SHIFT (3U) +/*! ENABLE3 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE3_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE3_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE4_MASK (0x10U) +#define DMA_COMMON_ENABLESET_ENABLE4_SHIFT (4U) +/*! ENABLE4 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE4_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE4_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE5_MASK (0x20U) +#define DMA_COMMON_ENABLESET_ENABLE5_SHIFT (5U) +/*! ENABLE5 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE5_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE5_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE6_MASK (0x40U) +#define DMA_COMMON_ENABLESET_ENABLE6_SHIFT (6U) +/*! ENABLE6 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE6_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE6_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE7_MASK (0x80U) +#define DMA_COMMON_ENABLESET_ENABLE7_SHIFT (7U) +/*! ENABLE7 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE7_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE7_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE8_MASK (0x100U) +#define DMA_COMMON_ENABLESET_ENABLE8_SHIFT (8U) +/*! ENABLE8 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE8_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE8_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE9_MASK (0x200U) +#define DMA_COMMON_ENABLESET_ENABLE9_SHIFT (9U) +/*! ENABLE9 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE9_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE9_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE10_MASK (0x400U) +#define DMA_COMMON_ENABLESET_ENABLE10_SHIFT (10U) +/*! ENABLE10 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE10_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE10_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE11_MASK (0x800U) +#define DMA_COMMON_ENABLESET_ENABLE11_SHIFT (11U) +/*! ENABLE11 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE11_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE11_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE12_MASK (0x1000U) +#define DMA_COMMON_ENABLESET_ENABLE12_SHIFT (12U) +/*! ENABLE12 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE12_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE12_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE13_MASK (0x2000U) +#define DMA_COMMON_ENABLESET_ENABLE13_SHIFT (13U) +/*! ENABLE13 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE13_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE13_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE14_MASK (0x4000U) +#define DMA_COMMON_ENABLESET_ENABLE14_SHIFT (14U) +/*! ENABLE14 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE14_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE14_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE15_MASK (0x8000U) +#define DMA_COMMON_ENABLESET_ENABLE15_SHIFT (15U) +/*! ENABLE15 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE15_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE15_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE16_MASK (0x10000U) +#define DMA_COMMON_ENABLESET_ENABLE16_SHIFT (16U) +/*! ENABLE16 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE16_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE16_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE17_MASK (0x20000U) +#define DMA_COMMON_ENABLESET_ENABLE17_SHIFT (17U) +/*! ENABLE17 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE17_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE17_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE18_MASK (0x40000U) +#define DMA_COMMON_ENABLESET_ENABLE18_SHIFT (18U) +/*! ENABLE18 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE18_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE18_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE19_MASK (0x80000U) +#define DMA_COMMON_ENABLESET_ENABLE19_SHIFT (19U) +/*! ENABLE19 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE19_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE19_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE20_MASK (0x100000U) +#define DMA_COMMON_ENABLESET_ENABLE20_SHIFT (20U) +/*! ENABLE20 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE20_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE20_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE21_MASK (0x200000U) +#define DMA_COMMON_ENABLESET_ENABLE21_SHIFT (21U) +/*! ENABLE21 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE21_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE21_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE22_MASK (0x400000U) +#define DMA_COMMON_ENABLESET_ENABLE22_SHIFT (22U) +/*! ENABLE22 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE22_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE22_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE23_MASK (0x800000U) +#define DMA_COMMON_ENABLESET_ENABLE23_SHIFT (23U) +/*! ENABLE23 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE23_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE23_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE24_MASK (0x1000000U) +#define DMA_COMMON_ENABLESET_ENABLE24_SHIFT (24U) +/*! ENABLE24 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE24_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE24_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE25_MASK (0x2000000U) +#define DMA_COMMON_ENABLESET_ENABLE25_SHIFT (25U) +/*! ENABLE25 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE25_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE25_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE26_MASK (0x4000000U) +#define DMA_COMMON_ENABLESET_ENABLE26_SHIFT (26U) +/*! ENABLE26 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE26_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE26_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE27_MASK (0x8000000U) +#define DMA_COMMON_ENABLESET_ENABLE27_SHIFT (27U) +/*! ENABLE27 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE27_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE27_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE28_MASK (0x10000000U) +#define DMA_COMMON_ENABLESET_ENABLE28_SHIFT (28U) +/*! ENABLE28 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE28_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE28_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE29_MASK (0x20000000U) +#define DMA_COMMON_ENABLESET_ENABLE29_SHIFT (29U) +/*! ENABLE29 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE29_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE29_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE30_MASK (0x40000000U) +#define DMA_COMMON_ENABLESET_ENABLE30_SHIFT (30U) +/*! ENABLE30 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE30_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE30_MASK) + +#define DMA_COMMON_ENABLESET_ENABLE31_MASK (0x80000000U) +#define DMA_COMMON_ENABLESET_ENABLE31_SHIFT (31U) +/*! ENABLE31 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET_ENABLE31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE31_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLESET1 - Channel Enable read and set for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ENABLESET1_ENABLE32_MASK (0x1U) +#define DMA_COMMON_ENABLESET1_ENABLE32_SHIFT (0U) +/*! ENABLE32 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE32_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE32_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE33_MASK (0x2U) +#define DMA_COMMON_ENABLESET1_ENABLE33_SHIFT (1U) +/*! ENABLE33 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE33_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE33_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE34_MASK (0x4U) +#define DMA_COMMON_ENABLESET1_ENABLE34_SHIFT (2U) +/*! ENABLE34 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE34_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE34_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE35_MASK (0x8U) +#define DMA_COMMON_ENABLESET1_ENABLE35_SHIFT (3U) +/*! ENABLE35 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE35_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE35_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE36_MASK (0x10U) +#define DMA_COMMON_ENABLESET1_ENABLE36_SHIFT (4U) +/*! ENABLE36 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE36_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE36_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE37_MASK (0x20U) +#define DMA_COMMON_ENABLESET1_ENABLE37_SHIFT (5U) +/*! ENABLE37 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE37_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE37_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE38_MASK (0x40U) +#define DMA_COMMON_ENABLESET1_ENABLE38_SHIFT (6U) +/*! ENABLE38 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE38_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE38_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE39_MASK (0x80U) +#define DMA_COMMON_ENABLESET1_ENABLE39_SHIFT (7U) +/*! ENABLE39 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE39_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE39_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE40_MASK (0x100U) +#define DMA_COMMON_ENABLESET1_ENABLE40_SHIFT (8U) +/*! ENABLE40 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE40_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE40_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE41_MASK (0x200U) +#define DMA_COMMON_ENABLESET1_ENABLE41_SHIFT (9U) +/*! ENABLE41 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE41_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE41_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE42_MASK (0x400U) +#define DMA_COMMON_ENABLESET1_ENABLE42_SHIFT (10U) +/*! ENABLE42 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE42_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE42_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE43_MASK (0x800U) +#define DMA_COMMON_ENABLESET1_ENABLE43_SHIFT (11U) +/*! ENABLE43 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE43_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE43_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE44_MASK (0x1000U) +#define DMA_COMMON_ENABLESET1_ENABLE44_SHIFT (12U) +/*! ENABLE44 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE44_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE44_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE45_MASK (0x2000U) +#define DMA_COMMON_ENABLESET1_ENABLE45_SHIFT (13U) +/*! ENABLE45 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE45_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE45_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE46_MASK (0x4000U) +#define DMA_COMMON_ENABLESET1_ENABLE46_SHIFT (14U) +/*! ENABLE46 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE46_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE46_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE47_MASK (0x8000U) +#define DMA_COMMON_ENABLESET1_ENABLE47_SHIFT (15U) +/*! ENABLE47 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE47_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE47_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE48_MASK (0x10000U) +#define DMA_COMMON_ENABLESET1_ENABLE48_SHIFT (16U) +/*! ENABLE48 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE48_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE48_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE49_MASK (0x20000U) +#define DMA_COMMON_ENABLESET1_ENABLE49_SHIFT (17U) +/*! ENABLE49 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE49_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE49_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE50_MASK (0x40000U) +#define DMA_COMMON_ENABLESET1_ENABLE50_SHIFT (18U) +/*! ENABLE50 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE50_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE50_MASK) + +#define DMA_COMMON_ENABLESET1_ENABLE51_MASK (0x80000U) +#define DMA_COMMON_ENABLESET1_ENABLE51_SHIFT (19U) +/*! ENABLE51 - Enable for DMA channel + * 0b0..DMA channel is disabled. + * 0b1..DMA channel is enabled. + */ +#define DMA_COMMON_ENABLESET1_ENABLE51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE51_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET1 */ +#define DMA_COMMON_ENABLESET1_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) +#define DMA_COMMON_ENABLECLR_CLR0_SHIFT (0U) +/*! CLR0 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK) + +#define DMA_COMMON_ENABLECLR_CLR1_MASK (0x2U) +#define DMA_COMMON_ENABLECLR_CLR1_SHIFT (1U) +/*! CLR1 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR1_SHIFT)) & DMA_COMMON_ENABLECLR_CLR1_MASK) + +#define DMA_COMMON_ENABLECLR_CLR2_MASK (0x4U) +#define DMA_COMMON_ENABLECLR_CLR2_SHIFT (2U) +/*! CLR2 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR2_SHIFT)) & DMA_COMMON_ENABLECLR_CLR2_MASK) + +#define DMA_COMMON_ENABLECLR_CLR3_MASK (0x8U) +#define DMA_COMMON_ENABLECLR_CLR3_SHIFT (3U) +/*! CLR3 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR3_SHIFT)) & DMA_COMMON_ENABLECLR_CLR3_MASK) + +#define DMA_COMMON_ENABLECLR_CLR4_MASK (0x10U) +#define DMA_COMMON_ENABLECLR_CLR4_SHIFT (4U) +/*! CLR4 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR4_SHIFT)) & DMA_COMMON_ENABLECLR_CLR4_MASK) + +#define DMA_COMMON_ENABLECLR_CLR5_MASK (0x20U) +#define DMA_COMMON_ENABLECLR_CLR5_SHIFT (5U) +/*! CLR5 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR5_SHIFT)) & DMA_COMMON_ENABLECLR_CLR5_MASK) + +#define DMA_COMMON_ENABLECLR_CLR6_MASK (0x40U) +#define DMA_COMMON_ENABLECLR_CLR6_SHIFT (6U) +/*! CLR6 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR6_SHIFT)) & DMA_COMMON_ENABLECLR_CLR6_MASK) + +#define DMA_COMMON_ENABLECLR_CLR7_MASK (0x80U) +#define DMA_COMMON_ENABLECLR_CLR7_SHIFT (7U) +/*! CLR7 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR7_SHIFT)) & DMA_COMMON_ENABLECLR_CLR7_MASK) + +#define DMA_COMMON_ENABLECLR_CLR8_MASK (0x100U) +#define DMA_COMMON_ENABLECLR_CLR8_SHIFT (8U) +/*! CLR8 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR8_SHIFT)) & DMA_COMMON_ENABLECLR_CLR8_MASK) + +#define DMA_COMMON_ENABLECLR_CLR9_MASK (0x200U) +#define DMA_COMMON_ENABLECLR_CLR9_SHIFT (9U) +/*! CLR9 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR9_SHIFT)) & DMA_COMMON_ENABLECLR_CLR9_MASK) + +#define DMA_COMMON_ENABLECLR_CLR10_MASK (0x400U) +#define DMA_COMMON_ENABLECLR_CLR10_SHIFT (10U) +/*! CLR10 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR10_SHIFT)) & DMA_COMMON_ENABLECLR_CLR10_MASK) + +#define DMA_COMMON_ENABLECLR_CLR11_MASK (0x800U) +#define DMA_COMMON_ENABLECLR_CLR11_SHIFT (11U) +/*! CLR11 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR11_SHIFT)) & DMA_COMMON_ENABLECLR_CLR11_MASK) + +#define DMA_COMMON_ENABLECLR_CLR12_MASK (0x1000U) +#define DMA_COMMON_ENABLECLR_CLR12_SHIFT (12U) +/*! CLR12 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR12_SHIFT)) & DMA_COMMON_ENABLECLR_CLR12_MASK) + +#define DMA_COMMON_ENABLECLR_CLR13_MASK (0x2000U) +#define DMA_COMMON_ENABLECLR_CLR13_SHIFT (13U) +/*! CLR13 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR13_SHIFT)) & DMA_COMMON_ENABLECLR_CLR13_MASK) + +#define DMA_COMMON_ENABLECLR_CLR14_MASK (0x4000U) +#define DMA_COMMON_ENABLECLR_CLR14_SHIFT (14U) +/*! CLR14 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR14_SHIFT)) & DMA_COMMON_ENABLECLR_CLR14_MASK) + +#define DMA_COMMON_ENABLECLR_CLR15_MASK (0x8000U) +#define DMA_COMMON_ENABLECLR_CLR15_SHIFT (15U) +/*! CLR15 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR15_SHIFT)) & DMA_COMMON_ENABLECLR_CLR15_MASK) + +#define DMA_COMMON_ENABLECLR_CLR16_MASK (0x10000U) +#define DMA_COMMON_ENABLECLR_CLR16_SHIFT (16U) +/*! CLR16 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR16_SHIFT)) & DMA_COMMON_ENABLECLR_CLR16_MASK) + +#define DMA_COMMON_ENABLECLR_CLR17_MASK (0x20000U) +#define DMA_COMMON_ENABLECLR_CLR17_SHIFT (17U) +/*! CLR17 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR17_SHIFT)) & DMA_COMMON_ENABLECLR_CLR17_MASK) + +#define DMA_COMMON_ENABLECLR_CLR18_MASK (0x40000U) +#define DMA_COMMON_ENABLECLR_CLR18_SHIFT (18U) +/*! CLR18 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR18_SHIFT)) & DMA_COMMON_ENABLECLR_CLR18_MASK) + +#define DMA_COMMON_ENABLECLR_CLR19_MASK (0x80000U) +#define DMA_COMMON_ENABLECLR_CLR19_SHIFT (19U) +/*! CLR19 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR19_SHIFT)) & DMA_COMMON_ENABLECLR_CLR19_MASK) + +#define DMA_COMMON_ENABLECLR_CLR20_MASK (0x100000U) +#define DMA_COMMON_ENABLECLR_CLR20_SHIFT (20U) +/*! CLR20 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR20_SHIFT)) & DMA_COMMON_ENABLECLR_CLR20_MASK) + +#define DMA_COMMON_ENABLECLR_CLR21_MASK (0x200000U) +#define DMA_COMMON_ENABLECLR_CLR21_SHIFT (21U) +/*! CLR21 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR21_SHIFT)) & DMA_COMMON_ENABLECLR_CLR21_MASK) + +#define DMA_COMMON_ENABLECLR_CLR22_MASK (0x400000U) +#define DMA_COMMON_ENABLECLR_CLR22_SHIFT (22U) +/*! CLR22 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR22_SHIFT)) & DMA_COMMON_ENABLECLR_CLR22_MASK) + +#define DMA_COMMON_ENABLECLR_CLR23_MASK (0x800000U) +#define DMA_COMMON_ENABLECLR_CLR23_SHIFT (23U) +/*! CLR23 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR23_SHIFT)) & DMA_COMMON_ENABLECLR_CLR23_MASK) + +#define DMA_COMMON_ENABLECLR_CLR24_MASK (0x1000000U) +#define DMA_COMMON_ENABLECLR_CLR24_SHIFT (24U) +/*! CLR24 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR24_SHIFT)) & DMA_COMMON_ENABLECLR_CLR24_MASK) + +#define DMA_COMMON_ENABLECLR_CLR25_MASK (0x2000000U) +#define DMA_COMMON_ENABLECLR_CLR25_SHIFT (25U) +/*! CLR25 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR25_SHIFT)) & DMA_COMMON_ENABLECLR_CLR25_MASK) + +#define DMA_COMMON_ENABLECLR_CLR26_MASK (0x4000000U) +#define DMA_COMMON_ENABLECLR_CLR26_SHIFT (26U) +/*! CLR26 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR26_SHIFT)) & DMA_COMMON_ENABLECLR_CLR26_MASK) + +#define DMA_COMMON_ENABLECLR_CLR27_MASK (0x8000000U) +#define DMA_COMMON_ENABLECLR_CLR27_SHIFT (27U) +/*! CLR27 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR27_SHIFT)) & DMA_COMMON_ENABLECLR_CLR27_MASK) + +#define DMA_COMMON_ENABLECLR_CLR28_MASK (0x10000000U) +#define DMA_COMMON_ENABLECLR_CLR28_SHIFT (28U) +/*! CLR28 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR28_SHIFT)) & DMA_COMMON_ENABLECLR_CLR28_MASK) + +#define DMA_COMMON_ENABLECLR_CLR29_MASK (0x20000000U) +#define DMA_COMMON_ENABLECLR_CLR29_SHIFT (29U) +/*! CLR29 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR29_SHIFT)) & DMA_COMMON_ENABLECLR_CLR29_MASK) + +#define DMA_COMMON_ENABLECLR_CLR30_MASK (0x40000000U) +#define DMA_COMMON_ENABLECLR_CLR30_SHIFT (30U) +/*! CLR30 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR30_SHIFT)) & DMA_COMMON_ENABLECLR_CLR30_MASK) + +#define DMA_COMMON_ENABLECLR_CLR31_MASK (0x80000000U) +#define DMA_COMMON_ENABLECLR_CLR31_SHIFT (31U) +/*! CLR31 - Writing ones to this register clears the corresponding bits in ENABLESET0. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR31_SHIFT)) & DMA_COMMON_ENABLECLR_CLR31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ENABLECLR1 - Channel Enable Clear for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) +#define DMA_COMMON_ENABLECLR1_CLR32_SHIFT (0U) +/*! CLR32 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR33_MASK (0x2U) +#define DMA_COMMON_ENABLECLR1_CLR33_SHIFT (1U) +/*! CLR33 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR33_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR33_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR34_MASK (0x4U) +#define DMA_COMMON_ENABLECLR1_CLR34_SHIFT (2U) +/*! CLR34 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR34_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR34_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR35_MASK (0x8U) +#define DMA_COMMON_ENABLECLR1_CLR35_SHIFT (3U) +/*! CLR35 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR35_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR35_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR36_MASK (0x10U) +#define DMA_COMMON_ENABLECLR1_CLR36_SHIFT (4U) +/*! CLR36 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR36_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR36_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR37_MASK (0x20U) +#define DMA_COMMON_ENABLECLR1_CLR37_SHIFT (5U) +/*! CLR37 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR37_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR37_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR38_MASK (0x40U) +#define DMA_COMMON_ENABLECLR1_CLR38_SHIFT (6U) +/*! CLR38 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR38_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR38_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR39_MASK (0x80U) +#define DMA_COMMON_ENABLECLR1_CLR39_SHIFT (7U) +/*! CLR39 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR39_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR39_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR40_MASK (0x100U) +#define DMA_COMMON_ENABLECLR1_CLR40_SHIFT (8U) +/*! CLR40 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR40_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR40_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR41_MASK (0x200U) +#define DMA_COMMON_ENABLECLR1_CLR41_SHIFT (9U) +/*! CLR41 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR41_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR41_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR42_MASK (0x400U) +#define DMA_COMMON_ENABLECLR1_CLR42_SHIFT (10U) +/*! CLR42 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR42_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR42_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR43_MASK (0x800U) +#define DMA_COMMON_ENABLECLR1_CLR43_SHIFT (11U) +/*! CLR43 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR43_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR43_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR44_MASK (0x1000U) +#define DMA_COMMON_ENABLECLR1_CLR44_SHIFT (12U) +/*! CLR44 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR44_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR44_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR45_MASK (0x2000U) +#define DMA_COMMON_ENABLECLR1_CLR45_SHIFT (13U) +/*! CLR45 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR45_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR45_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR46_MASK (0x4000U) +#define DMA_COMMON_ENABLECLR1_CLR46_SHIFT (14U) +/*! CLR46 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR46_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR46_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR47_MASK (0x8000U) +#define DMA_COMMON_ENABLECLR1_CLR47_SHIFT (15U) +/*! CLR47 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR47_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR47_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR48_MASK (0x10000U) +#define DMA_COMMON_ENABLECLR1_CLR48_SHIFT (16U) +/*! CLR48 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR48_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR48_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR49_MASK (0x20000U) +#define DMA_COMMON_ENABLECLR1_CLR49_SHIFT (17U) +/*! CLR49 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR49_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR49_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR50_MASK (0x40000U) +#define DMA_COMMON_ENABLECLR1_CLR50_SHIFT (18U) +/*! CLR50 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR50_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR50_MASK) + +#define DMA_COMMON_ENABLECLR1_CLR51_MASK (0x80000U) +#define DMA_COMMON_ENABLECLR1_CLR51_SHIFT (19U) +/*! CLR51 - Writing ones to this register clears the corresponding bits in ENABLESET1. + * 0b0..No effect. + * 0b1..DMA channel is cleared. + */ +#define DMA_COMMON_ENABLECLR1_CLR51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR51_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR1 */ +#define DMA_COMMON_ENABLECLR1_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ACTIVE_ACTIVE0_MASK (0x1U) +#define DMA_COMMON_ACTIVE_ACTIVE0_SHIFT (0U) +/*! ACTIVE0 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE0_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE0_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE1_MASK (0x2U) +#define DMA_COMMON_ACTIVE_ACTIVE1_SHIFT (1U) +/*! ACTIVE1 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE1_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE1_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE2_MASK (0x4U) +#define DMA_COMMON_ACTIVE_ACTIVE2_SHIFT (2U) +/*! ACTIVE2 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE2_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE2_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE3_MASK (0x8U) +#define DMA_COMMON_ACTIVE_ACTIVE3_SHIFT (3U) +/*! ACTIVE3 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE3_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE3_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE4_MASK (0x10U) +#define DMA_COMMON_ACTIVE_ACTIVE4_SHIFT (4U) +/*! ACTIVE4 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE4_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE4_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE5_MASK (0x20U) +#define DMA_COMMON_ACTIVE_ACTIVE5_SHIFT (5U) +/*! ACTIVE5 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE5_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE5_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE6_MASK (0x40U) +#define DMA_COMMON_ACTIVE_ACTIVE6_SHIFT (6U) +/*! ACTIVE6 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE6_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE6_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE7_MASK (0x80U) +#define DMA_COMMON_ACTIVE_ACTIVE7_SHIFT (7U) +/*! ACTIVE7 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE7_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE7_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE8_MASK (0x100U) +#define DMA_COMMON_ACTIVE_ACTIVE8_SHIFT (8U) +/*! ACTIVE8 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE8_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE8_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE9_MASK (0x200U) +#define DMA_COMMON_ACTIVE_ACTIVE9_SHIFT (9U) +/*! ACTIVE9 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE9_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE9_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE10_MASK (0x400U) +#define DMA_COMMON_ACTIVE_ACTIVE10_SHIFT (10U) +/*! ACTIVE10 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE10_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE10_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE11_MASK (0x800U) +#define DMA_COMMON_ACTIVE_ACTIVE11_SHIFT (11U) +/*! ACTIVE11 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE11_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE11_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE12_MASK (0x1000U) +#define DMA_COMMON_ACTIVE_ACTIVE12_SHIFT (12U) +/*! ACTIVE12 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE12_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE12_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE13_MASK (0x2000U) +#define DMA_COMMON_ACTIVE_ACTIVE13_SHIFT (13U) +/*! ACTIVE13 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE13_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE13_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE14_MASK (0x4000U) +#define DMA_COMMON_ACTIVE_ACTIVE14_SHIFT (14U) +/*! ACTIVE14 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE14_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE14_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE15_MASK (0x8000U) +#define DMA_COMMON_ACTIVE_ACTIVE15_SHIFT (15U) +/*! ACTIVE15 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE15_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE15_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE16_MASK (0x10000U) +#define DMA_COMMON_ACTIVE_ACTIVE16_SHIFT (16U) +/*! ACTIVE16 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE16_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE16_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE17_MASK (0x20000U) +#define DMA_COMMON_ACTIVE_ACTIVE17_SHIFT (17U) +/*! ACTIVE17 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE17_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE17_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE18_MASK (0x40000U) +#define DMA_COMMON_ACTIVE_ACTIVE18_SHIFT (18U) +/*! ACTIVE18 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE18_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE18_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE19_MASK (0x80000U) +#define DMA_COMMON_ACTIVE_ACTIVE19_SHIFT (19U) +/*! ACTIVE19 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE19_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE19_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE20_MASK (0x100000U) +#define DMA_COMMON_ACTIVE_ACTIVE20_SHIFT (20U) +/*! ACTIVE20 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE20_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE20_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE21_MASK (0x200000U) +#define DMA_COMMON_ACTIVE_ACTIVE21_SHIFT (21U) +/*! ACTIVE21 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE21_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE21_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE22_MASK (0x400000U) +#define DMA_COMMON_ACTIVE_ACTIVE22_SHIFT (22U) +/*! ACTIVE22 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE22_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE22_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE23_MASK (0x800000U) +#define DMA_COMMON_ACTIVE_ACTIVE23_SHIFT (23U) +/*! ACTIVE23 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE23_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE23_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE24_MASK (0x1000000U) +#define DMA_COMMON_ACTIVE_ACTIVE24_SHIFT (24U) +/*! ACTIVE24 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE24_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE24_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE25_MASK (0x2000000U) +#define DMA_COMMON_ACTIVE_ACTIVE25_SHIFT (25U) +/*! ACTIVE25 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE25_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE25_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE26_MASK (0x4000000U) +#define DMA_COMMON_ACTIVE_ACTIVE26_SHIFT (26U) +/*! ACTIVE26 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE26_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE26_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE27_MASK (0x8000000U) +#define DMA_COMMON_ACTIVE_ACTIVE27_SHIFT (27U) +/*! ACTIVE27 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE27_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE27_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE28_MASK (0x10000000U) +#define DMA_COMMON_ACTIVE_ACTIVE28_SHIFT (28U) +/*! ACTIVE28 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE28_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE28_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE29_MASK (0x20000000U) +#define DMA_COMMON_ACTIVE_ACTIVE29_SHIFT (29U) +/*! ACTIVE29 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE29_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE29_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE30_MASK (0x40000000U) +#define DMA_COMMON_ACTIVE_ACTIVE30_SHIFT (30U) +/*! ACTIVE30 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE30_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE30_MASK) + +#define DMA_COMMON_ACTIVE_ACTIVE31_MASK (0x80000000U) +#define DMA_COMMON_ACTIVE_ACTIVE31_SHIFT (31U) +/*! ACTIVE31 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE_ACTIVE31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE31_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_ACTIVE1 - Channel Active status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ACTIVE1_ACTIVE32_MASK (0x1U) +#define DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT (0U) +/*! ACTIVE32 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE32_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE33_MASK (0x2U) +#define DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT (1U) +/*! ACTIVE33 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE33_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE34_MASK (0x4U) +#define DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT (2U) +/*! ACTIVE34 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE34_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE35_MASK (0x8U) +#define DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT (3U) +/*! ACTIVE35 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE35_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE36_MASK (0x10U) +#define DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT (4U) +/*! ACTIVE36 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE36_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE37_MASK (0x20U) +#define DMA_COMMON_ACTIVE1_ACTIVE37_SHIFT (5U) +/*! ACTIVE37 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE37_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE37_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE38_MASK (0x40U) +#define DMA_COMMON_ACTIVE1_ACTIVE38_SHIFT (6U) +/*! ACTIVE38 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE38_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE38_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE39_MASK (0x80U) +#define DMA_COMMON_ACTIVE1_ACTIVE39_SHIFT (7U) +/*! ACTIVE39 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE39_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE39_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE40_MASK (0x100U) +#define DMA_COMMON_ACTIVE1_ACTIVE40_SHIFT (8U) +/*! ACTIVE40 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE40_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE40_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE41_MASK (0x200U) +#define DMA_COMMON_ACTIVE1_ACTIVE41_SHIFT (9U) +/*! ACTIVE41 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE41_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE41_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE42_MASK (0x400U) +#define DMA_COMMON_ACTIVE1_ACTIVE42_SHIFT (10U) +/*! ACTIVE42 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE42_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE42_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE43_MASK (0x800U) +#define DMA_COMMON_ACTIVE1_ACTIVE43_SHIFT (11U) +/*! ACTIVE43 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE43_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE43_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE44_MASK (0x1000U) +#define DMA_COMMON_ACTIVE1_ACTIVE44_SHIFT (12U) +/*! ACTIVE44 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE44_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE44_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE45_MASK (0x2000U) +#define DMA_COMMON_ACTIVE1_ACTIVE45_SHIFT (13U) +/*! ACTIVE45 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE45_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE45_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE46_MASK (0x4000U) +#define DMA_COMMON_ACTIVE1_ACTIVE46_SHIFT (14U) +/*! ACTIVE46 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE46_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE46_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE47_MASK (0x8000U) +#define DMA_COMMON_ACTIVE1_ACTIVE47_SHIFT (15U) +/*! ACTIVE47 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE47_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE47_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE48_MASK (0x10000U) +#define DMA_COMMON_ACTIVE1_ACTIVE48_SHIFT (16U) +/*! ACTIVE48 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE48_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE48_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE49_MASK (0x20000U) +#define DMA_COMMON_ACTIVE1_ACTIVE49_SHIFT (17U) +/*! ACTIVE49 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE49_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE49_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE50_MASK (0x40000U) +#define DMA_COMMON_ACTIVE1_ACTIVE50_SHIFT (18U) +/*! ACTIVE50 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE50_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE50_MASK) + +#define DMA_COMMON_ACTIVE1_ACTIVE51_MASK (0x80000U) +#define DMA_COMMON_ACTIVE1_ACTIVE51_SHIFT (19U) +/*! ACTIVE51 - Active flag for DMA channel. + * 0b0..DMA channel is not active. + * 0b1..DMA channel is active. + */ +#define DMA_COMMON_ACTIVE1_ACTIVE51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE51_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE1 */ +#define DMA_COMMON_ACTIVE1_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_BUSY_BUSY0_MASK (0x1U) +#define DMA_COMMON_BUSY_BUSY0_SHIFT (0U) +/*! BUSY0 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY0_SHIFT)) & DMA_COMMON_BUSY_BUSY0_MASK) + +#define DMA_COMMON_BUSY_BUSY1_MASK (0x2U) +#define DMA_COMMON_BUSY_BUSY1_SHIFT (1U) +/*! BUSY1 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY1_SHIFT)) & DMA_COMMON_BUSY_BUSY1_MASK) + +#define DMA_COMMON_BUSY_BUSY2_MASK (0x4U) +#define DMA_COMMON_BUSY_BUSY2_SHIFT (2U) +/*! BUSY2 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY2_SHIFT)) & DMA_COMMON_BUSY_BUSY2_MASK) + +#define DMA_COMMON_BUSY_BUSY3_MASK (0x8U) +#define DMA_COMMON_BUSY_BUSY3_SHIFT (3U) +/*! BUSY3 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY3_SHIFT)) & DMA_COMMON_BUSY_BUSY3_MASK) + +#define DMA_COMMON_BUSY_BUSY4_MASK (0x10U) +#define DMA_COMMON_BUSY_BUSY4_SHIFT (4U) +/*! BUSY4 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY4_SHIFT)) & DMA_COMMON_BUSY_BUSY4_MASK) + +#define DMA_COMMON_BUSY_BUSY5_MASK (0x20U) +#define DMA_COMMON_BUSY_BUSY5_SHIFT (5U) +/*! BUSY5 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY5_SHIFT)) & DMA_COMMON_BUSY_BUSY5_MASK) + +#define DMA_COMMON_BUSY_BUSY6_MASK (0x40U) +#define DMA_COMMON_BUSY_BUSY6_SHIFT (6U) +/*! BUSY6 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY6_SHIFT)) & DMA_COMMON_BUSY_BUSY6_MASK) + +#define DMA_COMMON_BUSY_BUSY7_MASK (0x80U) +#define DMA_COMMON_BUSY_BUSY7_SHIFT (7U) +/*! BUSY7 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY7_SHIFT)) & DMA_COMMON_BUSY_BUSY7_MASK) + +#define DMA_COMMON_BUSY_BUSY8_MASK (0x100U) +#define DMA_COMMON_BUSY_BUSY8_SHIFT (8U) +/*! BUSY8 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY8_SHIFT)) & DMA_COMMON_BUSY_BUSY8_MASK) + +#define DMA_COMMON_BUSY_BUSY9_MASK (0x200U) +#define DMA_COMMON_BUSY_BUSY9_SHIFT (9U) +/*! BUSY9 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY9_SHIFT)) & DMA_COMMON_BUSY_BUSY9_MASK) + +#define DMA_COMMON_BUSY_BUSY10_MASK (0x400U) +#define DMA_COMMON_BUSY_BUSY10_SHIFT (10U) +/*! BUSY10 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY10_SHIFT)) & DMA_COMMON_BUSY_BUSY10_MASK) + +#define DMA_COMMON_BUSY_BUSY11_MASK (0x800U) +#define DMA_COMMON_BUSY_BUSY11_SHIFT (11U) +/*! BUSY11 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY11_SHIFT)) & DMA_COMMON_BUSY_BUSY11_MASK) + +#define DMA_COMMON_BUSY_BUSY12_MASK (0x1000U) +#define DMA_COMMON_BUSY_BUSY12_SHIFT (12U) +/*! BUSY12 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY12_SHIFT)) & DMA_COMMON_BUSY_BUSY12_MASK) + +#define DMA_COMMON_BUSY_BUSY13_MASK (0x2000U) +#define DMA_COMMON_BUSY_BUSY13_SHIFT (13U) +/*! BUSY13 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY13_SHIFT)) & DMA_COMMON_BUSY_BUSY13_MASK) + +#define DMA_COMMON_BUSY_BUSY14_MASK (0x4000U) +#define DMA_COMMON_BUSY_BUSY14_SHIFT (14U) +/*! BUSY14 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY14_SHIFT)) & DMA_COMMON_BUSY_BUSY14_MASK) + +#define DMA_COMMON_BUSY_BUSY15_MASK (0x8000U) +#define DMA_COMMON_BUSY_BUSY15_SHIFT (15U) +/*! BUSY15 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY15_SHIFT)) & DMA_COMMON_BUSY_BUSY15_MASK) + +#define DMA_COMMON_BUSY_BUSY16_MASK (0x10000U) +#define DMA_COMMON_BUSY_BUSY16_SHIFT (16U) +/*! BUSY16 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY16_SHIFT)) & DMA_COMMON_BUSY_BUSY16_MASK) + +#define DMA_COMMON_BUSY_BUSY17_MASK (0x20000U) +#define DMA_COMMON_BUSY_BUSY17_SHIFT (17U) +/*! BUSY17 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY17_SHIFT)) & DMA_COMMON_BUSY_BUSY17_MASK) + +#define DMA_COMMON_BUSY_BUSY18_MASK (0x40000U) +#define DMA_COMMON_BUSY_BUSY18_SHIFT (18U) +/*! BUSY18 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY18_SHIFT)) & DMA_COMMON_BUSY_BUSY18_MASK) + +#define DMA_COMMON_BUSY_BUSY19_MASK (0x80000U) +#define DMA_COMMON_BUSY_BUSY19_SHIFT (19U) +/*! BUSY19 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY19_SHIFT)) & DMA_COMMON_BUSY_BUSY19_MASK) + +#define DMA_COMMON_BUSY_BUSY20_MASK (0x100000U) +#define DMA_COMMON_BUSY_BUSY20_SHIFT (20U) +/*! BUSY20 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY20_SHIFT)) & DMA_COMMON_BUSY_BUSY20_MASK) + +#define DMA_COMMON_BUSY_BUSY21_MASK (0x200000U) +#define DMA_COMMON_BUSY_BUSY21_SHIFT (21U) +/*! BUSY21 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY21_SHIFT)) & DMA_COMMON_BUSY_BUSY21_MASK) + +#define DMA_COMMON_BUSY_BUSY22_MASK (0x400000U) +#define DMA_COMMON_BUSY_BUSY22_SHIFT (22U) +/*! BUSY22 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY22_SHIFT)) & DMA_COMMON_BUSY_BUSY22_MASK) + +#define DMA_COMMON_BUSY_BUSY23_MASK (0x800000U) +#define DMA_COMMON_BUSY_BUSY23_SHIFT (23U) +/*! BUSY23 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY23_SHIFT)) & DMA_COMMON_BUSY_BUSY23_MASK) + +#define DMA_COMMON_BUSY_BUSY24_MASK (0x1000000U) +#define DMA_COMMON_BUSY_BUSY24_SHIFT (24U) +/*! BUSY24 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY24_SHIFT)) & DMA_COMMON_BUSY_BUSY24_MASK) + +#define DMA_COMMON_BUSY_BUSY25_MASK (0x2000000U) +#define DMA_COMMON_BUSY_BUSY25_SHIFT (25U) +/*! BUSY25 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY25_SHIFT)) & DMA_COMMON_BUSY_BUSY25_MASK) + +#define DMA_COMMON_BUSY_BUSY26_MASK (0x4000000U) +#define DMA_COMMON_BUSY_BUSY26_SHIFT (26U) +/*! BUSY26 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY26_SHIFT)) & DMA_COMMON_BUSY_BUSY26_MASK) + +#define DMA_COMMON_BUSY_BUSY27_MASK (0x8000000U) +#define DMA_COMMON_BUSY_BUSY27_SHIFT (27U) +/*! BUSY27 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY27_SHIFT)) & DMA_COMMON_BUSY_BUSY27_MASK) + +#define DMA_COMMON_BUSY_BUSY28_MASK (0x10000000U) +#define DMA_COMMON_BUSY_BUSY28_SHIFT (28U) +/*! BUSY28 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY28_SHIFT)) & DMA_COMMON_BUSY_BUSY28_MASK) + +#define DMA_COMMON_BUSY_BUSY29_MASK (0x20000000U) +#define DMA_COMMON_BUSY_BUSY29_SHIFT (29U) +/*! BUSY29 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY29_SHIFT)) & DMA_COMMON_BUSY_BUSY29_MASK) + +#define DMA_COMMON_BUSY_BUSY30_MASK (0x40000000U) +#define DMA_COMMON_BUSY_BUSY30_SHIFT (30U) +/*! BUSY30 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY30_SHIFT)) & DMA_COMMON_BUSY_BUSY30_MASK) + +#define DMA_COMMON_BUSY_BUSY31_MASK (0x80000000U) +#define DMA_COMMON_BUSY_BUSY31_SHIFT (31U) +/*! BUSY31 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY_BUSY31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY31_SHIFT)) & DMA_COMMON_BUSY_BUSY31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_BUSY1 - Channel Busy status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_BUSY1_BUSY32_MASK (0x1U) +#define DMA_COMMON_BUSY1_BUSY32_SHIFT (0U) +/*! BUSY32 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY32_SHIFT)) & DMA_COMMON_BUSY1_BUSY32_MASK) + +#define DMA_COMMON_BUSY1_BUSY33_MASK (0x2U) +#define DMA_COMMON_BUSY1_BUSY33_SHIFT (1U) +/*! BUSY33 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY33_SHIFT)) & DMA_COMMON_BUSY1_BUSY33_MASK) + +#define DMA_COMMON_BUSY1_BUSY34_MASK (0x4U) +#define DMA_COMMON_BUSY1_BUSY34_SHIFT (2U) +/*! BUSY34 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY34_SHIFT)) & DMA_COMMON_BUSY1_BUSY34_MASK) + +#define DMA_COMMON_BUSY1_BUSY35_MASK (0x8U) +#define DMA_COMMON_BUSY1_BUSY35_SHIFT (3U) +/*! BUSY35 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY35_SHIFT)) & DMA_COMMON_BUSY1_BUSY35_MASK) + +#define DMA_COMMON_BUSY1_BUSY36_MASK (0x10U) +#define DMA_COMMON_BUSY1_BUSY36_SHIFT (4U) +/*! BUSY36 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY36_SHIFT)) & DMA_COMMON_BUSY1_BUSY36_MASK) + +#define DMA_COMMON_BUSY1_BUSY37_MASK (0x20U) +#define DMA_COMMON_BUSY1_BUSY37_SHIFT (5U) +/*! BUSY37 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY37_SHIFT)) & DMA_COMMON_BUSY1_BUSY37_MASK) + +#define DMA_COMMON_BUSY1_BUSY38_MASK (0x40U) +#define DMA_COMMON_BUSY1_BUSY38_SHIFT (6U) +/*! BUSY38 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY38_SHIFT)) & DMA_COMMON_BUSY1_BUSY38_MASK) + +#define DMA_COMMON_BUSY1_BUSY39_MASK (0x80U) +#define DMA_COMMON_BUSY1_BUSY39_SHIFT (7U) +/*! BUSY39 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY39_SHIFT)) & DMA_COMMON_BUSY1_BUSY39_MASK) + +#define DMA_COMMON_BUSY1_BUSY40_MASK (0x100U) +#define DMA_COMMON_BUSY1_BUSY40_SHIFT (8U) +/*! BUSY40 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY40_SHIFT)) & DMA_COMMON_BUSY1_BUSY40_MASK) + +#define DMA_COMMON_BUSY1_BUSY41_MASK (0x200U) +#define DMA_COMMON_BUSY1_BUSY41_SHIFT (9U) +/*! BUSY41 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY41_SHIFT)) & DMA_COMMON_BUSY1_BUSY41_MASK) + +#define DMA_COMMON_BUSY1_BUSY42_MASK (0x400U) +#define DMA_COMMON_BUSY1_BUSY42_SHIFT (10U) +/*! BUSY42 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY42_SHIFT)) & DMA_COMMON_BUSY1_BUSY42_MASK) + +#define DMA_COMMON_BUSY1_BUSY43_MASK (0x800U) +#define DMA_COMMON_BUSY1_BUSY43_SHIFT (11U) +/*! BUSY43 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY43_SHIFT)) & DMA_COMMON_BUSY1_BUSY43_MASK) + +#define DMA_COMMON_BUSY1_BUSY44_MASK (0x1000U) +#define DMA_COMMON_BUSY1_BUSY44_SHIFT (12U) +/*! BUSY44 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY44_SHIFT)) & DMA_COMMON_BUSY1_BUSY44_MASK) + +#define DMA_COMMON_BUSY1_BUSY45_MASK (0x2000U) +#define DMA_COMMON_BUSY1_BUSY45_SHIFT (13U) +/*! BUSY45 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY45_SHIFT)) & DMA_COMMON_BUSY1_BUSY45_MASK) + +#define DMA_COMMON_BUSY1_BUSY46_MASK (0x4000U) +#define DMA_COMMON_BUSY1_BUSY46_SHIFT (14U) +/*! BUSY46 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY46_SHIFT)) & DMA_COMMON_BUSY1_BUSY46_MASK) + +#define DMA_COMMON_BUSY1_BUSY47_MASK (0x8000U) +#define DMA_COMMON_BUSY1_BUSY47_SHIFT (15U) +/*! BUSY47 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY47_SHIFT)) & DMA_COMMON_BUSY1_BUSY47_MASK) + +#define DMA_COMMON_BUSY1_BUSY48_MASK (0x10000U) +#define DMA_COMMON_BUSY1_BUSY48_SHIFT (16U) +/*! BUSY48 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY48_SHIFT)) & DMA_COMMON_BUSY1_BUSY48_MASK) + +#define DMA_COMMON_BUSY1_BUSY49_MASK (0x20000U) +#define DMA_COMMON_BUSY1_BUSY49_SHIFT (17U) +/*! BUSY49 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY49_SHIFT)) & DMA_COMMON_BUSY1_BUSY49_MASK) + +#define DMA_COMMON_BUSY1_BUSY50_MASK (0x40000U) +#define DMA_COMMON_BUSY1_BUSY50_SHIFT (18U) +/*! BUSY50 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY50_SHIFT)) & DMA_COMMON_BUSY1_BUSY50_MASK) + +#define DMA_COMMON_BUSY1_BUSY51_MASK (0x80000U) +#define DMA_COMMON_BUSY1_BUSY51_SHIFT (19U) +/*! BUSY51 - Busy flag for DMA channel. + * 0b0..DMA channel is not busy. + * 0b1..DMA channel is busy. + */ +#define DMA_COMMON_BUSY1_BUSY51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY51_SHIFT)) & DMA_COMMON_BUSY1_BUSY51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY1 */ +#define DMA_COMMON_BUSY1_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ERRINT_ERR0_MASK (0x1U) +#define DMA_COMMON_ERRINT_ERR0_SHIFT (0U) +/*! ERR0 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR0_SHIFT)) & DMA_COMMON_ERRINT_ERR0_MASK) + +#define DMA_COMMON_ERRINT_ERR1_MASK (0x2U) +#define DMA_COMMON_ERRINT_ERR1_SHIFT (1U) +/*! ERR1 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR1_SHIFT)) & DMA_COMMON_ERRINT_ERR1_MASK) + +#define DMA_COMMON_ERRINT_ERR2_MASK (0x4U) +#define DMA_COMMON_ERRINT_ERR2_SHIFT (2U) +/*! ERR2 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR2_SHIFT)) & DMA_COMMON_ERRINT_ERR2_MASK) + +#define DMA_COMMON_ERRINT_ERR3_MASK (0x8U) +#define DMA_COMMON_ERRINT_ERR3_SHIFT (3U) +/*! ERR3 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR3_SHIFT)) & DMA_COMMON_ERRINT_ERR3_MASK) + +#define DMA_COMMON_ERRINT_ERR4_MASK (0x10U) +#define DMA_COMMON_ERRINT_ERR4_SHIFT (4U) +/*! ERR4 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR4_SHIFT)) & DMA_COMMON_ERRINT_ERR4_MASK) + +#define DMA_COMMON_ERRINT_ERR5_MASK (0x20U) +#define DMA_COMMON_ERRINT_ERR5_SHIFT (5U) +/*! ERR5 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR5_SHIFT)) & DMA_COMMON_ERRINT_ERR5_MASK) + +#define DMA_COMMON_ERRINT_ERR6_MASK (0x40U) +#define DMA_COMMON_ERRINT_ERR6_SHIFT (6U) +/*! ERR6 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR6_SHIFT)) & DMA_COMMON_ERRINT_ERR6_MASK) + +#define DMA_COMMON_ERRINT_ERR7_MASK (0x80U) +#define DMA_COMMON_ERRINT_ERR7_SHIFT (7U) +/*! ERR7 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR7_SHIFT)) & DMA_COMMON_ERRINT_ERR7_MASK) + +#define DMA_COMMON_ERRINT_ERR8_MASK (0x100U) +#define DMA_COMMON_ERRINT_ERR8_SHIFT (8U) +/*! ERR8 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR8_SHIFT)) & DMA_COMMON_ERRINT_ERR8_MASK) + +#define DMA_COMMON_ERRINT_ERR9_MASK (0x200U) +#define DMA_COMMON_ERRINT_ERR9_SHIFT (9U) +/*! ERR9 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR9_SHIFT)) & DMA_COMMON_ERRINT_ERR9_MASK) + +#define DMA_COMMON_ERRINT_ERR10_MASK (0x400U) +#define DMA_COMMON_ERRINT_ERR10_SHIFT (10U) +/*! ERR10 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR10_SHIFT)) & DMA_COMMON_ERRINT_ERR10_MASK) + +#define DMA_COMMON_ERRINT_ERR11_MASK (0x800U) +#define DMA_COMMON_ERRINT_ERR11_SHIFT (11U) +/*! ERR11 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR11_SHIFT)) & DMA_COMMON_ERRINT_ERR11_MASK) + +#define DMA_COMMON_ERRINT_ERR12_MASK (0x1000U) +#define DMA_COMMON_ERRINT_ERR12_SHIFT (12U) +/*! ERR12 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR12_SHIFT)) & DMA_COMMON_ERRINT_ERR12_MASK) + +#define DMA_COMMON_ERRINT_ERR13_MASK (0x2000U) +#define DMA_COMMON_ERRINT_ERR13_SHIFT (13U) +/*! ERR13 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR13_SHIFT)) & DMA_COMMON_ERRINT_ERR13_MASK) + +#define DMA_COMMON_ERRINT_ERR14_MASK (0x4000U) +#define DMA_COMMON_ERRINT_ERR14_SHIFT (14U) +/*! ERR14 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR14_SHIFT)) & DMA_COMMON_ERRINT_ERR14_MASK) + +#define DMA_COMMON_ERRINT_ERR15_MASK (0x8000U) +#define DMA_COMMON_ERRINT_ERR15_SHIFT (15U) +/*! ERR15 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR15_SHIFT)) & DMA_COMMON_ERRINT_ERR15_MASK) + +#define DMA_COMMON_ERRINT_ERR16_MASK (0x10000U) +#define DMA_COMMON_ERRINT_ERR16_SHIFT (16U) +/*! ERR16 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR16_SHIFT)) & DMA_COMMON_ERRINT_ERR16_MASK) + +#define DMA_COMMON_ERRINT_ERR17_MASK (0x20000U) +#define DMA_COMMON_ERRINT_ERR17_SHIFT (17U) +/*! ERR17 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR17_SHIFT)) & DMA_COMMON_ERRINT_ERR17_MASK) + +#define DMA_COMMON_ERRINT_ERR18_MASK (0x40000U) +#define DMA_COMMON_ERRINT_ERR18_SHIFT (18U) +/*! ERR18 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR18_SHIFT)) & DMA_COMMON_ERRINT_ERR18_MASK) + +#define DMA_COMMON_ERRINT_ERR19_MASK (0x80000U) +#define DMA_COMMON_ERRINT_ERR19_SHIFT (19U) +/*! ERR19 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR19_SHIFT)) & DMA_COMMON_ERRINT_ERR19_MASK) + +#define DMA_COMMON_ERRINT_ERR20_MASK (0x100000U) +#define DMA_COMMON_ERRINT_ERR20_SHIFT (20U) +/*! ERR20 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR20_SHIFT)) & DMA_COMMON_ERRINT_ERR20_MASK) + +#define DMA_COMMON_ERRINT_ERR21_MASK (0x200000U) +#define DMA_COMMON_ERRINT_ERR21_SHIFT (21U) +/*! ERR21 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR21_SHIFT)) & DMA_COMMON_ERRINT_ERR21_MASK) + +#define DMA_COMMON_ERRINT_ERR22_MASK (0x400000U) +#define DMA_COMMON_ERRINT_ERR22_SHIFT (22U) +/*! ERR22 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR22_SHIFT)) & DMA_COMMON_ERRINT_ERR22_MASK) + +#define DMA_COMMON_ERRINT_ERR23_MASK (0x800000U) +#define DMA_COMMON_ERRINT_ERR23_SHIFT (23U) +/*! ERR23 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR23_SHIFT)) & DMA_COMMON_ERRINT_ERR23_MASK) + +#define DMA_COMMON_ERRINT_ERR24_MASK (0x1000000U) +#define DMA_COMMON_ERRINT_ERR24_SHIFT (24U) +/*! ERR24 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR24_SHIFT)) & DMA_COMMON_ERRINT_ERR24_MASK) + +#define DMA_COMMON_ERRINT_ERR25_MASK (0x2000000U) +#define DMA_COMMON_ERRINT_ERR25_SHIFT (25U) +/*! ERR25 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR25_SHIFT)) & DMA_COMMON_ERRINT_ERR25_MASK) + +#define DMA_COMMON_ERRINT_ERR26_MASK (0x4000000U) +#define DMA_COMMON_ERRINT_ERR26_SHIFT (26U) +/*! ERR26 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR26_SHIFT)) & DMA_COMMON_ERRINT_ERR26_MASK) + +#define DMA_COMMON_ERRINT_ERR27_MASK (0x8000000U) +#define DMA_COMMON_ERRINT_ERR27_SHIFT (27U) +/*! ERR27 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR27_SHIFT)) & DMA_COMMON_ERRINT_ERR27_MASK) + +#define DMA_COMMON_ERRINT_ERR28_MASK (0x10000000U) +#define DMA_COMMON_ERRINT_ERR28_SHIFT (28U) +/*! ERR28 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR28_SHIFT)) & DMA_COMMON_ERRINT_ERR28_MASK) + +#define DMA_COMMON_ERRINT_ERR29_MASK (0x20000000U) +#define DMA_COMMON_ERRINT_ERR29_SHIFT (29U) +/*! ERR29 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR29_SHIFT)) & DMA_COMMON_ERRINT_ERR29_MASK) + +#define DMA_COMMON_ERRINT_ERR30_MASK (0x40000000U) +#define DMA_COMMON_ERRINT_ERR30_SHIFT (30U) +/*! ERR30 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR30_SHIFT)) & DMA_COMMON_ERRINT_ERR30_MASK) + +#define DMA_COMMON_ERRINT_ERR31_MASK (0x80000000U) +#define DMA_COMMON_ERRINT_ERR31_SHIFT (31U) +/*! ERR31 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR31_SHIFT)) & DMA_COMMON_ERRINT_ERR31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_ERRINT1 - Error Interrupt status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ERRINT1_ERR32_MASK (0x1U) +#define DMA_COMMON_ERRINT1_ERR32_SHIFT (0U) +/*! ERR32 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR32_SHIFT)) & DMA_COMMON_ERRINT1_ERR32_MASK) + +#define DMA_COMMON_ERRINT1_ERR33_MASK (0x2U) +#define DMA_COMMON_ERRINT1_ERR33_SHIFT (1U) +/*! ERR33 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR33_SHIFT)) & DMA_COMMON_ERRINT1_ERR33_MASK) + +#define DMA_COMMON_ERRINT1_ERR34_MASK (0x4U) +#define DMA_COMMON_ERRINT1_ERR34_SHIFT (2U) +/*! ERR34 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR34_SHIFT)) & DMA_COMMON_ERRINT1_ERR34_MASK) + +#define DMA_COMMON_ERRINT1_ERR35_MASK (0x8U) +#define DMA_COMMON_ERRINT1_ERR35_SHIFT (3U) +/*! ERR35 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR35_SHIFT)) & DMA_COMMON_ERRINT1_ERR35_MASK) + +#define DMA_COMMON_ERRINT1_ERR36_MASK (0x10U) +#define DMA_COMMON_ERRINT1_ERR36_SHIFT (4U) +/*! ERR36 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR36_SHIFT)) & DMA_COMMON_ERRINT1_ERR36_MASK) + +#define DMA_COMMON_ERRINT1_ERR37_MASK (0x20U) +#define DMA_COMMON_ERRINT1_ERR37_SHIFT (5U) +/*! ERR37 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR37_SHIFT)) & DMA_COMMON_ERRINT1_ERR37_MASK) + +#define DMA_COMMON_ERRINT1_ERR38_MASK (0x40U) +#define DMA_COMMON_ERRINT1_ERR38_SHIFT (6U) +/*! ERR38 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR38_SHIFT)) & DMA_COMMON_ERRINT1_ERR38_MASK) + +#define DMA_COMMON_ERRINT1_ERR39_MASK (0x80U) +#define DMA_COMMON_ERRINT1_ERR39_SHIFT (7U) +/*! ERR39 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR39_SHIFT)) & DMA_COMMON_ERRINT1_ERR39_MASK) + +#define DMA_COMMON_ERRINT1_ERR40_MASK (0x100U) +#define DMA_COMMON_ERRINT1_ERR40_SHIFT (8U) +/*! ERR40 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR40_SHIFT)) & DMA_COMMON_ERRINT1_ERR40_MASK) + +#define DMA_COMMON_ERRINT1_ERR41_MASK (0x200U) +#define DMA_COMMON_ERRINT1_ERR41_SHIFT (9U) +/*! ERR41 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR41_SHIFT)) & DMA_COMMON_ERRINT1_ERR41_MASK) + +#define DMA_COMMON_ERRINT1_ERR42_MASK (0x400U) +#define DMA_COMMON_ERRINT1_ERR42_SHIFT (10U) +/*! ERR42 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR42_SHIFT)) & DMA_COMMON_ERRINT1_ERR42_MASK) + +#define DMA_COMMON_ERRINT1_ERR43_MASK (0x800U) +#define DMA_COMMON_ERRINT1_ERR43_SHIFT (11U) +/*! ERR43 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR43_SHIFT)) & DMA_COMMON_ERRINT1_ERR43_MASK) + +#define DMA_COMMON_ERRINT1_ERR44_MASK (0x1000U) +#define DMA_COMMON_ERRINT1_ERR44_SHIFT (12U) +/*! ERR44 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR44_SHIFT)) & DMA_COMMON_ERRINT1_ERR44_MASK) + +#define DMA_COMMON_ERRINT1_ERR45_MASK (0x2000U) +#define DMA_COMMON_ERRINT1_ERR45_SHIFT (13U) +/*! ERR45 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR45_SHIFT)) & DMA_COMMON_ERRINT1_ERR45_MASK) + +#define DMA_COMMON_ERRINT1_ERR46_MASK (0x4000U) +#define DMA_COMMON_ERRINT1_ERR46_SHIFT (14U) +/*! ERR46 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR46_SHIFT)) & DMA_COMMON_ERRINT1_ERR46_MASK) + +#define DMA_COMMON_ERRINT1_ERR47_MASK (0x8000U) +#define DMA_COMMON_ERRINT1_ERR47_SHIFT (15U) +/*! ERR47 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR47_SHIFT)) & DMA_COMMON_ERRINT1_ERR47_MASK) + +#define DMA_COMMON_ERRINT1_ERR48_MASK (0x10000U) +#define DMA_COMMON_ERRINT1_ERR48_SHIFT (16U) +/*! ERR48 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR48_SHIFT)) & DMA_COMMON_ERRINT1_ERR48_MASK) + +#define DMA_COMMON_ERRINT1_ERR49_MASK (0x20000U) +#define DMA_COMMON_ERRINT1_ERR49_SHIFT (17U) +/*! ERR49 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR49_SHIFT)) & DMA_COMMON_ERRINT1_ERR49_MASK) + +#define DMA_COMMON_ERRINT1_ERR50_MASK (0x40000U) +#define DMA_COMMON_ERRINT1_ERR50_SHIFT (18U) +/*! ERR50 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR50_SHIFT)) & DMA_COMMON_ERRINT1_ERR50_MASK) + +#define DMA_COMMON_ERRINT1_ERR51_MASK (0x80000U) +#define DMA_COMMON_ERRINT1_ERR51_SHIFT (19U) +/*! ERR51 - Error Interrupt flag for DMA channel. + * 0b0..The Error Interrupt is not active for DMA channel. + * 0b1..The Error Interrupt is pending for DMA channel. + */ +#define DMA_COMMON_ERRINT1_ERR51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR51_SHIFT)) & DMA_COMMON_ERRINT1_ERR51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT1 */ +#define DMA_COMMON_ERRINT1_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTENSET_INTEN0_MASK (0x1U) +#define DMA_COMMON_INTENSET_INTEN0_SHIFT (0U) +/*! INTEN0 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN0_SHIFT)) & DMA_COMMON_INTENSET_INTEN0_MASK) + +#define DMA_COMMON_INTENSET_INTEN1_MASK (0x2U) +#define DMA_COMMON_INTENSET_INTEN1_SHIFT (1U) +/*! INTEN1 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN1_SHIFT)) & DMA_COMMON_INTENSET_INTEN1_MASK) + +#define DMA_COMMON_INTENSET_INTEN2_MASK (0x4U) +#define DMA_COMMON_INTENSET_INTEN2_SHIFT (2U) +/*! INTEN2 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN2_SHIFT)) & DMA_COMMON_INTENSET_INTEN2_MASK) + +#define DMA_COMMON_INTENSET_INTEN3_MASK (0x8U) +#define DMA_COMMON_INTENSET_INTEN3_SHIFT (3U) +/*! INTEN3 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN3_SHIFT)) & DMA_COMMON_INTENSET_INTEN3_MASK) + +#define DMA_COMMON_INTENSET_INTEN4_MASK (0x10U) +#define DMA_COMMON_INTENSET_INTEN4_SHIFT (4U) +/*! INTEN4 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN4_SHIFT)) & DMA_COMMON_INTENSET_INTEN4_MASK) + +#define DMA_COMMON_INTENSET_INTEN5_MASK (0x20U) +#define DMA_COMMON_INTENSET_INTEN5_SHIFT (5U) +/*! INTEN5 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN5_SHIFT)) & DMA_COMMON_INTENSET_INTEN5_MASK) + +#define DMA_COMMON_INTENSET_INTEN6_MASK (0x40U) +#define DMA_COMMON_INTENSET_INTEN6_SHIFT (6U) +/*! INTEN6 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN6_SHIFT)) & DMA_COMMON_INTENSET_INTEN6_MASK) + +#define DMA_COMMON_INTENSET_INTEN7_MASK (0x80U) +#define DMA_COMMON_INTENSET_INTEN7_SHIFT (7U) +/*! INTEN7 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN7_SHIFT)) & DMA_COMMON_INTENSET_INTEN7_MASK) + +#define DMA_COMMON_INTENSET_INTEN8_MASK (0x100U) +#define DMA_COMMON_INTENSET_INTEN8_SHIFT (8U) +/*! INTEN8 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN8_SHIFT)) & DMA_COMMON_INTENSET_INTEN8_MASK) + +#define DMA_COMMON_INTENSET_INTEN9_MASK (0x200U) +#define DMA_COMMON_INTENSET_INTEN9_SHIFT (9U) +/*! INTEN9 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN9_SHIFT)) & DMA_COMMON_INTENSET_INTEN9_MASK) + +#define DMA_COMMON_INTENSET_INTEN10_MASK (0x400U) +#define DMA_COMMON_INTENSET_INTEN10_SHIFT (10U) +/*! INTEN10 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN10_SHIFT)) & DMA_COMMON_INTENSET_INTEN10_MASK) + +#define DMA_COMMON_INTENSET_INTEN11_MASK (0x800U) +#define DMA_COMMON_INTENSET_INTEN11_SHIFT (11U) +/*! INTEN11 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN11_SHIFT)) & DMA_COMMON_INTENSET_INTEN11_MASK) + +#define DMA_COMMON_INTENSET_INTEN12_MASK (0x1000U) +#define DMA_COMMON_INTENSET_INTEN12_SHIFT (12U) +/*! INTEN12 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN12_SHIFT)) & DMA_COMMON_INTENSET_INTEN12_MASK) + +#define DMA_COMMON_INTENSET_INTEN13_MASK (0x2000U) +#define DMA_COMMON_INTENSET_INTEN13_SHIFT (13U) +/*! INTEN13 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN13_SHIFT)) & DMA_COMMON_INTENSET_INTEN13_MASK) + +#define DMA_COMMON_INTENSET_INTEN14_MASK (0x4000U) +#define DMA_COMMON_INTENSET_INTEN14_SHIFT (14U) +/*! INTEN14 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN14_SHIFT)) & DMA_COMMON_INTENSET_INTEN14_MASK) + +#define DMA_COMMON_INTENSET_INTEN15_MASK (0x8000U) +#define DMA_COMMON_INTENSET_INTEN15_SHIFT (15U) +/*! INTEN15 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN15_SHIFT)) & DMA_COMMON_INTENSET_INTEN15_MASK) + +#define DMA_COMMON_INTENSET_INTEN16_MASK (0x10000U) +#define DMA_COMMON_INTENSET_INTEN16_SHIFT (16U) +/*! INTEN16 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN16_SHIFT)) & DMA_COMMON_INTENSET_INTEN16_MASK) + +#define DMA_COMMON_INTENSET_INTEN17_MASK (0x20000U) +#define DMA_COMMON_INTENSET_INTEN17_SHIFT (17U) +/*! INTEN17 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN17_SHIFT)) & DMA_COMMON_INTENSET_INTEN17_MASK) + +#define DMA_COMMON_INTENSET_INTEN18_MASK (0x40000U) +#define DMA_COMMON_INTENSET_INTEN18_SHIFT (18U) +/*! INTEN18 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN18_SHIFT)) & DMA_COMMON_INTENSET_INTEN18_MASK) + +#define DMA_COMMON_INTENSET_INTEN19_MASK (0x80000U) +#define DMA_COMMON_INTENSET_INTEN19_SHIFT (19U) +/*! INTEN19 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN19_SHIFT)) & DMA_COMMON_INTENSET_INTEN19_MASK) + +#define DMA_COMMON_INTENSET_INTEN20_MASK (0x100000U) +#define DMA_COMMON_INTENSET_INTEN20_SHIFT (20U) +/*! INTEN20 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN20_SHIFT)) & DMA_COMMON_INTENSET_INTEN20_MASK) + +#define DMA_COMMON_INTENSET_INTEN21_MASK (0x200000U) +#define DMA_COMMON_INTENSET_INTEN21_SHIFT (21U) +/*! INTEN21 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN21_SHIFT)) & DMA_COMMON_INTENSET_INTEN21_MASK) + +#define DMA_COMMON_INTENSET_INTEN22_MASK (0x400000U) +#define DMA_COMMON_INTENSET_INTEN22_SHIFT (22U) +/*! INTEN22 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN22_SHIFT)) & DMA_COMMON_INTENSET_INTEN22_MASK) + +#define DMA_COMMON_INTENSET_INTEN23_MASK (0x800000U) +#define DMA_COMMON_INTENSET_INTEN23_SHIFT (23U) +/*! INTEN23 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN23_SHIFT)) & DMA_COMMON_INTENSET_INTEN23_MASK) + +#define DMA_COMMON_INTENSET_INTEN24_MASK (0x1000000U) +#define DMA_COMMON_INTENSET_INTEN24_SHIFT (24U) +/*! INTEN24 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN24_SHIFT)) & DMA_COMMON_INTENSET_INTEN24_MASK) + +#define DMA_COMMON_INTENSET_INTEN25_MASK (0x2000000U) +#define DMA_COMMON_INTENSET_INTEN25_SHIFT (25U) +/*! INTEN25 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN25_SHIFT)) & DMA_COMMON_INTENSET_INTEN25_MASK) + +#define DMA_COMMON_INTENSET_INTEN26_MASK (0x4000000U) +#define DMA_COMMON_INTENSET_INTEN26_SHIFT (26U) +/*! INTEN26 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN26_SHIFT)) & DMA_COMMON_INTENSET_INTEN26_MASK) + +#define DMA_COMMON_INTENSET_INTEN27_MASK (0x8000000U) +#define DMA_COMMON_INTENSET_INTEN27_SHIFT (27U) +/*! INTEN27 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN27_SHIFT)) & DMA_COMMON_INTENSET_INTEN27_MASK) + +#define DMA_COMMON_INTENSET_INTEN28_MASK (0x10000000U) +#define DMA_COMMON_INTENSET_INTEN28_SHIFT (28U) +/*! INTEN28 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN28_SHIFT)) & DMA_COMMON_INTENSET_INTEN28_MASK) + +#define DMA_COMMON_INTENSET_INTEN29_MASK (0x20000000U) +#define DMA_COMMON_INTENSET_INTEN29_SHIFT (29U) +/*! INTEN29 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN29_SHIFT)) & DMA_COMMON_INTENSET_INTEN29_MASK) + +#define DMA_COMMON_INTENSET_INTEN30_MASK (0x40000000U) +#define DMA_COMMON_INTENSET_INTEN30_SHIFT (30U) +/*! INTEN30 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN30_SHIFT)) & DMA_COMMON_INTENSET_INTEN30_MASK) + +#define DMA_COMMON_INTENSET_INTEN31_MASK (0x80000000U) +#define DMA_COMMON_INTENSET_INTEN31_SHIFT (31U) +/*! INTEN31 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN31_SHIFT)) & DMA_COMMON_INTENSET_INTEN31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENSET1 - Interrupt Enable read and Set for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) +#define DMA_COMMON_INTENSET1_INTEN32_SHIFT (0U) +/*! INTEN32 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK) + +#define DMA_COMMON_INTENSET1_INTEN33_MASK (0x2U) +#define DMA_COMMON_INTENSET1_INTEN33_SHIFT (1U) +/*! INTEN33 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN33_SHIFT)) & DMA_COMMON_INTENSET1_INTEN33_MASK) + +#define DMA_COMMON_INTENSET1_INTEN34_MASK (0x4U) +#define DMA_COMMON_INTENSET1_INTEN34_SHIFT (2U) +/*! INTEN34 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN34_SHIFT)) & DMA_COMMON_INTENSET1_INTEN34_MASK) + +#define DMA_COMMON_INTENSET1_INTEN35_MASK (0x8U) +#define DMA_COMMON_INTENSET1_INTEN35_SHIFT (3U) +/*! INTEN35 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN35_SHIFT)) & DMA_COMMON_INTENSET1_INTEN35_MASK) + +#define DMA_COMMON_INTENSET1_INTEN36_MASK (0x10U) +#define DMA_COMMON_INTENSET1_INTEN36_SHIFT (4U) +/*! INTEN36 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN36_SHIFT)) & DMA_COMMON_INTENSET1_INTEN36_MASK) + +#define DMA_COMMON_INTENSET1_INTEN37_MASK (0x20U) +#define DMA_COMMON_INTENSET1_INTEN37_SHIFT (5U) +/*! INTEN37 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN37_SHIFT)) & DMA_COMMON_INTENSET1_INTEN37_MASK) + +#define DMA_COMMON_INTENSET1_INTEN38_MASK (0x40U) +#define DMA_COMMON_INTENSET1_INTEN38_SHIFT (6U) +/*! INTEN38 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN38_SHIFT)) & DMA_COMMON_INTENSET1_INTEN38_MASK) + +#define DMA_COMMON_INTENSET1_INTEN39_MASK (0x80U) +#define DMA_COMMON_INTENSET1_INTEN39_SHIFT (7U) +/*! INTEN39 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN39_SHIFT)) & DMA_COMMON_INTENSET1_INTEN39_MASK) + +#define DMA_COMMON_INTENSET1_INTEN40_MASK (0x100U) +#define DMA_COMMON_INTENSET1_INTEN40_SHIFT (8U) +/*! INTEN40 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN40_SHIFT)) & DMA_COMMON_INTENSET1_INTEN40_MASK) + +#define DMA_COMMON_INTENSET1_INTEN41_MASK (0x200U) +#define DMA_COMMON_INTENSET1_INTEN41_SHIFT (9U) +/*! INTEN41 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN41_SHIFT)) & DMA_COMMON_INTENSET1_INTEN41_MASK) + +#define DMA_COMMON_INTENSET1_INTEN42_MASK (0x400U) +#define DMA_COMMON_INTENSET1_INTEN42_SHIFT (10U) +/*! INTEN42 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN42_SHIFT)) & DMA_COMMON_INTENSET1_INTEN42_MASK) + +#define DMA_COMMON_INTENSET1_INTEN43_MASK (0x800U) +#define DMA_COMMON_INTENSET1_INTEN43_SHIFT (11U) +/*! INTEN43 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN43_SHIFT)) & DMA_COMMON_INTENSET1_INTEN43_MASK) + +#define DMA_COMMON_INTENSET1_INTEN44_MASK (0x1000U) +#define DMA_COMMON_INTENSET1_INTEN44_SHIFT (12U) +/*! INTEN44 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN44_SHIFT)) & DMA_COMMON_INTENSET1_INTEN44_MASK) + +#define DMA_COMMON_INTENSET1_INTEN45_MASK (0x2000U) +#define DMA_COMMON_INTENSET1_INTEN45_SHIFT (13U) +/*! INTEN45 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN45_SHIFT)) & DMA_COMMON_INTENSET1_INTEN45_MASK) + +#define DMA_COMMON_INTENSET1_INTEN46_MASK (0x4000U) +#define DMA_COMMON_INTENSET1_INTEN46_SHIFT (14U) +/*! INTEN46 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN46_SHIFT)) & DMA_COMMON_INTENSET1_INTEN46_MASK) + +#define DMA_COMMON_INTENSET1_INTEN47_MASK (0x8000U) +#define DMA_COMMON_INTENSET1_INTEN47_SHIFT (15U) +/*! INTEN47 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN47_SHIFT)) & DMA_COMMON_INTENSET1_INTEN47_MASK) + +#define DMA_COMMON_INTENSET1_INTEN48_MASK (0x10000U) +#define DMA_COMMON_INTENSET1_INTEN48_SHIFT (16U) +/*! INTEN48 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN48_SHIFT)) & DMA_COMMON_INTENSET1_INTEN48_MASK) + +#define DMA_COMMON_INTENSET1_INTEN49_MASK (0x20000U) +#define DMA_COMMON_INTENSET1_INTEN49_SHIFT (17U) +/*! INTEN49 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN49_SHIFT)) & DMA_COMMON_INTENSET1_INTEN49_MASK) + +#define DMA_COMMON_INTENSET1_INTEN50_MASK (0x40000U) +#define DMA_COMMON_INTENSET1_INTEN50_SHIFT (18U) +/*! INTEN50 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN50_SHIFT)) & DMA_COMMON_INTENSET1_INTEN50_MASK) + +#define DMA_COMMON_INTENSET1_INTEN51_MASK (0x80000U) +#define DMA_COMMON_INTENSET1_INTEN51_SHIFT (19U) +/*! INTEN51 - Interrupt Enable read and set for DMA channel. + * 0b0..The Interrupt for DMA channel is disabled. + * 0b1..The Interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET1_INTEN51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN51_SHIFT)) & DMA_COMMON_INTENSET1_INTEN51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET1 */ +#define DMA_COMMON_INTENSET1_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTENCLR_CLR0_MASK (0x1U) +#define DMA_COMMON_INTENCLR_CLR0_SHIFT (0U) +/*! CLR0 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR0_SHIFT)) & DMA_COMMON_INTENCLR_CLR0_MASK) + +#define DMA_COMMON_INTENCLR_CLR1_MASK (0x2U) +#define DMA_COMMON_INTENCLR_CLR1_SHIFT (1U) +/*! CLR1 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR1_SHIFT)) & DMA_COMMON_INTENCLR_CLR1_MASK) + +#define DMA_COMMON_INTENCLR_CLR2_MASK (0x4U) +#define DMA_COMMON_INTENCLR_CLR2_SHIFT (2U) +/*! CLR2 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR2_SHIFT)) & DMA_COMMON_INTENCLR_CLR2_MASK) + +#define DMA_COMMON_INTENCLR_CLR3_MASK (0x8U) +#define DMA_COMMON_INTENCLR_CLR3_SHIFT (3U) +/*! CLR3 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR3_SHIFT)) & DMA_COMMON_INTENCLR_CLR3_MASK) + +#define DMA_COMMON_INTENCLR_CLR4_MASK (0x10U) +#define DMA_COMMON_INTENCLR_CLR4_SHIFT (4U) +/*! CLR4 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR4_SHIFT)) & DMA_COMMON_INTENCLR_CLR4_MASK) + +#define DMA_COMMON_INTENCLR_CLR5_MASK (0x20U) +#define DMA_COMMON_INTENCLR_CLR5_SHIFT (5U) +/*! CLR5 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR5_SHIFT)) & DMA_COMMON_INTENCLR_CLR5_MASK) + +#define DMA_COMMON_INTENCLR_CLR6_MASK (0x40U) +#define DMA_COMMON_INTENCLR_CLR6_SHIFT (6U) +/*! CLR6 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR6_SHIFT)) & DMA_COMMON_INTENCLR_CLR6_MASK) + +#define DMA_COMMON_INTENCLR_CLR7_MASK (0x80U) +#define DMA_COMMON_INTENCLR_CLR7_SHIFT (7U) +/*! CLR7 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR7_SHIFT)) & DMA_COMMON_INTENCLR_CLR7_MASK) + +#define DMA_COMMON_INTENCLR_CLR8_MASK (0x100U) +#define DMA_COMMON_INTENCLR_CLR8_SHIFT (8U) +/*! CLR8 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR8_SHIFT)) & DMA_COMMON_INTENCLR_CLR8_MASK) + +#define DMA_COMMON_INTENCLR_CLR9_MASK (0x200U) +#define DMA_COMMON_INTENCLR_CLR9_SHIFT (9U) +/*! CLR9 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR9_SHIFT)) & DMA_COMMON_INTENCLR_CLR9_MASK) + +#define DMA_COMMON_INTENCLR_CLR10_MASK (0x400U) +#define DMA_COMMON_INTENCLR_CLR10_SHIFT (10U) +/*! CLR10 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR10_SHIFT)) & DMA_COMMON_INTENCLR_CLR10_MASK) + +#define DMA_COMMON_INTENCLR_CLR11_MASK (0x800U) +#define DMA_COMMON_INTENCLR_CLR11_SHIFT (11U) +/*! CLR11 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR11_SHIFT)) & DMA_COMMON_INTENCLR_CLR11_MASK) + +#define DMA_COMMON_INTENCLR_CLR12_MASK (0x1000U) +#define DMA_COMMON_INTENCLR_CLR12_SHIFT (12U) +/*! CLR12 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR12_SHIFT)) & DMA_COMMON_INTENCLR_CLR12_MASK) + +#define DMA_COMMON_INTENCLR_CLR13_MASK (0x2000U) +#define DMA_COMMON_INTENCLR_CLR13_SHIFT (13U) +/*! CLR13 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR13_SHIFT)) & DMA_COMMON_INTENCLR_CLR13_MASK) + +#define DMA_COMMON_INTENCLR_CLR14_MASK (0x4000U) +#define DMA_COMMON_INTENCLR_CLR14_SHIFT (14U) +/*! CLR14 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR14_SHIFT)) & DMA_COMMON_INTENCLR_CLR14_MASK) + +#define DMA_COMMON_INTENCLR_CLR15_MASK (0x8000U) +#define DMA_COMMON_INTENCLR_CLR15_SHIFT (15U) +/*! CLR15 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR15_SHIFT)) & DMA_COMMON_INTENCLR_CLR15_MASK) + +#define DMA_COMMON_INTENCLR_CLR16_MASK (0x10000U) +#define DMA_COMMON_INTENCLR_CLR16_SHIFT (16U) +/*! CLR16 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR16_SHIFT)) & DMA_COMMON_INTENCLR_CLR16_MASK) + +#define DMA_COMMON_INTENCLR_CLR17_MASK (0x20000U) +#define DMA_COMMON_INTENCLR_CLR17_SHIFT (17U) +/*! CLR17 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR17_SHIFT)) & DMA_COMMON_INTENCLR_CLR17_MASK) + +#define DMA_COMMON_INTENCLR_CLR18_MASK (0x40000U) +#define DMA_COMMON_INTENCLR_CLR18_SHIFT (18U) +/*! CLR18 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR18_SHIFT)) & DMA_COMMON_INTENCLR_CLR18_MASK) + +#define DMA_COMMON_INTENCLR_CLR19_MASK (0x80000U) +#define DMA_COMMON_INTENCLR_CLR19_SHIFT (19U) +/*! CLR19 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR19_SHIFT)) & DMA_COMMON_INTENCLR_CLR19_MASK) + +#define DMA_COMMON_INTENCLR_CLR20_MASK (0x100000U) +#define DMA_COMMON_INTENCLR_CLR20_SHIFT (20U) +/*! CLR20 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR20_SHIFT)) & DMA_COMMON_INTENCLR_CLR20_MASK) + +#define DMA_COMMON_INTENCLR_CLR21_MASK (0x200000U) +#define DMA_COMMON_INTENCLR_CLR21_SHIFT (21U) +/*! CLR21 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR21_SHIFT)) & DMA_COMMON_INTENCLR_CLR21_MASK) + +#define DMA_COMMON_INTENCLR_CLR22_MASK (0x400000U) +#define DMA_COMMON_INTENCLR_CLR22_SHIFT (22U) +/*! CLR22 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR22_SHIFT)) & DMA_COMMON_INTENCLR_CLR22_MASK) + +#define DMA_COMMON_INTENCLR_CLR23_MASK (0x800000U) +#define DMA_COMMON_INTENCLR_CLR23_SHIFT (23U) +/*! CLR23 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR23_SHIFT)) & DMA_COMMON_INTENCLR_CLR23_MASK) + +#define DMA_COMMON_INTENCLR_CLR24_MASK (0x1000000U) +#define DMA_COMMON_INTENCLR_CLR24_SHIFT (24U) +/*! CLR24 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR24_SHIFT)) & DMA_COMMON_INTENCLR_CLR24_MASK) + +#define DMA_COMMON_INTENCLR_CLR25_MASK (0x2000000U) +#define DMA_COMMON_INTENCLR_CLR25_SHIFT (25U) +/*! CLR25 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR25_SHIFT)) & DMA_COMMON_INTENCLR_CLR25_MASK) + +#define DMA_COMMON_INTENCLR_CLR26_MASK (0x4000000U) +#define DMA_COMMON_INTENCLR_CLR26_SHIFT (26U) +/*! CLR26 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR26_SHIFT)) & DMA_COMMON_INTENCLR_CLR26_MASK) + +#define DMA_COMMON_INTENCLR_CLR27_MASK (0x8000000U) +#define DMA_COMMON_INTENCLR_CLR27_SHIFT (27U) +/*! CLR27 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR27_SHIFT)) & DMA_COMMON_INTENCLR_CLR27_MASK) + +#define DMA_COMMON_INTENCLR_CLR28_MASK (0x10000000U) +#define DMA_COMMON_INTENCLR_CLR28_SHIFT (28U) +/*! CLR28 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR28_SHIFT)) & DMA_COMMON_INTENCLR_CLR28_MASK) + +#define DMA_COMMON_INTENCLR_CLR29_MASK (0x20000000U) +#define DMA_COMMON_INTENCLR_CLR29_SHIFT (29U) +/*! CLR29 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR29_SHIFT)) & DMA_COMMON_INTENCLR_CLR29_MASK) + +#define DMA_COMMON_INTENCLR_CLR30_MASK (0x40000000U) +#define DMA_COMMON_INTENCLR_CLR30_SHIFT (30U) +/*! CLR30 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR30_SHIFT)) & DMA_COMMON_INTENCLR_CLR30_MASK) + +#define DMA_COMMON_INTENCLR_CLR31_MASK (0x80000000U) +#define DMA_COMMON_INTENCLR_CLR31_SHIFT (31U) +/*! CLR31 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0. + */ +#define DMA_COMMON_INTENCLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR31_SHIFT)) & DMA_COMMON_INTENCLR_CLR31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTENCLR1 - Interrupt Enable Clear for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTENCLR1_CLR32_MASK (0x1U) +#define DMA_COMMON_INTENCLR1_CLR32_SHIFT (0U) +/*! CLR32 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR32_SHIFT)) & DMA_COMMON_INTENCLR1_CLR32_MASK) + +#define DMA_COMMON_INTENCLR1_CLR33_MASK (0x2U) +#define DMA_COMMON_INTENCLR1_CLR33_SHIFT (1U) +/*! CLR33 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR33_SHIFT)) & DMA_COMMON_INTENCLR1_CLR33_MASK) + +#define DMA_COMMON_INTENCLR1_CLR34_MASK (0x4U) +#define DMA_COMMON_INTENCLR1_CLR34_SHIFT (2U) +/*! CLR34 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR34_SHIFT)) & DMA_COMMON_INTENCLR1_CLR34_MASK) + +#define DMA_COMMON_INTENCLR1_CLR35_MASK (0x8U) +#define DMA_COMMON_INTENCLR1_CLR35_SHIFT (3U) +/*! CLR35 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR35_SHIFT)) & DMA_COMMON_INTENCLR1_CLR35_MASK) + +#define DMA_COMMON_INTENCLR1_CLR36_MASK (0x10U) +#define DMA_COMMON_INTENCLR1_CLR36_SHIFT (4U) +/*! CLR36 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR36_SHIFT)) & DMA_COMMON_INTENCLR1_CLR36_MASK) + +#define DMA_COMMON_INTENCLR1_CLR37_MASK (0x20U) +#define DMA_COMMON_INTENCLR1_CLR37_SHIFT (5U) +/*! CLR37 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR37_SHIFT)) & DMA_COMMON_INTENCLR1_CLR37_MASK) + +#define DMA_COMMON_INTENCLR1_CLR38_MASK (0x40U) +#define DMA_COMMON_INTENCLR1_CLR38_SHIFT (6U) +/*! CLR38 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR38_SHIFT)) & DMA_COMMON_INTENCLR1_CLR38_MASK) + +#define DMA_COMMON_INTENCLR1_CLR39_MASK (0x80U) +#define DMA_COMMON_INTENCLR1_CLR39_SHIFT (7U) +/*! CLR39 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR39_SHIFT)) & DMA_COMMON_INTENCLR1_CLR39_MASK) + +#define DMA_COMMON_INTENCLR1_CLR40_MASK (0x100U) +#define DMA_COMMON_INTENCLR1_CLR40_SHIFT (8U) +/*! CLR40 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR40_SHIFT)) & DMA_COMMON_INTENCLR1_CLR40_MASK) + +#define DMA_COMMON_INTENCLR1_CLR41_MASK (0x200U) +#define DMA_COMMON_INTENCLR1_CLR41_SHIFT (9U) +/*! CLR41 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR41_SHIFT)) & DMA_COMMON_INTENCLR1_CLR41_MASK) + +#define DMA_COMMON_INTENCLR1_CLR42_MASK (0x400U) +#define DMA_COMMON_INTENCLR1_CLR42_SHIFT (10U) +/*! CLR42 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR42_SHIFT)) & DMA_COMMON_INTENCLR1_CLR42_MASK) + +#define DMA_COMMON_INTENCLR1_CLR43_MASK (0x800U) +#define DMA_COMMON_INTENCLR1_CLR43_SHIFT (11U) +/*! CLR43 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR43_SHIFT)) & DMA_COMMON_INTENCLR1_CLR43_MASK) + +#define DMA_COMMON_INTENCLR1_CLR44_MASK (0x1000U) +#define DMA_COMMON_INTENCLR1_CLR44_SHIFT (12U) +/*! CLR44 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR44_SHIFT)) & DMA_COMMON_INTENCLR1_CLR44_MASK) + +#define DMA_COMMON_INTENCLR1_CLR45_MASK (0x2000U) +#define DMA_COMMON_INTENCLR1_CLR45_SHIFT (13U) +/*! CLR45 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR45_SHIFT)) & DMA_COMMON_INTENCLR1_CLR45_MASK) + +#define DMA_COMMON_INTENCLR1_CLR46_MASK (0x4000U) +#define DMA_COMMON_INTENCLR1_CLR46_SHIFT (14U) +/*! CLR46 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR46_SHIFT)) & DMA_COMMON_INTENCLR1_CLR46_MASK) + +#define DMA_COMMON_INTENCLR1_CLR47_MASK (0x8000U) +#define DMA_COMMON_INTENCLR1_CLR47_SHIFT (15U) +/*! CLR47 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR47_SHIFT)) & DMA_COMMON_INTENCLR1_CLR47_MASK) + +#define DMA_COMMON_INTENCLR1_CLR48_MASK (0x10000U) +#define DMA_COMMON_INTENCLR1_CLR48_SHIFT (16U) +/*! CLR48 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR48_SHIFT)) & DMA_COMMON_INTENCLR1_CLR48_MASK) + +#define DMA_COMMON_INTENCLR1_CLR49_MASK (0x20000U) +#define DMA_COMMON_INTENCLR1_CLR49_SHIFT (17U) +/*! CLR49 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR49_SHIFT)) & DMA_COMMON_INTENCLR1_CLR49_MASK) + +#define DMA_COMMON_INTENCLR1_CLR50_MASK (0x40000U) +#define DMA_COMMON_INTENCLR1_CLR50_SHIFT (18U) +/*! CLR50 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR50_SHIFT)) & DMA_COMMON_INTENCLR1_CLR50_MASK) + +#define DMA_COMMON_INTENCLR1_CLR51_MASK (0x80000U) +#define DMA_COMMON_INTENCLR1_CLR51_SHIFT (19U) +/*! CLR51 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1. + */ +#define DMA_COMMON_INTENCLR1_CLR51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR51_SHIFT)) & DMA_COMMON_INTENCLR1_CLR51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR1 */ +#define DMA_COMMON_INTENCLR1_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTA_INTA0_MASK (0x1U) +#define DMA_COMMON_INTA_INTA0_SHIFT (0U) +/*! INTA0 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA0_SHIFT)) & DMA_COMMON_INTA_INTA0_MASK) + +#define DMA_COMMON_INTA_INTA1_MASK (0x2U) +#define DMA_COMMON_INTA_INTA1_SHIFT (1U) +/*! INTA1 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA1_SHIFT)) & DMA_COMMON_INTA_INTA1_MASK) + +#define DMA_COMMON_INTA_INTA2_MASK (0x4U) +#define DMA_COMMON_INTA_INTA2_SHIFT (2U) +/*! INTA2 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA2_SHIFT)) & DMA_COMMON_INTA_INTA2_MASK) + +#define DMA_COMMON_INTA_INTA3_MASK (0x8U) +#define DMA_COMMON_INTA_INTA3_SHIFT (3U) +/*! INTA3 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA3_SHIFT)) & DMA_COMMON_INTA_INTA3_MASK) + +#define DMA_COMMON_INTA_INTA4_MASK (0x10U) +#define DMA_COMMON_INTA_INTA4_SHIFT (4U) +/*! INTA4 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA4_SHIFT)) & DMA_COMMON_INTA_INTA4_MASK) + +#define DMA_COMMON_INTA_INTA5_MASK (0x20U) +#define DMA_COMMON_INTA_INTA5_SHIFT (5U) +/*! INTA5 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA5_SHIFT)) & DMA_COMMON_INTA_INTA5_MASK) + +#define DMA_COMMON_INTA_INTA6_MASK (0x40U) +#define DMA_COMMON_INTA_INTA6_SHIFT (6U) +/*! INTA6 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA6_SHIFT)) & DMA_COMMON_INTA_INTA6_MASK) + +#define DMA_COMMON_INTA_INTA7_MASK (0x80U) +#define DMA_COMMON_INTA_INTA7_SHIFT (7U) +/*! INTA7 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA7_SHIFT)) & DMA_COMMON_INTA_INTA7_MASK) + +#define DMA_COMMON_INTA_INTA8_MASK (0x100U) +#define DMA_COMMON_INTA_INTA8_SHIFT (8U) +/*! INTA8 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA8_SHIFT)) & DMA_COMMON_INTA_INTA8_MASK) + +#define DMA_COMMON_INTA_INTA9_MASK (0x200U) +#define DMA_COMMON_INTA_INTA9_SHIFT (9U) +/*! INTA9 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA9_SHIFT)) & DMA_COMMON_INTA_INTA9_MASK) + +#define DMA_COMMON_INTA_INTA10_MASK (0x400U) +#define DMA_COMMON_INTA_INTA10_SHIFT (10U) +/*! INTA10 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA10_SHIFT)) & DMA_COMMON_INTA_INTA10_MASK) + +#define DMA_COMMON_INTA_INTA11_MASK (0x800U) +#define DMA_COMMON_INTA_INTA11_SHIFT (11U) +/*! INTA11 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA11_SHIFT)) & DMA_COMMON_INTA_INTA11_MASK) + +#define DMA_COMMON_INTA_INTA12_MASK (0x1000U) +#define DMA_COMMON_INTA_INTA12_SHIFT (12U) +/*! INTA12 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA12_SHIFT)) & DMA_COMMON_INTA_INTA12_MASK) + +#define DMA_COMMON_INTA_INTA13_MASK (0x2000U) +#define DMA_COMMON_INTA_INTA13_SHIFT (13U) +/*! INTA13 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA13_SHIFT)) & DMA_COMMON_INTA_INTA13_MASK) + +#define DMA_COMMON_INTA_INTA14_MASK (0x4000U) +#define DMA_COMMON_INTA_INTA14_SHIFT (14U) +/*! INTA14 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA14_SHIFT)) & DMA_COMMON_INTA_INTA14_MASK) + +#define DMA_COMMON_INTA_INTA15_MASK (0x8000U) +#define DMA_COMMON_INTA_INTA15_SHIFT (15U) +/*! INTA15 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA15_SHIFT)) & DMA_COMMON_INTA_INTA15_MASK) + +#define DMA_COMMON_INTA_INTA16_MASK (0x10000U) +#define DMA_COMMON_INTA_INTA16_SHIFT (16U) +/*! INTA16 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA16_SHIFT)) & DMA_COMMON_INTA_INTA16_MASK) + +#define DMA_COMMON_INTA_INTA17_MASK (0x20000U) +#define DMA_COMMON_INTA_INTA17_SHIFT (17U) +/*! INTA17 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA17_SHIFT)) & DMA_COMMON_INTA_INTA17_MASK) + +#define DMA_COMMON_INTA_INTA18_MASK (0x40000U) +#define DMA_COMMON_INTA_INTA18_SHIFT (18U) +/*! INTA18 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA18_SHIFT)) & DMA_COMMON_INTA_INTA18_MASK) + +#define DMA_COMMON_INTA_INTA19_MASK (0x80000U) +#define DMA_COMMON_INTA_INTA19_SHIFT (19U) +/*! INTA19 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA19_SHIFT)) & DMA_COMMON_INTA_INTA19_MASK) + +#define DMA_COMMON_INTA_INTA20_MASK (0x100000U) +#define DMA_COMMON_INTA_INTA20_SHIFT (20U) +/*! INTA20 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA20_SHIFT)) & DMA_COMMON_INTA_INTA20_MASK) + +#define DMA_COMMON_INTA_INTA21_MASK (0x200000U) +#define DMA_COMMON_INTA_INTA21_SHIFT (21U) +/*! INTA21 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA21_SHIFT)) & DMA_COMMON_INTA_INTA21_MASK) + +#define DMA_COMMON_INTA_INTA22_MASK (0x400000U) +#define DMA_COMMON_INTA_INTA22_SHIFT (22U) +/*! INTA22 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA22_SHIFT)) & DMA_COMMON_INTA_INTA22_MASK) + +#define DMA_COMMON_INTA_INTA23_MASK (0x800000U) +#define DMA_COMMON_INTA_INTA23_SHIFT (23U) +/*! INTA23 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA23_SHIFT)) & DMA_COMMON_INTA_INTA23_MASK) + +#define DMA_COMMON_INTA_INTA24_MASK (0x1000000U) +#define DMA_COMMON_INTA_INTA24_SHIFT (24U) +/*! INTA24 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA24_SHIFT)) & DMA_COMMON_INTA_INTA24_MASK) + +#define DMA_COMMON_INTA_INTA25_MASK (0x2000000U) +#define DMA_COMMON_INTA_INTA25_SHIFT (25U) +/*! INTA25 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA25_SHIFT)) & DMA_COMMON_INTA_INTA25_MASK) + +#define DMA_COMMON_INTA_INTA26_MASK (0x4000000U) +#define DMA_COMMON_INTA_INTA26_SHIFT (26U) +/*! INTA26 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA26_SHIFT)) & DMA_COMMON_INTA_INTA26_MASK) + +#define DMA_COMMON_INTA_INTA27_MASK (0x8000000U) +#define DMA_COMMON_INTA_INTA27_SHIFT (27U) +/*! INTA27 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA27_SHIFT)) & DMA_COMMON_INTA_INTA27_MASK) + +#define DMA_COMMON_INTA_INTA28_MASK (0x10000000U) +#define DMA_COMMON_INTA_INTA28_SHIFT (28U) +/*! INTA28 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA28_SHIFT)) & DMA_COMMON_INTA_INTA28_MASK) + +#define DMA_COMMON_INTA_INTA29_MASK (0x20000000U) +#define DMA_COMMON_INTA_INTA29_SHIFT (29U) +/*! INTA29 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA29_SHIFT)) & DMA_COMMON_INTA_INTA29_MASK) + +#define DMA_COMMON_INTA_INTA30_MASK (0x40000000U) +#define DMA_COMMON_INTA_INTA30_SHIFT (30U) +/*! INTA30 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA30_SHIFT)) & DMA_COMMON_INTA_INTA30_MASK) + +#define DMA_COMMON_INTA_INTA31_MASK (0x80000000U) +#define DMA_COMMON_INTA_INTA31_SHIFT (31U) +/*! INTA31 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_INTA31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA31_SHIFT)) & DMA_COMMON_INTA_INTA31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTA1 - Interrupt A status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTA1_INTA32_MASK (0x1U) +#define DMA_COMMON_INTA1_INTA32_SHIFT (0U) +/*! INTA32 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA32_SHIFT)) & DMA_COMMON_INTA1_INTA32_MASK) + +#define DMA_COMMON_INTA1_INTA33_MASK (0x2U) +#define DMA_COMMON_INTA1_INTA33_SHIFT (1U) +/*! INTA33 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA33_SHIFT)) & DMA_COMMON_INTA1_INTA33_MASK) + +#define DMA_COMMON_INTA1_INTA34_MASK (0x4U) +#define DMA_COMMON_INTA1_INTA34_SHIFT (2U) +/*! INTA34 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA34_SHIFT)) & DMA_COMMON_INTA1_INTA34_MASK) + +#define DMA_COMMON_INTA1_INTA35_MASK (0x8U) +#define DMA_COMMON_INTA1_INTA35_SHIFT (3U) +/*! INTA35 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA35_SHIFT)) & DMA_COMMON_INTA1_INTA35_MASK) + +#define DMA_COMMON_INTA1_INTA36_MASK (0x10U) +#define DMA_COMMON_INTA1_INTA36_SHIFT (4U) +/*! INTA36 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA36_SHIFT)) & DMA_COMMON_INTA1_INTA36_MASK) + +#define DMA_COMMON_INTA1_INTA37_MASK (0x20U) +#define DMA_COMMON_INTA1_INTA37_SHIFT (5U) +/*! INTA37 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA37_SHIFT)) & DMA_COMMON_INTA1_INTA37_MASK) + +#define DMA_COMMON_INTA1_INTA38_MASK (0x40U) +#define DMA_COMMON_INTA1_INTA38_SHIFT (6U) +/*! INTA38 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA38_SHIFT)) & DMA_COMMON_INTA1_INTA38_MASK) + +#define DMA_COMMON_INTA1_INTA39_MASK (0x80U) +#define DMA_COMMON_INTA1_INTA39_SHIFT (7U) +/*! INTA39 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA39_SHIFT)) & DMA_COMMON_INTA1_INTA39_MASK) + +#define DMA_COMMON_INTA1_INTA40_MASK (0x100U) +#define DMA_COMMON_INTA1_INTA40_SHIFT (8U) +/*! INTA40 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA40_SHIFT)) & DMA_COMMON_INTA1_INTA40_MASK) + +#define DMA_COMMON_INTA1_INTA41_MASK (0x200U) +#define DMA_COMMON_INTA1_INTA41_SHIFT (9U) +/*! INTA41 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA41_SHIFT)) & DMA_COMMON_INTA1_INTA41_MASK) + +#define DMA_COMMON_INTA1_INTA42_MASK (0x400U) +#define DMA_COMMON_INTA1_INTA42_SHIFT (10U) +/*! INTA42 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA42_SHIFT)) & DMA_COMMON_INTA1_INTA42_MASK) + +#define DMA_COMMON_INTA1_INTA43_MASK (0x800U) +#define DMA_COMMON_INTA1_INTA43_SHIFT (11U) +/*! INTA43 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA43_SHIFT)) & DMA_COMMON_INTA1_INTA43_MASK) + +#define DMA_COMMON_INTA1_INTA44_MASK (0x1000U) +#define DMA_COMMON_INTA1_INTA44_SHIFT (12U) +/*! INTA44 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA44_SHIFT)) & DMA_COMMON_INTA1_INTA44_MASK) + +#define DMA_COMMON_INTA1_INTA45_MASK (0x2000U) +#define DMA_COMMON_INTA1_INTA45_SHIFT (13U) +/*! INTA45 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA45_SHIFT)) & DMA_COMMON_INTA1_INTA45_MASK) + +#define DMA_COMMON_INTA1_INTA46_MASK (0x4000U) +#define DMA_COMMON_INTA1_INTA46_SHIFT (14U) +/*! INTA46 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA46_SHIFT)) & DMA_COMMON_INTA1_INTA46_MASK) + +#define DMA_COMMON_INTA1_INTA47_MASK (0x8000U) +#define DMA_COMMON_INTA1_INTA47_SHIFT (15U) +/*! INTA47 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA47_SHIFT)) & DMA_COMMON_INTA1_INTA47_MASK) + +#define DMA_COMMON_INTA1_INTA48_MASK (0x10000U) +#define DMA_COMMON_INTA1_INTA48_SHIFT (16U) +/*! INTA48 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA48_SHIFT)) & DMA_COMMON_INTA1_INTA48_MASK) + +#define DMA_COMMON_INTA1_INTA49_MASK (0x20000U) +#define DMA_COMMON_INTA1_INTA49_SHIFT (17U) +/*! INTA49 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA49_SHIFT)) & DMA_COMMON_INTA1_INTA49_MASK) + +#define DMA_COMMON_INTA1_INTA50_MASK (0x40000U) +#define DMA_COMMON_INTA1_INTA50_SHIFT (18U) +/*! INTA50 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA50_SHIFT)) & DMA_COMMON_INTA1_INTA50_MASK) + +#define DMA_COMMON_INTA1_INTA51_MASK (0x80000U) +#define DMA_COMMON_INTA1_INTA51_SHIFT (19U) +/*! INTA51 - Interrupt A status for DMA channel. + * 0b0..The DMA channel interrupt A is not active. + * 0b1..The DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA1_INTA51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA51_SHIFT)) & DMA_COMMON_INTA1_INTA51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA1 */ +#define DMA_COMMON_INTA1_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTB_INTB0_MASK (0x1U) +#define DMA_COMMON_INTB_INTB0_SHIFT (0U) +/*! INTB0 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB0_SHIFT)) & DMA_COMMON_INTB_INTB0_MASK) + +#define DMA_COMMON_INTB_INTB1_MASK (0x2U) +#define DMA_COMMON_INTB_INTB1_SHIFT (1U) +/*! INTB1 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB1_SHIFT)) & DMA_COMMON_INTB_INTB1_MASK) + +#define DMA_COMMON_INTB_INTB2_MASK (0x4U) +#define DMA_COMMON_INTB_INTB2_SHIFT (2U) +/*! INTB2 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB2_SHIFT)) & DMA_COMMON_INTB_INTB2_MASK) + +#define DMA_COMMON_INTB_INTB3_MASK (0x8U) +#define DMA_COMMON_INTB_INTB3_SHIFT (3U) +/*! INTB3 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB3_SHIFT)) & DMA_COMMON_INTB_INTB3_MASK) + +#define DMA_COMMON_INTB_INTB4_MASK (0x10U) +#define DMA_COMMON_INTB_INTB4_SHIFT (4U) +/*! INTB4 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB4_SHIFT)) & DMA_COMMON_INTB_INTB4_MASK) + +#define DMA_COMMON_INTB_INTB5_MASK (0x20U) +#define DMA_COMMON_INTB_INTB5_SHIFT (5U) +/*! INTB5 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB5_SHIFT)) & DMA_COMMON_INTB_INTB5_MASK) + +#define DMA_COMMON_INTB_INTB6_MASK (0x40U) +#define DMA_COMMON_INTB_INTB6_SHIFT (6U) +/*! INTB6 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB6_SHIFT)) & DMA_COMMON_INTB_INTB6_MASK) + +#define DMA_COMMON_INTB_INTB7_MASK (0x80U) +#define DMA_COMMON_INTB_INTB7_SHIFT (7U) +/*! INTB7 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB7_SHIFT)) & DMA_COMMON_INTB_INTB7_MASK) + +#define DMA_COMMON_INTB_INTB8_MASK (0x100U) +#define DMA_COMMON_INTB_INTB8_SHIFT (8U) +/*! INTB8 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB8_SHIFT)) & DMA_COMMON_INTB_INTB8_MASK) + +#define DMA_COMMON_INTB_INTB9_MASK (0x200U) +#define DMA_COMMON_INTB_INTB9_SHIFT (9U) +/*! INTB9 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB9_SHIFT)) & DMA_COMMON_INTB_INTB9_MASK) + +#define DMA_COMMON_INTB_INTB10_MASK (0x400U) +#define DMA_COMMON_INTB_INTB10_SHIFT (10U) +/*! INTB10 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB10_SHIFT)) & DMA_COMMON_INTB_INTB10_MASK) + +#define DMA_COMMON_INTB_INTB11_MASK (0x800U) +#define DMA_COMMON_INTB_INTB11_SHIFT (11U) +/*! INTB11 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB11_SHIFT)) & DMA_COMMON_INTB_INTB11_MASK) + +#define DMA_COMMON_INTB_INTB12_MASK (0x1000U) +#define DMA_COMMON_INTB_INTB12_SHIFT (12U) +/*! INTB12 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB12_SHIFT)) & DMA_COMMON_INTB_INTB12_MASK) + +#define DMA_COMMON_INTB_INTB13_MASK (0x2000U) +#define DMA_COMMON_INTB_INTB13_SHIFT (13U) +/*! INTB13 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB13_SHIFT)) & DMA_COMMON_INTB_INTB13_MASK) + +#define DMA_COMMON_INTB_INTB14_MASK (0x4000U) +#define DMA_COMMON_INTB_INTB14_SHIFT (14U) +/*! INTB14 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB14_SHIFT)) & DMA_COMMON_INTB_INTB14_MASK) + +#define DMA_COMMON_INTB_INTB15_MASK (0x8000U) +#define DMA_COMMON_INTB_INTB15_SHIFT (15U) +/*! INTB15 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB15_SHIFT)) & DMA_COMMON_INTB_INTB15_MASK) + +#define DMA_COMMON_INTB_INTB16_MASK (0x10000U) +#define DMA_COMMON_INTB_INTB16_SHIFT (16U) +/*! INTB16 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB16_SHIFT)) & DMA_COMMON_INTB_INTB16_MASK) + +#define DMA_COMMON_INTB_INTB17_MASK (0x20000U) +#define DMA_COMMON_INTB_INTB17_SHIFT (17U) +/*! INTB17 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB17_SHIFT)) & DMA_COMMON_INTB_INTB17_MASK) + +#define DMA_COMMON_INTB_INTB18_MASK (0x40000U) +#define DMA_COMMON_INTB_INTB18_SHIFT (18U) +/*! INTB18 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB18_SHIFT)) & DMA_COMMON_INTB_INTB18_MASK) + +#define DMA_COMMON_INTB_INTB19_MASK (0x80000U) +#define DMA_COMMON_INTB_INTB19_SHIFT (19U) +/*! INTB19 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB19_SHIFT)) & DMA_COMMON_INTB_INTB19_MASK) + +#define DMA_COMMON_INTB_INTB20_MASK (0x100000U) +#define DMA_COMMON_INTB_INTB20_SHIFT (20U) +/*! INTB20 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB20_SHIFT)) & DMA_COMMON_INTB_INTB20_MASK) + +#define DMA_COMMON_INTB_INTB21_MASK (0x200000U) +#define DMA_COMMON_INTB_INTB21_SHIFT (21U) +/*! INTB21 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB21_SHIFT)) & DMA_COMMON_INTB_INTB21_MASK) + +#define DMA_COMMON_INTB_INTB22_MASK (0x400000U) +#define DMA_COMMON_INTB_INTB22_SHIFT (22U) +/*! INTB22 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB22_SHIFT)) & DMA_COMMON_INTB_INTB22_MASK) + +#define DMA_COMMON_INTB_INTB23_MASK (0x800000U) +#define DMA_COMMON_INTB_INTB23_SHIFT (23U) +/*! INTB23 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB23_SHIFT)) & DMA_COMMON_INTB_INTB23_MASK) + +#define DMA_COMMON_INTB_INTB24_MASK (0x1000000U) +#define DMA_COMMON_INTB_INTB24_SHIFT (24U) +/*! INTB24 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB24_SHIFT)) & DMA_COMMON_INTB_INTB24_MASK) + +#define DMA_COMMON_INTB_INTB25_MASK (0x2000000U) +#define DMA_COMMON_INTB_INTB25_SHIFT (25U) +/*! INTB25 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB25_SHIFT)) & DMA_COMMON_INTB_INTB25_MASK) + +#define DMA_COMMON_INTB_INTB26_MASK (0x4000000U) +#define DMA_COMMON_INTB_INTB26_SHIFT (26U) +/*! INTB26 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB26_SHIFT)) & DMA_COMMON_INTB_INTB26_MASK) + +#define DMA_COMMON_INTB_INTB27_MASK (0x8000000U) +#define DMA_COMMON_INTB_INTB27_SHIFT (27U) +/*! INTB27 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB27_SHIFT)) & DMA_COMMON_INTB_INTB27_MASK) + +#define DMA_COMMON_INTB_INTB28_MASK (0x10000000U) +#define DMA_COMMON_INTB_INTB28_SHIFT (28U) +/*! INTB28 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB28_SHIFT)) & DMA_COMMON_INTB_INTB28_MASK) + +#define DMA_COMMON_INTB_INTB29_MASK (0x20000000U) +#define DMA_COMMON_INTB_INTB29_SHIFT (29U) +/*! INTB29 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB29_SHIFT)) & DMA_COMMON_INTB_INTB29_MASK) + +#define DMA_COMMON_INTB_INTB30_MASK (0x40000000U) +#define DMA_COMMON_INTB_INTB30_SHIFT (30U) +/*! INTB30 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB30_SHIFT)) & DMA_COMMON_INTB_INTB30_MASK) + +#define DMA_COMMON_INTB_INTB31_MASK (0x80000000U) +#define DMA_COMMON_INTB_INTB31_SHIFT (31U) +/*! INTB31 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_INTB31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB31_SHIFT)) & DMA_COMMON_INTB_INTB31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_INTB1 - Interrupt B status for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_INTB1_INTB0_MASK (0x1U) +#define DMA_COMMON_INTB1_INTB0_SHIFT (0U) +/*! INTB0 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB0_SHIFT)) & DMA_COMMON_INTB1_INTB0_MASK) + +#define DMA_COMMON_INTB1_INTB1_MASK (0x2U) +#define DMA_COMMON_INTB1_INTB1_SHIFT (1U) +/*! INTB1 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB1_SHIFT)) & DMA_COMMON_INTB1_INTB1_MASK) + +#define DMA_COMMON_INTB1_INTB2_MASK (0x4U) +#define DMA_COMMON_INTB1_INTB2_SHIFT (2U) +/*! INTB2 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB2_SHIFT)) & DMA_COMMON_INTB1_INTB2_MASK) + +#define DMA_COMMON_INTB1_INTB3_MASK (0x8U) +#define DMA_COMMON_INTB1_INTB3_SHIFT (3U) +/*! INTB3 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB3_SHIFT)) & DMA_COMMON_INTB1_INTB3_MASK) + +#define DMA_COMMON_INTB1_INTB4_MASK (0x10U) +#define DMA_COMMON_INTB1_INTB4_SHIFT (4U) +/*! INTB4 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB4_SHIFT)) & DMA_COMMON_INTB1_INTB4_MASK) + +#define DMA_COMMON_INTB1_INTB5_MASK (0x20U) +#define DMA_COMMON_INTB1_INTB5_SHIFT (5U) +/*! INTB5 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB5_SHIFT)) & DMA_COMMON_INTB1_INTB5_MASK) + +#define DMA_COMMON_INTB1_INTB6_MASK (0x40U) +#define DMA_COMMON_INTB1_INTB6_SHIFT (6U) +/*! INTB6 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB6_SHIFT)) & DMA_COMMON_INTB1_INTB6_MASK) + +#define DMA_COMMON_INTB1_INTB7_MASK (0x80U) +#define DMA_COMMON_INTB1_INTB7_SHIFT (7U) +/*! INTB7 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB7_SHIFT)) & DMA_COMMON_INTB1_INTB7_MASK) + +#define DMA_COMMON_INTB1_INTB8_MASK (0x100U) +#define DMA_COMMON_INTB1_INTB8_SHIFT (8U) +/*! INTB8 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB8_SHIFT)) & DMA_COMMON_INTB1_INTB8_MASK) + +#define DMA_COMMON_INTB1_INTB9_MASK (0x200U) +#define DMA_COMMON_INTB1_INTB9_SHIFT (9U) +/*! INTB9 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB9_SHIFT)) & DMA_COMMON_INTB1_INTB9_MASK) + +#define DMA_COMMON_INTB1_INTB10_MASK (0x400U) +#define DMA_COMMON_INTB1_INTB10_SHIFT (10U) +/*! INTB10 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB10_SHIFT)) & DMA_COMMON_INTB1_INTB10_MASK) + +#define DMA_COMMON_INTB1_INTB11_MASK (0x800U) +#define DMA_COMMON_INTB1_INTB11_SHIFT (11U) +/*! INTB11 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB11_SHIFT)) & DMA_COMMON_INTB1_INTB11_MASK) + +#define DMA_COMMON_INTB1_INTB12_MASK (0x1000U) +#define DMA_COMMON_INTB1_INTB12_SHIFT (12U) +/*! INTB12 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB12_SHIFT)) & DMA_COMMON_INTB1_INTB12_MASK) + +#define DMA_COMMON_INTB1_INTB13_MASK (0x2000U) +#define DMA_COMMON_INTB1_INTB13_SHIFT (13U) +/*! INTB13 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB13_SHIFT)) & DMA_COMMON_INTB1_INTB13_MASK) + +#define DMA_COMMON_INTB1_INTB14_MASK (0x4000U) +#define DMA_COMMON_INTB1_INTB14_SHIFT (14U) +/*! INTB14 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB14_SHIFT)) & DMA_COMMON_INTB1_INTB14_MASK) + +#define DMA_COMMON_INTB1_INTB15_MASK (0x8000U) +#define DMA_COMMON_INTB1_INTB15_SHIFT (15U) +/*! INTB15 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB15_SHIFT)) & DMA_COMMON_INTB1_INTB15_MASK) + +#define DMA_COMMON_INTB1_INTB16_MASK (0x10000U) +#define DMA_COMMON_INTB1_INTB16_SHIFT (16U) +/*! INTB16 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB16_SHIFT)) & DMA_COMMON_INTB1_INTB16_MASK) + +#define DMA_COMMON_INTB1_INTB17_MASK (0x20000U) +#define DMA_COMMON_INTB1_INTB17_SHIFT (17U) +/*! INTB17 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB17_SHIFT)) & DMA_COMMON_INTB1_INTB17_MASK) + +#define DMA_COMMON_INTB1_INTB18_MASK (0x40000U) +#define DMA_COMMON_INTB1_INTB18_SHIFT (18U) +/*! INTB18 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB18_SHIFT)) & DMA_COMMON_INTB1_INTB18_MASK) + +#define DMA_COMMON_INTB1_INTB19_MASK (0x80000U) +#define DMA_COMMON_INTB1_INTB19_SHIFT (19U) +/*! INTB19 - Interrupt B status for DMA channel. + * 0b0..The DMA channel interrupt B is not active. + * 0b1..The DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB1_INTB19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB19_SHIFT)) & DMA_COMMON_INTB1_INTB19_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB1 */ +#define DMA_COMMON_INTB1_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_SETVALID_SETVALID0_MASK (0x1U) +#define DMA_COMMON_SETVALID_SETVALID0_SHIFT (0U) +/*! SETVALID0 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID0_SHIFT)) & DMA_COMMON_SETVALID_SETVALID0_MASK) + +#define DMA_COMMON_SETVALID_SETVALID1_MASK (0x2U) +#define DMA_COMMON_SETVALID_SETVALID1_SHIFT (1U) +/*! SETVALID1 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID1_SHIFT)) & DMA_COMMON_SETVALID_SETVALID1_MASK) + +#define DMA_COMMON_SETVALID_SETVALID2_MASK (0x4U) +#define DMA_COMMON_SETVALID_SETVALID2_SHIFT (2U) +/*! SETVALID2 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID2_SHIFT)) & DMA_COMMON_SETVALID_SETVALID2_MASK) + +#define DMA_COMMON_SETVALID_SETVALID3_MASK (0x8U) +#define DMA_COMMON_SETVALID_SETVALID3_SHIFT (3U) +/*! SETVALID3 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID3_SHIFT)) & DMA_COMMON_SETVALID_SETVALID3_MASK) + +#define DMA_COMMON_SETVALID_SETVALID4_MASK (0x10U) +#define DMA_COMMON_SETVALID_SETVALID4_SHIFT (4U) +/*! SETVALID4 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID4_SHIFT)) & DMA_COMMON_SETVALID_SETVALID4_MASK) + +#define DMA_COMMON_SETVALID_SETVALID5_MASK (0x20U) +#define DMA_COMMON_SETVALID_SETVALID5_SHIFT (5U) +/*! SETVALID5 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID5_SHIFT)) & DMA_COMMON_SETVALID_SETVALID5_MASK) + +#define DMA_COMMON_SETVALID_SETVALID6_MASK (0x40U) +#define DMA_COMMON_SETVALID_SETVALID6_SHIFT (6U) +/*! SETVALID6 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID6_SHIFT)) & DMA_COMMON_SETVALID_SETVALID6_MASK) + +#define DMA_COMMON_SETVALID_SETVALID7_MASK (0x80U) +#define DMA_COMMON_SETVALID_SETVALID7_SHIFT (7U) +/*! SETVALID7 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID7_SHIFT)) & DMA_COMMON_SETVALID_SETVALID7_MASK) + +#define DMA_COMMON_SETVALID_SETVALID8_MASK (0x100U) +#define DMA_COMMON_SETVALID_SETVALID8_SHIFT (8U) +/*! SETVALID8 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID8_SHIFT)) & DMA_COMMON_SETVALID_SETVALID8_MASK) + +#define DMA_COMMON_SETVALID_SETVALID9_MASK (0x200U) +#define DMA_COMMON_SETVALID_SETVALID9_SHIFT (9U) +/*! SETVALID9 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID9_SHIFT)) & DMA_COMMON_SETVALID_SETVALID9_MASK) + +#define DMA_COMMON_SETVALID_SETVALID10_MASK (0x400U) +#define DMA_COMMON_SETVALID_SETVALID10_SHIFT (10U) +/*! SETVALID10 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID10_SHIFT)) & DMA_COMMON_SETVALID_SETVALID10_MASK) + +#define DMA_COMMON_SETVALID_SETVALID11_MASK (0x800U) +#define DMA_COMMON_SETVALID_SETVALID11_SHIFT (11U) +/*! SETVALID11 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID11_SHIFT)) & DMA_COMMON_SETVALID_SETVALID11_MASK) + +#define DMA_COMMON_SETVALID_SETVALID12_MASK (0x1000U) +#define DMA_COMMON_SETVALID_SETVALID12_SHIFT (12U) +/*! SETVALID12 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID12_SHIFT)) & DMA_COMMON_SETVALID_SETVALID12_MASK) + +#define DMA_COMMON_SETVALID_SETVALID13_MASK (0x2000U) +#define DMA_COMMON_SETVALID_SETVALID13_SHIFT (13U) +/*! SETVALID13 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID13_SHIFT)) & DMA_COMMON_SETVALID_SETVALID13_MASK) + +#define DMA_COMMON_SETVALID_SETVALID14_MASK (0x4000U) +#define DMA_COMMON_SETVALID_SETVALID14_SHIFT (14U) +/*! SETVALID14 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID14_SHIFT)) & DMA_COMMON_SETVALID_SETVALID14_MASK) + +#define DMA_COMMON_SETVALID_SETVALID15_MASK (0x8000U) +#define DMA_COMMON_SETVALID_SETVALID15_SHIFT (15U) +/*! SETVALID15 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID15_SHIFT)) & DMA_COMMON_SETVALID_SETVALID15_MASK) + +#define DMA_COMMON_SETVALID_SETVALID16_MASK (0x10000U) +#define DMA_COMMON_SETVALID_SETVALID16_SHIFT (16U) +/*! SETVALID16 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID16_SHIFT)) & DMA_COMMON_SETVALID_SETVALID16_MASK) + +#define DMA_COMMON_SETVALID_SETVALID17_MASK (0x20000U) +#define DMA_COMMON_SETVALID_SETVALID17_SHIFT (17U) +/*! SETVALID17 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID17_SHIFT)) & DMA_COMMON_SETVALID_SETVALID17_MASK) + +#define DMA_COMMON_SETVALID_SETVALID18_MASK (0x40000U) +#define DMA_COMMON_SETVALID_SETVALID18_SHIFT (18U) +/*! SETVALID18 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID18_SHIFT)) & DMA_COMMON_SETVALID_SETVALID18_MASK) + +#define DMA_COMMON_SETVALID_SETVALID19_MASK (0x80000U) +#define DMA_COMMON_SETVALID_SETVALID19_SHIFT (19U) +/*! SETVALID19 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID19_SHIFT)) & DMA_COMMON_SETVALID_SETVALID19_MASK) + +#define DMA_COMMON_SETVALID_SETVALID20_MASK (0x100000U) +#define DMA_COMMON_SETVALID_SETVALID20_SHIFT (20U) +/*! SETVALID20 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID20_SHIFT)) & DMA_COMMON_SETVALID_SETVALID20_MASK) + +#define DMA_COMMON_SETVALID_SETVALID21_MASK (0x200000U) +#define DMA_COMMON_SETVALID_SETVALID21_SHIFT (21U) +/*! SETVALID21 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID21_SHIFT)) & DMA_COMMON_SETVALID_SETVALID21_MASK) + +#define DMA_COMMON_SETVALID_SETVALID22_MASK (0x400000U) +#define DMA_COMMON_SETVALID_SETVALID22_SHIFT (22U) +/*! SETVALID22 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID22_SHIFT)) & DMA_COMMON_SETVALID_SETVALID22_MASK) + +#define DMA_COMMON_SETVALID_SETVALID23_MASK (0x800000U) +#define DMA_COMMON_SETVALID_SETVALID23_SHIFT (23U) +/*! SETVALID23 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID23_SHIFT)) & DMA_COMMON_SETVALID_SETVALID23_MASK) + +#define DMA_COMMON_SETVALID_SETVALID24_MASK (0x1000000U) +#define DMA_COMMON_SETVALID_SETVALID24_SHIFT (24U) +/*! SETVALID24 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID24_SHIFT)) & DMA_COMMON_SETVALID_SETVALID24_MASK) + +#define DMA_COMMON_SETVALID_SETVALID25_MASK (0x2000000U) +#define DMA_COMMON_SETVALID_SETVALID25_SHIFT (25U) +/*! SETVALID25 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID25_SHIFT)) & DMA_COMMON_SETVALID_SETVALID25_MASK) + +#define DMA_COMMON_SETVALID_SETVALID26_MASK (0x4000000U) +#define DMA_COMMON_SETVALID_SETVALID26_SHIFT (26U) +/*! SETVALID26 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID26_SHIFT)) & DMA_COMMON_SETVALID_SETVALID26_MASK) + +#define DMA_COMMON_SETVALID_SETVALID27_MASK (0x8000000U) +#define DMA_COMMON_SETVALID_SETVALID27_SHIFT (27U) +/*! SETVALID27 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID27_SHIFT)) & DMA_COMMON_SETVALID_SETVALID27_MASK) + +#define DMA_COMMON_SETVALID_SETVALID28_MASK (0x10000000U) +#define DMA_COMMON_SETVALID_SETVALID28_SHIFT (28U) +/*! SETVALID28 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID28_SHIFT)) & DMA_COMMON_SETVALID_SETVALID28_MASK) + +#define DMA_COMMON_SETVALID_SETVALID29_MASK (0x20000000U) +#define DMA_COMMON_SETVALID_SETVALID29_SHIFT (29U) +/*! SETVALID29 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID29_SHIFT)) & DMA_COMMON_SETVALID_SETVALID29_MASK) + +#define DMA_COMMON_SETVALID_SETVALID30_MASK (0x40000000U) +#define DMA_COMMON_SETVALID_SETVALID30_SHIFT (30U) +/*! SETVALID30 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID30_SHIFT)) & DMA_COMMON_SETVALID_SETVALID30_MASK) + +#define DMA_COMMON_SETVALID_SETVALID31_MASK (0x80000000U) +#define DMA_COMMON_SETVALID_SETVALID31_SHIFT (31U) +/*! SETVALID31 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID_SETVALID31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID31_SHIFT)) & DMA_COMMON_SETVALID_SETVALID31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETVALID1 - Set ValidPending control bits for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_SETVALID1_SETVALID32_MASK (0x1U) +#define DMA_COMMON_SETVALID1_SETVALID32_SHIFT (0U) +/*! SETVALID32 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID32_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID32_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID33_MASK (0x2U) +#define DMA_COMMON_SETVALID1_SETVALID33_SHIFT (1U) +/*! SETVALID33 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID33_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID33_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID34_MASK (0x4U) +#define DMA_COMMON_SETVALID1_SETVALID34_SHIFT (2U) +/*! SETVALID34 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID34_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID34_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID35_MASK (0x8U) +#define DMA_COMMON_SETVALID1_SETVALID35_SHIFT (3U) +/*! SETVALID35 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID35_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID35_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID36_MASK (0x10U) +#define DMA_COMMON_SETVALID1_SETVALID36_SHIFT (4U) +/*! SETVALID36 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID36_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID36_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID37_MASK (0x20U) +#define DMA_COMMON_SETVALID1_SETVALID37_SHIFT (5U) +/*! SETVALID37 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID37_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID37_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID38_MASK (0x40U) +#define DMA_COMMON_SETVALID1_SETVALID38_SHIFT (6U) +/*! SETVALID38 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID38_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID38_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID39_MASK (0x80U) +#define DMA_COMMON_SETVALID1_SETVALID39_SHIFT (7U) +/*! SETVALID39 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID39_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID39_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID40_MASK (0x100U) +#define DMA_COMMON_SETVALID1_SETVALID40_SHIFT (8U) +/*! SETVALID40 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID40_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID40_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID41_MASK (0x200U) +#define DMA_COMMON_SETVALID1_SETVALID41_SHIFT (9U) +/*! SETVALID41 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID41_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID41_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID42_MASK (0x400U) +#define DMA_COMMON_SETVALID1_SETVALID42_SHIFT (10U) +/*! SETVALID42 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID42_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID42_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID43_MASK (0x800U) +#define DMA_COMMON_SETVALID1_SETVALID43_SHIFT (11U) +/*! SETVALID43 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID43_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID43_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID44_MASK (0x1000U) +#define DMA_COMMON_SETVALID1_SETVALID44_SHIFT (12U) +/*! SETVALID44 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID44_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID44_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID45_MASK (0x2000U) +#define DMA_COMMON_SETVALID1_SETVALID45_SHIFT (13U) +/*! SETVALID45 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID45_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID45_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID46_MASK (0x4000U) +#define DMA_COMMON_SETVALID1_SETVALID46_SHIFT (14U) +/*! SETVALID46 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID46_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID46_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID47_MASK (0x8000U) +#define DMA_COMMON_SETVALID1_SETVALID47_SHIFT (15U) +/*! SETVALID47 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID47_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID47_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID48_MASK (0x10000U) +#define DMA_COMMON_SETVALID1_SETVALID48_SHIFT (16U) +/*! SETVALID48 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID48_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID48_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID49_MASK (0x20000U) +#define DMA_COMMON_SETVALID1_SETVALID49_SHIFT (17U) +/*! SETVALID49 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID49_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID49_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID50_MASK (0x40000U) +#define DMA_COMMON_SETVALID1_SETVALID50_SHIFT (18U) +/*! SETVALID50 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID50_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID50_MASK) + +#define DMA_COMMON_SETVALID1_SETVALID51_MASK (0x80000U) +#define DMA_COMMON_SETVALID1_SETVALID51_SHIFT (19U) +/*! SETVALID51 - SetValid control for DMA channel. + * 0b0..No effect. + * 0b1..Sets the ValidPending control bit for DMA channel. + */ +#define DMA_COMMON_SETVALID1_SETVALID51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID51_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID1 */ +#define DMA_COMMON_SETVALID1_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_SETTRIG_SETTRIG0_MASK (0x1U) +#define DMA_COMMON_SETTRIG_SETTRIG0_SHIFT (0U) +/*! SETTRIG0 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG0_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG0_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG1_MASK (0x2U) +#define DMA_COMMON_SETTRIG_SETTRIG1_SHIFT (1U) +/*! SETTRIG1 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG1_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG1_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG2_MASK (0x4U) +#define DMA_COMMON_SETTRIG_SETTRIG2_SHIFT (2U) +/*! SETTRIG2 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG2_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG2_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG3_MASK (0x8U) +#define DMA_COMMON_SETTRIG_SETTRIG3_SHIFT (3U) +/*! SETTRIG3 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG3_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG3_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG4_MASK (0x10U) +#define DMA_COMMON_SETTRIG_SETTRIG4_SHIFT (4U) +/*! SETTRIG4 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG4_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG4_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG5_MASK (0x20U) +#define DMA_COMMON_SETTRIG_SETTRIG5_SHIFT (5U) +/*! SETTRIG5 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG5_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG5_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG6_MASK (0x40U) +#define DMA_COMMON_SETTRIG_SETTRIG6_SHIFT (6U) +/*! SETTRIG6 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG6_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG6_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG7_MASK (0x80U) +#define DMA_COMMON_SETTRIG_SETTRIG7_SHIFT (7U) +/*! SETTRIG7 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG7_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG7_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG8_MASK (0x100U) +#define DMA_COMMON_SETTRIG_SETTRIG8_SHIFT (8U) +/*! SETTRIG8 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG8_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG8_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG9_MASK (0x200U) +#define DMA_COMMON_SETTRIG_SETTRIG9_SHIFT (9U) +/*! SETTRIG9 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG9_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG9_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG10_MASK (0x400U) +#define DMA_COMMON_SETTRIG_SETTRIG10_SHIFT (10U) +/*! SETTRIG10 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG10_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG10_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG11_MASK (0x800U) +#define DMA_COMMON_SETTRIG_SETTRIG11_SHIFT (11U) +/*! SETTRIG11 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG11_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG11_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG12_MASK (0x1000U) +#define DMA_COMMON_SETTRIG_SETTRIG12_SHIFT (12U) +/*! SETTRIG12 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG12_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG12_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG13_MASK (0x2000U) +#define DMA_COMMON_SETTRIG_SETTRIG13_SHIFT (13U) +/*! SETTRIG13 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG13_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG13_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG14_MASK (0x4000U) +#define DMA_COMMON_SETTRIG_SETTRIG14_SHIFT (14U) +/*! SETTRIG14 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG14_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG14_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG15_MASK (0x8000U) +#define DMA_COMMON_SETTRIG_SETTRIG15_SHIFT (15U) +/*! SETTRIG15 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG15_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG15_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG16_MASK (0x10000U) +#define DMA_COMMON_SETTRIG_SETTRIG16_SHIFT (16U) +/*! SETTRIG16 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG16_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG16_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG17_MASK (0x20000U) +#define DMA_COMMON_SETTRIG_SETTRIG17_SHIFT (17U) +/*! SETTRIG17 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG17_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG17_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG18_MASK (0x40000U) +#define DMA_COMMON_SETTRIG_SETTRIG18_SHIFT (18U) +/*! SETTRIG18 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG18_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG18_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG19_MASK (0x80000U) +#define DMA_COMMON_SETTRIG_SETTRIG19_SHIFT (19U) +/*! SETTRIG19 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG19_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG19_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG20_MASK (0x100000U) +#define DMA_COMMON_SETTRIG_SETTRIG20_SHIFT (20U) +/*! SETTRIG20 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG20_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG20_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG21_MASK (0x200000U) +#define DMA_COMMON_SETTRIG_SETTRIG21_SHIFT (21U) +/*! SETTRIG21 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG21_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG21_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG22_MASK (0x400000U) +#define DMA_COMMON_SETTRIG_SETTRIG22_SHIFT (22U) +/*! SETTRIG22 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG22_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG22_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG23_MASK (0x800000U) +#define DMA_COMMON_SETTRIG_SETTRIG23_SHIFT (23U) +/*! SETTRIG23 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG23_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG23_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG24_MASK (0x1000000U) +#define DMA_COMMON_SETTRIG_SETTRIG24_SHIFT (24U) +/*! SETTRIG24 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG24_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG24_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG25_MASK (0x2000000U) +#define DMA_COMMON_SETTRIG_SETTRIG25_SHIFT (25U) +/*! SETTRIG25 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG25_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG25_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG26_MASK (0x4000000U) +#define DMA_COMMON_SETTRIG_SETTRIG26_SHIFT (26U) +/*! SETTRIG26 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG26_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG26_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG27_MASK (0x8000000U) +#define DMA_COMMON_SETTRIG_SETTRIG27_SHIFT (27U) +/*! SETTRIG27 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG27_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG27_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG28_MASK (0x10000000U) +#define DMA_COMMON_SETTRIG_SETTRIG28_SHIFT (28U) +/*! SETTRIG28 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG28_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG28_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG29_MASK (0x20000000U) +#define DMA_COMMON_SETTRIG_SETTRIG29_SHIFT (29U) +/*! SETTRIG29 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG29_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG29_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG30_MASK (0x40000000U) +#define DMA_COMMON_SETTRIG_SETTRIG30_SHIFT (30U) +/*! SETTRIG30 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG30_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG30_MASK) + +#define DMA_COMMON_SETTRIG_SETTRIG31_MASK (0x80000000U) +#define DMA_COMMON_SETTRIG_SETTRIG31_SHIFT (31U) +/*! SETTRIG31 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG_SETTRIG31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG31_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_SETTRIG1 - Set Trigger control bits for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_SETTRIG1_SETTRIG32_MASK (0x1U) +#define DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT (0U) +/*! SETTRIG32 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG32_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG33_MASK (0x2U) +#define DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT (1U) +/*! SETTRIG33 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG33_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG34_MASK (0x4U) +#define DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT (2U) +/*! SETTRIG34 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG34_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG35_MASK (0x8U) +#define DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT (3U) +/*! SETTRIG35 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG35_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG36_MASK (0x10U) +#define DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT (4U) +/*! SETTRIG36 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG36_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG37_MASK (0x20U) +#define DMA_COMMON_SETTRIG1_SETTRIG37_SHIFT (5U) +/*! SETTRIG37 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG37_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG37_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG38_MASK (0x40U) +#define DMA_COMMON_SETTRIG1_SETTRIG38_SHIFT (6U) +/*! SETTRIG38 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG38_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG38_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG39_MASK (0x80U) +#define DMA_COMMON_SETTRIG1_SETTRIG39_SHIFT (7U) +/*! SETTRIG39 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG39_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG39_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG40_MASK (0x100U) +#define DMA_COMMON_SETTRIG1_SETTRIG40_SHIFT (8U) +/*! SETTRIG40 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG40_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG40_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG41_MASK (0x200U) +#define DMA_COMMON_SETTRIG1_SETTRIG41_SHIFT (9U) +/*! SETTRIG41 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG41_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG41_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG42_MASK (0x400U) +#define DMA_COMMON_SETTRIG1_SETTRIG42_SHIFT (10U) +/*! SETTRIG42 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG42_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG42_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG43_MASK (0x800U) +#define DMA_COMMON_SETTRIG1_SETTRIG43_SHIFT (11U) +/*! SETTRIG43 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG43_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG43_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG44_MASK (0x1000U) +#define DMA_COMMON_SETTRIG1_SETTRIG44_SHIFT (12U) +/*! SETTRIG44 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG44_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG44_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG45_MASK (0x2000U) +#define DMA_COMMON_SETTRIG1_SETTRIG45_SHIFT (13U) +/*! SETTRIG45 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG45_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG45_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG46_MASK (0x4000U) +#define DMA_COMMON_SETTRIG1_SETTRIG46_SHIFT (14U) +/*! SETTRIG46 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG46_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG46_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG47_MASK (0x8000U) +#define DMA_COMMON_SETTRIG1_SETTRIG47_SHIFT (15U) +/*! SETTRIG47 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG47_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG47_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG48_MASK (0x10000U) +#define DMA_COMMON_SETTRIG1_SETTRIG48_SHIFT (16U) +/*! SETTRIG48 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG48_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG48_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG49_MASK (0x20000U) +#define DMA_COMMON_SETTRIG1_SETTRIG49_SHIFT (17U) +/*! SETTRIG49 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG49_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG49_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG50_MASK (0x40000U) +#define DMA_COMMON_SETTRIG1_SETTRIG50_SHIFT (18U) +/*! SETTRIG50 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG50_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG50_MASK) + +#define DMA_COMMON_SETTRIG1_SETTRIG51_MASK (0x80000U) +#define DMA_COMMON_SETTRIG1_SETTRIG51_SHIFT (19U) +/*! SETTRIG51 - Set Trigger control bit for DMA channel. + * 0b0..No effect. + * 0b1..Sets the Trig bit for DMA channel. + */ +#define DMA_COMMON_SETTRIG1_SETTRIG51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG51_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG1 */ +#define DMA_COMMON_SETTRIG1_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ABORT_ABORT0_MASK (0x1U) +#define DMA_COMMON_ABORT_ABORT0_SHIFT (0U) +/*! ABORT0 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT0_SHIFT)) & DMA_COMMON_ABORT_ABORT0_MASK) + +#define DMA_COMMON_ABORT_ABORT1_MASK (0x2U) +#define DMA_COMMON_ABORT_ABORT1_SHIFT (1U) +/*! ABORT1 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT1_SHIFT)) & DMA_COMMON_ABORT_ABORT1_MASK) + +#define DMA_COMMON_ABORT_ABORT2_MASK (0x4U) +#define DMA_COMMON_ABORT_ABORT2_SHIFT (2U) +/*! ABORT2 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT2_SHIFT)) & DMA_COMMON_ABORT_ABORT2_MASK) + +#define DMA_COMMON_ABORT_ABORT3_MASK (0x8U) +#define DMA_COMMON_ABORT_ABORT3_SHIFT (3U) +/*! ABORT3 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT3_SHIFT)) & DMA_COMMON_ABORT_ABORT3_MASK) + +#define DMA_COMMON_ABORT_ABORT4_MASK (0x10U) +#define DMA_COMMON_ABORT_ABORT4_SHIFT (4U) +/*! ABORT4 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT4_SHIFT)) & DMA_COMMON_ABORT_ABORT4_MASK) + +#define DMA_COMMON_ABORT_ABORT5_MASK (0x20U) +#define DMA_COMMON_ABORT_ABORT5_SHIFT (5U) +/*! ABORT5 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT5_SHIFT)) & DMA_COMMON_ABORT_ABORT5_MASK) + +#define DMA_COMMON_ABORT_ABORT6_MASK (0x40U) +#define DMA_COMMON_ABORT_ABORT6_SHIFT (6U) +/*! ABORT6 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT6_SHIFT)) & DMA_COMMON_ABORT_ABORT6_MASK) + +#define DMA_COMMON_ABORT_ABORT7_MASK (0x80U) +#define DMA_COMMON_ABORT_ABORT7_SHIFT (7U) +/*! ABORT7 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT7_SHIFT)) & DMA_COMMON_ABORT_ABORT7_MASK) + +#define DMA_COMMON_ABORT_ABORT8_MASK (0x100U) +#define DMA_COMMON_ABORT_ABORT8_SHIFT (8U) +/*! ABORT8 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT8_SHIFT)) & DMA_COMMON_ABORT_ABORT8_MASK) + +#define DMA_COMMON_ABORT_ABORT9_MASK (0x200U) +#define DMA_COMMON_ABORT_ABORT9_SHIFT (9U) +/*! ABORT9 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT9_SHIFT)) & DMA_COMMON_ABORT_ABORT9_MASK) + +#define DMA_COMMON_ABORT_ABORT10_MASK (0x400U) +#define DMA_COMMON_ABORT_ABORT10_SHIFT (10U) +/*! ABORT10 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT10_SHIFT)) & DMA_COMMON_ABORT_ABORT10_MASK) + +#define DMA_COMMON_ABORT_ABORT11_MASK (0x800U) +#define DMA_COMMON_ABORT_ABORT11_SHIFT (11U) +/*! ABORT11 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT11_SHIFT)) & DMA_COMMON_ABORT_ABORT11_MASK) + +#define DMA_COMMON_ABORT_ABORT12_MASK (0x1000U) +#define DMA_COMMON_ABORT_ABORT12_SHIFT (12U) +/*! ABORT12 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT12_SHIFT)) & DMA_COMMON_ABORT_ABORT12_MASK) + +#define DMA_COMMON_ABORT_ABORT13_MASK (0x2000U) +#define DMA_COMMON_ABORT_ABORT13_SHIFT (13U) +/*! ABORT13 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT13_SHIFT)) & DMA_COMMON_ABORT_ABORT13_MASK) + +#define DMA_COMMON_ABORT_ABORT14_MASK (0x4000U) +#define DMA_COMMON_ABORT_ABORT14_SHIFT (14U) +/*! ABORT14 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT14_SHIFT)) & DMA_COMMON_ABORT_ABORT14_MASK) + +#define DMA_COMMON_ABORT_ABORT15_MASK (0x8000U) +#define DMA_COMMON_ABORT_ABORT15_SHIFT (15U) +/*! ABORT15 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT15_SHIFT)) & DMA_COMMON_ABORT_ABORT15_MASK) + +#define DMA_COMMON_ABORT_ABORT16_MASK (0x10000U) +#define DMA_COMMON_ABORT_ABORT16_SHIFT (16U) +/*! ABORT16 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT16_SHIFT)) & DMA_COMMON_ABORT_ABORT16_MASK) + +#define DMA_COMMON_ABORT_ABORT17_MASK (0x20000U) +#define DMA_COMMON_ABORT_ABORT17_SHIFT (17U) +/*! ABORT17 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT17_SHIFT)) & DMA_COMMON_ABORT_ABORT17_MASK) + +#define DMA_COMMON_ABORT_ABORT18_MASK (0x40000U) +#define DMA_COMMON_ABORT_ABORT18_SHIFT (18U) +/*! ABORT18 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT18_SHIFT)) & DMA_COMMON_ABORT_ABORT18_MASK) + +#define DMA_COMMON_ABORT_ABORT19_MASK (0x80000U) +#define DMA_COMMON_ABORT_ABORT19_SHIFT (19U) +/*! ABORT19 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT19_SHIFT)) & DMA_COMMON_ABORT_ABORT19_MASK) + +#define DMA_COMMON_ABORT_ABORT20_MASK (0x100000U) +#define DMA_COMMON_ABORT_ABORT20_SHIFT (20U) +/*! ABORT20 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT20_SHIFT)) & DMA_COMMON_ABORT_ABORT20_MASK) + +#define DMA_COMMON_ABORT_ABORT21_MASK (0x200000U) +#define DMA_COMMON_ABORT_ABORT21_SHIFT (21U) +/*! ABORT21 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT21_SHIFT)) & DMA_COMMON_ABORT_ABORT21_MASK) + +#define DMA_COMMON_ABORT_ABORT22_MASK (0x400000U) +#define DMA_COMMON_ABORT_ABORT22_SHIFT (22U) +/*! ABORT22 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT22_SHIFT)) & DMA_COMMON_ABORT_ABORT22_MASK) + +#define DMA_COMMON_ABORT_ABORT23_MASK (0x800000U) +#define DMA_COMMON_ABORT_ABORT23_SHIFT (23U) +/*! ABORT23 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT23_SHIFT)) & DMA_COMMON_ABORT_ABORT23_MASK) + +#define DMA_COMMON_ABORT_ABORT24_MASK (0x1000000U) +#define DMA_COMMON_ABORT_ABORT24_SHIFT (24U) +/*! ABORT24 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT24_SHIFT)) & DMA_COMMON_ABORT_ABORT24_MASK) + +#define DMA_COMMON_ABORT_ABORT25_MASK (0x2000000U) +#define DMA_COMMON_ABORT_ABORT25_SHIFT (25U) +/*! ABORT25 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT25_SHIFT)) & DMA_COMMON_ABORT_ABORT25_MASK) + +#define DMA_COMMON_ABORT_ABORT26_MASK (0x4000000U) +#define DMA_COMMON_ABORT_ABORT26_SHIFT (26U) +/*! ABORT26 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT26_SHIFT)) & DMA_COMMON_ABORT_ABORT26_MASK) + +#define DMA_COMMON_ABORT_ABORT27_MASK (0x8000000U) +#define DMA_COMMON_ABORT_ABORT27_SHIFT (27U) +/*! ABORT27 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT27_SHIFT)) & DMA_COMMON_ABORT_ABORT27_MASK) + +#define DMA_COMMON_ABORT_ABORT28_MASK (0x10000000U) +#define DMA_COMMON_ABORT_ABORT28_SHIFT (28U) +/*! ABORT28 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT28_SHIFT)) & DMA_COMMON_ABORT_ABORT28_MASK) + +#define DMA_COMMON_ABORT_ABORT29_MASK (0x20000000U) +#define DMA_COMMON_ABORT_ABORT29_SHIFT (29U) +/*! ABORT29 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT29_SHIFT)) & DMA_COMMON_ABORT_ABORT29_MASK) + +#define DMA_COMMON_ABORT_ABORT30_MASK (0x40000000U) +#define DMA_COMMON_ABORT_ABORT30_SHIFT (30U) +/*! ABORT30 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT30_SHIFT)) & DMA_COMMON_ABORT_ABORT30_MASK) + +#define DMA_COMMON_ABORT_ABORT31_MASK (0x80000000U) +#define DMA_COMMON_ABORT_ABORT31_SHIFT (31U) +/*! ABORT31 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT_ABORT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT31_SHIFT)) & DMA_COMMON_ABORT_ABORT31_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name COMMON_ABORT1 - Channel Abort control for all DMA channels */ +/*! @{ */ + +#define DMA_COMMON_ABORT1_ABORT32_MASK (0x1U) +#define DMA_COMMON_ABORT1_ABORT32_SHIFT (0U) +/*! ABORT32 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT32_SHIFT)) & DMA_COMMON_ABORT1_ABORT32_MASK) + +#define DMA_COMMON_ABORT1_ABORT33_MASK (0x2U) +#define DMA_COMMON_ABORT1_ABORT33_SHIFT (1U) +/*! ABORT33 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT33_SHIFT)) & DMA_COMMON_ABORT1_ABORT33_MASK) + +#define DMA_COMMON_ABORT1_ABORT34_MASK (0x4U) +#define DMA_COMMON_ABORT1_ABORT34_SHIFT (2U) +/*! ABORT34 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT34_SHIFT)) & DMA_COMMON_ABORT1_ABORT34_MASK) + +#define DMA_COMMON_ABORT1_ABORT35_MASK (0x8U) +#define DMA_COMMON_ABORT1_ABORT35_SHIFT (3U) +/*! ABORT35 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT35_SHIFT)) & DMA_COMMON_ABORT1_ABORT35_MASK) + +#define DMA_COMMON_ABORT1_ABORT36_MASK (0x10U) +#define DMA_COMMON_ABORT1_ABORT36_SHIFT (4U) +/*! ABORT36 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT36_SHIFT)) & DMA_COMMON_ABORT1_ABORT36_MASK) + +#define DMA_COMMON_ABORT1_ABORT37_MASK (0x20U) +#define DMA_COMMON_ABORT1_ABORT37_SHIFT (5U) +/*! ABORT37 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT37(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT37_SHIFT)) & DMA_COMMON_ABORT1_ABORT37_MASK) + +#define DMA_COMMON_ABORT1_ABORT38_MASK (0x40U) +#define DMA_COMMON_ABORT1_ABORT38_SHIFT (6U) +/*! ABORT38 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT38(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT38_SHIFT)) & DMA_COMMON_ABORT1_ABORT38_MASK) + +#define DMA_COMMON_ABORT1_ABORT39_MASK (0x80U) +#define DMA_COMMON_ABORT1_ABORT39_SHIFT (7U) +/*! ABORT39 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT39(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT39_SHIFT)) & DMA_COMMON_ABORT1_ABORT39_MASK) + +#define DMA_COMMON_ABORT1_ABORT40_MASK (0x100U) +#define DMA_COMMON_ABORT1_ABORT40_SHIFT (8U) +/*! ABORT40 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT40(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT40_SHIFT)) & DMA_COMMON_ABORT1_ABORT40_MASK) + +#define DMA_COMMON_ABORT1_ABORT41_MASK (0x200U) +#define DMA_COMMON_ABORT1_ABORT41_SHIFT (9U) +/*! ABORT41 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT41(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT41_SHIFT)) & DMA_COMMON_ABORT1_ABORT41_MASK) + +#define DMA_COMMON_ABORT1_ABORT42_MASK (0x400U) +#define DMA_COMMON_ABORT1_ABORT42_SHIFT (10U) +/*! ABORT42 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT42(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT42_SHIFT)) & DMA_COMMON_ABORT1_ABORT42_MASK) + +#define DMA_COMMON_ABORT1_ABORT43_MASK (0x800U) +#define DMA_COMMON_ABORT1_ABORT43_SHIFT (11U) +/*! ABORT43 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT43(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT43_SHIFT)) & DMA_COMMON_ABORT1_ABORT43_MASK) + +#define DMA_COMMON_ABORT1_ABORT44_MASK (0x1000U) +#define DMA_COMMON_ABORT1_ABORT44_SHIFT (12U) +/*! ABORT44 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT44(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT44_SHIFT)) & DMA_COMMON_ABORT1_ABORT44_MASK) + +#define DMA_COMMON_ABORT1_ABORT45_MASK (0x2000U) +#define DMA_COMMON_ABORT1_ABORT45_SHIFT (13U) +/*! ABORT45 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT45(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT45_SHIFT)) & DMA_COMMON_ABORT1_ABORT45_MASK) + +#define DMA_COMMON_ABORT1_ABORT46_MASK (0x4000U) +#define DMA_COMMON_ABORT1_ABORT46_SHIFT (14U) +/*! ABORT46 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT46(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT46_SHIFT)) & DMA_COMMON_ABORT1_ABORT46_MASK) + +#define DMA_COMMON_ABORT1_ABORT47_MASK (0x8000U) +#define DMA_COMMON_ABORT1_ABORT47_SHIFT (15U) +/*! ABORT47 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT47(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT47_SHIFT)) & DMA_COMMON_ABORT1_ABORT47_MASK) + +#define DMA_COMMON_ABORT1_ABORT48_MASK (0x10000U) +#define DMA_COMMON_ABORT1_ABORT48_SHIFT (16U) +/*! ABORT48 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT48(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT48_SHIFT)) & DMA_COMMON_ABORT1_ABORT48_MASK) + +#define DMA_COMMON_ABORT1_ABORT49_MASK (0x20000U) +#define DMA_COMMON_ABORT1_ABORT49_SHIFT (17U) +/*! ABORT49 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT49(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT49_SHIFT)) & DMA_COMMON_ABORT1_ABORT49_MASK) + +#define DMA_COMMON_ABORT1_ABORT50_MASK (0x40000U) +#define DMA_COMMON_ABORT1_ABORT50_SHIFT (18U) +/*! ABORT50 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT50(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT50_SHIFT)) & DMA_COMMON_ABORT1_ABORT50_MASK) + +#define DMA_COMMON_ABORT1_ABORT51_MASK (0x80000U) +#define DMA_COMMON_ABORT1_ABORT51_SHIFT (19U) +/*! ABORT51 - Abort control for DMA channel. + * 0b0..No effect. + * 0b1..Aborts DMA operations on channel. + */ +#define DMA_COMMON_ABORT1_ABORT51(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT51_SHIFT)) & DMA_COMMON_ABORT1_ABORT51_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT1 */ +#define DMA_COMMON_ABORT1_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel */ +/*! @{ */ + +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. + * 0b0..Peripheral DMA requests disabled. + * 0b1..Peripheral DMA requests enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for channel. + * 0b0..Hardware triggering not used for channel. + * 0b1..Hardware triggering used for channel. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. + * 0b0..Single transfer. + * 0b1..Burst transfer. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power. + */ +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of channel when multiple DMA requests are pending. + */ +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (52U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel */ +/*! @{ */ + +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. + * 0b0..No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (52U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel */ +/*! @{ */ + +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. + * 0b0..Not valid. + * 0b1..Valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Reload. + * 0b0..Disabled. The channels' control structure should not be reloaded when the current descriptor is exhausted. + * 0b1..Enabled. The channels' control structure should be reloaded when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. + * 0b1..Set. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. + * 0b1..Cleared. + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for channel. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for channel. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. + * 0b01..16-bit. + * 0b10..32-bit. + * 0b11..Reserved. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Source address increment + * 0b00..No increment. + * 0b01..1 x width. + * 0b10..2 x width. + * 0b11..4 x width. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Destination address increment + * 0b00..No increment. + * 0b01..1 x width. + * 0b10..2 x width. + * 0b11..4 x width. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. + */ +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (52U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMIC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer + * @{ + */ + +/** DMIC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t OSR; /**< Oversample Rate, array offset: 0x0, array step: 0x100 */ + __IO uint32_t DIVHFCLK; /**< DMIC Clock, array offset: 0x4, array step: 0x100 */ + __IO uint32_t PREAC2FSCOEF; /**< Compensation Filter for 2 FS, array offset: 0x8, array step: 0x100 */ + __IO uint32_t PREAC4FSCOEF; /**< Compensation Filter for 4 FS, array offset: 0xC, array step: 0x100 */ + __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_0[108]; + __IO uint32_t FIFO_CTRL; /**< FIFO Control, array offset: 0x80, array step: 0x100 */ + __IO uint32_t FIFO_STATUS; /**< FIFO Status, array offset: 0x84, array step: 0x100 */ + __I uint32_t FIFO_DATA; /**< FIFO Data, array offset: 0x88, array step: 0x100 */ + __IO uint32_t PHY_CTRL; /**< Physical Control, array offset: 0x8C, array step: 0x100 */ + __IO uint32_t DC_CTRL; /**< DC Filter Control, array offset: 0x90, array step: 0x100 */ + uint8_t RESERVED_1[108]; + } CHANNEL[2]; + uint8_t RESERVED_0[3328]; + __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */ + uint8_t RESERVED_1[12]; + __IO uint32_t USE2FS; /**< Use 2 FS register, offset: 0xF10 */ + __IO uint32_t GLOBAL_SYNC_EN; /**< Global Channel Synchronization Enable, offset: 0xF14 */ + __IO uint32_t GLOBAL_COUNT_VAL; /**< Global channel synchronization counter value, offset: 0xF18 */ + __IO uint32_t DECRESET; /**< DMIC decimator reset, offset: 0xF1C */ + uint8_t RESERVED_2[96]; + __IO uint32_t HWVADGAIN; /**< HWVAD Input Gain, offset: 0xF80 */ + __IO uint32_t HWVADHPFS; /**< HWVAD Filter Control, offset: 0xF84 */ + __IO uint32_t HWVADST10; /**< HWVAD Control, offset: 0xF88 */ + __IO uint32_t HWVADRSTT; /**< HWVAD Filter Reset, offset: 0xF8C */ + __IO uint32_t HWVADTHGN; /**< HWVAD Noise Estimator Gain, offset: 0xF90 */ + __IO uint32_t HWVADTHGS; /**< HWVAD Signal Estimator Gain, offset: 0xF94 */ + __I uint32_t HWVADLOWZ; /**< HWVAD Noise Envelope Estimator, offset: 0xF98 */ +} DMIC_Type; + +/* ---------------------------------------------------------------------------- + -- DMIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Register_Masks DMIC Register Masks + * @{ + */ + +/*! @name CHANNEL_OSR - Oversample Rate */ +/*! @{ */ + +#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) +#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) +/*! OSR - Oversample Rate + */ +#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_OSR */ +#define DMIC_CHANNEL_OSR_COUNT (2U) + +/*! @name CHANNEL_DIVHFCLK - DMIC Clock */ +/*! @{ */ + +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) +/*! PDMDIV - PDM Clock Divider Value + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b0010..Divide by 3 + * 0b0011..Divide by 4 + * 0b0100..Divide by 6 + * 0b0101..Divide by 8 + * 0b0110..Divide by 12 + * 0b0111..Divide by 16 + * 0b1000..Divide by 24 + * 0b1001..Divide by 32 + * 0b1010..Divide by 48 + * 0b1011..Divide by 64 + * 0b1100..Divide by 96 + * 0b1101..Divide by 128 + * 0b1110-0b1111..Reserved + */ +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_DIVHFCLK */ +#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) + +/*! @name CHANNEL_PREAC2FSCOEF - Compensation Filter for 2 FS */ +/*! @{ */ + +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) +/*! COMP - Compensation value + * 0b00..Compensation = 0. This is the recommended setting. + * 0b01..Compensation = -0.16 + * 0b10..Compensation = -0.15 + * 0b11..Compensation = -0.13 + */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) + +/*! @name CHANNEL_PREAC4FSCOEF - Compensation Filter for 4 FS */ +/*! @{ */ + +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) +/*! COMP - Compensation value + * 0b00..Compensation = 0. This is the recommended setting. + * 0b01..Compensation = -0.16 + * 0b10..Compensation = -0.15 + * 0b11..Compensation = -0.13 + */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) + +/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift */ +/*! @{ */ + +#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x1FU) +#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) +/*! GAIN - Gain + */ +#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_GAINSHIFT */ +#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) + +/*! @name CHANNEL_FIFO_CTRL - FIFO Control */ +/*! @{ */ + +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - FIFO Enable. + * 0b0..Disabled. + * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register. + */ +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) + +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) +/*! RESETN - FIFO Reset + * 0b0..Reset the FIFO. This must be cleared before resuming operation. + * 0b1..Normal operation + */ +#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) + +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) +/*! INTEN - Interrupt Enable. + * 0b0..FIFO level interrupts are not enabled. + * 0b1..FIFO level interrupts are enabled. + */ +#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) + +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) +/*! DMAEN - DMA Enable + * 0b0..DMA requests are not enabled. + * 0b1..DMA requests based on FIFO level are enabled. + */ +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) + +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) +/*! TRIGLVL - FIFO Trigger Level for Interrupt + * 0b00000..Trigger when the FIFO has received one entry (is no longer empty). + * 0b00001..Trigger when the FIFO has received two entries. + * 0b01110..Trigger when the FIFO has received 15 entries. + * 0b01111..Trigger when the FIFO has received 16 entries (has become full). + */ +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_CTRL */ +#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) + +/*! @name CHANNEL_FIFO_STATUS - FIFO Status */ +/*! @{ */ + +#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) +/*! INT - Status of Interrupt (write 1 to clear) + */ +#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) + +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) +/*! OVERRUN - Overrun Detected (write 1 to clear) + */ +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) + +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) +/*! UNDERRUN - Underrun Detected (write 1 to clear) + */ +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_STATUS */ +#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) + +/*! @name CHANNEL_FIFO_DATA - FIFO Data */ +/*! @{ */ + +#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) +#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) +/*! DATA - PCM Data + */ +#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_DATA */ +#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) + +/*! @name CHANNEL_PHY_CTRL - Physical Control */ +/*! @{ */ + +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) +/*! PHY_FALL - Capture DMIC on Falling edge (0 means on rising) + * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK. + * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK. + */ +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) + +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) +/*! PHY_HALF - Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing) + * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. + * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate that the decimator is providing. + */ +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PHY_CTRL */ +#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) + +/*! @name CHANNEL_DC_CTRL - DC Filter Control */ +/*! @{ */ + +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) +/*! DCPOLE - DC Block Filter + * 0b00..Flat Response, no filter + * 0b01..155 Hz + * 0b10..78 Hz + * 0b11..39 Hz + */ +#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) + +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) +/*! DCGAIN - DC Gain + */ +#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) + +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) +/*! SATURATEAT16BIT - Saturate at 16 Bit + * 0b0..Do not Saturate. Results roll over if out range and do not saturate. + * 0b1..Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow. + */ +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) + +#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK (0x200U) +#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT (9U) +/*! SIGNEXTEND - Sign Extend + * 0b0..Disabled + * 0b1..Enabled + */ +#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_DC_CTRL */ +#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) + +/*! @name CHANEN - Channel Enable */ +/*! @{ */ + +#define DMIC_CHANEN_EN_CH0_MASK (0x1U) +#define DMIC_CHANEN_EN_CH0_SHIFT (0U) +/*! EN_CH0 - Enable Channel n + * 0b0..PDM channel n is disabled. + * 0b1..PDM channel n is enabled. + */ +#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) + +#define DMIC_CHANEN_EN_CH1_MASK (0x2U) +#define DMIC_CHANEN_EN_CH1_SHIFT (1U) +/*! EN_CH1 - Enable Channel n + * 0b0..PDM channel n is disabled. + * 0b1..PDM channel n is enabled. + */ +#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) +/*! @} */ + +/*! @name USE2FS - Use 2 FS register */ +/*! @{ */ + +#define DMIC_USE2FS_USE2FS_MASK (0x1U) +#define DMIC_USE2FS_USE2FS_SHIFT (0U) +/*! USE2FS - Use 2FS register + * 0b0..Use 1 FS output for PCM data. + * 0b1..Use 2 FS output for PCM data. + */ +#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) +/*! @} */ + +/*! @name GLOBAL_SYNC_EN - Global Channel Synchronization Enable */ +/*! @{ */ + +#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK (0x3U) +#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT (0U) +/*! CH_SYNC_EN - Channel synch enable + */ +#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT)) & DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK) +/*! @} */ + +/*! @name GLOBAL_COUNT_VAL - Global channel synchronization counter value */ +/*! @{ */ + +#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK (0xFFFFFFFFU) +#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT (0U) +/*! CCOUNTVAL - Channel Counter Value + */ +#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT)) & DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK) +/*! @} */ + +/*! @name DECRESET - DMIC decimator reset */ +/*! @{ */ + +#define DMIC_DECRESET_DECRESET_MASK (0x3U) +#define DMIC_DECRESET_DECRESET_SHIFT (0U) +/*! DECRESET - Decimator reset + * 0b00..Disable + * 0b01..Enable + */ +#define DMIC_DECRESET_DECRESET(x) (((uint32_t)(((uint32_t)(x)) << DMIC_DECRESET_DECRESET_SHIFT)) & DMIC_DECRESET_DECRESET_MASK) +/*! @} */ + +/*! @name HWVADGAIN - HWVAD Input Gain */ +/*! @{ */ + +#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) +#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) +/*! INPUTGAIN - Input Gain + * 0b0000..-10 bits + * 0b0001..-8 bits + * 0b0010..-6 bits + * 0b0011..-4 bits + * 0b0100..-2 bits + * 0b0101..0 bits (default) + * 0b0110..+2 bits + * 0b0111..+4 bits + * 0b1000..+6 bits + * 0b1001..+8 bits + * 0b1010..+10 bits + * 0b1011..+12 bits + * 0b1100..+14 bits + * 0b1101-0b1111..Reserved + */ +#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) +/*! @} */ + +/*! @name HWVADHPFS - HWVAD Filter Control */ +/*! @{ */ + +#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) +#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) +/*! HPFS - The HPFS field chooses the High Pass filter in first part of HWVAD. + * 0b00..Bypass + * 0b01..High Pass 1750 Hz + * 0b10..High Pass 215 Hz + * 0b11..Reserved + */ +#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) +/*! @} */ + +/*! @name HWVADST10 - HWVAD Control */ +/*! @{ */ + +#define DMIC_HWVADST10_ST10_MASK (0x1U) +#define DMIC_HWVADST10_ST10_SHIFT (0U) +/*! ST10 - STAGE 1 + * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0). + * 0b1..Reset internal interrupt flag by writing a '1' (stage 1) pulse. + */ +#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) +/*! @} */ + +/*! @name HWVADRSTT - HWVAD Filter Reset */ +/*! @{ */ + +#define DMIC_HWVADRSTT_RSST_MASK (0x1U) +#define DMIC_HWVADRSTT_RSST_SHIFT (0U) +/*! RSST - Reset HWVAD + */ +#define DMIC_HWVADRSTT_RSST(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSST_SHIFT)) & DMIC_HWVADRSTT_RSST_MASK) +/*! @} */ + +/*! @name HWVADTHGN - HWVAD Noise Estimator Gain */ +/*! @{ */ + +#define DMIC_HWVADTHGN_THGN_MASK (0xFU) +#define DMIC_HWVADTHGN_THGN_SHIFT (0U) +/*! THGN - Gain Factor for Noise Estimator + */ +#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) +/*! @} */ + +/*! @name HWVADTHGS - HWVAD Signal Estimator Gain */ +/*! @{ */ + +#define DMIC_HWVADTHGS_THGS_MASK (0xFU) +#define DMIC_HWVADTHGS_THGS_SHIFT (0U) +/*! THGS - Signal Gain Factor + */ +#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) +/*! @} */ + +/*! @name HWVADLOWZ - HWVAD Noise Envelope Estimator */ +/*! @{ */ + +#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) +#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) +/*! LOWZ - Average Noise-floor Value + */ +#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DMIC_Register_Masks */ + + +/* DMIC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMIC0 base address */ + #define DMIC0_BASE (0x50090000u) + /** Peripheral DMIC0 base address */ + #define DMIC0_BASE_NS (0x40090000u) + /** Peripheral DMIC0 base pointer */ + #define DMIC0 ((DMIC_Type *)DMIC0_BASE) + /** Peripheral DMIC0 base pointer */ + #define DMIC0_NS ((DMIC_Type *)DMIC0_BASE_NS) + /** Array initializer of DMIC peripheral base addresses */ + #define DMIC_BASE_ADDRS { DMIC0_BASE } + /** Array initializer of DMIC peripheral base pointers */ + #define DMIC_BASE_PTRS { DMIC0 } + /** Array initializer of DMIC peripheral base addresses */ + #define DMIC_BASE_ADDRS_NS { DMIC0_BASE_NS } + /** Array initializer of DMIC peripheral base pointers */ + #define DMIC_BASE_PTRS_NS { DMIC0_NS } +#else + /** Peripheral DMIC0 base address */ + #define DMIC0_BASE (0x40090000u) + /** Peripheral DMIC0 base pointer */ + #define DMIC0 ((DMIC_Type *)DMIC0_BASE) + /** Array initializer of DMIC peripheral base addresses */ + #define DMIC_BASE_ADDRS { DMIC0_BASE } + /** Array initializer of DMIC peripheral base pointers */ + #define DMIC_BASE_PTRS { DMIC0 } +#endif +/** Interrupt vectors for the DMIC peripheral type */ +#define DMIC_IRQS { DMIC_IRQn } +#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } + +/*! + * @} + */ /* end of group DMIC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer + * @{ + */ + +/** ENC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ + __IO uint16_t TST; /**< Test Register, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3 Register, offset: 0x32 */ +} ENC_Type; + +/* ---------------------------------------------------------------------------- + -- ENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Register_Masks ENC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ENC_CTRL_CMPIE_MASK (0x1U) +#define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) + +#define ENC_CTRL_CMPIRQ_MASK (0x2U) +#define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred (the counter does not match the COMP value) + * 0b1..COMP match has occurred (the counter matches the COMP value) + */ +#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) + +#define ENC_CTRL_WDE_MASK (0x4U) +#define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) + +#define ENC_CTRL_DIE_MASK (0x8U) +#define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) + +#define ENC_CTRL_DIRQ_MASK (0x10U) +#define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No Watchdog timeout interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) + +#define ENC_CTRL_XNE_MASK (0x20U) +#define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive edge of INDEX pulse + * 0b1..Use negative edge of INDEX pulse + */ +#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) + +#define ENC_CTRL_XIP_MASK (0x40U) +#define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..INDEX pulse does not initialize the position counter + * 0b1..INDEX pulse initializes the position counter + */ +#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) + +#define ENC_CTRL_XIE_MASK (0x80U) +#define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) + +#define ENC_CTRL_XIRQ_MASK (0x100U) +#define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..INDEX pulse has not occurred + * 0b1..INDEX pulse has occurred + */ +#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) + +#define ENC_CTRL_PH1_MASK (0x200U) +#define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The + * PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If + * CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, + * PHASEB = 0, then count down + */ +#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) + +#define ENC_CTRL_REV_MASK (0x400U) +#define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ +#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) + +#define ENC_CTRL_SWIP_MASK (0x800U) +#define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT) + */ +#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) + +#define ENC_CTRL_HNE_MASK (0x1000U) +#define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) + +#define ENC_CTRL_HIP_MASK (0x2000U) +#define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) + +#define ENC_CTRL_HIE_MASK (0x4000U) +#define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) + +#define ENC_CTRL_HIRQ_MASK (0x8000U) +#define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No transition on the HOME signal has occurred + * 0b1..A transition on the HOME signal has occurred + */ +#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ + +#define ENC_FILT_FILT_PER_MASK (0xFFU) +#define ENC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period + */ +#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) + +#define ENC_FILT_FILT_CNT_MASK (0x700U) +#define ENC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count + */ +#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) + +#define ENC_FILT_FILT_PRSC_MASK (0xE000U) +#define ENC_FILT_FILT_PRSC_SHIFT (13U) +/*! FILT_PRSC - prescaler divide IPbus clock to FILT clk + */ +#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ + +#define ENC_WTR_WDOG_MASK (0xFFFFU) +#define ENC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG + */ +#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ + +#define ENC_POSD_POSD_MASK (0xFFFFU) +#define ENC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD + */ +#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ + +#define ENC_POSDH_POSDH_MASK (0xFFFFU) +#define ENC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH + */ +#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ + +#define ENC_REV_REV_MASK (0xFFFFU) +#define ENC_REV_REV_SHIFT (0U) +/*! REV - REV + */ +#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ + +#define ENC_REVH_REVH_MASK (0xFFFFU) +#define ENC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH + */ +#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ + +#define ENC_UPOS_POS_MASK (0xFFFFU) +#define ENC_UPOS_POS_SHIFT (0U) +/*! POS - POS + */ +#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ + +#define ENC_LPOS_POS_MASK (0xFFFFU) +#define ENC_LPOS_POS_SHIFT (0U) +/*! POS - POS + */ +#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ + +#define ENC_UPOSH_POSH_MASK (0xFFFFU) +#define ENC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH + */ +#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ + +#define ENC_LPOSH_POSH_MASK (0xFFFFU) +#define ENC_LPOSH_POSH_SHIFT (0U) +/*! POSH - POSH + */ +#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ + +#define ENC_UINIT_INIT_MASK (0xFFFFU) +#define ENC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT + */ +#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ + +#define ENC_LINIT_INIT_MASK (0xFFFFU) +#define ENC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT + */ +#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ + +#define ENC_IMR_HOME_MASK (0x1U) +#define ENC_IMR_HOME_SHIFT (0U) +/*! HOME - HOME + */ +#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) + +#define ENC_IMR_INDEX_MASK (0x2U) +#define ENC_IMR_INDEX_SHIFT (1U) +/*! INDEX - INDEX + */ +#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) + +#define ENC_IMR_PHB_MASK (0x4U) +#define ENC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB + */ +#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) + +#define ENC_IMR_PHA_MASK (0x8U) +#define ENC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA + */ +#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) + +#define ENC_IMR_FHOM_MASK (0x10U) +#define ENC_IMR_FHOM_SHIFT (4U) +/*! FHOM - FHOM + */ +#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) + +#define ENC_IMR_FIND_MASK (0x20U) +#define ENC_IMR_FIND_SHIFT (5U) +/*! FIND - FIND + */ +#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) + +#define ENC_IMR_FPHB_MASK (0x40U) +#define ENC_IMR_FPHB_SHIFT (6U) +/*! FPHB - FPHB + */ +#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) + +#define ENC_IMR_FPHA_MASK (0x80U) +#define ENC_IMR_FPHA_SHIFT (7U) +/*! FPHA - FPHA + */ +#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ + +#define ENC_TST_TEST_COUNT_MASK (0xFFU) +#define ENC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT + */ +#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) + +#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) +#define ENC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD + */ +#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) + +#define ENC_TST_QDN_MASK (0x2000U) +#define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Generates a positive quadrature decoder signal + * 0b1..Generates a negative quadrature decoder signal + */ +#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) + +#define ENC_TST_TCE_MASK (0x4000U) +#define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) + +#define ENC_TST_TEN_MASK (0x8000U) +#define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define ENC_CTRL2_UPDHLD_MASK (0x1U) +#define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal + * 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal + */ +#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) + +#define ENC_CTRL2_UPDPOS_MASK (0x2U) +#define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) + +#define ENC_CTRL2_MOD_MASK (0x4U) +#define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ +#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) + +#define ENC_CTRL2_DIR_MASK (0x8U) +#define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ +#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) + +#define ENC_CTRL2_RUIE_MASK (0x10U) +#define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) + +#define ENC_CTRL2_RUIRQ_MASK (0x20U) +#define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) + +#define ENC_CTRL2_ROIE_MASK (0x40U) +#define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) + +#define ENC_CTRL2_ROIRQ_MASK (0x80U) +#define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) + +#define ENC_CTRL2_REVMOD_MASK (0x100U) +#define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV) + */ +#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) + +#define ENC_CTRL2_OUTCTL_MASK (0x200U) +#define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + */ +#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) + +#define ENC_CTRL2_SABIE_MASK (0x400U) +#define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) + +#define ENC_CTRL2_SABIRQ_MASK (0x800U) +#define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred + */ +#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ + +#define ENC_UMOD_MOD_MASK (0xFFFFU) +#define ENC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD + */ +#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ + +#define ENC_LMOD_MOD_MASK (0xFFFFU) +#define ENC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD + */ +#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ + +#define ENC_UCOMP_COMP_MASK (0xFFFFU) +#define ENC_UCOMP_COMP_SHIFT (0U) +/*! COMP - COMP + */ +#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ + +#define ENC_LCOMP_COMP_MASK (0xFFFFU) +#define ENC_LCOMP_COMP_SHIFT (0U) +/*! COMP - COMP + */ +#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time Register */ +/*! @{ */ + +#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter + */ +#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold Register */ +/*! @{ */ + +#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold + */ +#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter Register */ +/*! @{ */ + +#define ENC_POSDPER_POSDPER_MASK (0xFFFFU) +#define ENC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period + */ +#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer Register */ +/*! @{ */ + +#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer + */ +#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold Register */ +/*! @{ */ + +#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define ENC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold + */ +#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 Register */ +/*! @{ */ + +#define ENC_CTRL3_PMEN_MASK (0x1U) +#define ENC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period measurement function enable + * 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read. + * 0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read. + */ +#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK) + +#define ENC_CTRL3_PRSC_MASK (0xF0U) +#define ENC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + */ +#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ENC_Register_Masks */ + + +/* ENC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ENC0 base address */ + #define ENC0_BASE (0x500C4000u) + /** Peripheral ENC0 base address */ + #define ENC0_BASE_NS (0x400C4000u) + /** Peripheral ENC0 base pointer */ + #define ENC0 ((ENC_Type *)ENC0_BASE) + /** Peripheral ENC0 base pointer */ + #define ENC0_NS ((ENC_Type *)ENC0_BASE_NS) + /** Peripheral ENC1 base address */ + #define ENC1_BASE (0x500C6000u) + /** Peripheral ENC1 base address */ + #define ENC1_BASE_NS (0x400C6000u) + /** Peripheral ENC1 base pointer */ + #define ENC1 ((ENC_Type *)ENC1_BASE) + /** Peripheral ENC1 base pointer */ + #define ENC1_NS ((ENC_Type *)ENC1_BASE_NS) + /** Array initializer of ENC peripheral base addresses */ + #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } + /** Array initializer of ENC peripheral base pointers */ + #define ENC_BASE_PTRS { ENC0, ENC1 } + /** Array initializer of ENC peripheral base addresses */ + #define ENC_BASE_ADDRS_NS { ENC0_BASE_NS, ENC1_BASE_NS } + /** Array initializer of ENC peripheral base pointers */ + #define ENC_BASE_PTRS_NS { ENC0_NS, ENC1_NS } +#else + /** Peripheral ENC0 base address */ + #define ENC0_BASE (0x400C4000u) + /** Peripheral ENC0 base pointer */ + #define ENC0 ((ENC_Type *)ENC0_BASE) + /** Peripheral ENC1 base address */ + #define ENC1_BASE (0x400C6000u) + /** Peripheral ENC1 base pointer */ + #define ENC1 ((ENC_Type *)ENC1_BASE) + /** Array initializer of ENC peripheral base addresses */ + #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } + /** Array initializer of ENC peripheral base pointers */ + #define ENC_BASE_PTRS { ENC0, ENC1 } +#endif +/** Interrupt vectors for the ENC peripheral type */ +#define ENC_COMPARE_IRQS { ENC0_COMPARE_IRQn, ENC1_COMPARE_IRQn } +#define ENC_HOME_IRQS { ENC0_HOME_IRQn, ENC1_HOME_IRQn } +#define ENC_WDOG_IRQS { ENC0_WDG_IRQn, ENC1_WDG_IRQn } +#define ENC_INDEX_IRQS { ENC0_IDX_IRQn, ENC1_IDX_IRQn } + +/*! + * @} + */ /* end of group ENC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< Command, offset: 0x0 */ + __O uint32_t EVENT; /**< Event, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t STARTA; /**< Start address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< End address for next flash command, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[4]; /**< Data register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; + __O uint32_t INTEN_CLR; /**< Clear interrupt enables, offset: 0xFD8 */ + __O uint32_t INTEN_SET; /**< Set interrupt enables, offset: 0xFDC */ + __I uint32_t INTSTAT; /**< Interrupt status, offset: 0xFE0 */ + __I uint32_t INTEN; /**< Interrupt enable, offset: 0xFE4 */ + __O uint32_t INTSTAT_CLR; /**< Clear interrupt status, offset: 0xFE8 */ + __O uint32_t INTSTAT_SET; /**< Set interrupt status, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - Command */ +/*! @{ */ + +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. + */ +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - Event */ +/*! @{ */ + +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. + */ +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + */ +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. + */ +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name STARTA - Start address for next flash command */ +/*! @{ */ + +#define FLASH_STARTA_STARTA_MASK (0x3FFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. + */ +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - End address for next flash command */ +/*! @{ */ + +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - Data register */ +/*! @{ */ + +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +/*! DATAW - Memory data, or command parameter, or command result. + */ +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (4U) + +/*! @name INTEN_CLR - Clear interrupt enables */ +/*! @{ */ + +#define FLASH_INTEN_CLR_FAIL_MASK (0x1U) +#define FLASH_INTEN_CLR_FAIL_SHIFT (0U) +/*! FAIL - Clears the fail interrupt. + */ +#define FLASH_INTEN_CLR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_FAIL_SHIFT)) & FLASH_INTEN_CLR_FAIL_MASK) + +#define FLASH_INTEN_CLR_ERR_MASK (0x2U) +#define FLASH_INTEN_CLR_ERR_SHIFT (1U) +/*! ERR - Clears the error interrupt. + */ +#define FLASH_INTEN_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_ERR_SHIFT)) & FLASH_INTEN_CLR_ERR_MASK) + +#define FLASH_INTEN_CLR_DONE_MASK (0x4U) +#define FLASH_INTEN_CLR_DONE_SHIFT (2U) +/*! DONE - Clears the done interrupt. + */ +#define FLASH_INTEN_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_DONE_SHIFT)) & FLASH_INTEN_CLR_DONE_MASK) + +#define FLASH_INTEN_CLR_ECC_ERR_MASK (0x8U) +#define FLASH_INTEN_CLR_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - Clears the ECC error interrupt. + */ +#define FLASH_INTEN_CLR_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_ECC_ERR_SHIFT)) & FLASH_INTEN_CLR_ECC_ERR_MASK) +/*! @} */ + +/*! @name INTEN_SET - Set interrupt enables */ +/*! @{ */ + +#define FLASH_INTEN_SET_FAIL_MASK (0x1U) +#define FLASH_INTEN_SET_FAIL_SHIFT (0U) +/*! FAIL - Sets Fail interrupt. + */ +#define FLASH_INTEN_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_FAIL_SHIFT)) & FLASH_INTEN_SET_FAIL_MASK) + +#define FLASH_INTEN_SET_ERR_MASK (0x2U) +#define FLASH_INTEN_SET_ERR_SHIFT (1U) +/*! ERR - Sets error interrupt + */ +#define FLASH_INTEN_SET_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_ERR_SHIFT)) & FLASH_INTEN_SET_ERR_MASK) + +#define FLASH_INTEN_SET_DONE_MASK (0x4U) +#define FLASH_INTEN_SET_DONE_SHIFT (2U) +/*! DONE - Sets done interrupt. + */ +#define FLASH_INTEN_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_DONE_SHIFT)) & FLASH_INTEN_SET_DONE_MASK) + +#define FLASH_INTEN_SET_ECC_ERR_MASK (0x8U) +#define FLASH_INTEN_SET_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - Sets ECC error interrupt. + */ +#define FLASH_INTEN_SET_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_ECC_ERR_SHIFT)) & FLASH_INTEN_SET_ECC_ERR_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status */ +/*! @{ */ + +#define FLASH_INTSTAT_FAIL_MASK (0x1U) +#define FLASH_INTSTAT_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. + */ +#define FLASH_INTSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_FAIL_SHIFT)) & FLASH_INTSTAT_FAIL_MASK) + +#define FLASH_INTSTAT_ERR_MASK (0x2U) +#define FLASH_INTSTAT_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. + */ +#define FLASH_INTSTAT_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_ERR_SHIFT)) & FLASH_INTSTAT_ERR_MASK) + +#define FLASH_INTSTAT_DONE_MASK (0x4U) +#define FLASH_INTSTAT_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. + */ +#define FLASH_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_DONE_SHIFT)) & FLASH_INTSTAT_DONE_MASK) + +#define FLASH_INTSTAT_ECC_ERR_MASK (0x8U) +#define FLASH_INTSTAT_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ +#define FLASH_INTSTAT_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_ECC_ERR_SHIFT)) & FLASH_INTSTAT_ECC_ERR_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt enable */ +/*! @{ */ + +#define FLASH_INTEN_FAIL_MASK (0x1U) +#define FLASH_INTEN_FAIL_SHIFT (0U) +/*! FAIL - Enables fail interrupt. + */ +#define FLASH_INTEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_FAIL_SHIFT)) & FLASH_INTEN_FAIL_MASK) + +#define FLASH_INTEN_ERR_MASK (0x2U) +#define FLASH_INTEN_ERR_SHIFT (1U) +/*! ERR - Enables error interrupt. + */ +#define FLASH_INTEN_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ERR_SHIFT)) & FLASH_INTEN_ERR_MASK) + +#define FLASH_INTEN_DONE_MASK (0x4U) +#define FLASH_INTEN_DONE_SHIFT (2U) +/*! DONE - Enables done interrupt. + */ +#define FLASH_INTEN_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_DONE_SHIFT)) & FLASH_INTEN_DONE_MASK) + +#define FLASH_INTEN_ECC_ERR_MASK (0x8U) +#define FLASH_INTEN_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - Enables ECC error interrupt. + */ +#define FLASH_INTEN_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ECC_ERR_SHIFT)) & FLASH_INTEN_ECC_ERR_MASK) +/*! @} */ + +/*! @name INTSTAT_CLR - Clear interrupt status */ +/*! @{ */ + +#define FLASH_INTSTAT_CLR_FAIL_MASK (0x1U) +#define FLASH_INTSTAT_CLR_FAIL_SHIFT (0U) +/*! FAIL - Clears fail interrupt status. + */ +#define FLASH_INTSTAT_CLR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_FAIL_SHIFT)) & FLASH_INTSTAT_CLR_FAIL_MASK) + +#define FLASH_INTSTAT_CLR_ERR_MASK (0x2U) +#define FLASH_INTSTAT_CLR_ERR_SHIFT (1U) +/*! ERR - Clears error interrupt status. + */ +#define FLASH_INTSTAT_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_ERR_SHIFT)) & FLASH_INTSTAT_CLR_ERR_MASK) + +#define FLASH_INTSTAT_CLR_DONE_MASK (0x4U) +#define FLASH_INTSTAT_CLR_DONE_SHIFT (2U) +/*! DONE - Clears done interrupt status. + */ +#define FLASH_INTSTAT_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_DONE_SHIFT)) & FLASH_INTSTAT_CLR_DONE_MASK) + +#define FLASH_INTSTAT_CLR_ECC_ERR_MASK (0x8U) +#define FLASH_INTSTAT_CLR_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - Clears ECC error interrupt status. + */ +#define FLASH_INTSTAT_CLR_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_ECC_ERR_SHIFT)) & FLASH_INTSTAT_CLR_ECC_ERR_MASK) +/*! @} */ + +/*! @name INTSTAT_SET - Set interrupt status */ +/*! @{ */ + +#define FLASH_INTSTAT_SET_FAIL_MASK (0x1U) +#define FLASH_INTSTAT_SET_FAIL_SHIFT (0U) +/*! FAIL - Sets fail interrupt status. + */ +#define FLASH_INTSTAT_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_FAIL_SHIFT)) & FLASH_INTSTAT_SET_FAIL_MASK) + +#define FLASH_INTSTAT_SET_ERR_MASK (0x2U) +#define FLASH_INTSTAT_SET_ERR_SHIFT (1U) +/*! ERR - Sets error interrupt status. + */ +#define FLASH_INTSTAT_SET_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_ERR_SHIFT)) & FLASH_INTSTAT_SET_ERR_MASK) + +#define FLASH_INTSTAT_SET_DONE_MASK (0x4U) +#define FLASH_INTSTAT_SET_DONE_SHIFT (2U) +/*! DONE - Sets done interrupt status. + */ +#define FLASH_INTSTAT_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_DONE_SHIFT)) & FLASH_INTSTAT_SET_DONE_MASK) + +#define FLASH_INTSTAT_SET_ECC_ERR_MASK (0x8U) +#define FLASH_INTSTAT_SET_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - Sets ECC error interrupt status. + */ +#define FLASH_INTSTAT_SET_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_ECC_ERR_SHIFT)) & FLASH_INTSTAT_SET_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Module identification */ +/*! @{ */ + +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. + */ +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. + */ +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm module ID, offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral Identification, offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm module ID */ +/*! @{ */ + +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select + * 0b000..No peripheral selected. + * 0b001..USART function selected + * 0b010..SPI function selected + * 0b011..I2C + * 0b100..I2S Transmit + * 0b101..I2S Receive + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm module or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator + * 0b0..This Flexcomm module does not include the USART function. + * 0b1..This Flexcomm module includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator + * 0b0..This Flexcomm module does not include the SPI function. + * 0b1..This Flexcomm module includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator + * 0b0..I2C Not Present + * 0b1..I2C Present + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I2S Present + * 0b0..I2S Not Present + * 0b1..I2S Present + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID + */ +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral Identification */ +/*! @{ */ + +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +/*! Minor_Rev - Minor revision of module implementation + */ +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) + +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +/*! Major_Rev - Major revision of module implementation + */ +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) + +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function + */ +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __I uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[32]; + __IO uint32_t FLSHCR0[2]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t FLSHCR1[2]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + uint8_t RESERVED_2[8]; + __IO uint32_t FLSHCR2[2]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + uint8_t RESERVED_5[8]; + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_7[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[288]; + __IO uint32_t HADDRSTART; /**< HADDR REMAP START ADDR, offset: 0x420 */ + __IO uint32_t HADDREND; /**< HADDR REMAP END ADDR, offset: 0x424 */ + __IO uint32_t HADDROFFSET; /**< HADDR REMAP OFFSET, offset: 0x428 */ + __IO uint32_t IPEDCTRL; /**< IPED function control, offset: 0x42C */ + uint8_t RESERVED_9[208]; + __IO uint32_t IPEDCTXCTRL[2]; /**< IPED context control 0..IPED context control 1, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t IPEDCTX0IV0; /**< IPED context0 IV0, offset: 0x520 */ + __IO uint32_t IPEDCTX0IV1; /**< IPED context0 IV1, offset: 0x524 */ + __IO uint32_t IPEDCTX0START; /**< Start address of region 0, offset: 0x528 */ + __IO uint32_t IPEDCTX0END; /**< End address of region 0, offset: 0x52C */ + __IO uint32_t IPEDCTX0AAD0; /**< IPED context0 AAD0, offset: 0x530 */ + __IO uint32_t IPEDCTX0AAD1; /**< IPED context0 AAD1, offset: 0x534 */ + uint8_t RESERVED_11[8]; + __IO uint32_t IPEDCTX1IV0; /**< IPED context1 IV0, offset: 0x540 */ + __IO uint32_t IPEDCTX1IV1; /**< IPED context1 IV1, offset: 0x544 */ + __IO uint32_t IPEDCTX1START; /**< Start address of region 1, offset: 0x548 */ + __IO uint32_t IPEDCTX1END; /**< End address of region 1, offset: 0x54C */ + __IO uint32_t IPEDCTX1AAD0; /**< IPED context1 AAD0, offset: 0x550 */ + __IO uint32_t IPEDCTX1AAD1; /**< IPED context1 AAD1, offset: 0x554 */ + uint8_t RESERVED_12[8]; + __IO uint32_t IPEDCTX2IV0; /**< IPED context2 IV0, offset: 0x560 */ + __IO uint32_t IPEDCTX2IV1; /**< IPED context2 IV1, offset: 0x564 */ + __IO uint32_t IPEDCTX2START; /**< Start address of region 2, offset: 0x568 */ + __IO uint32_t IPEDCTX2END; /**< End address of region 2, offset: 0x56C */ + __IO uint32_t IPEDCTX2AAD0; /**< IPED context2 AAD0, offset: 0x570 */ + __IO uint32_t IPEDCTX2AAD1; /**< IPED context2 AAD1, offset: 0x574 */ + uint8_t RESERVED_13[8]; + __IO uint32_t IPEDCTX3IV0; /**< IPED context3 IV0, offset: 0x580 */ + __IO uint32_t IPEDCTX3IV1; /**< IPED context3 IV1, offset: 0x584 */ + __IO uint32_t IPEDCTX3START; /**< Start address of region 3, offset: 0x588 */ + __IO uint32_t IPEDCTX3END; /**< End address of region 3, offset: 0x58C */ + __IO uint32_t IPEDCTX3AAD0; /**< IPED context3 AAD0, offset: 0x590 */ + __IO uint32_t IPEDCTX3AAD1; /**< IPED context3 AAD1, offset: 0x594 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ + +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +/*! SWRESET - Software Reset + */ +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) + +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + */ +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) + +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..SCLK output clock and loopback from SCLK pad + * 0b11..Flash provided Read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) + +#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) +/*! SERCLKDIV - Serial root clock + * 0b000..Divided by 1 + * 0b001..Divided by 2 + * 0b010..Divided by 3 + * 0b011..Divided by 4 + * 0b100..Divided by 5 + * 0b101..Divided by 6 + * 0b110..Divided by 7 + * 0b111..Divided by 8 + */ +#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) + +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) + +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) + +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, + * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is + * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) + +#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) +#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) +/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is + * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction + * is correctly executed. + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) + +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +/*! IPGRANTWAIT - Timeout wait cycle for IP command grant. + */ +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) + +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. + */ +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ + +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +/*! AHBBUSWAIT - AHB Bus wait + */ +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) + +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +/*! SEQWAIT - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root + * Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated + * (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is + * ignored by arbitrator. + */ +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ + +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - Clear AHB buffer + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) + +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is + * written with 0x1. This bit will be auto-cleared immediately. + */ +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) + +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx register setting will be applied to Flash A1/A2 separately. Disabled. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2. FLSHA2CRx will be ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) + +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. + */ +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ + +#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) +#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) +/*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared. + */ +#define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) + +#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) +#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) +/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared. + */ +#define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) + +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) + +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus + * ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is + * granted by arbitrator and will not wait for AHB command finished. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) + +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +/*! PREFETCHEN - AHB Read Prefetch Enable. + */ +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) + +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in flash is word-addressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB + * burst required to meet the alignment requirement. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) + +#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) +#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) +/*! READSZALIGN - AHB Read Size Alignment + * 0b0..AHB read size will be decided by other register setting like PREFETCH_EN + * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching + */ +#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) + +#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) +#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) +/*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses. + * 0b00..No limit + * 0b01..1 KBytes + * 0b10..512 Bytes + * 0b11..256 Bytes + */ +#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) + +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) + +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. + */ +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) + +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) + +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. + */ +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) + +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. + */ +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) + +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. + */ +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) + +#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) +/*! DATALEARNFAILEN - Data Learning failed interrupt enable. + */ +#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) + +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. + */ +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) + +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. + */ +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) + +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt. + */ +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) + +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable. + */ +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) + +#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) +#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) +/*! IPCMDSECUREVIOEN - IP command security violation interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) + +#define FLEXSPI_INTEN_AHBGCMERREN_MASK (0x20000U) +#define FLEXSPI_INTEN_AHBGCMERREN_SHIFT (17U) +/*! AHBGCMERREN - AHB read gcm error interrupt enable. + */ +#define FLEXSPI_INTEN_AHBGCMERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBGCMERREN_SHIFT)) & FLEXSPI_INTEN_AHBGCMERREN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Register */ +/*! @{ */ + +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also + * generated when there is IPCMDGE or IPCMDERR interrupt generated. + */ +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) + +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. + */ +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) + +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. + */ +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) + +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for + * IP command, this command will be ignored and not executed at all. + */ +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) + +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for + * AHB command, this command will be ignored and not executed at all. + */ +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) + +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +/*! IPRXWA - IP RX FIFO watermark available interrupt. + */ +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) + +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +/*! IPTXWE - IP TX FIFO watermark empty interrupt. + */ +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) + +#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) +#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) +/*! DATALEARNFAIL - Data Learning failed interrupt. + */ +#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) + +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. + */ +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) + +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. + */ +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) + +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt. + */ +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) + +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +/*! SEQTIMEOUT - Sequence execution timeout interrupt. + */ +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) + +#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) +#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) +/*! IPCMDSECUREVIO - IP command security violation interrupt. + */ +#define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) + +#define FLEXSPI_INTR_AHBGCMERR_MASK (0x20000U) +#define FLEXSPI_INTR_AHBGCMERR_SHIFT (17U) +/*! AHBGCMERR - AHB read gcm error interrupt. + */ +#define FLEXSPI_INTR_AHBGCMERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBGCMERR_SHIFT)) & FLEXSPI_INTR_AHBGCMERR_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ + +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +/*! KEY - The Key to lock or unlock LUT. + */ +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control Register */ +/*! @{ */ + +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +/*! LOCK - Lock LUT + */ +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) + +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +/*! UNLOCK - Unlock LUT + */ +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) + +#define FLEXSPI_LUTCR_PROTECT_MASK (0x4U) +#define FLEXSPI_LUTCR_PROTECT_SHIFT (2U) +/*! PROTECT - LUT protection + */ +#define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ +/*! @{ */ + +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +/*! BUFSZ - AHB RX Buffer Size in 64 bits. + */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) + +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). + */ +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) + +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. + */ +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) + +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + */ +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) + +/*! @name FLSHCR0 - Flash Control Register 0 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +/*! FLSHSZ - Flash Size in KByte. + */ +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) + +#define FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) +#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) +/*! SPLITWREN - AHB write access split function control. + */ +#define FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) + +#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) +#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) +/*! SPLITRDEN - AHB read access split function control. + */ +#define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (2U) + +/*! @name FLSHCR1 - Flash Control Register 1 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +/*! TCSS - Serial Flash CS setup time. + */ +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) + +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +/*! TCSH - Serial Flash CS Hold time. + */ +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) + +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +/*! WA - Word Addressable. + */ +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) + +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +/*! CAS - Column Address Size. + */ +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) + +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) + +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection + * deassertion and flash device Chip selection assertion. If external flash has a limitation on + * the interval between command sequences, this field should be set accordingly. If there is no + * limitation, set this field with value 0x0. + */ +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (2U) + +/*! @name FLSHCR2 - Flash Control Register 2 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. + */ +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) + +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. + */ +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) + +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +/*! AWRSEQID - Sequence Index for AHB Write triggered Command. + */ +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) + +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. + */ +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) + +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +/*! AWRWAIT - For certain devices (such as FPGA), it need some time to write data into internal + * memory after the command sequences finished on FlexSPI interface. If another Read command sequence + * comes before previous programming finished internally, the read data may be wrong. This field + * is used to hold AHB Bus ready for AHB write access to wait the programming finished in + * external device. Then there will be no AHB read command triggered before the programming finished in + * external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI + * interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT + */ +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) + +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) + +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. + */ +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (2U) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) + +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for + * memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ + +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +/*! SFAR - Serial Flash Address for IP command. + */ +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ + +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. + */ +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) + +#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +/*! ISEQID - Sequence Index in LUT for IP command. + */ +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) + +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. + */ +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command Register */ +/*! @{ */ + +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +/*! TRG - Setting this bit will trigger an IP Command. + */ +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name DLPR - Data Learn Pattern Register */ +/*! @{ */ + +#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) +#define FLEXSPI_DLPR_DLP_SHIFT (0U) +/*! DLP - Data Learning Pattern. + */ +#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ + +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. + */ +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) + +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) + +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. + */ +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ + +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. + */ +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) + +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) + +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. + */ +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ + +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +/*! DLLEN - DLL calibration enable. + */ +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) + +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +/*! DLLRESET - DLL reset + */ +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) + +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle + * of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, + * OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended. + */ +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) + +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +/*! OVRDEN - Slave clock delay line delay cell number selection override enable. + */ +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) + +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +/*! OVRDVAL - Slave clock delay line delay cell number selection override value. + */ +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status Register 0 */ +/*! @{ */ + +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command + * sequence executing on FlexSPI interface. + */ +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) + +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command + * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state + * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So + * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. + */ +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) + +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted + * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) + +#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) +#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) +/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. + */ +#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) +/*! @} */ + +/*! @name STS1 - Status Register 1 */ +/*! @{ */ + +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field + * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + */ +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) + +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be + * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) + +#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. + */ +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) + +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be + * cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status Register 2 */ +/*! @{ */ + +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +/*! ASLVLOCK - Flash A sample clock slave delay line locked. + */ +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) + +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +/*! AREFLOCK - Flash A sample clock reference delay line locked. + */ +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) + +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . + */ +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) + +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. + */ +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ + +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. + */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) + +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +/*! BUFID - AHB RX BUF ID for suspended command sequence. + */ +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) + +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +/*! DATLFT - Left Data size for suspended command sequence (in byte). + */ +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ + +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill level of IP RX FIFO. + */ +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) + +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. + */ +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ + +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill level of IP TX FIFO. + */ +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) + +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. + */ +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ + +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +/*! RXDATA - RX Data + */ +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ + +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +/*! TXDATA - TX Data + */ +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ + +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +/*! OPERAND0 - OPERAND0 + */ +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) + +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +/*! NUM_PADS0 - NUM_PADS0 + */ +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) + +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +/*! OPCODE0 - OPCODE + */ +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) + +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +/*! OPERAND1 - OPERAND1 + */ +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) + +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +/*! NUM_PADS1 - NUM_PADS1 + */ +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) + +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +/*! OPCODE1 - OPCODE1 + */ +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + +/*! @name HADDRSTART - HADDR REMAP START ADDR */ +/*! @{ */ + +#define FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) +#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) +/*! REMAPEN - AHB Bus address remap function enable + * 0b0..HADDR REMAP Disabled + * 0b1..HADDR REMAP Enabled + */ +#define FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) + +#define FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) +#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) +/*! ADDRSTART - HADDR start address + */ +#define FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) +/*! @} */ + +/*! @name HADDREND - HADDR REMAP END ADDR */ +/*! @{ */ + +#define FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U) +#define FLEXSPI_HADDREND_ENDSTART_SHIFT (12U) +/*! ENDSTART - HADDR remap range's end addr, 4K aligned + */ +#define FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK) +/*! @} */ + +/*! @name HADDROFFSET - HADDR REMAP OFFSET */ +/*! @{ */ + +#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U) +#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U) +/*! ADDROFFSET - HADDR offset field, remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET + */ +#define FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK) +/*! @} */ + +/*! @name IPEDCTRL - IPED function control */ +/*! @{ */ + +#define FLEXSPI_IPEDCTRL_CONFIG_MASK (0x1U) +#define FLEXSPI_IPEDCTRL_CONFIG_SHIFT (0U) +/*! CONFIG - Drive IPED interface i_config. + */ +#define FLEXSPI_IPEDCTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_CONFIG_SHIFT)) & FLEXSPI_IPEDCTRL_CONFIG_MASK) + +#define FLEXSPI_IPEDCTRL_IPED_EN_MASK (0x2U) +#define FLEXSPI_IPEDCTRL_IPED_EN_SHIFT (1U) +/*! IPED_EN - Drive IPED interface i_enable + */ +#define FLEXSPI_IPEDCTRL_IPED_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_EN_MASK) + +#define FLEXSPI_IPEDCTRL_IPWR_EN_MASK (0x4U) +#define FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT (2U) +/*! IPWR_EN - IP write IPED CTR mode encryption enable + */ +#define FLEXSPI_IPEDCTRL_IPWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPWR_EN_MASK) + +#define FLEXSPI_IPEDCTRL_AHBWR_EN_MASK (0x8U) +#define FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT (3U) +/*! AHBWR_EN - AHB write IPED CTR mode encryption enable + */ +#define FLEXSPI_IPEDCTRL_AHBWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBWR_EN_MASK) + +#define FLEXSPI_IPEDCTRL_AHBRD_EN_MASK (0x10U) +#define FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT (4U) +/*! AHBRD_EN - AHB read IPED CTR mode decryption enable + */ +#define FLEXSPI_IPEDCTRL_AHBRD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBRD_EN_MASK) + +#define FLEXSPI_IPEDCTRL_IPGCMWR_MASK (0x40U) +#define FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT (6U) +/*! IPGCMWR - IP write GCM mode enable + */ +#define FLEXSPI_IPEDCTRL_IPGCMWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_IPGCMWR_MASK) + +#define FLEXSPI_IPEDCTRL_AHGCMWR_MASK (0x80U) +#define FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT (7U) +/*! AHGCMWR - AHB write IPED GCM mode encryption enable + */ +#define FLEXSPI_IPEDCTRL_AHGCMWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_AHGCMWR_MASK) + +#define FLEXSPI_IPEDCTRL_AHBGCMRD_MASK (0x100U) +#define FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT (8U) +/*! AHBGCMRD - AHB read IPED GCM mode decryption enable + */ +#define FLEXSPI_IPEDCTRL_AHBGCMRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & FLEXSPI_IPEDCTRL_AHBGCMRD_MASK) + +#define FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK (0x200U) +#define FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT (9U) +/*! IPED_PROTECT - when ipedctrl protect = 0 or priviledge access, no restriction when ipedctrl + * protect = 1, only priviledge access can write. + */ +#define FLEXSPI_IPEDCTRL_IPED_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK) + +#define FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK (0x400U) +#define FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT (10U) +/*! IPED_SWRESET - Drive IPED interface i_abort. + */ +#define FLEXSPI_IPEDCTRL_IPED_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK) +/*! @} */ + +/*! @name IPEDCTXCTRLX_IPEDCTXCTRL - IPED context control 0..IPED context control 1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK (0x3U) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT (0U) +/*! CTX0_FREEZE0 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK (0x3U) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT (0U) +/*! CTX0_FREEZE1 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK (0xCU) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT (2U) +/*! CTX1_FREEZE0 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK (0xCU) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT (2U) +/*! CTX1_FREEZE1 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK (0x30U) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT (4U) +/*! CTX2_FREEZE0 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK (0x30U) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT (4U) +/*! CTX2_FREEZE1 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK (0xC0U) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT (6U) +/*! CTX3_FREEZE0 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK) + +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK (0xC0U) +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT (6U) +/*! CTX3_FREEZE1 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx). + */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL */ +#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_COUNT (2U) + +/*! @name IPEDCTX0IV0 - IPED context0 IV0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT (0U) +/*! CTX0_IV0 - Lowest 32 bits of IV for region 0. + */ +#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT)) & FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK) +/*! @} */ + +/*! @name IPEDCTX0IV1 - IPED context0 IV1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT (0U) +/*! CTX0_IV1 - Highest 32 bits of IV for region 0. + */ +#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT)) & FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK) +/*! @} */ + +/*! @name IPEDCTX0START - Start address of region 0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX0START_GCM_MASK (0x1U) +#define FLEXSPI_IPEDCTX0START_GCM_SHIFT (0U) +/*! GCM - If this bit is 1, current region is GCM mode region. + */ +#define FLEXSPI_IPEDCTX0START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_GCM_SHIFT)) & FLEXSPI_IPEDCTX0START_GCM_MASK) + +#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK (0x2U) +#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT (1U) +/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. + */ +#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK) + +#define FLEXSPI_IPEDCTX0START_start_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX0START_start_address_SHIFT (8U) +/*! start_address - Start address of region 0. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX0START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_start_address_SHIFT)) & FLEXSPI_IPEDCTX0START_start_address_MASK) +/*! @} */ + +/*! @name IPEDCTX0END - End address of region 0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX0END_end_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX0END_end_address_SHIFT (8U) +/*! end_address - End address of region 0. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX0END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0END_end_address_SHIFT)) & FLEXSPI_IPEDCTX0END_end_address_MASK) +/*! @} */ + +/*! @name IPEDCTX0AAD0 - IPED context0 AAD0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT (0U) +/*! CTX0_AAD0 - Lowest 32 bits of AAD for region 0. + */ +#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT)) & FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK) +/*! @} */ + +/*! @name IPEDCTX0AAD1 - IPED context0 AAD1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT (0U) +/*! CTX0_AAD1 - Highest 32 bits of AAD for region 0. + */ +#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT)) & FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK) +/*! @} */ + +/*! @name IPEDCTX1IV0 - IPED context1 IV0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT (0U) +/*! CTX1_IV0 - Lowest 32 bits of IV for region 1. + */ +#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT)) & FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK) +/*! @} */ + +/*! @name IPEDCTX1IV1 - IPED context1 IV1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT (0U) +/*! CTX1_IV1 - Highest 32 bits of IV for region 1. + */ +#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT)) & FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK) +/*! @} */ + +/*! @name IPEDCTX1START - Start address of region 1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX1START_GCM_MASK (0x1U) +#define FLEXSPI_IPEDCTX1START_GCM_SHIFT (0U) +/*! GCM - If this bit is 1, current region is GCM mode region. + */ +#define FLEXSPI_IPEDCTX1START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_GCM_SHIFT)) & FLEXSPI_IPEDCTX1START_GCM_MASK) + +#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK (0x2U) +#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT (1U) +/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. + */ +#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK) + +#define FLEXSPI_IPEDCTX1START_start_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX1START_start_address_SHIFT (8U) +/*! start_address - Start address of region 1. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX1START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_start_address_SHIFT)) & FLEXSPI_IPEDCTX1START_start_address_MASK) +/*! @} */ + +/*! @name IPEDCTX1END - End address of region 1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX1END_end_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX1END_end_address_SHIFT (8U) +/*! end_address - End address of region 1. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX1END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1END_end_address_SHIFT)) & FLEXSPI_IPEDCTX1END_end_address_MASK) +/*! @} */ + +/*! @name IPEDCTX1AAD0 - IPED context1 AAD0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT (0U) +/*! CTX1_AAD0 - Lowest 32 bits of AAD for region 1. + */ +#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT)) & FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK) +/*! @} */ + +/*! @name IPEDCTX1AAD1 - IPED context1 AAD1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT (0U) +/*! CTX1_AAD1 - Highest 32 bits of AAD for region 1. + */ +#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT)) & FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK) +/*! @} */ + +/*! @name IPEDCTX2IV0 - IPED context2 IV0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT (0U) +/*! CTX2_IV0 - Lowest 32 bits of IV for region 2. + */ +#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT)) & FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK) +/*! @} */ + +/*! @name IPEDCTX2IV1 - IPED context2 IV1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT (0U) +/*! CTX2_IV1 - Highest 32 bits of IV for region 2. + */ +#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT)) & FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK) +/*! @} */ + +/*! @name IPEDCTX2START - Start address of region 2 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX2START_GCM_MASK (0x1U) +#define FLEXSPI_IPEDCTX2START_GCM_SHIFT (0U) +/*! GCM - If this bit is 1, current region is GCM mode region. + */ +#define FLEXSPI_IPEDCTX2START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_GCM_SHIFT)) & FLEXSPI_IPEDCTX2START_GCM_MASK) + +#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK (0x2U) +#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT (1U) +/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. + */ +#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK) + +#define FLEXSPI_IPEDCTX2START_start_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX2START_start_address_SHIFT (8U) +/*! start_address - Start address of region 2. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX2START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_start_address_SHIFT)) & FLEXSPI_IPEDCTX2START_start_address_MASK) +/*! @} */ + +/*! @name IPEDCTX2END - End address of region 2 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX2END_end_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX2END_end_address_SHIFT (8U) +/*! end_address - End address of region 2. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX2END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2END_end_address_SHIFT)) & FLEXSPI_IPEDCTX2END_end_address_MASK) +/*! @} */ + +/*! @name IPEDCTX2AAD0 - IPED context2 AAD0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT (0U) +/*! CTX2_AAD0 - Lowest 32 bits of AAD for region 2. + */ +#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT)) & FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK) +/*! @} */ + +/*! @name IPEDCTX2AAD1 - IPED context2 AAD1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT (0U) +/*! CTX2_AAD1 - Highest 32 bits of AAD for region 2. + */ +#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT)) & FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK) +/*! @} */ + +/*! @name IPEDCTX3IV0 - IPED context3 IV0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT (0U) +/*! CTX3_IV0 - Lowest 32 bits of IV for region 3. + */ +#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT)) & FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK) +/*! @} */ + +/*! @name IPEDCTX3IV1 - IPED context3 IV1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT (0U) +/*! CTX3_IV1 - Highest 32 bits of IV for region 3. + */ +#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT)) & FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK) +/*! @} */ + +/*! @name IPEDCTX3START - Start address of region 3 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX3START_GCM_MASK (0x1U) +#define FLEXSPI_IPEDCTX3START_GCM_SHIFT (0U) +/*! GCM - If this bit is 1, current region is GCM mode region. + */ +#define FLEXSPI_IPEDCTX3START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_GCM_SHIFT)) & FLEXSPI_IPEDCTX3START_GCM_MASK) + +#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK (0x2U) +#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT (1U) +/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable. + */ +#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK) + +#define FLEXSPI_IPEDCTX3START_start_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX3START_start_address_SHIFT (8U) +/*! start_address - Start address of region 3. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX3START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_start_address_SHIFT)) & FLEXSPI_IPEDCTX3START_start_address_MASK) +/*! @} */ + +/*! @name IPEDCTX3END - End address of region 3 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX3END_end_address_MASK (0xFFFFFF00U) +#define FLEXSPI_IPEDCTX3END_end_address_SHIFT (8U) +/*! end_address - End address of region 3. Minimal 256 Bytes aligned. It is system address. + */ +#define FLEXSPI_IPEDCTX3END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3END_end_address_SHIFT)) & FLEXSPI_IPEDCTX3END_end_address_MASK) +/*! @} */ + +/*! @name IPEDCTX3AAD0 - IPED context3 AAD0 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT (0U) +/*! CTX3_AAD0 - Lowest 32 bits of AAD for region 3. + */ +#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT)) & FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK) +/*! @} */ + +/*! @name IPEDCTX3AAD1 - IPED context3 AAD1 */ +/*! @{ */ + +#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT (0U) +/*! CTX3_AAD1 - Highest 32 bits of AAD for region 3. + */ +#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT)) & FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C0000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C0000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C0000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FlexSPI0_IRQn } +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** FlexSPI0 AMBA address */ +#define FlexSPI0_AMBA_BASE (0x18000000u) +/** FlexSPI0 AMBA address */ +#define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else +/** FlexSPI0 AMBA address */ +#define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t FREQMECTRL_R; /**< Frequency Measurement (in Read mode), offset: 0x0 */ + __O uint32_t FREQMECTRL_W; /**< Frequency Measurement (in Write mode), offset: 0x0 */ + }; + __IO uint32_t FREQMECTRLSTAT; /**< Frequency Measurement Control Status, offset: 0x4 */ + __IO uint32_t FREQMEMIN; /**< Frequency Measurement Minimum, offset: 0x8 */ + __IO uint32_t FREQMEMAX; /**< Frequency Measurement Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name FREQMECTRL_R - Frequency Measurement (in Read mode) */ +/*! @{ */ + +#define FREQME_FREQMECTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_FREQMECTRL_R_RESULT_SHIFT (0U) +/*! RESULT - Result + */ +#define FREQME_FREQMECTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_RESULT_SHIFT)) & FREQME_FREQMECTRL_R_RESULT_MASK) + +#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measure in Progress + * 0b0..Process complete. Measurement cycle is complete. The results are ready in the RESULT field. + * 0b1..In Progress. Measurement cycle is in progress. + */ +#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name FREQMECTRL_W - Frequency Measurement (in Write mode) */ +/*! @{ */ + +#define FREQME_FREQMECTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_FREQMECTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor + * 0b00000..Count cycle = 2 ^ 0 = 1 + * 0b00001..Count cycle = 2 ^ 1 = 2 + * 0b00010..Count cycle = 2 ^ 2 = 4 + * 0b11111..Count cycle = 2 ^ 31 = 2,147,483,648 + */ +#define FREQME_FREQMECTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_REF_SCALE_SHIFT)) & FREQME_FREQMECTRL_W_REF_SCALE_MASK) + +#define FREQME_FREQMECTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement mode select + * 0b0..Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the measurement starts + * (real count start is aligned at rising edge arrival on reference clock), the target counter increments by + * the target clock until the reference counter running by the reference clock reaches the count end point + * selected by REF_SCALE. + * 0b1..Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, measuring the high or + * low period of reference clock input selected by PULSE_POL. The target counter starts incrementing by the + * target clock once a corresponding trigger edge (rising edge for high period measurement and falling edge for + * low period) occurs. + */ +#define FREQME_FREQMECTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_MODE_MASK) + +#define FREQME_FREQMECTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_FREQMECTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High Period. High period of reference clock is measured in Pulse Width Measurement mode triggered by the + * rising edge on the reference clock input. + * 0b1..Low Period. Low period of reference clock is measured in Pulse Width Measurement mode triggered by the + * falling edge on the reference clock input. + */ +#define FREQME_FREQMECTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_POL_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_POL_MASK) + +#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measure in Progress + * 0b0..Force Terminate + * 0b1..Initiates Measurement Cycle + */ +#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name FREQMECTRLSTAT - Frequency Measurement Control Status */ +/*! @{ */ + +#define FREQME_FREQMECTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_FREQMECTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale Value + */ +#define FREQME_FREQMECTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_REF_SCALE_SHIFT)) & FREQME_FREQMECTRLSTAT_REF_SCALE_MASK) + +#define FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_FREQMECTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode Status + */ +#define FREQME_FREQMECTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_FREQMECTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_FREQMECTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity Status + */ +#define FREQME_FREQMECTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_PULSE_POL_SHIFT)) & FREQME_FREQMECTRLSTAT_PULSE_POL_MASK) + +#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable Status + */ +#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Then Maximum Interrupt Enable Status + */ +#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable Status + */ +#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + */ +#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + */ +#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + */ +#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + */ +#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measure in Progress Status + */ +#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name FREQMEMIN - Frequency Measurement Minimum */ +/*! @{ */ + +#define FREQME_FREQMEMIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_FREQMEMIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minumum Value + */ +#define FREQME_FREQMEMIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMEMIN_MIN_VALUE_SHIFT)) & FREQME_FREQMEMIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name FREQMEMAX - Frequency Measurement Maximum */ +/*! @{ */ + +#define FREQME_FREQMEMAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_FREQMEMAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value + */ +#define FREQME_FREQMEMAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMEMAX_MAX_VALUE_SHIFT)) & FREQME_FREQMEMAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME base address */ + #define FREQME_BASE (0x50013140u) + /** Peripheral FREQME base address */ + #define FREQME_BASE_NS (0x40013140u) + /** Peripheral FREQME base pointer */ + #define FREQME ((FREQME_Type *)FREQME_BASE) + /** Peripheral FREQME base pointer */ + #define FREQME_NS ((FREQME_Type *)FREQME_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME_NS } +#else + /** Peripheral FREQME base address */ + #define FREQME_BASE (0x40013140u) + /** Peripheral FREQME base pointer */ + #define FREQME ((FREQME_Type *)FREQME_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< Port polarity, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control */ +/*! @{ */ + +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status + * 0b0..No interrupt request is pending. + * 0b1..Interrupt request is pending. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..OR functionality + * 0b1..AND functionality + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered + * 0b1..Level-triggered + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - Port polarity */ +/*! @{ */ + +#define GINT_PORT_POL_POL0_MASK (0x1U) +#define GINT_PORT_POL_POL0_SHIFT (0U) +/*! POL0 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL0_SHIFT)) & GINT_PORT_POL_POL0_MASK) + +#define GINT_PORT_POL_POL1_MASK (0x2U) +#define GINT_PORT_POL_POL1_SHIFT (1U) +/*! POL1 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL1_SHIFT)) & GINT_PORT_POL_POL1_MASK) + +#define GINT_PORT_POL_POL2_MASK (0x4U) +#define GINT_PORT_POL_POL2_SHIFT (2U) +/*! POL2 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL2_SHIFT)) & GINT_PORT_POL_POL2_MASK) + +#define GINT_PORT_POL_POL3_MASK (0x8U) +#define GINT_PORT_POL_POL3_SHIFT (3U) +/*! POL3 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL3_SHIFT)) & GINT_PORT_POL_POL3_MASK) + +#define GINT_PORT_POL_POL4_MASK (0x10U) +#define GINT_PORT_POL_POL4_SHIFT (4U) +/*! POL4 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL4_SHIFT)) & GINT_PORT_POL_POL4_MASK) + +#define GINT_PORT_POL_POL5_MASK (0x20U) +#define GINT_PORT_POL_POL5_SHIFT (5U) +/*! POL5 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL5_SHIFT)) & GINT_PORT_POL_POL5_MASK) + +#define GINT_PORT_POL_POL6_MASK (0x40U) +#define GINT_PORT_POL_POL6_SHIFT (6U) +/*! POL6 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL6_SHIFT)) & GINT_PORT_POL_POL6_MASK) + +#define GINT_PORT_POL_POL7_MASK (0x80U) +#define GINT_PORT_POL_POL7_SHIFT (7U) +/*! POL7 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL7_SHIFT)) & GINT_PORT_POL_POL7_MASK) + +#define GINT_PORT_POL_POL8_MASK (0x100U) +#define GINT_PORT_POL_POL8_SHIFT (8U) +/*! POL8 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL8(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL8_SHIFT)) & GINT_PORT_POL_POL8_MASK) + +#define GINT_PORT_POL_POL9_MASK (0x200U) +#define GINT_PORT_POL_POL9_SHIFT (9U) +/*! POL9 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL9(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL9_SHIFT)) & GINT_PORT_POL_POL9_MASK) + +#define GINT_PORT_POL_POL10_MASK (0x400U) +#define GINT_PORT_POL_POL10_SHIFT (10U) +/*! POL10 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL10(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL10_SHIFT)) & GINT_PORT_POL_POL10_MASK) + +#define GINT_PORT_POL_POL11_MASK (0x800U) +#define GINT_PORT_POL_POL11_SHIFT (11U) +/*! POL11 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL11(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL11_SHIFT)) & GINT_PORT_POL_POL11_MASK) + +#define GINT_PORT_POL_POL12_MASK (0x1000U) +#define GINT_PORT_POL_POL12_SHIFT (12U) +/*! POL12 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL12(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL12_SHIFT)) & GINT_PORT_POL_POL12_MASK) + +#define GINT_PORT_POL_POL13_MASK (0x2000U) +#define GINT_PORT_POL_POL13_SHIFT (13U) +/*! POL13 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL13(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL13_SHIFT)) & GINT_PORT_POL_POL13_MASK) + +#define GINT_PORT_POL_POL14_MASK (0x4000U) +#define GINT_PORT_POL_POL14_SHIFT (14U) +/*! POL14 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL14(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL14_SHIFT)) & GINT_PORT_POL_POL14_MASK) + +#define GINT_PORT_POL_POL15_MASK (0x8000U) +#define GINT_PORT_POL_POL15_SHIFT (15U) +/*! POL15 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL15(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL15_SHIFT)) & GINT_PORT_POL_POL15_MASK) + +#define GINT_PORT_POL_POL16_MASK (0x10000U) +#define GINT_PORT_POL_POL16_SHIFT (16U) +/*! POL16 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL16(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL16_SHIFT)) & GINT_PORT_POL_POL16_MASK) + +#define GINT_PORT_POL_POL17_MASK (0x20000U) +#define GINT_PORT_POL_POL17_SHIFT (17U) +/*! POL17 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL17(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL17_SHIFT)) & GINT_PORT_POL_POL17_MASK) + +#define GINT_PORT_POL_POL18_MASK (0x40000U) +#define GINT_PORT_POL_POL18_SHIFT (18U) +/*! POL18 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL18(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL18_SHIFT)) & GINT_PORT_POL_POL18_MASK) + +#define GINT_PORT_POL_POL19_MASK (0x80000U) +#define GINT_PORT_POL_POL19_SHIFT (19U) +/*! POL19 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL19(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL19_SHIFT)) & GINT_PORT_POL_POL19_MASK) + +#define GINT_PORT_POL_POL20_MASK (0x100000U) +#define GINT_PORT_POL_POL20_SHIFT (20U) +/*! POL20 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL20(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL20_SHIFT)) & GINT_PORT_POL_POL20_MASK) + +#define GINT_PORT_POL_POL21_MASK (0x200000U) +#define GINT_PORT_POL_POL21_SHIFT (21U) +/*! POL21 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL21(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL21_SHIFT)) & GINT_PORT_POL_POL21_MASK) + +#define GINT_PORT_POL_POL22_MASK (0x400000U) +#define GINT_PORT_POL_POL22_SHIFT (22U) +/*! POL22 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL22(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL22_SHIFT)) & GINT_PORT_POL_POL22_MASK) + +#define GINT_PORT_POL_POL23_MASK (0x800000U) +#define GINT_PORT_POL_POL23_SHIFT (23U) +/*! POL23 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL23(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL23_SHIFT)) & GINT_PORT_POL_POL23_MASK) + +#define GINT_PORT_POL_POL24_MASK (0x1000000U) +#define GINT_PORT_POL_POL24_SHIFT (24U) +/*! POL24 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL24(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL24_SHIFT)) & GINT_PORT_POL_POL24_MASK) + +#define GINT_PORT_POL_POL25_MASK (0x2000000U) +#define GINT_PORT_POL_POL25_SHIFT (25U) +/*! POL25 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL25(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL25_SHIFT)) & GINT_PORT_POL_POL25_MASK) + +#define GINT_PORT_POL_POL26_MASK (0x4000000U) +#define GINT_PORT_POL_POL26_SHIFT (26U) +/*! POL26 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL26(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL26_SHIFT)) & GINT_PORT_POL_POL26_MASK) + +#define GINT_PORT_POL_POL27_MASK (0x8000000U) +#define GINT_PORT_POL_POL27_SHIFT (27U) +/*! POL27 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL27(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL27_SHIFT)) & GINT_PORT_POL_POL27_MASK) + +#define GINT_PORT_POL_POL28_MASK (0x10000000U) +#define GINT_PORT_POL_POL28_SHIFT (28U) +/*! POL28 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL28(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL28_SHIFT)) & GINT_PORT_POL_POL28_MASK) + +#define GINT_PORT_POL_POL29_MASK (0x20000000U) +#define GINT_PORT_POL_POL29_SHIFT (29U) +/*! POL29 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL29(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL29_SHIFT)) & GINT_PORT_POL_POL29_MASK) + +#define GINT_PORT_POL_POL30_MASK (0x40000000U) +#define GINT_PORT_POL_POL30_SHIFT (30U) +/*! POL30 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL30(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL30_SHIFT)) & GINT_PORT_POL_POL30_MASK) + +#define GINT_PORT_POL_POL31_MASK (0x80000000U) +#define GINT_PORT_POL_POL31_SHIFT (31U) +/*! POL31 - Polarity of pin n of the port + * 0b0..Pin is active LOW + * 0b1..Pin is active HIGH + */ +#define GINT_PORT_POL_POL31(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL31_SHIFT)) & GINT_PORT_POL_POL31_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ + +#define GINT_PORT_ENA_ENA0_MASK (0x1U) +#define GINT_PORT_ENA_ENA0_SHIFT (0U) +/*! ENA0 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA0(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA0_SHIFT)) & GINT_PORT_ENA_ENA0_MASK) + +#define GINT_PORT_ENA_ENA1_MASK (0x2U) +#define GINT_PORT_ENA_ENA1_SHIFT (1U) +/*! ENA1 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA1(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA1_SHIFT)) & GINT_PORT_ENA_ENA1_MASK) + +#define GINT_PORT_ENA_ENA2_MASK (0x4U) +#define GINT_PORT_ENA_ENA2_SHIFT (2U) +/*! ENA2 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA2(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA2_SHIFT)) & GINT_PORT_ENA_ENA2_MASK) + +#define GINT_PORT_ENA_ENA3_MASK (0x8U) +#define GINT_PORT_ENA_ENA3_SHIFT (3U) +/*! ENA3 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA3(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA3_SHIFT)) & GINT_PORT_ENA_ENA3_MASK) + +#define GINT_PORT_ENA_ENA4_MASK (0x10U) +#define GINT_PORT_ENA_ENA4_SHIFT (4U) +/*! ENA4 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA4(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA4_SHIFT)) & GINT_PORT_ENA_ENA4_MASK) + +#define GINT_PORT_ENA_ENA5_MASK (0x20U) +#define GINT_PORT_ENA_ENA5_SHIFT (5U) +/*! ENA5 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA5(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA5_SHIFT)) & GINT_PORT_ENA_ENA5_MASK) + +#define GINT_PORT_ENA_ENA6_MASK (0x40U) +#define GINT_PORT_ENA_ENA6_SHIFT (6U) +/*! ENA6 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA6(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA6_SHIFT)) & GINT_PORT_ENA_ENA6_MASK) + +#define GINT_PORT_ENA_ENA7_MASK (0x80U) +#define GINT_PORT_ENA_ENA7_SHIFT (7U) +/*! ENA7 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA7(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA7_SHIFT)) & GINT_PORT_ENA_ENA7_MASK) + +#define GINT_PORT_ENA_ENA8_MASK (0x100U) +#define GINT_PORT_ENA_ENA8_SHIFT (8U) +/*! ENA8 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA8(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA8_SHIFT)) & GINT_PORT_ENA_ENA8_MASK) + +#define GINT_PORT_ENA_ENA9_MASK (0x200U) +#define GINT_PORT_ENA_ENA9_SHIFT (9U) +/*! ENA9 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA9(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA9_SHIFT)) & GINT_PORT_ENA_ENA9_MASK) + +#define GINT_PORT_ENA_ENA10_MASK (0x400U) +#define GINT_PORT_ENA_ENA10_SHIFT (10U) +/*! ENA10 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA10(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA10_SHIFT)) & GINT_PORT_ENA_ENA10_MASK) + +#define GINT_PORT_ENA_ENA11_MASK (0x800U) +#define GINT_PORT_ENA_ENA11_SHIFT (11U) +/*! ENA11 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA11(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA11_SHIFT)) & GINT_PORT_ENA_ENA11_MASK) + +#define GINT_PORT_ENA_ENA12_MASK (0x1000U) +#define GINT_PORT_ENA_ENA12_SHIFT (12U) +/*! ENA12 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA12(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA12_SHIFT)) & GINT_PORT_ENA_ENA12_MASK) + +#define GINT_PORT_ENA_ENA13_MASK (0x2000U) +#define GINT_PORT_ENA_ENA13_SHIFT (13U) +/*! ENA13 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA13(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA13_SHIFT)) & GINT_PORT_ENA_ENA13_MASK) + +#define GINT_PORT_ENA_ENA14_MASK (0x4000U) +#define GINT_PORT_ENA_ENA14_SHIFT (14U) +/*! ENA14 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA14(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA14_SHIFT)) & GINT_PORT_ENA_ENA14_MASK) + +#define GINT_PORT_ENA_ENA15_MASK (0x8000U) +#define GINT_PORT_ENA_ENA15_SHIFT (15U) +/*! ENA15 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA15(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA15_SHIFT)) & GINT_PORT_ENA_ENA15_MASK) + +#define GINT_PORT_ENA_ENA16_MASK (0x10000U) +#define GINT_PORT_ENA_ENA16_SHIFT (16U) +/*! ENA16 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA16(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA16_SHIFT)) & GINT_PORT_ENA_ENA16_MASK) + +#define GINT_PORT_ENA_ENA17_MASK (0x20000U) +#define GINT_PORT_ENA_ENA17_SHIFT (17U) +/*! ENA17 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA17(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA17_SHIFT)) & GINT_PORT_ENA_ENA17_MASK) + +#define GINT_PORT_ENA_ENA18_MASK (0x40000U) +#define GINT_PORT_ENA_ENA18_SHIFT (18U) +/*! ENA18 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA18(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA18_SHIFT)) & GINT_PORT_ENA_ENA18_MASK) + +#define GINT_PORT_ENA_ENA19_MASK (0x80000U) +#define GINT_PORT_ENA_ENA19_SHIFT (19U) +/*! ENA19 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA19(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA19_SHIFT)) & GINT_PORT_ENA_ENA19_MASK) + +#define GINT_PORT_ENA_ENA20_MASK (0x100000U) +#define GINT_PORT_ENA_ENA20_SHIFT (20U) +/*! ENA20 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA20(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA20_SHIFT)) & GINT_PORT_ENA_ENA20_MASK) + +#define GINT_PORT_ENA_ENA21_MASK (0x200000U) +#define GINT_PORT_ENA_ENA21_SHIFT (21U) +/*! ENA21 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA21(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA21_SHIFT)) & GINT_PORT_ENA_ENA21_MASK) + +#define GINT_PORT_ENA_ENA22_MASK (0x400000U) +#define GINT_PORT_ENA_ENA22_SHIFT (22U) +/*! ENA22 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA22(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA22_SHIFT)) & GINT_PORT_ENA_ENA22_MASK) + +#define GINT_PORT_ENA_ENA23_MASK (0x800000U) +#define GINT_PORT_ENA_ENA23_SHIFT (23U) +/*! ENA23 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA23(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA23_SHIFT)) & GINT_PORT_ENA_ENA23_MASK) + +#define GINT_PORT_ENA_ENA24_MASK (0x1000000U) +#define GINT_PORT_ENA_ENA24_SHIFT (24U) +/*! ENA24 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA24(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA24_SHIFT)) & GINT_PORT_ENA_ENA24_MASK) + +#define GINT_PORT_ENA_ENA25_MASK (0x2000000U) +#define GINT_PORT_ENA_ENA25_SHIFT (25U) +/*! ENA25 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA25(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA25_SHIFT)) & GINT_PORT_ENA_ENA25_MASK) + +#define GINT_PORT_ENA_ENA26_MASK (0x4000000U) +#define GINT_PORT_ENA_ENA26_SHIFT (26U) +/*! ENA26 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA26(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA26_SHIFT)) & GINT_PORT_ENA_ENA26_MASK) + +#define GINT_PORT_ENA_ENA27_MASK (0x8000000U) +#define GINT_PORT_ENA_ENA27_SHIFT (27U) +/*! ENA27 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA27(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA27_SHIFT)) & GINT_PORT_ENA_ENA27_MASK) + +#define GINT_PORT_ENA_ENA28_MASK (0x10000000U) +#define GINT_PORT_ENA_ENA28_SHIFT (28U) +/*! ENA28 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA28(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA28_SHIFT)) & GINT_PORT_ENA_ENA28_MASK) + +#define GINT_PORT_ENA_ENA29_MASK (0x20000000U) +#define GINT_PORT_ENA_ENA29_SHIFT (29U) +/*! ENA29 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA29(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA29_SHIFT)) & GINT_PORT_ENA_ENA29_MASK) + +#define GINT_PORT_ENA_ENA30_MASK (0x40000000U) +#define GINT_PORT_ENA_ENA30_SHIFT (30U) +/*! ENA30 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA30(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA30_SHIFT)) & GINT_PORT_ENA_ENA30_MASK) + +#define GINT_PORT_ENA_ENA31_MASK (0x80000000U) +#define GINT_PORT_ENA_ENA31_SHIFT (31U) +/*! ENA31 - Enables port pin n to contribute to the group interrupt + * 0b0..Pin is disabled and does not contribute to the grouped interrupt + * 0b1..Pin is enabled and contributes to the grouped interrupt + */ +#define GINT_PORT_ENA_ENA31(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA31_SHIFT)) & GINT_PORT_ENA_ENA31_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[3968]; + __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3584]; + __O uint32_t DIR[4]; /**< Port direction, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[112]; + __IO uint32_t MASK[4]; /**< Port mask, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[112]; + __IO uint32_t PIN[4]; /**< Port pin, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t MPIN[4]; /**< Masked Port Pin, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[112]; + __IO uint32_t SET[4]; /**< Port set, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t CLR[4]; /**< Port clear, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __O uint32_t NOT[4]; /**< Port toggle, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __O uint32_t DIRSET[4]; /**< Port direction set, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t DIRCLR[4]; /**< Port direction clear, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __O uint32_t DIRNOT[4]; /**< Port direction toggle, array offset: 0x2480, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t INTENA[4]; /**< Interrupt A enable control, array offset: 0x2500, array step: 0x4 */ + uint8_t RESERVED_12[112]; + __IO uint32_t INTENB[4]; /**< Interrupt B enable control, array offset: 0x2580, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t INTPOL[4]; /**< Interupt polarity control, array offset: 0x2600, array step: 0x4 */ + uint8_t RESERVED_14[112]; + __IO uint32_t INTEDG[4]; /**< Interrupt edge select, array offset: 0x2680, array step: 0x4 */ + uint8_t RESERVED_15[112]; + __IO uint32_t INTSTATA[4]; /**< Interrupt status for interrupt A, array offset: 0x2700, array step: 0x4 */ + uint8_t RESERVED_16[112]; + __IO uint32_t INTSTATB[4]; /**< Interrupt status for interrupt B, array offset: 0x2780, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name BYTE_PIN_BYTE_PIN_B - Byte pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_MASK (0x1U) +#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_SHIFT (0U) +/*! PBYTE - Port Byte + */ +#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_SHIFT)) & GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_BYTE_PIN_BYTE_PIN_B */ +#define GPIO_BYTE_PIN_BYTE_PIN_B_COUNT (4U) + +/* The count of GPIO_BYTE_PIN_BYTE_PIN_B */ +#define GPIO_BYTE_PIN_BYTE_PIN_B_COUNT2 (32U) + +/*! @name WORD_PIN_WORD_PIN_W - Word pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_WORD_PIN_WORD_PIN_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_WORD_PIN_WORD_PIN_W_PWORD_SHIFT (0U) +/*! PWORD - PWORD + */ +#define GPIO_WORD_PIN_WORD_PIN_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_WORD_PIN_WORD_PIN_W_PWORD_SHIFT)) & GPIO_WORD_PIN_WORD_PIN_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_WORD_PIN_WORD_PIN_W */ +#define GPIO_WORD_PIN_WORD_PIN_W_COUNT (4U) + +/* The count of GPIO_WORD_PIN_WORD_PIN_W */ +#define GPIO_WORD_PIN_WORD_PIN_W_COUNT2 (32U) + +/*! @name DIR - Port direction */ +/*! @{ */ + +#define GPIO_DIR_DIRP0_MASK (0x1U) +#define GPIO_DIR_DIRP0_SHIFT (0U) +/*! DIRP0 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP0_SHIFT)) & GPIO_DIR_DIRP0_MASK) + +#define GPIO_DIR_DIRP1_MASK (0x2U) +#define GPIO_DIR_DIRP1_SHIFT (1U) +/*! DIRP1 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP1_SHIFT)) & GPIO_DIR_DIRP1_MASK) + +#define GPIO_DIR_DIRP2_MASK (0x4U) +#define GPIO_DIR_DIRP2_SHIFT (2U) +/*! DIRP2 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP2_SHIFT)) & GPIO_DIR_DIRP2_MASK) + +#define GPIO_DIR_DIRP3_MASK (0x8U) +#define GPIO_DIR_DIRP3_SHIFT (3U) +/*! DIRP3 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP3_SHIFT)) & GPIO_DIR_DIRP3_MASK) + +#define GPIO_DIR_DIRP4_MASK (0x10U) +#define GPIO_DIR_DIRP4_SHIFT (4U) +/*! DIRP4 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP4_SHIFT)) & GPIO_DIR_DIRP4_MASK) + +#define GPIO_DIR_DIRP5_MASK (0x20U) +#define GPIO_DIR_DIRP5_SHIFT (5U) +/*! DIRP5 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP5_SHIFT)) & GPIO_DIR_DIRP5_MASK) + +#define GPIO_DIR_DIRP6_MASK (0x40U) +#define GPIO_DIR_DIRP6_SHIFT (6U) +/*! DIRP6 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP6_SHIFT)) & GPIO_DIR_DIRP6_MASK) + +#define GPIO_DIR_DIRP7_MASK (0x80U) +#define GPIO_DIR_DIRP7_SHIFT (7U) +/*! DIRP7 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP7_SHIFT)) & GPIO_DIR_DIRP7_MASK) + +#define GPIO_DIR_DIRP8_MASK (0x100U) +#define GPIO_DIR_DIRP8_SHIFT (8U) +/*! DIRP8 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP8_SHIFT)) & GPIO_DIR_DIRP8_MASK) + +#define GPIO_DIR_DIRP9_MASK (0x200U) +#define GPIO_DIR_DIRP9_SHIFT (9U) +/*! DIRP9 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP9_SHIFT)) & GPIO_DIR_DIRP9_MASK) + +#define GPIO_DIR_DIRP10_MASK (0x400U) +#define GPIO_DIR_DIRP10_SHIFT (10U) +/*! DIRP10 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP10_SHIFT)) & GPIO_DIR_DIRP10_MASK) + +#define GPIO_DIR_DIRP11_MASK (0x800U) +#define GPIO_DIR_DIRP11_SHIFT (11U) +/*! DIRP11 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP11_SHIFT)) & GPIO_DIR_DIRP11_MASK) + +#define GPIO_DIR_DIRP12_MASK (0x1000U) +#define GPIO_DIR_DIRP12_SHIFT (12U) +/*! DIRP12 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP12_SHIFT)) & GPIO_DIR_DIRP12_MASK) + +#define GPIO_DIR_DIRP13_MASK (0x2000U) +#define GPIO_DIR_DIRP13_SHIFT (13U) +/*! DIRP13 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP13_SHIFT)) & GPIO_DIR_DIRP13_MASK) + +#define GPIO_DIR_DIRP14_MASK (0x4000U) +#define GPIO_DIR_DIRP14_SHIFT (14U) +/*! DIRP14 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP14_SHIFT)) & GPIO_DIR_DIRP14_MASK) + +#define GPIO_DIR_DIRP15_MASK (0x8000U) +#define GPIO_DIR_DIRP15_SHIFT (15U) +/*! DIRP15 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP15_SHIFT)) & GPIO_DIR_DIRP15_MASK) + +#define GPIO_DIR_DIRP16_MASK (0x10000U) +#define GPIO_DIR_DIRP16_SHIFT (16U) +/*! DIRP16 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP16_SHIFT)) & GPIO_DIR_DIRP16_MASK) + +#define GPIO_DIR_DIRP17_MASK (0x20000U) +#define GPIO_DIR_DIRP17_SHIFT (17U) +/*! DIRP17 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP17_SHIFT)) & GPIO_DIR_DIRP17_MASK) + +#define GPIO_DIR_DIRP18_MASK (0x40000U) +#define GPIO_DIR_DIRP18_SHIFT (18U) +/*! DIRP18 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP18_SHIFT)) & GPIO_DIR_DIRP18_MASK) + +#define GPIO_DIR_DIRP19_MASK (0x80000U) +#define GPIO_DIR_DIRP19_SHIFT (19U) +/*! DIRP19 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP19_SHIFT)) & GPIO_DIR_DIRP19_MASK) + +#define GPIO_DIR_DIRP20_MASK (0x100000U) +#define GPIO_DIR_DIRP20_SHIFT (20U) +/*! DIRP20 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP20_SHIFT)) & GPIO_DIR_DIRP20_MASK) + +#define GPIO_DIR_DIRP21_MASK (0x200000U) +#define GPIO_DIR_DIRP21_SHIFT (21U) +/*! DIRP21 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP21_SHIFT)) & GPIO_DIR_DIRP21_MASK) + +#define GPIO_DIR_DIRP22_MASK (0x400000U) +#define GPIO_DIR_DIRP22_SHIFT (22U) +/*! DIRP22 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP22_SHIFT)) & GPIO_DIR_DIRP22_MASK) + +#define GPIO_DIR_DIRP23_MASK (0x800000U) +#define GPIO_DIR_DIRP23_SHIFT (23U) +/*! DIRP23 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP23_SHIFT)) & GPIO_DIR_DIRP23_MASK) + +#define GPIO_DIR_DIRP24_MASK (0x1000000U) +#define GPIO_DIR_DIRP24_SHIFT (24U) +/*! DIRP24 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP24_SHIFT)) & GPIO_DIR_DIRP24_MASK) + +#define GPIO_DIR_DIRP25_MASK (0x2000000U) +#define GPIO_DIR_DIRP25_SHIFT (25U) +/*! DIRP25 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP25_SHIFT)) & GPIO_DIR_DIRP25_MASK) + +#define GPIO_DIR_DIRP26_MASK (0x4000000U) +#define GPIO_DIR_DIRP26_SHIFT (26U) +/*! DIRP26 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP26_SHIFT)) & GPIO_DIR_DIRP26_MASK) + +#define GPIO_DIR_DIRP27_MASK (0x8000000U) +#define GPIO_DIR_DIRP27_SHIFT (27U) +/*! DIRP27 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP27_SHIFT)) & GPIO_DIR_DIRP27_MASK) + +#define GPIO_DIR_DIRP28_MASK (0x10000000U) +#define GPIO_DIR_DIRP28_SHIFT (28U) +/*! DIRP28 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP28_SHIFT)) & GPIO_DIR_DIRP28_MASK) + +#define GPIO_DIR_DIRP29_MASK (0x20000000U) +#define GPIO_DIR_DIRP29_SHIFT (29U) +/*! DIRP29 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP29_SHIFT)) & GPIO_DIR_DIRP29_MASK) + +#define GPIO_DIR_DIRP30_MASK (0x40000000U) +#define GPIO_DIR_DIRP30_SHIFT (30U) +/*! DIRP30 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP30_SHIFT)) & GPIO_DIR_DIRP30_MASK) + +#define GPIO_DIR_DIRP31_MASK (0x80000000U) +#define GPIO_DIR_DIRP31_SHIFT (31U) +/*! DIRP31 - Selects pin direction for pin PIOa_b. + * 0b0..Input + * 0b1..Output + */ +#define GPIO_DIR_DIRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP31_SHIFT)) & GPIO_DIR_DIRP31_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (4U) + +/*! @name MASK - Port mask */ +/*! @{ */ + +#define GPIO_MASK_MASKP0_MASK (0x1U) +#define GPIO_MASK_MASKP0_SHIFT (0U) +/*! MASKP0 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP0_SHIFT)) & GPIO_MASK_MASKP0_MASK) + +#define GPIO_MASK_MASKP1_MASK (0x2U) +#define GPIO_MASK_MASKP1_SHIFT (1U) +/*! MASKP1 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP1_SHIFT)) & GPIO_MASK_MASKP1_MASK) + +#define GPIO_MASK_MASKP2_MASK (0x4U) +#define GPIO_MASK_MASKP2_SHIFT (2U) +/*! MASKP2 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP2_SHIFT)) & GPIO_MASK_MASKP2_MASK) + +#define GPIO_MASK_MASKP3_MASK (0x8U) +#define GPIO_MASK_MASKP3_SHIFT (3U) +/*! MASKP3 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP3_SHIFT)) & GPIO_MASK_MASKP3_MASK) + +#define GPIO_MASK_MASKP4_MASK (0x10U) +#define GPIO_MASK_MASKP4_SHIFT (4U) +/*! MASKP4 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP4_SHIFT)) & GPIO_MASK_MASKP4_MASK) + +#define GPIO_MASK_MASKP5_MASK (0x20U) +#define GPIO_MASK_MASKP5_SHIFT (5U) +/*! MASKP5 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP5_SHIFT)) & GPIO_MASK_MASKP5_MASK) + +#define GPIO_MASK_MASKP6_MASK (0x40U) +#define GPIO_MASK_MASKP6_SHIFT (6U) +/*! MASKP6 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP6_SHIFT)) & GPIO_MASK_MASKP6_MASK) + +#define GPIO_MASK_MASKP7_MASK (0x80U) +#define GPIO_MASK_MASKP7_SHIFT (7U) +/*! MASKP7 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP7_SHIFT)) & GPIO_MASK_MASKP7_MASK) + +#define GPIO_MASK_MASKP8_MASK (0x100U) +#define GPIO_MASK_MASKP8_SHIFT (8U) +/*! MASKP8 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP8_SHIFT)) & GPIO_MASK_MASKP8_MASK) + +#define GPIO_MASK_MASKP9_MASK (0x200U) +#define GPIO_MASK_MASKP9_SHIFT (9U) +/*! MASKP9 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP9_SHIFT)) & GPIO_MASK_MASKP9_MASK) + +#define GPIO_MASK_MASKP10_MASK (0x400U) +#define GPIO_MASK_MASKP10_SHIFT (10U) +/*! MASKP10 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP10_SHIFT)) & GPIO_MASK_MASKP10_MASK) + +#define GPIO_MASK_MASKP11_MASK (0x800U) +#define GPIO_MASK_MASKP11_SHIFT (11U) +/*! MASKP11 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP11_SHIFT)) & GPIO_MASK_MASKP11_MASK) + +#define GPIO_MASK_MASKP12_MASK (0x1000U) +#define GPIO_MASK_MASKP12_SHIFT (12U) +/*! MASKP12 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP12_SHIFT)) & GPIO_MASK_MASKP12_MASK) + +#define GPIO_MASK_MASKP13_MASK (0x2000U) +#define GPIO_MASK_MASKP13_SHIFT (13U) +/*! MASKP13 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP13_SHIFT)) & GPIO_MASK_MASKP13_MASK) + +#define GPIO_MASK_MASKP14_MASK (0x4000U) +#define GPIO_MASK_MASKP14_SHIFT (14U) +/*! MASKP14 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP14_SHIFT)) & GPIO_MASK_MASKP14_MASK) + +#define GPIO_MASK_MASKP15_MASK (0x8000U) +#define GPIO_MASK_MASKP15_SHIFT (15U) +/*! MASKP15 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP15_SHIFT)) & GPIO_MASK_MASKP15_MASK) + +#define GPIO_MASK_MASKP16_MASK (0x10000U) +#define GPIO_MASK_MASKP16_SHIFT (16U) +/*! MASKP16 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP16_SHIFT)) & GPIO_MASK_MASKP16_MASK) + +#define GPIO_MASK_MASKP17_MASK (0x20000U) +#define GPIO_MASK_MASKP17_SHIFT (17U) +/*! MASKP17 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP17_SHIFT)) & GPIO_MASK_MASKP17_MASK) + +#define GPIO_MASK_MASKP18_MASK (0x40000U) +#define GPIO_MASK_MASKP18_SHIFT (18U) +/*! MASKP18 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP18_SHIFT)) & GPIO_MASK_MASKP18_MASK) + +#define GPIO_MASK_MASKP19_MASK (0x80000U) +#define GPIO_MASK_MASKP19_SHIFT (19U) +/*! MASKP19 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP19_SHIFT)) & GPIO_MASK_MASKP19_MASK) + +#define GPIO_MASK_MASKP20_MASK (0x100000U) +#define GPIO_MASK_MASKP20_SHIFT (20U) +/*! MASKP20 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP20_SHIFT)) & GPIO_MASK_MASKP20_MASK) + +#define GPIO_MASK_MASKP21_MASK (0x200000U) +#define GPIO_MASK_MASKP21_SHIFT (21U) +/*! MASKP21 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP21_SHIFT)) & GPIO_MASK_MASKP21_MASK) + +#define GPIO_MASK_MASKP22_MASK (0x400000U) +#define GPIO_MASK_MASKP22_SHIFT (22U) +/*! MASKP22 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP22_SHIFT)) & GPIO_MASK_MASKP22_MASK) + +#define GPIO_MASK_MASKP23_MASK (0x800000U) +#define GPIO_MASK_MASKP23_SHIFT (23U) +/*! MASKP23 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP23_SHIFT)) & GPIO_MASK_MASKP23_MASK) + +#define GPIO_MASK_MASKP24_MASK (0x1000000U) +#define GPIO_MASK_MASKP24_SHIFT (24U) +/*! MASKP24 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP24_SHIFT)) & GPIO_MASK_MASKP24_MASK) + +#define GPIO_MASK_MASKP25_MASK (0x2000000U) +#define GPIO_MASK_MASKP25_SHIFT (25U) +/*! MASKP25 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP25_SHIFT)) & GPIO_MASK_MASKP25_MASK) + +#define GPIO_MASK_MASKP26_MASK (0x4000000U) +#define GPIO_MASK_MASKP26_SHIFT (26U) +/*! MASKP26 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP26_SHIFT)) & GPIO_MASK_MASKP26_MASK) + +#define GPIO_MASK_MASKP27_MASK (0x8000000U) +#define GPIO_MASK_MASKP27_SHIFT (27U) +/*! MASKP27 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP27_SHIFT)) & GPIO_MASK_MASKP27_MASK) + +#define GPIO_MASK_MASKP28_MASK (0x10000000U) +#define GPIO_MASK_MASKP28_SHIFT (28U) +/*! MASKP28 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP28_SHIFT)) & GPIO_MASK_MASKP28_MASK) + +#define GPIO_MASK_MASKP29_MASK (0x20000000U) +#define GPIO_MASK_MASKP29_SHIFT (29U) +/*! MASKP29 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP29_SHIFT)) & GPIO_MASK_MASKP29_MASK) + +#define GPIO_MASK_MASKP30_MASK (0x40000000U) +#define GPIO_MASK_MASKP30_SHIFT (30U) +/*! MASKP30 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP30_SHIFT)) & GPIO_MASK_MASKP30_MASK) + +#define GPIO_MASK_MASKP31_MASK (0x80000000U) +#define GPIO_MASK_MASKP31_SHIFT (31U) +/*! MASKP31 - Port Mask + * 0b0..Read MPIN: pin state; write MPIN: load output bit + * 0b1..Read MPIN: 0; write MPIN: output bit not affected + */ +#define GPIO_MASK_MASKP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP31_SHIFT)) & GPIO_MASK_MASKP31_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (4U) + +/*! @name PIN - Port pin */ +/*! @{ */ + +#define GPIO_PIN_PORT0_MASK (0x1U) +#define GPIO_PIN_PORT0_SHIFT (0U) +/*! PORT0 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT0_SHIFT)) & GPIO_PIN_PORT0_MASK) + +#define GPIO_PIN_PORT1_MASK (0x2U) +#define GPIO_PIN_PORT1_SHIFT (1U) +/*! PORT1 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT1_SHIFT)) & GPIO_PIN_PORT1_MASK) + +#define GPIO_PIN_PORT2_MASK (0x4U) +#define GPIO_PIN_PORT2_SHIFT (2U) +/*! PORT2 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT2_SHIFT)) & GPIO_PIN_PORT2_MASK) + +#define GPIO_PIN_PORT3_MASK (0x8U) +#define GPIO_PIN_PORT3_SHIFT (3U) +/*! PORT3 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT3_SHIFT)) & GPIO_PIN_PORT3_MASK) + +#define GPIO_PIN_PORT4_MASK (0x10U) +#define GPIO_PIN_PORT4_SHIFT (4U) +/*! PORT4 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT4_SHIFT)) & GPIO_PIN_PORT4_MASK) + +#define GPIO_PIN_PORT5_MASK (0x20U) +#define GPIO_PIN_PORT5_SHIFT (5U) +/*! PORT5 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT5_SHIFT)) & GPIO_PIN_PORT5_MASK) + +#define GPIO_PIN_PORT6_MASK (0x40U) +#define GPIO_PIN_PORT6_SHIFT (6U) +/*! PORT6 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT6_SHIFT)) & GPIO_PIN_PORT6_MASK) + +#define GPIO_PIN_PORT7_MASK (0x80U) +#define GPIO_PIN_PORT7_SHIFT (7U) +/*! PORT7 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT7_SHIFT)) & GPIO_PIN_PORT7_MASK) + +#define GPIO_PIN_PORT8_MASK (0x100U) +#define GPIO_PIN_PORT8_SHIFT (8U) +/*! PORT8 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT8_SHIFT)) & GPIO_PIN_PORT8_MASK) + +#define GPIO_PIN_PORT9_MASK (0x200U) +#define GPIO_PIN_PORT9_SHIFT (9U) +/*! PORT9 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT9_SHIFT)) & GPIO_PIN_PORT9_MASK) + +#define GPIO_PIN_PORT10_MASK (0x400U) +#define GPIO_PIN_PORT10_SHIFT (10U) +/*! PORT10 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT10_SHIFT)) & GPIO_PIN_PORT10_MASK) + +#define GPIO_PIN_PORT11_MASK (0x800U) +#define GPIO_PIN_PORT11_SHIFT (11U) +/*! PORT11 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT11_SHIFT)) & GPIO_PIN_PORT11_MASK) + +#define GPIO_PIN_PORT12_MASK (0x1000U) +#define GPIO_PIN_PORT12_SHIFT (12U) +/*! PORT12 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT12_SHIFT)) & GPIO_PIN_PORT12_MASK) + +#define GPIO_PIN_PORT13_MASK (0x2000U) +#define GPIO_PIN_PORT13_SHIFT (13U) +/*! PORT13 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT13_SHIFT)) & GPIO_PIN_PORT13_MASK) + +#define GPIO_PIN_PORT14_MASK (0x4000U) +#define GPIO_PIN_PORT14_SHIFT (14U) +/*! PORT14 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT14_SHIFT)) & GPIO_PIN_PORT14_MASK) + +#define GPIO_PIN_PORT15_MASK (0x8000U) +#define GPIO_PIN_PORT15_SHIFT (15U) +/*! PORT15 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT15_SHIFT)) & GPIO_PIN_PORT15_MASK) + +#define GPIO_PIN_PORT16_MASK (0x10000U) +#define GPIO_PIN_PORT16_SHIFT (16U) +/*! PORT16 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT16_SHIFT)) & GPIO_PIN_PORT16_MASK) + +#define GPIO_PIN_PORT17_MASK (0x20000U) +#define GPIO_PIN_PORT17_SHIFT (17U) +/*! PORT17 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT17_SHIFT)) & GPIO_PIN_PORT17_MASK) + +#define GPIO_PIN_PORT18_MASK (0x40000U) +#define GPIO_PIN_PORT18_SHIFT (18U) +/*! PORT18 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT18_SHIFT)) & GPIO_PIN_PORT18_MASK) + +#define GPIO_PIN_PORT19_MASK (0x80000U) +#define GPIO_PIN_PORT19_SHIFT (19U) +/*! PORT19 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT19_SHIFT)) & GPIO_PIN_PORT19_MASK) + +#define GPIO_PIN_PORT20_MASK (0x100000U) +#define GPIO_PIN_PORT20_SHIFT (20U) +/*! PORT20 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT20_SHIFT)) & GPIO_PIN_PORT20_MASK) + +#define GPIO_PIN_PORT21_MASK (0x200000U) +#define GPIO_PIN_PORT21_SHIFT (21U) +/*! PORT21 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT21_SHIFT)) & GPIO_PIN_PORT21_MASK) + +#define GPIO_PIN_PORT22_MASK (0x400000U) +#define GPIO_PIN_PORT22_SHIFT (22U) +/*! PORT22 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT22_SHIFT)) & GPIO_PIN_PORT22_MASK) + +#define GPIO_PIN_PORT23_MASK (0x800000U) +#define GPIO_PIN_PORT23_SHIFT (23U) +/*! PORT23 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT23_SHIFT)) & GPIO_PIN_PORT23_MASK) + +#define GPIO_PIN_PORT24_MASK (0x1000000U) +#define GPIO_PIN_PORT24_SHIFT (24U) +/*! PORT24 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT24_SHIFT)) & GPIO_PIN_PORT24_MASK) + +#define GPIO_PIN_PORT25_MASK (0x2000000U) +#define GPIO_PIN_PORT25_SHIFT (25U) +/*! PORT25 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT25_SHIFT)) & GPIO_PIN_PORT25_MASK) + +#define GPIO_PIN_PORT26_MASK (0x4000000U) +#define GPIO_PIN_PORT26_SHIFT (26U) +/*! PORT26 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT26_SHIFT)) & GPIO_PIN_PORT26_MASK) + +#define GPIO_PIN_PORT27_MASK (0x8000000U) +#define GPIO_PIN_PORT27_SHIFT (27U) +/*! PORT27 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT27_SHIFT)) & GPIO_PIN_PORT27_MASK) + +#define GPIO_PIN_PORT28_MASK (0x10000000U) +#define GPIO_PIN_PORT28_SHIFT (28U) +/*! PORT28 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT28_SHIFT)) & GPIO_PIN_PORT28_MASK) + +#define GPIO_PIN_PORT29_MASK (0x20000000U) +#define GPIO_PIN_PORT29_SHIFT (29U) +/*! PORT29 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT29_SHIFT)) & GPIO_PIN_PORT29_MASK) + +#define GPIO_PIN_PORT30_MASK (0x40000000U) +#define GPIO_PIN_PORT30_SHIFT (30U) +/*! PORT30 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT30_SHIFT)) & GPIO_PIN_PORT30_MASK) + +#define GPIO_PIN_PORT31_MASK (0x80000000U) +#define GPIO_PIN_PORT31_SHIFT (31U) +/*! PORT31 - Port pins + * 0b0..Read- pin is low; Write- clear output bit + * 0b1..Read- pin is high; Write- set output bit + */ +#define GPIO_PIN_PORT31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT31_SHIFT)) & GPIO_PIN_PORT31_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (4U) + +/*! @name MPIN - Masked Port Pin */ +/*! @{ */ + +#define GPIO_MPIN_MPORTP0_MASK (0x1U) +#define GPIO_MPIN_MPORTP0_SHIFT (0U) +/*! MPORTP0 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP0_SHIFT)) & GPIO_MPIN_MPORTP0_MASK) + +#define GPIO_MPIN_MPORTP1_MASK (0x2U) +#define GPIO_MPIN_MPORTP1_SHIFT (1U) +/*! MPORTP1 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP1_SHIFT)) & GPIO_MPIN_MPORTP1_MASK) + +#define GPIO_MPIN_MPORTP2_MASK (0x4U) +#define GPIO_MPIN_MPORTP2_SHIFT (2U) +/*! MPORTP2 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP2_SHIFT)) & GPIO_MPIN_MPORTP2_MASK) + +#define GPIO_MPIN_MPORTP3_MASK (0x8U) +#define GPIO_MPIN_MPORTP3_SHIFT (3U) +/*! MPORTP3 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP3_SHIFT)) & GPIO_MPIN_MPORTP3_MASK) + +#define GPIO_MPIN_MPORTP4_MASK (0x10U) +#define GPIO_MPIN_MPORTP4_SHIFT (4U) +/*! MPORTP4 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP4_SHIFT)) & GPIO_MPIN_MPORTP4_MASK) + +#define GPIO_MPIN_MPORTP5_MASK (0x20U) +#define GPIO_MPIN_MPORTP5_SHIFT (5U) +/*! MPORTP5 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP5_SHIFT)) & GPIO_MPIN_MPORTP5_MASK) + +#define GPIO_MPIN_MPORTP6_MASK (0x40U) +#define GPIO_MPIN_MPORTP6_SHIFT (6U) +/*! MPORTP6 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP6_SHIFT)) & GPIO_MPIN_MPORTP6_MASK) + +#define GPIO_MPIN_MPORTP7_MASK (0x80U) +#define GPIO_MPIN_MPORTP7_SHIFT (7U) +/*! MPORTP7 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP7_SHIFT)) & GPIO_MPIN_MPORTP7_MASK) + +#define GPIO_MPIN_MPORTP8_MASK (0x100U) +#define GPIO_MPIN_MPORTP8_SHIFT (8U) +/*! MPORTP8 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP8_SHIFT)) & GPIO_MPIN_MPORTP8_MASK) + +#define GPIO_MPIN_MPORTP9_MASK (0x200U) +#define GPIO_MPIN_MPORTP9_SHIFT (9U) +/*! MPORTP9 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP9_SHIFT)) & GPIO_MPIN_MPORTP9_MASK) + +#define GPIO_MPIN_MPORTP10_MASK (0x400U) +#define GPIO_MPIN_MPORTP10_SHIFT (10U) +/*! MPORTP10 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP10_SHIFT)) & GPIO_MPIN_MPORTP10_MASK) + +#define GPIO_MPIN_MPORTP11_MASK (0x800U) +#define GPIO_MPIN_MPORTP11_SHIFT (11U) +/*! MPORTP11 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP11_SHIFT)) & GPIO_MPIN_MPORTP11_MASK) + +#define GPIO_MPIN_MPORTP12_MASK (0x1000U) +#define GPIO_MPIN_MPORTP12_SHIFT (12U) +/*! MPORTP12 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP12_SHIFT)) & GPIO_MPIN_MPORTP12_MASK) + +#define GPIO_MPIN_MPORTP13_MASK (0x2000U) +#define GPIO_MPIN_MPORTP13_SHIFT (13U) +/*! MPORTP13 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP13_SHIFT)) & GPIO_MPIN_MPORTP13_MASK) + +#define GPIO_MPIN_MPORTP14_MASK (0x4000U) +#define GPIO_MPIN_MPORTP14_SHIFT (14U) +/*! MPORTP14 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP14_SHIFT)) & GPIO_MPIN_MPORTP14_MASK) + +#define GPIO_MPIN_MPORTP15_MASK (0x8000U) +#define GPIO_MPIN_MPORTP15_SHIFT (15U) +/*! MPORTP15 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP15_SHIFT)) & GPIO_MPIN_MPORTP15_MASK) + +#define GPIO_MPIN_MPORTP16_MASK (0x10000U) +#define GPIO_MPIN_MPORTP16_SHIFT (16U) +/*! MPORTP16 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP16_SHIFT)) & GPIO_MPIN_MPORTP16_MASK) + +#define GPIO_MPIN_MPORTP17_MASK (0x20000U) +#define GPIO_MPIN_MPORTP17_SHIFT (17U) +/*! MPORTP17 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP17_SHIFT)) & GPIO_MPIN_MPORTP17_MASK) + +#define GPIO_MPIN_MPORTP18_MASK (0x40000U) +#define GPIO_MPIN_MPORTP18_SHIFT (18U) +/*! MPORTP18 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP18_SHIFT)) & GPIO_MPIN_MPORTP18_MASK) + +#define GPIO_MPIN_MPORTP19_MASK (0x80000U) +#define GPIO_MPIN_MPORTP19_SHIFT (19U) +/*! MPORTP19 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP19_SHIFT)) & GPIO_MPIN_MPORTP19_MASK) + +#define GPIO_MPIN_MPORTP20_MASK (0x100000U) +#define GPIO_MPIN_MPORTP20_SHIFT (20U) +/*! MPORTP20 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP20_SHIFT)) & GPIO_MPIN_MPORTP20_MASK) + +#define GPIO_MPIN_MPORTP21_MASK (0x200000U) +#define GPIO_MPIN_MPORTP21_SHIFT (21U) +/*! MPORTP21 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP21_SHIFT)) & GPIO_MPIN_MPORTP21_MASK) + +#define GPIO_MPIN_MPORTP22_MASK (0x400000U) +#define GPIO_MPIN_MPORTP22_SHIFT (22U) +/*! MPORTP22 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP22_SHIFT)) & GPIO_MPIN_MPORTP22_MASK) + +#define GPIO_MPIN_MPORTP23_MASK (0x800000U) +#define GPIO_MPIN_MPORTP23_SHIFT (23U) +/*! MPORTP23 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP23_SHIFT)) & GPIO_MPIN_MPORTP23_MASK) + +#define GPIO_MPIN_MPORTP24_MASK (0x1000000U) +#define GPIO_MPIN_MPORTP24_SHIFT (24U) +/*! MPORTP24 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP24_SHIFT)) & GPIO_MPIN_MPORTP24_MASK) + +#define GPIO_MPIN_MPORTP25_MASK (0x2000000U) +#define GPIO_MPIN_MPORTP25_SHIFT (25U) +/*! MPORTP25 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP25_SHIFT)) & GPIO_MPIN_MPORTP25_MASK) + +#define GPIO_MPIN_MPORTP26_MASK (0x4000000U) +#define GPIO_MPIN_MPORTP26_SHIFT (26U) +/*! MPORTP26 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP26_SHIFT)) & GPIO_MPIN_MPORTP26_MASK) + +#define GPIO_MPIN_MPORTP27_MASK (0x8000000U) +#define GPIO_MPIN_MPORTP27_SHIFT (27U) +/*! MPORTP27 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP27_SHIFT)) & GPIO_MPIN_MPORTP27_MASK) + +#define GPIO_MPIN_MPORTP28_MASK (0x10000000U) +#define GPIO_MPIN_MPORTP28_SHIFT (28U) +/*! MPORTP28 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP28_SHIFT)) & GPIO_MPIN_MPORTP28_MASK) + +#define GPIO_MPIN_MPORTP29_MASK (0x20000000U) +#define GPIO_MPIN_MPORTP29_SHIFT (29U) +/*! MPORTP29 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP29_SHIFT)) & GPIO_MPIN_MPORTP29_MASK) + +#define GPIO_MPIN_MPORTP30_MASK (0x40000000U) +#define GPIO_MPIN_MPORTP30_SHIFT (30U) +/*! MPORTP30 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP30_SHIFT)) & GPIO_MPIN_MPORTP30_MASK) + +#define GPIO_MPIN_MPORTP31_MASK (0x80000000U) +#define GPIO_MPIN_MPORTP31_SHIFT (31U) +/*! MPORTP31 - Mask bits for port pins + * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the + * corresponding bit in the MASK register is 0 + * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the + * corresponding bit in the MASK register is 0 + */ +#define GPIO_MPIN_MPORTP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP31_SHIFT)) & GPIO_MPIN_MPORTP31_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (4U) + +/*! @name SET - Port set */ +/*! @{ */ + +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits + * 0b00000000000000000000000000000000..Read- output bit; write- no operation + * 0b00000000000000000000000000000001..Read- output bit; write- set output bit + */ +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (4U) + +/*! @name CLR - Port clear */ +/*! @{ */ + +#define GPIO_CLR_CLRP0_MASK (0x1U) +#define GPIO_CLR_CLRP0_SHIFT (0U) +/*! CLRP0 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP0_SHIFT)) & GPIO_CLR_CLRP0_MASK) + +#define GPIO_CLR_CLRP1_MASK (0x2U) +#define GPIO_CLR_CLRP1_SHIFT (1U) +/*! CLRP1 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP1_SHIFT)) & GPIO_CLR_CLRP1_MASK) + +#define GPIO_CLR_CLRP2_MASK (0x4U) +#define GPIO_CLR_CLRP2_SHIFT (2U) +/*! CLRP2 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP2_SHIFT)) & GPIO_CLR_CLRP2_MASK) + +#define GPIO_CLR_CLRP3_MASK (0x8U) +#define GPIO_CLR_CLRP3_SHIFT (3U) +/*! CLRP3 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP3_SHIFT)) & GPIO_CLR_CLRP3_MASK) + +#define GPIO_CLR_CLRP4_MASK (0x10U) +#define GPIO_CLR_CLRP4_SHIFT (4U) +/*! CLRP4 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP4_SHIFT)) & GPIO_CLR_CLRP4_MASK) + +#define GPIO_CLR_CLRP5_MASK (0x20U) +#define GPIO_CLR_CLRP5_SHIFT (5U) +/*! CLRP5 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP5_SHIFT)) & GPIO_CLR_CLRP5_MASK) + +#define GPIO_CLR_CLRP6_MASK (0x40U) +#define GPIO_CLR_CLRP6_SHIFT (6U) +/*! CLRP6 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP6_SHIFT)) & GPIO_CLR_CLRP6_MASK) + +#define GPIO_CLR_CLRP7_MASK (0x80U) +#define GPIO_CLR_CLRP7_SHIFT (7U) +/*! CLRP7 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP7_SHIFT)) & GPIO_CLR_CLRP7_MASK) + +#define GPIO_CLR_CLRP8_MASK (0x100U) +#define GPIO_CLR_CLRP8_SHIFT (8U) +/*! CLRP8 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP8_SHIFT)) & GPIO_CLR_CLRP8_MASK) + +#define GPIO_CLR_CLRP9_MASK (0x200U) +#define GPIO_CLR_CLRP9_SHIFT (9U) +/*! CLRP9 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP9_SHIFT)) & GPIO_CLR_CLRP9_MASK) + +#define GPIO_CLR_CLRP10_MASK (0x400U) +#define GPIO_CLR_CLRP10_SHIFT (10U) +/*! CLRP10 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP10_SHIFT)) & GPIO_CLR_CLRP10_MASK) + +#define GPIO_CLR_CLRP11_MASK (0x800U) +#define GPIO_CLR_CLRP11_SHIFT (11U) +/*! CLRP11 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP11_SHIFT)) & GPIO_CLR_CLRP11_MASK) + +#define GPIO_CLR_CLRP12_MASK (0x1000U) +#define GPIO_CLR_CLRP12_SHIFT (12U) +/*! CLRP12 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP12_SHIFT)) & GPIO_CLR_CLRP12_MASK) + +#define GPIO_CLR_CLRP13_MASK (0x2000U) +#define GPIO_CLR_CLRP13_SHIFT (13U) +/*! CLRP13 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP13_SHIFT)) & GPIO_CLR_CLRP13_MASK) + +#define GPIO_CLR_CLRP14_MASK (0x4000U) +#define GPIO_CLR_CLRP14_SHIFT (14U) +/*! CLRP14 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP14_SHIFT)) & GPIO_CLR_CLRP14_MASK) + +#define GPIO_CLR_CLRP15_MASK (0x8000U) +#define GPIO_CLR_CLRP15_SHIFT (15U) +/*! CLRP15 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP15_SHIFT)) & GPIO_CLR_CLRP15_MASK) + +#define GPIO_CLR_CLRP16_MASK (0x10000U) +#define GPIO_CLR_CLRP16_SHIFT (16U) +/*! CLRP16 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP16_SHIFT)) & GPIO_CLR_CLRP16_MASK) + +#define GPIO_CLR_CLRP17_MASK (0x20000U) +#define GPIO_CLR_CLRP17_SHIFT (17U) +/*! CLRP17 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP17_SHIFT)) & GPIO_CLR_CLRP17_MASK) + +#define GPIO_CLR_CLRP18_MASK (0x40000U) +#define GPIO_CLR_CLRP18_SHIFT (18U) +/*! CLRP18 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP18_SHIFT)) & GPIO_CLR_CLRP18_MASK) + +#define GPIO_CLR_CLRP19_MASK (0x80000U) +#define GPIO_CLR_CLRP19_SHIFT (19U) +/*! CLRP19 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP19_SHIFT)) & GPIO_CLR_CLRP19_MASK) + +#define GPIO_CLR_CLRP20_MASK (0x100000U) +#define GPIO_CLR_CLRP20_SHIFT (20U) +/*! CLRP20 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP20_SHIFT)) & GPIO_CLR_CLRP20_MASK) + +#define GPIO_CLR_CLRP21_MASK (0x200000U) +#define GPIO_CLR_CLRP21_SHIFT (21U) +/*! CLRP21 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP21_SHIFT)) & GPIO_CLR_CLRP21_MASK) + +#define GPIO_CLR_CLRP22_MASK (0x400000U) +#define GPIO_CLR_CLRP22_SHIFT (22U) +/*! CLRP22 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP22_SHIFT)) & GPIO_CLR_CLRP22_MASK) + +#define GPIO_CLR_CLRP23_MASK (0x800000U) +#define GPIO_CLR_CLRP23_SHIFT (23U) +/*! CLRP23 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP23_SHIFT)) & GPIO_CLR_CLRP23_MASK) + +#define GPIO_CLR_CLRP24_MASK (0x1000000U) +#define GPIO_CLR_CLRP24_SHIFT (24U) +/*! CLRP24 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP24_SHIFT)) & GPIO_CLR_CLRP24_MASK) + +#define GPIO_CLR_CLRP25_MASK (0x2000000U) +#define GPIO_CLR_CLRP25_SHIFT (25U) +/*! CLRP25 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP25_SHIFT)) & GPIO_CLR_CLRP25_MASK) + +#define GPIO_CLR_CLRP26_MASK (0x4000000U) +#define GPIO_CLR_CLRP26_SHIFT (26U) +/*! CLRP26 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP26_SHIFT)) & GPIO_CLR_CLRP26_MASK) + +#define GPIO_CLR_CLRP27_MASK (0x8000000U) +#define GPIO_CLR_CLRP27_SHIFT (27U) +/*! CLRP27 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP27_SHIFT)) & GPIO_CLR_CLRP27_MASK) + +#define GPIO_CLR_CLRP28_MASK (0x10000000U) +#define GPIO_CLR_CLRP28_SHIFT (28U) +/*! CLRP28 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP28_SHIFT)) & GPIO_CLR_CLRP28_MASK) + +#define GPIO_CLR_CLRP29_MASK (0x20000000U) +#define GPIO_CLR_CLRP29_SHIFT (29U) +/*! CLRP29 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP29_SHIFT)) & GPIO_CLR_CLRP29_MASK) + +#define GPIO_CLR_CLRP30_MASK (0x40000000U) +#define GPIO_CLR_CLRP30_SHIFT (30U) +/*! CLRP30 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP30_SHIFT)) & GPIO_CLR_CLRP30_MASK) + +#define GPIO_CLR_CLRP31_MASK (0x80000000U) +#define GPIO_CLR_CLRP31_SHIFT (31U) +/*! CLRP31 - Clear output bits + * 0b0..No operation + * 0b1..Clears output bit + */ +#define GPIO_CLR_CLRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP31_SHIFT)) & GPIO_CLR_CLRP31_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (4U) + +/*! @name NOT - Port toggle */ +/*! @{ */ + +#define GPIO_NOT_NOTP0_MASK (0x1U) +#define GPIO_NOT_NOTP0_SHIFT (0U) +/*! NOTP0 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP0_SHIFT)) & GPIO_NOT_NOTP0_MASK) + +#define GPIO_NOT_NOTP1_MASK (0x2U) +#define GPIO_NOT_NOTP1_SHIFT (1U) +/*! NOTP1 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP1_SHIFT)) & GPIO_NOT_NOTP1_MASK) + +#define GPIO_NOT_NOTP2_MASK (0x4U) +#define GPIO_NOT_NOTP2_SHIFT (2U) +/*! NOTP2 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP2_SHIFT)) & GPIO_NOT_NOTP2_MASK) + +#define GPIO_NOT_NOTP3_MASK (0x8U) +#define GPIO_NOT_NOTP3_SHIFT (3U) +/*! NOTP3 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP3_SHIFT)) & GPIO_NOT_NOTP3_MASK) + +#define GPIO_NOT_NOTP4_MASK (0x10U) +#define GPIO_NOT_NOTP4_SHIFT (4U) +/*! NOTP4 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP4_SHIFT)) & GPIO_NOT_NOTP4_MASK) + +#define GPIO_NOT_NOTP5_MASK (0x20U) +#define GPIO_NOT_NOTP5_SHIFT (5U) +/*! NOTP5 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP5_SHIFT)) & GPIO_NOT_NOTP5_MASK) + +#define GPIO_NOT_NOTP6_MASK (0x40U) +#define GPIO_NOT_NOTP6_SHIFT (6U) +/*! NOTP6 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP6_SHIFT)) & GPIO_NOT_NOTP6_MASK) + +#define GPIO_NOT_NOTP7_MASK (0x80U) +#define GPIO_NOT_NOTP7_SHIFT (7U) +/*! NOTP7 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP7_SHIFT)) & GPIO_NOT_NOTP7_MASK) + +#define GPIO_NOT_NOTP8_MASK (0x100U) +#define GPIO_NOT_NOTP8_SHIFT (8U) +/*! NOTP8 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP8_SHIFT)) & GPIO_NOT_NOTP8_MASK) + +#define GPIO_NOT_NOTP9_MASK (0x200U) +#define GPIO_NOT_NOTP9_SHIFT (9U) +/*! NOTP9 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP9_SHIFT)) & GPIO_NOT_NOTP9_MASK) + +#define GPIO_NOT_NOTP10_MASK (0x400U) +#define GPIO_NOT_NOTP10_SHIFT (10U) +/*! NOTP10 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP10_SHIFT)) & GPIO_NOT_NOTP10_MASK) + +#define GPIO_NOT_NOTP11_MASK (0x800U) +#define GPIO_NOT_NOTP11_SHIFT (11U) +/*! NOTP11 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP11_SHIFT)) & GPIO_NOT_NOTP11_MASK) + +#define GPIO_NOT_NOTP12_MASK (0x1000U) +#define GPIO_NOT_NOTP12_SHIFT (12U) +/*! NOTP12 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP12_SHIFT)) & GPIO_NOT_NOTP12_MASK) + +#define GPIO_NOT_NOTP13_MASK (0x2000U) +#define GPIO_NOT_NOTP13_SHIFT (13U) +/*! NOTP13 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP13_SHIFT)) & GPIO_NOT_NOTP13_MASK) + +#define GPIO_NOT_NOTP14_MASK (0x4000U) +#define GPIO_NOT_NOTP14_SHIFT (14U) +/*! NOTP14 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP14_SHIFT)) & GPIO_NOT_NOTP14_MASK) + +#define GPIO_NOT_NOTP15_MASK (0x8000U) +#define GPIO_NOT_NOTP15_SHIFT (15U) +/*! NOTP15 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP15_SHIFT)) & GPIO_NOT_NOTP15_MASK) + +#define GPIO_NOT_NOTP16_MASK (0x10000U) +#define GPIO_NOT_NOTP16_SHIFT (16U) +/*! NOTP16 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP16_SHIFT)) & GPIO_NOT_NOTP16_MASK) + +#define GPIO_NOT_NOTP17_MASK (0x20000U) +#define GPIO_NOT_NOTP17_SHIFT (17U) +/*! NOTP17 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP17_SHIFT)) & GPIO_NOT_NOTP17_MASK) + +#define GPIO_NOT_NOTP18_MASK (0x40000U) +#define GPIO_NOT_NOTP18_SHIFT (18U) +/*! NOTP18 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP18_SHIFT)) & GPIO_NOT_NOTP18_MASK) + +#define GPIO_NOT_NOTP19_MASK (0x80000U) +#define GPIO_NOT_NOTP19_SHIFT (19U) +/*! NOTP19 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP19_SHIFT)) & GPIO_NOT_NOTP19_MASK) + +#define GPIO_NOT_NOTP20_MASK (0x100000U) +#define GPIO_NOT_NOTP20_SHIFT (20U) +/*! NOTP20 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP20_SHIFT)) & GPIO_NOT_NOTP20_MASK) + +#define GPIO_NOT_NOTP21_MASK (0x200000U) +#define GPIO_NOT_NOTP21_SHIFT (21U) +/*! NOTP21 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP21_SHIFT)) & GPIO_NOT_NOTP21_MASK) + +#define GPIO_NOT_NOTP22_MASK (0x400000U) +#define GPIO_NOT_NOTP22_SHIFT (22U) +/*! NOTP22 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP22_SHIFT)) & GPIO_NOT_NOTP22_MASK) + +#define GPIO_NOT_NOTP23_MASK (0x800000U) +#define GPIO_NOT_NOTP23_SHIFT (23U) +/*! NOTP23 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP23_SHIFT)) & GPIO_NOT_NOTP23_MASK) + +#define GPIO_NOT_NOTP24_MASK (0x1000000U) +#define GPIO_NOT_NOTP24_SHIFT (24U) +/*! NOTP24 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP24_SHIFT)) & GPIO_NOT_NOTP24_MASK) + +#define GPIO_NOT_NOTP25_MASK (0x2000000U) +#define GPIO_NOT_NOTP25_SHIFT (25U) +/*! NOTP25 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP25_SHIFT)) & GPIO_NOT_NOTP25_MASK) + +#define GPIO_NOT_NOTP26_MASK (0x4000000U) +#define GPIO_NOT_NOTP26_SHIFT (26U) +/*! NOTP26 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP26_SHIFT)) & GPIO_NOT_NOTP26_MASK) + +#define GPIO_NOT_NOTP27_MASK (0x8000000U) +#define GPIO_NOT_NOTP27_SHIFT (27U) +/*! NOTP27 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP27_SHIFT)) & GPIO_NOT_NOTP27_MASK) + +#define GPIO_NOT_NOTP28_MASK (0x10000000U) +#define GPIO_NOT_NOTP28_SHIFT (28U) +/*! NOTP28 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP28_SHIFT)) & GPIO_NOT_NOTP28_MASK) + +#define GPIO_NOT_NOTP29_MASK (0x20000000U) +#define GPIO_NOT_NOTP29_SHIFT (29U) +/*! NOTP29 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP29_SHIFT)) & GPIO_NOT_NOTP29_MASK) + +#define GPIO_NOT_NOTP30_MASK (0x40000000U) +#define GPIO_NOT_NOTP30_SHIFT (30U) +/*! NOTP30 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP30_SHIFT)) & GPIO_NOT_NOTP30_MASK) + +#define GPIO_NOT_NOTP31_MASK (0x80000000U) +#define GPIO_NOT_NOTP31_SHIFT (31U) +/*! NOTP31 - Toggle output bits + * 0b0..No operation + * 0b1..Toggle output bit + */ +#define GPIO_NOT_NOTP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP31_SHIFT)) & GPIO_NOT_NOTP31_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (4U) + +/*! @name DIRSET - Port direction set */ +/*! @{ */ + +#define GPIO_DIRSET_DIRSETP0_MASK (0x1U) +#define GPIO_DIRSET_DIRSETP0_SHIFT (0U) +/*! DIRSETP0 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP0_SHIFT)) & GPIO_DIRSET_DIRSETP0_MASK) + +#define GPIO_DIRSET_DIRSETP1_MASK (0x2U) +#define GPIO_DIRSET_DIRSETP1_SHIFT (1U) +/*! DIRSETP1 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP1_SHIFT)) & GPIO_DIRSET_DIRSETP1_MASK) + +#define GPIO_DIRSET_DIRSETP2_MASK (0x4U) +#define GPIO_DIRSET_DIRSETP2_SHIFT (2U) +/*! DIRSETP2 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP2_SHIFT)) & GPIO_DIRSET_DIRSETP2_MASK) + +#define GPIO_DIRSET_DIRSETP3_MASK (0x8U) +#define GPIO_DIRSET_DIRSETP3_SHIFT (3U) +/*! DIRSETP3 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP3_SHIFT)) & GPIO_DIRSET_DIRSETP3_MASK) + +#define GPIO_DIRSET_DIRSETP4_MASK (0x10U) +#define GPIO_DIRSET_DIRSETP4_SHIFT (4U) +/*! DIRSETP4 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP4_SHIFT)) & GPIO_DIRSET_DIRSETP4_MASK) + +#define GPIO_DIRSET_DIRSETP5_MASK (0x20U) +#define GPIO_DIRSET_DIRSETP5_SHIFT (5U) +/*! DIRSETP5 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP5_SHIFT)) & GPIO_DIRSET_DIRSETP5_MASK) + +#define GPIO_DIRSET_DIRSETP6_MASK (0x40U) +#define GPIO_DIRSET_DIRSETP6_SHIFT (6U) +/*! DIRSETP6 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP6_SHIFT)) & GPIO_DIRSET_DIRSETP6_MASK) + +#define GPIO_DIRSET_DIRSETP7_MASK (0x80U) +#define GPIO_DIRSET_DIRSETP7_SHIFT (7U) +/*! DIRSETP7 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP7_SHIFT)) & GPIO_DIRSET_DIRSETP7_MASK) + +#define GPIO_DIRSET_DIRSETP8_MASK (0x100U) +#define GPIO_DIRSET_DIRSETP8_SHIFT (8U) +/*! DIRSETP8 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP8_SHIFT)) & GPIO_DIRSET_DIRSETP8_MASK) + +#define GPIO_DIRSET_DIRSETP9_MASK (0x200U) +#define GPIO_DIRSET_DIRSETP9_SHIFT (9U) +/*! DIRSETP9 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP9_SHIFT)) & GPIO_DIRSET_DIRSETP9_MASK) + +#define GPIO_DIRSET_DIRSETP10_MASK (0x400U) +#define GPIO_DIRSET_DIRSETP10_SHIFT (10U) +/*! DIRSETP10 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP10_SHIFT)) & GPIO_DIRSET_DIRSETP10_MASK) + +#define GPIO_DIRSET_DIRSETP11_MASK (0x800U) +#define GPIO_DIRSET_DIRSETP11_SHIFT (11U) +/*! DIRSETP11 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP11_SHIFT)) & GPIO_DIRSET_DIRSETP11_MASK) + +#define GPIO_DIRSET_DIRSETP12_MASK (0x1000U) +#define GPIO_DIRSET_DIRSETP12_SHIFT (12U) +/*! DIRSETP12 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP12_SHIFT)) & GPIO_DIRSET_DIRSETP12_MASK) + +#define GPIO_DIRSET_DIRSETP13_MASK (0x2000U) +#define GPIO_DIRSET_DIRSETP13_SHIFT (13U) +/*! DIRSETP13 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP13_SHIFT)) & GPIO_DIRSET_DIRSETP13_MASK) + +#define GPIO_DIRSET_DIRSETP14_MASK (0x4000U) +#define GPIO_DIRSET_DIRSETP14_SHIFT (14U) +/*! DIRSETP14 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP14_SHIFT)) & GPIO_DIRSET_DIRSETP14_MASK) + +#define GPIO_DIRSET_DIRSETP15_MASK (0x8000U) +#define GPIO_DIRSET_DIRSETP15_SHIFT (15U) +/*! DIRSETP15 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP15_SHIFT)) & GPIO_DIRSET_DIRSETP15_MASK) + +#define GPIO_DIRSET_DIRSETP16_MASK (0x10000U) +#define GPIO_DIRSET_DIRSETP16_SHIFT (16U) +/*! DIRSETP16 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP16_SHIFT)) & GPIO_DIRSET_DIRSETP16_MASK) + +#define GPIO_DIRSET_DIRSETP17_MASK (0x20000U) +#define GPIO_DIRSET_DIRSETP17_SHIFT (17U) +/*! DIRSETP17 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP17_SHIFT)) & GPIO_DIRSET_DIRSETP17_MASK) + +#define GPIO_DIRSET_DIRSETP18_MASK (0x40000U) +#define GPIO_DIRSET_DIRSETP18_SHIFT (18U) +/*! DIRSETP18 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP18_SHIFT)) & GPIO_DIRSET_DIRSETP18_MASK) + +#define GPIO_DIRSET_DIRSETP19_MASK (0x80000U) +#define GPIO_DIRSET_DIRSETP19_SHIFT (19U) +/*! DIRSETP19 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP19_SHIFT)) & GPIO_DIRSET_DIRSETP19_MASK) + +#define GPIO_DIRSET_DIRSETP20_MASK (0x100000U) +#define GPIO_DIRSET_DIRSETP20_SHIFT (20U) +/*! DIRSETP20 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP20_SHIFT)) & GPIO_DIRSET_DIRSETP20_MASK) + +#define GPIO_DIRSET_DIRSETP21_MASK (0x200000U) +#define GPIO_DIRSET_DIRSETP21_SHIFT (21U) +/*! DIRSETP21 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP21_SHIFT)) & GPIO_DIRSET_DIRSETP21_MASK) + +#define GPIO_DIRSET_DIRSETP22_MASK (0x400000U) +#define GPIO_DIRSET_DIRSETP22_SHIFT (22U) +/*! DIRSETP22 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP22_SHIFT)) & GPIO_DIRSET_DIRSETP22_MASK) + +#define GPIO_DIRSET_DIRSETP23_MASK (0x800000U) +#define GPIO_DIRSET_DIRSETP23_SHIFT (23U) +/*! DIRSETP23 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP23_SHIFT)) & GPIO_DIRSET_DIRSETP23_MASK) + +#define GPIO_DIRSET_DIRSETP24_MASK (0x1000000U) +#define GPIO_DIRSET_DIRSETP24_SHIFT (24U) +/*! DIRSETP24 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP24_SHIFT)) & GPIO_DIRSET_DIRSETP24_MASK) + +#define GPIO_DIRSET_DIRSETP25_MASK (0x2000000U) +#define GPIO_DIRSET_DIRSETP25_SHIFT (25U) +/*! DIRSETP25 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP25_SHIFT)) & GPIO_DIRSET_DIRSETP25_MASK) + +#define GPIO_DIRSET_DIRSETP26_MASK (0x4000000U) +#define GPIO_DIRSET_DIRSETP26_SHIFT (26U) +/*! DIRSETP26 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP26_SHIFT)) & GPIO_DIRSET_DIRSETP26_MASK) + +#define GPIO_DIRSET_DIRSETP27_MASK (0x8000000U) +#define GPIO_DIRSET_DIRSETP27_SHIFT (27U) +/*! DIRSETP27 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP27_SHIFT)) & GPIO_DIRSET_DIRSETP27_MASK) + +#define GPIO_DIRSET_DIRSETP28_MASK (0x10000000U) +#define GPIO_DIRSET_DIRSETP28_SHIFT (28U) +/*! DIRSETP28 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP28_SHIFT)) & GPIO_DIRSET_DIRSETP28_MASK) + +#define GPIO_DIRSET_DIRSETP29_MASK (0x20000000U) +#define GPIO_DIRSET_DIRSETP29_SHIFT (29U) +/*! DIRSETP29 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP29_SHIFT)) & GPIO_DIRSET_DIRSETP29_MASK) + +#define GPIO_DIRSET_DIRSETP30_MASK (0x40000000U) +#define GPIO_DIRSET_DIRSETP30_SHIFT (30U) +/*! DIRSETP30 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP30_SHIFT)) & GPIO_DIRSET_DIRSETP30_MASK) + +#define GPIO_DIRSET_DIRSETP31_MASK (0x80000000U) +#define GPIO_DIRSET_DIRSETP31_SHIFT (31U) +/*! DIRSETP31 - Direction set bits for Port pins + * 0b0..No operation + * 0b1..Sets direction bit + */ +#define GPIO_DIRSET_DIRSETP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP31_SHIFT)) & GPIO_DIRSET_DIRSETP31_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (4U) + +/*! @name DIRCLR - Port direction clear */ +/*! @{ */ + +#define GPIO_DIRCLR_DIRCLRP0_MASK (0x1U) +#define GPIO_DIRCLR_DIRCLRP0_SHIFT (0U) +/*! DIRCLRP0 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP0_SHIFT)) & GPIO_DIRCLR_DIRCLRP0_MASK) + +#define GPIO_DIRCLR_DIRCLRP1_MASK (0x2U) +#define GPIO_DIRCLR_DIRCLRP1_SHIFT (1U) +/*! DIRCLRP1 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP1_SHIFT)) & GPIO_DIRCLR_DIRCLRP1_MASK) + +#define GPIO_DIRCLR_DIRCLRP2_MASK (0x4U) +#define GPIO_DIRCLR_DIRCLRP2_SHIFT (2U) +/*! DIRCLRP2 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP2_SHIFT)) & GPIO_DIRCLR_DIRCLRP2_MASK) + +#define GPIO_DIRCLR_DIRCLRP3_MASK (0x8U) +#define GPIO_DIRCLR_DIRCLRP3_SHIFT (3U) +/*! DIRCLRP3 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP3_SHIFT)) & GPIO_DIRCLR_DIRCLRP3_MASK) + +#define GPIO_DIRCLR_DIRCLRP4_MASK (0x10U) +#define GPIO_DIRCLR_DIRCLRP4_SHIFT (4U) +/*! DIRCLRP4 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP4_SHIFT)) & GPIO_DIRCLR_DIRCLRP4_MASK) + +#define GPIO_DIRCLR_DIRCLRP5_MASK (0x20U) +#define GPIO_DIRCLR_DIRCLRP5_SHIFT (5U) +/*! DIRCLRP5 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP5_SHIFT)) & GPIO_DIRCLR_DIRCLRP5_MASK) + +#define GPIO_DIRCLR_DIRCLRP6_MASK (0x40U) +#define GPIO_DIRCLR_DIRCLRP6_SHIFT (6U) +/*! DIRCLRP6 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP6_SHIFT)) & GPIO_DIRCLR_DIRCLRP6_MASK) + +#define GPIO_DIRCLR_DIRCLRP7_MASK (0x80U) +#define GPIO_DIRCLR_DIRCLRP7_SHIFT (7U) +/*! DIRCLRP7 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP7_SHIFT)) & GPIO_DIRCLR_DIRCLRP7_MASK) + +#define GPIO_DIRCLR_DIRCLRP8_MASK (0x100U) +#define GPIO_DIRCLR_DIRCLRP8_SHIFT (8U) +/*! DIRCLRP8 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP8_SHIFT)) & GPIO_DIRCLR_DIRCLRP8_MASK) + +#define GPIO_DIRCLR_DIRCLRP9_MASK (0x200U) +#define GPIO_DIRCLR_DIRCLRP9_SHIFT (9U) +/*! DIRCLRP9 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP9_SHIFT)) & GPIO_DIRCLR_DIRCLRP9_MASK) + +#define GPIO_DIRCLR_DIRCLRP10_MASK (0x400U) +#define GPIO_DIRCLR_DIRCLRP10_SHIFT (10U) +/*! DIRCLRP10 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP10_SHIFT)) & GPIO_DIRCLR_DIRCLRP10_MASK) + +#define GPIO_DIRCLR_DIRCLRP11_MASK (0x800U) +#define GPIO_DIRCLR_DIRCLRP11_SHIFT (11U) +/*! DIRCLRP11 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP11_SHIFT)) & GPIO_DIRCLR_DIRCLRP11_MASK) + +#define GPIO_DIRCLR_DIRCLRP12_MASK (0x1000U) +#define GPIO_DIRCLR_DIRCLRP12_SHIFT (12U) +/*! DIRCLRP12 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP12_SHIFT)) & GPIO_DIRCLR_DIRCLRP12_MASK) + +#define GPIO_DIRCLR_DIRCLRP13_MASK (0x2000U) +#define GPIO_DIRCLR_DIRCLRP13_SHIFT (13U) +/*! DIRCLRP13 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP13_SHIFT)) & GPIO_DIRCLR_DIRCLRP13_MASK) + +#define GPIO_DIRCLR_DIRCLRP14_MASK (0x4000U) +#define GPIO_DIRCLR_DIRCLRP14_SHIFT (14U) +/*! DIRCLRP14 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP14_SHIFT)) & GPIO_DIRCLR_DIRCLRP14_MASK) + +#define GPIO_DIRCLR_DIRCLRP15_MASK (0x8000U) +#define GPIO_DIRCLR_DIRCLRP15_SHIFT (15U) +/*! DIRCLRP15 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP15_SHIFT)) & GPIO_DIRCLR_DIRCLRP15_MASK) + +#define GPIO_DIRCLR_DIRCLRP16_MASK (0x10000U) +#define GPIO_DIRCLR_DIRCLRP16_SHIFT (16U) +/*! DIRCLRP16 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP16_SHIFT)) & GPIO_DIRCLR_DIRCLRP16_MASK) + +#define GPIO_DIRCLR_DIRCLRP17_MASK (0x20000U) +#define GPIO_DIRCLR_DIRCLRP17_SHIFT (17U) +/*! DIRCLRP17 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP17_SHIFT)) & GPIO_DIRCLR_DIRCLRP17_MASK) + +#define GPIO_DIRCLR_DIRCLRP18_MASK (0x40000U) +#define GPIO_DIRCLR_DIRCLRP18_SHIFT (18U) +/*! DIRCLRP18 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP18_SHIFT)) & GPIO_DIRCLR_DIRCLRP18_MASK) + +#define GPIO_DIRCLR_DIRCLRP19_MASK (0x80000U) +#define GPIO_DIRCLR_DIRCLRP19_SHIFT (19U) +/*! DIRCLRP19 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP19_SHIFT)) & GPIO_DIRCLR_DIRCLRP19_MASK) + +#define GPIO_DIRCLR_DIRCLRP20_MASK (0x100000U) +#define GPIO_DIRCLR_DIRCLRP20_SHIFT (20U) +/*! DIRCLRP20 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP20_SHIFT)) & GPIO_DIRCLR_DIRCLRP20_MASK) + +#define GPIO_DIRCLR_DIRCLRP21_MASK (0x200000U) +#define GPIO_DIRCLR_DIRCLRP21_SHIFT (21U) +/*! DIRCLRP21 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP21_SHIFT)) & GPIO_DIRCLR_DIRCLRP21_MASK) + +#define GPIO_DIRCLR_DIRCLRP22_MASK (0x400000U) +#define GPIO_DIRCLR_DIRCLRP22_SHIFT (22U) +/*! DIRCLRP22 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP22_SHIFT)) & GPIO_DIRCLR_DIRCLRP22_MASK) + +#define GPIO_DIRCLR_DIRCLRP23_MASK (0x800000U) +#define GPIO_DIRCLR_DIRCLRP23_SHIFT (23U) +/*! DIRCLRP23 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP23_SHIFT)) & GPIO_DIRCLR_DIRCLRP23_MASK) + +#define GPIO_DIRCLR_DIRCLRP24_MASK (0x1000000U) +#define GPIO_DIRCLR_DIRCLRP24_SHIFT (24U) +/*! DIRCLRP24 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP24_SHIFT)) & GPIO_DIRCLR_DIRCLRP24_MASK) + +#define GPIO_DIRCLR_DIRCLRP25_MASK (0x2000000U) +#define GPIO_DIRCLR_DIRCLRP25_SHIFT (25U) +/*! DIRCLRP25 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP25_SHIFT)) & GPIO_DIRCLR_DIRCLRP25_MASK) + +#define GPIO_DIRCLR_DIRCLRP26_MASK (0x4000000U) +#define GPIO_DIRCLR_DIRCLRP26_SHIFT (26U) +/*! DIRCLRP26 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP26_SHIFT)) & GPIO_DIRCLR_DIRCLRP26_MASK) + +#define GPIO_DIRCLR_DIRCLRP27_MASK (0x8000000U) +#define GPIO_DIRCLR_DIRCLRP27_SHIFT (27U) +/*! DIRCLRP27 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP27_SHIFT)) & GPIO_DIRCLR_DIRCLRP27_MASK) + +#define GPIO_DIRCLR_DIRCLRP28_MASK (0x10000000U) +#define GPIO_DIRCLR_DIRCLRP28_SHIFT (28U) +/*! DIRCLRP28 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP28_SHIFT)) & GPIO_DIRCLR_DIRCLRP28_MASK) + +#define GPIO_DIRCLR_DIRCLRP29_MASK (0x20000000U) +#define GPIO_DIRCLR_DIRCLRP29_SHIFT (29U) +/*! DIRCLRP29 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP29_SHIFT)) & GPIO_DIRCLR_DIRCLRP29_MASK) + +#define GPIO_DIRCLR_DIRCLRP30_MASK (0x40000000U) +#define GPIO_DIRCLR_DIRCLRP30_SHIFT (30U) +/*! DIRCLRP30 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP30_SHIFT)) & GPIO_DIRCLR_DIRCLRP30_MASK) + +#define GPIO_DIRCLR_DIRCLRP31_MASK (0x80000000U) +#define GPIO_DIRCLR_DIRCLRP31_SHIFT (31U) +/*! DIRCLRP31 - Clear direction bits. + * 0b0..No operation + * 0b1..Clears direction bits + */ +#define GPIO_DIRCLR_DIRCLRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP31_SHIFT)) & GPIO_DIRCLR_DIRCLRP31_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (4U) + +/*! @name DIRNOT - Port direction toggle */ +/*! @{ */ + +#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits. + * 0b00000000000000000000000000000..No operation + * 0b00000000000000000000000000001..Toggles direction bit + */ +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (4U) + +/*! @name INTENA - Interrupt A enable control */ +/*! @{ */ + +#define GPIO_INTENA_INT_EN0_MASK (0x1U) +#define GPIO_INTENA_INT_EN0_SHIFT (0U) +/*! INT_EN0 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN0_SHIFT)) & GPIO_INTENA_INT_EN0_MASK) + +#define GPIO_INTENA_INT_EN1_MASK (0x2U) +#define GPIO_INTENA_INT_EN1_SHIFT (1U) +/*! INT_EN1 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN1_SHIFT)) & GPIO_INTENA_INT_EN1_MASK) + +#define GPIO_INTENA_INT_EN2_MASK (0x4U) +#define GPIO_INTENA_INT_EN2_SHIFT (2U) +/*! INT_EN2 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN2_SHIFT)) & GPIO_INTENA_INT_EN2_MASK) + +#define GPIO_INTENA_INT_EN3_MASK (0x8U) +#define GPIO_INTENA_INT_EN3_SHIFT (3U) +/*! INT_EN3 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN3_SHIFT)) & GPIO_INTENA_INT_EN3_MASK) + +#define GPIO_INTENA_INT_EN4_MASK (0x10U) +#define GPIO_INTENA_INT_EN4_SHIFT (4U) +/*! INT_EN4 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN4_SHIFT)) & GPIO_INTENA_INT_EN4_MASK) + +#define GPIO_INTENA_INT_EN5_MASK (0x20U) +#define GPIO_INTENA_INT_EN5_SHIFT (5U) +/*! INT_EN5 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN5_SHIFT)) & GPIO_INTENA_INT_EN5_MASK) + +#define GPIO_INTENA_INT_EN6_MASK (0x40U) +#define GPIO_INTENA_INT_EN6_SHIFT (6U) +/*! INT_EN6 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN6_SHIFT)) & GPIO_INTENA_INT_EN6_MASK) + +#define GPIO_INTENA_INT_EN7_MASK (0x80U) +#define GPIO_INTENA_INT_EN7_SHIFT (7U) +/*! INT_EN7 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN7_SHIFT)) & GPIO_INTENA_INT_EN7_MASK) + +#define GPIO_INTENA_INT_EN8_MASK (0x100U) +#define GPIO_INTENA_INT_EN8_SHIFT (8U) +/*! INT_EN8 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN8_SHIFT)) & GPIO_INTENA_INT_EN8_MASK) + +#define GPIO_INTENA_INT_EN9_MASK (0x200U) +#define GPIO_INTENA_INT_EN9_SHIFT (9U) +/*! INT_EN9 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN9_SHIFT)) & GPIO_INTENA_INT_EN9_MASK) + +#define GPIO_INTENA_INT_EN10_MASK (0x400U) +#define GPIO_INTENA_INT_EN10_SHIFT (10U) +/*! INT_EN10 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN10_SHIFT)) & GPIO_INTENA_INT_EN10_MASK) + +#define GPIO_INTENA_INT_EN11_MASK (0x800U) +#define GPIO_INTENA_INT_EN11_SHIFT (11U) +/*! INT_EN11 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN11_SHIFT)) & GPIO_INTENA_INT_EN11_MASK) + +#define GPIO_INTENA_INT_EN12_MASK (0x1000U) +#define GPIO_INTENA_INT_EN12_SHIFT (12U) +/*! INT_EN12 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN12_SHIFT)) & GPIO_INTENA_INT_EN12_MASK) + +#define GPIO_INTENA_INT_EN13_MASK (0x2000U) +#define GPIO_INTENA_INT_EN13_SHIFT (13U) +/*! INT_EN13 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN13_SHIFT)) & GPIO_INTENA_INT_EN13_MASK) + +#define GPIO_INTENA_INT_EN14_MASK (0x4000U) +#define GPIO_INTENA_INT_EN14_SHIFT (14U) +/*! INT_EN14 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN14_SHIFT)) & GPIO_INTENA_INT_EN14_MASK) + +#define GPIO_INTENA_INT_EN15_MASK (0x8000U) +#define GPIO_INTENA_INT_EN15_SHIFT (15U) +/*! INT_EN15 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN15_SHIFT)) & GPIO_INTENA_INT_EN15_MASK) + +#define GPIO_INTENA_INT_EN16_MASK (0x10000U) +#define GPIO_INTENA_INT_EN16_SHIFT (16U) +/*! INT_EN16 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN16_SHIFT)) & GPIO_INTENA_INT_EN16_MASK) + +#define GPIO_INTENA_INT_EN17_MASK (0x20000U) +#define GPIO_INTENA_INT_EN17_SHIFT (17U) +/*! INT_EN17 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN17_SHIFT)) & GPIO_INTENA_INT_EN17_MASK) + +#define GPIO_INTENA_INT_EN18_MASK (0x40000U) +#define GPIO_INTENA_INT_EN18_SHIFT (18U) +/*! INT_EN18 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN18_SHIFT)) & GPIO_INTENA_INT_EN18_MASK) + +#define GPIO_INTENA_INT_EN19_MASK (0x80000U) +#define GPIO_INTENA_INT_EN19_SHIFT (19U) +/*! INT_EN19 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN19_SHIFT)) & GPIO_INTENA_INT_EN19_MASK) + +#define GPIO_INTENA_INT_EN20_MASK (0x100000U) +#define GPIO_INTENA_INT_EN20_SHIFT (20U) +/*! INT_EN20 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN20_SHIFT)) & GPIO_INTENA_INT_EN20_MASK) + +#define GPIO_INTENA_INT_EN21_MASK (0x200000U) +#define GPIO_INTENA_INT_EN21_SHIFT (21U) +/*! INT_EN21 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN21_SHIFT)) & GPIO_INTENA_INT_EN21_MASK) + +#define GPIO_INTENA_INT_EN22_MASK (0x400000U) +#define GPIO_INTENA_INT_EN22_SHIFT (22U) +/*! INT_EN22 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN22_SHIFT)) & GPIO_INTENA_INT_EN22_MASK) + +#define GPIO_INTENA_INT_EN23_MASK (0x800000U) +#define GPIO_INTENA_INT_EN23_SHIFT (23U) +/*! INT_EN23 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN23_SHIFT)) & GPIO_INTENA_INT_EN23_MASK) + +#define GPIO_INTENA_INT_EN24_MASK (0x1000000U) +#define GPIO_INTENA_INT_EN24_SHIFT (24U) +/*! INT_EN24 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN24_SHIFT)) & GPIO_INTENA_INT_EN24_MASK) + +#define GPIO_INTENA_INT_EN25_MASK (0x2000000U) +#define GPIO_INTENA_INT_EN25_SHIFT (25U) +/*! INT_EN25 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN25_SHIFT)) & GPIO_INTENA_INT_EN25_MASK) + +#define GPIO_INTENA_INT_EN26_MASK (0x4000000U) +#define GPIO_INTENA_INT_EN26_SHIFT (26U) +/*! INT_EN26 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN26_SHIFT)) & GPIO_INTENA_INT_EN26_MASK) + +#define GPIO_INTENA_INT_EN27_MASK (0x8000000U) +#define GPIO_INTENA_INT_EN27_SHIFT (27U) +/*! INT_EN27 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN27_SHIFT)) & GPIO_INTENA_INT_EN27_MASK) + +#define GPIO_INTENA_INT_EN28_MASK (0x10000000U) +#define GPIO_INTENA_INT_EN28_SHIFT (28U) +/*! INT_EN28 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN28_SHIFT)) & GPIO_INTENA_INT_EN28_MASK) + +#define GPIO_INTENA_INT_EN29_MASK (0x20000000U) +#define GPIO_INTENA_INT_EN29_SHIFT (29U) +/*! INT_EN29 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN29_SHIFT)) & GPIO_INTENA_INT_EN29_MASK) + +#define GPIO_INTENA_INT_EN30_MASK (0x40000000U) +#define GPIO_INTENA_INT_EN30_SHIFT (30U) +/*! INT_EN30 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN30_SHIFT)) & GPIO_INTENA_INT_EN30_MASK) + +#define GPIO_INTENA_INT_EN31_MASK (0x80000000U) +#define GPIO_INTENA_INT_EN31_SHIFT (31U) +/*! INT_EN31 - Interrupt A enable bits. + * 0b0..Pin does not contribute to GPIO interrupt A + * 0b1..Pin contributes to GPIO interrupt A + */ +#define GPIO_INTENA_INT_EN31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN31_SHIFT)) & GPIO_INTENA_INT_EN31_MASK) +/*! @} */ + +/* The count of GPIO_INTENA */ +#define GPIO_INTENA_COUNT (4U) + +/*! @name INTENB - Interrupt B enable control */ +/*! @{ */ + +#define GPIO_INTENB_INT_EN0_MASK (0x1U) +#define GPIO_INTENB_INT_EN0_SHIFT (0U) +/*! INT_EN0 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN0_SHIFT)) & GPIO_INTENB_INT_EN0_MASK) + +#define GPIO_INTENB_INT_EN1_MASK (0x2U) +#define GPIO_INTENB_INT_EN1_SHIFT (1U) +/*! INT_EN1 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN1_SHIFT)) & GPIO_INTENB_INT_EN1_MASK) + +#define GPIO_INTENB_INT_EN2_MASK (0x4U) +#define GPIO_INTENB_INT_EN2_SHIFT (2U) +/*! INT_EN2 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN2_SHIFT)) & GPIO_INTENB_INT_EN2_MASK) + +#define GPIO_INTENB_INT_EN3_MASK (0x8U) +#define GPIO_INTENB_INT_EN3_SHIFT (3U) +/*! INT_EN3 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN3_SHIFT)) & GPIO_INTENB_INT_EN3_MASK) + +#define GPIO_INTENB_INT_EN4_MASK (0x10U) +#define GPIO_INTENB_INT_EN4_SHIFT (4U) +/*! INT_EN4 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN4_SHIFT)) & GPIO_INTENB_INT_EN4_MASK) + +#define GPIO_INTENB_INT_EN5_MASK (0x20U) +#define GPIO_INTENB_INT_EN5_SHIFT (5U) +/*! INT_EN5 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN5_SHIFT)) & GPIO_INTENB_INT_EN5_MASK) + +#define GPIO_INTENB_INT_EN6_MASK (0x40U) +#define GPIO_INTENB_INT_EN6_SHIFT (6U) +/*! INT_EN6 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN6_SHIFT)) & GPIO_INTENB_INT_EN6_MASK) + +#define GPIO_INTENB_INT_EN7_MASK (0x80U) +#define GPIO_INTENB_INT_EN7_SHIFT (7U) +/*! INT_EN7 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN7_SHIFT)) & GPIO_INTENB_INT_EN7_MASK) + +#define GPIO_INTENB_INT_EN8_MASK (0x100U) +#define GPIO_INTENB_INT_EN8_SHIFT (8U) +/*! INT_EN8 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN8_SHIFT)) & GPIO_INTENB_INT_EN8_MASK) + +#define GPIO_INTENB_INT_EN9_MASK (0x200U) +#define GPIO_INTENB_INT_EN9_SHIFT (9U) +/*! INT_EN9 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN9_SHIFT)) & GPIO_INTENB_INT_EN9_MASK) + +#define GPIO_INTENB_INT_EN10_MASK (0x400U) +#define GPIO_INTENB_INT_EN10_SHIFT (10U) +/*! INT_EN10 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN10_SHIFT)) & GPIO_INTENB_INT_EN10_MASK) + +#define GPIO_INTENB_INT_EN11_MASK (0x800U) +#define GPIO_INTENB_INT_EN11_SHIFT (11U) +/*! INT_EN11 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN11_SHIFT)) & GPIO_INTENB_INT_EN11_MASK) + +#define GPIO_INTENB_INT_EN12_MASK (0x1000U) +#define GPIO_INTENB_INT_EN12_SHIFT (12U) +/*! INT_EN12 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN12_SHIFT)) & GPIO_INTENB_INT_EN12_MASK) + +#define GPIO_INTENB_INT_EN13_MASK (0x2000U) +#define GPIO_INTENB_INT_EN13_SHIFT (13U) +/*! INT_EN13 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN13_SHIFT)) & GPIO_INTENB_INT_EN13_MASK) + +#define GPIO_INTENB_INT_EN14_MASK (0x4000U) +#define GPIO_INTENB_INT_EN14_SHIFT (14U) +/*! INT_EN14 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN14_SHIFT)) & GPIO_INTENB_INT_EN14_MASK) + +#define GPIO_INTENB_INT_EN15_MASK (0x8000U) +#define GPIO_INTENB_INT_EN15_SHIFT (15U) +/*! INT_EN15 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN15_SHIFT)) & GPIO_INTENB_INT_EN15_MASK) + +#define GPIO_INTENB_INT_EN16_MASK (0x10000U) +#define GPIO_INTENB_INT_EN16_SHIFT (16U) +/*! INT_EN16 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN16_SHIFT)) & GPIO_INTENB_INT_EN16_MASK) + +#define GPIO_INTENB_INT_EN17_MASK (0x20000U) +#define GPIO_INTENB_INT_EN17_SHIFT (17U) +/*! INT_EN17 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN17_SHIFT)) & GPIO_INTENB_INT_EN17_MASK) + +#define GPIO_INTENB_INT_EN18_MASK (0x40000U) +#define GPIO_INTENB_INT_EN18_SHIFT (18U) +/*! INT_EN18 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN18_SHIFT)) & GPIO_INTENB_INT_EN18_MASK) + +#define GPIO_INTENB_INT_EN19_MASK (0x80000U) +#define GPIO_INTENB_INT_EN19_SHIFT (19U) +/*! INT_EN19 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN19_SHIFT)) & GPIO_INTENB_INT_EN19_MASK) + +#define GPIO_INTENB_INT_EN20_MASK (0x100000U) +#define GPIO_INTENB_INT_EN20_SHIFT (20U) +/*! INT_EN20 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN20_SHIFT)) & GPIO_INTENB_INT_EN20_MASK) + +#define GPIO_INTENB_INT_EN21_MASK (0x200000U) +#define GPIO_INTENB_INT_EN21_SHIFT (21U) +/*! INT_EN21 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN21_SHIFT)) & GPIO_INTENB_INT_EN21_MASK) + +#define GPIO_INTENB_INT_EN22_MASK (0x400000U) +#define GPIO_INTENB_INT_EN22_SHIFT (22U) +/*! INT_EN22 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN22_SHIFT)) & GPIO_INTENB_INT_EN22_MASK) + +#define GPIO_INTENB_INT_EN23_MASK (0x800000U) +#define GPIO_INTENB_INT_EN23_SHIFT (23U) +/*! INT_EN23 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN23_SHIFT)) & GPIO_INTENB_INT_EN23_MASK) + +#define GPIO_INTENB_INT_EN24_MASK (0x1000000U) +#define GPIO_INTENB_INT_EN24_SHIFT (24U) +/*! INT_EN24 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN24_SHIFT)) & GPIO_INTENB_INT_EN24_MASK) + +#define GPIO_INTENB_INT_EN25_MASK (0x2000000U) +#define GPIO_INTENB_INT_EN25_SHIFT (25U) +/*! INT_EN25 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN25_SHIFT)) & GPIO_INTENB_INT_EN25_MASK) + +#define GPIO_INTENB_INT_EN26_MASK (0x4000000U) +#define GPIO_INTENB_INT_EN26_SHIFT (26U) +/*! INT_EN26 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN26_SHIFT)) & GPIO_INTENB_INT_EN26_MASK) + +#define GPIO_INTENB_INT_EN27_MASK (0x8000000U) +#define GPIO_INTENB_INT_EN27_SHIFT (27U) +/*! INT_EN27 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN27_SHIFT)) & GPIO_INTENB_INT_EN27_MASK) + +#define GPIO_INTENB_INT_EN28_MASK (0x10000000U) +#define GPIO_INTENB_INT_EN28_SHIFT (28U) +/*! INT_EN28 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN28_SHIFT)) & GPIO_INTENB_INT_EN28_MASK) + +#define GPIO_INTENB_INT_EN29_MASK (0x20000000U) +#define GPIO_INTENB_INT_EN29_SHIFT (29U) +/*! INT_EN29 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN29_SHIFT)) & GPIO_INTENB_INT_EN29_MASK) + +#define GPIO_INTENB_INT_EN30_MASK (0x40000000U) +#define GPIO_INTENB_INT_EN30_SHIFT (30U) +/*! INT_EN30 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN30_SHIFT)) & GPIO_INTENB_INT_EN30_MASK) + +#define GPIO_INTENB_INT_EN31_MASK (0x80000000U) +#define GPIO_INTENB_INT_EN31_SHIFT (31U) +/*! INT_EN31 - Interrupt B enable bits. + * 0b0..Pin does not contribute to GPIO interrupt B + * 0b1..Pin contributes to GPIO interrupt B + */ +#define GPIO_INTENB_INT_EN31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN31_SHIFT)) & GPIO_INTENB_INT_EN31_MASK) +/*! @} */ + +/* The count of GPIO_INTENB */ +#define GPIO_INTENB_COUNT (4U) + +/*! @name INTPOL - Interupt polarity control */ +/*! @{ */ + +#define GPIO_INTPOL_POL_CTL0_MASK (0x1U) +#define GPIO_INTPOL_POL_CTL0_SHIFT (0U) +/*! POL_CTL0 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL0_SHIFT)) & GPIO_INTPOL_POL_CTL0_MASK) + +#define GPIO_INTPOL_POL_CTL1_MASK (0x2U) +#define GPIO_INTPOL_POL_CTL1_SHIFT (1U) +/*! POL_CTL1 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL1_SHIFT)) & GPIO_INTPOL_POL_CTL1_MASK) + +#define GPIO_INTPOL_POL_CTL2_MASK (0x4U) +#define GPIO_INTPOL_POL_CTL2_SHIFT (2U) +/*! POL_CTL2 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL2_SHIFT)) & GPIO_INTPOL_POL_CTL2_MASK) + +#define GPIO_INTPOL_POL_CTL3_MASK (0x8U) +#define GPIO_INTPOL_POL_CTL3_SHIFT (3U) +/*! POL_CTL3 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL3_SHIFT)) & GPIO_INTPOL_POL_CTL3_MASK) + +#define GPIO_INTPOL_POL_CTL4_MASK (0x10U) +#define GPIO_INTPOL_POL_CTL4_SHIFT (4U) +/*! POL_CTL4 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL4_SHIFT)) & GPIO_INTPOL_POL_CTL4_MASK) + +#define GPIO_INTPOL_POL_CTL5_MASK (0x20U) +#define GPIO_INTPOL_POL_CTL5_SHIFT (5U) +/*! POL_CTL5 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL5_SHIFT)) & GPIO_INTPOL_POL_CTL5_MASK) + +#define GPIO_INTPOL_POL_CTL6_MASK (0x40U) +#define GPIO_INTPOL_POL_CTL6_SHIFT (6U) +/*! POL_CTL6 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL6_SHIFT)) & GPIO_INTPOL_POL_CTL6_MASK) + +#define GPIO_INTPOL_POL_CTL7_MASK (0x80U) +#define GPIO_INTPOL_POL_CTL7_SHIFT (7U) +/*! POL_CTL7 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL7_SHIFT)) & GPIO_INTPOL_POL_CTL7_MASK) + +#define GPIO_INTPOL_POL_CTL8_MASK (0x100U) +#define GPIO_INTPOL_POL_CTL8_SHIFT (8U) +/*! POL_CTL8 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL8_SHIFT)) & GPIO_INTPOL_POL_CTL8_MASK) + +#define GPIO_INTPOL_POL_CTL9_MASK (0x200U) +#define GPIO_INTPOL_POL_CTL9_SHIFT (9U) +/*! POL_CTL9 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL9_SHIFT)) & GPIO_INTPOL_POL_CTL9_MASK) + +#define GPIO_INTPOL_POL_CTL10_MASK (0x400U) +#define GPIO_INTPOL_POL_CTL10_SHIFT (10U) +/*! POL_CTL10 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL10_SHIFT)) & GPIO_INTPOL_POL_CTL10_MASK) + +#define GPIO_INTPOL_POL_CTL11_MASK (0x800U) +#define GPIO_INTPOL_POL_CTL11_SHIFT (11U) +/*! POL_CTL11 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL11_SHIFT)) & GPIO_INTPOL_POL_CTL11_MASK) + +#define GPIO_INTPOL_POL_CTL12_MASK (0x1000U) +#define GPIO_INTPOL_POL_CTL12_SHIFT (12U) +/*! POL_CTL12 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL12_SHIFT)) & GPIO_INTPOL_POL_CTL12_MASK) + +#define GPIO_INTPOL_POL_CTL13_MASK (0x2000U) +#define GPIO_INTPOL_POL_CTL13_SHIFT (13U) +/*! POL_CTL13 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL13_SHIFT)) & GPIO_INTPOL_POL_CTL13_MASK) + +#define GPIO_INTPOL_POL_CTL14_MASK (0x4000U) +#define GPIO_INTPOL_POL_CTL14_SHIFT (14U) +/*! POL_CTL14 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL14_SHIFT)) & GPIO_INTPOL_POL_CTL14_MASK) + +#define GPIO_INTPOL_POL_CTL15_MASK (0x8000U) +#define GPIO_INTPOL_POL_CTL15_SHIFT (15U) +/*! POL_CTL15 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL15_SHIFT)) & GPIO_INTPOL_POL_CTL15_MASK) + +#define GPIO_INTPOL_POL_CTL16_MASK (0x10000U) +#define GPIO_INTPOL_POL_CTL16_SHIFT (16U) +/*! POL_CTL16 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL16_SHIFT)) & GPIO_INTPOL_POL_CTL16_MASK) + +#define GPIO_INTPOL_POL_CTL17_MASK (0x20000U) +#define GPIO_INTPOL_POL_CTL17_SHIFT (17U) +/*! POL_CTL17 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL17_SHIFT)) & GPIO_INTPOL_POL_CTL17_MASK) + +#define GPIO_INTPOL_POL_CTL18_MASK (0x40000U) +#define GPIO_INTPOL_POL_CTL18_SHIFT (18U) +/*! POL_CTL18 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL18_SHIFT)) & GPIO_INTPOL_POL_CTL18_MASK) + +#define GPIO_INTPOL_POL_CTL19_MASK (0x80000U) +#define GPIO_INTPOL_POL_CTL19_SHIFT (19U) +/*! POL_CTL19 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL19_SHIFT)) & GPIO_INTPOL_POL_CTL19_MASK) + +#define GPIO_INTPOL_POL_CTL20_MASK (0x100000U) +#define GPIO_INTPOL_POL_CTL20_SHIFT (20U) +/*! POL_CTL20 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL20_SHIFT)) & GPIO_INTPOL_POL_CTL20_MASK) + +#define GPIO_INTPOL_POL_CTL21_MASK (0x200000U) +#define GPIO_INTPOL_POL_CTL21_SHIFT (21U) +/*! POL_CTL21 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL21_SHIFT)) & GPIO_INTPOL_POL_CTL21_MASK) + +#define GPIO_INTPOL_POL_CTL22_MASK (0x400000U) +#define GPIO_INTPOL_POL_CTL22_SHIFT (22U) +/*! POL_CTL22 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL22_SHIFT)) & GPIO_INTPOL_POL_CTL22_MASK) + +#define GPIO_INTPOL_POL_CTL23_MASK (0x800000U) +#define GPIO_INTPOL_POL_CTL23_SHIFT (23U) +/*! POL_CTL23 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL23_SHIFT)) & GPIO_INTPOL_POL_CTL23_MASK) + +#define GPIO_INTPOL_POL_CTL24_MASK (0x1000000U) +#define GPIO_INTPOL_POL_CTL24_SHIFT (24U) +/*! POL_CTL24 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL24_SHIFT)) & GPIO_INTPOL_POL_CTL24_MASK) + +#define GPIO_INTPOL_POL_CTL25_MASK (0x2000000U) +#define GPIO_INTPOL_POL_CTL25_SHIFT (25U) +/*! POL_CTL25 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL25_SHIFT)) & GPIO_INTPOL_POL_CTL25_MASK) + +#define GPIO_INTPOL_POL_CTL26_MASK (0x4000000U) +#define GPIO_INTPOL_POL_CTL26_SHIFT (26U) +/*! POL_CTL26 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL26_SHIFT)) & GPIO_INTPOL_POL_CTL26_MASK) + +#define GPIO_INTPOL_POL_CTL27_MASK (0x8000000U) +#define GPIO_INTPOL_POL_CTL27_SHIFT (27U) +/*! POL_CTL27 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL27_SHIFT)) & GPIO_INTPOL_POL_CTL27_MASK) + +#define GPIO_INTPOL_POL_CTL28_MASK (0x10000000U) +#define GPIO_INTPOL_POL_CTL28_SHIFT (28U) +/*! POL_CTL28 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL28_SHIFT)) & GPIO_INTPOL_POL_CTL28_MASK) + +#define GPIO_INTPOL_POL_CTL29_MASK (0x20000000U) +#define GPIO_INTPOL_POL_CTL29_SHIFT (29U) +/*! POL_CTL29 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL29_SHIFT)) & GPIO_INTPOL_POL_CTL29_MASK) + +#define GPIO_INTPOL_POL_CTL30_MASK (0x40000000U) +#define GPIO_INTPOL_POL_CTL30_SHIFT (30U) +/*! POL_CTL30 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL30_SHIFT)) & GPIO_INTPOL_POL_CTL30_MASK) + +#define GPIO_INTPOL_POL_CTL31_MASK (0x80000000U) +#define GPIO_INTPOL_POL_CTL31_SHIFT (31U) +/*! POL_CTL31 - Polarity control for each pin + * 0b0..High level or rising edge triggered + * 0b1..Low level or falling edge triggered + */ +#define GPIO_INTPOL_POL_CTL31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL31_SHIFT)) & GPIO_INTPOL_POL_CTL31_MASK) +/*! @} */ + +/* The count of GPIO_INTPOL */ +#define GPIO_INTPOL_COUNT (4U) + +/*! @name INTEDG - Interrupt edge select */ +/*! @{ */ + +#define GPIO_INTEDG_EDGE0_MASK (0x1U) +#define GPIO_INTEDG_EDGE0_SHIFT (0U) +/*! EDGE0 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE0_SHIFT)) & GPIO_INTEDG_EDGE0_MASK) + +#define GPIO_INTEDG_EDGE1_MASK (0x2U) +#define GPIO_INTEDG_EDGE1_SHIFT (1U) +/*! EDGE1 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE1_SHIFT)) & GPIO_INTEDG_EDGE1_MASK) + +#define GPIO_INTEDG_EDGE2_MASK (0x4U) +#define GPIO_INTEDG_EDGE2_SHIFT (2U) +/*! EDGE2 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE2_SHIFT)) & GPIO_INTEDG_EDGE2_MASK) + +#define GPIO_INTEDG_EDGE3_MASK (0x8U) +#define GPIO_INTEDG_EDGE3_SHIFT (3U) +/*! EDGE3 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE3_SHIFT)) & GPIO_INTEDG_EDGE3_MASK) + +#define GPIO_INTEDG_EDGE4_MASK (0x10U) +#define GPIO_INTEDG_EDGE4_SHIFT (4U) +/*! EDGE4 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE4_SHIFT)) & GPIO_INTEDG_EDGE4_MASK) + +#define GPIO_INTEDG_EDGE5_MASK (0x20U) +#define GPIO_INTEDG_EDGE5_SHIFT (5U) +/*! EDGE5 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE5_SHIFT)) & GPIO_INTEDG_EDGE5_MASK) + +#define GPIO_INTEDG_EDGE6_MASK (0x40U) +#define GPIO_INTEDG_EDGE6_SHIFT (6U) +/*! EDGE6 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE6_SHIFT)) & GPIO_INTEDG_EDGE6_MASK) + +#define GPIO_INTEDG_EDGE7_MASK (0x80U) +#define GPIO_INTEDG_EDGE7_SHIFT (7U) +/*! EDGE7 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE7_SHIFT)) & GPIO_INTEDG_EDGE7_MASK) + +#define GPIO_INTEDG_EDGE8_MASK (0x100U) +#define GPIO_INTEDG_EDGE8_SHIFT (8U) +/*! EDGE8 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE8_SHIFT)) & GPIO_INTEDG_EDGE8_MASK) + +#define GPIO_INTEDG_EDGE9_MASK (0x200U) +#define GPIO_INTEDG_EDGE9_SHIFT (9U) +/*! EDGE9 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE9_SHIFT)) & GPIO_INTEDG_EDGE9_MASK) + +#define GPIO_INTEDG_EDGE10_MASK (0x400U) +#define GPIO_INTEDG_EDGE10_SHIFT (10U) +/*! EDGE10 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE10_SHIFT)) & GPIO_INTEDG_EDGE10_MASK) + +#define GPIO_INTEDG_EDGE11_MASK (0x800U) +#define GPIO_INTEDG_EDGE11_SHIFT (11U) +/*! EDGE11 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE11_SHIFT)) & GPIO_INTEDG_EDGE11_MASK) + +#define GPIO_INTEDG_EDGE12_MASK (0x1000U) +#define GPIO_INTEDG_EDGE12_SHIFT (12U) +/*! EDGE12 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE12_SHIFT)) & GPIO_INTEDG_EDGE12_MASK) + +#define GPIO_INTEDG_EDGE13_MASK (0x2000U) +#define GPIO_INTEDG_EDGE13_SHIFT (13U) +/*! EDGE13 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE13_SHIFT)) & GPIO_INTEDG_EDGE13_MASK) + +#define GPIO_INTEDG_EDGE14_MASK (0x4000U) +#define GPIO_INTEDG_EDGE14_SHIFT (14U) +/*! EDGE14 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE14_SHIFT)) & GPIO_INTEDG_EDGE14_MASK) + +#define GPIO_INTEDG_EDGE15_MASK (0x8000U) +#define GPIO_INTEDG_EDGE15_SHIFT (15U) +/*! EDGE15 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE15_SHIFT)) & GPIO_INTEDG_EDGE15_MASK) + +#define GPIO_INTEDG_EDGE16_MASK (0x10000U) +#define GPIO_INTEDG_EDGE16_SHIFT (16U) +/*! EDGE16 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE16_SHIFT)) & GPIO_INTEDG_EDGE16_MASK) + +#define GPIO_INTEDG_EDGE17_MASK (0x20000U) +#define GPIO_INTEDG_EDGE17_SHIFT (17U) +/*! EDGE17 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE17_SHIFT)) & GPIO_INTEDG_EDGE17_MASK) + +#define GPIO_INTEDG_EDGE18_MASK (0x40000U) +#define GPIO_INTEDG_EDGE18_SHIFT (18U) +/*! EDGE18 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE18_SHIFT)) & GPIO_INTEDG_EDGE18_MASK) + +#define GPIO_INTEDG_EDGE19_MASK (0x80000U) +#define GPIO_INTEDG_EDGE19_SHIFT (19U) +/*! EDGE19 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE19_SHIFT)) & GPIO_INTEDG_EDGE19_MASK) + +#define GPIO_INTEDG_EDGE20_MASK (0x100000U) +#define GPIO_INTEDG_EDGE20_SHIFT (20U) +/*! EDGE20 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE20_SHIFT)) & GPIO_INTEDG_EDGE20_MASK) + +#define GPIO_INTEDG_EDGE21_MASK (0x200000U) +#define GPIO_INTEDG_EDGE21_SHIFT (21U) +/*! EDGE21 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE21_SHIFT)) & GPIO_INTEDG_EDGE21_MASK) + +#define GPIO_INTEDG_EDGE22_MASK (0x400000U) +#define GPIO_INTEDG_EDGE22_SHIFT (22U) +/*! EDGE22 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE22_SHIFT)) & GPIO_INTEDG_EDGE22_MASK) + +#define GPIO_INTEDG_EDGE23_MASK (0x800000U) +#define GPIO_INTEDG_EDGE23_SHIFT (23U) +/*! EDGE23 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE23_SHIFT)) & GPIO_INTEDG_EDGE23_MASK) + +#define GPIO_INTEDG_EDGE24_MASK (0x1000000U) +#define GPIO_INTEDG_EDGE24_SHIFT (24U) +/*! EDGE24 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE24_SHIFT)) & GPIO_INTEDG_EDGE24_MASK) + +#define GPIO_INTEDG_EDGE25_MASK (0x2000000U) +#define GPIO_INTEDG_EDGE25_SHIFT (25U) +/*! EDGE25 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE25_SHIFT)) & GPIO_INTEDG_EDGE25_MASK) + +#define GPIO_INTEDG_EDGE26_MASK (0x4000000U) +#define GPIO_INTEDG_EDGE26_SHIFT (26U) +/*! EDGE26 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE26_SHIFT)) & GPIO_INTEDG_EDGE26_MASK) + +#define GPIO_INTEDG_EDGE27_MASK (0x8000000U) +#define GPIO_INTEDG_EDGE27_SHIFT (27U) +/*! EDGE27 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE27_SHIFT)) & GPIO_INTEDG_EDGE27_MASK) + +#define GPIO_INTEDG_EDGE28_MASK (0x10000000U) +#define GPIO_INTEDG_EDGE28_SHIFT (28U) +/*! EDGE28 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE28_SHIFT)) & GPIO_INTEDG_EDGE28_MASK) + +#define GPIO_INTEDG_EDGE29_MASK (0x20000000U) +#define GPIO_INTEDG_EDGE29_SHIFT (29U) +/*! EDGE29 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE29_SHIFT)) & GPIO_INTEDG_EDGE29_MASK) + +#define GPIO_INTEDG_EDGE30_MASK (0x40000000U) +#define GPIO_INTEDG_EDGE30_SHIFT (30U) +/*! EDGE30 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE30_SHIFT)) & GPIO_INTEDG_EDGE30_MASK) + +#define GPIO_INTEDG_EDGE31_MASK (0x80000000U) +#define GPIO_INTEDG_EDGE31_SHIFT (31U) +/*! EDGE31 - Edge or level mode select bits. + * 0b0..Level mode + * 0b1..Edge mode + */ +#define GPIO_INTEDG_EDGE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE31_SHIFT)) & GPIO_INTEDG_EDGE31_MASK) +/*! @} */ + +/* The count of GPIO_INTEDG */ +#define GPIO_INTEDG_COUNT (4U) + +/*! @name INTSTATA - Interrupt status for interrupt A */ +/*! @{ */ + +#define GPIO_INTSTATA_STATUS_MASK (0xFFFFFFFFU) +#define GPIO_INTSTATA_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status. + */ +#define GPIO_INTSTATA_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATA_STATUS_SHIFT)) & GPIO_INTSTATA_STATUS_MASK) +/*! @} */ + +/* The count of GPIO_INTSTATA */ +#define GPIO_INTSTATA_COUNT (4U) + +/*! @name INTSTATB - Interrupt status for interrupt B */ +/*! @{ */ + +#define GPIO_INTSTATB_STATUS_MASK (0xFFFFFFFFU) +#define GPIO_INTSTATB_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status + */ +#define GPIO_INTSTATB_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATB_STATUS_SHIFT)) & GPIO_INTSTATB_STATUS_MASK) +/*! @} */ + +/* The count of GPIO_INTSTATB */ +#define GPIO_INTSTATB_COUNT (4U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HSCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HSCMP_Peripheral_Access_Layer HSCMP Peripheral Access Layer + * @{ + */ + +/** HSCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control Register, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status Register, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status Register, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} HSCMP_Type; + +/* ---------------------------------------------------------------------------- + -- HSCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HSCMP_Register_Masks HSCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define HSCMP_VERID_FEATURE_MASK (0xFFFFU) +#define HSCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define HSCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_FEATURE_SHIFT)) & HSCMP_VERID_FEATURE_MASK) + +#define HSCMP_VERID_MINOR_MASK (0xFF0000U) +#define HSCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define HSCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_MINOR_SHIFT)) & HSCMP_VERID_MINOR_MASK) + +#define HSCMP_VERID_MAJOR_MASK (0xFF000000U) +#define HSCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define HSCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_MAJOR_SHIFT)) & HSCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define HSCMP_PARAM_DAC_RES_MASK (0xFU) +#define HSCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4 bit DAC + * 0b0001..6 bit DAC + * 0b0010..8 bit DAC + * 0b0011..10 bit DAC + * 0b0100..12 bit DAC + * 0b0101..14 bit DAC + * 0b0110..16 bit DAC + */ +#define HSCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_PARAM_DAC_RES_SHIFT)) & HSCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define HSCMP_CCR0_CMP_EN_MASK (0x1U) +#define HSCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define HSCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_CMP_EN_SHIFT)) & HSCMP_CCR0_CMP_EN_MASK) + +#define HSCMP_CCR0_CMP_STOP_EN_MASK (0x2U) +#define HSCMP_CCR0_CMP_STOP_EN_SHIFT (1U) +/*! CMP_STOP_EN - Comparator STOP Mode Enable + * 0b0..Disable the analog comparator regardless of CMP_EN. + * 0b1..Allow the analog comparator to be enabled by CMP_EN. + */ +#define HSCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_CMP_STOP_EN_SHIFT)) & HSCMP_CCR0_CMP_STOP_EN_MASK) + +#define HSCMP_CCR0_LINKEN_MASK (0x4U) +#define HSCMP_CCR0_LINKEN_SHIFT (2U) +/*! LINKEN - CMP-to-DAC Link Enable + * 0b0..Disable the CMP-to-DAC link: enabling or disabling the DAC is independent from enabling or disabling the CMP. + * 0b1..Enable the CMP-to-DAC link: the DAC enable/disable is controlled by the CMP_EN bit instead of DCR[DAC_EN]. + */ +#define HSCMP_CCR0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_LINKEN_SHIFT)) & HSCMP_CCR0_LINKEN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define HSCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define HSCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define HSCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_EN_SHIFT)) & HSCMP_CCR1_WINDOW_EN_MASK) + +#define HSCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define HSCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define HSCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_SAMPLE_EN_SHIFT)) & HSCMP_CCR1_SAMPLE_EN_MASK) + +#define HSCMP_CCR1_DMA_EN_MASK (0x4U) +#define HSCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define HSCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_DMA_EN_SHIFT)) & HSCMP_CCR1_DMA_EN_MASK) + +#define HSCMP_CCR1_COUT_INV_MASK (0x8U) +#define HSCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define HSCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_INV_SHIFT)) & HSCMP_CCR1_COUT_INV_MASK) + +#define HSCMP_CCR1_COUT_SEL_MASK (0x10U) +#define HSCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define HSCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_SEL_SHIFT)) & HSCMP_CCR1_COUT_SEL_MASK) + +#define HSCMP_CCR1_COUT_PEN_MASK (0x20U) +#define HSCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define HSCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_PEN_SHIFT)) & HSCMP_CCR1_COUT_PEN_MASK) + +#define HSCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define HSCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value + * 0b1..COUTA is defined by the COUTA_OW bit + */ +#define HSCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUTA_OWEN_SHIFT)) & HSCMP_CCR1_COUTA_OWEN_MASK) + +#define HSCMP_CCR1_COUTA_OW_MASK (0x80U) +#define HSCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define HSCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUTA_OW_SHIFT)) & HSCMP_CCR1_COUTA_OW_MASK) + +#define HSCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define HSCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define HSCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_INV_SHIFT)) & HSCMP_CCR1_WINDOW_INV_MASK) + +#define HSCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define HSCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define HSCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_CLS_SHIFT)) & HSCMP_CCR1_WINDOW_CLS_MASK) + +#define HSCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define HSCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define HSCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_EVT_SEL_SHIFT)) & HSCMP_CCR1_EVT_SEL_MASK) + +#define HSCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define HSCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define HSCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_FILT_CNT_SHIFT)) & HSCMP_CCR1_FILT_CNT_MASK) + +#define HSCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define HSCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period + */ +#define HSCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_FILT_PER_SHIFT)) & HSCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define HSCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define HSCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power(speed) comparison mode + * 0b1..High power(speed) comparison mode + */ +#define HSCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_CMP_HPMD_SHIFT)) & HSCMP_CCR2_CMP_HPMD_MASK) + +#define HSCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define HSCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disable (Mode is determined by CMP_HPMD.) + * 0b1..Enable + */ +#define HSCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_CMP_NPMD_SHIFT)) & HSCMP_CCR2_CMP_NPMD_MASK) + +#define HSCMP_CCR2_OFFSET_MASK (0x4U) +#define HSCMP_CCR2_OFFSET_SHIFT (2U) +/*! OFFSET - Comparator Offset Control + * 0b0..Level 0: The hysteresis selected by HYSTCTR is valid for both directions (rising and falling). + * 0b1..Level 1: Hysteresis does not apply when INP (input-plus) crosses INM (input-minus) in the rising + * direction or when INM crosses INP in the falling direction. Hysteresis still applies for INP crossing INM in the + * falling direction. + */ +#define HSCMP_CCR2_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_OFFSET_SHIFT)) & HSCMP_CCR2_OFFSET_MASK) + +#define HSCMP_CCR2_HYSTCTR_MASK (0x30U) +#define HSCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ +#define HSCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_HYSTCTR_SHIFT)) & HSCMP_CCR2_HYSTCTR_MASK) + +#define HSCMP_CCR2_PSEL_MASK (0x70000U) +#define HSCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define HSCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_PSEL_SHIFT)) & HSCMP_CCR2_PSEL_MASK) + +#define HSCMP_CCR2_MSEL_MASK (0x700000U) +#define HSCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define HSCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_MSEL_SHIFT)) & HSCMP_CCR2_MSEL_MASK) + +#define HSCMP_CCR2_INPSEL_MASK (0x3000000U) +#define HSCMP_CCR2_INPSEL_SHIFT (24U) +/*! INPSEL - Input Plus Select + * 0b00..IN0: from the 8-bit DAC output + * 0b01..IN1: from the analog 8-1 mux + * 0b10..Reserved + * 0b11..Reserved + */ +#define HSCMP_CCR2_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_INPSEL_SHIFT)) & HSCMP_CCR2_INPSEL_MASK) + +#define HSCMP_CCR2_INMSEL_MASK (0x30000000U) +#define HSCMP_CCR2_INMSEL_SHIFT (28U) +/*! INMSEL - Input Minus Select + * 0b00..IN0: from the 8-bit DAC output + * 0b01..IN1: from the analog 8-1 mux + * 0b10..Reserved + * 0b11..Reserved + */ +#define HSCMP_CCR2_INMSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_INMSEL_SHIFT)) & HSCMP_CCR2_INMSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control Register */ +/*! @{ */ + +#define HSCMP_DCR_DAC_EN_MASK (0x1U) +#define HSCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define HSCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_EN_SHIFT)) & HSCMP_DCR_DAC_EN_MASK) + +#define HSCMP_DCR_DAC_HPMD_MASK (0x2U) +#define HSCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode Select + * 0b0..Disable + * 0b1..Enable + */ +#define HSCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_HPMD_SHIFT)) & HSCMP_DCR_DAC_HPMD_MASK) + +#define HSCMP_DCR_VRSEL_MASK (0x100U) +#define HSCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..vrefh0 + * 0b1..vrefh1 + */ +#define HSCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_VRSEL_SHIFT)) & HSCMP_DCR_VRSEL_MASK) + +#define HSCMP_DCR_DACOE_MASK (0x8000U) +#define HSCMP_DCR_DACOE_SHIFT (15U) +/*! DACOE - DAC Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define HSCMP_DCR_DACOE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DACOE_SHIFT)) & HSCMP_DCR_DACOE_MASK) + +#define HSCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define HSCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select + */ +#define HSCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_DATA_SHIFT)) & HSCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ + +#define HSCMP_IER_CFR_IE_MASK (0x1U) +#define HSCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disable + * 0b1..Enable: Assert an interrupt when CFR is set. + */ +#define HSCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_CFR_IE_SHIFT)) & HSCMP_IER_CFR_IE_MASK) + +#define HSCMP_IER_CFF_IE_MASK (0x2U) +#define HSCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disable + * 0b1..Enable: Assert an interrupt when CFF is set. + */ +#define HSCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_CFF_IE_SHIFT)) & HSCMP_IER_CFF_IE_MASK) + +#define HSCMP_IER_RRF_IE_MASK (0x4U) +#define HSCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disable + * 0b1..Enable: Assert an interrupt when the comparison result changes for a given channel. + */ +#define HSCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_RRF_IE_SHIFT)) & HSCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status Register */ +/*! @{ */ + +#define HSCMP_CSR_CFR_MASK (0x1U) +#define HSCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define HSCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_CFR_SHIFT)) & HSCMP_CSR_CFR_MASK) + +#define HSCMP_CSR_CFF_MASK (0x2U) +#define HSCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define HSCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_CFF_SHIFT)) & HSCMP_CSR_CFF_MASK) + +#define HSCMP_CSR_RRF_MASK (0x4U) +#define HSCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define HSCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_RRF_SHIFT)) & HSCMP_CSR_RRF_MASK) + +#define HSCMP_CSR_COUT_MASK (0x100U) +#define HSCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output + */ +#define HSCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_COUT_SHIFT)) & HSCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define HSCMP_RRCR0_RR_EN_MASK (0x1U) +#define HSCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_EN_SHIFT)) & HSCMP_RRCR0_RR_EN_MASK) + +#define HSCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define HSCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clocks + * 0b01..1 clocks + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define HSCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_NSAM_SHIFT)) & HSCMP_RRCR0_RR_NSAM_MASK) + +#define HSCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define HSCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define HSCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_INITMOD_SHIFT)) & HSCMP_RRCR0_RR_INITMOD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define HSCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define HSCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH0EN_SHIFT)) & HSCMP_RRCR1_RR_CH0EN_MASK) + +#define HSCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define HSCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH1EN_SHIFT)) & HSCMP_RRCR1_RR_CH1EN_MASK) + +#define HSCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define HSCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH2EN_SHIFT)) & HSCMP_RRCR1_RR_CH2EN_MASK) + +#define HSCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define HSCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH3EN_SHIFT)) & HSCMP_RRCR1_RR_CH3EN_MASK) + +#define HSCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define HSCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH4EN_SHIFT)) & HSCMP_RRCR1_RR_CH4EN_MASK) + +#define HSCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define HSCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH5EN_SHIFT)) & HSCMP_RRCR1_RR_CH5EN_MASK) + +#define HSCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define HSCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH6EN_SHIFT)) & HSCMP_RRCR1_RR_CH6EN_MASK) + +#define HSCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define HSCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define HSCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH7EN_SHIFT)) & HSCMP_RRCR1_RR_CH7EN_MASK) + +#define HSCMP_RRCR1_FIXP_MASK (0x10000U) +#define HSCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the Plus port. Sweep only the inputs to the Minus port. + * 0b1..Fix the Minus port. Sweep only the inputs to the Plus port. + */ +#define HSCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_FIXP_SHIFT)) & HSCMP_RRCR1_FIXP_MASK) + +#define HSCMP_RRCR1_FIXCH_MASK (0x700000U) +#define HSCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define HSCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_FIXCH_SHIFT)) & HSCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status Register */ +/*! @{ */ + +#define HSCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define HSCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 + */ +#define HSCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH0OUT_SHIFT)) & HSCMP_RRCSR_RR_CH0OUT_MASK) + +#define HSCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define HSCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 + */ +#define HSCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH1OUT_SHIFT)) & HSCMP_RRCSR_RR_CH1OUT_MASK) + +#define HSCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define HSCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 + */ +#define HSCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH2OUT_SHIFT)) & HSCMP_RRCSR_RR_CH2OUT_MASK) + +#define HSCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define HSCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 + */ +#define HSCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH3OUT_SHIFT)) & HSCMP_RRCSR_RR_CH3OUT_MASK) + +#define HSCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define HSCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 + */ +#define HSCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH4OUT_SHIFT)) & HSCMP_RRCSR_RR_CH4OUT_MASK) + +#define HSCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define HSCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 + */ +#define HSCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH5OUT_SHIFT)) & HSCMP_RRCSR_RR_CH5OUT_MASK) + +#define HSCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define HSCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 + */ +#define HSCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH6OUT_SHIFT)) & HSCMP_RRCSR_RR_CH6OUT_MASK) + +#define HSCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define HSCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 + */ +#define HSCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH7OUT_SHIFT)) & HSCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status Register */ +/*! @{ */ + +#define HSCMP_RRSR_RR_CH0F_MASK (0x1U) +#define HSCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH0F_SHIFT)) & HSCMP_RRSR_RR_CH0F_MASK) + +#define HSCMP_RRSR_RR_CH1F_MASK (0x2U) +#define HSCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH1F_SHIFT)) & HSCMP_RRSR_RR_CH1F_MASK) + +#define HSCMP_RRSR_RR_CH2F_MASK (0x4U) +#define HSCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH2F_SHIFT)) & HSCMP_RRSR_RR_CH2F_MASK) + +#define HSCMP_RRSR_RR_CH3F_MASK (0x8U) +#define HSCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH3F_SHIFT)) & HSCMP_RRSR_RR_CH3F_MASK) + +#define HSCMP_RRSR_RR_CH4F_MASK (0x10U) +#define HSCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH4F_SHIFT)) & HSCMP_RRSR_RR_CH4F_MASK) + +#define HSCMP_RRSR_RR_CH5F_MASK (0x20U) +#define HSCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH5F_SHIFT)) & HSCMP_RRSR_RR_CH5F_MASK) + +#define HSCMP_RRSR_RR_CH6F_MASK (0x40U) +#define HSCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH6F_SHIFT)) & HSCMP_RRSR_RR_CH6F_MASK) + +#define HSCMP_RRSR_RR_CH7F_MASK (0x80U) +#define HSCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..Not different + * 0b1..Different + */ +#define HSCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH7F_SHIFT)) & HSCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define HSCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define HSCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of sample clocks + */ +#define HSCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & HSCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define HSCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define HSCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin internal timer enable. + * 0b0..Round-Robin internal timer is disabled. + * 0b1..Round-Robin internal timer is enabled. + */ +#define HSCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR2_RR_TIMER_EN_SHIFT)) & HSCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group HSCMP_Register_Masks */ + + +/* HSCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral HSCMP0 base address */ + #define HSCMP0_BASE (0x500B3000u) + /** Peripheral HSCMP0 base address */ + #define HSCMP0_BASE_NS (0x400B3000u) + /** Peripheral HSCMP0 base pointer */ + #define HSCMP0 ((HSCMP_Type *)HSCMP0_BASE) + /** Peripheral HSCMP0 base pointer */ + #define HSCMP0_NS ((HSCMP_Type *)HSCMP0_BASE_NS) + /** Peripheral HSCMP1 base address */ + #define HSCMP1_BASE (0x500B7000u) + /** Peripheral HSCMP1 base address */ + #define HSCMP1_BASE_NS (0x400B7000u) + /** Peripheral HSCMP1 base pointer */ + #define HSCMP1 ((HSCMP_Type *)HSCMP1_BASE) + /** Peripheral HSCMP1 base pointer */ + #define HSCMP1_NS ((HSCMP_Type *)HSCMP1_BASE_NS) + /** Peripheral HSCMP2 base address */ + #define HSCMP2_BASE (0x500BA000u) + /** Peripheral HSCMP2 base address */ + #define HSCMP2_BASE_NS (0x400BA000u) + /** Peripheral HSCMP2 base pointer */ + #define HSCMP2 ((HSCMP_Type *)HSCMP2_BASE) + /** Peripheral HSCMP2 base pointer */ + #define HSCMP2_NS ((HSCMP_Type *)HSCMP2_BASE_NS) + /** Array initializer of HSCMP peripheral base addresses */ + #define HSCMP_BASE_ADDRS { HSCMP0_BASE, HSCMP1_BASE, HSCMP2_BASE } + /** Array initializer of HSCMP peripheral base pointers */ + #define HSCMP_BASE_PTRS { HSCMP0, HSCMP1, HSCMP2 } + /** Array initializer of HSCMP peripheral base addresses */ + #define HSCMP_BASE_ADDRS_NS { HSCMP0_BASE_NS, HSCMP1_BASE_NS, HSCMP2_BASE_NS } + /** Array initializer of HSCMP peripheral base pointers */ + #define HSCMP_BASE_PTRS_NS { HSCMP0_NS, HSCMP1_NS, HSCMP2_NS } +#else + /** Peripheral HSCMP0 base address */ + #define HSCMP0_BASE (0x400B3000u) + /** Peripheral HSCMP0 base pointer */ + #define HSCMP0 ((HSCMP_Type *)HSCMP0_BASE) + /** Peripheral HSCMP1 base address */ + #define HSCMP1_BASE (0x400B7000u) + /** Peripheral HSCMP1 base pointer */ + #define HSCMP1 ((HSCMP_Type *)HSCMP1_BASE) + /** Peripheral HSCMP2 base address */ + #define HSCMP2_BASE (0x400BA000u) + /** Peripheral HSCMP2 base pointer */ + #define HSCMP2 ((HSCMP_Type *)HSCMP2_BASE) + /** Array initializer of HSCMP peripheral base addresses */ + #define HSCMP_BASE_ADDRS { HSCMP0_BASE, HSCMP1_BASE, HSCMP2_BASE } + /** Array initializer of HSCMP peripheral base pointers */ + #define HSCMP_BASE_PTRS { HSCMP0, HSCMP1, HSCMP2 } +#endif +/** Interrupt vectors for the HSCMP peripheral type */ +#define HSCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/*! + * @} + */ /* end of group HSCMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration Register, offset: 0x800 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set Register, offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out Register, offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock Divider Register, offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master Control Register, offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master Timing Register, offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Master Data Register, offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave Control Register, offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Slave Data Register, offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave Address Register, array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for Address 0 Register, offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor Receiver Data Register, offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable + * 0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not + * changed, but the Master function is internally reset. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable + * 0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not + * changed, but the Slave function is internally reset. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable + * 0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration + * settings are not changed, but the Monitor function is internally reset. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable + * 0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset. + * 0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used + * when non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read + * all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High Speed mode Capable enable + * 0b0..Fast mode Plus enable + * 0b1..High Speed mode enable + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave. + * 0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag + * 0b0..No Arbitration Loss has occurred + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and has gone into an idle state. Software can respond by doing + * nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle). + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start + * or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and + * gone into an idle state; no action is required. A request for a Start could be made, or software could + * attempt to make sure that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending + * 0b0..In progress. The Slave function does not currently need software service. + * 0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE). + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State + * 0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (in Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode). + * 0b11..Reserved + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index T + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is + * currently selected. That information is in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See SLVSEL for details about when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching + * not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag + * 0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set Register */ +/*! @{ */ + +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear Register */ +/*! @{ */ + +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear + * 0b0..No effect on interrupt + * 0b1..Clears the interrupt bit in INTENSET register + */ +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out Register */ +/*! @{ */ + +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, the bottom 4 bits + */ +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value + * 0b000000000000..A time-out will occur after 16 counts of the I2C function clock. + * 0b000000000001..A time-out will occur after 32 counts of the I2C function clock. + * 0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock. + */ +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider Register */ +/*! @{ */ + +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Divider Value + * 0b0000000000000000..FCLK is used directly by the I2C. + * 0b0000000000000001..FCLK is divided by 2 before being used by the I2C. + * 0b0000000000000010..FCLK is divided by 3 before being used by the I2C. + * 0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C. + */ +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status Register */ +/*! @{ */ + +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag + * 0b0..Not active + * 0b1..Active + */ +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master Control Register */ +/*! @{ */ + +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue(write-only) + * 0b0..No effect + * 0b1..Continue. Informs the Master function to continue to the next operation. This action must done after + * writing transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control(write-only) + * 0b0..No effect + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control(write-only) + * 0b0..No effect + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (in Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master Timing Register */ +/*! @{ */ + +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time + * 0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Master Data Register */ +/*! @{ */ + +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register + */ +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave Control Register */ +/*! @{ */ + +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue + * 0b0..No effect + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING] + * flag. This must be done after writing transmit data, reading received data, or any other housekeeping + * related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be + * set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK + * 0b0..No effect + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a + * matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set, + * then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - Automatic Match Read + * 0b0..In Automatic Mode, the expected next operation is an I2C write. + * 0b1..In Automatic Mode, the expected next operation is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Slave Data Register */ +/*! @{ */ + +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register + */ +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave Address Register */ +/*! @{ */ + +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored. Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. + */ +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address + * matches SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */ +/*! @{ */ + +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0 + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0 + */ +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor Receiver Data Register */ +/*! @{ */ + +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data + */ +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral Identification Register */ +/*! @{ */ + +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture + */ +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation + */ +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation + */ +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function + */ +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration Register 1 for the Primary Channel Pair, offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration Register 2 for the Primary Channel Pair, offset: 0xC04 */ + __IO uint32_t STAT; /**< Status Register for the Primary Channel Pair, offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock Divider, offset: 0xC1C */ + struct { /* offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG1; /**< Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3, array offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG2; /**< Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3, array offset: 0xC24, array step: 0x20 */ + __I uint32_t PSTAT; /**< Status Register for Channel Pair 1..Status Register for Channel Pair 3, array offset: 0xC28, array step: 0x20 */ + uint8_t RESERVED_0[20]; + } SECCHANNEL[3]; + uint8_t RESERVED_2[384]; + __IO uint32_t FIFOCFG; /**< FIFO Configuration and Enable, offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO Status, offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO Trigger Settings, offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable Set and Read, offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear and Read, offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status, offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO Write Data, offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO Write Data for Upper Data Bits, offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO Read Data, offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO Read Data for Upper Data Bits, offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO Data Read for Upper Data Bits with No FIFO Pop, offset: 0xE44 */ + __I uint32_t FIFOSIZE; /**< FIFO Size Register, offset: 0xE48 */ + __IO uint32_t FIFORXTIMEOUTCFG; /**< FIFO Receive Timeout Configuration, offset: 0xE4C */ + __I uint32_t FIFORXTIMEOUTCNT; /**< FIFO Receive Timeout Counter, offset: 0xE50 */ + uint8_t RESERVED_7[424]; + __I uint32_t ID; /**< I2S Module Identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration Register 1 for the Primary Channel Pair */ +/*! @{ */ + +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data Flow Pause + * 0b0..Normal operation + * 0b1..Pause + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Pair Count + * 0b00..One Pair + * 0b01..Two Pairs + * 0b10..Three Pairs + * 0b11..Four Pairs + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master/Slave Configuration Selection + * 0b00..Normal Slave Mode + * 0b01..WS Synchronized Master Mode + * 0b10..Master Using an Existing SCK Mode + * 0b11..Normal Master Mode + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Mode + * 0b00..Classic Mode + * 0b01..DSP mode WS 50% duty cycle + * 0b10..DSP mode WS 1 clock + * 0b11..DSP mode WS 1 data + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right Channel Low + * 0b0..Right high + * 0b1..Right low + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left-Justify Data + * 0b0..Right-justified + * 0b1..Left-justified + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single Channel Mode + * 0b0..Dual channel + * 0b1..Single channel + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) + +#define I2S_CFG1_PDMDATA_MASK (0x800U) +#define I2S_CFG1_PDMDATA_SHIFT (11U) +/*! PDMDATA - PDM Data Selection + * 0b0..Normal Operation + * 0b1..DMIC subsystem + */ +#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) + +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK Polarity + * 0b0..Falling edge + * 0b1..Rising edge + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length + * 0b00011..Data is 4 bits in length. + * 0b00100..Data is 5 bits in length. + * 0b00111..Data is 8 bits in length. + * 0b11110..Data is 31 bits in length. + * 0b11111..Data is 32 bits in length. + */ +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration Register 2 for the Primary Channel Pair */ +/*! @{ */ + +#define I2S_CFG2_FRAMELEN_MASK (0x7FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length + * 0b00000000011..Frame is 4 bits in total length + * 0b00000000100..Frame is 5 bits in total length + * 0b00111111111..Frame is 512 bits in total length + * 0b11111111111..Frame is 2048 bits in total length + */ +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + +#define I2S_CFG2_POSITION_MASK (0x7FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position + * 0b00000000000..Data begins at bit position 0 (the first bit position) within the frame or WS phase + * 0b00000000001..Data begins at bit position 1 within the frame or WS phase + * 0b00000000010..Data begins at bit position 2 within the frame or WS phase + */ +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status Register for the Primary Channel Pair */ +/*! @{ */ + +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy Status + * 0b0..Idle + * 0b1..Busy + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error + * 0b0..No error + * 0b1..Error + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right Indication + * 0b0..Left channel + * 0b1..Right channel + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused + * 0b0..Not Paused + * 0b1..Paused + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock Divider */ +/*! @{ */ + +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - Divider + * 0b000000000000..FCLK is used directly. + * 0b000000000001..FCLK is divided by 2. + * 0b000000000010..FCLK is divided by 3. + * 0b111111111111..FCLK is divided by 4,096. + */ +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name SECCHANNEL_PCFG1 - Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3 */ +/*! @{ */ + +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) +/*! PAIRENABLE - Pair Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) + +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single Channel Mode + * 0b0..Dual Channel + * 0b1..Single Channel + */ +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG1 */ +#define I2S_SECCHANNEL_PCFG1_COUNT (3U) + +/*! @name SECCHANNEL_PCFG2 - Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3 */ +/*! @{ */ + +#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) +#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position + */ +#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG2 */ +#define I2S_SECCHANNEL_PCFG2_COUNT (3U) + +/*! @name SECCHANNEL_PSTAT - Status Register for Channel Pair 1..Status Register for Channel Pair 3 */ +/*! @{ */ + +#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) +#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) +/*! BUSY - Busy Status for Channel Pair + * 0b0..Idle. The transmitter/receiver for this channel pair is currently idle. + * 0b1..Busy. The transmitter/receiver for this channel pair is currently processing data. + */ +#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) + +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Save Frame Error Flag + * 0b0..No Error + * 0b1..Error + */ +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) + +#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) +#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) +/*! LR - Left/Right Indication + * 0b0..Left channel + * 0b1..Right channel + */ +#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) + +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused Status Flag + * 0b0..Data Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in + * force, waiting for an allowed pause point. Refer to the description in CFG1[DATAPAUSE]. + * 0b1..Data Paused. A data pause has been requested and is now in force. + */ +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PSTAT */ +#define I2S_SECCHANNEL_PSTAT_COUNT (3U) + +/*! @name FIFOCFG - FIFO Configuration and Enable */ +/*! @{ */ + +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable Transmit FIFO + * 0b0..Disabled Transmit. The transmit FIFO is not enabled. + * 0b1..Enabled transmit. The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable Receive FIFO + * 0b0..Disabled. The receive FIFO is not enabled. + * 0b1..Enabled. The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S Empty 0 + * 0b0..Last value + * 0b1..Zero + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing Format 48-bit data + * 0b0..Bits_24 + * 0b1..Bits_32_16 + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO Size Configuration + * 0b10..Size 32 Bits + * 0b11..Size 48 Bits + */ +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA Transmit + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA Receive + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for Transmit FIFO Level + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for Receive FIFO Level + * 0b0..Only enabled interrupts wake up the device from reduced power modes. + * 0b1..A device wake-up for DMA occurs if the receive FIFO level reaches the value specified by FIFOTRIG[RXLVL], + * even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) + +#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) +#define I2S_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for Debug Reads + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read causes the FIFO to pop. + */ +#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO Status */ +/*! @{ */ + +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO Error + * 0b0..No transmit FIFO error occured + * 0b1..Transmit FIFO error occured + */ +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO Error + * 0b0..No receive FIFO error occured + * 0b1..Receive FIFO error occured + */ +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral Interrupt + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO Empty + * 0b0..Transmit FIFO is not empty + * 0b1..Transmit FIFO is empty; however, the peripheral may still be processing the last piece of data. + */ +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO Not Full + * 0b0..Transmit FIFO is full, and another write would cause an overflow + * 0b1..Transmit FIFO is not full, so more data can be written + */ +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO Not Empty + * 0b0..Receive FIFO is empty + * 0b1..Receive FIFO is not empty, so data can be read. + */ +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO Full + * 0b0..Receive FIFO is not full + * 0b1..Receive FIFO is full + */ +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO Current Level + * 0b00000..TX FIFO is empty + */ +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO Current Level + * 0b00000..RX FIFO is empty + */ +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) + +#define I2S_FIFOSTAT_RXTIMEOUT_MASK (0x1000000U) +#define I2S_FIFOSTAT_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive FIFO Timeout + * 0b0..RX FIFO on + * 0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register. + */ +#define I2S_FIFOSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOSTAT_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO Trigger Settings */ +/*! @{ */ + +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO Level Trigger Enable + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger generates if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO Level Trigger Enable + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger generates if the receive FIFO level reaches the value specified by the RXLVL. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO Level Trigger Point + * 0b0000..Trigger when the TX FIFO becomes empty. + * 0b0001..Trigger when the TX FIFO level decreases to one entry. + * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full). + */ +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO Level Trigger Point + * 0b0000..Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty). + * 0b0001..Trigger when the RX FIFO has received 2 entries. + * 0b1111..Trigger when the RX FIFO has received 16 entries (the FIFO has become full). + */ +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO Interrupt Enable Set and Read */ +/*! @{ */ + +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Transmit Error Interrupt + * 0b0..Disabled. No interrupt generates for a transmit error. + * 0b1..Enabled. An interrupt generates when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Receive Error Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit Level Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Receive Level Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) + +#define I2S_FIFOINTENSET_RXTIMEOUT_MASK (0x1000000U) +#define I2S_FIFOINTENSET_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout + * 0b0..No RX interrupt will be generated. + * 0b1..Asserts RX interrupt if RX FIFO Timeout event occurs. + */ +#define I2S_FIFOINTENSET_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENSET_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear and Read */ +/*! @{ */ + +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Transmit Error Interrupt Clear + * 0b0..Interrupt is not cleared. + * 0b1..Interrupt is cleared. + */ +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Receive Error Interrupt Clear + * 0b0..Interrupt is not cleared. + * 0b1..Interrupt is cleared. + */ +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit Level Interrupt Clear + * 0b0..Interrupt is not cleared. + * 0b1..Interrupt is cleared. + */ +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Receive Level Interrupt Clear + * 0b0..Interrupt is not cleared. + * 0b1..Interrupt is cleared. + */ +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) + +#define I2S_FIFOINTENCLR_RXTIMEOUT_MASK (0x1000000U) +#define I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define I2S_FIFOINTENCLR_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENCLR_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO Interrupt Status */ +/*! @{ */ + +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO Error Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO Error Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) + +#define I2S_FIFOINTSTAT_RXTIMEOUT_MASK (0x1000000U) +#define I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout Status + * 0b0..Not pending + * 0b1..Pending + */ +#define I2S_FIFOINTSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOINTSTAT_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO Write Data */ +/*! @{ */ + +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit Data to the FIFO + */ +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO Write Data for Upper Data Bits */ +/*! @{ */ + +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit Data to the FIFO + */ +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO Read Data */ +/*! @{ */ + +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO Read Data for Upper Data Bits */ +/*! @{ */ + +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */ +/*! @{ */ + +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO Data Read for Upper Data Bits with No FIFO Pop */ +/*! @{ */ + +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO Size Register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - FIFO Size + */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */ +/*! @{ */ + +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU) +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U) +/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler + */ +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK) + +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U) +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U) +/*! RXTIMEOUT_VALUE - Receive Timeout Value + */ +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK) + +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U) +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U) +/*! RXTIMEOUT_EN - Receive Timeout Enable + * 0b0..Disable RX FIFO timeout + * 0b1..Enable RX FIFO timeout + */ +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK) + +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U) +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U) +/*! RXTIMEOUT_COW - Receive Timeout Continue On Write + * 0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO. + * 0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO. + */ +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK) + +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U) +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U) +/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty + * 0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty. + * 0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty. + */ +#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK) +/*! @} */ + +/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */ +/*! @{ */ + +#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU) +#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U) +/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value + */ +#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK) +/*! @} */ + +/*! @name ID - I2S Module Identification */ +/*! @{ */ + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture + */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor Revision + */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major Revision + */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +/*! ID - Module Identifier + */ +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Master Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Slave Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Slave Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Slave Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Slave Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Slave Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Slave Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Slave Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Slave DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Slave Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Slave Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Slave Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Slave Write Data Half-word, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Slave Write Data Half-word End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Slave Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Slave Read Data Half-word, offset: 0x48 */ + uint8_t RESERVED_2[16]; + __I uint32_t SCAPABILITIES2; /**< Slave Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Slave Capabilities, offset: 0x60 */ + __IO uint32_t SDYNADDR; /**< Slave Dynamic Address, offset: 0x64 */ + __IO uint32_t SMAXLIMITS; /**< Slave Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Slave ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Slave ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Slave Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Slave Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Slave Message Map Address, offset: 0x7C */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCTRL; /**< Master Main Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Master In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Master Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Master Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Master Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Master Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Master DMA Control, offset: 0xA0 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Master Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Master Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Master Write Data Half-word, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Master Write Data Byte End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Master Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_5[4]; + __I uint32_t MRDATAH; /**< Master Read Data Half-word, offset: 0xC8 */ + __O uint32_t MWDATAB1; /**< Byte-only Write Byte Data (to bus), offset: 0xCC */ + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Master Write Message in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Master Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Master Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Master Write Message in DDR mode, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Master Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Master Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_6[4]; + __IO uint32_t MDYNADDR; /**< Master Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_7[52]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + uint8_t RESERVED_8[32]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_9[3764]; + __I uint32_t SID; /**< Slave Module ID, offset: 0xFFC */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Master Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Master enable + * 0b00..MASTER_OFF + * 0b01..MASTER_ON + * 0b10..MASTER_CAPABLE + * 0b11..I2C_MASTER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..NONE + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open drain stop + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-pull baud rate + */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull low + */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open drain baud rate + */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew + */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C baud rate + */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Slave Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Slave enable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not acknowledge + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match START or STOP + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - S0/S1 errors ignore + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_DDROK_MASK (0x10U) +#define I3C_SCONFIG_DDROK_SHIFT (4U) +/*! DDROK - DDR OK + */ +#define I3C_SCONFIG_DDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK) + +#define I3C_SCONFIG_IDRAND_MASK (0x100U) +#define I3C_SCONFIG_IDRAND_SHIFT (8U) +/*! IDRAND - ID random + */ +#define I3C_SCONFIG_IDRAND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus available match + */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static address + */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Slave Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not stop + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status message + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status request read + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status request write + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit buffer is not full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - DACHG + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error warning + */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate command match + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code handled + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event details + * 0b00..NONE + * 0b01..NO_REQUEST + * 0b10..NACKED + * 0b11..ACKED + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts are disabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Master requests are disabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join is disabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity state from Common Command Codes (CCC) + * 0b00..NO_LATENCY + * 0b01..LATENCY_1MS + * 0b10..LATENCY_100MS + * 0b11..LATENCY_10S + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time control + * 0b00..NO_TIME_CONTROL + * 0b01.. + * 0b10..ASYNC_MODE + * 0b11.. + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Slave Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - EVENT + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..MASTER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt data + */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending interrupt + */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity state (of slave) + */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor information + */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Slave Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start interrupt enable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match interrupt enable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop interrupt enable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive interrupt enable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit interrupt enable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic address change interrupt enable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error/warning interrupt enable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event interrupt enable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) +/*! @} */ + +/*! @name SINTCLR - Slave Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START interrupt enable clear + */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED interrupt enable clear + */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP interrupt enable clear + */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND interrupt enable clear + */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND interrupt enable clear + */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG interrupt enable clear + */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC interrupt enable clear + */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN interrupt enable clear + */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED interrupt enable clear + */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED interrupt enable clear + */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT interrupt enable clear + */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) +/*! @} */ + +/*! @name SINTMASKED - Slave Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START interrupt mask + */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED interrupt mask + */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP interrupt mask + */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND interrupt mask + */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND interrupt mask + */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG interrupt mask + */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC interrupt mask + */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN interrupt mask + */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED interrupt mask + */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED interrupt mask + */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT interrupt mask + */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) +/*! @} */ + +/*! @name SERRWARN - Slave Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun error + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun error + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated error + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid start error + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR parity error + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR parity error + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC error + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - S0 or S1 error + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-read error + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-write error + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Slave DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-bus) trigger + * 0b00..DMA not used + * 0b01..DMA is enabled for 1 frame + * 0b10..DMA enable + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-bus) trigger + * 0b00..NOT_USED + * 0b01..ENABLE_ONE_FRAME + * 0b10..ENABLE + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA operations + * 0b00, 0b01..BYTE, Default = 1 + * 0b10..HALF_WORD + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name SDATACTRL - Slave Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush the to-bus buffer/FIFO + */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flushes the from-bus buffer/FIFO + */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Trigger level for TX FIFO emptiness + * 0b00..Trigger on empty + * 0b01..Trigger on ¼ full or less + * 0b10..Trigger on .5 full or less + * 0b11..Trigger on 1 less than full or less (Default) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Trigger level for RX FIFO fullness + * 0b00..Trigger on not empty + * 0b01..Trigger on ¼ or more full + * 0b10..Trigger on .5 or more full + * 0b11..Trigger on 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of bytes in TX + */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of bytes in RX + */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - TX is full + * 0b1..TX is full + * 0b0..TX is not full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - RX is empty + * 0b1..RX is empty + * 0b0..RX is not empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Slave Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - The data byte to send to the master + */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End also + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Slave Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - The data byte to send to the master + */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Slave Write Data Half-word */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - The 1st byte to send to the master + */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - The 2nd byte to send to the master + */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of message + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Slave Write Data Half-word End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - The 1st byte to send to the master + */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - The 2nd byte to send to the master + */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Slave Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Byte read from the master + */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Slave Read Data Half-word */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - The 1st byte read from the slave + */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - The 2nd byte read from the slave + */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Slave Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count + */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Does not support I2C10B + * 0b1..Supports I2C10B + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) +#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) +/*! I2CRST - I2C SW Reset + * 0b0..Does not support I2CRST + * 0b1..Supports I2CRST + */ +#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Does not support I2CDEVID + * 0b1..Supports I2CDEVID + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Does not support IBIEXT + * 0b1..Supports IBIEXT + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Does not support IBIXREG + * 0b1..Supports IBIXREG + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Slave Reset + * 0b0..Does not support Slave Reset + * 0b1..Supports Slave Reset + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - GROUP + * 0b00..Does not supports v1.1 Group addressing + * 0b01..Supports one group + * 0b10..Supports two groups + * 0b11..Supports three groups + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - Supports SETAASA + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Slave-Slave(s)-Tunnel subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Slave-Slave(s)-Tunnel write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Slave Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b handler + * 0b00..APPLICATION + * 0b01..HW + * 0b10..HW_BUT + * 0b11..PARTNO + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID register + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - HDR support + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Master + * 0b0..MASTERNOTSUPPORTED + * 0b1..MASTERSUPPORTED + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static address + * 0b00..NO_STATIC + * 0b01..STATIC + * 0b10..HW_CONTROL + * 0b11..CONFIG + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes (CCC) handling + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time control + * 0b0..NO_TIME_CONTROL_TYPE + * 0b1..ATLEAST1_TIME_CONTROL + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..NO_EXT_FIFO + * 0b001..STD_EXT_FIFO + * 0b010..REQUEST_EXT_FIFO + * 0b011.. + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO transmit + * 0b00..FIFO_2BYTE + * 0b01..FIFO_4BYTE: 4-byte TX FIFO + * 0b10..FIFO_8BYTE: 8-byte TX FIFO + * 0b11..FIFO_16BYTE: 16-byte TX FIFO or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO receive + * 0b00..FIFO_2BYTE + * 0b01..FIFO_4BYTE + * 0b10..FIFO_8BYTE + * 0b11..FIFO_16BYTE + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - INT + * 0b1..Interrupts are supported + * 0b0..Interrupts are not supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - DMA + * 0b1..DMA is supported + * 0b0..DMA is not supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SDYNADDR - Slave Dynamic Address */ +/*! @{ */ + +#define I3C_SDYNADDR_DAVALID_MASK (0x1U) +#define I3C_SDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - DAVALID + * 0b0..DANOTASSIGNED: a Dynamic Address is not assigned + * 0b1..DAASSIGNED: a Dynamic Address is assigned + */ +#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) + +#define I3C_SDYNADDR_DADDR_MASK (0xFEU) +#define I3C_SDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic address + */ +#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) + +#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) +#define I3C_SDYNADDR_MAPSA_SHIFT (12U) +/*! MAPSA - Map a Static Address + */ +#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) + +#define I3C_SDYNADDR_SA10B_MASK (0xE000U) +#define I3C_SDYNADDR_SA10B_SHIFT (13U) +/*! SA10B - 10bit Static Address + */ +#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) + +#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) +#define I3C_SDYNADDR_KEY_SHIFT (16U) +/*! KEY - Key + */ +#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Slave Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum read length + */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum write length + */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Slave ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part number + */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Slave ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register + */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register + */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Slave Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID + */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Slave Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock accuracy + */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock frequency + */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Slave Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index + */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 + */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 + */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCTRL - Master Main Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..FORCEEXIT and SLAVERESET + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt (IBI) response + * 0b00..ACK + * 0b01..NACK + * 0b10..ACK_WITH_MANDATORY + * 0b11..MANUAL + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - DIR + * 0b0..DIRWRITE: Write + * 0b1..DIRREAD: Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address + */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read terminate + */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Master Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the master + * 0b000..IDLE: the bus has STOPped. + * 0b001..SLVREQ + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not acknowledged + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) type + * 0b00..NONE + * 0b01..IBI + * 0b10..MR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Slave start + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Master control done + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX buffer/FIFO not yet full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) won + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now master (now this module is a master) + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI address + */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 + */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 + */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 + */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 + */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 + */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Set Most Significant address Bit to 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Master Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Slave start interrupt enable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Master control done interrupt enable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed message interrupt enable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - RX pending interrupt enable + */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or warning (ERRWARN) interrupt enable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Master Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART interrupt enable clear + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE interrupt enable clear + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE interrupt enable clear + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND interrupt enable clear + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL interrupt enable clear + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON interrupt enable clear + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN interrupt enable clear + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWMASTER interrupt enable clear + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Master Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART interrupt mask + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE interrupt mask + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE interrupt mask + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND interrupt mask + */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL interrupt mask + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON interrupt mask + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN interrupt mask + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWMASTER interrupt mask + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Master Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not acknowledge (NACK) error + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - WRABT (Write abort) error + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High data rate parity + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High data rate CRC error + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-read error + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-write error + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message error + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid request error + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - TIMEOUT error + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Master DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from bus + * 0b00..NOT_USED + * 0b01..ENABLE_ONE_FRAME + * 0b10..ENABLE + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to bus + * 0b00..NOT_USED + * 0b01..ENABLE_ONE_FRAME + * 0b10..ENABLE + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA width + * 0b00, 0b01..BYTE + * 0b10..HALF_WORD + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name MDATACTRL - Master Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush to-bus buffer/FIFO + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush from-bus buffer/FIFO + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - TX trigger level + * 0b00..Trigger on empty + * 0b01..Trigger on 1/4 full or less + * 0b10..Trigger on 1/2 full or less + * 0b11..Default. Trigger on 1 less than full or less + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - RX trigger level + * 0b00..Trigger on not empty + * 0b01..Trigger on 1/4 full or more + * 0b10..Trigger on 1/2 full or more + * 0b11..Trigger on 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - TX byte count + */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - RX byte count + */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - TX is full. + * 0b0..TX is not yet full. + * 0b1..TX is full. + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - RX is empty. + * 0b0..RX is not yet empty. + * 0b1..RX is empty. + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Master Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data byte + */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of message + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of message also + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Master Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data + */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Master Write Data Half-word */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data byte 0 + */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data byte 1 + */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of message + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Master Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - DATA 0 + */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - DATA 1 + */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Master Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - VALUE + */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Master Read Data Half-word */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - LSB + */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - MSB + */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Byte-only Write Byte Data (to bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value + */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address to be written to + */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR message + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length + */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data + */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Master Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data + */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT (0U) +/*! LEN - Length of message + */ +#define I3C_MWMSG_DDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL_END_SHIFT (14U) +/*! END - End of message + */ +#define I3C_MWMSG_DDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data + */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Master Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data + */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Master Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic address valid + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic address + */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address + */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count + */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum + */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra byte 1 + */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra byte 2 + */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra byte 3 + */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra byte 4 + */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra byte 5 + */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra byte 6 + */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra byte 7 + */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SID - Slave Module ID */ +/*! @{ */ + +#define I3C_SID_ID_MASK (0xFFFFFFFFU) +#define I3C_SID_ID_SHIFT (0U) +/*! ID - ID + */ +#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50016000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40016000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40016000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Inputmux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAP[4]; /**< Capture select register for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + __IO uint32_t TIMER0TRIG; /**< Trigger register for TIMER0, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t TIMER1CAP[4]; /**< Capture select register for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + __IO uint32_t TIMER1TRIG; /**< Trigger register for TIMER1, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMER2CAP[4]; /**< Capture select register for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + __IO uint32_t TIMER2TRIG; /**< Trigger register for TIMER2, offset: 0x70 */ + uint8_t RESERVED_3[44]; + __IO uint32_t EZHARCHB_INMUX[8]; /**< Inputmux register for EZH arch B inputs, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[32]; /**< Trigger select for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + __IO uint32_t DMA0_OTRIG_INMUX[7]; /**< DMA0 output trigger selection for DMA0 input trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_4[4]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_5[24]; + __IO uint32_t TIMER3CAP[4]; /**< Capture select register for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + __IO uint32_t TIMER3TRIG; /**< Trigger register for TIMER3, offset: 0x1B0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t TIMER4CAP[4]; /**< Capture select register for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + __IO uint32_t TIMER4TRIG; /**< Trigger register for TIMER4, offset: 0x1D0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_8[24]; + __IO uint32_t DMA1_ITRIG_INMUX[16]; /**< Trigger select for DMA1 channel, array offset: 0x200, array step: 0x4 */ + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection for DMA1 input trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_9[16]; + __IO uint32_t HSCMP0_TRIG; /**< Input connections for HSCMP0, offset: 0x260 */ + uint8_t RESERVED_10[28]; + __IO uint32_t ADC0_TRIG[4]; /**< ADC0 Trigger input connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_11[48]; + __IO uint32_t ADC1_TRIG[4]; /**< ADC1 Trigger input connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_12[48]; + __IO uint32_t DAC0_TRIG; /**< DAC0 Trigger Inputs, offset: 0x300 */ + uint8_t RESERVED_13[28]; + __IO uint32_t DAC1_TRIG; /**< DAC1 Trigger Inputs, offset: 0x320 */ + uint8_t RESERVED_14[28]; + __IO uint32_t DAC2_TRIG; /**< DAC2 Trigger Inputs, offset: 0x340 */ + uint8_t RESERVED_15[28]; + __IO uint32_t ENC0_TRIG; /**< ENC0 Trigger Input Connections, offset: 0x360 */ + __IO uint32_t ENC0_HOME; /**< ENC0 Input Connections, offset: 0x364 */ + __IO uint32_t ENC0_INDEX; /**< ENC0 Input Connections, offset: 0x368 */ + __IO uint32_t ENC0_PHASEB; /**< ENC0 Input Connections, offset: 0x36C */ + __IO uint32_t ENC0_PHASEA; /**< ENC0 Input Connections, offset: 0x370 */ + uint8_t RESERVED_16[12]; + __IO uint32_t ENC1_TRIG; /**< ENC1 Trigger Input Connections, offset: 0x380 */ + __IO uint32_t ENC1_HOME; /**< ENC1 Input Connections, offset: 0x384 */ + __IO uint32_t ENC1_INDEX; /**< ENC1 Input Connections, offset: 0x388 */ + __IO uint32_t ENC1_PHASEB; /**< ENC1 Input Connections, offset: 0x38C */ + __IO uint32_t ENC1_PHASEA; /**< ENC1 Input Connections, offset: 0x390 */ + uint8_t RESERVED_17[12]; + __IO uint32_t PWM0_EXTSYNC[4]; /**< PWM0 external synchronization, array offset: 0x3A0, array step: 0x4 */ + __IO uint32_t PWM0_EXTA[4]; /**< PWM0 input trigger connections, array offset: 0x3B0, array step: 0x4 */ + __IO uint32_t PWM0_EXTFORCE; /**< PWM0 external force trigger connections, offset: 0x3C0 */ + __IO uint32_t PWM0_FAULT[4]; /**< PWM0 fault input trigger connections, array offset: 0x3C4, array step: 0x4 */ + uint8_t RESERVED_18[12]; + __IO uint32_t PWM1_EXTSYNC[4]; /**< PWM1 external synchronization, array offset: 0x3E0, array step: 0x4 */ + __IO uint32_t PWM1_EXTA[4]; /**< PWM1 input trigger connections, array offset: 0x3F0, array step: 0x4 */ + __IO uint32_t PWM1_EXTFORCE; /**< PWM1 external force trigger connections, offset: 0x400 */ + __IO uint32_t PWM1_FAULT[4]; /**< PWM1 fault input trigger connections, array offset: 0x404, array step: 0x4 */ + uint8_t RESERVED_19[12]; + __IO uint32_t PWM0_EXTCLK; /**< PWM0 external clock trigger connections, offset: 0x420 */ + __IO uint32_t PWM1_EXTCLK; /**< PWM1 external clock trigger connections, offset: 0x424 */ + uint8_t RESERVED_20[24]; + __IO uint32_t AOI0_IN[16]; /**< AOI0 trigger inputs, array offset: 0x440, array step: 0x4 */ + __IO uint32_t AOI1_IN[16]; /**< AOI1 trigger inputs, array offset: 0x480, array step: 0x4 */ + __IO uint32_t AOI_EXT_TRIG[8]; /**< AOI External Trigger Inputs, array offset: 0x4C0, array step: 0x4 */ + __IO uint32_t HSCMP1_TRIG; /**< Input connections for HSCMP1, offset: 0x4E0 */ + uint8_t RESERVED_21[28]; + __IO uint32_t HSCMP2_TRIG; /**< Input connections for HSCMP2, offset: 0x500 */ + uint8_t RESERVED_22[28]; + __IO uint32_t DMA0_ITRIG_INMUX32[20]; /**< Trigger select for DMA0 channel, array offset: 0x520, array step: 0x4 */ + uint8_t RESERVED_23[464]; + __IO uint32_t DMA0_REQEN0; /**< Enable DMA0 requests, offset: 0x740 */ + __IO uint32_t DMA0_REQEN1; /**< Enable DMA0 requests, offset: 0x744 */ + __O uint32_t DMA0_REQEN0_SET; /**< Set bits in DMA0_REQEN0 register, offset: 0x748 */ + __O uint32_t DMA0_REQEN1_SET; /**< Set bits in DMA0_REQEN1 register, offset: 0x74C */ + __O uint32_t DMA0_REQEN0_CLR; /**< Clear bits in DMA0_REQEN0 register, offset: 0x750 */ + __O uint32_t DMA0_REQEN1_CLR; /**< Clear bits in DMA0_REQEN1 register, offset: 0x754 */ + uint8_t RESERVED_24[8]; + __IO uint32_t DMA1_REQEN; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_25[4]; + __O uint32_t DMA1_REQEN_SET; /**< Set bits in DMA1_REQEN register, offset: 0x768 */ + uint8_t RESERVED_26[4]; + __O uint32_t DMA1_REQEN_CLR; /**< Clear bits in DMA1_REQEN register, offset: 0x770 */ + uint8_t RESERVED_27[12]; + __IO uint32_t DMA0_ITRIGEN0; /**< Enable DMA0 triggers, offset: 0x780 */ + __IO uint32_t DMA0_ITRIGEN1; /**< Enable DMA0 triggers, offset: 0x784 */ + __O uint32_t DMA0_ITRIGEN0_SET; /**< Set bits in DMA0_ITRIGEN0 register, offset: 0x788 */ + __O uint32_t DMA0_ITRIGEN1_SET; /**< Set bits in DMA0_ITRIGEN1 register, offset: 0x78C */ + __O uint32_t DMA0_ITRIGEN0_CLR; /**< Clear bits in DMA0_ITRIGEN0 register, offset: 0x790 */ + __O uint32_t DMA0_ITRIGEN1_CLR; /**< Clear bits in DMA0_ITRIGEN1 register, offset: 0x794 */ + uint8_t RESERVED_28[8]; + __IO uint32_t DMA1_ITRIGEN; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_29[4]; + __O uint32_t DMA1_ITRIGEN_SET; /**< Set bits in DMA1_ITRIGEN register, offset: 0x7A8 */ + uint8_t RESERVED_30[4]; + __O uint32_t DMA1_ITRIGEN_CLR; /**< Clear bits in DMA1_ITRIGEN register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Inputmux register for SCT0 input */ +/*! @{ */ + +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x3FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6. + * 0b000000..SCT_GPIO_IN_A function selected from IOCON register + * 0b000001..SCT_GPIO_IN_B function selected from IOCON register + * 0b000010..SCT_GPIO_IN_C function selected from IOCON register + * 0b000011..SCT_GPIO_IN_D function selected from IOCON register + * 0b000100..SCT_GPIO_IN_E function selected from IOCON register + * 0b000101..SCT_GPIO_IN_F function selected from IOCON register + * 0b000110..SCT_GPIO_IN_G function selected from IOCON register + * 0b000111..SCT_GPIO_IN_H function selected from IOCON register + * 0b001000..T0_MAT0 ctimer 0 match[0] output + * 0b001001..T1_MAT0 ctimer 1 match[0] output + * 0b001010..T2_MAT0 ctimer 2 match[0] output + * 0b001011..T3_MAT0 ctimer 3 match[0] output + * 0b001100..T4_MAT0 ctimer 4 match[0] output + * 0b001101..ADC0_IRQ interrupt request from ADC0 + * 0b001110..GPIOINT_BMATCH + * 0b001111..USB0_FRAME_TOGGLE + * 0b010000..Reserved + * 0b010001..ACMP0_OUT from analog comparator + * 0b010010..SHARED_I2S_SCLK0 output from I2S pin sharing + * 0b010011..SHARED_I2S_SCLK1 output from I2S pin sharing + * 0b010100..SHARED_I2S_WS0 output from I2S pin sharing + * 0b010101..SHARED_I2S_WS1 output from I2S pin sharing + * 0b010110..ARM_TXEV interrupt event from CPU0 + * 0b010111..DEBUG_HALTED from CPU0 + * 0b011000..ADC1_IRQ interrupt request from ADC1 + * 0b011001..ADC0_tcomp[0] + * 0b011010..ADC0_tcomp[1] + * 0b011011..ADC0_tcomp[2] + * 0b011100..ADC0_tcomp[3] + * 0b011101..ADC1_tcomp[0] + * 0b011110..ADC1_tcomp[1] + * 0b011111..ADC1_tcomp[2] + * 0b100000..ADC1_tcomp[3] + * 0b100001..HSCMP0_OUT + * 0b100010..HSCMP1_OUT + * 0b100011..HSCMP2_OUT + * 0b100100..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b100101..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100110..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100111..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b101000..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b101001..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b101010..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b101011..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b101100..ENC0_CMP/POS_MATCH + * 0b101101..ENC1_CMP/POS_MATCH + * 0b101110..AOI0_OUT0 + * 0b101111..AOI0_OUT1 + * 0b110000..AOI0_OUT2 + * 0b110001..AOI0_OUT3 + * 0b110010..AOI1_OUT0 + * 0b110011..AOI1_OUT1 + * 0b110100..AOI1_OUT2 + * 0b110101..AOI1_OUT3 + * 0b110110..FC3_SCK + * 0b110111..FC3_RXD_SDA_MOSI_DATA + * 0b111000..FC3_TXD_SCL_MISO_WS + * 0b111001..FC3_CTS_DSA_SSEL0 + * 0b111010..TMPR_OUT + * 0b111011-0b111111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAP - Capture select register for TIMER0 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER0CAP_CAPTSEL_MASK (0x3FU) +#define INPUTMUX_TIMER0CAP_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 5 + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER0CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAP_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAP */ +#define INPUTMUX_TIMER0CAP_COUNT (4U) + +/*! @name TIMER0TRIG - Trigger register for TIMER0 */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_TIMER0TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - Input number to TIMER0 trigger inputs + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER0TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER0TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name TIMER1CAP - Capture select register for TIMER1 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER1CAP_CAPTSEL_MASK (0x3FU) +#define INPUTMUX_TIMER1CAP_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 5 + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER1CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAP_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAP */ +#define INPUTMUX_TIMER1CAP_COUNT (4U) + +/*! @name TIMER1TRIG - Trigger register for TIMER1 */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_TIMER1TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - Input number to TIMER1 trigger inputs + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER1TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER1TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name TIMER2CAP - Capture select register for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2CAP_CAPTSEL_MASK (0x3FU) +#define INPUTMUX_TIMER2CAP_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 5 + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER2CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAP_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAP */ +#define INPUTMUX_TIMER2CAP_COUNT (4U) + +/*! @name TIMER2TRIG - Trigger register for TIMER2 */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_TIMER2TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - Input number to TIMER2 trigger inputs + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER2TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER2TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name EZHARCHB_INMUX - Inputmux register for EZH arch B inputs */ +/*! @{ */ + +#define INPUTMUX_EZHARCHB_INMUX_INP_MASK (0x7FU) +#define INPUTMUX_EZHARCHB_INMUX_INP_SHIFT (0U) +/*! INP - Input number select to EZHARCHB input + * 0b0000000-0b0001111..GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register + * 0b0010000..SCT_OUT8 output from SCTimer, synced to system clock + * 0b0010001..SCT_OUT9 output from SCTimer, synced to system clock + * 0b0010010..Reserved + * 0b0010011..Reserved + * 0b0010100..MRT_IRQ0 Multi-rate timer interrupt request 0 + * 0b0010101..MRT_IRQ1 Multi-rate timer interrupt request 1 + * 0b0010110..T4_MAT3 ctimer 4 match[3] output + * 0b0010111..T4_MAT2 ctimer 4 match[2] output + * 0b0011000..T3_MAT3 ctimer 3 match[3] output + * 0b0011001..T3_MAT2 ctimer 3 match[2] output + * 0b0011010..T1_MAT3 ctimer 1 match[3] output + * 0b0011011..T1_MAT2 ctimer 1 match[2] output + * 0b0011100..UTICK0_IRQ Micro-tick timer interrupt, synced to system clock + * 0b0011101..WDT_IRQ Watchdog Timer interrupt request, synced to system clock + * 0b0011110..ADC0_IRQ interrupt request from ADC + * 0b0011111..ACMP0_IRQ Combined Analog comparator interrupt request + * 0b0100000..LSPI_HS_IRQ High speed Serial Peripheral interface interrupt request + * 0b0100001..FLEXCOMM7_IRQ Flexcomm7 interrupt synced to system clock + * 0b0100010..FLEXCOMM6_IRQ Flexcomm6 interrupt synced to system clock + * 0b0100011..FLEXCOMM5_IRQ Flexcomm5 interrupt synced to system clock + * 0b0100100..FLEXCOMM4_IRQ Flexcomm4 interrupt synced to system clock + * 0b0100101..FLEXCOMM3_IRQ Flexcomm3 interrupt synced to system clock + * 0b0100110..FLEXCOMM2_IRQ Flexcomm2 interrupt synced to system clock + * 0b0100111..FLEXCOMM1_IRQ Flexcomm1 interrupt synced to system clock + * 0b0101000..FLEXCOMM0_IRQ Flexcomm0 interrupt synced to system clock + * 0b0101001..DMA0_IRQ DMA0 interrupt request + * 0b0101010..DMA1_IRQ DMA1 interrupt request + * 0b0101011..SYS_IRQ combined WDT_INT Watchdog Timer interrupt request | FLASH_IRQ Flash interrupt request | BOD_IRQ BrownOut Detection interrupt request + * 0b0101100..RTC_COMBO_IRQ Real Time Clock Combined Alarm | Wake-up interrupt request + * 0b0101101..ARM_TXEV interrupt event from CPU0 + * 0b0101110..GPIOINT_BMATCH GPIO_INT boolean pattern match output + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..ACMP_OUT output from analog comparator + * 0b0110010..USB0_FRAME_TOGGLE + * 0b0110011..Reserved + * 0b0110100..OSTIMER_IRQ OS Timer interrupt request + * 0b0110101..ADC1 interrupt + * 0b0110110..HSCOMP0_IRQ/HSCOMP1_IRQ/HSCOMP2_IRQ + * 0b0110111..DAC0 interrupt + * 0b0111000..DAC1/2 interrupt + * 0b0111001..FlexPWM0 interrupt + * 0b0111010..FlexPWM1 interrupt + * 0b0111011..ENC0 interrupt + * 0b0111100..ENC1 interrupt + * 0b0111101..AOI0_OUT0 + * 0b0111110..AOI1_OUT0 + * 0b0111111..TMPR_OUT + * 0b1000000-0b1111110..Reserved + */ +#define INPUTMUX_EZHARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EZHARCHB_INMUX_INP_SHIFT)) & INPUTMUX_EZHARCHB_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EZHARCHB_INMUX */ +#define INPUTMUX_EZHARCHB_INMUX_COUNT (8U) + +/*! @name PINTSEL - Pin interrupt select */ +/*! @{ */ + +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select for DMA0 channel */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x3FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (binary value) for DMA channel n (n = 0 to 31). + * 0b000000..FlexSPI_RX + * 0b000001..FlexSPI_TX + * 0b000010..GPIO_INT0 + * 0b000011..GPIO_INT1 + * 0b000100..GPIO_INT2 + * 0b000101..GPIO_INT3 + * 0b000110..T0_DMAREQ_M0 + * 0b000111..T0_DMAREQ_M1 + * 0b001000..T1_DMAREQ_M0 + * 0b001001..T1_DMAREQ_M1 + * 0b001010..T2_DMAREQ_M0 + * 0b001011..T2_DMAREQ_M1 + * 0b001100..T3_DMAREQ_M0 + * 0b001101..T3_DMAREQ_M1 + * 0b001110..T4_DMAREQ_M0 + * 0b001111..T4_DMAREQ_M1 + * 0b010000..ACMP0_OUT + * 0b010001..SDMA0_TRIGOUT_A + * 0b010010..SDMA0_TRIGOUT_B + * 0b010011..SDMA0_TRIGOUT_C + * 0b010100..SDMA0_TRIGOUT_D + * 0b010101..SCT_DMA0 + * 0b010110..SCT_DMA1 + * 0b010111..ADC0_tcomp[0] + * 0b011000..ADC1_tcomp[0] + * 0b011001..HSCMP0 + * 0b011010..HSCMP1 + * 0b011011..HSCMP2 + * 0b011100..AOI0_OUT0 + * 0b011101..AOI0_OUT1 + * 0b011110..AOI0_OUT2 + * 0b011111..AOI0_OUT3 + * 0b100000..AOI1_OUT0 + * 0b100001..AOI1_OUT1 + * 0b100010..AOI1_OUT2 + * 0b100011..AOI1_OUT3 + * 0b100100..FlexPWM0_req_capt0 + * 0b100101..FlexPWM0_req_capt1 + * 0b100110..FlexPWM0_req_capt2 + * 0b100111..FlexPWM0_req_capt3 + * 0b101000..FlexPWM0_req_val0 + * 0b101001..FlexPWM0_req_val1 + * 0b101010..FlexPWM0_req_val2 + * 0b101011..FlexPWM0_req_val3 + * 0b101100..FlexPWM1_req_capt0 + * 0b101101..FlexPWM1_req_capt1 + * 0b101110..FlexPWM1_req_capt2 + * 0b101111..FlexPWM1_req_capt3 + * 0b110000..FlexPWM1_req_val0 + * 0b110001..FlexPWM1_req_val1 + * 0b110010..FlexPWM1_req_val2 + * 0b110011..FlexPWM1_req_val3 + * 0b110100..TMPR_OUT + * 0b110110-0b111111..Reserved + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (32U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection for DMA0 input trigger */ +/*! @{ */ + +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x3FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (binary value) for DMA channel n (n = 0 to 52). + */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (7U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (binary value) for frequency measure function target clock. + * 0b00000..XTAL32MHz + * 0b00001..FRO_OSC_12M + * 0b00010..FRO_OSC_96M + * 0b00011..WDOSC (FRO1M) + * 0b00100..32KHZ_OSC + * 0b00101..MAIN_SYS_CLOCK + * 0b00110..FREQME_GPIO_CLK_A + * 0b00111..FREQME_GPIO_CLK_B + * 0b01000..AOI0_OUT2 + * 0b01001..AOI1_OUT2 + */ +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for frequency measurement target clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TAR_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (binary value) for frequency measure function target clock + * 0b00000..XTAL32MHz + * 0b00001..FRO_OSC_12M + * 0b00010..FRO_OSC_96M + * 0b00011..WDOSC (FRO1M) + * 0b00100..32KHZ_OSC + * 0b00101..MAIN_SYS_CLOCK + * 0b00110..FREQME_GPIO_CLK_A + * 0b00111..FREQME_GPIO_CLK_B + * 0b01000..AOI0_OUT2 + * 0b01001..AOI1_OUT2 + */ +#define INPUTMUX_FREQMEAS_TAR_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TAR_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAP - Capture select register for TIMER3 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER3CAP_CAPTSEL_MASK (0x3FU) +#define INPUTMUX_TIMER3CAP_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 5 + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER3CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAP_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAP */ +#define INPUTMUX_TIMER3CAP_COUNT (4U) + +/*! @name TIMER3TRIG - Trigger register for TIMER3 */ +/*! @{ */ + +#define INPUTMUX_TIMER3TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_TIMER3TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - Input number to TIMER3 trigger inputs + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER3TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER3TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name TIMER4CAP - Capture select register for TIMER4 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER4CAP_CAPTSEL_MASK (0x3FU) +#define INPUTMUX_TIMER4CAP_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 5 + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER4CAP_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAP_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAP */ +#define INPUTMUX_TIMER4CAP_COUNT (4U) + +/*! @name TIMER4TRIG - Trigger register for TIMER4 */ +/*! @{ */ + +#define INPUTMUX_TIMER4TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_TIMER4TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - Input number to TIMER4 trigger inputs + * 0b000000..CTIMER_INP0 function selected from IOCON register + * 0b000001..CTIMER_INP1 function selected from IOCON register + * 0b000010..CTIMER_INP2 function selected from IOCON register + * 0b000011..CTIMER_INP3 function selected from IOCON register + * 0b000100..CTIMER_INP4 function selected from IOCON register + * 0b000101..CTIMER_INP5 function selected from IOCON register + * 0b000110..CTIMER_INP6 function selected from IOCON register + * 0b000111..CTIMER_INP7 function selected from IOCON register + * 0b001000..CTIMER_INP8 function selected from IOCON register + * 0b001001..CTIMER_INP9 function selected from IOCON register + * 0b001010..CTIMER_INP10 function selected from IOCON register + * 0b001011..CTIMER_INP11 function selected from IOCON register + * 0b001100..CTIMER_INP12 function selected from IOCON register + * 0b001101..CTIMER_INP13 function selected from IOCON register + * 0b001110..CTIMER_INP14 function selected from IOCON register + * 0b001111..CTIMER_INP15 function selected from IOCON register + * 0b010000..CTIMER_INP16 function selected from IOCON register + * 0b010001..CTIMER_INP17 function selected from IOCON register + * 0b010010..CTIMER_INP18 function selected from IOCON register + * 0b010011..CTIMER_INP19 function selected from IOCON register + * 0b010100..USB0_FRAME_TOGGLE + * 0b010101..Reserved + * 0b010110..ACMP0_OUT from analog comparator + * 0b010111..SHARED_I2S_WS0 output from I2S pin sharing + * 0b011000..SHARED_I2S_WS1 output from I2S pin sharing + * 0b011001..ADC0_IRQ + * 0b011010..ADC1_IRQ + * 0b011011..HSCMP0_OUT + * 0b011100..HSCMP1_OUT + * 0b011101..HSCMP2_OUT + * 0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b100110..ENC0_CMP/POS_MATCH + * 0b100111..ENC1_CMP/POS_MATCH + * 0b101000..AOI0_OUT0 + * 0b101001..AOI0_OUT1 + * 0b101010..AOI0_OUT2 + * 0b101011..AOI0_OUT3 + * 0b101100..AOI1_OUT0 + * 0b101101..AOI1_OUT1 + * 0b101110..AOI1_OUT2 + * 0b101111..AOI1_OUT3 + * 0b110000..TMPR_OUT + * 0b110001-0b111111..None + */ +#define INPUTMUX_TIMER4TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER4TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name PINTSECSEL - Pin interrupt secure select */ +/*! @{ */ + +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select for DMA1 channel */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (binary value) for DMA channel n (n = 0 to 14). + * 0b00000..Pin interrupt 0 (GPIO_INT0) + * 0b00001..Pin interrupt 1 (GPIO_INT1) + * 0b00010..Pin interrupt 2 (GPIO_INT2) + * 0b00011..Pin interrupt 3 (GPIO_INT3) + * 0b00100..Timer CTIMER0 Match 0 (T0_DMAREQ_M0) + * 0b00101..Timer CTIMER0 Match 1 (T0_DMAREQ_M1) + * 0b00110..Timer CTIMER2 Match 0 (T2_DMAREQ_M0) + * 0b00111..Timer CTIMER4 Match 0 (T4_DMAREQ_M0) + * 0b01000..SDMA1_TRIGOUT_A + * 0b01001..SDMA1_TRIGOUT_B + * 0b01010..SDMA1_TRIGOUT_C + * 0b01011..SDMA1_TRIGOUT_D + * 0b01100..SCT_DMA_REQ0 + * 0b01101..SCT_DMA_REQ1 + * 0b01110..FlexSPI_RX + * 0b01111..FlexSPI_TX + * 0b10000..AOI0_OUT0 + * 0b10001..AOI0_OUT1 + * 0b10010..AOI0_OUT2 + * 0b10011..AOI0_OUT3 + * 0b10100..AOI1_OUT0 + * 0b10101..AOI1_OUT1 + * 0b10110..AOI1_OUT2 + * 0b10111..AOI1_OUT3 + * 0b11000..TMPR_OUT + * 0b11001-0b11111..Reserved + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (16U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection for DMA1 input trigger */ +/*! @{ */ + +#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_SHIFT (0U) +/*! SDMA1_CH_TRIGOUT - DMA trigger output number (binary value) for DMA channel n (n = 0 to 15). + * 0b0000..SDMA1_CH0_TRIGOUT + * 0b0001..SDMA1_CH1_TRIGOUT + * 0b0010..SDMA1_CH2_TRIGOUT + * 0b0011..SDMA1_CH3_TRIGOUT + * 0b0100..SDMA1_CH4_TRIGOUT + * 0b0101..SDMA1_CH5_TRIGOUT + * 0b0110..SDMA1_CH6_TRIGOUT + * 0b0111..SDMA1_CH7_TRIGOUT + * 0b1000..SDMA1_CH8_TRIGOUT + * 0b1001..SDMA1_CH9_TRIGOUT + * 0b1010..SDMA1_CH10_TRIGOUT + * 0b1011..SDMA1_CH11_TRIGOUT + * 0b1100..SDMA1_CH12_TRIGOUT + * 0b1101..SDMA1_CH13_TRIGOUT + * 0b1110-0b1111..Reserved + */ +#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name HSCMP0_TRIG - Input connections for HSCMP0 */ +/*! @{ */ + +#define INPUTMUX_HSCMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_HSCMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT6 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT6 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T0_MAT0 + * 0b001001..T4_MAT0 + * 0b001010..Reserved + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC1_tcomp[0] + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b011001..ENC0_CMP/POS_MATCH + * 0b011010..ENC1_CMP/POS_MATCH + * 0b011011..AOI0_OUT0 + * 0b011100..AOI0_OUT1 + * 0b011101..AOI0_OUT2 + * 0b011110..AOI0_OUT3 + * 0b011111..AOI1_OUT0 + * 0b100000..AOI1_OUT1 + * 0b100001..AOI1_OUT2 + * 0b100010..AOI1_OUT3 + * 0b100011..DMA0_TRIGOUT0 + * 0b100100..DMA0_TRIGOUT1 + * 0b100101..DMA0_TRIGOUT2 + */ +#define INPUTMUX_HSCMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGN_ADC0_TRIG - ADC0 Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT1 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT9 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T3_MAT3 + * 0b001001..T4_MAT3 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..PWM1_SM0_MUX_TRIG0 + * 0b100001..PWM1_SM0_MUX_TRIG1 + * 0b100010..PWM1_SM1_MUX_TRIG0 + * 0b100011..PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 + * 0b100101..PWM1_SM2_MUX_TRIG1 + * 0b100110..PWM1_SM3_MUX_TRIG0 + * 0b100111..PWM1_SM3_MUX_TRIG1 + * 0b101000..ENC0_CMP/POS_MATCH + * 0b101001..ENC1_CMP/POS_MATCH + * 0b101010..AOI0_OUT0 + * 0b101011..AOI0_OUT1 + * 0b101100..AOI0_OUT2 + * 0b101101..AOI0_OUT3 + * 0b101110..AOI1_OUT0 + * 0b101111..AOI1_OUT1 + * 0b110000..AOI1_OUT2 + * 0b110001..AOI1_OUT3 + * 0b110010..DMA0_TRIGOUT0 + * 0b110011..DMA0_TRIGOUT1 + * 0b110100..DMA0_TRIGOUT2 + * 0b110101-0b111111..None + */ +#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGN_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGN_ADC1_TRIG - ADC1 Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC1 trigger inputs + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT2 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT3 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T3_MAT2 + * 0b001001..T4_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..PWM1_SM0_MUX_TRIG0 + * 0b100001..PWM1_SM0_MUX_TRIG1 + * 0b100010..PWM1_SM1_MUX_TRIG0 + * 0b100011..PWM1_SM1_MUX_TRIG1 + * 0b100100..PWM1_SM2_MUX_TRIG0 + * 0b100101..PWM1_SM2_MUX_TRIG1 + * 0b100110..PWM1_SM3_MUX_TRIG0 + * 0b100111..PWM1_SM3_MUX_TRIG1 + * 0b101000..ENC0_CMP/POS_MATCH + * 0b101001..ENC1_CMP/POS_MATCH + * 0b101010..AOI0_OUT0 + * 0b101011..AOI0_OUT1 + * 0b101100..AOI0_OUT2 + * 0b101101..AOI0_OUT3 + * 0b101110..AOI1_OUT0 + * 0b101111..AOI1_OUT1 + * 0b110000..AOI1_OUT2 + * 0b110001..AOI1_OUT3 + * 0b110010..DMA0_TRIGOUT0 + * 0b110011..DMA0_TRIGOUT1 + * 0b110100..DMA0_TRIGOUT2 + * 0b110101-0b111111..None + */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT (4U) + +/*! @name DAC0_TRIG - DAC0 Trigger Inputs */ +/*! @{ */ + +#define INPUTMUX_DAC0_TRIG_TRIGIN_MASK (0x1FU) +#define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - DAC0 trigger input + * 0b00000..PIN_INT0 + * 0b00001..PIN_INT3 + * 0b00010..SCT_OUT4 + * 0b00011..SCT_OUT5 + * 0b00100..SCT_OUT0 + * 0b00101..T0_MAT3 + * 0b00110..T1_MAT3 + * 0b00111..T2_MAT3 + * 0b01000..T2_MAT0 + * 0b01001..T3_MAT0 + * 0b01010..ACMP0_OUT + * 0b01011..ARM_TXEV + * 0b01100..GPIOINT_BMATCH + * 0b01101..ADC0_tcomp[0] + * 0b01110..ADC1_tcomp[0] + * 0b01111..HSCMP0_OUT + * 0b10000..HSCMP1_OUT + * 0b10001..HSCMP2_OUT + * 0b10010..AOI0_OUT0 + * 0b10011..AOI0_OUT1 + * 0b10100..AOI0_OUT2 + * 0b10101..AOI0_OUT3 + * 0b10110..AOI1_OUT0 + * 0b10111..AOI1_OUT1 + * 0b11000..AOI1_OUT2 + * 0b11001..AOI1_OUT3 + * 0b11010..DMA0_TRIGOUT0 + * 0b11011..DMA0_TRIGOUT1 + * 0b11100..DMA0_TRIGOUT2 + */ +#define INPUTMUX_DAC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name DAC1_TRIG - DAC1 Trigger Inputs */ +/*! @{ */ + +#define INPUTMUX_DAC1_TRIG_TRIGIN_MASK (0x1FU) +#define INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - DAC1 trigger input + * 0b00000..PIN_INT0 + * 0b00001..PIN_INT4 + * 0b00010..SCT_OUT4 + * 0b00011..SCT_OUT5 + * 0b00100..SCT_OUT1 + * 0b00101..T0_MAT3 + * 0b00110..T1_MAT3 + * 0b00111..T2_MAT3 + * 0b01000..T2_MAT1 + * 0b01001..T3_MAT1 + * 0b01010..ACMP0_OUT + * 0b01011..ARM_TXEV + * 0b01100..GPIOINT_BMATCH + * 0b01101..ADC0_tcomp[1] + * 0b01110..ADC1_tcomp[1] + * 0b01111..HSCMP0_OUT + * 0b10000..HSCMP1_OUT + * 0b10001..HSCMP2_OUT + * 0b10010..AOI0_OUT0 + * 0b10011..AOI0_OUT1 + * 0b10100..AOI0_OUT2 + * 0b10101..AOI0_OUT3 + * 0b10110..AOI1_OUT0 + * 0b10111..AOI1_OUT1 + * 0b11000..AOI1_OUT2 + * 0b11001..AOI1_OUT3 + * 0b11010..DMA0_TRIGOUT0 + * 0b11011..DMA0_TRIGOUT1 + * 0b11100..DMA0_TRIGOUT2 + */ +#define INPUTMUX_DAC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name DAC2_TRIG - DAC2 Trigger Inputs */ +/*! @{ */ + +#define INPUTMUX_DAC2_TRIG_TRIGIN_MASK (0x1FU) +#define INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - DAC2 trigger input + * 0b00000..PIN_INT0 + * 0b00001..PIN_INT5 + * 0b00010..SCT_OUT4 + * 0b00011..SCT_OUT5 + * 0b00100..SCT_OUT2 + * 0b00101..T0_MAT3 + * 0b00110..T1_MAT3 + * 0b00111..T2_MAT3 + * 0b01000..T2_MAT2 + * 0b01001..T3_MAT2 + * 0b01010..ACMP0_OUT + * 0b01011..ARM_TXEV + * 0b01100..GPIOINT_BMATCH + * 0b01101..ADC0_tcomp[2] + * 0b01110..ADC1_tcomp[2] + * 0b01111..HSCMP0_OUT + * 0b10000..HSCMP1_OUT + * 0b10001..HSCMP2_OUT + * 0b10010..AOI0_OUT0 + * 0b10011..AOI0_OUT1 + * 0b10100..AOI0_OUT2 + * 0b10101..AOI0_OUT3 + * 0b10110..AOI1_OUT0 + * 0b10111..AOI1_OUT1 + * 0b11000..AOI1_OUT2 + * 0b11001..AOI1_OUT3 + * 0b11010..DMA0_TRIGOUT0 + * 0b11011..DMA0_TRIGOUT1 + * 0b11100..DMA0_TRIGOUT2 + */ +#define INPUTMUX_DAC2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ENC0_TRIG - ENC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ENC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ENC0 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT4 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT1 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT0 + * 0b001001..T3_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ENC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ENC0_HOME - ENC0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC0_HOME_ENC0_HOME_MASK (0x3FU) +#define INPUTMUX_ENC0_HOME_ENC0_HOME_SHIFT (0U) +/*! ENC0_HOME - ENC0 Input Connections + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT4 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT1 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT0 + * 0b001001..T3_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM0_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC0_HOME_ENC0_HOME(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_HOME_ENC0_HOME_SHIFT)) & INPUTMUX_ENC0_HOME_ENC0_HOME_MASK) +/*! @} */ + +/*! @name ENC0_INDEX - ENC0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC0_INDEX_ENC0_INDEX_MASK (0x3FU) +#define INPUTMUX_ENC0_INDEX_ENC0_INDEX_SHIFT (0U) +/*! ENC0_INDEX - ENC0 Input Connections + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT4 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT1 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT0 + * 0b001001..T3_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC0_INDEX_ENC0_INDEX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_INDEX_ENC0_INDEX_SHIFT)) & INPUTMUX_ENC0_INDEX_ENC0_INDEX_MASK) +/*! @} */ + +/*! @name ENC0_PHASEB - ENC0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_MASK (0x3FU) +#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_SHIFT (0U) +/*! ENC0_PHASEB - ENC0 Input Connections + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT4 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT1 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT0 + * 0b001001..T3_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_SHIFT)) & INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_MASK) +/*! @} */ + +/*! @name ENC0_PHASEA - ENC0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_MASK (0x3FU) +#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_SHIFT (0U) +/*! ENC0_PHASEA - ENC0 Input Connections + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT4 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT1 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT0 + * 0b001001..T3_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_SHIFT)) & INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_MASK) +/*! @} */ + +/*! @name ENC1_TRIG - ENC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ENC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ENC1 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT7 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT1 + * 0b001001..T3_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ENC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ENC1_HOME - ENC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC1_HOME_ENC1_HOME_MASK (0x3FU) +#define INPUTMUX_ENC1_HOME_ENC1_HOME_SHIFT (0U) +/*! ENC1_HOME - ENC1 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT7 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT1 + * 0b001001..T3_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC1_HOME_ENC1_HOME(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_HOME_ENC1_HOME_SHIFT)) & INPUTMUX_ENC1_HOME_ENC1_HOME_MASK) +/*! @} */ + +/*! @name ENC1_INDEX - ENC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC1_INDEX_ENC1_INDEX_MASK (0x3FU) +#define INPUTMUX_ENC1_INDEX_ENC1_INDEX_SHIFT (0U) +/*! ENC1_INDEX - ENC1 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT7 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT1 + * 0b001001..T3_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC1_INDEX_ENC1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_INDEX_ENC1_INDEX_SHIFT)) & INPUTMUX_ENC1_INDEX_ENC1_INDEX_MASK) +/*! @} */ + +/*! @name ENC1_PHASEB - ENC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_MASK (0x3FU) +#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_SHIFT (0U) +/*! ENC1_PHASEB - ENC1 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT7 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT1 + * 0b001001..T3_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_SHIFT)) & INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_MASK) +/*! @} */ + +/*! @name ENC1_PHASEA - ENC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_MASK (0x3FU) +#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_SHIFT (0U) +/*! ENC1_PHASEA - ENC1 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT7 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T1_MAT1 + * 0b001001..T3_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_SHIFT)) & INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_MASK) +/*! @} */ + +/*! @name PWM0_EXTSYNCN_PWM0_EXTSYNC - PWM0 external synchronization */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT2 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT0 + * 0b001001..T4_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC */ +#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_COUNT (4U) + +/*! @name PWM0_EXTAN_PWM0_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT2 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT0 + * 0b001001..T4_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PWM0_EXTAN_PWM0_EXTA */ +#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_COUNT (4U) + +/*! @name PWM0_EXTFORCE - PWM0 external force trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM0_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT2 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT0 + * 0b001001..T4_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM0_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM0_FAULTN_PWM0_FAULT - PWM0 fault input trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT2 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT0 + * 0b001001..T4_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PWM0_FAULTN_PWM0_FAULT */ +#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_COUNT (4U) + +/*! @name PWM1_EXTSYNCN_PWM1_EXTSYNC - PWM1 external synchronization */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT2 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT3 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT1 + * 0b001001..T4_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC */ +#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_COUNT (4U) + +/*! @name PWM1_EXTAN_PWM1_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT2 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT3 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT1 + * 0b001001..T4_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PWM1_EXTAN_PWM1_EXTA */ +#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_COUNT (4U) + +/*! @name PWM1_EXTFORCE - PWM1 external force trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM1_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT2 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT3 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT1 + * 0b001001..T4_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM1_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_FAULTN_PWM1_FAULT - PWM1 fault input trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT2 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT3 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT1 + * 0b001001..T4_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PWM1_FAULTN_PWM1_FAULT */ +#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_COUNT (4U) + +/*! @name PWM0_EXTCLK - PWM0 external clock trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXTCLK_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM0_EXTCLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT5 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT2 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT0 + * 0b001001..T4_MAT0 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM1_SM0_MUX_TRIG0 + * 0b011001..PWM1_SM0_MUX_TRIG1 + * 0b011010..PWM1_SM1_MUX_TRIG0 + * 0b011011..PWM1_SM1_MUX_TRIG1 + * 0b011100..PWM1_SM2_MUX_TRIG0 + * 0b011101..PWM1_SM2_MUX_TRIG1 + * 0b011110..PWM1_SM3_MUX_TRIG0 + * 0b011111..PWM1_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM0_EXTCLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTCLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTCLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXTCLK - PWM1 external clock trigger connections */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXTCLK_TRIGIN_MASK (0x3FU) +#define INPUTMUX_PWM1_EXTCLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT2 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT3 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T2_MAT1 + * 0b001001..T4_MAT1 + * 0b001010..ACMP0_OUT + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[0] + * 0b001110..ADC0_tcomp[1] + * 0b001111..ADC0_tcomp[2] + * 0b010000..ADC0_tcomp[3] + * 0b010001..ADC1_tcomp[0] + * 0b010010..ADC1_tcomp[1] + * 0b010011..ADC1_tcomp[2] + * 0b010100..ADC1_tcomp[3] + * 0b010101..HSCMP0_OUT + * 0b010110..HSCMP1_OUT + * 0b010111..HSCMP2_OUT + * 0b011000..PWM0_SM0_MUX_TRIG0 + * 0b011001..PWM0_SM0_MUX_TRIG1 + * 0b011010..PWM0_SM1_MUX_TRIG0 + * 0b011011..PWM0_SM1_MUX_TRIG1 + * 0b011100..PWM0_SM2_MUX_TRIG0 + * 0b011101..PWM0_SM2_MUX_TRIG1 + * 0b011110..PWM0_SM3_MUX_TRIG0 + * 0b011111..PWM0_SM3_MUX_TRIG1 + * 0b100000..ENC0_CMP/POS_MATCH + * 0b100001..ENC1_CMP/POS_MATCH + * 0b100010..AOI0_OUT0 + * 0b100011..AOI0_OUT1 + * 0b100100..AOI0_OUT2 + * 0b100101..AOI0_OUT3 + * 0b100110..AOI1_OUT0 + * 0b100111..AOI1_OUT1 + * 0b101000..AOI1_OUT2 + * 0b101001..AOI1_OUT3 + * 0b101010..EXTTRIG_IN0 + * 0b101011..EXTTRIG_IN1 + * 0b101100..EXTTRIG_IN2 + * 0b101101..EXTTRIG_IN3 + * 0b101110..EXTTRIG_IN4 + * 0b101111..EXTTRIG_IN5 + * 0b110000..EXTTRIG_IN6 + * 0b110001..EXTTRIG_IN7 + * 0b110010..EXTTRIG_IN8 + * 0b110011..EXTTRIG_IN9 + * 0b110100..DMA0_TRIGOUT0 + * 0b110101..DMA0_TRIGOUT1 + * 0b110110..DMA0_TRIGOUT2 + */ +#define INPUTMUX_PWM1_EXTCLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTCLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTCLK_TRIGIN_MASK) +/*! @} */ + +/*! @name AOI0_IN - AOI0 trigger inputs */ +/*! @{ */ + +#define INPUTMUX_AOI0_IN_IN_MASK (0x3FU) +#define INPUTMUX_AOI0_IN_IN_SHIFT (0U) +/*! IN - Input trigger assignments + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT1 + * 0b000010..SCT_OUT0 + * 0b000011..SCT_OUT1 + * 0b000100..SCT_OUT2 + * 0b000101..SCT_OUT3 + * 0b000110..T0_MAT3 + * 0b000111..T1_MAT3 + * 0b001000..T2_MAT3 + * 0b001001..T2_MAT2 + * 0b001010..T3_MAT2 + * 0b001011..T4_MAT2 + * 0b001100..ACMP0_OUT + * 0b001101..GPIOINT_BMATCH + * 0b001110..ADC0_IRQ + * 0b001111..ADC1_IRQ + * 0b010000..ADC0_tcomp[0] + * 0b010001..ADC0_tcomp[1] + * 0b010010..ADC0_tcomp[2] + * 0b010011..ADC0_tcomp[3] + * 0b010100..ADC1_tcomp[0] + * 0b010101..ADC1_tcomp[1] + * 0b010110..ADC1_tcomp[2] + * 0b010111..ADC1_tcomp[3] + * 0b011000..HSCMP0_OUT + * 0b011001..HSCMP1_OUT + * 0b011010..HSCMP2_OUT + * 0b011011..PWM0_SM0_MUX_TRIG0 + * 0b011100..PWM0_SM0_MUX_TRIG1 + * 0b011101..PWM0_SM1_MUX_TRIG0 + * 0b011110..PWM0_SM1_MUX_TRIG1 + * 0b011111..PWM0_SM2_MUX_TRIG0 + * 0b100000..PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 + * 0b100010..PWM0_SM3_MUX_TRIG1 + * 0b100011..PWM1_SM0_MUX_TRIG0 + * 0b100100..PWM1_SM0_MUX_TRIG1 + * 0b100101..PWM1_SM1_MUX_TRIG0 + * 0b100110..PWM1_SM1_MUX_TRIG1 + * 0b100111..PWM1_SM2_MUX_TRIG0 + * 0b101000..PWM1_SM2_MUX_TRIG1 + * 0b101001..PWM1_SM3_MUX_TRIG0 + * 0b101010..PWM1_SM3_MUX_TRIG1 + * 0b101011..ENC0_CMP/POS_MATCH + * 0b101100..ENC1_CMP/POS_MATCH + * 0b101101..EXTTRIG_IN0 + * 0b101110..EXTTRIG_IN1 + * 0b101111..EXTTRIG_IN2 + * 0b110000..EXTTRIG_IN3 + * 0b110001..Reserved + * 0b110010..Reserved + * 0b110011..DMA0_TRIGOUT0 + * 0b110100..DMA0_TRIGOUT1 + * 0b110101..DMA0_TRIGOUT2 + * 0b110110..DMA0_TRIGOUT3 + * 0b110111..DMA0_TRIGOUT4 + * 0b111000..DMA0_TRIGOUT5 + * 0b111001..DMA0_TRIGOUT6 + * 0b111010..DMA1_TRIGOUT0 + * 0b111011..DMA1_TRIGOUT1 + * 0b111100..DMA1_TRIGOUT2 + */ +#define INPUTMUX_AOI0_IN_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_IN_IN_SHIFT)) & INPUTMUX_AOI0_IN_IN_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI0_IN */ +#define INPUTMUX_AOI0_INPUTTRIGGER0 (16U) + +/*! @name AOI1_IN - AOI1 trigger inputs */ +/*! @{ */ + +#define INPUTMUX_AOI1_IN_IN_MASK (0x3FU) +#define INPUTMUX_AOI1_IN_IN_SHIFT (0U) +/*! IN - Input trigger assignments + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT1 + * 0b000010..SCT_OUT0 + * 0b000011..SCT_OUT1 + * 0b000100..SCT_OUT2 + * 0b000101..SCT_OUT3 + * 0b000110..T0_MAT3 + * 0b000111..T1_MAT3 + * 0b001000..T2_MAT3 + * 0b001001..T2_MAT2 + * 0b001010..T3_MAT2 + * 0b001011..T4_MAT2 + * 0b001100..ACMP0_OUT + * 0b001101..GPIOINT_BMATCH + * 0b001110..ADC0_IRQ + * 0b001111..ADC1_IRQ + * 0b010000..ADC0_tcomp[0] + * 0b010001..ADC0_tcomp[1] + * 0b010010..ADC0_tcomp[2] + * 0b010011..ADC0_tcomp[3] + * 0b010100..ADC1_tcomp[0] + * 0b010101..ADC1_tcomp[1] + * 0b010110..ADC1_tcomp[2] + * 0b010111..ADC1_tcomp[3] + * 0b011000..HSCMP0_OUT + * 0b011001..HSCMP1_OUT + * 0b011010..HSCMP2_OUT + * 0b011011..PWM0_SM0_MUX_TRIG0 + * 0b011100..PWM0_SM0_MUX_TRIG1 + * 0b011101..PWM0_SM1_MUX_TRIG0 + * 0b011110..PWM0_SM1_MUX_TRIG1 + * 0b011111..PWM0_SM2_MUX_TRIG0 + * 0b100000..PWM0_SM2_MUX_TRIG1 + * 0b100001..PWM0_SM3_MUX_TRIG0 + * 0b100010..PWM0_SM3_MUX_TRIG1 + * 0b100011..PWM1_SM0_MUX_TRIG0 + * 0b100100..PWM1_SM0_MUX_TRIG1 + * 0b100101..PWM1_SM1_MUX_TRIG0 + * 0b100110..PWM1_SM1_MUX_TRIG1 + * 0b100111..PWM1_SM2_MUX_TRIG0 + * 0b101000..PWM1_SM2_MUX_TRIG1 + * 0b101001..PWM1_SM3_MUX_TRIG0 + * 0b101010..PWM1_SM3_MUX_TRIG1 + * 0b101011..ENC0_CMP/POS_MATCH + * 0b101100..ENC1_CMP/POS_MATCH + * 0b101101..EXTTRIG_IN0 + * 0b101110..EXTTRIG_IN1 + * 0b101111..EXTTRIG_IN2 + * 0b110000..EXTTRIG_IN3 + * 0b110001..Reserved + * 0b110010..Reserved + * 0b110011..DMA0_TRIGOUT0 + * 0b110100..DMA0_TRIGOUT1 + * 0b110101..DMA0_TRIGOUT2 + * 0b110110..DMA0_TRIGOUT3 + * 0b110111..DMA0_TRIGOUT4 + * 0b111000..DMA0_TRIGOUT5 + * 0b111001..DMA0_TRIGOUT6 + * 0b111010..DMA1_TRIGOUT0 + * 0b111011..DMA1_TRIGOUT1 + * 0b111100..DMA1_TRIGOUT2 + */ +#define INPUTMUX_AOI1_IN_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_IN_IN_SHIFT)) & INPUTMUX_AOI1_IN_IN_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI1_IN */ +#define INPUTMUX_AOI1_INPUTTRIGGER0 (16U) + +/*! @name AOIX_EXT_TRIGN_AOI_EXT_TRIG - AOI External Trigger Inputs */ +/*! @{ */ + +#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_MASK (0x1FU) +#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - AOI external trigger inputs from 0 to 4. + * 0b00000..PIN_INT0 + * 0b00001..PIN_INT1 + * 0b00010..ADC0_IRQ + * 0b00011..ADC1_IRQ + * 0b00100..ADC0_tcomp[0] + * 0b00101..ADC1_tcomp[0] + * 0b00110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b00111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b01000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b01001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b01010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b01011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b01100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b01101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b01110..ENC0_CMP/POS_MATCH + * 0b01111..ENC1_CMP/POS_MATCH + * 0b10000..AOI0_OUT0 + * 0b10001..AOI0_OUT1 + * 0b10010..AOI0_OUT2 + * 0b10011..AOI0_OUT3 + * 0b10100..AOI1_OUT0 + * 0b10101..AOI1_OUT1 + * 0b10110..AOI1_OUT2 + * 0b10111..AOI1_OUT3 + * 0b11000..TMPR_OUT + * 0b11001-0b11111..None + */ +#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_SHIFT)) & INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG */ +#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_COUNT (8U) + +/*! @name HSCMP1_TRIG - Input connections for HSCMP1 */ +/*! @{ */ + +#define INPUTMUX_HSCMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_HSCMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP1 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT7 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT7 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T0_MAT1 + * 0b001001..T4_MAT1 + * 0b001010..Reserved + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[1] + * 0b001110..ADC1_tcomp[1] + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b011001..ENC0_CMP/POS_MATCH + * 0b011010..ENC1_CMP/POS_MATCH + * 0b011011..AOI0_OUT0 + * 0b011100..AOI0_OUT1 + * 0b011101..AOI0_OUT2 + * 0b011110..AOI0_OUT3 + * 0b011111..AOI1_OUT0 + * 0b100000..AOI1_OUT1 + * 0b100001..AOI1_OUT2 + * 0b100010..AOI1_OUT3 + * 0b100011..DMA0_TRIGOUT0 + * 0b100100..DMA0_TRIGOUT1 + * 0b100101..DMA0_TRIGOUT2 + */ +#define INPUTMUX_HSCMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name HSCMP2_TRIG - Input connections for HSCMP2 */ +/*! @{ */ + +#define INPUTMUX_HSCMP2_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_HSCMP2_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP2 input trigger + * 0b000000..PIN_INT0 + * 0b000001..PIN_INT4 + * 0b000010..SCT_OUT4 + * 0b000011..SCT_OUT5 + * 0b000100..SCT_OUT8 + * 0b000101..T0_MAT3 + * 0b000110..T1_MAT3 + * 0b000111..T2_MAT3 + * 0b001000..T0_MAT2 + * 0b001001..T4_MAT2 + * 0b001010..Reserved + * 0b001011..ARM_TXEV + * 0b001100..GPIOINT_BMATCH + * 0b001101..ADC0_tcomp[2] + * 0b001110..ADC1_tcomp[2] + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1 + * 0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1 + * 0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1 + * 0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1 + * 0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1 + * 0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1 + * 0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1 + * 0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1 + * 0b011001..ENC0_CMP/POS_MATCH + * 0b011010..ENC1_CMP/POS_MATCH + * 0b011011..AOI0_OUT0 + * 0b011100..AOI0_OUT1 + * 0b011101..AOI0_OUT2 + * 0b011110..AOI0_OUT3 + * 0b011111..AOI1_OUT0 + * 0b100000..AOI1_OUT1 + * 0b100001..AOI1_OUT2 + * 0b100010..AOI1_OUT3 + * 0b100011..DMA0_TRIGOUT0 + * 0b100100..DMA0_TRIGOUT1 + * 0b100101..DMA0_TRIGOUT2 + */ +#define INPUTMUX_HSCMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP2_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_INMUX32 - Trigger select for DMA0 channel */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_INMUX32_INP_MASK (0x3FU) +#define INPUTMUX_DMA0_ITRIG_INMUX32_INP_SHIFT (0U) +/*! INP - Trigger input number (binary value) for DMA channel n (n = 32 to 51). + * 0b000000..FlexSPI_RX + * 0b000001..FlexSPI_TX + * 0b000010..GPIO_INT0 + * 0b000011..GPIO_INT1 + * 0b000100..GPIO_INT2 + * 0b000101..GPIO_INT3 + * 0b000110..T0_DMAREQ_M0 + * 0b000111..T0_DMAREQ_M1 + * 0b001000..T1_DMAREQ_M0 + * 0b001001..T1_DMAREQ_M1 + * 0b001010..T2_DMAREQ_M0 + * 0b001011..T2_DMAREQ_M1 + * 0b001100..T3_DMAREQ_M0 + * 0b001101..T3_DMAREQ_M1 + * 0b001110..T4_DMAREQ_M0 + * 0b001111..T4_DMAREQ_M1 + * 0b010000..ACMP0_OUT + * 0b010001..SDMA0_TRIGOUT_A + * 0b010010..SDMA0_TRIGOUT_B + * 0b010011..SDMA0_TRIGOUT_C + * 0b010100..SDMA0_TRIGOUT_D + * 0b010101..SCT_DMA0 + * 0b010110..SCT_DMA1 + * 0b010111..ADC0_tcomp[0] + * 0b011000..ADC1_tcomp[0] + * 0b011001..HSCMP0 + * 0b011010..HSCMP1 + * 0b011011..HSCMP2 + * 0b011100..AOI0_OUT0 + * 0b011101..AOI0_OUT1 + * 0b011110..AOI0_OUT2 + * 0b011111..AOI0_OUT3 + * 0b100000..AOI1_OUT0 + * 0b100001..AOI1_OUT1 + * 0b100010..AOI1_OUT2 + * 0b100011..AOI1_OUT3 + * 0b100100..FlexPWM0_req_capt0 + * 0b100101..FlexPWM0_req_capt1 + * 0b100110..FlexPWM0_req_capt2 + * 0b100111..FlexPWM0_req_capt3 + * 0b101000..FlexPWM0_req_val0 + * 0b101001..FlexPWM0_req_val1 + * 0b101010..FlexPWM0_req_val2 + * 0b101011..FlexPWM0_req_val3 + * 0b101100..FlexPWM1_req_capt0 + * 0b101101..FlexPWM1_req_capt1 + * 0b101110..FlexPWM1_req_capt2 + * 0b101111..FlexPWM1_req_capt3 + * 0b110000..FlexPWM1_req_val0 + * 0b110001..FlexPWM1_req_val1 + * 0b110010..FlexPWM1_req_val2 + * 0b110011..FlexPWM1_req_val3 + * 0b110100..TMPR_OUT + * 0b110110-0b111111..Reserved + */ +#define INPUTMUX_DMA0_ITRIG_INMUX32_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX32_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX32_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX32 */ +#define INPUTMUX_DMA0_ITRIG_INMUX32_COUNT (20U) + +/*! @name DMA0_REQEN0 - Enable DMA0 requests */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA0_MASK (0x1U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA0_SHIFT (0U) +/*! REQ_ENA0 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA0_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA1_MASK (0x2U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA1_SHIFT (1U) +/*! REQ_ENA1 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA1_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA2_MASK (0x4U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA2_SHIFT (2U) +/*! REQ_ENA2 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA2_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA3_MASK (0x8U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA3_SHIFT (3U) +/*! REQ_ENA3 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA3_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA4_MASK (0x10U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA4_SHIFT (4U) +/*! REQ_ENA4 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA4_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA5_MASK (0x20U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA5_SHIFT (5U) +/*! REQ_ENA5 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA5_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA6_MASK (0x40U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA6_SHIFT (6U) +/*! REQ_ENA6 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA6_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA7_MASK (0x80U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA7_SHIFT (7U) +/*! REQ_ENA7 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA7_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA8_MASK (0x100U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA8_SHIFT (8U) +/*! REQ_ENA8 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA8_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA9_MASK (0x200U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA9_SHIFT (9U) +/*! REQ_ENA9 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA9_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA10_MASK (0x400U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA10_SHIFT (10U) +/*! REQ_ENA10 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA10_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA11_MASK (0x800U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA11_SHIFT (11U) +/*! REQ_ENA11 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA11_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA12_MASK (0x1000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA12_SHIFT (12U) +/*! REQ_ENA12 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA12_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA13_MASK (0x2000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA13_SHIFT (13U) +/*! REQ_ENA13 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA13_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA14_MASK (0x4000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA14_SHIFT (14U) +/*! REQ_ENA14 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA14_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA15_MASK (0x8000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA15_SHIFT (15U) +/*! REQ_ENA15 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA15_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA16_MASK (0x10000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA16_SHIFT (16U) +/*! REQ_ENA16 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA16_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA17_MASK (0x20000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA17_SHIFT (17U) +/*! REQ_ENA17 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA17_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA18_MASK (0x40000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA18_SHIFT (18U) +/*! REQ_ENA18 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA18_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA19_MASK (0x80000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA19_SHIFT (19U) +/*! REQ_ENA19 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA19_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA20_MASK (0x100000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA20_SHIFT (20U) +/*! REQ_ENA20 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA20_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA20_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA21_MASK (0x200000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA21_SHIFT (21U) +/*! REQ_ENA21 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA21_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA21_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA22_MASK (0x400000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA22_SHIFT (22U) +/*! REQ_ENA22 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA22_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA22_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA23_MASK (0x800000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA23_SHIFT (23U) +/*! REQ_ENA23 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA23_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA23_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA24_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA24_SHIFT (24U) +/*! REQ_ENA24 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA24_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA24_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA25_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA25_SHIFT (25U) +/*! REQ_ENA25 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA25_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA25_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA26_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA26_SHIFT (26U) +/*! REQ_ENA26 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA26_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA26_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA27_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA27_SHIFT (27U) +/*! REQ_ENA27 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA27_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA27_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA28_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA28_SHIFT (28U) +/*! REQ_ENA28 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA28_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA28_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA29_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA29_SHIFT (29U) +/*! REQ_ENA29 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA29_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA29_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA30_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA30_SHIFT (30U) +/*! REQ_ENA30 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA30_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA30_MASK) + +#define INPUTMUX_DMA0_REQEN0_REQ_ENA31_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQEN0_REQ_ENA31_SHIFT (31U) +/*! REQ_ENA31 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQEN0_REQ_ENA31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA31_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA31_MASK) +/*! @} */ + +/*! @name DMA0_REQEN1 - Enable DMA0 requests */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA0_MASK (0x1U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA0_SHIFT (0U) +/*! REQ_ENA0 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA0_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA1_MASK (0x2U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA1_SHIFT (1U) +/*! REQ_ENA1 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA1_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA2_MASK (0x4U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA2_SHIFT (2U) +/*! REQ_ENA2 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA2_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA3_MASK (0x8U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA3_SHIFT (3U) +/*! REQ_ENA3 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA3_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA4_MASK (0x10U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA4_SHIFT (4U) +/*! REQ_ENA4 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA4_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA5_MASK (0x20U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA5_SHIFT (5U) +/*! REQ_ENA5 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA5_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA6_MASK (0x40U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA6_SHIFT (6U) +/*! REQ_ENA6 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA6_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA7_MASK (0x80U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA7_SHIFT (7U) +/*! REQ_ENA7 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA7_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA8_MASK (0x100U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA8_SHIFT (8U) +/*! REQ_ENA8 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA8_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA9_MASK (0x200U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA9_SHIFT (9U) +/*! REQ_ENA9 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA9_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA10_MASK (0x400U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA10_SHIFT (10U) +/*! REQ_ENA10 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA10_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA11_MASK (0x800U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA11_SHIFT (11U) +/*! REQ_ENA11 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA11_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA12_MASK (0x1000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA12_SHIFT (12U) +/*! REQ_ENA12 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA12_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA13_MASK (0x2000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA13_SHIFT (13U) +/*! REQ_ENA13 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA13_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA14_MASK (0x4000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA14_SHIFT (14U) +/*! REQ_ENA14 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA14_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA15_MASK (0x8000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA15_SHIFT (15U) +/*! REQ_ENA15 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA15_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA16_MASK (0x10000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA16_SHIFT (16U) +/*! REQ_ENA16 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA16_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA17_MASK (0x20000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA17_SHIFT (17U) +/*! REQ_ENA17 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA17_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA18_MASK (0x40000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA18_SHIFT (18U) +/*! REQ_ENA18 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA18_MASK) + +#define INPUTMUX_DMA0_REQEN1_REQ_ENA19_MASK (0x80000U) +#define INPUTMUX_DMA0_REQEN1_REQ_ENA19_SHIFT (19U) +/*! REQ_ENA19 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled. + */ +#define INPUTMUX_DMA0_REQEN1_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA19_MASK) +/*! @} */ + +/*! @name DMA0_REQEN0_SET - Set bits in DMA0_REQEN0 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQEN0_SET_SET0_MASK (0x1U) +#define INPUTMUX_DMA0_REQEN0_SET_SET0_SHIFT (0U) +/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET0_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET0_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET1_MASK (0x2U) +#define INPUTMUX_DMA0_REQEN0_SET_SET1_SHIFT (1U) +/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET1_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET1_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET2_MASK (0x4U) +#define INPUTMUX_DMA0_REQEN0_SET_SET2_SHIFT (2U) +/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET2_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET2_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET3_MASK (0x8U) +#define INPUTMUX_DMA0_REQEN0_SET_SET3_SHIFT (3U) +/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET3_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET3_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET4_MASK (0x10U) +#define INPUTMUX_DMA0_REQEN0_SET_SET4_SHIFT (4U) +/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET4_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET4_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET5_MASK (0x20U) +#define INPUTMUX_DMA0_REQEN0_SET_SET5_SHIFT (5U) +/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET5_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET5_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET6_MASK (0x40U) +#define INPUTMUX_DMA0_REQEN0_SET_SET6_SHIFT (6U) +/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET6_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET6_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET7_MASK (0x80U) +#define INPUTMUX_DMA0_REQEN0_SET_SET7_SHIFT (7U) +/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET7_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET7_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET8_MASK (0x100U) +#define INPUTMUX_DMA0_REQEN0_SET_SET8_SHIFT (8U) +/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET8_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET8_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET9_MASK (0x200U) +#define INPUTMUX_DMA0_REQEN0_SET_SET9_SHIFT (9U) +/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET9_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET9_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET10_MASK (0x400U) +#define INPUTMUX_DMA0_REQEN0_SET_SET10_SHIFT (10U) +/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET10_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET10_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET11_MASK (0x800U) +#define INPUTMUX_DMA0_REQEN0_SET_SET11_SHIFT (11U) +/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET11_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET11_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET12_MASK (0x1000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET12_SHIFT (12U) +/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET12_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET12_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET13_MASK (0x2000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET13_SHIFT (13U) +/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET13_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET13_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET14_MASK (0x4000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET14_SHIFT (14U) +/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET14_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET14_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET15_MASK (0x8000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET15_SHIFT (15U) +/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET15_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET15_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET16_MASK (0x10000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET16_SHIFT (16U) +/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET16_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET16_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET17_MASK (0x20000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET17_SHIFT (17U) +/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET17_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET17_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET18_MASK (0x40000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET18_SHIFT (18U) +/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET18_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET18_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET19_MASK (0x80000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET19_SHIFT (19U) +/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET19_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET19_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET20_MASK (0x100000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET20_SHIFT (20U) +/*! SET20 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET20_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET20_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET21_MASK (0x200000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET21_SHIFT (21U) +/*! SET21 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET21_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET21_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET22_MASK (0x400000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET22_SHIFT (22U) +/*! SET22 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET22_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET22_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET23_MASK (0x800000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET23_SHIFT (23U) +/*! SET23 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET23_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET23_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET24_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET24_SHIFT (24U) +/*! SET24 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET24_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET24_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET25_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET25_SHIFT (25U) +/*! SET25 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET25_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET25_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET26_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET26_SHIFT (26U) +/*! SET26 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET26_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET26_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET27_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET27_SHIFT (27U) +/*! SET27 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET27_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET27_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET28_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET28_SHIFT (28U) +/*! SET28 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET28_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET28_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET29_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET29_SHIFT (29U) +/*! SET29 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET29_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET29_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET30_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET30_SHIFT (30U) +/*! SET30 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET30_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET30_MASK) + +#define INPUTMUX_DMA0_REQEN0_SET_SET31_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQEN0_SET_SET31_SHIFT (31U) +/*! SET31 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_SET_SET31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET31_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET31_MASK) +/*! @} */ + +/*! @name DMA0_REQEN1_SET - Set bits in DMA0_REQEN1 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_MASK (0x1U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_SHIFT (0U) +/*! REQ_ENA0 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_MASK (0x2U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_SHIFT (1U) +/*! REQ_ENA1 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_MASK (0x4U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_SHIFT (2U) +/*! REQ_ENA2 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_MASK (0x8U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_SHIFT (3U) +/*! REQ_ENA3 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_MASK (0x10U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_SHIFT (4U) +/*! REQ_ENA4 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_MASK (0x20U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_SHIFT (5U) +/*! REQ_ENA5 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_MASK (0x40U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_SHIFT (6U) +/*! REQ_ENA6 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_MASK (0x80U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_SHIFT (7U) +/*! REQ_ENA7 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_MASK (0x100U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_SHIFT (8U) +/*! REQ_ENA8 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_MASK (0x200U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_SHIFT (9U) +/*! REQ_ENA9 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_MASK (0x400U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_SHIFT (10U) +/*! REQ_ENA10 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_MASK (0x800U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_SHIFT (11U) +/*! REQ_ENA11 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_MASK (0x1000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_SHIFT (12U) +/*! REQ_ENA12 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_MASK (0x2000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_SHIFT (13U) +/*! REQ_ENA13 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_MASK (0x4000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_SHIFT (14U) +/*! REQ_ENA14 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_MASK (0x8000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_SHIFT (15U) +/*! REQ_ENA15 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_MASK (0x10000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_SHIFT (16U) +/*! REQ_ENA16 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_MASK (0x20000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_SHIFT (17U) +/*! REQ_ENA17 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_MASK (0x40000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_SHIFT (18U) +/*! REQ_ENA18 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_MASK) + +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_MASK (0x80000U) +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_SHIFT (19U) +/*! REQ_ENA19 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_MASK) +/*! @} */ + +/*! @name DMA0_REQEN0_CLR - Clear bits in DMA0_REQEN0 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR0_MASK (0x1U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR0_SHIFT (0U) +/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR0_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR1_MASK (0x2U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR1_SHIFT (1U) +/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR1_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR2_MASK (0x4U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR2_SHIFT (2U) +/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR2_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR3_MASK (0x8U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR3_SHIFT (3U) +/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR3_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR4_MASK (0x10U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR4_SHIFT (4U) +/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR4_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR5_MASK (0x20U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR5_SHIFT (5U) +/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR5_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR6_MASK (0x40U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR6_SHIFT (6U) +/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR6_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR7_MASK (0x80U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR7_SHIFT (7U) +/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR7_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR8_MASK (0x100U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR8_SHIFT (8U) +/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR8_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR9_MASK (0x200U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR9_SHIFT (9U) +/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR9_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR10_MASK (0x400U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR10_SHIFT (10U) +/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR10_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR11_MASK (0x800U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR11_SHIFT (11U) +/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR11_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR12_MASK (0x1000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR12_SHIFT (12U) +/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR12_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR13_MASK (0x2000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR13_SHIFT (13U) +/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR13_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR14_MASK (0x4000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR14_SHIFT (14U) +/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR14_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR15_MASK (0x8000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR15_SHIFT (15U) +/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR15_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR16_MASK (0x10000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR16_SHIFT (16U) +/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR16_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR17_MASK (0x20000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR17_SHIFT (17U) +/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR17_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR18_MASK (0x40000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR18_SHIFT (18U) +/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR18_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR19_MASK (0x80000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR19_SHIFT (19U) +/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR19_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR20_MASK (0x100000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR20_SHIFT (20U) +/*! CLR20 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR20_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR20_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR21_MASK (0x200000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR21_SHIFT (21U) +/*! CLR21 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR21_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR21_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR22_MASK (0x400000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR22_SHIFT (22U) +/*! CLR22 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR22_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR22_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR23_MASK (0x800000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR23_SHIFT (23U) +/*! CLR23 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR23_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR23_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR24_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR24_SHIFT (24U) +/*! CLR24 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR24_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR24_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR25_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR25_SHIFT (25U) +/*! CLR25 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR25_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR25_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR26_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR26_SHIFT (26U) +/*! CLR26 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR26_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR26_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR27_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR27_SHIFT (27U) +/*! CLR27 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR27_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR27_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR28_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR28_SHIFT (28U) +/*! CLR28 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR28_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR28_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR29_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR29_SHIFT (29U) +/*! CLR29 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR29_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR29_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR30_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR30_SHIFT (30U) +/*! CLR30 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR30_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR30_MASK) + +#define INPUTMUX_DMA0_REQEN0_CLR_CLR31_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQEN0_CLR_CLR31_SHIFT (31U) +/*! CLR31 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register. + */ +#define INPUTMUX_DMA0_REQEN0_CLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR31_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR31_MASK) +/*! @} */ + +/*! @name DMA0_REQEN1_CLR - Clear bits in DMA0_REQEN1 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_MASK (0x1U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_SHIFT (0U) +/*! REQ_ENA0 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_MASK (0x2U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_SHIFT (1U) +/*! REQ_ENA1 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_MASK (0x4U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_SHIFT (2U) +/*! REQ_ENA2 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_MASK (0x8U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_SHIFT (3U) +/*! REQ_ENA3 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_MASK (0x10U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_SHIFT (4U) +/*! REQ_ENA4 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_MASK (0x20U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_SHIFT (5U) +/*! REQ_ENA5 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_MASK (0x40U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_SHIFT (6U) +/*! REQ_ENA6 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_MASK (0x80U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_SHIFT (7U) +/*! REQ_ENA7 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_MASK (0x100U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_SHIFT (8U) +/*! REQ_ENA8 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_MASK (0x200U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_SHIFT (9U) +/*! REQ_ENA9 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_MASK (0x400U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_SHIFT (10U) +/*! REQ_ENA10 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_MASK (0x800U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_SHIFT (11U) +/*! REQ_ENA11 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_MASK (0x1000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_SHIFT (12U) +/*! REQ_ENA12 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_MASK (0x2000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_SHIFT (13U) +/*! REQ_ENA13 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_MASK (0x4000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_SHIFT (14U) +/*! REQ_ENA14 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_MASK (0x8000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_SHIFT (15U) +/*! REQ_ENA15 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_MASK (0x10000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_SHIFT (16U) +/*! REQ_ENA16 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_MASK (0x20000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_SHIFT (17U) +/*! REQ_ENA17 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_MASK (0x40000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_SHIFT (18U) +/*! REQ_ENA18 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_MASK) + +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_MASK (0x80000U) +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_SHIFT (19U) +/*! REQ_ENA19 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register. + */ +#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_MASK) +/*! @} */ + +/*! @name DMA1_REQEN - Enable DMA1 requests */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQEN_REQ_ENA0_MASK (0x1U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA0_SHIFT (0U) +/*! REQ_ENA0 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA0_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA0_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA1_MASK (0x2U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA1_SHIFT (1U) +/*! REQ_ENA1 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA1_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA1_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA2_MASK (0x4U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA2_SHIFT (2U) +/*! REQ_ENA2 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA2_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA2_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA3_MASK (0x8U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA3_SHIFT (3U) +/*! REQ_ENA3 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA3_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA3_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA4_MASK (0x10U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA4_SHIFT (4U) +/*! REQ_ENA4 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA4_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA4_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA5_MASK (0x20U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA5_SHIFT (5U) +/*! REQ_ENA5 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA5_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA5_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA6_MASK (0x40U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA6_SHIFT (6U) +/*! REQ_ENA6 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA6_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA6_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA7_MASK (0x80U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA7_SHIFT (7U) +/*! REQ_ENA7 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA7_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA7_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA8_MASK (0x100U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA8_SHIFT (8U) +/*! REQ_ENA8 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA8_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA8_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA9_MASK (0x200U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA9_SHIFT (9U) +/*! REQ_ENA9 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA9_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA9_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA10_MASK (0x400U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA10_SHIFT (10U) +/*! REQ_ENA10 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA10_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA10_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA11_MASK (0x800U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA11_SHIFT (11U) +/*! REQ_ENA11 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA11_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA11_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA12_MASK (0x1000U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA12_SHIFT (12U) +/*! REQ_ENA12 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA12_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA12_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA13_MASK (0x2000U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA13_SHIFT (13U) +/*! REQ_ENA13 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA13_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA13_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA14_MASK (0x4000U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA14_SHIFT (14U) +/*! REQ_ENA14 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA14_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA14_MASK) + +#define INPUTMUX_DMA1_REQEN_REQ_ENA15_MASK (0x8000U) +#define INPUTMUX_DMA1_REQEN_REQ_ENA15_SHIFT (15U) +/*! REQ_ENA15 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQEN_REQ_ENA15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA15_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA15_MASK) +/*! @} */ + +/*! @name DMA1_REQEN_SET - Set bits in DMA1_REQEN register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQEN_SET_SET0_MASK (0x1U) +#define INPUTMUX_DMA1_REQEN_SET_SET0_SHIFT (0U) +/*! SET0 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET0_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET0_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET1_MASK (0x2U) +#define INPUTMUX_DMA1_REQEN_SET_SET1_SHIFT (1U) +/*! SET1 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET1_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET1_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET2_MASK (0x4U) +#define INPUTMUX_DMA1_REQEN_SET_SET2_SHIFT (2U) +/*! SET2 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET2_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET2_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET3_MASK (0x8U) +#define INPUTMUX_DMA1_REQEN_SET_SET3_SHIFT (3U) +/*! SET3 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET3_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET3_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET4_MASK (0x10U) +#define INPUTMUX_DMA1_REQEN_SET_SET4_SHIFT (4U) +/*! SET4 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET4_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET4_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET5_MASK (0x20U) +#define INPUTMUX_DMA1_REQEN_SET_SET5_SHIFT (5U) +/*! SET5 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET5_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET5_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET6_MASK (0x40U) +#define INPUTMUX_DMA1_REQEN_SET_SET6_SHIFT (6U) +/*! SET6 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET6_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET6_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET7_MASK (0x80U) +#define INPUTMUX_DMA1_REQEN_SET_SET7_SHIFT (7U) +/*! SET7 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET7_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET7_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET8_MASK (0x100U) +#define INPUTMUX_DMA1_REQEN_SET_SET8_SHIFT (8U) +/*! SET8 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET8_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET8_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET9_MASK (0x200U) +#define INPUTMUX_DMA1_REQEN_SET_SET9_SHIFT (9U) +/*! SET9 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET9_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET9_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET10_MASK (0x400U) +#define INPUTMUX_DMA1_REQEN_SET_SET10_SHIFT (10U) +/*! SET10 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET10_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET10_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET11_MASK (0x800U) +#define INPUTMUX_DMA1_REQEN_SET_SET11_SHIFT (11U) +/*! SET11 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET11_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET11_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET12_MASK (0x1000U) +#define INPUTMUX_DMA1_REQEN_SET_SET12_SHIFT (12U) +/*! SET12 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET12_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET12_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET13_MASK (0x2000U) +#define INPUTMUX_DMA1_REQEN_SET_SET13_SHIFT (13U) +/*! SET13 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET13_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET13_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET14_MASK (0x4000U) +#define INPUTMUX_DMA1_REQEN_SET_SET14_SHIFT (14U) +/*! SET14 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET14_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET14_MASK) + +#define INPUTMUX_DMA1_REQEN_SET_SET15_MASK (0x8000U) +#define INPUTMUX_DMA1_REQEN_SET_SET15_SHIFT (15U) +/*! SET15 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET15_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET15_MASK) +/*! @} */ + +/*! @name DMA1_REQEN_CLR - Clear bits in DMA1_REQEN register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQEN_CLR_CLR0_MASK (0x1U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR0_SHIFT (0U) +/*! CLR0 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR0_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR0_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR1_MASK (0x2U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR1_SHIFT (1U) +/*! CLR1 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR1_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR1_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR2_MASK (0x4U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR2_SHIFT (2U) +/*! CLR2 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR2_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR2_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR3_MASK (0x8U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR3_SHIFT (3U) +/*! CLR3 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR3_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR3_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR4_MASK (0x10U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR4_SHIFT (4U) +/*! CLR4 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR4_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR4_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR5_MASK (0x20U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR5_SHIFT (5U) +/*! CLR5 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR5_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR5_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR6_MASK (0x40U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR6_SHIFT (6U) +/*! CLR6 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR6_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR6_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR7_MASK (0x80U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR7_SHIFT (7U) +/*! CLR7 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR7_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR7_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR8_MASK (0x100U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR8_SHIFT (8U) +/*! CLR8 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR8_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR8_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR9_MASK (0x200U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR9_SHIFT (9U) +/*! CLR9 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR9_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR9_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR10_MASK (0x400U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR10_SHIFT (10U) +/*! CLR10 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR10_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR10_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR11_MASK (0x800U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR11_SHIFT (11U) +/*! CLR11 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR11_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR11_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR12_MASK (0x1000U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR12_SHIFT (12U) +/*! CLR12 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR12_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR12_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR13_MASK (0x2000U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR13_SHIFT (13U) +/*! CLR13 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR13_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR13_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR14_MASK (0x4000U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR14_SHIFT (14U) +/*! CLR14 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR14_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR14_MASK) + +#define INPUTMUX_DMA1_REQEN_CLR_CLR15_MASK (0x8000U) +#define INPUTMUX_DMA1_REQEN_CLR_CLR15_SHIFT (15U) +/*! CLR15 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register + */ +#define INPUTMUX_DMA1_REQEN_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR15_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR15_MASK) +/*! @} */ + +/*! @name DMA0_ITRIGEN0 - Enable DMA0 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_MASK (0x1U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_SHIFT (0U) +/*! ITRIGEN0 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_MASK (0x2U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_SHIFT (1U) +/*! ITRIGEN1 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_MASK (0x4U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_SHIFT (2U) +/*! ITRIGEN2 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_MASK (0x8U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_SHIFT (3U) +/*! ITRIGEN3 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_MASK (0x10U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_SHIFT (4U) +/*! ITRIGEN4 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_MASK (0x20U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_SHIFT (5U) +/*! ITRIGEN5 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_MASK (0x40U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_SHIFT (6U) +/*! ITRIGEN6 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_MASK (0x80U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_SHIFT (7U) +/*! ITRIGEN7 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_MASK (0x100U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_SHIFT (8U) +/*! ITRIGEN8 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_MASK (0x200U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_SHIFT (9U) +/*! ITRIGEN9 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_MASK (0x400U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_SHIFT (10U) +/*! ITRIGEN10 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_MASK (0x800U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_SHIFT (11U) +/*! ITRIGEN11 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_MASK (0x1000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_SHIFT (12U) +/*! ITRIGEN12 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_MASK (0x2000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_SHIFT (13U) +/*! ITRIGEN13 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_MASK (0x4000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_SHIFT (14U) +/*! ITRIGEN14 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_MASK (0x8000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_SHIFT (15U) +/*! ITRIGEN15 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_MASK (0x10000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_SHIFT (16U) +/*! ITRIGEN16 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_MASK (0x20000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_SHIFT (17U) +/*! ITRIGEN17 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_MASK (0x40000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_SHIFT (18U) +/*! ITRIGEN18 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_MASK (0x80000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_SHIFT (19U) +/*! ITRIGEN19 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_MASK (0x100000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_SHIFT (20U) +/*! ITRIGEN20 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_MASK (0x200000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_SHIFT (21U) +/*! ITRIGEN21 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_MASK (0x400000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_SHIFT (22U) +/*! ITRIGEN22 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_MASK (0x800000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_SHIFT (23U) +/*! ITRIGEN23 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_MASK (0x1000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_SHIFT (24U) +/*! ITRIGEN24 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_MASK (0x2000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_SHIFT (25U) +/*! ITRIGEN25 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_MASK (0x4000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_SHIFT (26U) +/*! ITRIGEN26 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_MASK (0x8000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_SHIFT (27U) +/*! ITRIGEN27 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_MASK (0x10000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_SHIFT (28U) +/*! ITRIGEN28 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_MASK (0x20000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_SHIFT (29U) +/*! ITRIGEN29 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_MASK (0x40000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_SHIFT (30U) +/*! ITRIGEN30 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_MASK (0x80000000U) +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_SHIFT (31U) +/*! ITRIGEN31 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_MASK) +/*! @} */ + +/*! @name DMA0_ITRIGEN1 - Enable DMA0 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_MASK (0x1U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_SHIFT (0U) +/*! ITRIGEN0 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_MASK (0x2U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_SHIFT (1U) +/*! ITRIGEN1 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_MASK (0x4U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_SHIFT (2U) +/*! ITRIGEN2 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_MASK (0x8U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_SHIFT (3U) +/*! ITRIGEN3 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_MASK (0x10U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_SHIFT (4U) +/*! ITRIGEN4 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_MASK (0x20U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_SHIFT (5U) +/*! ITRIGEN5 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_MASK (0x40U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_SHIFT (6U) +/*! ITRIGEN6 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_MASK (0x80U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_SHIFT (7U) +/*! ITRIGEN7 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_MASK (0x100U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_SHIFT (8U) +/*! ITRIGEN8 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_MASK (0x200U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_SHIFT (9U) +/*! ITRIGEN9 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_MASK (0x400U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_SHIFT (10U) +/*! ITRIGEN10 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_MASK (0x800U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_SHIFT (11U) +/*! ITRIGEN11 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_MASK (0x1000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_SHIFT (12U) +/*! ITRIGEN12 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_MASK (0x2000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_SHIFT (13U) +/*! ITRIGEN13 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_MASK (0x4000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_SHIFT (14U) +/*! ITRIGEN14 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_MASK (0x8000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_SHIFT (15U) +/*! ITRIGEN15 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_MASK (0x10000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_SHIFT (16U) +/*! ITRIGEN16 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_MASK (0x20000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_SHIFT (17U) +/*! ITRIGEN17 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_MASK (0x40000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_SHIFT (18U) +/*! ITRIGEN18 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_MASK (0x80000U) +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_SHIFT (19U) +/*! ITRIGEN19 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled. + */ +#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_MASK) +/*! @} */ + +/*! @name DMA0_ITRIGEN0_SET - Set bits in DMA0_ITRIGEN0 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0_MASK (0x1U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0_SHIFT (0U) +/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET0_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1_MASK (0x2U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1_SHIFT (1U) +/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET1_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2_MASK (0x4U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2_SHIFT (2U) +/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET2_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3_MASK (0x8U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3_SHIFT (3U) +/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET3_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4_MASK (0x10U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4_SHIFT (4U) +/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET4_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5_MASK (0x20U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5_SHIFT (5U) +/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET5_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6_MASK (0x40U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6_SHIFT (6U) +/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET6_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7_MASK (0x80U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7_SHIFT (7U) +/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET7_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8_MASK (0x100U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8_SHIFT (8U) +/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET8_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9_MASK (0x200U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9_SHIFT (9U) +/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET9_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10_MASK (0x400U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10_SHIFT (10U) +/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET10_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11_MASK (0x800U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11_SHIFT (11U) +/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET11_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12_MASK (0x1000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12_SHIFT (12U) +/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET12_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13_MASK (0x2000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13_SHIFT (13U) +/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET13_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14_MASK (0x4000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14_SHIFT (14U) +/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET14_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15_MASK (0x8000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15_SHIFT (15U) +/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET15_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16_MASK (0x10000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16_SHIFT (16U) +/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET16_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17_MASK (0x20000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17_SHIFT (17U) +/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET17_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18_MASK (0x40000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18_SHIFT (18U) +/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET18_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19_MASK (0x80000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19_SHIFT (19U) +/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET19_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20_MASK (0x100000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20_SHIFT (20U) +/*! SET20 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET20_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21_MASK (0x200000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21_SHIFT (21U) +/*! SET21 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET21_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22_MASK (0x400000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22_SHIFT (22U) +/*! SET22 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET22_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23_MASK (0x800000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23_SHIFT (23U) +/*! SET23 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET23_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24_MASK (0x1000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24_SHIFT (24U) +/*! SET24 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET24_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25_MASK (0x2000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25_SHIFT (25U) +/*! SET25 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET25_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26_MASK (0x4000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26_SHIFT (26U) +/*! SET26 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET26_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27_MASK (0x8000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27_SHIFT (27U) +/*! SET27 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET27_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28_MASK (0x10000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28_SHIFT (28U) +/*! SET28 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET28_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29_MASK (0x20000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29_SHIFT (29U) +/*! SET29 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET29_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30_MASK (0x40000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30_SHIFT (30U) +/*! SET30 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET30_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31_MASK (0x80000000U) +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31_SHIFT (31U) +/*! SET31 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET31_MASK) +/*! @} */ + +/*! @name DMA0_ITRIGEN1_SET - Set bits in DMA0_ITRIGEN1 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0_MASK (0x1U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0_SHIFT (0U) +/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET0_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1_MASK (0x2U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1_SHIFT (1U) +/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET1_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2_MASK (0x4U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2_SHIFT (2U) +/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET2_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3_MASK (0x8U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3_SHIFT (3U) +/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET3_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4_MASK (0x10U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4_SHIFT (4U) +/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET4_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5_MASK (0x20U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5_SHIFT (5U) +/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET5_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6_MASK (0x40U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6_SHIFT (6U) +/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET6_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7_MASK (0x80U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7_SHIFT (7U) +/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET7_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8_MASK (0x100U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8_SHIFT (8U) +/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET8_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9_MASK (0x200U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9_SHIFT (9U) +/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET9_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10_MASK (0x400U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10_SHIFT (10U) +/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET10_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11_MASK (0x800U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11_SHIFT (11U) +/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET11_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12_MASK (0x1000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12_SHIFT (12U) +/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET12_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13_MASK (0x2000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13_SHIFT (13U) +/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET13_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14_MASK (0x4000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14_SHIFT (14U) +/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET14_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15_MASK (0x8000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15_SHIFT (15U) +/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET15_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16_MASK (0x10000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16_SHIFT (16U) +/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET16_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17_MASK (0x20000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17_SHIFT (17U) +/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET17_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18_MASK (0x40000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18_SHIFT (18U) +/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET18_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19_MASK (0x80000U) +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19_SHIFT (19U) +/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET19_MASK) +/*! @} */ + +/*! @name DMA0_ITRIGEN0_CLR - Clear bits in DMA0_ITRIGEN0 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_MASK (0x1U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_SHIFT (0U) +/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_MASK (0x2U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_SHIFT (1U) +/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_MASK (0x4U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_SHIFT (2U) +/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_MASK (0x8U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_SHIFT (3U) +/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_MASK (0x10U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_SHIFT (4U) +/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_MASK (0x20U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_SHIFT (5U) +/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_MASK (0x40U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_SHIFT (6U) +/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_MASK (0x80U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_SHIFT (7U) +/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_MASK (0x100U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_SHIFT (8U) +/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_MASK (0x200U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_SHIFT (9U) +/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_MASK (0x400U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_SHIFT (10U) +/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_MASK (0x800U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_SHIFT (11U) +/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_MASK (0x1000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_SHIFT (12U) +/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_MASK (0x2000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_SHIFT (13U) +/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_MASK (0x4000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_SHIFT (14U) +/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_MASK (0x8000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_SHIFT (15U) +/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_MASK (0x10000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_SHIFT (16U) +/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_MASK (0x20000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_SHIFT (17U) +/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_MASK (0x40000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_SHIFT (18U) +/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_MASK (0x80000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_SHIFT (19U) +/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_MASK (0x100000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_SHIFT (20U) +/*! CLR20 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_MASK (0x200000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_SHIFT (21U) +/*! CLR21 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_MASK (0x400000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_SHIFT (22U) +/*! CLR22 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_MASK (0x800000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_SHIFT (23U) +/*! CLR23 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_MASK (0x1000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_SHIFT (24U) +/*! CLR24 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_MASK (0x2000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_SHIFT (25U) +/*! CLR25 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_MASK (0x4000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_SHIFT (26U) +/*! CLR26 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_MASK (0x8000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_SHIFT (27U) +/*! CLR27 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_MASK (0x10000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_SHIFT (28U) +/*! CLR28 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_MASK (0x20000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_SHIFT (29U) +/*! CLR29 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_MASK (0x40000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_SHIFT (30U) +/*! CLR30 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_MASK) + +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_MASK (0x80000000U) +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_SHIFT (31U) +/*! CLR31 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN0 register. + */ +#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_MASK) +/*! @} */ + +/*! @name DMA0_ITRIGEN1_CLR - Clear bits in DMA0_ITRIGEN1 register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_MASK (0x1U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_SHIFT (0U) +/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_MASK (0x2U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_SHIFT (1U) +/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_MASK (0x4U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_SHIFT (2U) +/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_MASK (0x8U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_SHIFT (3U) +/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_MASK (0x10U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_SHIFT (4U) +/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_MASK (0x20U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_SHIFT (5U) +/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_MASK (0x40U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_SHIFT (6U) +/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_MASK (0x80U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_SHIFT (7U) +/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_MASK (0x100U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_SHIFT (8U) +/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_MASK (0x200U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_SHIFT (9U) +/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_MASK (0x400U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_SHIFT (10U) +/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_MASK (0x800U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_SHIFT (11U) +/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_MASK (0x1000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_SHIFT (12U) +/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_MASK (0x2000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_SHIFT (13U) +/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_MASK (0x4000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_SHIFT (14U) +/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_MASK (0x8000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_SHIFT (15U) +/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_MASK (0x10000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_SHIFT (16U) +/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_MASK (0x20000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_SHIFT (17U) +/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_MASK (0x40000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_SHIFT (18U) +/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_MASK) + +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_MASK (0x80000U) +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_SHIFT (19U) +/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , + * no change in DMA0_ITRIGEN1 register. + */ +#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_MASK) +/*! @} */ + +/*! @name DMA1_ITRIGEN - Enable DMA1 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_MASK (0x1U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_SHIFT (0U) +/*! ITRIGEN0 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_MASK (0x2U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_SHIFT (1U) +/*! ITRIGEN1 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_MASK (0x4U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_SHIFT (2U) +/*! ITRIGEN2 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_MASK (0x8U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_SHIFT (3U) +/*! ITRIGEN3 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_MASK (0x10U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_SHIFT (4U) +/*! ITRIGEN4 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_MASK (0x20U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_SHIFT (5U) +/*! ITRIGEN5 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_MASK (0x40U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_SHIFT (6U) +/*! ITRIGEN6 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_MASK (0x80U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_SHIFT (7U) +/*! ITRIGEN7 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_MASK (0x100U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_SHIFT (8U) +/*! ITRIGEN8 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_MASK (0x200U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_SHIFT (9U) +/*! ITRIGEN9 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_MASK (0x400U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_SHIFT (10U) +/*! ITRIGEN10 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_MASK (0x800U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_SHIFT (11U) +/*! ITRIGEN11 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_MASK (0x1000U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_SHIFT (12U) +/*! ITRIGEN12 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_MASK (0x2000U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_SHIFT (13U) +/*! ITRIGEN13 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_MASK (0x4000U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_SHIFT (14U) +/*! ITRIGEN14 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_MASK (0x8000U) +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_SHIFT (15U) +/*! ITRIGEN15 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_MASK) +/*! @} */ + +/*! @name DMA1_ITRIGEN_SET - Set bits in DMA1_ITRIGEN register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET0_MASK (0x1U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET0_SHIFT (0U) +/*! SET0 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET0_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET1_MASK (0x2U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET1_SHIFT (1U) +/*! SET1 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET1_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET2_MASK (0x4U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET2_SHIFT (2U) +/*! SET2 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET2_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET3_MASK (0x8U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET3_SHIFT (3U) +/*! SET3 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET3_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET4_MASK (0x10U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET4_SHIFT (4U) +/*! SET4 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET4_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET5_MASK (0x20U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET5_SHIFT (5U) +/*! SET5 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET5_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET6_MASK (0x40U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET6_SHIFT (6U) +/*! SET6 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET6_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET7_MASK (0x80U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET7_SHIFT (7U) +/*! SET7 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET7_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET8_MASK (0x100U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET8_SHIFT (8U) +/*! SET8 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET8_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET9_MASK (0x200U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET9_SHIFT (9U) +/*! SET9 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET9_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET10_MASK (0x400U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET10_SHIFT (10U) +/*! SET10 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET10_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET11_MASK (0x800U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET11_SHIFT (11U) +/*! SET11 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET11_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET12_MASK (0x1000U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET12_SHIFT (12U) +/*! SET12 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET12_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET13_MASK (0x2000U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET13_SHIFT (13U) +/*! SET13 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET13_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET14_MASK (0x4000U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET14_SHIFT (14U) +/*! SET14 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET14_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_SET_SET15_MASK (0x8000U) +#define INPUTMUX_DMA1_ITRIGEN_SET_SET15_SHIFT (15U) +/*! SET15 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_SET_SET15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET15_MASK) +/*! @} */ + +/*! @name DMA1_ITRIGEN_CLR - Clear bits in DMA1_ITRIGEN register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_MASK (0x1U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_SHIFT (0U) +/*! CLR0 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_MASK (0x2U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_SHIFT (1U) +/*! CLR1 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_MASK (0x4U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_SHIFT (2U) +/*! CLR2 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_MASK (0x8U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_SHIFT (3U) +/*! CLR3 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_MASK (0x10U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_SHIFT (4U) +/*! CLR4 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_MASK (0x20U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_SHIFT (5U) +/*! CLR5 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_MASK (0x40U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_SHIFT (6U) +/*! CLR6 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_MASK (0x80U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_SHIFT (7U) +/*! CLR7 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_MASK (0x100U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_SHIFT (8U) +/*! CLR8 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_MASK (0x200U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_SHIFT (9U) +/*! CLR9 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_MASK (0x400U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_SHIFT (10U) +/*! CLR10 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_MASK (0x800U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_SHIFT (11U) +/*! CLR11 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_MASK (0x1000U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_SHIFT (12U) +/*! CLR12 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_MASK (0x2000U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_SHIFT (13U) +/*! CLR13 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_MASK (0x4000U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_SHIFT (14U) +/*! CLR14 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_MASK) + +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_MASK (0x8000U) +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_SHIFT (15U) +/*! CLR15 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register + */ +#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[4][32]; /**< Analog/Digital I/O control for port..Digital I/O control for port, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Analog/Digital I/O control for port..Digital I/O control for port */ +/*! @{ */ + +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Signal(function) select + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Mode select (on-chip pull-up/pull-down resistor control) + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Invert polarity of input signal + * 0b0..Don't invert the signal. + * 0b1..Invert the signal. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + +#define IOCON_PIO_ASW0_MASK (0x400U) +#define IOCON_PIO_ASW0_SHIFT (10U) +/*! ASW0 - Analog switch input control + * 0b0..Analog switch is open. (disable) + * 0b1..Analog switch is closed. (enable) + */ +#define IOCON_PIO_ASW0(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW0_SHIFT)) & IOCON_PIO_ASW0_MASK) + +#define IOCON_PIO_ASW1_MASK (0x800U) +#define IOCON_PIO_ASW1_SHIFT (11U) +/*! ASW1 - Analog switch input control + * 0b0..Analog switch is open. (disable) + * 0b1..Analog switch is closed. (enable) + */ +#define IOCON_PIO_ASW1(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW1_SHIFT)) & IOCON_PIO_ASW1_MASK) + +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter + * 0b0..Filter enabled. + * 0b1..Filter disabled. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in I2C mode + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain cell. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Switch between GPIO mode and I2C mode + * 0b0..I2C mode + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (4U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ITRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer + * @{ + */ + +/** ITRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t STATUS; /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OUT0_SEL0; /**< ITRC_IRQ trigger Source IN0 to IN15 selector 0, offset: 0x8 */ + __IO uint32_t OUT0_SEL1; /**< ITRC_IRQ Trigger source IN0 to IN15 selector 1, offset: 0xC */ + __IO uint32_t OUT1_SEL0; /**< CSS_RESET Trigger source IN0 to IN15 selector 0, offset: 0x10 */ + __IO uint32_t OUT1_SEL1; /**< CSS_RESET Trigger source IN0 to IN15 selector 1, offset: 0x14 */ + __IO uint32_t OUT2_SEL0; /**< PUF_ZEROIZE Trigger source IN0 to IN15 selector 0, offset: 0x18 */ + __IO uint32_t OUT2_SEL1; /**< PUF_ZEROIZE Trigger source IN0 to IN15 selector 1, offset: 0x1C */ + __IO uint32_t OUT3_SEL0; /**< RAM_ZEROIZE Trigger source IN0 to IN15 selector 0, offset: 0x20 */ + __IO uint32_t OUT3_SEL1; /**< RAM_ZEROIZE Trigger source IN0 to IN15 selector 1, offset: 0x24 */ + __IO uint32_t OUT4_SEL0; /**< CHIP_RESET Trigger source IN0 to IN15 selector 0, offset: 0x28 */ + __IO uint32_t OUT4_SEL1; /**< CHIP_RESET Trigger source IN0 to IN15 selector 1, offset: 0x2C */ + __IO uint32_t OUT5_SEL0; /**< TMPR_OUT0 IN0 to IN15 selector 0, offset: 0x30 */ + __IO uint32_t OUT5_SEL1; /**< TMPR_OUT0 IN0 to IN15 selector 1, offset: 0x34 */ + __IO uint32_t OUT6_SEL0; /**< TMPR_OUT1 IN0 to IN15 selector 0, offset: 0x38 */ + __IO uint32_t OUT6_SEL1; /**< TMPR_OUT1 IN0 to IN15 selector 1, offset: 0x3C */ + uint8_t RESERVED_1[176]; + __O uint32_t SW_EVENT0; /**< Software event 0, offset: 0xF0 */ + __O uint32_t SW_EVENT1; /**< Software event 1, offset: 0xF4 */ +} ITRC_Type; + +/* ---------------------------------------------------------------------------- + -- ITRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Register_Masks ITRC Register Masks + * @{ + */ + +/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */ +/*! @{ */ + +#define ITRC_STATUS_IN0_STATUS_MASK (0x1U) +#define ITRC_STATUS_IN0_STATUS_SHIFT (0U) +/*! IN0_STATUS - Digital glitch detector event occurred. + */ +#define ITRC_STATUS_IN0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK) + +#define ITRC_STATUS_IN1_STATUS_MASK (0x2U) +#define ITRC_STATUS_IN1_STATUS_SHIFT (1U) +/*! IN1_STATUS - Tamper pins logic detected an event. + */ +#define ITRC_STATUS_IN1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK) + +#define ITRC_STATUS_IN2_STATUS_MASK (0x4U) +#define ITRC_STATUS_IN2_STATUS_SHIFT (2U) +/*! IN2_STATUS - Code watchdog detected an code execution anomaly. + */ +#define ITRC_STATUS_IN2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK) + +#define ITRC_STATUS_IN3_STATUS_MASK (0x8U) +#define ITRC_STATUS_IN3_STATUS_SHIFT (3U) +/*! IN3_STATUS - Low voltage event (BoD) detected on VDD_MAIN rail. + */ +#define ITRC_STATUS_IN3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK) + +#define ITRC_STATUS_IN4_STATUS_MASK (0x10U) +#define ITRC_STATUS_IN4_STATUS_SHIFT (4U) +/*! IN4_STATUS - Low voltage event (BoD) detected on VDD_CORE rail. + */ +#define ITRC_STATUS_IN4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK) + +#define ITRC_STATUS_IN5_STATUS_MASK (0x20U) +#define ITRC_STATUS_IN5_STATUS_SHIFT (5U) +/*! IN5_STATUS - Watch Dog timer event occurred. + */ +#define ITRC_STATUS_IN5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK) + +#define ITRC_STATUS_IN6_STATUS_MASK (0x40U) +#define ITRC_STATUS_IN6_STATUS_SHIFT (6U) +/*! IN6_STATUS - Flash ECC mismatch event occurred. + */ +#define ITRC_STATUS_IN6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK) + +#define ITRC_STATUS_IN7_STATUS_MASK (0x80U) +#define ITRC_STATUS_IN7_STATUS_SHIFT (7U) +/*! IN7_STATUS - AHB secure bus checkers detected illegal access. + */ +#define ITRC_STATUS_IN7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK) + +#define ITRC_STATUS_IN8_STATUS_MASK (0x100U) +#define ITRC_STATUS_IN8_STATUS_SHIFT (8U) +/*! IN8_STATUS - CSS error event occurred. + */ +#define ITRC_STATUS_IN8_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK) + +#define ITRC_STATUS_IN10_STATUS_MASK (0x400U) +#define ITRC_STATUS_IN10_STATUS_SHIFT (10U) +/*! IN10_STATUS - PKC module detected an error event. + */ +#define ITRC_STATUS_IN10_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK) + +#define ITRC_STATUS_IN14_STATUS_MASK (0x4000U) +#define ITRC_STATUS_IN14_STATUS_SHIFT (14U) +/*! IN14_STATUS - Software event 0 occurred. + */ +#define ITRC_STATUS_IN14_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK) + +#define ITRC_STATUS_IN15_STATUS_MASK (0x8000U) +#define ITRC_STATUS_IN15_STATUS_SHIFT (15U) +/*! IN15_STATUS - Software event 1 occurred. + */ +#define ITRC_STATUS_IN15_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK) + +#define ITRC_STATUS_OUT0_STATUS_MASK (0x10000U) +#define ITRC_STATUS_OUT0_STATUS_SHIFT (16U) +/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. + */ +#define ITRC_STATUS_OUT0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK) + +#define ITRC_STATUS_OUT1_STATUS_MASK (0x20000U) +#define ITRC_STATUS_OUT1_STATUS_SHIFT (17U) +/*! OUT1_STATUS - ITRC triggered CSS_RESET to clear CSS key store. + */ +#define ITRC_STATUS_OUT1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK) + +#define ITRC_STATUS_OUT2_STATUS_MASK (0x40000U) +#define ITRC_STATUS_OUT2_STATUS_SHIFT (18U) +/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM. + */ +#define ITRC_STATUS_OUT2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK) + +#define ITRC_STATUS_OUT3_STATUS_MASK (0x80000U) +#define ITRC_STATUS_OUT3_STATUS_SHIFT (19U) +/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE to clear retention and PKC RAM contents. + */ +#define ITRC_STATUS_OUT3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK) + +#define ITRC_STATUS_OUT4_STATUS_MASK (0x100000U) +#define ITRC_STATUS_OUT4_STATUS_SHIFT (20U) +/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. + */ +#define ITRC_STATUS_OUT4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK) + +#define ITRC_STATUS_OUT5_STATUS_MASK (0x200000U) +#define ITRC_STATUS_OUT5_STATUS_SHIFT (21U) +/*! OUT5_STATUS - ITRC triggered TMPR_OUT internal signal connected to various on-chip multiplexers. + */ +#define ITRC_STATUS_OUT5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK) +/*! @} */ + +/*! @name OUT0_SEL0 - ITRC_IRQ trigger Source IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT0_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT0_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT0_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT0_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT0_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT0_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT0_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT0_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT0_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT0_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT0_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT0_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT0_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT0_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT0_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT0_SEL1 - ITRC_IRQ Trigger source IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT0_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT0_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT0_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT0_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT0_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT0_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT0_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT0_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT0_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT0_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT0_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT0_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT0_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT0_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT0_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name OUT1_SEL0 - CSS_RESET Trigger source IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT1_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT1_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. + */ +#define ITRC_OUT1_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT1_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT1_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT1_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT1_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT1_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT1_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT1_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT1_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT1_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT1_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT1_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT1_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT1_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT1_SEL1 - CSS_RESET Trigger source IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT1_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT1_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT1_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT1_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT1_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT1_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT1_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT1_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT1_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT1_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT1_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT1_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT1_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT1_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT1_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name OUT2_SEL0 - PUF_ZEROIZE Trigger source IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT2_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT2_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. + */ +#define ITRC_OUT2_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT2_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT2_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT2_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT2_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT2_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT2_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT2_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT2_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT2_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT2_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT2_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT2_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT2_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT2_SEL1 - PUF_ZEROIZE Trigger source IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT2_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT2_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT2_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT2_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT2_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT2_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT2_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT2_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT2_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT2_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT2_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT2_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT2_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT2_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT2_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name OUT3_SEL0 - RAM_ZEROIZE Trigger source IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT3_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT3_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. + */ +#define ITRC_OUT3_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT3_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT3_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT3_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT3_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT3_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT3_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT3_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT3_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT3_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT3_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT3_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT3_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT3_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT3_SEL1 - RAM_ZEROIZE Trigger source IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT3_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT3_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT3_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT3_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT3_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT3_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT3_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT3_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT3_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT3_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT3_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT3_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT3_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT3_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT3_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name OUT4_SEL0 - CHIP_RESET Trigger source IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT4_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT4_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. + */ +#define ITRC_OUT4_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT4_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT4_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT4_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT4_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT4_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT4_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT4_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT4_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT4_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT4_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT4_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT4_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT4_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT4_SEL1 - CHIP_RESET Trigger source IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT4_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT4_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT4_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT4_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT4_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT4_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT4_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT4_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT4_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT4_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT4_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT4_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT4_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT4_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT4_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name OUT5_SEL0 - TMPR_OUT0 IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT5_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT5_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. + */ +#define ITRC_OUT5_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT5_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT5_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT5_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT5_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT5_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT5_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT5_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT5_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT5_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT5_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT5_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT5_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT5_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT5_SEL1 - TMPR_OUT0 IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT5_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT5_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT5_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT5_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT5_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT5_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT5_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT5_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT5_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT5_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT5_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT5_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT5_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT5_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT5_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name OUT6_SEL0 - TMPR_OUT1 IN0 to IN15 selector 0 */ +/*! @{ */ + +#define ITRC_OUT6_SEL0_IN0_SEL0_MASK (0x3U) +#define ITRC_OUT6_SEL0_IN0_SEL0_SHIFT (0U) +/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register. + */ +#define ITRC_OUT6_SEL0_IN0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN0_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN1_SEL0_MASK (0xCU) +#define ITRC_OUT6_SEL0_IN1_SEL0_SHIFT (2U) +/*! IN1_SEL0 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN1_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN1_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN2_SEL0_MASK (0x30U) +#define ITRC_OUT6_SEL0_IN2_SEL0_SHIFT (4U) +/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN2_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN2_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN3_SEL0_MASK (0xC0U) +#define ITRC_OUT6_SEL0_IN3_SEL0_SHIFT (6U) +/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN3_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN3_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN4_SEL0_MASK (0x300U) +#define ITRC_OUT6_SEL0_IN4_SEL0_SHIFT (8U) +/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN4_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN4_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN5_SEL0_MASK (0xC00U) +#define ITRC_OUT6_SEL0_IN5_SEL0_SHIFT (10U) +/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN5_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN5_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN6_SEL0_MASK (0x3000U) +#define ITRC_OUT6_SEL0_IN6_SEL0_SHIFT (12U) +/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN6_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN6_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN7_SEL0_MASK (0xC000U) +#define ITRC_OUT6_SEL0_IN7_SEL0_SHIFT (14U) +/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN7_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN7_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN8_SEL0_MASK (0x30000U) +#define ITRC_OUT6_SEL0_IN8_SEL0_SHIFT (16U) +/*! IN8_SEL0 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN8_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN8_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN10_SEL0_MASK (0x300000U) +#define ITRC_OUT6_SEL0_IN10_SEL0_SHIFT (20U) +/*! IN10_SEL0 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN10_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN10_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN14_SEL0_MASK (0x30000000U) +#define ITRC_OUT6_SEL0_IN14_SEL0_SHIFT (28U) +/*! IN14_SEL0 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN14_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN14_SEL0_MASK) + +#define ITRC_OUT6_SEL0_IN15_SEL0_MASK (0xC0000000U) +#define ITRC_OUT6_SEL0_IN15_SEL0_SHIFT (30U) +/*! IN15_SEL0 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT6_SEL0_IN15_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN15_SEL0_MASK) +/*! @} */ + +/*! @name OUT6_SEL1 - TMPR_OUT1 IN0 to IN15 selector 1 */ +/*! @{ */ + +#define ITRC_OUT6_SEL1_IN0_SEL1_MASK (0x3U) +#define ITRC_OUT6_SEL1_IN0_SEL1_SHIFT (0U) +/*! IN0_SEL1 - Selects digital glitch detector as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN0_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN1_SEL1_MASK (0xCU) +#define ITRC_OUT6_SEL1_IN1_SEL1_SHIFT (2U) +/*! IN1_SEL1 - Selects tamper pin event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN1_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN1_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN2_SEL1_MASK (0x30U) +#define ITRC_OUT6_SEL1_IN2_SEL1_SHIFT (4U) +/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN2_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN2_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN3_SEL1_MASK (0xC0U) +#define ITRC_OUT6_SEL1_IN3_SEL1_SHIFT (6U) +/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN3_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN3_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN4_SEL1_MASK (0x300U) +#define ITRC_OUT6_SEL1_IN4_SEL1_SHIFT (8U) +/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN4_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN4_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN5_SEL1_MASK (0xC00U) +#define ITRC_OUT6_SEL1_IN5_SEL1_SHIFT (10U) +/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN5_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN5_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN6_SEL1_MASK (0x3000U) +#define ITRC_OUT6_SEL1_IN6_SEL1_SHIFT (12U) +/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN6_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN6_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN7_SEL1_MASK (0xC000U) +#define ITRC_OUT6_SEL1_IN7_SEL1_SHIFT (14U) +/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN7_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN7_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN8_SEL1_MASK (0x30000U) +#define ITRC_OUT6_SEL1_IN8_SEL1_SHIFT (16U) +/*! IN8_SEL1 - Selects CSS error event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN8_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN8_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN10_SEL1_MASK (0x300000U) +#define ITRC_OUT6_SEL1_IN10_SEL1_SHIFT (20U) +/*! IN10_SEL1 - Selects PKC error event as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN10_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN10_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN14_SEL1_MASK (0x30000000U) +#define ITRC_OUT6_SEL1_IN14_SEL1_SHIFT (28U) +/*! IN14_SEL1 - Selects software event 0 as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN14_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN14_SEL1_MASK) + +#define ITRC_OUT6_SEL1_IN15_SEL1_MASK (0xC0000000U) +#define ITRC_OUT6_SEL1_IN15_SEL1_SHIFT (30U) +/*! IN15_SEL1 - Selects software event 1 as a trigger source. + */ +#define ITRC_OUT6_SEL1_IN15_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN15_SEL1_MASK) +/*! @} */ + +/*! @name SW_EVENT0 - Software event 0 */ +/*! @{ */ + +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT (0U) +/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. + */ +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK) +/*! @} */ + +/*! @name SW_EVENT1 - Software event 1 */ +/*! @{ */ + +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT (0U) +/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. + */ +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ITRC_Register_Masks */ + + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x5000F000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x4000F000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x4000F000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/*! + * @} + */ /* end of group ITRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPDAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer + * @{ + */ + +/** LPDAC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __O uint32_t DATA; /**< Data Register, offset: 0x8 */ + __IO uint32_t GCR; /**< Global Control Register, offset: 0xC */ + __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ + __I uint32_t FPR; /**< DAC FIFO Pointer Register, offset: 0x14 */ + __IO uint32_t FSR; /**< FIFO Status Register, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ + __IO uint32_t DER; /**< DMA Enable Register, offset: 0x20 */ + __IO uint32_t RCR; /**< Reset Control Register, offset: 0x24 */ + __O uint32_t TCR; /**< Trigger Control Register, offset: 0x28 */ + __IO uint32_t PCR; /**< Periodic Trigger Control Register, offset: 0x2C */ +} LPDAC_Type; + +/* ---------------------------------------------------------------------------- + -- LPDAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPDAC_Register_Masks LPDAC Register Masks + * @{ + */ + +/*! @name VERID - Version Identifier Register */ +/*! @{ */ + +#define LPDAC_VERID_FEATURE_MASK (0xFFFFU) +#define LPDAC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + */ +#define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) + +#define LPDAC_VERID_MINOR_MASK (0xFF0000U) +#define LPDAC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor version number + */ +#define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) + +#define LPDAC_VERID_MAJOR_MASK (0xFF000000U) +#define LPDAC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major version number + */ +#define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define LPDAC_PARAM_FIFOSZ_MASK (0x7U) +#define LPDAC_PARAM_FIFOSZ_SHIFT (0U) +/*! FIFOSZ - FIFO size + * 0b000..Reserved + * 0b001..FIFO depth is 4 + * 0b010..FIFO depth is 8 + * 0b011..FIFO depth is 16 + * 0b100..FIFO depth is 32 + * 0b101..FIFO depth is 64 + * 0b110..FIFO depth is 128 + * 0b111..FIFO depth is 256 + */ +#define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) +/*! @} */ + +/*! @name DATA - Data Register */ +/*! @{ */ + +#define LPDAC_DATA_DATA_MASK (0xFFFU) +#define LPDAC_DATA_DATA_SHIFT (0U) +/*! DATA - FIFO entry or Buffer entry + */ +#define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) +/*! @} */ + +/*! @name GCR - Global Control Register */ +/*! @{ */ + +#define LPDAC_GCR_DACEN_MASK (0x1U) +#define LPDAC_GCR_DACEN_SHIFT (0U) +/*! DACEN - DAC Enable + * 0b0..The DAC system is disabled. + * 0b1..The DAC system is enabled. + */ +#define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) + +#define LPDAC_GCR_DACRFS_MASK (0x6U) +#define LPDAC_GCR_DACRFS_SHIFT (1U) +/*! DACRFS - DAC Reference Select + * 0b00..The DAC selects VREFH1 as the reference voltage. + * 0b01..The DAC selects VREFH2 as the reference voltage. + * 0b10..The DAC selects VREFH3 as the reference voltage. + * 0b11..Reserved. + */ +#define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) + +#define LPDAC_GCR_FIFOEN_MASK (0x8U) +#define LPDAC_GCR_FIFOEN_SHIFT (3U) +/*! FIFOEN - FIFO Enable + * 0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion. + * 0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion + */ +#define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) + +#define LPDAC_GCR_SWMD_MASK (0x10U) +#define LPDAC_GCR_SWMD_SHIFT (4U) +/*! SWMD - Swing Back Mode + * 0b0..Swing back mode disable + * 0b1..Swing back mode enable + */ +#define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) + +#define LPDAC_GCR_TRGSEL_MASK (0x20U) +#define LPDAC_GCR_TRGSEL_SHIFT (5U) +/*! TRGSEL - DAC Trigger Select + * 0b0..The DAC hardware trigger is selected. + * 0b1..The DAC software trigger is selected. + */ +#define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) + +#define LPDAC_GCR_PTGEN_MASK (0x40U) +#define LPDAC_GCR_PTGEN_SHIFT (6U) +/*! PTGEN - DAC periodic trigger mode enable + * 0b0..DAC periodic trigger mode is disabled. + * 0b1..DAC periodic trigger mode is enabled. + */ +#define LPDAC_GCR_PTGEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK) + +#define LPDAC_GCR_LATCH_CYC_MASK (0xF00U) +#define LPDAC_GCR_LATCH_CYC_SHIFT (8U) +/*! LATCH_CYC - RCLK cycles before data latch + * 0b0000..Sync time is 1 RCLK cycle, RCLK <= 25MHz + * 0b0001..Sync time is 2 RCLK cycles, 25MHz < RCLK <= 50MHz + * 0b0010..Sync time is 3 RCLK cycles, 50MHz < RCLK <= 75MHz + * 0b0011..Sync time is 4 RCLK cycles, 75MHz < RCLK <= 100MHz + * 0b0100..Sync time is 5 RCLK cycles, 100MHz < RCLK <= 125MHz + * 0b0101..Sync time is 6 RCLK cycles, 125MHz < RCLK <= 150MHz + * 0b0110..Sync time is 7 RCLK cycles, 150MHz < RCLK <= 175MHz + * 0b0111..Sync time is 8 RCLK cycles, 175MHz < RCLK <= 200MHz + * 0b1000..Sync time is 9 RCLK cycles, 200MHz < RCLK <= 225MHz + * 0b1001..Sync time is 10 RCLK cycles, 225MHz < RCLK <= 250MHz + * 0b1010..Sync time is 11 RCLK cycles, 250MHz < RCLK <= 275MHz + * 0b1011..Sync time is 12 RCLK cycles, 275MHz < RCLK <= 300MHz + * 0b1100..Sync time is 13 RCLK cycles, 300MHz < RCLK <= 325MHz + * 0b1101..Sync time is 14 RCLK cycles, 325MHz < RCLK <= 350MHz + * 0b1110..Sync time is 15 RCLK cycles, 350MHz < RCLK <= 375MHz + * 0b1111..Sync time is 16 RCLK cycles, 375MHz < RCLK <= 400MHz + */ +#define LPDAC_GCR_LATCH_CYC(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK) + +#define LPDAC_GCR_BUF_EN_MASK (0x20000U) +#define LPDAC_GCR_BUF_EN_SHIFT (17U) +/*! BUF_EN - Buffer Enable + * 0b0..Opamp is not used as buffer + * 0b1..Opamp is used as buffer + */ +#define LPDAC_GCR_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK) + +#define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK (0x100000U) +#define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT (20U) +/*! IREF_PTAT_EXT_SEL - Internal PTAT Current Reference Select + * 0b0..Internal PTAT Current Reference not selected + * 0b1..Internal PTAT Current Reference selected + */ +#define LPDAC_GCR_IREF_PTAT_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK) + +#define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK (0x200000U) +#define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT (21U) +/*! IREF_ZTC_EXT_SEL - Internal ZTC Current Reference Select + * 0b0..Internal ZTC Current Reference not selected + * 0b1..Internal ZTC Current Reference selected + */ +#define LPDAC_GCR_IREF_ZTC_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK) + +#define LPDAC_GCR_BUF_SPD_CTRL_MASK (0x800000U) +#define LPDAC_GCR_BUF_SPD_CTRL_SHIFT (23U) +/*! BUF_SPD_CTRL - OPAMP as buffer, speed control signal + * 0b0..Lower low power mode + * 0b1..Low power mode + */ +#define LPDAC_GCR_BUF_SPD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK) +/*! @} */ + +/*! @name FCR - DAC FIFO Control Register */ +/*! @{ */ + +#define LPDAC_FCR_WML_MASK (0xFU) +#define LPDAC_FCR_WML_SHIFT (0U) +/*! WML - Watermark Level + */ +#define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) +/*! @} */ + +/*! @name FPR - DAC FIFO Pointer Register */ +/*! @{ */ + +#define LPDAC_FPR_FIFO_RPT_MASK (0xFU) +#define LPDAC_FPR_FIFO_RPT_SHIFT (0U) +/*! FIFO_RPT - FIFO Read Pointer + */ +#define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) + +#define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) +#define LPDAC_FPR_FIFO_WPT_SHIFT (16U) +/*! FIFO_WPT - FIFO Write Pointer + */ +#define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status Register */ +/*! @{ */ + +#define LPDAC_FSR_FULL_MASK (0x1U) +#define LPDAC_FSR_FULL_SHIFT (0U) +/*! FULL - FIFO Full Flag + * 0b0..FIFO is not full + * 0b1..FIFO is full + */ +#define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) + +#define LPDAC_FSR_EMPTY_MASK (0x2U) +#define LPDAC_FSR_EMPTY_SHIFT (1U) +/*! EMPTY - FIFO Empty Flag + * 0b0..FIFO is not empty + * 0b1..FIFO is empty + */ +#define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) + +#define LPDAC_FSR_WM_MASK (0x4U) +#define LPDAC_FSR_WM_SHIFT (2U) +/*! WM - FIFO Watermark Status Flag + * 0b0..Data in FIFO is more than watermark level + * 0b1..Data in FIFO is less than or equal to watermark level + */ +#define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) + +#define LPDAC_FSR_SWBK_MASK (0x8U) +#define LPDAC_FSR_SWBK_SHIFT (3U) +/*! SWBK - Swing Back One Cycle Complete Flag + * 0b0..No swing back cycle has completed since the last time the flag was cleared. + * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared. + */ +#define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) + +#define LPDAC_FSR_OF_MASK (0x40U) +#define LPDAC_FSR_OF_SHIFT (6U) +/*! OF - FIFO Overflow Flag + * 0b0..No overflow has occurred since the last time the flag was cleared. + * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. + */ +#define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) + +#define LPDAC_FSR_UF_MASK (0x80U) +#define LPDAC_FSR_UF_SHIFT (7U) +/*! UF - FIFO Underflow Flag + * 0b0..No underflow has occurred since the last time the flag was cleared. + * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. + */ +#define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) + +#define LPDAC_FSR_PTGCOCO_MASK (0x100U) +#define LPDAC_FSR_PTGCOCO_SHIFT (8U) +/*! PTGCOCO - Period trigger mode conversion complete flag + * 0b0..PTG mode conversion is not completed or not started. + * 0b1..PTG mode conversion is completed. + */ +#define LPDAC_FSR_PTGCOCO(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ + +#define LPDAC_IER_FULL_IE_MASK (0x1U) +#define LPDAC_IER_FULL_IE_SHIFT (0U) +/*! FULL_IE - FIFO Full Interrupt Enable + * 0b0..FIFO Full interrupt is disabled. + * 0b1..FIFO Full interrupt is enabled. + */ +#define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) + +#define LPDAC_IER_EMPTY_IE_MASK (0x2U) +#define LPDAC_IER_EMPTY_IE_SHIFT (1U) +/*! EMPTY_IE - FIFO Empty Interrupt Enable + * 0b0..FIFO Empty interrupt is disabled. + * 0b1..FIFO Empty interrupt is enabled. + */ +#define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) + +#define LPDAC_IER_WM_IE_MASK (0x4U) +#define LPDAC_IER_WM_IE_SHIFT (2U) +/*! WM_IE - FIFO Watermark Interrupt Enable + * 0b0..Watermark interrupt is disabled. + * 0b1..Watermark interrupt is enabled. + */ +#define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) + +#define LPDAC_IER_SWBK_IE_MASK (0x8U) +#define LPDAC_IER_SWBK_IE_SHIFT (3U) +/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable + * 0b0..Swing back one time complete interrupt is disabled. + * 0b1..Swing back one time complete interrupt is enabled. + */ +#define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) + +#define LPDAC_IER_OF_IE_MASK (0x40U) +#define LPDAC_IER_OF_IE_SHIFT (6U) +/*! OF_IE - FIFO Overflow Interrupt Enable + * 0b0..Overflow interrupt is disabled + * 0b1..Overflow interrupt is enabled. + */ +#define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) + +#define LPDAC_IER_UF_IE_MASK (0x80U) +#define LPDAC_IER_UF_IE_SHIFT (7U) +/*! UF_IE - FIFO Underflow Interrupt Enable + * 0b0..Underflow interrupt is disabled. + * 0b1..Underflow interrupt is enabled. + */ +#define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) + +#define LPDAC_IER_PTGCOCO_IE_MASK (0x100U) +#define LPDAC_IER_PTGCOCO_IE_SHIFT (8U) +/*! PTGCOCO_IE - PTG mode conversion complete interrupt enable + * 0b0..PTG mode conversion complete interrupt is disabled. + * 0b1..PTG mode conversion complete interrupt is enabled. + */ +#define LPDAC_IER_PTGCOCO_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable Register */ +/*! @{ */ + +#define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) +#define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) +/*! EMPTY_DMAEN - FIFO Empty DMA Enable + * 0b0..FIFO Empty DMA request is disabled. + * 0b1..FIFO Empty DMA request is enabled. + */ +#define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) + +#define LPDAC_DER_WM_DMAEN_MASK (0x4U) +#define LPDAC_DER_WM_DMAEN_SHIFT (2U) +/*! WM_DMAEN - FIFO Watermark DMA Enable + * 0b0..Watermark DMA request is disabled. + * 0b1..Watermark DMA request is enabled. + */ +#define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) +/*! @} */ + +/*! @name RCR - Reset Control Register */ +/*! @{ */ + +#define LPDAC_RCR_SWRST_MASK (0x1U) +#define LPDAC_RCR_SWRST_SHIFT (0U) +/*! SWRST - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) + +#define LPDAC_RCR_FIFORST_MASK (0x2U) +#define LPDAC_RCR_FIFORST_SHIFT (1U) +/*! FIFORST - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) +/*! @} */ + +/*! @name TCR - Trigger Control Register */ +/*! @{ */ + +#define LPDAC_TCR_SWTRG_MASK (0x1U) +#define LPDAC_TCR_SWTRG_SHIFT (0U) +/*! SWTRG - Software Trigger + * 0b0..The DAC soft trigger is not valid. + * 0b1..The DAC soft trigger is valid. + */ +#define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) +/*! @} */ + +/*! @name PCR - Periodic Trigger Control Register */ +/*! @{ */ + +#define LPDAC_PCR_PTG_NUM_MASK (0xFFFFU) +#define LPDAC_PCR_PTG_NUM_SHIFT (0U) +/*! PTG_NUM - Periodic trigger number + */ +#define LPDAC_PCR_PTG_NUM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK) + +#define LPDAC_PCR_PTG_PERIOD_MASK (0xFFFF0000U) +#define LPDAC_PCR_PTG_PERIOD_SHIFT (16U) +/*! PTG_PERIOD - Periodic trigger period width + */ +#define LPDAC_PCR_PTG_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPDAC_Register_Masks */ + + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x500B2000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x400B2000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x500B6000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x400B6000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x500B9000u) + /** Peripheral DAC2 base address */ + #define DAC2_BASE_NS (0x400B9000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((LPDAC_Type *)DAC2_BASE) + /** Peripheral DAC2 base pointer */ + #define DAC2_NS ((LPDAC_Type *)DAC2_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE, DAC2_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1, DAC2 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS, DAC2_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS, DAC2_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x400B2000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x400B6000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x400B9000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((LPDAC_Type *)DAC2_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE, DAC2_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1, DAC2 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn, DAC2_IRQn } + +/*! + * @} + */ /* end of group LPDAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */ + __I uint32_t ID_CODE; /**< Multi-Rate Timer ID code, offset: 0xFC */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - Time Interval Value */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. + */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register. + * 0b0..No force load. + * 0b1..Force load. T + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - Timer */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. + */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - Control */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMER n interrupt. + * 0b0..Disabled. TIMER n interrupt is disabled. + * 0b1..Enabled. TIMER n interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects the timer mode + * 0b00..Repeat interrupt mode + * 0b01..One-shot interrupt mode + * 0b10..One-shot stall mode + * 0b11..Reserved + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - Status */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMER n. RUN bit is read-only. + * 0b0..Idle state. TIMER n has stopped. + * 0b1..Running. TIMER n is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel-In-Use flag + * 0b0..This timer channel is not in use. + * 0b1..This timer channel is in use. Writing a 1 to this bit clears the status. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded) + */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device) + */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle Channel */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. + */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global Interrupt Flag */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + +/*! @name ID_CODE - Multi-Rate Timer ID code */ +/*! @{ */ + +#define MRT_ID_CODE_ID_CODE_MASK (0xFFFFFFFFU) +#define MRT_ID_CODE_ID_CODE_SHIFT (0U) +/*! ID_CODE - Multi-Rate Timer ID code + */ +#define MRT_ID_CODE_ID_CODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OPAMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer + * @{ + */ + +/** OPAMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t OPAMP_CTR; /**< OPAMP control register, offset: 0x8 */ +} OPAMP_Type; + +/* ---------------------------------------------------------------------------- + -- OPAMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Register_Masks OPAMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define OPAMP_VERID_FEATURE_MASK (0xFFFFU) +#define OPAMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + */ +#define OPAMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK) + +#define OPAMP_VERID_MINOR_MASK (0xFF0000U) +#define OPAMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define OPAMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK) + +#define OPAMP_VERID_MAJOR_MASK (0xFF000000U) +#define OPAMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define OPAMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define OPAMP_PARAM_PGA_FUNCTION_MASK (0x1U) +#define OPAMP_PARAM_PGA_FUNCTION_SHIFT (0U) +/*! PGA_FUNCTION - PGA Function Option + * 0b0..Core amplifier is enabled. + * 0b1..PGA function is enabled. + */ +#define OPAMP_PARAM_PGA_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PGA_FUNCTION_SHIFT)) & OPAMP_PARAM_PGA_FUNCTION_MASK) +/*! @} */ + +/*! @name OPAMP_CTR - OPAMP control register */ +/*! @{ */ + +#define OPAMP_OPAMP_CTR_EN_MASK (0x1U) +#define OPAMP_OPAMP_CTR_EN_SHIFT (0U) +/*! EN - OPAMP Enable + * 0b0..OPAMP is disabled + * 0b1..OPAMP is enabled + */ +#define OPAMP_OPAMP_CTR_EN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_EN_SHIFT)) & OPAMP_OPAMP_CTR_EN_MASK) + +#define OPAMP_OPAMP_CTR_MODE_MASK (0x2U) +#define OPAMP_OPAMP_CTR_MODE_SHIFT (1U) +/*! MODE - Mode Selection + * 0b0..Low noise mode. + * 0b1..High speed mode. + */ +#define OPAMP_OPAMP_CTR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_MODE_SHIFT)) & OPAMP_OPAMP_CTR_MODE_MASK) + +#define OPAMP_OPAMP_CTR_BIASC_MASK (0xCU) +#define OPAMP_OPAMP_CTR_BIASC_SHIFT (2U) +/*! BIASC - Bias Current Trim Selection + * 0b00..Default. + * 0b01..Increase current. + * 0b10..Decrease current. + * 0b11..Further decrease current. + */ +#define OPAMP_OPAMP_CTR_BIASC(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BIASC_SHIFT)) & OPAMP_OPAMP_CTR_BIASC_MASK) + +#define OPAMP_OPAMP_CTR_INTREF_MASK (0x30U) +#define OPAMP_OPAMP_CTR_INTREF_SHIFT (4U) +/*! INTREF - Internal Reference Voltage Selection + * 0b00..Select vdda/2. + * 0b01..Select vdda_3v. + * 0b10..Select vssa_3v. + * 0b11..Not allowed. + */ +#define OPAMP_OPAMP_CTR_INTREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK) + +#define OPAMP_OPAMP_CTR_ADCSW_MASK (0x10000U) +#define OPAMP_OPAMP_CTR_ADCSW_SHIFT (16U) +/*! ADCSW - ADC Channel Switch + */ +#define OPAMP_OPAMP_CTR_ADCSW(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW_MASK) + +#define OPAMP_OPAMP_CTR_PREF_MASK (0x60000U) +#define OPAMP_OPAMP_CTR_PREF_SHIFT (17U) +/*! PREF - Positive Reference Voltage Selection + * 0b00..Select vrefh3. + * 0b01..Select vrefh0. + * 0b10..Select vrefh1. + * 0b11..Reserved. + */ +#define OPAMP_OPAMP_CTR_PREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK) + +#define OPAMP_OPAMP_CTR_PGAIN_MASK (0x700000U) +#define OPAMP_OPAMP_CTR_PGAIN_SHIFT (20U) +/*! PGAIN - Positive PGA Selection. + * 0b000..Reserved. + * 0b001..Inverting gain application 2X. + * 0b010..Inverting gain application 3X. + * 0b011..Inverting gain application 5X. + * 0b100..Inverting gain application 9X. + * 0b101..Inverting gain application 17X. + * 0b110..Inverting gain application 34X. + * 0b111..Inverting gain application 65X. + */ +#define OPAMP_OPAMP_CTR_PGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK) + +#define OPAMP_OPAMP_CTR_NGAIN_MASK (0x7000000U) +#define OPAMP_OPAMP_CTR_NGAIN_SHIFT (24U) +/*! NGAIN - Negative PGA selection + * 0b000..Buffer. + * 0b001..Inverting gain application -1X. + * 0b010..Inverting gain application -2X. + * 0b011..Inverting gain application -4X. + * 0b100..Inverting gain application -8X. + * 0b101..Inverting gain application -16X. + * 0b110..Inverting gain application -33X. + * 0b111..Inverting gain application -64X. + */ +#define OPAMP_OPAMP_CTR_NGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OPAMP_Register_Masks */ + + +/* OPAMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x500B4000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x400B4000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x500B8000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x400B8000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x500BB000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x400BB000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x400B4000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x400B8000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x400BB000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/*! + * @} + */ /* end of group OPAMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low Register for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High Register for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low Register for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High Register for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS Event Timer Control Register for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count value + */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count value + */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low Register for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture value + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High Register for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture value + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low Register for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match value + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High Register for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match value + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS Event Timer Control Register for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt/Wake-up Request + * 0b0..Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked. + * 0b1..An interrupt/wake-up request to the domain processor will be asserted when the OSTIMER_INTR flag is set. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x5002D000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x4002D000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */ + __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */ + __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */ + __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern Match Interrupt Control, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Interrupt mode + * 0b00000000..Edge-sensitive + * 0b00000001..Level-sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enable Interrupt + * 0b00000000..Disable rising edge or level interrupt + * 0b00000001..Enable rising edge or level interrupt + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Set bits in the IENR + * 0b00000000..No operation + * 0b00000001..Enable rising edge or level interrupt + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Clear bits in the IENR + * 0b00000000..No operation + * 0b00000001..Disable rising edge or level interrupt + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enable Interrupt + * 0b00000000..Disable falling edge interrupt or set active interrupt level LOW + * 0b00000001..Enable falling edge interrupt enabled or set active interrupt level HIGH + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Set bits in the IENF + * 0b00000000..No operation + * 0b00000001..Select HIGH-active interrupt or enable falling edge interrupt + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Clear bits in the IENF + * 0b00000000..No operation + * 0b00000001..LOW-active interrupt selected or falling edge interrupt disabled + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name RISE - Pin Interrupt Rising Edge */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect + * 0b00000000..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation + * 0b00000001..Read 1- a rising edge has been detected since Reset or the last time a one was written to this + * bit, Write 1- clear rising edge detection for this pin + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name FALL - Pin Interrupt Falling Edge */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect + * 0b00000000..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation + * 0b00000001..Read 1- a falling edge has been detected since Reset or the last time a one was written to this + * bit, Write 1- clear falling edge detection for this bit + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name IST - Pin Interrupt Status */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status + * 0b00000000..Read 0- interrupt is not being requested for this pin, Write 0- no operation. + * 0b00000001..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and + * falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin + * (in the IENF register). + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) /* Merged from fields with different position or width, of widths (2, 8), largest definition used */ +/*! @} */ + +/*! @name PMCTRL - Pattern Match Interrupt Control */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match- interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true. + * 0b0..Disabled- RXEV output to the CPU is disabled. + * 0b1..Enabled- RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - Pattern Matches + * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs. + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n. + * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n. + * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n. + * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n. + * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n. + * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n. + * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n. + * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This match condition is only cleared when the + * PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This match condition + * is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge + * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is + * cleared after 1 clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PKC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer + * @{ + */ + +/** PKC - Register Layout Typedef */ +typedef struct { + __I uint32_t PKC_STATUS; /**< Status register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control register, offset: 0x4 */ + __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ + __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ + __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ + __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ + __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ + __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ + __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ + __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ + __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ + __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ + uint8_t RESERVED_4[3916]; + __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ + uint8_t RESERVED_5[12]; + __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ + __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ + uint8_t RESERVED_6[16]; + __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ + __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ + __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ + __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ + __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ + __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ + uint8_t RESERVED_7[12]; + __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ +} PKC_Type; + +/* ---------------------------------------------------------------------------- + -- PKC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Register_Masks PKC Register Masks + * @{ + */ + +/*! @name PKC_STATUS - Status register */ +/*! @{ */ + +#define PKC_PKC_STATUS_activ_MASK (0x1U) +#define PKC_PKC_STATUS_activ_SHIFT (0U) +/*! activ - PKC active: ACTIV=1 signals that a calculation is in progress or about to start. At the + * end of a calculation ACTIV is automatically reset to logic 0 in case no further GO bit is set. + * If the next PKC operation has been started by setting a GO bit during a calculation, ACTIV + * remains high. ACTIV is always '1' in case PKC_STATUS.GOANY is set. ACTIV is always '0' in case + * PKC_CTRL_RESET is set. + */ +#define PKC_PKC_STATUS_activ(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_activ_SHIFT)) & PKC_PKC_STATUS_activ_MASK) + +#define PKC_PKC_STATUS_carry_MASK (0x2U) +#define PKC_PKC_STATUS_carry_SHIFT (1U) +/*! carry - Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case + */ +#define PKC_PKC_STATUS_carry(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_carry_SHIFT)) & PKC_PKC_STATUS_carry_MASK) + +#define PKC_PKC_STATUS_zero_MASK (0x4U) +#define PKC_PKC_STATUS_zero_SHIFT (2U) +/*! zero - Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result + * of the calculation is equal zero. ZERO is updated for each PKC calculation mode, except for + * MUL1 (opcode 0x20) and MUL1_GF2 (opcode 0x24). + */ +#define PKC_PKC_STATUS_zero(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_zero_SHIFT)) & PKC_PKC_STATUS_zero_MASK) + +#define PKC_PKC_STATUS_goany_MASK (0x8U) +#define PKC_PKC_STATUS_goany_SHIFT (3U) +/*! goany - Combined GO status flag: GOANY is set in case either PKC_CTRL.GOD1, GOD2, GOM1, GOM2 or + * GOU is set. The 1-to-0 transition of GOANY indicates that a calculation has been started and + * that a new GO bit can be set. If GOANY is cleared also all PKC_STATUS.LOCKED bits are cleared + * to indicate that the parameter set can be updated. GOANY is always '0' in case PKC_CTRL.RESET + * is set. + */ +#define PKC_PKC_STATUS_goany(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_goany_SHIFT)) & PKC_PKC_STATUS_goany_MASK) + +#define PKC_PKC_STATUS_reserved4_MASK (0x10U) +#define PKC_PKC_STATUS_reserved4_SHIFT (4U) +/*! reserved4 - reserved + */ +#define PKC_PKC_STATUS_reserved4(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_reserved4_SHIFT)) & PKC_PKC_STATUS_reserved4_MASK) + +#define PKC_PKC_STATUS_locked_MASK (0x60U) +#define PKC_PKC_STATUS_locked_SHIFT (5U) +/*! locked - Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten. + */ +#define PKC_PKC_STATUS_locked(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_locked_SHIFT)) & PKC_PKC_STATUS_locked_MASK) + +#define PKC_PKC_STATUS_reserved31_MASK (0xFFFFFF80U) +#define PKC_PKC_STATUS_reserved31_SHIFT (7U) +/*! reserved31 - reserved + */ +#define PKC_PKC_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_reserved31_SHIFT)) & PKC_PKC_STATUS_reserved31_MASK) +/*! @} */ + +/*! @name PKC_CTRL - Control register */ +/*! @{ */ + +#define PKC_PKC_CTRL_reset_MASK (0x1U) +#define PKC_PKC_CTRL_reset_SHIFT (0U) +/*! reset - PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation + * cannot be started and by which any ongoing calculation process is stopped. RESET can be + * set/cleared by the CPU in order to switch between PKC reset and calculation enable. RESET=1 is the + * default state after a chip reset. + */ +#define PKC_PKC_CTRL_reset(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_reset_SHIFT)) & PKC_PKC_CTRL_reset_MASK) + +#define PKC_PKC_CTRL_stop_MASK (0x2U) +#define PKC_PKC_CTRL_stop_SHIFT (1U) +/*! stop - Freeze PKC calculation: STOP=1 freezes all PKC activity incl. RAM accesses and reduces + * the PKC power consumption to its minimum. The difference compared to the reset of the PKC is + * that a stopped calculation can be continued when STOP is released (reset to '0') again. The + * status flags are not affected by the STOP control bit. + */ +#define PKC_PKC_CTRL_stop(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_stop_SHIFT)) & PKC_PKC_CTRL_stop_MASK) + +#define PKC_PKC_CTRL_god1_MASK (0x4U) +#define PKC_PKC_CTRL_god1_SHIFT (2U) +/*! god1 - Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will + * start a direct / layer0 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, + * PKC_LEN1). + */ +#define PKC_PKC_CTRL_god1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_god1_SHIFT)) & PKC_PKC_CTRL_god1_MASK) + +#define PKC_PKC_CTRL_god2_MASK (0x8U) +#define PKC_PKC_CTRL_god2_SHIFT (3U) +/*! god2 - Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will + * start a direct / layer0 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, + * PKC_LEN2). + */ +#define PKC_PKC_CTRL_god2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_god2_SHIFT)) & PKC_PKC_CTRL_god2_MASK) + +#define PKC_PKC_CTRL_gom1_MASK (0x10U) +#define PKC_PKC_CTRL_gom1_SHIFT (4U) +/*! gom1 - Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC + * pattern / layer1 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, + * PKC_LEN1). + */ +#define PKC_PKC_CTRL_gom1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gom1_SHIFT)) & PKC_PKC_CTRL_gom1_MASK) + +#define PKC_PKC_CTRL_gom2_MASK (0x20U) +#define PKC_PKC_CTRL_gom2_SHIFT (5U) +/*! gom2 - Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC + * pattern / layer1 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, + * PKC_LEN2). + */ +#define PKC_PKC_CTRL_gom2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gom2_SHIFT)) & PKC_PKC_CTRL_gom2_MASK) + +#define PKC_PKC_CTRL_gou_MASK (0x40U) +#define PKC_PKC_CTRL_gou_SHIFT (6U) +/*! gou - Control bit to start pipe operation: If GOU is set PKC will start the pipe / layer2 + * operation (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch + * Operation'. + */ +#define PKC_PKC_CTRL_gou(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gou_SHIFT)) & PKC_PKC_CTRL_gou_MASK) + +#define PKC_PKC_CTRL_gf2conv_MASK (0x80U) +#define PKC_PKC_CTRL_gf2conv_SHIFT (7U) +/*! gf2conv - Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes. + */ +#define PKC_PKC_CTRL_gf2conv(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gf2conv_SHIFT)) & PKC_PKC_CTRL_gf2conv_MASK) + +#define PKC_PKC_CTRL_clrcache_MASK (0x100U) +#define PKC_PKC_CTRL_clrcache_SHIFT (8U) +/*! clrcache - Clear universal pointer cache: Invalidates the cache such that all previously fetched + * parameters are withdrawn and have to be fetched again via DMA accesses. + */ +#define PKC_PKC_CTRL_clrcache(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_clrcache_SHIFT)) & PKC_PKC_CTRL_clrcache_MASK) + +#define PKC_PKC_CTRL_cache_en_MASK (0x200U) +#define PKC_PKC_CTRL_cache_en_SHIFT (9U) +/*! cache_en - Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer + * parameters is enabled. In case a parameter value is found in the cache (from a previous fetch) no + * DMA access is triggered. As such the amount of DMA accesses for the parameter fetch vary + * between 0 and 4. To further optimize the cache utilization not used parameters, e.g. XPTR for a + * plain addition (opcode 0x0A), could be defined equal to a used one (e.g. equal YPTR or RPTR) or + * a previously fetched parameter. + */ +#define PKC_PKC_CTRL_cache_en(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_cache_en_SHIFT)) & PKC_PKC_CTRL_cache_en_MASK) + +#define PKC_PKC_CTRL_redmul_MASK (0xC00U) +#define PKC_PKC_CTRL_redmul_SHIFT (10U) +/*! redmul - Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor. + * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b01..RFU Error Generated if selected + * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b11..RFU Error Generated if selected + */ +#define PKC_PKC_CTRL_redmul(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_redmul_SHIFT)) & PKC_PKC_CTRL_redmul_MASK) + +#define PKC_PKC_CTRL_reserved31_MASK (0xFFFFF000U) +#define PKC_PKC_CTRL_reserved31_SHIFT (12U) +/*! reserved31 - reserved + */ +#define PKC_PKC_CTRL_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_reserved31_SHIFT)) & PKC_PKC_CTRL_reserved31_MASK) +/*! @} */ + +/*! @name PKC_CFG - Configuration register */ +/*! @{ */ + +#define PKC_PKC_CFG_idleop_MASK (0x1U) +#define PKC_PKC_CFG_idleop_SHIFT (0U) +/*! idleop - Idle operation feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_idleop(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_idleop_SHIFT)) & PKC_PKC_CFG_idleop_MASK) + +#define PKC_PKC_CFG_rfu1_MASK (0x2U) +#define PKC_PKC_CFG_rfu1_SHIFT (1U) +/*! rfu1 - RFU + */ +#define PKC_PKC_CFG_rfu1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rfu1_SHIFT)) & PKC_PKC_CFG_rfu1_MASK) + +#define PKC_PKC_CFG_rfu2_MASK (0x4U) +#define PKC_PKC_CFG_rfu2_SHIFT (2U) +/*! rfu2 - RFU + */ +#define PKC_PKC_CFG_rfu2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rfu2_SHIFT)) & PKC_PKC_CFG_rfu2_MASK) + +#define PKC_PKC_CFG_clkrnd_MASK (0x8U) +#define PKC_PKC_CFG_clkrnd_SHIFT (3U) +/*! clkrnd - Clock randomization feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_clkrnd(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_clkrnd_SHIFT)) & PKC_PKC_CFG_clkrnd_MASK) + +#define PKC_PKC_CFG_redmulnoise_MASK (0x10U) +#define PKC_PKC_CFG_redmulnoise_SHIFT (4U) +/*! redmulnoise - Noise in reduced multiplier mode feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_redmulnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_redmulnoise_SHIFT)) & PKC_PKC_CFG_redmulnoise_MASK) + +#define PKC_PKC_CFG_rnddly_MASK (0xE0U) +#define PKC_PKC_CFG_rnddly_SHIFT (5U) +/*! rnddly - Random delay feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_rnddly(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rnddly_SHIFT)) & PKC_PKC_CFG_rnddly_MASK) + +#define PKC_PKC_CFG_sbxnoise_MASK (0x100U) +#define PKC_PKC_CFG_sbxnoise_SHIFT (8U) +/*! sbxnoise - Noise feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_sbxnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_sbxnoise_SHIFT)) & PKC_PKC_CFG_sbxnoise_MASK) + +#define PKC_PKC_CFG_alpnoise_MASK (0x200U) +#define PKC_PKC_CFG_alpnoise_SHIFT (9U) +/*! alpnoise - Noise feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_alpnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_alpnoise_SHIFT)) & PKC_PKC_CFG_alpnoise_MASK) + +#define PKC_PKC_CFG_fmulnoise_MASK (0x400U) +#define PKC_PKC_CFG_fmulnoise_SHIFT (10U) +/*! fmulnoise - Noise feature not available in this version (flag is don't care). + */ +#define PKC_PKC_CFG_fmulnoise(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_fmulnoise_SHIFT)) & PKC_PKC_CFG_fmulnoise_MASK) + +#define PKC_PKC_CFG_reserved31_MASK (0xFFFFF800U) +#define PKC_PKC_CFG_reserved31_SHIFT (11U) +/*! reserved31 - reserved + */ +#define PKC_PKC_CFG_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_reserved31_SHIFT)) & PKC_PKC_CFG_reserved31_MASK) +/*! @} */ + +/*! @name PKC_MODE1 - Mode register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_MODE1_mode_MASK (0xFFU) +#define PKC_PKC_MODE1_mode_SHIFT (0U) +/*! mode - Calculation Mode / MC Start address: + */ +#define PKC_PKC_MODE1_mode(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_mode_SHIFT)) & PKC_PKC_MODE1_mode_MASK) + +#define PKC_PKC_MODE1_reserved31_MASK (0xFFFFFF00U) +#define PKC_PKC_MODE1_reserved31_SHIFT (8U) +/*! reserved31 - reserved + */ +#define PKC_PKC_MODE1_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_reserved31_SHIFT)) & PKC_PKC_MODE1_reserved31_MASK) +/*! @} */ + +/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_XYPTR1_xptr_MASK (0xFFFFU) +#define PKC_PKC_XYPTR1_xptr_SHIFT (0U) +/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are + * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on + * available PKCRAM size. + */ +#define PKC_PKC_XYPTR1_xptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_xptr_SHIFT)) & PKC_PKC_XYPTR1_xptr_MASK) + +#define PKC_PKC_XYPTR1_yptr_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR1_yptr_SHIFT (16U) +/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are + * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on + * available PKCRAM size. + */ +#define PKC_PKC_XYPTR1_yptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_yptr_SHIFT)) & PKC_PKC_XYPTR1_yptr_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR1_zptr_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR1_zptr_SHIFT (0U) +/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: + */ +#define PKC_PKC_ZRPTR1_zptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_zptr_SHIFT)) & PKC_PKC_ZRPTR1_zptr_MASK) + +#define PKC_PKC_ZRPTR1_rptr_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR1_rptr_SHIFT (16U) +/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are + * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on + * available PKCRAM size. + */ +#define PKC_PKC_ZRPTR1_rptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_rptr_SHIFT)) & PKC_PKC_ZRPTR1_rptr_MASK) +/*! @} */ + +/*! @name PKC_LEN1 - Length register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_LEN1_len_MASK (0xFFFFU) +#define PKC_PKC_LEN1_len_SHIFT (0U) +/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length + * of Y, Z and R depend furthermore on the selected calculation mode. + */ +#define PKC_PKC_LEN1_len(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_len_SHIFT)) & PKC_PKC_LEN1_len_MASK) + +#define PKC_PKC_LEN1_mclen_MASK (0xFFFF0000U) +#define PKC_PKC_LEN1_mclen_SHIFT (16U) +/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that + * can be used in layer1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC + * patterns Modular Multiplication (MC start address 0x00), Plain Multiplication (0x13), Plain + * Multiplication with Addition (0x1D) and Modular Reduction (0x33) MCLEN defines the length of the X + * operand in bytes. + */ +#define PKC_PKC_LEN1_mclen(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_mclen_SHIFT)) & PKC_PKC_LEN1_mclen_MASK) +/*! @} */ + +/*! @name PKC_MODE2 - Mode register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_MODE2_mode_MASK (0xFFU) +#define PKC_PKC_MODE2_mode_SHIFT (0U) +/*! mode - Calculation Mode / MC Start address: + */ +#define PKC_PKC_MODE2_mode(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_mode_SHIFT)) & PKC_PKC_MODE2_mode_MASK) + +#define PKC_PKC_MODE2_reserved31_MASK (0xFFFFFF00U) +#define PKC_PKC_MODE2_reserved31_SHIFT (8U) +/*! reserved31 - reserved + */ +#define PKC_PKC_MODE2_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_reserved31_SHIFT)) & PKC_PKC_MODE2_reserved31_MASK) +/*! @} */ + +/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_XYPTR2_xptr_MASK (0xFFFFU) +#define PKC_PKC_XYPTR2_xptr_SHIFT (0U) +/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are + * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on + * available PKCRAM size. + */ +#define PKC_PKC_XYPTR2_xptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_xptr_SHIFT)) & PKC_PKC_XYPTR2_xptr_MASK) + +#define PKC_PKC_XYPTR2_yptr_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR2_yptr_SHIFT (16U) +/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are + * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on + * available PKCRAM size. + */ +#define PKC_PKC_XYPTR2_yptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_yptr_SHIFT)) & PKC_PKC_XYPTR2_yptr_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR2_zptr_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_zptr_SHIFT (0U) +/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: + */ +#define PKC_PKC_ZRPTR2_zptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_zptr_SHIFT)) & PKC_PKC_ZRPTR2_zptr_MASK) + +#define PKC_PKC_ZRPTR2_rptr_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR2_rptr_SHIFT (16U) +/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are + * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on + * available PKCRAM size. + */ +#define PKC_PKC_ZRPTR2_rptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_rptr_SHIFT)) & PKC_PKC_ZRPTR2_rptr_MASK) +/*! @} */ + +/*! @name PKC_LEN2 - Length register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_LEN2_len_MASK (0xFFFFU) +#define PKC_PKC_LEN2_len_SHIFT (0U) +/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length + * of Y, Z and R depend furthermore on the selected calculation mode. + */ +#define PKC_PKC_LEN2_len(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_len_SHIFT)) & PKC_PKC_LEN2_len_MASK) + +#define PKC_PKC_LEN2_mclen_MASK (0xFFFF0000U) +#define PKC_PKC_LEN2_mclen_SHIFT (16U) +/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that + * can be used in layer1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC + * patterns Modular Multiplication (MC start address 0x00) + */ +#define PKC_PKC_LEN2_mclen(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_mclen_SHIFT)) & PKC_PKC_LEN2_mclen_MASK) +/*! @} */ + +/*! @name PKC_UPTR - Universal pointer FUP program */ +/*! @{ */ + +#define PKC_PKC_UPTR_ptr_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTR_ptr_SHIFT (0U) +/*! ptr - Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting + * a universal pointer PKC calculation (layer2) via PKC_CTRL.GOU. The pointer address needs to be + * valid and the memory space the pointer addresses needs to be enabled for PKC access by the + * system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). + */ +#define PKC_PKC_UPTR_ptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_ptr_SHIFT)) & PKC_PKC_UPTR_ptr_MASK) +/*! @} */ + +/*! @name PKC_UPTRT - Universal pointer FUP table */ +/*! @{ */ + +#define PKC_PKC_UPTRT_ptr_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTRT_ptr_SHIFT (0U) +/*! ptr - Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a + * universal pointer PKC calculation (layer2) via PKC_CTRL.GOU. The pointer address needs to be + * valid and the memory space the pointer addresses needs to be enabled for PKC access by the + * system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). + */ +#define PKC_PKC_UPTRT_ptr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_ptr_SHIFT)) & PKC_PKC_UPTRT_ptr_MASK) +/*! @} */ + +/*! @name PKC_ULEN - Universal pointer length */ +/*! @{ */ + +#define PKC_PKC_ULEN_len_MASK (0xFFU) +#define PKC_PKC_ULEN_len_SHIFT (0U) +/*! len - Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries + * shall be processed for one layer2 calculation started via PKC_CTRL.GOU. The FUP program entries + * include layer0 calculations, layer1 calculations and CRC entries for FUP program integrity + * protection. + */ +#define PKC_PKC_ULEN_len(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_len_SHIFT)) & PKC_PKC_ULEN_len_MASK) + +#define PKC_PKC_ULEN_reserved31_MASK (0xFFFFFF00U) +#define PKC_PKC_ULEN_reserved31_SHIFT (8U) +/*! reserved31 - reserved + */ +#define PKC_PKC_ULEN_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_reserved31_SHIFT)) & PKC_PKC_ULEN_reserved31_MASK) +/*! @} */ + +/*! @name PKC_MCDATA - MC pattern data interface */ +/*! @{ */ + +#define PKC_PKC_MCDATA_mcdata_MASK (0xFFFFFFFFU) +#define PKC_PKC_MCDATA_mcdata_SHIFT (0U) +/*! mcdata - Microcode read/write data: This IP version does not support flexible MC patterns (only + * hard coded ones). Any read or write access to PKC_MCDATA triggers a security alarm + * (PKC_ACCESS_ERR.CTRL is set). + */ +#define PKC_PKC_MCDATA_mcdata(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_mcdata_SHIFT)) & PKC_PKC_MCDATA_mcdata_MASK) +/*! @} */ + +/*! @name PKC_VERSION - PKC version register */ +/*! @{ */ + +#define PKC_PKC_VERSION_mulsize_MASK (0x3U) +#define PKC_PKC_VERSION_mulsize_SHIFT (0U) +/*! mulsize - native multiplier size and operand granularity + * 0b01..32-bit multiplier + * 0b10..64-bit multiplier + * 0b11..128-bit multiplier + */ +#define PKC_PKC_VERSION_mulsize(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mulsize_SHIFT)) & PKC_PKC_VERSION_mulsize_MASK) + +#define PKC_PKC_VERSION_mcavail_MASK (0x4U) +#define PKC_PKC_VERSION_mcavail_SHIFT (2U) +/*! mcavail - MC feature (layer1 calculation) is available + */ +#define PKC_PKC_VERSION_mcavail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mcavail_SHIFT)) & PKC_PKC_VERSION_mcavail_MASK) + +#define PKC_PKC_VERSION_upavail_MASK (0x8U) +#define PKC_PKC_VERSION_upavail_SHIFT (3U) +/*! upavail - UP feature (layer2 calculation) is available + */ +#define PKC_PKC_VERSION_upavail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_upavail_SHIFT)) & PKC_PKC_VERSION_upavail_MASK) + +#define PKC_PKC_VERSION_upcacheavail_MASK (0x10U) +#define PKC_PKC_VERSION_upcacheavail_SHIFT (4U) +/*! upcacheavail - UP cache is available + */ +#define PKC_PKC_VERSION_upcacheavail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_upcacheavail_SHIFT)) & PKC_PKC_VERSION_upcacheavail_MASK) + +#define PKC_PKC_VERSION_gf2avail_MASK (0x20U) +#define PKC_PKC_VERSION_gf2avail_SHIFT (5U) +/*! gf2avail - GF2 calculation modes are available + */ +#define PKC_PKC_VERSION_gf2avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_gf2avail_SHIFT)) & PKC_PKC_VERSION_gf2avail_MASK) + +#define PKC_PKC_VERSION_paramnum_MASK (0xC0U) +#define PKC_PKC_VERSION_paramnum_SHIFT (6U) +/*! paramnum - Number of parameter sets for real calculation + */ +#define PKC_PKC_VERSION_paramnum(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_paramnum_SHIFT)) & PKC_PKC_VERSION_paramnum_MASK) + +#define PKC_PKC_VERSION_sbx0avail_MASK (0x100U) +#define PKC_PKC_VERSION_sbx0avail_SHIFT (8U) +/*! sbx0avail - SBX0 operation is available + */ +#define PKC_PKC_VERSION_sbx0avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx0avail_SHIFT)) & PKC_PKC_VERSION_sbx0avail_MASK) + +#define PKC_PKC_VERSION_sbx1avail_MASK (0x200U) +#define PKC_PKC_VERSION_sbx1avail_SHIFT (9U) +/*! sbx1avail - SBX1 operation is available + */ +#define PKC_PKC_VERSION_sbx1avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx1avail_SHIFT)) & PKC_PKC_VERSION_sbx1avail_MASK) + +#define PKC_PKC_VERSION_sbx2avail_MASK (0x400U) +#define PKC_PKC_VERSION_sbx2avail_SHIFT (10U) +/*! sbx2avail - SBX2 operation is available + */ +#define PKC_PKC_VERSION_sbx2avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx2avail_SHIFT)) & PKC_PKC_VERSION_sbx2avail_MASK) + +#define PKC_PKC_VERSION_sbx3avail_MASK (0x800U) +#define PKC_PKC_VERSION_sbx3avail_SHIFT (11U) +/*! sbx3avail - SBX3 operation is available + */ +#define PKC_PKC_VERSION_sbx3avail(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx3avail_SHIFT)) & PKC_PKC_VERSION_sbx3avail_MASK) + +#define PKC_PKC_VERSION_mcreconf_size_MASK (0xFF000U) +#define PKC_PKC_VERSION_mcreconf_size_SHIFT (12U) +/*! mcreconf_size - Size of reconfigurable MC table in bytes + */ +#define PKC_PKC_VERSION_mcreconf_size(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mcreconf_size_SHIFT)) & PKC_PKC_VERSION_mcreconf_size_MASK) + +#define PKC_PKC_VERSION_reserved31_MASK (0xFFF00000U) +#define PKC_PKC_VERSION_reserved31_SHIFT (20U) +/*! reserved31 - reserved + */ +#define PKC_PKC_VERSION_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_reserved31_SHIFT)) & PKC_PKC_VERSION_reserved31_MASK) +/*! @} */ + +/*! @name PKC_SOFT_RST - Software reset */ +/*! @{ */ + +#define PKC_PKC_SOFT_RST_soft_rst_MASK (0x1U) +#define PKC_PKC_SOFT_RST_soft_rst_SHIFT (0U) +/*! soft_rst - Write 1 to reset module (0 has no effect). All running and pending PKC calculation + * are stopped. All PKC SFRs are reset except PKC_ACCESS_ERR. + */ +#define PKC_PKC_SOFT_RST_soft_rst(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_soft_rst_SHIFT)) & PKC_PKC_SOFT_RST_soft_rst_MASK) + +#define PKC_PKC_SOFT_RST_reserved31_MASK (0xFFFFFFFEU) +#define PKC_PKC_SOFT_RST_reserved31_SHIFT (1U) +/*! reserved31 - reserved + */ +#define PKC_PKC_SOFT_RST_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_reserved31_SHIFT)) & PKC_PKC_SOFT_RST_reserved31_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR - Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_apb_notav_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_apb_notav_SHIFT (0U) +/*! apb_notav - APB Error: address not available + */ +#define PKC_PKC_ACCESS_ERR_apb_notav(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_notav_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_notav_MASK) + +#define PKC_PKC_ACCESS_ERR_apb_wrgmd_MASK (0x2U) +#define PKC_PKC_ACCESS_ERR_apb_wrgmd_SHIFT (1U) +/*! apb_wrgmd - APB Error: Wrong access mode + */ +#define PKC_PKC_ACCESS_ERR_apb_wrgmd(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_wrgmd_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_wrgmd_MASK) + +#define PKC_PKC_ACCESS_ERR_reserved3_MASK (0xCU) +#define PKC_PKC_ACCESS_ERR_reserved3_SHIFT (2U) +/*! reserved3 - reserved for future erors on APB I/F + */ +#define PKC_PKC_ACCESS_ERR_reserved3(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved3_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved3_MASK) + +#define PKC_PKC_ACCESS_ERR_apb_master_MASK (0xF0U) +#define PKC_PKC_ACCESS_ERR_apb_master_SHIFT (4U) +/*! apb_master - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV) + */ +#define PKC_PKC_ACCESS_ERR_apb_master(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_master_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_master_MASK) + +#define PKC_PKC_ACCESS_ERR_reserved9_MASK (0x300U) +#define PKC_PKC_ACCESS_ERR_reserved9_SHIFT (8U) +/*! reserved9 - reserved for future erors on AHB I/F Layer2 Only + */ +#define PKC_PKC_ACCESS_ERR_reserved9(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved9_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved9_MASK) + +#define PKC_PKC_ACCESS_ERR_ahb_MASK (0x400U) +#define PKC_PKC_ACCESS_ERR_ahb_SHIFT (10U) +/*! ahb - AHB Error: invalid AHB access Layer2 Only + */ +#define PKC_PKC_ACCESS_ERR_ahb(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ahb_SHIFT)) & PKC_PKC_ACCESS_ERR_ahb_MASK) + +#define PKC_PKC_ACCESS_ERR_reserved15_MASK (0xF800U) +#define PKC_PKC_ACCESS_ERR_reserved15_SHIFT (11U) +/*! reserved15 - reserved for future erors on AHB I/F Layer2 Only + */ +#define PKC_PKC_ACCESS_ERR_reserved15(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved15_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved15_MASK) + +#define PKC_PKC_ACCESS_ERR_pkcc_MASK (0x10000U) +#define PKC_PKC_ACCESS_ERR_pkcc_SHIFT (16U) +/*! pkcc - Error in PKC coprocessor kernel + */ +#define PKC_PKC_ACCESS_ERR_pkcc(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_pkcc_SHIFT)) & PKC_PKC_ACCESS_ERR_pkcc_MASK) + +#define PKC_PKC_ACCESS_ERR_fdet_MASK (0x20000U) +#define PKC_PKC_ACCESS_ERR_fdet_SHIFT (17U) +/*! fdet - Error due to error detection circuitry + */ +#define PKC_PKC_ACCESS_ERR_fdet(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_fdet_SHIFT)) & PKC_PKC_ACCESS_ERR_fdet_MASK) + +#define PKC_PKC_ACCESS_ERR_ctrl_MASK (0x40000U) +#define PKC_PKC_ACCESS_ERR_ctrl_SHIFT (18U) +/*! ctrl - Error in PKC software control + */ +#define PKC_PKC_ACCESS_ERR_ctrl(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ctrl_SHIFT)) & PKC_PKC_ACCESS_ERR_ctrl_MASK) + +#define PKC_PKC_ACCESS_ERR_ucrc_MASK (0x80000U) +#define PKC_PKC_ACCESS_ERR_ucrc_SHIFT (19U) +/*! ucrc - Error in layer2 CRC check + */ +#define PKC_PKC_ACCESS_ERR_ucrc(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ucrc_SHIFT)) & PKC_PKC_ACCESS_ERR_ucrc_MASK) + +#define PKC_PKC_ACCESS_ERR_reserved20_MASK (0x100000U) +#define PKC_PKC_ACCESS_ERR_reserved20_SHIFT (20U) +/*! reserved20 - reserved + */ +#define PKC_PKC_ACCESS_ERR_reserved20(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved20_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved20_MASK) + +#define PKC_PKC_ACCESS_ERR_reserved31_MASK (0xFFE00000U) +#define PKC_PKC_ACCESS_ERR_reserved31_SHIFT (21U) +/*! reserved31 - reserved for more block errors + */ +#define PKC_PKC_ACCESS_ERR_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved31_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved31_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_CLR_err_clr_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_CLR_err_clr_SHIFT (0U) +/*! err_clr - Write 1 to reset PKC_ACCESS_ERR SFR. + */ +#define PKC_PKC_ACCESS_ERR_CLR_err_clr(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_err_clr_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_err_clr_MASK) + +#define PKC_PKC_ACCESS_ERR_CLR_reserved31_MASK (0xFFFFFFFEU) +#define PKC_PKC_ACCESS_ERR_CLR_reserved31_SHIFT (1U) +/*! reserved31 - reserved + */ +#define PKC_PKC_ACCESS_ERR_CLR_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_reserved31_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_reserved31_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_ENABLE_en_pdone_MASK (0x1U) +#define PKC_PKC_INT_CLR_ENABLE_en_pdone_SHIFT (0U) +/*! en_pdone - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=0). + */ +#define PKC_PKC_INT_CLR_ENABLE_en_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_en_pdone_MASK) + +#define PKC_PKC_INT_CLR_ENABLE_reserved1_MASK (0x2U) +#define PKC_PKC_INT_CLR_ENABLE_reserved1_SHIFT (1U) +/*! reserved1 - reserved + */ +#define PKC_PKC_INT_CLR_ENABLE_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_reserved1_MASK) + +#define PKC_PKC_INT_CLR_ENABLE_reserved31_MASK (0xFFFFFFFCU) +#define PKC_PKC_INT_CLR_ENABLE_reserved31_SHIFT (2U) +/*! reserved31 - reserved + */ +#define PKC_PKC_INT_CLR_ENABLE_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_reserved31_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_ENABLE_en_pdone_MASK (0x1U) +#define PKC_PKC_INT_SET_ENABLE_en_pdone_SHIFT (0U) +/*! en_pdone - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=1). + */ +#define PKC_PKC_INT_SET_ENABLE_en_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_SET_ENABLE_en_pdone_MASK) + +#define PKC_PKC_INT_SET_ENABLE_reserved1_MASK (0x2U) +#define PKC_PKC_INT_SET_ENABLE_reserved1_SHIFT (1U) +/*! reserved1 - reserved + */ +#define PKC_PKC_INT_SET_ENABLE_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_SET_ENABLE_reserved1_MASK) + +#define PKC_PKC_INT_SET_ENABLE_reserved31_MASK (0xFFFFFFFCU) +#define PKC_PKC_INT_SET_ENABLE_reserved31_SHIFT (2U) +/*! reserved31 - reserved + */ +#define PKC_PKC_INT_SET_ENABLE_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_SET_ENABLE_reserved31_MASK) +/*! @} */ + +/*! @name PKC_INT_STATUS - Interrupt status */ +/*! @{ */ + +#define PKC_PKC_INT_STATUS_int_pdone_MASK (0x1U) +#define PKC_PKC_INT_STATUS_int_pdone_SHIFT (0U) +/*! int_pdone - End-of-computation status flag: INT_PDONE is set after EACH single PKC layer0 or + * layer1 calculation. In case of a universal pointer calculation (layer2) INT_PDONE is set at the + * end of the pipe calculation when PKC_ULEN has been decremented to zero and the final PKC + * calculation has completed. + */ +#define PKC_PKC_INT_STATUS_int_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_STATUS_int_pdone_MASK) + +#define PKC_PKC_INT_STATUS_reserved1_MASK (0x2U) +#define PKC_PKC_INT_STATUS_reserved1_SHIFT (1U) +/*! reserved1 - reserved + */ +#define PKC_PKC_INT_STATUS_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_STATUS_reserved1_MASK) + +#define PKC_PKC_INT_STATUS_reserved31_MASK (0xFFFFFFFCU) +#define PKC_PKC_INT_STATUS_reserved31_SHIFT (2U) +/*! reserved31 - reserved + */ +#define PKC_PKC_INT_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_STATUS_reserved31_MASK) +/*! @} */ + +/*! @name PKC_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define PKC_PKC_INT_ENABLE_en_pdone_MASK (0x1U) +#define PKC_PKC_INT_ENABLE_en_pdone_SHIFT (0U) +/*! en_pdone - PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time + * PKC_INT_STATUS.INT_PDONE is set. Otherwise the interrupt generation is suppressed. + */ +#define PKC_PKC_INT_ENABLE_en_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_ENABLE_en_pdone_MASK) + +#define PKC_PKC_INT_ENABLE_reserved1_MASK (0x2U) +#define PKC_PKC_INT_ENABLE_reserved1_SHIFT (1U) +/*! reserved1 - reserved + */ +#define PKC_PKC_INT_ENABLE_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_ENABLE_reserved1_MASK) + +#define PKC_PKC_INT_ENABLE_reserved31_MASK (0xFFFFFFFCU) +#define PKC_PKC_INT_ENABLE_reserved31_SHIFT (2U) +/*! reserved31 - reserved + */ +#define PKC_PKC_INT_ENABLE_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_ENABLE_reserved31_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_STATUS_int_pdone_MASK (0x1U) +#define PKC_PKC_INT_CLR_STATUS_int_pdone_SHIFT (0U) +/*! int_pdone - Write to clear End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=0). + */ +#define PKC_PKC_INT_CLR_STATUS_int_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_CLR_STATUS_int_pdone_MASK) + +#define PKC_PKC_INT_CLR_STATUS_reserved1_MASK (0x2U) +#define PKC_PKC_INT_CLR_STATUS_reserved1_SHIFT (1U) +/*! reserved1 - reserved + */ +#define PKC_PKC_INT_CLR_STATUS_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_CLR_STATUS_reserved1_MASK) + +#define PKC_PKC_INT_CLR_STATUS_reserved31_MASK (0xFFFFFFFCU) +#define PKC_PKC_INT_CLR_STATUS_reserved31_SHIFT (2U) +/*! reserved31 - reserved + */ +#define PKC_PKC_INT_CLR_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_CLR_STATUS_reserved31_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_STATUS - Interrupt status set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_STATUS_int_pdone_MASK (0x1U) +#define PKC_PKC_INT_SET_STATUS_int_pdone_SHIFT (0U) +/*! int_pdone - Write to set End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=1) to trigger + * a PKC interrupt via software, e.g. for debug purposes. + */ +#define PKC_PKC_INT_SET_STATUS_int_pdone(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_SET_STATUS_int_pdone_MASK) + +#define PKC_PKC_INT_SET_STATUS_reserved1_MASK (0x2U) +#define PKC_PKC_INT_SET_STATUS_reserved1_SHIFT (1U) +/*! reserved1 - reserved + */ +#define PKC_PKC_INT_SET_STATUS_reserved1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_SET_STATUS_reserved1_MASK) + +#define PKC_PKC_INT_SET_STATUS_reserved31_MASK (0xFFFFFFFCU) +#define PKC_PKC_INT_SET_STATUS_reserved31_SHIFT (2U) +/*! reserved31 - reserved + */ +#define PKC_PKC_INT_SET_STATUS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_SET_STATUS_reserved31_MASK) +/*! @} */ + +/*! @name PKC_MODULE_ID - Module ID */ +/*! @{ */ + +#define PKC_PKC_MODULE_ID_size_MASK (0xFFU) +#define PKC_PKC_MODULE_ID_size_SHIFT (0U) +/*! size - Address space of the IP + */ +#define PKC_PKC_MODULE_ID_size(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_size_SHIFT)) & PKC_PKC_MODULE_ID_size_MASK) + +#define PKC_PKC_MODULE_ID_minor_rev_MASK (0xF00U) +#define PKC_PKC_MODULE_ID_minor_rev_SHIFT (8U) +/*! minor_rev - Minor revision + */ +#define PKC_PKC_MODULE_ID_minor_rev(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_minor_rev_SHIFT)) & PKC_PKC_MODULE_ID_minor_rev_MASK) + +#define PKC_PKC_MODULE_ID_major_rev_MASK (0xF000U) +#define PKC_PKC_MODULE_ID_major_rev_SHIFT (12U) +/*! major_rev - Major revision + */ +#define PKC_PKC_MODULE_ID_major_rev(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_major_rev_SHIFT)) & PKC_PKC_MODULE_ID_major_rev_MASK) + +#define PKC_PKC_MODULE_ID_id_MASK (0xFFFF0000U) +#define PKC_PKC_MODULE_ID_id_SHIFT (16U) +/*! id - Module ID + */ +#define PKC_PKC_MODULE_ID_id(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_id_SHIFT)) & PKC_PKC_MODULE_ID_id_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PKC_Register_Masks */ + + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC base address */ + #define PKC_BASE (0x5002F000u) + /** Peripheral PKC base address */ + #define PKC_BASE_NS (0x4002F000u) + /** Peripheral PKC base pointer */ + #define PKC ((PKC_Type *)PKC_BASE) + /** Peripheral PKC base pointer */ + #define PKC_NS ((PKC_Type *)PKC_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC_NS } +#else + /** Peripheral PKC base address */ + #define PKC_BASE (0x4002F000u) + /** Peripheral PKC base pointer */ + #define PKC ((PKC_Type *)PKC_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC } +#endif + +/*! + * @} + */ /* end of group PKC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset], offset: 0x0 */ + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ + __IO uint32_t RESETCTRL; /**< Reset Control, offset: 0x8 */ + __IO uint32_t RESETCAUSE; /**< Reset Cause, offset: 0xC */ + __IO uint32_t DCDC0; /**< DCDC (first) control, offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + __IO uint32_t LDOMEM; /**< Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x20 */ + __IO uint32_t LDOCORE0; /**< LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x24 */ + __IO uint32_t LDOFLASHNV; /**< Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x28 */ + __IO uint32_t LDOEFUSEPROG; /**< eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x2C */ + __IO uint32_t BODVDDMAIN; /**< VDDMAIN Brown Out Dectector control, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_3[8]; + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __O uint32_t CMD; /**< DCDC and LDOCORE power state (enable/disable) control., offset: 0x60 */ + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ + __IO uint32_t WAKEIOCAUSE; /**< Wake-up I/O source, offset: 0x68 */ + __IO uint32_t LIFECYCLESTATE; /**< Life Cycle State as configured in the OTP, offset: 0x6C */ + __I uint32_t STATUSPWR; /**< Power status from various analog modules (DCDC, LDO, etc), offset: 0x70 */ + __IO uint32_t STATUSCLK; /**< Clock status, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t AOREG0; /**< Always-on 0, offset: 0x80 */ + __IO uint32_t AOREG1; /**< Always-on 1, offset: 0x84 */ + uint8_t RESERVED_6[8]; + __IO uint32_t MISCCTRL; /**< Miscellaneous Control Register for PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_7[4]; + __IO uint32_t RTCOSC32K; /**< 32 KHz clocks source control, offset: 0x98 */ + __IO uint32_t OSEVENTTIMER; /**< OS Event Timer control, offset: 0x9C */ + __IO uint32_t PDSLEEPCFG1; /**< Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xA0 */ + __IO uint32_t TIMEOUTEVENTS; /**< Record time-out errors that might occur at different stages during IC power up, offset: 0xA4 */ + uint8_t RESERVED_8[8]; + __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ + __IO uint32_t SRAMRETCTRL; /**< Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB4 */ + __IO uint32_t PDRUNCFG0; /**< Power configuration 0, offset: 0xB8 */ + __IO uint32_t PDRUNCFG1; /**< Power configuration 1, offset: 0xBC */ + __O uint32_t PDRUNCFGSET0; /**< Power configuration set 0, offset: 0xC0 */ + __O uint32_t PDRUNCFGSET1; /**< Power configuration set 1, offset: 0xC4 */ + __O uint32_t PDRUNCFGCLR0; /**< Power configuration clear 0, offset: 0xC8 */ + __O uint32_t PDRUNCFGCLR1; /**< Power configuration clear 1, offset: 0xCC */ + uint8_t RESERVED_9[4]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ + __IO uint32_t SRAMCTRL0; /**< RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode, offset: 0xD8 */ + __IO uint32_t SRAMCTRL1; /**< RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode, offset: 0xDC */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name CTRL - Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset] */ +/*! @{ */ + +#define PMC_CTRL_LPMODE_MASK (0x3U) +#define PMC_CTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Power Mode Control. + * 0b00..ACTIVE power mode. + * 0b01..DEEP-SLEEP low power mode. + * 0b10..POWER-DOWN low power mode. + * 0b11..DEEP-POWER-DOWN low power mode. + */ +#define PMC_CTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LPMODE_SHIFT)) & PMC_CTRL_LPMODE_MASK) + +#define PMC_CTRL_SELCLOCK_MASK (0x4U) +#define PMC_CTRL_SELCLOCK_SHIFT (2U) +/*! SELCLOCK - Select the Power Management Controller (PMC) functional clock : + * 0b0..1 MHz Free Running Oscillator. + * 0b1..12 MHz Free Running Oscillator. + */ +#define PMC_CTRL_SELCLOCK(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCLOCK_SHIFT)) & PMC_CTRL_SELCLOCK_MASK) + +#define PMC_CTRL_SELMEMSUPPLY_MASK (0x8U) +#define PMC_CTRL_SELMEMSUPPLY_SHIFT (3U) +/*! SELMEMSUPPLY - Select Memories supply source in DEEP-SLEEP low power mode: Note: in POWER-DOWN + * and DEEP-POWER-DOWN, memories are always supplied by LDO_MEM. + * 0b0..Memories are supplied by LDO_MEM in 'DEEP-SLEEP' low power mode. + * 0b1..Memories are supplied by DCDC/LDO_CORE in 'DEEP-SLEEP' low power mode. + */ +#define PMC_CTRL_SELMEMSUPPLY(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELMEMSUPPLY_SHIFT)) & PMC_CTRL_SELMEMSUPPLY_MASK) + +#define PMC_CTRL_SELCORESUPPLYWK_MASK (0x10U) +#define PMC_CTRL_SELCORESUPPLYWK_SHIFT (4U) +/*! SELCORESUPPLYWK - Select Core Logic supply source when waking up from DEEP-SLEEP and POWER-DOWN low power modes : + * 0b0..Core Logic is supplied by DCDC Converter. + * 0b1..Core Logic is supplied by LDO CORE (configured in High Power mode). + */ +#define PMC_CTRL_SELCORESUPPLYWK(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCORESUPPLYWK_SHIFT)) & PMC_CTRL_SELCORESUPPLYWK_MASK) + +#define PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK (0x60U) +#define PMC_CTRL_DEEPSLEEPCORESUPPLY_SHIFT (5U) +/*! DEEPSLEEPCORESUPPLY - Select Core Logic supply source during DEEP-SLEEP low power mode : + * 0b00..LDO CORE in Low Power Mode. + * 0b01..LDO CORE in High Power Mode. + * 0b10..DCDC Converter. + */ +#define PMC_CTRL_DEEPSLEEPCORESUPPLY(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_DEEPSLEEPCORESUPPLY_SHIFT)) & PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK) +/*! @} */ + +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP-SLEEP low power mode. + * 0b10..Latest IC boot was from POWER-DOWN low power mode. + * 0b11..Latest IC boot was from DEEP-POWER-DOWN low power mode. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) + +#define PMC_STATUS_FSMDCDCENABLE_MASK (0x100000U) +#define PMC_STATUS_FSMDCDCENABLE_SHIFT (20U) +/*! FSMDCDCENABLE - Indicates the power status of the DCDC (enabled or disabled) as driven by the Hardware Finite State Machines (FSM). + * 0b0..DCDC is currently disabled by the Hardware Finite State Machine (FSM). + * 0b1..DCDC is currently enabled by the Hardware Finite State Machine (FSM). + */ +#define PMC_STATUS_FSMDCDCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDCDCENABLE_SHIFT)) & PMC_STATUS_FSMDCDCENABLE_MASK) + +#define PMC_STATUS_FSMLDOCOREHPENABLE_MASK (0x200000U) +#define PMC_STATUS_FSMLDOCOREHPENABLE_SHIFT (21U) +/*! FSMLDOCOREHPENABLE - Indicates the power status of the LDO CORE High Power Mode (enabled or + * disabled) as driven by the Hardware Finite State Machines (FSM). + * 0b0..LDO CORE High Power Mode is currently disabled by the Hardware Finite State Machine (FSM). + * 0b1..LDO CORE High Power Mode is currently enabled by the Hardware Finite State Machine (FSM). + */ +#define PMC_STATUS_FSMLDOCOREHPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCOREHPENABLE_SHIFT)) & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) + +#define PMC_STATUS_FSMLDOCORELPENABLE_MASK (0x400000U) +#define PMC_STATUS_FSMLDOCORELPENABLE_SHIFT (22U) +/*! FSMLDOCORELPENABLE - Indicates the power status of the LDO CORE Low Power Mode (enabled or + * disabled) as driven by the Hardware Finite State Machines (FSM). + * 0b0..LDO CORE Low Power Mode is currently disabled by the Hardware Finite State Machine (FSM). + * 0b1..LDO CORE Low Power Mode is currently enabled by the Hardware Finite State Machine (FSM). + */ +#define PMC_STATUS_FSMLDOCORELPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCORELPENABLE_SHIFT)) & PMC_STATUS_FSMLDOCORELPENABLE_MASK) + +#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK (0x800000U) +#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE_SHIFT (23U) +/*! FSMLDOCOREEXPTMRENABLE - Indicates the status of the LDO CORE Exponential Timer (enabled or + * disabled) as driven by the Hardware Finite State Machines (FSM). + */ +#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCOREEXPTMRENABLE_SHIFT)) & PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK) +/*! @} */ + +/*! @name RESETCTRL - Reset Control */ +/*! @{ */ + +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP-POWER-DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP-POWER-DOWN mode is disabled. + * 0b1..Reset event from DEEP-POWER-DOWN mode is enabled. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disabled. + * 0b1..Software reset is enabled. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK (0x30U) +#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT (4U) +/*! BODVDDMAINRESETENA_SECURE - BOD_VDDMAIN reset enabled. + * 0b10..BOD_VDDMAIN reset is disabled. + * 0b01..And any other value than b10: BOD_VDDMAIN reset is enabled. + */ +#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK) + +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK (0xC0U) +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT (6U) +/*! BODCORERESETENA_SECURE - BOD_CORE reset enabled. + * 0b10..BODCORE reset is disabled. + * 0b01..And any other value than b10: BOD_CORE reset is enabled. + */ +#define PMC_RESETCTRL_BODCORERESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK) + +#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK (0x30000000U) +#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT (28U) +/*! BODVDDMAINRESETENA_SECURE_DP - BOD_VDDMAIN reset enabled. + * 0b10..BOD_VDDMAIN reset is disabled. + * 0b01..And any other value than b10: BOD_VDDMAIN reset is enabled. + */ +#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK) + +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK (0xC0000000U) +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT (30U) +/*! BODCORERESETENA_SECURE_DP - BOD_CORE reset enable. + * 0b10..BOD_CORE reset is disabled. + * 0b01..And any other value than b10: BOD_CORE reset is enabled. + */ +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK) +/*! @} */ + +/*! @name RESETCAUSE - Reset Cause */ +/*! @{ */ + +#define PMC_RESETCAUSE_POR_MASK (0x1U) +#define PMC_RESETCAUSE_POR_SHIFT (0U) +/*! POR - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) + +#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) +#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) +/*! PADRESET - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) + +#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) +#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) +/*! BODRESET - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN + * or BOD_CORE. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) + +#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) +#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) +/*! SYSTEMRESET - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) + +#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) +#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) +/*! WDTRESET - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) + +#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) +#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) +/*! SWRRESET - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) + +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) +/*! DPDRESET_WAKEUPIO - 1 : A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) + +#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) +#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) +/*! DPDRESET_RTC - 1 : A RTC (either RTC Alarm or RTC wake up) reset event occured during + * DEEP-POWER-DOWN mode. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) + +#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) +/*! DPDRESET_OSTIMER - 1 : A OS Event Timer reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) + +#define PMC_RESETCAUSE_CDOGRESET_MASK (0x200U) +#define PMC_RESETCAUSE_CDOGRESET_SHIFT (9U) +/*! CDOGRESET - 1 : The last chip reset was caused by the code Watchdog. Write '1' to clear this bit. + */ +#define PMC_RESETCAUSE_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_CDOGRESET_SHIFT)) & PMC_RESETCAUSE_CDOGRESET_MASK) + +#define PMC_RESETCAUSE_DPD_EVENTS_ORDER_MASK (0x1C00U) +#define PMC_RESETCAUSE_DPD_EVENTS_ORDER_SHIFT (10U) +/*! DPD_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which reset event occured first between + * DPDRESET_WAKEUPIO, DPDRESET_RTC and DPDRESET_OSTIMER. Write 'b001' to clear these bit field. + * 0b000..No event + * 0b001..WAKEUPIO + * 0b010..RTC + * 0b011..Both WAKEUPIO and RTC events occured at the same time (less than 1 nano-second from each other) + * 0b100..OSTIMER + * 0b101..Both WAKEUPIO and OSTIMER events occured at the same time (less than 1 nano-second from each other) + * 0b110..Both RTC and OSTIMER events occured at the same time (less than 1 nano-second from each other) + * 0b111..WAKEUPIO, RTC and OSTIMER events occured at the same time (less than 1 nano-second from each other) + */ +#define PMC_RESETCAUSE_DPD_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPD_EVENTS_ORDER_SHIFT)) & PMC_RESETCAUSE_DPD_EVENTS_ORDER_MASK) +/*! @} */ + +/*! @name DCDC0 - DCDC (first) control */ +/*! @{ */ + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. + */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. + */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. + */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) +/*! @} */ + +/*! @name LDOMEM - Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOMEM_VADJ_MASK (0x1FU) +#define PMC_LDOMEM_VADJ_SHIFT (0U) +/*! VADJ - Sets the Memories LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOMEM_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_SHIFT)) & PMC_LDOMEM_VADJ_MASK) + +#define PMC_LDOMEM_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOMEM_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Memories LDO output level in all power down modes. + */ +#define PMC_LDOMEM_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_PWD_SHIFT)) & PMC_LDOMEM_VADJ_PWD_MASK) + +#define PMC_LDOMEM_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOMEM_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Memories LDO Boost output level. + */ +#define PMC_LDOMEM_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_BOOST_SHIFT)) & PMC_LDOMEM_VADJ_BOOST_MASK) + +#define PMC_LDOMEM_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOMEM_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Memories LDO Boost output level in all power down modes. + */ +#define PMC_LDOMEM_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOMEM_VADJ_BOOST_PWD_MASK) +/*! @} */ + +/*! @name LDOCORE0 - LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOCORE0_LPREGREFSEL_MASK (0x60000U) +#define PMC_LDOCORE0_LPREGREFSEL_SHIFT (17U) +/*! LPREGREFSEL - Low Power regulation point select. + * 0b00..900 mV. + * 0b01..850 mV. + * 0b10..800 mV. + * 0b11..750 mV. + */ +#define PMC_LDOCORE0_LPREGREFSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOCORE0_LPREGREFSEL_SHIFT)) & PMC_LDOCORE0_LPREGREFSEL_MASK) + +#define PMC_LDOCORE0_REGREFTRIM_MASK (0x7F000000U) +#define PMC_LDOCORE0_REGREFTRIM_SHIFT (24U) +/*! REGREFTRIM - High Power regulation point select. + */ +#define PMC_LDOCORE0_REGREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOCORE0_REGREFTRIM_SHIFT)) & PMC_LDOCORE0_REGREFTRIM_MASK) +/*! @} */ + +/*! @name LDOFLASHNV - Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOFLASHNV_VADJ_MASK (0x7U) +#define PMC_LDOFLASHNV_VADJ_SHIFT (0U) +/*! VADJ - Sets the LDO output level. + * 0b000..1.650 V. + * 0b001..1.700 V. + * 0b010..1.750 V. + * 0b011..1.800 V. + * 0b100..1.850 V. + * 0b101..1.900 V. + * 0b110..1.950 V. + * 0b111..2.0 V. + */ +#define PMC_LDOFLASHNV_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOFLASHNV_VADJ_SHIFT)) & PMC_LDOFLASHNV_VADJ_MASK) +/*! @} */ + +/*! @name LDOEFUSEPROG - eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOEFUSEPROG_VADJ_MASK (0x7U) +#define PMC_LDOEFUSEPROG_VADJ_SHIFT (0U) +/*! VADJ - Sets the LDO output level. + * 0b000..1.650 V. + * 0b001..1.700 V. + * 0b010..1.750 V. + * 0b011..1.800 V. + * 0b100..1.850 V. + * 0b101..1.900 V. + * 0b110..1.950 V. + * 0b111..2.0 V. + */ +#define PMC_LDOEFUSEPROG_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOEFUSEPROG_VADJ_SHIFT)) & PMC_LDOEFUSEPROG_VADJ_MASK) +/*! @} */ + +/*! @name BODVDDMAIN - VDDMAIN Brown Out Dectector control */ +/*! @{ */ + +#define PMC_BODVDDMAIN_TRIGLVL_MASK (0x1FU) +#define PMC_BODVDDMAIN_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.80 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVDDMAIN_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVDDMAIN_TRIGLVL_SHIFT)) & PMC_BODVDDMAIN_TRIGLVL_MASK) + +#define PMC_BODVDDMAIN_HYST_MASK (0x60U) +#define PMC_BODVDDMAIN_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVDDMAIN_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVDDMAIN_HYST_SHIFT)) & PMC_BODVDDMAIN_HYST_MASK) +/*! @} */ + +/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_BODCORE_TRIGLVL_MASK (0x7U) +#define PMC_BODCORE_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b000..0.60 V. + * 0b001..0.65 V. + * 0b010..0.70 V. + * 0b011..0.75 V. + * 0b100..0.80 V. + * 0b101..0.85 V. + * 0b110..0.90 V. + * 0b111..0.95 V. + */ +#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) + +#define PMC_BODCORE_HYST_MASK (0x30U) +#define PMC_BODCORE_HYST_SHIFT (4U) +/*! HYST - BOD_CORE Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) +/*! @} */ + +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ +/*! @{ */ + +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN): + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. + */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) + +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Bypass Test Mode control. + * 0b0..Oscillation mode. + * 0b1..Bypass test mode is enabled. + */ +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. + */ +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. + */ +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control */ +/*! @{ */ + +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disabled. + * 0b1..Hysteresis is enabled. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). + */ +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +/*! @} */ + +/*! @name CMD - DCDC and LDOCORE power state (enable/disable) control. */ +/*! @{ */ + +#define PMC_CMD_DCDCENABLE_MASK (0x1U) +#define PMC_CMD_DCDCENABLE_SHIFT (0U) +/*! DCDCENABLE - Enable DCDC (self clearing bit). + * 0b0..No effect. + * 0b1..Enable DCDC. Automatically reset to '0' by the Hardware. + */ +#define PMC_CMD_DCDCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_DCDCENABLE_SHIFT)) & PMC_CMD_DCDCENABLE_MASK) + +#define PMC_CMD_DCDCDISABLE_MASK (0x2U) +#define PMC_CMD_DCDCDISABLE_SHIFT (1U) +/*! DCDCDISABLE - Disable DCDC (self clearing bit). + * 0b0..No effect. + * 0b1..Disbale DCDC. Automatically reset to '0' by the Hardware. + */ +#define PMC_CMD_DCDCDISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_DCDCDISABLE_SHIFT)) & PMC_CMD_DCDCDISABLE_MASK) + +#define PMC_CMD_LDOCOREHIGHPWRENABLE_MASK (0x4U) +#define PMC_CMD_LDOCOREHIGHPWRENABLE_SHIFT (2U) +/*! LDOCOREHIGHPWRENABLE - Enable LDO CORE High Power Mode (self clearing bit). + * 0b0..No effect. + * 0b1..Enable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware. + */ +#define PMC_CMD_LDOCOREHIGHPWRENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCOREHIGHPWRENABLE_SHIFT)) & PMC_CMD_LDOCOREHIGHPWRENABLE_MASK) + +#define PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK (0x8U) +#define PMC_CMD_LDOCOREHIGHPWRDISABLE_SHIFT (3U) +/*! LDOCOREHIGHPWRDISABLE - Disable LDO CORE High Power Mode (self clearing bit). + * 0b0..No effect. + * 0b1..Disable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware. + */ +#define PMC_CMD_LDOCOREHIGHPWRDISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCOREHIGHPWRDISABLE_SHIFT)) & PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK) + +#define PMC_CMD_LDOCORELOWPWRENABLE_MASK (0x10U) +#define PMC_CMD_LDOCORELOWPWRENABLE_SHIFT (4U) +/*! LDOCORELOWPWRENABLE - Enable LDO CORE Low Power Mode (self clearing bit). + * 0b0..No effect. + * 0b1..Enable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware. + */ +#define PMC_CMD_LDOCORELOWPWRENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCORELOWPWRENABLE_SHIFT)) & PMC_CMD_LDOCORELOWPWRENABLE_MASK) + +#define PMC_CMD_LDOCORELOWPWRDISABLE_MASK (0x20U) +#define PMC_CMD_LDOCORELOWPWRDISABLE_SHIFT (5U) +/*! LDOCORELOWPWRDISABLE - Disable LDO CORE Low Power Mode (self clearing bit). + * 0b0..No effect. + * 0b1..Disable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware. + */ +#define PMC_CMD_LDOCORELOWPWRDISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCORELOWPWRDISABLE_SHIFT)) & PMC_CMD_LDOCORELOWPWRDISABLE_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disabled. + * 0b1..Rising edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disabled. + * 0b1..Falling edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disabled. + * 0b1..Rising edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disabled. + * 0b1..Falling edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disabled. + * 0b1..Rising edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disabled. + * 0b1..Falling edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes: + * 0b0..Rising edge detection is disabled. + * 0b1..Rising edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes: + * 0b0..Falling edge detection is disabled. + * 0b1..Falling edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK (0x100U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_SHIFT (8U) +/*! RISINGEDGEWAKEUP4 - Enable / disable detection of rising edge events on Wake Up 4 pin in Deep Power Down modes: + * 0b0..Rising edge detection is disabled. + * 0b1..Rising edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK (0x200U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_SHIFT (9U) +/*! FALLINGEDGEWAKEUP4 - Enable / disable detection of falling edge events on Wake Up 4 pin in Deep Power Down modes: + * 0b0..Falling edge detection is disabled. + * 0b1..Falling edge detection is enabled. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK (0xC00U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT (10U) +/*! MODEWAKEUPIOPAD0 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK (0x3000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT (12U) +/*! MODEWAKEUPIOPAD1 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK (0xC000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT (14U) +/*! MODEWAKEUPIOPAD2 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK (0x30000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT (16U) +/*! MODEWAKEUPIOPAD3 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_MASK (0xC0000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_SHIFT (18U) +/*! MODEWAKEUPIOPAD4 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_MASK) + +#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK (0x100000U) +#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT (20U) +/*! WAKEUPIO_ENABLE_CTRL - Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 10 to 19). + * 0b0..WAKEUP IO PAD mode control comes from IOCON. + * 0b1..WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 10 to 19). + */ +#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK) + +#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK (0x200000U) +#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT (21U) +/*! WAKEUPIO_RSTN - WAKEUP IO event detector reset control. + * 0b0..Bloc is reset. + * 0b1..Bloc is not reset. + */ +#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Wake-up I/O source */ +/*! @{ */ + +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP4_MASK (0x10U) +#define PMC_WAKEIOCAUSE_WAKEUP4_SHIFT (4U) +/*! WAKEUP4 - Allows to identify Wake up I/O 4 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 4. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 4. + */ +#define PMC_WAKEIOCAUSE_WAKEUP4(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP4_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP4_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK (0x3E0U) +#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT (5U) +/*! WAKEUPIO_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which wake up I/O event occured first when several wake up I/Os are enabled. + * 0b00000..None + * 0b00001..Wake up I/O 0 + * 0b00010..Wake up I/O 1 + * 0b00100..Wake up I/O 2 + * 0b01000..Wake up I/O 3 + * 0b10000..Wake up I/O 4 + */ +#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK) +/*! @} */ + +/*! @name LIFECYCLESTATE - Life Cycle State as configured in the OTP */ +/*! @{ */ + +#define PMC_LIFECYCLESTATE_LC_MASK (0xFFU) +#define PMC_LIFECYCLESTATE_LC_SHIFT (0U) +/*! LC - Life Cycle state + */ +#define PMC_LIFECYCLESTATE_LC(x) (((uint32_t)(((uint32_t)(x)) << PMC_LIFECYCLESTATE_LC_SHIFT)) & PMC_LIFECYCLESTATE_LC_MASK) +/*! @} */ + +/*! @name STATUSPWR - Power status from various analog modules (DCDC, LDO, etc) */ +/*! @{ */ + +#define PMC_STATUSPWR_DCDCPWROK_MASK (0x1U) +#define PMC_STATUSPWR_DCDCPWROK_SHIFT (0U) +/*! DCDCPWROK - DCDC converter power OK. + */ +#define PMC_STATUSPWR_DCDCPWROK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSPWR_DCDCPWROK_SHIFT)) & PMC_STATUSPWR_DCDCPWROK_MASK) + +#define PMC_STATUSPWR_LDOCOREPWROK_MASK (0x10U) +#define PMC_STATUSPWR_LDOCOREPWROK_SHIFT (4U) +/*! LDOCOREPWROK - CORE LDO power OK. + */ +#define PMC_STATUSPWR_LDOCOREPWROK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSPWR_LDOCOREPWROK_SHIFT)) & PMC_STATUSPWR_LDOCOREPWROK_MASK) +/*! @} */ + +/*! @name STATUSCLK - Clock status */ +/*! @{ */ + +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. + */ +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) + +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG0 - Always-on 0 */ +/*! @{ */ + +#define PMC_AOREG0_DATA_15_0_MASK (0xFFFFU) +#define PMC_AOREG0_DATA_15_0_SHIFT (0U) +/*! DATA_15_0 - General purpose always on domain data storage. + */ +#define PMC_AOREG0_DATA_15_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG0_DATA_15_0_SHIFT)) & PMC_AOREG0_DATA_15_0_MASK) +/*! @} */ + +/*! @name AOREG1 - Always-on 1 */ +/*! @{ */ + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. + */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. + */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN or BOD_CORE. + */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. + */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. + */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. + */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode. + */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - A RTC event occured during DEEP-POWER-DOWN mode. + */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - An OS Timer event occured during a DEEP-POWER-DOWN mode. + */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_CDOGRESET_MASK (0x2000U) +#define PMC_AOREG1_CDOGRESET_SHIFT (13U) +/*! CDOGRESET - The last chip reset was caused by the code Watchdog. + */ +#define PMC_AOREG1_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_CDOGRESET_SHIFT)) & PMC_AOREG1_CDOGRESET_MASK) + +#define PMC_AOREG1_DPD_EVENTS_ORDER_MASK (0x1C000U) +#define PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT (14U) +/*! DPD_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which reset event occured first, between a + * wake up I/O event (in DEEP-POWER-DOWN), a RTC event (in DEEP-POWER-DOWN) and a OS Timer event + * (in DEEP-POWER-DOWN). May be usefull when several reset events are enabled during + * DEEP-POWER-DOWN. + * 0b000..No event + * 0b001..WAKEUPIO + * 0b010..RTC + * 0b011..Both WAKEUPIO and RTC events occured at the same time (the 2 events occured within 1 nano-second of each other) + * 0b100..OSTIMER + * 0b101..Both WAKEUPIO and OSTIMER events occured at the same time (the 2 events occured within 1 nano-second of each other) + * 0b110..Both RTC and OSTIMER events occured at the same time (the 2 events occured within 1 nano-second of each other) + * 0b111..WAKEUPIO, RTC and OSTIMER events occured at the same time (the 3 events occured within 1 nano-second of each other) + */ +#define PMC_AOREG1_DPD_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT)) & PMC_AOREG1_DPD_EVENTS_ORDER_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF000000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (24U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. + */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Miscellaneous Control Register for PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_VREF_ISO_MASK (0x10000U) +#define PMC_MISCCTRL_VREF_ISO_SHIFT (16U) +/*! VREF_ISO - VREF isolation control. + * 0b0..VREF module isolation is disabled. + * 0b1..VREF module isolation is enabled. + */ +#define PMC_MISCCTRL_VREF_ISO(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_VREF_ISO_SHIFT)) & PMC_MISCCTRL_VREF_ISO_MASK) +/*! @} */ + +/*! @name RTCOSC32K - 32 KHz clocks source control */ +/*! @{ */ + +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in for the RTC, the OS Event Timer and the rest of + * the SoC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) +/*! @} */ + +/*! @name OSEVENTTIMER - OS Event Timer control */ +/*! @{ */ + +#define PMC_OSEVENTTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSEVENTTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. + */ +#define PMC_OSEVENTTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_SOFTRESET_SHIFT)) & PMC_OSEVENTTIMER_SOFTRESET_MASK) + +#define PMC_OSEVENTTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSEVENTTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. + */ +#define PMC_OSEVENTTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_CLOCKENABLE_SHIFT)) & PMC_OSEVENTTIMER_CLOCKENABLE_MASK) + +#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + */ +#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSEVENTTIMER_DPDWAKEUPENABLE_MASK) + +#define PMC_OSEVENTTIMER_SELCLOCK_MASK (0x18U) +#define PMC_OSEVENTTIMER_SELCLOCK_SHIFT (3U) +/*! SELCLOCK - Select OS Event Timer Clock source + * 0b00..32-KHz Free Running Oscillator (FRO) + * 0b01..32-KHz Crystal Oscillator (XTAL) + * 0b10..1-MHz FRO + * 0b11..System Bus clock + */ +#define PMC_OSEVENTTIMER_SELCLOCK(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_SELCLOCK_SHIFT)) & PMC_OSEVENTTIMER_SELCLOCK_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG1 - Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS_MASK (0x1U) +#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS_SHIFT (0U) +/*! PDEN_CMPBIAS - Controls Comparators 1/2/3 Bias power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). + * 0b0..Analog Bias is powered on during low power mode. + * 0b1..Analog Bias is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_CMPBIAS_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_CMPBIAS_MASK) + +#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_MASK (0x2U) +#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_SHIFT (1U) +/*! PDEN_HSCMP0_DAC - Controls High Speed Comparator0 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). + * 0b0..High Speed Comparator0 DAC is powered on during low power mode. + * 0b1..High Speed Comparator0 DAC is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_MASK) + +#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_MASK (0x4U) +#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_SHIFT (2U) +/*! PDEN_HSCMP1_DAC - Controls High Speed Comparator1 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). + * 0b0..High Speed Comparator1 DAC is powered on during low power mode. + * 0b1..High Speed Comparator1 DAC is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_MASK) + +#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_MASK (0x8U) +#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_SHIFT (3U) +/*! PDEN_HSCMP2_DAC - Controls High Speed Comparator2 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN). + * 0b0..High Speed Comparator2 DAC is powered on during low power mode. + * 0b1..High Speed Comparator2 DAC is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_MASK) + +#define PMC_PDSLEEPCFG1_PDEN_DAC0_MASK (0x10U) +#define PMC_PDSLEEPCFG1_PDEN_DAC0_SHIFT (4U) +/*! PDEN_DAC0 - Controls DAC0 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..DAC0 is powered on during low power mode. + * 0b1..DAC0 is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC0_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC0_MASK) + +#define PMC_PDSLEEPCFG1_PDEN_DAC1_MASK (0x20U) +#define PMC_PDSLEEPCFG1_PDEN_DAC1_SHIFT (5U) +/*! PDEN_DAC1 - Controls DAC1 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..DAC1 is powered on during low power mode. + * 0b1..DAC1 is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC1_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC1_MASK) + +#define PMC_PDSLEEPCFG1_PDEN_DAC2_MASK (0x40U) +#define PMC_PDSLEEPCFG1_PDEN_DAC2_SHIFT (6U) +/*! PDEN_DAC2 - Controls DAC2 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..DAC2 is powered on during low power mode. + * 0b1..DAC2 is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG1_PDEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC2_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC2_MASK) + +#define PMC_PDSLEEPCFG1_STOPEN_DAC0_MASK (0x80U) +#define PMC_PDSLEEPCFG1_STOPEN_DAC0_SHIFT (7U) +/*! STOPEN_DAC0 - Controls DAC0 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN). + * 0b0..DAC Stop Mode is disabled. + * 0b1..DAC Stop Mode is enabled. + */ +#define PMC_PDSLEEPCFG1_STOPEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC0_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC0_MASK) + +#define PMC_PDSLEEPCFG1_STOPEN_DAC1_MASK (0x100U) +#define PMC_PDSLEEPCFG1_STOPEN_DAC1_SHIFT (8U) +/*! STOPEN_DAC1 - Controls DAC1 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN). + * 0b0..DAC Stop Mode is disabled. + * 0b1..DAC Stop Mode is enabled. + */ +#define PMC_PDSLEEPCFG1_STOPEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC1_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC1_MASK) + +#define PMC_PDSLEEPCFG1_STOPEN_DAC2_MASK (0x200U) +#define PMC_PDSLEEPCFG1_STOPEN_DAC2_SHIFT (9U) +/*! STOPEN_DAC2 - Controls DAC2 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN). + * 0b0..DAC Stop Mode is disabled. + * 0b1..DAC Stop Mode is enabled. + */ +#define PMC_PDSLEEPCFG1_STOPEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC2_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC2_MASK) +/*! @} */ + +/*! @name TIMEOUTEVENTS - Record time-out errors that might occur at different stages during IC power up */ +/*! @{ */ + +#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_MASK (0x1U) +#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_SHIFT (0U) +/*! PWUP_DCDC_OK - 1: a time out event occured during power up when waiting for DCDC to become functional. + */ +#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_MASK) + +#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_MASK (0x2U) +#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_SHIFT (1U) +/*! PWUP_LDOFLASHNV_OK - 1: a time out event occured during power up when waiting for LDO Flash NV to become functional. + */ +#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_MASK) + +#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_MASK (0x4U) +#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_SHIFT (2U) +/*! PWUP_SRAM_WAKEUP - 1: a time out event occured during power up when waiting for SRAM to become functional. + */ +#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_MASK) + +#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_MASK (0x8U) +#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_SHIFT (3U) +/*! PWUP_FLASHINIT_DONE - 1: a time out event occured during power up when waiting for Flash initialization. + */ +#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_MASK) + +#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_MASK (0x10U) +#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_SHIFT (4U) +/*! DSLP_LDOFLASH_SRAM_OFF - 1: a time out event occured during deep sleep when waiting for LDO Flash NV or SRAM shut off. + */ +#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_MASK) + +#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_MASK (0x20U) +#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_SHIFT (5U) +/*! DSLP_DCDC_OK - 1: a time out event occured during deep sleep when waiting for DCDC to become functional. + */ +#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_MASK) + +#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_MASK (0x40U) +#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_SHIFT (6U) +/*! DSLP_LDOFLASHNV_OK - 1: a time out event occured during deep sleep when waiting for LDO Flash NV to become functional. + */ +#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_MASK) + +#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_MASK (0x80U) +#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_SHIFT (7U) +/*! DSLP_SRAM_WAKEUP - 1: a time out event occured during deep sleep when waiting for SRAM to become functional. + */ +#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_MASK) + +#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_MASK (0x100U) +#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_SHIFT (8U) +/*! PDWN_LDOFLASH_SRAM_OFF - 1: a time out event occured during power down when waiting for for LDO Flash NV or SRAM shut off. + */ +#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_MASK) + +#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_MASK (0x200U) +#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_SHIFT (9U) +/*! PDWN_DCDC_BODVDDMAIN_OK - 1: a time out event occured during power down when waiting for DCDC or BOD_VDDMAIN to become functional. + */ +#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_MASK) + +#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_MASK (0x400U) +#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_SHIFT (10U) +/*! PDWN_LDOFLASHNV_OK - 1: a time out event occured during power down when waiting for LDO Flash NV to become functional. + */ +#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_MASK) + +#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_MASK (0x800U) +#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_SHIFT (11U) +/*! PDWN_SRAM_WAKEUP - 1: a time out event occured during power down when waiting for SRAM to become functional. + */ +#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_MASK) + +#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_MASK (0x1000U) +#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_SHIFT (12U) +/*! PDWN_FLASHINIT_DONE - 1: a time out event occured during power down when waiting for Flash initialization. + */ +#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) +#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) +/*! PDEN_BIAS - Controls Analog Bias power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..Analog Bias is powered on during low power mode. + * 0b1..Analog Bias is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) +#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) +/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..BOD_CORE is powered on during low power mode. + * 0b1..BOD_CORE is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_MASK (0x8U) +#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_SHIFT (3U) +/*! PDEN_BODVDDMAIN - Controls BOD_VDDMAIN power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..BOD_VDDMAIN is powered on during low power mode. + * 0b1..BOD_VDDMAIN is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) +#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) +/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. + * 0b0..FRO 1MHz is powered on during low power mode. + * 0b1..FRO 1MHz is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) +#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) +/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP-SLEEP (always shut down + * during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..FRO 192 MHz is powered on during low power mode. + * 0b1..FRO 192 MHz is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. + * 0b0..FRO 32 KHz is powered on during low power mode. + * 0b1..FRO 32 KHz is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. + * 0b0..crystal 32 KHz is powered on during low power mode. + * 0b1..crystal 32 KHz is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_XTALHF_MASK (0x100U) +#define PMC_PDSLEEPCFG0_PDEN_XTALHF_SHIFT (8U) +/*! PDEN_XTALHF - Controls high speed crystal power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..High speed crystal is powered on during low power mode. + * 0b1..High speed crystal is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_XTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTALHF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTALHF_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP-SLEEP (always shut down + * during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..System PLL (also refered as PLL0) is powered on during low power mode. + * 0b1..System PLL (also refered as PLL0) is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP-SLEEP (always shut down + * during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode. + * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..USB Full Speed phy is powered on during low power mode. + * 0b1..USB Full Speed phy is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls Analog Comparator power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN). + * 0b0..Analog Comparator is powered on during low power mode. + * 0b1..Analog Comparator is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) +/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN. + * 0b0..Memories LDO is powered on during low power mode. + * 0b1..Memories LDO is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_MASK (0x40000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_SHIFT (18U) +/*! PDEN_LDOEFUSEPROG - Controls USB high speed LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..USB high speed LDO is powered on during low power mode. + * 0b1..USB high speed LDO is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_MASK (0x100000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_SHIFT (20U) +/*! PDEN_LDOXTALHF - Controls High speed crystal LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..High speed crystal LDO is powered on during low power mode. + * 0b1..High speed crystal LDO is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) +/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..Flash NV (high voltage) is powered on during low power mode. + * 0b1..Flash NV (high voltage) is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP-SLEEP (PLL0 Spread + * Spectrum is always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode. + * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) +#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) +/*! PDEN_ROM - Controls ROM power during DEEP-SLEEP (ROM is always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..ROM is powered on during low power mode. + * 0b1..ROM is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_HSCMP0_MASK (0x2000000U) +#define PMC_PDSLEEPCFG0_PDEN_HSCMP0_SHIFT (25U) +/*! PDEN_HSCMP0 - Controls High Speed Comparator0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..High Speed Comparator is powered on during low power mode. + * 0b1..High Speed Comparator is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP0_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_HSCMP1_MASK (0x4000000U) +#define PMC_PDSLEEPCFG0_PDEN_HSCMP1_SHIFT (26U) +/*! PDEN_HSCMP1 - Controls High Speed Comparator1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..High Speed Comparator is powered on during low power mode. + * 0b1..High Speed Comparator is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP1_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_HSCMP2_MASK (0x8000000U) +#define PMC_PDSLEEPCFG0_PDEN_HSCMP2_SHIFT (27U) +/*! PDEN_HSCMP2 - Controls High Speed Comparator2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..High Speed Comparator is powered on during low power mode. + * 0b1..High Speed Comparator is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP2_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP2_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_OPAMP0_MASK (0x10000000U) +#define PMC_PDSLEEPCFG0_PDEN_OPAMP0_SHIFT (28U) +/*! PDEN_OPAMP0 - Controls Operational Amplifier0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..Operational Amplifier is powered on during low power mode. + * 0b1..Operational Amplifier is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP0_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_OPAMP1_MASK (0x20000000U) +#define PMC_PDSLEEPCFG0_PDEN_OPAMP1_SHIFT (29U) +/*! PDEN_OPAMP1 - Controls Operational Amplifier1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..Operational Amplifier is powered on during low power mode. + * 0b1..Operational Amplifier is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP1_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_OPAMP2_MASK (0x40000000U) +#define PMC_PDSLEEPCFG0_PDEN_OPAMP2_SHIFT (30U) +/*! PDEN_OPAMP2 - Controls Operational Amplifier2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..Operational Amplifier is powered on during low power mode. + * 0b1..Operational Amplifier is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP2_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP2_MASK) + +#define PMC_PDSLEEPCFG0_PDEN_VREF_MASK (0x80000000U) +#define PMC_PDSLEEPCFG0_PDEN_VREF_SHIFT (31U) +/*! PDEN_VREF - Controls VREF power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN). + * 0b0..VREF is powered on during low power mode. + * 0b1..VREF is powered off during low power mode. + */ +#define PMC_PDSLEEPCFG0_PDEN_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_VREF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_VREF_MASK) +/*! @} */ + +/*! @name SRAMRETCTRL - Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMRETCTRL_RETEN_RAM_X0_MASK (0x1U) +#define PMC_SRAMRETCTRL_RETEN_RAM_X0_SHIFT (0U) +/*! RETEN_RAM_X0 - Controls RAM_X0 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_X0(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_X0_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_X0_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_00_MASK (0x2U) +#define PMC_SRAMRETCTRL_RETEN_RAM_00_SHIFT (1U) +/*! RETEN_RAM_00 - Controls RAM_00 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_00(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_00_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_00_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_01_MASK (0x4U) +#define PMC_SRAMRETCTRL_RETEN_RAM_01_SHIFT (2U) +/*! RETEN_RAM_01 - Controls RAM_01 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_01(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_01_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_01_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_02_MASK (0x8U) +#define PMC_SRAMRETCTRL_RETEN_RAM_02_SHIFT (3U) +/*! RETEN_RAM_02 - Controls RAM_02 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_02(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_02_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_02_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_03_MASK (0x10U) +#define PMC_SRAMRETCTRL_RETEN_RAM_03_SHIFT (4U) +/*! RETEN_RAM_03 - Controls RAM_03 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_03(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_03_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_03_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_10_MASK (0x20U) +#define PMC_SRAMRETCTRL_RETEN_RAM_10_SHIFT (5U) +/*! RETEN_RAM_10 - Controls RAM_10 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_10(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_10_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_10_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_20_MASK (0x40U) +#define PMC_SRAMRETCTRL_RETEN_RAM_20_SHIFT (6U) +/*! RETEN_RAM_20 - Controls RAM_20 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_20(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_20_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_20_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_30_MASK (0x80U) +#define PMC_SRAMRETCTRL_RETEN_RAM_30_SHIFT (7U) +/*! RETEN_RAM_30 - Controls RAM_30 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_30(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_30_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_30_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_40_MASK (0x100U) +#define PMC_SRAMRETCTRL_RETEN_RAM_40_SHIFT (8U) +/*! RETEN_RAM_40 - Controls RAM_40 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_40(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_40_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_40_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_41_MASK (0x200U) +#define PMC_SRAMRETCTRL_RETEN_RAM_41_SHIFT (9U) +/*! RETEN_RAM_41 - Controls RAM_41 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_41(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_41_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_41_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_42_MASK (0x400U) +#define PMC_SRAMRETCTRL_RETEN_RAM_42_SHIFT (10U) +/*! RETEN_RAM_42 - Controls RAM_42 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_42(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_42_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_42_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_43_MASK (0x800U) +#define PMC_SRAMRETCTRL_RETEN_RAM_43_SHIFT (11U) +/*! RETEN_RAM_43 - Controls RAM_43 power down modes during low power modes. + * 0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is + * (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM + * instance is in 'Shutdown mode' (In this mode there is no data retention). + * 0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_43(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_43_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_43_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_MASK (0x1000U) +#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_SHIFT (12U) +/*! RETEN_RAM_FLASHLPCACHE - Controls Embedded Flash Cache SRAM power down modes during low power modes. + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_MASK) + +#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_MASK (0x2000U) +#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_SHIFT (13U) +/*! RETEN_RAM_FLEXSPILPCACHE - Controls FlexSPI Cache SRAM power down modes during low power modes. + */ +#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_MASK) + +#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_MASK (0x4000U) +#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_SHIFT (14U) +/*! RETEN_H2PREG_FLEXSPI - Controls FlexSPI Dual Port Register Files power down modes during deep + * sleep. In power-down and deep power-down modes, FlexSPI Dual Port Register Files are always + * shutoff. + * 0b0..DEEP-SLEEP: all FlexSPI dual port register files keep the configuration they had before entering + * DEEP-SLEEP. POWER-DOWN and DEEP-POWER-DOWN: all FlexSPI dual port register instances are shut off (In this mode + * there is no data retention). + * 0b1..DEEP-SLEEP: all FlexSPI Dual Port egister files are in 'Power Down' mode (In this mode there is data + * retention). POWER-DOWN and DEEP-POWER-DOWN: all FlexSPI dual port register instances are shut off (In this + * mode there is no data retention). + */ +#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_SHIFT)) & PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Power configuration 0 */ +/*! @{ */ + +#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) +#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) +/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. + * 0b0..DCDC is powered. + * 0b1..DCDC is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) + +#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) +#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) +/*! PDEN_BIAS - Controls power to . + * 0b0..Analog Bias is powered. + * 0b1..Analog Bias is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) + +#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) +#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) +/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD_CORE). + * 0b0..BOD_CORE is powered. + * 0b1..BOD_CORE is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) + +#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN_SHIFT (3U) +/*! PDEN_BODVDDMAIN - Controls power to VDDMAIN Brown Out Detector (BOD_VDDMAIN). + * 0b0..BOD_VDDMAIN is powered. + * 0b1..BOD_VDDMAIN is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVDDMAIN_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVDDMAIN_MASK) + +#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) +#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) +/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz + * and 96 MHz clocks are derived from this FRO. + * 0b0..FRO 192MHz is powered. + * 0b1..FRO 192MHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) + +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTALHF_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTALHF_SHIFT (8U) +/*! PDEN_XTALHF - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTALHF_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTALHF_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) +#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) +/*! PDEN_LDOMEM - Controls power to Memories LDO. + * 0b0..Memories LDO is powered. + * 0b1..Memories LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_SHIFT (18U) +/*! PDEN_LDOEFUSEPROG - Controls power to eFUSE Programming LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXTALHF_SHIFT (20U) +/*! PDEN_LDOXTALHF - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXTALHF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXTALHF_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) +/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. + * 0b0..Flash NV LDO is powered. + * 0b1..Flash NV LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) + +#define PMC_PDRUNCFG0_PDEN_HSCMP0_MASK (0x2000000U) +#define PMC_PDRUNCFG0_PDEN_HSCMP0_SHIFT (25U) +/*! PDEN_HSCMP0 - Controls power to High Speed Comparator0 + * 0b0..High Speed Comparator0 is powered on. + * 0b1..High Speed Comparator0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP0_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP0_MASK) + +#define PMC_PDRUNCFG0_PDEN_HSCMP1_MASK (0x4000000U) +#define PMC_PDRUNCFG0_PDEN_HSCMP1_SHIFT (26U) +/*! PDEN_HSCMP1 - Controls power to High Speed Comparator1 + * 0b0..High Speed Comparator1 is powered on + * 0b1..High Speed Comparator1 is powered down + */ +#define PMC_PDRUNCFG0_PDEN_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP1_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP1_MASK) + +#define PMC_PDRUNCFG0_PDEN_HSCMP2_MASK (0x8000000U) +#define PMC_PDRUNCFG0_PDEN_HSCMP2_SHIFT (27U) +/*! PDEN_HSCMP2 - Controls power to High Speed Comparator2 + * 0b0..High Speed Comparator2 is powered on + * 0b1..High Speed Comparator2 is powered down + */ +#define PMC_PDRUNCFG0_PDEN_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP2_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP2_MASK) + +#define PMC_PDRUNCFG0_PDEN_OPAMP0_MASK (0x10000000U) +#define PMC_PDRUNCFG0_PDEN_OPAMP0_SHIFT (28U) +/*! PDEN_OPAMP0 - Controls power to Operational Amplifier0 + * 0b0..Operational Amplifier0 is powered on. + * 0b1..Operational Amplifier0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP0_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP0_MASK) + +#define PMC_PDRUNCFG0_PDEN_OPAMP1_MASK (0x20000000U) +#define PMC_PDRUNCFG0_PDEN_OPAMP1_SHIFT (29U) +/*! PDEN_OPAMP1 - Controls power to Operational Amplifier1 + * 0b0..Operational Amplifier1 is powered on + * 0b1..Operational Amplifier1 is powered down + */ +#define PMC_PDRUNCFG0_PDEN_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP1_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP1_MASK) + +#define PMC_PDRUNCFG0_PDEN_OPAMP2_MASK (0x40000000U) +#define PMC_PDRUNCFG0_PDEN_OPAMP2_SHIFT (30U) +/*! PDEN_OPAMP2 - Controls power to Operational Amplifier2 + * 0b0..Operational Amplifier2 is powered on + * 0b1..Operational Amplifier2 is powered down + */ +#define PMC_PDRUNCFG0_PDEN_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP2_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP2_MASK) + +#define PMC_PDRUNCFG0_PDEN_VREF_MASK (0x80000000U) +#define PMC_PDRUNCFG0_PDEN_VREF_SHIFT (31U) +/*! PDEN_VREF - Controls power to VREF module + * 0b0..VREF is powered on. + * 0b1..VREF is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_VREF_SHIFT)) & PMC_PDRUNCFG0_PDEN_VREF_MASK) +/*! @} */ + +/*! @name PDRUNCFG1 - Power configuration 1 */ +/*! @{ */ + +#define PMC_PDRUNCFG1_PDEN_CMPBIAS_MASK (0x1U) +#define PMC_PDRUNCFG1_PDEN_CMPBIAS_SHIFT (0U) +/*! PDEN_CMPBIAS - Controls power of Comparators 1/2/3 bias. + * 0b0..Comparators 1/2/3 bias is powered. + * 0b1..Comparators 1/2/3 bias is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_CMPBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_CMPBIAS_SHIFT)) & PMC_PDRUNCFG1_PDEN_CMPBIAS_MASK) + +#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_MASK (0x2U) +#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_SHIFT (1U) +/*! PDEN_HSCMP0_DAC - Controls power to High Speed Comparator0 DAC. + * 0b0..High Speed Comparator0 DAC is powered. + * 0b1..High Speed Comparator0 DAC is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_MASK) + +#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_MASK (0x4U) +#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_SHIFT (2U) +/*! PDEN_HSCMP1_DAC - Controls power to High Speed Comparator1 DAC. + * 0b0..High Speed Comparator1 DAC is powered. + * 0b1..High Speed Comparator1 DAC is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_MASK) + +#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_MASK (0x8U) +#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_SHIFT (3U) +/*! PDEN_HSCMP2_DAC - Controls power to High Speed Comparator2 DAC. + * 0b0..High Speed Comparator2 DAC is powered. + * 0b1..High Speed Comparator2 DAC is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_MASK) + +#define PMC_PDRUNCFG1_PDEN_DAC0_MASK (0x10U) +#define PMC_PDRUNCFG1_PDEN_DAC0_SHIFT (4U) +/*! PDEN_DAC0 - Controls power to DAC0. + * 0b0..DAC0 is powered. + * 0b1..DAC0 is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC0_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC0_MASK) + +#define PMC_PDRUNCFG1_PDEN_DAC1_MASK (0x20U) +#define PMC_PDRUNCFG1_PDEN_DAC1_SHIFT (5U) +/*! PDEN_DAC1 - Controls power to DAC1. + * 0b0..DAC1 is powered. + * 0b1..DAC1 is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC1_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC1_MASK) + +#define PMC_PDRUNCFG1_PDEN_DAC2_MASK (0x40U) +#define PMC_PDRUNCFG1_PDEN_DAC2_SHIFT (6U) +/*! PDEN_DAC2 - Controls power to DAC2. + * 0b0..DAC2 is powered. + * 0b1..DAC2 is powered down. + */ +#define PMC_PDRUNCFG1_PDEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC2_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC2_MASK) + +#define PMC_PDRUNCFG1_STOPEN_DAC0_MASK (0x80U) +#define PMC_PDRUNCFG1_STOPEN_DAC0_SHIFT (7U) +/*! STOPEN_DAC0 - Controls DAC0 Stop mode. + * 0b0..DAC0 Stop mode is disabled. + * 0b1..DAC0 Stop mode is enabled. + */ +#define PMC_PDRUNCFG1_STOPEN_DAC0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC0_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC0_MASK) + +#define PMC_PDRUNCFG1_STOPEN_DAC1_MASK (0x100U) +#define PMC_PDRUNCFG1_STOPEN_DAC1_SHIFT (8U) +/*! STOPEN_DAC1 - Controls DAC1 Stop mode. + * 0b0..DAC1 Stop mode is disabled. + * 0b1..DAC1 Stop mode is enabled. + */ +#define PMC_PDRUNCFG1_STOPEN_DAC1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC1_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC1_MASK) + +#define PMC_PDRUNCFG1_STOPEN_DAC2_MASK (0x200U) +#define PMC_PDRUNCFG1_STOPEN_DAC2_SHIFT (9U) +/*! STOPEN_DAC2 - Controls DAC2 Stop mode. + * 0b0..DAC2 Stop mode is disabled. + * 0b1..DAC2 Stop mode is enabled. + */ +#define PMC_PDRUNCFG1_STOPEN_DAC2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC2_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC2_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Power configuration set 0 */ +/*! @{ */ + +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET1 - Power configuration set 1 */ +/*! @{ */ + +#define PMC_PDRUNCFGSET1_PDRUNCFGSET1_MASK (0x3FFU) +#define PMC_PDRUNCFGSET1_PDRUNCFGSET1_SHIFT (0U) +/*! PDRUNCFGSET1 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGSET1_PDRUNCFGSET1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET1_PDRUNCFGSET1_SHIFT)) & PMC_PDRUNCFGSET1_PDRUNCFGSET1_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Power configuration clear 0 */ +/*! @{ */ + +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR1 - Power configuration clear 1 */ +/*! @{ */ + +#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_MASK (0x3FFU) +#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_SHIFT (0U) +/*! PDRUNCFGCLR1 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_SHIFT)) & PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_MASK) +/*! @} */ + +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) +/*! @} */ + +/*! @name SRAMCTRL0 - RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode */ +/*! @{ */ + +#define PMC_SRAMCTRL0_RAM_X0_LS_MASK (0x1U) +#define PMC_SRAMCTRL0_RAM_X0_LS_SHIFT (0U) +/*! RAM_X0_LS - RAM_X0 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_X0_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_X0_DSB_MASK (0x2U) +#define PMC_SRAMCTRL0_RAM_X0_DSB_SHIFT (1U) +/*! RAM_X0_DSB - RAM_X0 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_X0_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_X0_DSBDEL_MASK (0x4U) +#define PMC_SRAMCTRL0_RAM_X0_DSBDEL_SHIFT (2U) +/*! RAM_X0_DSBDEL - RAM_X0 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_X0_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_X0_LSDEL_MASK (0x8U) +#define PMC_SRAMCTRL0_RAM_X0_LSDEL_SHIFT (3U) +/*! RAM_X0_LSDEL - RAM_X0 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_X0_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_00_LS_MASK (0x10U) +#define PMC_SRAMCTRL0_RAM_00_LS_SHIFT (4U) +/*! RAM_00_LS - RAM_00 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_00_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_00_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_00_DSB_MASK (0x20U) +#define PMC_SRAMCTRL0_RAM_00_DSB_SHIFT (5U) +/*! RAM_00_DSB - RAM_00 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_00_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_00_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_00_DSBDEL_MASK (0x40U) +#define PMC_SRAMCTRL0_RAM_00_DSBDEL_SHIFT (6U) +/*! RAM_00_DSBDEL - RAM_00 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_00_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_00_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_00_LSDEL_MASK (0x80U) +#define PMC_SRAMCTRL0_RAM_00_LSDEL_SHIFT (7U) +/*! RAM_00_LSDEL - RAM_00 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_00_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_00_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_01_LS_MASK (0x100U) +#define PMC_SRAMCTRL0_RAM_01_LS_SHIFT (8U) +/*! RAM_01_LS - RAM_01 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_01_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_01_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_01_DSB_MASK (0x200U) +#define PMC_SRAMCTRL0_RAM_01_DSB_SHIFT (9U) +/*! RAM_01_DSB - RAM_01 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_01_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_01_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_01_DSBDEL_MASK (0x400U) +#define PMC_SRAMCTRL0_RAM_01_DSBDEL_SHIFT (10U) +/*! RAM_01_DSBDEL - RAM_01 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_01_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_01_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_01_LSDEL_MASK (0x800U) +#define PMC_SRAMCTRL0_RAM_01_LSDEL_SHIFT (11U) +/*! RAM_01_LSDEL - RAM_01 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_01_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_01_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_02_LS_MASK (0x1000U) +#define PMC_SRAMCTRL0_RAM_02_LS_SHIFT (12U) +/*! RAM_02_LS - RAM_02 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_02_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_02_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_02_DSB_MASK (0x2000U) +#define PMC_SRAMCTRL0_RAM_02_DSB_SHIFT (13U) +/*! RAM_02_DSB - RAM_02 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_02_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_02_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_02_DSBDEL_MASK (0x4000U) +#define PMC_SRAMCTRL0_RAM_02_DSBDEL_SHIFT (14U) +/*! RAM_02_DSBDEL - RAM_02 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_02_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_02_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_02_LSDEL_MASK (0x8000U) +#define PMC_SRAMCTRL0_RAM_02_LSDEL_SHIFT (15U) +/*! RAM_02_LSDEL - RAM_02 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_02_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_02_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_03_LS_MASK (0x10000U) +#define PMC_SRAMCTRL0_RAM_03_LS_SHIFT (16U) +/*! RAM_03_LS - RAM_03 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_03_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_03_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_03_DSB_MASK (0x20000U) +#define PMC_SRAMCTRL0_RAM_03_DSB_SHIFT (17U) +/*! RAM_03_DSB - RAM_03 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_03_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_03_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_03_DSBDEL_MASK (0x40000U) +#define PMC_SRAMCTRL0_RAM_03_DSBDEL_SHIFT (18U) +/*! RAM_03_DSBDEL - RAM_03 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_03_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_03_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_03_LSDEL_MASK (0x80000U) +#define PMC_SRAMCTRL0_RAM_03_LSDEL_SHIFT (19U) +/*! RAM_03_LSDEL - RAM_03 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_03_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_03_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_10_LS_MASK (0x100000U) +#define PMC_SRAMCTRL0_RAM_10_LS_SHIFT (20U) +/*! RAM_10_LS - RAM_10 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_10_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_10_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_10_DSB_MASK (0x200000U) +#define PMC_SRAMCTRL0_RAM_10_DSB_SHIFT (21U) +/*! RAM_10_DSB - RAM_10 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_10_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_10_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_10_DSBDEL_MASK (0x400000U) +#define PMC_SRAMCTRL0_RAM_10_DSBDEL_SHIFT (22U) +/*! RAM_10_DSBDEL - RAM_10 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_10_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_10_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_10_LSDEL_MASK (0x800000U) +#define PMC_SRAMCTRL0_RAM_10_LSDEL_SHIFT (23U) +/*! RAM_10_LSDEL - RAM_10 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_10_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_10_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_20_LS_MASK (0x1000000U) +#define PMC_SRAMCTRL0_RAM_20_LS_SHIFT (24U) +/*! RAM_20_LS - RAM_20 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_20_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_20_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_20_DSB_MASK (0x2000000U) +#define PMC_SRAMCTRL0_RAM_20_DSB_SHIFT (25U) +/*! RAM_20_DSB - RAM_20 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_20_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_20_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_20_DSBDEL_MASK (0x4000000U) +#define PMC_SRAMCTRL0_RAM_20_DSBDEL_SHIFT (26U) +/*! RAM_20_DSBDEL - RAM_20 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_20_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_20_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_20_LSDEL_MASK (0x8000000U) +#define PMC_SRAMCTRL0_RAM_20_LSDEL_SHIFT (27U) +/*! RAM_20_LSDEL - RAM_20 Sleep mode disable. + */ +#define PMC_SRAMCTRL0_RAM_20_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_20_LSDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_30_LS_MASK (0x10000000U) +#define PMC_SRAMCTRL0_RAM_30_LS_SHIFT (28U) +/*! RAM_30_LS - RAM_30 Light Sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_30_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_30_LS_MASK) + +#define PMC_SRAMCTRL0_RAM_30_DSB_MASK (0x20000000U) +#define PMC_SRAMCTRL0_RAM_30_DSB_SHIFT (29U) +/*! RAM_30_DSB - RAM_30 Deep sleep mode. + */ +#define PMC_SRAMCTRL0_RAM_30_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_30_DSB_MASK) + +#define PMC_SRAMCTRL0_RAM_30_DSBDEL_MASK (0x40000000U) +#define PMC_SRAMCTRL0_RAM_30_DSBDEL_SHIFT (30U) +/*! RAM_30_DSBDEL - RAM_30 Deep sleep delayed. + */ +#define PMC_SRAMCTRL0_RAM_30_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_30_DSBDEL_MASK) + +#define PMC_SRAMCTRL0_RAM_30_LSDEL_MASK (0x80000000U) +#define PMC_SRAMCTRL0_RAM_30_LSDEL_SHIFT (31U) +/*! RAM_30_LSDEL - RAM_30 Light Sleep mode delayed. + */ +#define PMC_SRAMCTRL0_RAM_30_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_30_LSDEL_MASK) +/*! @} */ + +/*! @name SRAMCTRL1 - RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode */ +/*! @{ */ + +#define PMC_SRAMCTRL1_RAM_40_LS_MASK (0x1U) +#define PMC_SRAMCTRL1_RAM_40_LS_SHIFT (0U) +/*! RAM_40_LS - RAM_40 Light Sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_40_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_40_LS_MASK) + +#define PMC_SRAMCTRL1_RAM_40_DSB_MASK (0x2U) +#define PMC_SRAMCTRL1_RAM_40_DSB_SHIFT (1U) +/*! RAM_40_DSB - RAM_40 Deep sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_40_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_40_DSB_MASK) + +#define PMC_SRAMCTRL1_RAM_40_DSBDEL_MASK (0x4U) +#define PMC_SRAMCTRL1_RAM_40_DSBDEL_SHIFT (2U) +/*! RAM_40_DSBDEL - RAM_40 Deep sleep delayed. + */ +#define PMC_SRAMCTRL1_RAM_40_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_40_DSBDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_40_LSDEL_MASK (0x8U) +#define PMC_SRAMCTRL1_RAM_40_LSDEL_SHIFT (3U) +/*! RAM_40_LSDEL - RAM_40 Sleep mode disable. + */ +#define PMC_SRAMCTRL1_RAM_40_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_40_LSDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_41_LS_MASK (0x10U) +#define PMC_SRAMCTRL1_RAM_41_LS_SHIFT (4U) +/*! RAM_41_LS - RAM_41 Light Sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_41_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_41_LS_MASK) + +#define PMC_SRAMCTRL1_RAM_41_DSB_MASK (0x20U) +#define PMC_SRAMCTRL1_RAM_41_DSB_SHIFT (5U) +/*! RAM_41_DSB - RAM_41 Deep sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_41_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_41_DSB_MASK) + +#define PMC_SRAMCTRL1_RAM_41_DSBDEL_MASK (0x40U) +#define PMC_SRAMCTRL1_RAM_41_DSBDEL_SHIFT (6U) +/*! RAM_41_DSBDEL - RAM_41 Deep sleep delayed. + */ +#define PMC_SRAMCTRL1_RAM_41_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_41_DSBDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_41_LSDEL_MASK (0x80U) +#define PMC_SRAMCTRL1_RAM_41_LSDEL_SHIFT (7U) +/*! RAM_41_LSDEL - RAM_41 Sleep mode disable. + */ +#define PMC_SRAMCTRL1_RAM_41_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_41_LSDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_42_LS_MASK (0x100U) +#define PMC_SRAMCTRL1_RAM_42_LS_SHIFT (8U) +/*! RAM_42_LS - RAM_42 Light Sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_42_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_42_LS_MASK) + +#define PMC_SRAMCTRL1_RAM_42_DSB_MASK (0x200U) +#define PMC_SRAMCTRL1_RAM_42_DSB_SHIFT (9U) +/*! RAM_42_DSB - RAM_42 Deep sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_42_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_42_DSB_MASK) + +#define PMC_SRAMCTRL1_RAM_42_DSBDEL_MASK (0x400U) +#define PMC_SRAMCTRL1_RAM_42_DSBDEL_SHIFT (10U) +/*! RAM_42_DSBDEL - RAM_42 Deep sleep delayed. + */ +#define PMC_SRAMCTRL1_RAM_42_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_42_DSBDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_42_LSDEL_MASK (0x800U) +#define PMC_SRAMCTRL1_RAM_42_LSDEL_SHIFT (11U) +/*! RAM_42_LSDEL - RAM_42 Sleep mode disable. + */ +#define PMC_SRAMCTRL1_RAM_42_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_42_LSDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_43_LS_MASK (0x1000U) +#define PMC_SRAMCTRL1_RAM_43_LS_SHIFT (12U) +/*! RAM_43_LS - RAM_43 Light Sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_43_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_43_LS_MASK) + +#define PMC_SRAMCTRL1_RAM_43_DSB_MASK (0x2000U) +#define PMC_SRAMCTRL1_RAM_43_DSB_SHIFT (13U) +/*! RAM_43_DSB - RAM_43 Deep sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_43_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_43_DSB_MASK) + +#define PMC_SRAMCTRL1_RAM_43_DSBDEL_MASK (0x4000U) +#define PMC_SRAMCTRL1_RAM_43_DSBDEL_SHIFT (14U) +/*! RAM_43_DSBDEL - RAM_43 Deep sleep delayed. + */ +#define PMC_SRAMCTRL1_RAM_43_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_43_DSBDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_43_LSDEL_MASK (0x8000U) +#define PMC_SRAMCTRL1_RAM_43_LSDEL_SHIFT (15U) +/*! RAM_43_LSDEL - RAM_43 Sleep mode disable. + */ +#define PMC_SRAMCTRL1_RAM_43_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_43_LSDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_MASK (0x10000U) +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT (16U) +/*! RAM_FLASHLPCACHE_LS - Flash Cache RAM Light Sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_MASK) + +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_MASK (0x20000U) +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_SHIFT (17U) +/*! RAM_FLASHLPCACHE_DSB - Flash Cache RAM Deep sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_MASK) + +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_MASK (0x40000U) +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_SHIFT (18U) +/*! RAM_FLASHLPCACHE_DSBDEL - Flash Cache RAM Deep sleep delayed. + */ +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_MASK (0x80000U) +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_SHIFT (19U) +/*! RAM_FLASHLPCACHE_LSDEL - Flash Cache RAM Sleep mode disable. + */ +#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_MASK (0x100000U) +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT (20U) +/*! RAM_FLEXSPILPCACHE_LS - Flex SPI Cache RAM Light Sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_MASK) + +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_MASK (0x200000U) +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_SHIFT (21U) +/*! RAM_FLEXSPILPCACHE_DSB - Flex SPI Cache RAM Deep sleep mode. + */ +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_MASK) + +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_MASK (0x400000U) +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_SHIFT (22U) +/*! RAM_FLEXSPILPCACHE_DSBDEL - Flex SPI Cache RAM Deep sleep delayed. + */ +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_MASK) + +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_MASK (0x800000U) +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_SHIFT (23U) +/*! RAM_FLEXSPILPCACHE_LSDEL - Flex SPI Cache RAM Sleep mode disable. + */ +#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Output Base, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output Format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Temporary Base, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temporary Format, offset: 0xC */ + __IO uint32_t INABASE; /**< Input A Base, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A Format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Input B Base, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B Format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< Control, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Coprocessor Pre-scale, offset: 0x108 */ + __IO uint32_t MISC; /**< Miscellaneous, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic Input Y, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic Input Z, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Error Status, offset: 0x18C */ + __IO uint32_t INTREN; /**< Interrupt Enable, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< Interrupt Status, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[16]; /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[8]; /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Output Base */ +/*! @{ */ + +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +/*! OUTBASE - Base address register for the output region + */ +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output Format */ +/*! @{ */ + +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +/*! OUT_FORMATINT - Output Internal Format + */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +/*! OUT_FORMATEXT - Output External Format + */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +/*! OUT_SCALER - Output Scaler Value + */ +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Temporary Base */ +/*! @{ */ + +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +/*! TMPBASE - Base address register for the temporary region + */ +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temporary Format */ +/*! @{ */ + +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +/*! TMP_FORMATINT - Temporary Internal Format + */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +/*! TMP_FORMATEXT - Temporary External Format + */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +/*! TMP_SCALER - Temporary Scaler Value + */ +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Input A Base */ +/*! @{ */ + +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +/*! INABASE - Input A Base + */ +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A Format */ +/*! @{ */ + +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +/*! INA_FORMATINT - Input A Internal Format + */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) + +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +/*! INA_FORMATEXT - Input A External Format + */ +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) + +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +/*! INA_SCALER - Input A Scaler Value + */ +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Input B Base */ +/*! @{ */ + +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +/*! INBBASE - Input B Base + */ +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B Format */ +/*! @{ */ + +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +/*! INB_FORMATINT - Input B Internal Format + */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) + +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +/*! INB_FORMATEXT - Input B External Format + */ +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) + +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +/*! INB_SCALER - Input B Scaler Value + */ +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - Control */ +/*! @{ */ + +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +/*! DECODE_OPCODE - Decode Opcode + */ +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) + +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +/*! DECODE_MACHINE - Decode Machine + */ +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) + +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +/*! INST_BUSY - Instruction Busy + */ +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length */ +/*! @{ */ + +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +/*! INST_LENGTH - Instruction Length + */ +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Coprocessor Pre-scale */ +/*! @{ */ + +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +/*! CPPRE_IN - Input + */ +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) + +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +/*! CPPRE_OUT - Output + */ +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +/*! CPPRE_SAT - Saturation + * 0b0..No saturation + * 0b1..Forces sub-32 bit saturation + */ +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +/*! CPPRE_SAT8 - Saturation 8 + * 0b0..8 bits + * 0b1..16 bits + */ +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Miscellaneous */ +/*! @{ */ + +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +/*! INST_MISC - For Matrix : Used for scaling factor + */ +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory */ +/*! @{ */ + +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +/*! CURSORY - Cursory Mode + * 0b0..Disable Cursory mode + * 0b1..Enable Cursory Mode + */ +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X */ +/*! @{ */ + +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +/*! CORDIC_X - Cordic Input x + */ +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic Input Y */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +/*! CORDIC_Y - Cordic Input y + */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic Input Z */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +/*! CORDIC_Z - Cordic Input z + */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Error Status */ +/*! @{ */ + +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +/*! OVERFLOW - Floating Point Overflow + * 0b0..No Error + * 0b1..Error on Floating Point Overflow + */ +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +/*! NAN - Floating Point NaN + * 0b0..No Error + * 0b1..Error on Floating Point NaN + */ +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) + +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +/*! FIXEDOVERFLOW - Fixed Point Overflow + * 0b0..No Error + * 0b1..Error on Fixed Point Overflow + */ +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +/*! UNDERFLOW - Underflow + * 0b0..No Error + * 0b1..Error on Underflow + */ +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +/*! BUSERROR - Bus Error + * 0b0..No Error + * 0b1..Error on Bus + */ +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - Interrupt Enable */ +/*! @{ */ + +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +/*! INTR_OFLOW - Interrupt Floating Point Overflow + * 0b0..Disable + * 0b1..Enable interrupt on floating point overflow + */ +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +/*! INTR_NAN - Interrupt Floating Point NaN + * 0b0..Disable + * 0b1..Enable interrupt on floating point NaN + */ +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) + +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +/*! INTR_FIXED - Interrupt on Fixed Point Overflow + * 0b0..Disable + * 0b1..Enable interrupt on fixed point overflow + */ +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) + +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +/*! INTR_UFLOW - Interrupt on Subnormal Truncation + * 0b0..Disable + * 0b1..Enable interrupt on subnormal truncation + */ +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +/*! INTR_BERR - Interrupt on AHBM Bus Error + * 0b0..Disable + * 0b1..Enable interrupt on AHBM Bus Error + */ +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) + +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +/*! INTR_COMP - Interrupt on Instruction Completion + * 0b0..Disable + * 0b1..Enable interrupt on instruction completion + */ +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable */ +/*! @{ */ + +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +/*! EVENT_OFLOW - Event Trigger on Floating Point Overflow + * 0b0..Disable + * 0b1..Enable event trigger on Floating point overflow + */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +/*! EVENT_NAN - Event Trigger on Floating Point NaN + * 0b0..Disable + * 0b1..Enable event trigger on floating point NaN + */ +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) + +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +/*! EVENT_FIXED - Event Trigger on Fixed Point Overflow + * 0b0..Disable + * 0b1..Enable event trigger on fixed point overflow + */ +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) + +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +/*! EVENT_UFLOW - Event Trigger on Subnormal Truncation + * 0b0..Disable + * 0b1..Enable event trigger on subnormal truncation + */ +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +/*! EVENT_BERR - Event Trigger on AHBM Bus Error + * 0b0..Disable + * 0b1..Enable event trigger on AHBM bus error + */ +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) + +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +/*! EVENT_COMP - Event Trigger on Instruction Completion + * 0b0..Disable + * 0b1..Enable event trigger on instruction completion + */ +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - Interrupt Status */ +/*! @{ */ + +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +/*! INTR_STAT - Interrupt Status + * 0b0..No new interrupt + * 0b1..Interrupt captured + */ +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose Register Bank n */ +/*! @{ */ + +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +/*! GPREG - General Purpose Register Bank + */ +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_GPREG */ +#define POWERQUAD_GPREG_COUNT (16U) + +/*! @name COMPREGS_COMPREG - Compute Register Bank n */ +/*! @{ */ + +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +/*! COMPREG - Compute Register Bank + */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { POWERQUAD_IRQn } + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ + uint8_t RESERVED_0[80]; + __IO uint32_t ERR; /**< Error status register, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __IO uint32_t SR_XOM[3]; /**< XOM enable for sub region 0..XOM enable for sub region 2, array offset: 0x100, array step: 0x4 */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ + +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Enables PRINCE encryption for flash programming. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ + +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, and SR_ENABLE0 are writable. + * 0b1..Enabled. IV_LSB0, IV_MSB0, and SR_ENABLE0 are not writable. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, and SR_ENABLE1 are writable. + * 0b1..Enabled. IV_LSB1, IV_MSB1, and SR_ENABLE1 are not writable. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, and SR_ENABLE2 are writable. + * 0b1..Enabled. IV_LSB2, IV_MSB2, and SR_ENABLE2 are not writable. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + * 0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region. + * 0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region. + */ +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + * 0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region. + * 0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region. + */ +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + * 0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region. + * 0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region. + */ +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + +/*! @name ERR - Error status register */ +/*! @{ */ + +#define PRINCE_ERR_ERRSTAT_MASK (0x1U) +#define PRINCE_ERR_ERRSTAT_SHIFT (0U) +/*! ERRSTAT - PRINCE Error Status. This bit is write-1 to clear. + * 0b0..No PRINCE error. + * 0b1..Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE[EN]=1. + */ +#define PRINCE_ERR_ERRSTAT(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ERR_ERRSTAT_SHIFT)) & PRINCE_ERR_ERRSTAT_MASK) +/*! @} */ + +/*! @name SR_XOMX_SR_XOM - XOM enable for sub region 0..XOM enable for sub region 2 */ +/*! @{ */ + +#define PRINCE_SR_XOMX_SR_XOM_XOM_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_XOMX_SR_XOM_XOM_EN_SHIFT (0U) +/*! XOM_EN - XOM enable + * 0b00000000000000000000000000000000..A 0 in bit n means that decryption of data associated with sub-region n is done for both data and code read transactions. + * 0b00000000000000000000000000000001..A 1 in bit n means that decryption of data associated with sub-region n is done for code fetch transactions only. + */ +#define PRINCE_SR_XOMX_SR_XOM_XOM_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_XOMX_SR_XOM_XOM_EN_SHIFT)) & PRINCE_SR_XOMX_SR_XOM_XOM_EN_MASK) +/*! @} */ + +/* The count of PRINCE_SR_XOMX_SR_XOM */ +#define PRINCE_SR_XOMX_SR_XOM_COUNT (3U) + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PRINCE0 base address */ + #define PRINCE0_BASE (0x50035000u) + /** Peripheral PRINCE0 base address */ + #define PRINCE0_BASE_NS (0x40035000u) + /** Peripheral PRINCE0 base pointer */ + #define PRINCE0 ((PRINCE_Type *)PRINCE0_BASE) + /** Peripheral PRINCE0 base pointer */ + #define PRINCE0_NS ((PRINCE_Type *)PRINCE0_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE0_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE0 } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE0_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE0_NS } +#else + /** Peripheral PRINCE0 base address */ + #define PRINCE0_BASE (0x40035000u) + /** Peripheral PRINCE0 base pointer */ + #define PRINCE0 ((PRINCE_Type *)PRINCE0_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE0_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE0 } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control, offset: 0x0 */ + __I uint32_t ORR; /**< Operation Result, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + __I uint32_t AR; /**< Allow, offset: 0xC */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x10 */ + __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ + __IO uint32_t ISR; /**< Interrupt Status, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t KEY_DEST; /**< Key Destination, offset: 0x20 */ + uint8_t RESERVED_1[124]; + __O uint32_t DIR; /**< Data Input, offset: 0xA0 */ + uint8_t RESERVED_2[4]; + __I uint32_t DOR; /**< Data Output, offset: 0xA8 */ + uint8_t RESERVED_3[20]; + __IO uint32_t MISC; /**< Miscellaneous, offset: 0xC0 */ + uint8_t RESERVED_4[12]; + __IO uint32_t IF_SR; /**< Interface Status, offset: 0xD0 */ + uint8_t RESERVED_5[8]; + __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ + __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ + __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ + uint8_t RESERVED_6[12]; + __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ + __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ + __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ + __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ + __IO uint32_t SEC_LOCK; /**< Lock the security level of PUF block until key generate, wrap or unwrap operation is completed., offset: 0x104 */ + __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ + uint8_t RESERVED_7[500]; + __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ + __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ + uint8_t RESERVED_8[208]; + __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ + __O uint32_t SRAM_INT_SET_ENABLE; /**< Interrupt Enable Set, offset: 0x3DC */ + __I uint32_t SRAM_INT_STATUS; /**< Interrupt Status, offset: 0x3E0 */ + __I uint32_t SRAM_INT_ENABLE; /**< Interrupt Enable, offset: 0x3E4 */ + __O uint32_t SRAM_INT_CLR_STATUS; /**< Interrupt Status Clear, offset: 0x3E8 */ + __O uint32_t SRAM_INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define PUF_CR_ZEROIZE_MASK (0x1U) +#define PUF_CR_ZEROIZE_SHIFT (0U) +/*! ZEROIZE - Begin Zeroize operation + */ +#define PUF_CR_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK) + +#define PUF_CR_ENROLL_MASK (0x2U) +#define PUF_CR_ENROLL_SHIFT (1U) +/*! ENROLL - Begin Enroll operation + */ +#define PUF_CR_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK) + +#define PUF_CR_START_MASK (0x4U) +#define PUF_CR_START_SHIFT (2U) +/*! START - Begin Start operation + */ +#define PUF_CR_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK) + +#define PUF_CR_STOP_MASK (0x20U) +#define PUF_CR_STOP_SHIFT (5U) +/*! STOP - Begin Stop operation + */ +#define PUF_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK) + +#define PUF_CR_GET_KEY_MASK (0x40U) +#define PUF_CR_GET_KEY_SHIFT (6U) +/*! GET_KEY - Begin Get Key operation + */ +#define PUF_CR_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK) + +#define PUF_CR_UNWRAP_MASK (0x80U) +#define PUF_CR_UNWRAP_SHIFT (7U) +/*! UNWRAP - Begin Unwrap operation + */ +#define PUF_CR_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK) + +#define PUF_CR_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! WRAP_GENERATED_RANDOM - Begin Wrap Generated Random operation + */ +#define PUF_CR_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_CR_WRAP_MASK (0x200U) +#define PUF_CR_WRAP_SHIFT (9U) +/*! WRAP - Begin Wrap operation + */ +#define PUF_CR_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK) + +#define PUF_CR_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_CR_GENERATE_RANDOM_SHIFT (15U) +/*! GENERATE_RANDOM - Begin Generate Random operation + */ +#define PUF_CR_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK) + +#define PUF_CR_TEST_PUF_MASK (0x80000000U) +#define PUF_CR_TEST_PUF_SHIFT (31U) +/*! TEST_PUF - Begin Test PUF operation + */ +#define PUF_CR_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK) +/*! @} */ + +/*! @name ORR - Operation Result */ +/*! @{ */ + +#define PUF_ORR_RESULT_CODE_MASK (0xFFU) +#define PUF_ORR_RESULT_CODE_SHIFT (0U) +/*! RESULT_CODE - Result code of last operation + * 0b00000000..Last operation was successful or operation is in progress. + * 0b11110000..Provided AC is not for the current product/version. + * 0b11110001..AC in the second phase is not for the current product/version. + * 0b11110010..Provided AC is corrupted. + * 0b11110011..AC in the second phase is corrupted. + * 0b11110100..Authentication of the provided AC failed. + * 0b11110101..Authentication of the provided AC failed in the second phase. + * 0b11110110..SRAM PUF quality verification fails. + * 0b11110111..Incorrect or unsupported context is provided. + * 0b11111000..A data destination was set that is not allowed according to other settings and the current PUF state. + * 0b11111111..PUF SRAM access has failed. + */ +#define PUF_ORR_RESULT_CODE(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK) + +#define PUF_ORR_LAST_OPERATION_MASK (0xFF000000U) +#define PUF_ORR_LAST_OPERATION_SHIFT (24U) +/*! LAST_OPERATION - Number of last operation + * 0b00000000..Operation is in progress. + * 0b00000001..Last operation was Enroll. + * 0b00000010..Last operation was Start. + * 0b00000101..Last operation was Stop. + * 0b00000110..Last operation was Get Key. + * 0b00000111..Last operation was Unwrap. + * 0b00001000..Last operation was Wrap Generated Random. + * 0b00001001..Last operation was Wrap. + * 0b00001111..Last operation was Generate Random. + * 0b00011110..Last operation was Test Memory. + * 0b00011111..Last operation was Test PUF. + * 0b00100000..Last operation was Initialization. + * 0b00101111..Last operation was Zeroize. + */ +#define PUF_ORR_LAST_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define PUF_SR_BUSY_MASK (0x1U) +#define PUF_SR_BUSY_SHIFT (0U) +/*! BUSY - Operation is in progress + */ +#define PUF_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK) + +#define PUF_SR_OK_MASK (0x2U) +#define PUF_SR_OK_SHIFT (1U) +/*! OK - Last operation was successful + */ +#define PUF_SR_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK) + +#define PUF_SR_ERROR_MASK (0x4U) +#define PUF_SR_ERROR_SHIFT (2U) +/*! ERROR - Last operation failed + */ +#define PUF_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK) + +#define PUF_SR_ZEROIZED_MASK (0x8U) +#define PUF_SR_ZEROIZED_SHIFT (3U) +/*! ZEROIZED - Zeroized or Locked state + */ +#define PUF_SR_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK) + +#define PUF_SR_REJECTED_MASK (0x10U) +#define PUF_SR_REJECTED_SHIFT (4U) +/*! REJECTED - Operation rejected + */ +#define PUF_SR_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK) + +#define PUF_SR_DI_REQUEST_MASK (0x20U) +#define PUF_SR_DI_REQUEST_SHIFT (5U) +/*! DI_REQUEST - Request for data in transfer via the DIR register + */ +#define PUF_SR_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK) + +#define PUF_SR_DO_REQUEST_MASK (0x40U) +#define PUF_SR_DO_REQUEST_SHIFT (6U) +/*! DO_REQUEST - Request for data out transfer via the DOR register + */ +#define PUF_SR_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK) +/*! @} */ + +/*! @name AR - Allow */ +/*! @{ */ + +#define PUF_AR_ALLOW_ENROLL_MASK (0x2U) +#define PUF_AR_ALLOW_ENROLL_SHIFT (1U) +/*! ALLOW_ENROLL - Enroll operation + * 0b0..Enroll operation is not allowed + * 0b1..Enroll operation is allowed + */ +#define PUF_AR_ALLOW_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK) + +#define PUF_AR_ALLOW_START_MASK (0x4U) +#define PUF_AR_ALLOW_START_SHIFT (2U) +/*! ALLOW_START - Start operation + * 0b0..Start operation is not allowed + * 0b1..Start operation is allowed + */ +#define PUF_AR_ALLOW_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK) + +#define PUF_AR_ALLOW_STOP_MASK (0x20U) +#define PUF_AR_ALLOW_STOP_SHIFT (5U) +/*! ALLOW_STOP - Stop operation + * 0b1..Stop operation is allowed + * 0b0..Stop operation is not allowed + */ +#define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) + +#define PUF_AR_ALLOW_GET_KEY_MASK (0x40U) +#define PUF_AR_ALLOW_GET_KEY_SHIFT (6U) +/*! ALLOW_GET_KEY - Get Key operation + * 0b0..Get Key operation is not allowed + * 0b1..Get Key operation is allowed + */ +#define PUF_AR_ALLOW_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK) + +#define PUF_AR_ALLOW_UNWRAP_MASK (0x80U) +#define PUF_AR_ALLOW_UNWRAP_SHIFT (7U) +/*! ALLOW_UNWRAP - Unwrap operation + * 0b0..Unwrap operation is not allowed + * 0b1..Unwrap operation is allowed + */ +#define PUF_AR_ALLOW_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK) + +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation + * 0b0..Wrap Generated Random operation is not allowed + * 0b1..Wrap Generated Random operation is allowed + */ +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_AR_ALLOW_WRAP_MASK (0x200U) +#define PUF_AR_ALLOW_WRAP_SHIFT (9U) +/*! ALLOW_WRAP - Wrap operation + * 0b0..Wrap operation is not allowed + * 0b1..Wrap operation is allowed + */ +#define PUF_AR_ALLOW_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK) + +#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT (15U) +/*! ALLOW_GENERATE_RANDOM - Generate Random operation + * 0b0..Generate Random operation is not allowed + * 0b1..Generate Random operation is allowed + */ +#define PUF_AR_ALLOW_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK) + +#define PUF_AR_ALLOW_TEST_PUF_MASK (0x80000000U) +#define PUF_AR_ALLOW_TEST_PUF_SHIFT (31U) +/*! ALLOW_TEST_PUF - Test PUF operation + * 0b0..Test PUF operation is not allowed + * 0b1..Test PUF operation is allowed + */ +#define PUF_AR_ALLOW_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define PUF_IER_INT_EN_MASK (0x1U) +#define PUF_IER_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt enable + * 0b0..Disables all PUF interrupts + * 0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register + */ +#define PUF_IER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask */ +/*! @{ */ + +#define PUF_IMR_INT_EN_BUSY_MASK (0x1U) +#define PUF_IMR_INT_EN_BUSY_SHIFT (0U) +/*! INT_EN_BUSY - Enable busy interrupt + */ +#define PUF_IMR_INT_EN_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK) + +#define PUF_IMR_INT_EN_OK_MASK (0x2U) +#define PUF_IMR_INT_EN_OK_SHIFT (1U) +/*! INT_EN_OK - Enable ok interrupt + */ +#define PUF_IMR_INT_EN_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK) + +#define PUF_IMR_INT_EN_ERROR_MASK (0x4U) +#define PUF_IMR_INT_EN_ERROR_SHIFT (2U) +/*! INT_EN_ERROR - Enable error interrupt + */ +#define PUF_IMR_INT_EN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK) + +#define PUF_IMR_INT_EN_ZEROIZED_MASK (0x8U) +#define PUF_IMR_INT_EN_ZEROIZED_SHIFT (3U) +/*! INT_EN_ZEROIZED - Enable zeroized interrupt + */ +#define PUF_IMR_INT_EN_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK) + +#define PUF_IMR_INT_EN_REJECTED_MASK (0x10U) +#define PUF_IMR_INT_EN_REJECTED_SHIFT (4U) +/*! INT_EN_REJECTED - Enable rejected interrupt + */ +#define PUF_IMR_INT_EN_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK) + +#define PUF_IMR_INT_EN_DI_REQUEST_MASK (0x20U) +#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT (5U) +/*! INT_EN_DI_REQUEST - Enable data in request interrupt + */ +#define PUF_IMR_INT_EN_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK) + +#define PUF_IMR_INT_EN_DO_REQUEST_MASK (0x40U) +#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT (6U) +/*! INT_EN_DO_REQUEST - Enable data out request interrupt + */ +#define PUF_IMR_INT_EN_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define PUF_ISR_INT_BUSY_MASK (0x1U) +#define PUF_ISR_INT_BUSY_SHIFT (0U) +/*! INT_BUSY - Negative edge occurred on busy, which means that an operation has completed + */ +#define PUF_ISR_INT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK) + +#define PUF_ISR_INT_OK_MASK (0x2U) +#define PUF_ISR_INT_OK_SHIFT (1U) +/*! INT_OK - Positive edge occurred on ok, which means that an operation successfully completed + */ +#define PUF_ISR_INT_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK) + +#define PUF_ISR_INT_ERROR_MASK (0x4U) +#define PUF_ISR_INT_ERROR_SHIFT (2U) +/*! INT_ERROR - Positive edge occurred on error, which means that an operation has failed + */ +#define PUF_ISR_INT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK) + +#define PUF_ISR_INT_ZEROIZED_MASK (0x8U) +#define PUF_ISR_INT_ZEROIZED_SHIFT (3U) +/*! INT_ZEROIZED - Positive edge occurred on zeroized, which means that PUF has moved to the Zeroized or Locked state + */ +#define PUF_ISR_INT_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK) + +#define PUF_ISR_INT_REJECTED_MASK (0x10U) +#define PUF_ISR_INT_REJECTED_SHIFT (4U) +/*! INT_REJECTED - Positive edge occurred on rejected, which means that a command was rejected + */ +#define PUF_ISR_INT_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK) + +#define PUF_ISR_INT_DI_REQUEST_MASK (0x20U) +#define PUF_ISR_INT_DI_REQUEST_SHIFT (5U) +/*! INT_DI_REQUEST - Positive edge occurred on di_request, which means that a data in transfer is requested via the DIR register + */ +#define PUF_ISR_INT_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK) + +#define PUF_ISR_INT_DO_REQUEST_MASK (0x40U) +#define PUF_ISR_INT_DO_REQUEST_SHIFT (6U) +/*! INT_DO_REQUEST - Positive edge occurred on do_request, which means that a data out transfer is requested via the DOR register + */ +#define PUF_ISR_INT_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK) +/*! @} */ + +/*! @name KEY_DEST - Key Destination */ +/*! @{ */ + +#define PUF_KEY_DEST_DEST_DOR_MASK (0x1U) +#define PUF_KEY_DEST_DEST_DOR_SHIFT (0U) +/*! DEST_DOR - Key will be made available via the DOR register + */ +#define PUF_KEY_DEST_DEST_DOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEY_DEST_DEST_DOR_SHIFT)) & PUF_KEY_DEST_DEST_DOR_MASK) + +#define PUF_KEY_DEST_DEST_KO_MASK (0x2U) +#define PUF_KEY_DEST_DEST_KO_SHIFT (1U) +/*! DEST_KO - Key will be made available via the KO interface + */ +#define PUF_KEY_DEST_DEST_KO(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEY_DEST_DEST_KO_SHIFT)) & PUF_KEY_DEST_DEST_KO_MASK) +/*! @} */ + +/*! @name DIR - Data Input */ +/*! @{ */ + +#define PUF_DIR_DI_MASK (0xFFFFFFFFU) +#define PUF_DIR_DI_SHIFT (0U) +/*! DI - Input data to PUF + */ +#define PUF_DIR_DI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK) +/*! @} */ + +/*! @name DOR - Data Output */ +/*! @{ */ + +#define PUF_DOR_DO_MASK (0xFFFFFFFFU) +#define PUF_DOR_DO_SHIFT (0U) +/*! DO - Output data from PUF + */ +#define PUF_DOR_DO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK) +/*! @} */ + +/*! @name MISC - Miscellaneous */ +/*! @{ */ + +#define PUF_MISC_DATA_ENDIANNESS_MASK (0x1U) +#define PUF_MISC_DATA_ENDIANNESS_SHIFT (0U) +/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR: + * 0b0..Little endian + * 0b1..Big endian (default) + */ +#define PUF_MISC_DATA_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK) +/*! @} */ + +/*! @name IF_SR - Interface Status */ +/*! @{ */ + +#define PUF_IF_SR_APB_ERROR_MASK (0x1U) +#define PUF_IF_SR_APB_ERROR_SHIFT (0U) +/*! APB_ERROR - An APB error occurred + */ +#define PUF_IF_SR_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK) +/*! @} */ + +/*! @name PSR - PUF Score */ +/*! @{ */ + +#define PUF_PSR_PUF_SCORE_MASK (0xFU) +#define PUF_PSR_PUF_SCORE_SHIFT (0U) +/*! PUF_SCORE - PUF score obtained during the last Test PUF, Enroll or Start operation + */ +#define PUF_PSR_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK) +/*! @} */ + +/*! @name HW_RUC0 - Hardware Restrict User Context 0 */ +/*! @{ */ + +#define PUF_HW_RUC0_LC_STATE_MASK (0xFFU) +#define PUF_HW_RUC0_LC_STATE_SHIFT (0U) +/*! LC_STATE - Life cycle state based restrictions + * 0b00000011..OEM Develop + * 0b00000111..OEM Develop 2 + * 0b00001111..OEM In-field + * 0b00011111..OEM Field return + * 0b00111111..NXP Field Return/Failure Analysis + * 0b11001111..In-field Locked + * 0b11111111..Bricked + */ +#define PUF_HW_RUC0_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK) + +#define PUF_HW_RUC0_BOOT_STATE_MASK (0xFFFF00U) +#define PUF_HW_RUC0_BOOT_STATE_SHIFT (8U) +/*! BOOT_STATE - Temporal boot state + */ +#define PUF_HW_RUC0_BOOT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK) + +#define PUF_HW_RUC0_CPU0_DEBUG_MASK (0x1000000U) +#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT (24U) +/*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up + */ +#define PUF_HW_RUC0_CPU0_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK) + +#define PUF_HW_RUC0_RUC026_MASK (0x4000000U) +#define PUF_HW_RUC0_RUC026_SHIFT (26U) +/*! RUC026 - Restrict user context 0 + * 0b0..Bit can be used + * 0b1..Bit cannot be used + */ +#define PUF_HW_RUC0_RUC026(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_RUC026_SHIFT)) & PUF_HW_RUC0_RUC026_MASK) + +#define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) +#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT (28U) +/*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level + */ +#define PUF_HW_RUC0_ACCESS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK) +/*! @} */ + +/*! @name HW_RUC1 - Hardware Restrict User Context 1 */ +/*! @{ */ + +#define PUF_HW_RUC1_APP_CTX_MASK (0xFFFFFFFFU) +#define PUF_HW_RUC1_APP_CTX_SHIFT (0U) +/*! APP_CTX - Application customizable context + */ +#define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) +/*! @} */ + +/*! @name HW_INFO - Hardware Information */ +/*! @{ */ + +#define PUF_HW_INFO_CONFIG_BIST_MASK (0x400000U) +#define PUF_HW_INFO_CONFIG_BIST_SHIFT (22U) +/*! CONFIG_BIST - BIST configuration + * 0b0..BIST is not included + * 0b1..BIST is included + */ +#define PUF_HW_INFO_CONFIG_BIST(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_BIST_SHIFT)) & PUF_HW_INFO_CONFIG_BIST_MASK) + +#define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) +#define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) +/*! CONFIG_WRAP - Wrap configuration + * 0b0..Wrap is not included + * 0b1..Wrap is included + */ +#define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) + +#define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) +#define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) +/*! CONFIG_TYPE - PUF configuration + * 0b0001..PUF configuration is Safe. + * 0b0010..PUF configuration is Plus. + */ +#define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) +/*! @} */ + +/*! @name HW_ID - Hardware Identifier */ +/*! @{ */ + +#define PUF_HW_ID_HW_ID_MASK (0xFFFFFFFFU) +#define PUF_HW_ID_HW_ID_SHIFT (0U) +/*! HW_ID - Hardware identifier + */ +#define PUF_HW_ID_HW_ID(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK) +/*! @} */ + +/*! @name HW_VER - Hardware Version */ +/*! @{ */ + +#define PUF_HW_VER_HW_REV_MASK (0xFFU) +#define PUF_HW_VER_HW_REV_SHIFT (0U) +/*! HW_REV - Hardware version, patch part + */ +#define PUF_HW_VER_HW_REV(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK) + +#define PUF_HW_VER_HW_VERSION_MINOR_MASK (0xFF00U) +#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT (8U) +/*! HW_VERSION_MINOR - Hardware version, minor part + */ +#define PUF_HW_VER_HW_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK) + +#define PUF_HW_VER_HW_VERSION_MAJOR_MASK (0xFF0000U) +#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT (16U) +/*! HW_VERSION_MAJOR - Hardware version, major part + */ +#define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name CONFIG - PUF command blocking configuration */ +/*! @{ */ + +#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) +#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) +/*! DIS_PUF_ENROLL - Disable PUF enroll command + */ +#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) + +#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) +#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) +/*! DIS_PUF_START - Disable PUF start command + */ +#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) + +#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) +#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) +/*! DIS_PUF_STOP - Disable PUF stop command + */ +#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) + +#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) +#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) +/*! DIS_PUF_GET_KEY - Disable PUF get key command + */ +#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) +/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command + */ +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) +/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command + */ +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) +/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command + */ +#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) +/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command + */ +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) + +#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) +#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) +/*! DIS_PUF_TEST - Disable PUF test command + */ +#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) +/*! @} */ + +/*! @name SEC_LOCK - Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. */ +/*! @{ */ + +#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) +#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) +/*! SEC_LEVEL - Disable PUF enroll command + * 0b00..Nonsecure user + * 0b00..Nonsecure privilege + * 0b00..Secure user + * 0b00..Secure privilege + */ +#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) +/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level + */ +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) +#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Pattern + */ +#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name APP_CTX_MASK - Application defined context mask */ +/*! @{ */ + +#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) +#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) +/*! APP_CTX_MASK - Application defined context + */ +#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) +/*! @} */ + +/*! @name SRAM_CFG - SRAM Configuration */ +/*! @{ */ + +#define PUF_SRAM_CFG_ENABLE_MASK (0x1U) +#define PUF_SRAM_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - PUF SRAM Controller activation + * 0b1..Enabled + * 0b1..Disabled + */ +#define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) + +#define PUF_SRAM_CFG_CKGATING_MASK (0x4U) +#define PUF_SRAM_CFG_CKGATING_SHIFT (2U) +/*! CKGATING - PUF SRAM Clock Gating control + * 0b1..Enabled + * 0b1..Disabled + */ +#define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) +/*! @} */ + +/*! @name SRAM_STATUS - Status */ +/*! @{ */ + +#define PUF_SRAM_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_STATUS_READY_SHIFT (0U) +/*! READY - PUF SRAM Controller State + */ +#define PUF_SRAM_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable clear + */ +#define PUF_SRAM_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable clear + */ +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable set + */ +#define PUF_SRAM_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable set + */ +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define PUF_SRAM_INT_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status + */ +#define PUF_SRAM_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK) + +#define PUF_SRAM_INT_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status + */ +#define PUF_SRAM_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable + * 0b1..Enabled + * 0b1..Disabled + */ +#define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) +/*! SRAM_APB_ERR - APB_ERR Interrupt Enable + * 0b1..Enabled + * 0b1..Disabled + */ +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status clear + */ +#define PUF_SRAM_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK) + +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Clear + */ +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_STATUS - Interrupt Status set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status set + */ +#define PUF_SRAM_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK) + +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Set + */ +#define PUF_SRAM_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address 0 */ + #define PUF_BASE_0 (0x5003A000u) + /** Peripheral PUF base address 0 */ + #define PUF_BASE_0_NS (0x4003A000u) + /** Peripheral PUF base address 1 */ + #define PUF_BASE_1 (0x5003B000u) + /** Peripheral PUF base address 1 */ + #define PUF_BASE_1_NS (0x4003B000u) + /** Peripheral PUF base address 2 */ + #define PUF_BASE_2 (0x5003C000u) + /** Peripheral PUF base address 2 */ + #define PUF_BASE_2_NS (0x4003C000u) + /** Peripheral PUF base address 3 */ + #define PUF_BASE_3 (0x5003D000u) + /** Peripheral PUF base address 3 */ + #define PUF_BASE_3_NS (0x4003D000u) + /** Peripheral PUF base pointer 0 */ + #define PUF_ALIAS_0 ((PUF_Type *)PUF_BASE_0) + /** Peripheral PUF base pointer 0 */ + #define PUF_ALIAS_0_NS ((PUF_Type *)PUF_BASE_0_NS) + /** Peripheral PUF base pointer 1 */ + #define PUF_ALIAS_1 ((PUF_Type *)PUF_BASE_1) + /** Peripheral PUF base pointer 1 */ + #define PUF_ALIAS_1_NS ((PUF_Type *)PUF_BASE_1_NS) + /** Peripheral PUF base pointer 2 */ + #define PUF_ALIAS_2 ((PUF_Type *)PUF_BASE_2) + /** Peripheral PUF base pointer 2 */ + #define PUF_ALIAS_2_NS ((PUF_Type *)PUF_BASE_2_NS) + /** Peripheral PUF base pointer 3 */ + #define PUF_ALIAS_3 ((PUF_Type *)PUF_BASE_3) + /** Peripheral PUF base pointer 3 */ + #define PUF_ALIAS_3_NS ((PUF_Type *)PUF_BASE_3_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_0 { PUF_BASE_0 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_1 { PUF_BASE_1 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_2 { PUF_BASE_2 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_3 { PUF_BASE_3 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_0 { PUF_ALIAS_0 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_1 { PUF_ALIAS_1 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_2 { PUF_ALIAS_2 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_3 { PUF_ALIAS_3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_0_NS { PUF_BASE_0_NS } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_1_NS { PUF_BASE_1_NS } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_2_NS { PUF_BASE_2_NS } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_3_NS { PUF_BASE_3_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_0_NS { PUF_ALIAS_0_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_1_NS { PUF_ALIAS_1_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_2_NS { PUF_ALIAS_2_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_3_NS { PUF_ALIAS_3_NS } +#else + /** Peripheral PUF base address 0 */ + #define PUF_BASE_0 (0x4003A000u) + /** Peripheral PUF base address 1 */ + #define PUF_BASE_1 (0x4003B000u) + /** Peripheral PUF base address 2 */ + #define PUF_BASE_2 (0x4003C000u) + /** Peripheral PUF base address 3 */ + #define PUF_BASE_3 (0x4003D000u) + /** Peripheral PUF base pointer 0 */ + #define PUF_ALIAS_0 ((PUF_Type *)PUF_BASE_0) + /** Peripheral PUF base pointer 1 */ + #define PUF_ALIAS_1 ((PUF_Type *)PUF_BASE_1) + /** Peripheral PUF base pointer 2 */ + #define PUF_ALIAS_2 ((PUF_Type *)PUF_BASE_2) + /** Peripheral PUF base pointer 3 */ + #define PUF_ALIAS_3 ((PUF_Type *)PUF_BASE_3) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_0 { PUF_BASE_0 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_1 { PUF_BASE_1 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_2 { PUF_BASE_2 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_3 { PUF_BASE_3 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_0 { PUF_ALIAS_0 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_1 { PUF_ALIAS_1 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_2 { PUF_ALIAS_2 } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_3 { PUF_ALIAS_3 } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_1[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60 */ + __IO uint16_t CAPTFILTA; /**< Capture PWMA Input Filter Register, array offset: 0x5A, array step: 0x60 */ + __IO uint16_t CAPTFILTB; /**< Capture PWMB Input Filter Register, array offset: 0x5C, array step: 0x60 */ + __IO uint16_t CAPTFILTX; /**< Capture PWMX Input Filter Register, array offset: 0x5E, array step: 0x60 */ + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits + */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits + */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it will force the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization + */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master + * reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it + * will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value + */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value + */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value + */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_WAITEN_MASK (0x4000U) +#define PWM_CTRL2_WAITEN_SHIFT (14U) +/*! WAITEN - Sleep Enable + */ +#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable + */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA + * output that is high at the end of a period will maintain this state until a match with VAL3 clears the + * output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWMA output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime + */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value Register 0 + */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ + +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +/*! FRACVAL1 - Fractional Value 1 Register + */ +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value Register 1 + */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ + +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +/*! FRACVAL2 - Fractional Value 2 + */ +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value Register 2 + */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ + +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +/*! FRACVAL3 - Fractional Value 3 + */ +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value Register 3 + */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ + +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +/*! FRACVAL4 - Fractional Value 4 + */ +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value Register 4 + */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ + +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +/*! FRACVAL5 - Fractional Value 5 + */ +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value Register 5 + */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ + +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) + +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) + +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) + +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +/*! TEST - Test Status Bit + */ +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input + */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input + */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input + */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 + */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 + */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +/*! CFB0 - Capture Flag B0 + */ +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) + +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +/*! CFB1 - Capture Flag B1 + */ +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) + +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +/*! CFA0 - Capture Flag A0 + */ +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) + +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +/*! CFA1 - Capture Flag A1 + */ +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) + +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) + +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) + +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable + */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable + */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +/*! CB0DE - Capture B0 FIFO DMA Enable + */ +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) + +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +/*! CB1DE - Capture B1 FIFO DMA Enable + */ +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) + +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +/*! CA0DE - Capture A0 FIFO DMA Enable + */ +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) + +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +/*! CA1DE - Capture A1 FIFO DMA Enable + */ +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to + * which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 + */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 + */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 + */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 + */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 + */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ + +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) + +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) + +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) + +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) + +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) + +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) + +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +/*! CFAWM - Capture A FIFOs Water Mark + */ +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) + +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +/*! CA0CNT - Capture A0 FIFO Word Count + */ +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) + +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +/*! CA1CNT - Capture A1 FIFO Word Count + */ +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ + +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +/*! EDGCMPA - Edge Compare A + */ +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) + +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +/*! EDGCNTA - Edge Counter A + */ +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ + +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) + +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) + +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) + +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) + +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) + +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) + +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +/*! CFBWM - Capture B FIFOs Water Mark + */ +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) + +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +/*! CB0CNT - Capture B0 FIFO Word Count + */ +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) + +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +/*! CB1CNT - Capture B1 FIFO Word Count + */ +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ + +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +/*! EDGCMPB - Edge Compare B + */ +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) + +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +/*! EDGCNTB - Edge Counter B + */ +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark + */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count + */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count + */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X + */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X + */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - CAPTVAL0 + */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - CVAL0CYC + */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - CAPTVAL1 + */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - CVAL1CYC + */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ + +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +/*! CAPTVAL2 - CAPTVAL2 + */ +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +/*! CVAL2CYC - CVAL2CYC + */ +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ + +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +/*! CAPTVAL3 - CAPTVAL3 + */ +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +/*! CVAL3CYC - CVAL3CYC + */ +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ + +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +/*! CAPTVAL4 - CAPTVAL4 + */ +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +/*! CVAL4CYC - CVAL4CYC + */ +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ + +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +/*! CAPTVAL5 - CAPTVAL5 + */ +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +/*! CVAL5CYC - CVAL5CYC + */ +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits + */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (4U) + +/*! @name CAPTFILTA - Capture PWMA Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) +/*! CAPTA_FILT_PER - Fault Filter Period + */ +#define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) + +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) +/*! CAPTA_FILT_CNT - Fault Filter Count + */ +#define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTA */ +#define PWM_CAPTFILTA_COUNT (4U) + +/*! @name CAPTFILTB - Capture PWMB Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) +/*! CAPTB_FILT_PER - Fault Filter Period + */ +#define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) + +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) +/*! CAPTB_FILT_CNT - Fault Filter Count + */ +#define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTB */ +#define PWM_CAPTFILTB_COUNT (4U) + +/*! @name CAPTFILTX - Capture PWMX Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Fault Filter Period + */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Fault Filter Count + */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay + */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM counter is stopped, but PWM outputs will hold the current state. + * 0b0001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_MONPLL_MASK (0x3U) +#define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock + * will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL + * encounters problems. These bits are write protected until the next reset. + */ +#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by + * FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins + */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period + */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count + */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500C3000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400C3000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x500C5000u) + /** Peripheral PWM1 base address */ + #define PWM1_BASE_NS (0x400C5000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Peripheral PWM1 base pointer */ + #define PWM1_NS ((PWM_Type *)PWM1_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS, PWM1_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS, PWM1_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400C3000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x400C5000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_COMPARE0_IRQn, FLEXPWM0_COMPARE1_IRQn, FLEXPWM0_COMPARE2_IRQn, FLEXPWM0_COMPARE3_IRQn }, { FLEXPWM1_COMPARE0_IRQn, FLEXPWM1_COMPARE1_IRQn, FLEXPWM1_COMPARE2_IRQn, FLEXPWM1_COMPARE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_RELOAD0_IRQn, FLEXPWM0_RELOAD1_IRQn, FLEXPWM0_RELOAD2_IRQn, FLEXPWM0_RELOAD3_IRQn }, { FLEXPWM1_RELOAD0_IRQn, FLEXPWM1_RELOAD1_IRQn, FLEXPWM1_RELOAD2_IRQn, FLEXPWM1_RELOAD3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn }, { FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint16_t YEARMON; /**< Year and Month Counters, offset: 0x0 */ + __IO uint16_t DAYS; /**< Days and Day-of-Week Counters, offset: 0x2 */ + __IO uint16_t HOURMIN; /**< Hours and Minutes Counters, offset: 0x4 */ + __IO uint16_t SECONDS; /**< Seconds Counters, offset: 0x6 */ + __IO uint16_t ALM_YEARMON; /**< Year and Months Alarm, offset: 0x8 */ + __IO uint16_t ALM_DAYS; /**< Days Alarm, offset: 0xA */ + __IO uint16_t ALM_HOURMIN; /**< Hours and Minutes Alarm, offset: 0xC */ + __IO uint16_t ALM_SECONDS; /**< Seconds Alarm, offset: 0xE */ + __IO uint16_t CTRL; /**< Control, offset: 0x10 */ + __IO uint16_t STATUS; /**< Status, offset: 0x12 */ + __IO uint16_t ISR; /**< Interrupt Status, offset: 0x14 */ + __IO uint16_t IER; /**< Interrupt Enable, offset: 0x16 */ + uint8_t RESERVED_0[8]; + __IO uint16_t GP_DATA_REG; /**< General Purpose Data, offset: 0x20 */ + __IO uint16_t DST_HOUR; /**< Daylight Saving Hour, offset: 0x22 */ + __IO uint16_t DST_MONTH; /**< Daylight Saving Month, offset: 0x24 */ + __IO uint16_t DST_DAY; /**< Daylight Saving Day, offset: 0x26 */ + __IO uint16_t COMPEN; /**< Compensation, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint16_t TAMPER_QSCR; /**< Tamper Queue Status and Control, offset: 0x2E */ + uint8_t RESERVED_2[2]; + __IO uint16_t TAMPER_SCR; /**< Tamper Status and Control, offset: 0x32 */ + __IO uint16_t FILTER01_CFG; /**< Tamper 01 Filter Configuration, offset: 0x34 */ + __IO uint16_t FILTER23_CFG; /**< Tamper 23 Filter Configuration, offset: 0x36 */ + uint8_t RESERVED_3[8]; + __I uint16_t TAMPER_QUEUE; /**< Tamper Queue, offset: 0x40 */ + __IO uint16_t CTRL2; /**< Control 2, offset: 0x42 */ + uint8_t RESERVED_4[1980]; + __IO uint32_t SUBSECOND_CTRL; /**< Sub-second control, offset: 0x800 */ + __I uint32_t SUBSECOND_CNT; /**< Sub-second counter, offset: 0x804 */ + uint8_t RESERVED_5[1016]; + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake timer control, offset: 0xC00 */ + uint8_t RESERVED_6[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake timer counter, offset: 0xC0C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name YEARMON - Year and Month Counters */ +/*! @{ */ + +#define RTC_YEARMON_MON_CNT_MASK (0xFU) +#define RTC_YEARMON_MON_CNT_SHIFT (0U) +/*! MON_CNT - Month Counter + * 0b0000, 0b1101, 0b1110, 0b1111..Illegal Value + * 0b0001..January + * 0b0010..February + * 0b0011..March + * 0b0100..April + * 0b0101..May + * 0b0110..June + * 0b0111..July + * 0b1000..August + * 0b1001..September + * 0b1010..October + * 0b1011..November + * 0b1100..December + */ +#define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) + +#define RTC_YEARMON_YROFST_MASK (0xFF00U) +#define RTC_YEARMON_YROFST_SHIFT (8U) +/*! YROFST - Year Offset Count Value + */ +#define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) +/*! @} */ + +/*! @name DAYS - Days and Day-of-Week Counters */ +/*! @{ */ + +#define RTC_DAYS_DAY_CNT_MASK (0x1FU) +#define RTC_DAYS_DAY_CNT_SHIFT (0U) +/*! DAY_CNT - Days Counter Value + */ +#define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) + +#define RTC_DAYS_DOW_MASK (0x700U) +#define RTC_DAYS_DOW_SHIFT (8U) +/*! DOW - Day of Week Counter Value + * 0b000..Sunday + * 0b001..Monday + * 0b010..Tuesday + * 0b011..Wednesday + * 0b100..Thursday + * 0b101..Friday + * 0b110..Saturday + * 0b111.. + */ +#define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) +/*! @} */ + +/*! @name HOURMIN - Hours and Minutes Counters */ +/*! @{ */ + +#define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) +#define RTC_HOURMIN_MIN_CNT_SHIFT (0U) +/*! MIN_CNT - Minutes Counter Value + */ +#define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) + +#define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) +#define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) +/*! HOUR_CNT - Hours Counter Value + */ +#define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) +/*! @} */ + +/*! @name SECONDS - Seconds Counters */ +/*! @{ */ + +#define RTC_SECONDS_SEC_CNT_MASK (0x3FU) +#define RTC_SECONDS_SEC_CNT_SHIFT (0U) +/*! SEC_CNT - Seconds Counter Value + */ +#define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) +/*! @} */ + +/*! @name ALM_YEARMON - Year and Months Alarm */ +/*! @{ */ + +#define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) +#define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) +/*! ALM_MON - Months Value for Alarm + */ +#define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) + +#define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) +#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) +/*! ALM_YEAR - Year Value for Alarm + */ +#define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) +/*! @} */ + +/*! @name ALM_DAYS - Days Alarm */ +/*! @{ */ + +#define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) +#define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) +/*! ALM_DAY - Days Value for Alarm + */ +#define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) +/*! @} */ + +/*! @name ALM_HOURMIN - Hours and Minutes Alarm */ +/*! @{ */ + +#define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) +#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) +/*! ALM_MIN - Minutes Value for Alarm + */ +#define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) + +#define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) +#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) +/*! ALM_HOUR - Hours Value for Alarm + */ +#define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) +/*! @} */ + +/*! @name ALM_SECONDS - Seconds Alarm */ +/*! @{ */ + +#define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) +#define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) +/*! ALM_SEC - Seconds Alarm Value + */ +#define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) + +#define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) +#define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) +/*! DEC_SEC - Decrement Seconds Counter by 1. + */ +#define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) + +#define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) +#define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) +/*! INC_SEC - Increment Seconds Counter by 1. + */ +#define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define RTC_CTRL_FINEEN_MASK (0x1U) +#define RTC_CTRL_FINEEN_SHIFT (0U) +/*! FINEEN - Fine Compensation Enable + * 0b1..Fine compensation is enabled. + * 0b0..Fine compensation is disabled + */ +#define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) + +#define RTC_CTRL_COMP_EN_MASK (0x2U) +#define RTC_CTRL_COMP_EN_SHIFT (1U) +/*! COMP_EN - Compensation Enable + * 0b0..Coarse Compensation is disabled. + * 0b1..Coarse Compensation is enabled. + */ +#define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) + +#define RTC_CTRL_ALM_MATCH_MASK (0xCU) +#define RTC_CTRL_ALM_MATCH_SHIFT (2U) +/*! ALM_MATCH - Alarm Match + * 0b00..Only Seconds, Minutes, and Hours matched. + * 0b01..Only Seconds, Minutes, Hours, and Days matched. + * 0b10..Only Seconds, Minutes, Hours, Days, and Months matched. + * 0b11..Only Seconds, Minutes, Hours, Days, Months, and Year (offset) matched. + */ +#define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) + +#define RTC_CTRL_TIMER_STB_MASK_MASK (0x10U) +#define RTC_CTRL_TIMER_STB_MASK_SHIFT (4U) +/*! TIMER_STB_MASK - Sampling Timer Clocks Mask + * 0b1..Sampling clocks are gated in standby mode + * 0b0..Sampling clocks are not gated when in standby mode + */ +#define RTC_CTRL_TIMER_STB_MASK(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_TIMER_STB_MASK_SHIFT)) & RTC_CTRL_TIMER_STB_MASK_MASK) + +#define RTC_CTRL_DST_EN_MASK (0x40U) +#define RTC_CTRL_DST_EN_SHIFT (6U) +/*! DST_EN - Daylight Saving Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) + +#define RTC_CTRL_SWR_MASK (0x100U) +#define RTC_CTRL_SWR_SHIFT (8U) +/*! SWR - Software Reset + * 0b0..Software Reset cleared + * 0b1..Software Reset asserted + */ +#define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) + +#define RTC_CTRL_CLKOUT_MASK (0x6000U) +#define RTC_CTRL_CLKOUT_SHIFT (13U) +/*! CLKOUT - RTC Clock Output Selection + * 0b00..No Output Clock + * 0b01..Fine 1 Hz Clock with both precise edges + * 0b10..32.768 kHz Clock + * 0b11..Coarse 1 Hz Clock with both precise edges + */ +#define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define RTC_STATUS_INVAL_BIT_MASK (0x1U) +#define RTC_STATUS_INVAL_BIT_SHIFT (0U) +/*! INVAL_BIT - Invalidate CPU Read/Write Access + * 0b0..Time /Date Counters can be read/written. Time /Date is valid. + * 0b1..Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written. + */ +#define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) + +#define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) +#define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) +/*! WRITE_PROT_EN - Write Protect Enable Status + * 0b0..Registers are unlocked and can be accessed. + * 0b1..Registers are locked and in read-only mode. + */ +#define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) + +#define RTC_STATUS_CPU_LOW_VOLT_MASK (0x4U) +#define RTC_STATUS_CPU_LOW_VOLT_SHIFT (2U) +/*! CPU_LOW_VOLT - CPU Low Voltage Warning Status + * 0b0..CPU in Normal Operating Voltage. + * 0b1..CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode. + */ +#define RTC_STATUS_CPU_LOW_VOLT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CPU_LOW_VOLT_SHIFT)) & RTC_STATUS_CPU_LOW_VOLT_MASK) + +#define RTC_STATUS_RST_SRC_MASK (0x8U) +#define RTC_STATUS_RST_SRC_SHIFT (3U) +/*! RST_SRC - Reset Source + * 0b0..Standby Mode Exit + * 0b1..Power-On Reset + */ +#define RTC_STATUS_RST_SRC(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_RST_SRC_SHIFT)) & RTC_STATUS_RST_SRC_MASK) + +#define RTC_STATUS_CMP_INT_MASK (0x20U) +#define RTC_STATUS_CMP_INT_SHIFT (5U) +/*! CMP_INT - Compensation Interval + */ +#define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) + +#define RTC_STATUS_WE_MASK (0xC0U) +#define RTC_STATUS_WE_SHIFT (6U) +/*! WE - Write Enable + * 0b10..Enable Write Protection - Registers are locked. + * 0b00, 0b01, 0b11, 0b10..Disable Write Protection - Registers are unlocked. + */ +#define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) + +#define RTC_STATUS_BUS_ERR_MASK (0x100U) +#define RTC_STATUS_BUS_ERR_SHIFT (8U) +/*! BUS_ERR - Bus Error + * 0b0..Read and Write accesses are normal. + * 0b1..Read or Write accesses occurred when INVAL_BIT was asserted. + */ +#define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) + +#define RTC_STATUS_CMP_DONE_MASK (0x800U) +#define RTC_STATUS_CMP_DONE_SHIFT (11U) +/*! CMP_DONE - Compensation Done + * 0b0..Compensation busy or not enabled + * 0b1..Compensation completed + */ +#define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define RTC_ISR_TAMPER_IS_MASK (0x1U) +#define RTC_ISR_TAMPER_IS_SHIFT (0U) +/*! TAMPER_IS - Tamper Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted (Default on reset) . + */ +#define RTC_ISR_TAMPER_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_TAMPER_IS_SHIFT)) & RTC_ISR_TAMPER_IS_MASK) + +#define RTC_ISR_ALM_IS_MASK (0x4U) +#define RTC_ISR_ALM_IS_SHIFT (2U) +/*! ALM_IS - Alarm Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) + +#define RTC_ISR_DAY_IS_MASK (0x8U) +#define RTC_ISR_DAY_IS_SHIFT (3U) +/*! DAY_IS - Days Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) + +#define RTC_ISR_HOUR_IS_MASK (0x10U) +#define RTC_ISR_HOUR_IS_SHIFT (4U) +/*! HOUR_IS - Hours Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) + +#define RTC_ISR_MIN_IS_MASK (0x20U) +#define RTC_ISR_MIN_IS_SHIFT (5U) +/*! MIN_IS - Minutes Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) + +#define RTC_ISR_IS_1HZ_MASK (0x40U) +#define RTC_ISR_IS_1HZ_SHIFT (6U) +/*! IS_1HZ - 1 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) + +#define RTC_ISR_IS_2HZ_MASK (0x80U) +#define RTC_ISR_IS_2HZ_SHIFT (7U) +/*! IS_2HZ - 2 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) + +#define RTC_ISR_IS_4HZ_MASK (0x100U) +#define RTC_ISR_IS_4HZ_SHIFT (8U) +/*! IS_4HZ - 4 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) + +#define RTC_ISR_IS_8HZ_MASK (0x200U) +#define RTC_ISR_IS_8HZ_SHIFT (9U) +/*! IS_8HZ - 8 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) + +#define RTC_ISR_IS_16HZ_MASK (0x400U) +#define RTC_ISR_IS_16HZ_SHIFT (10U) +/*! IS_16HZ - 16 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) + +#define RTC_ISR_IS_32HZ_MASK (0x800U) +#define RTC_ISR_IS_32HZ_SHIFT (11U) +/*! IS_32HZ - 32 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) + +#define RTC_ISR_IS_64HZ_MASK (0x1000U) +#define RTC_ISR_IS_64HZ_SHIFT (12U) +/*! IS_64HZ - 64 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) + +#define RTC_ISR_IS_128HZ_MASK (0x2000U) +#define RTC_ISR_IS_128HZ_SHIFT (13U) +/*! IS_128HZ - 128 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) + +#define RTC_ISR_IS_256HZ_MASK (0x4000U) +#define RTC_ISR_IS_256HZ_SHIFT (14U) +/*! IS_256HZ - 256 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) + +#define RTC_ISR_IS_512HZ_MASK (0x8000U) +#define RTC_ISR_IS_512HZ_SHIFT (15U) +/*! IS_512HZ - 512 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define RTC_IER_TAMPER_IE_MASK (0x1U) +#define RTC_IER_TAMPER_IE_SHIFT (0U) +/*! TAMPER_IE - Tamper Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled (Default on reset). + */ +#define RTC_IER_TAMPER_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_TAMPER_IE_SHIFT)) & RTC_IER_TAMPER_IE_MASK) + +#define RTC_IER_ALM_IE_MASK (0x4U) +#define RTC_IER_ALM_IE_SHIFT (2U) +/*! ALM_IE - Alarm Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) + +#define RTC_IER_DAY_IE_MASK (0x8U) +#define RTC_IER_DAY_IE_SHIFT (3U) +/*! DAY_IE - Days Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) + +#define RTC_IER_HOUR_IE_MASK (0x10U) +#define RTC_IER_HOUR_IE_SHIFT (4U) +/*! HOUR_IE - Hours Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) + +#define RTC_IER_MIN_IE_MASK (0x20U) +#define RTC_IER_MIN_IE_SHIFT (5U) +/*! MIN_IE - Minutes Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) + +#define RTC_IER_IE_1HZ_MASK (0x40U) +#define RTC_IER_IE_1HZ_SHIFT (6U) +/*! IE_1HZ - 1 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) + +#define RTC_IER_IE_2HZ_MASK (0x80U) +#define RTC_IER_IE_2HZ_SHIFT (7U) +/*! IE_2HZ - 2 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) + +#define RTC_IER_IE_4HZ_MASK (0x100U) +#define RTC_IER_IE_4HZ_SHIFT (8U) +/*! IE_4HZ - 4 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) + +#define RTC_IER_IE_8HZ_MASK (0x200U) +#define RTC_IER_IE_8HZ_SHIFT (9U) +/*! IE_8HZ - 8 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) + +#define RTC_IER_IE_16HZ_MASK (0x400U) +#define RTC_IER_IE_16HZ_SHIFT (10U) +/*! IE_16HZ - 16 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) + +#define RTC_IER_IE_32HZ_MASK (0x800U) +#define RTC_IER_IE_32HZ_SHIFT (11U) +/*! IE_32HZ - 32 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) + +#define RTC_IER_IE_64HZ_MASK (0x1000U) +#define RTC_IER_IE_64HZ_SHIFT (12U) +/*! IE_64HZ - 64 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) + +#define RTC_IER_IE_128HZ_MASK (0x2000U) +#define RTC_IER_IE_128HZ_SHIFT (13U) +/*! IE_128HZ - 128 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) + +#define RTC_IER_IE_256HZ_MASK (0x4000U) +#define RTC_IER_IE_256HZ_SHIFT (14U) +/*! IE_256HZ - 256 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) + +#define RTC_IER_IE_512HZ_MASK (0x8000U) +#define RTC_IER_IE_512HZ_SHIFT (15U) +/*! IE_512HZ - 512 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) +/*! @} */ + +/*! @name GP_DATA_REG - General Purpose Data */ +/*! @{ */ + +#define RTC_GP_DATA_REG_CFG0_MASK (0x1U) +#define RTC_GP_DATA_REG_CFG0_SHIFT (0U) +/*! CFG0 - CFGn + */ +#define RTC_GP_DATA_REG_CFG0(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG0_SHIFT)) & RTC_GP_DATA_REG_CFG0_MASK) + +#define RTC_GP_DATA_REG_CFG1_MASK (0x2U) +#define RTC_GP_DATA_REG_CFG1_SHIFT (1U) +/*! CFG1 - CFGn + */ +#define RTC_GP_DATA_REG_CFG1(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG1_SHIFT)) & RTC_GP_DATA_REG_CFG1_MASK) + +#define RTC_GP_DATA_REG_CFG2_MASK (0x4U) +#define RTC_GP_DATA_REG_CFG2_SHIFT (2U) +/*! CFG2 - CFGn + */ +#define RTC_GP_DATA_REG_CFG2(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG2_SHIFT)) & RTC_GP_DATA_REG_CFG2_MASK) + +#define RTC_GP_DATA_REG_CFG3_MASK (0x8U) +#define RTC_GP_DATA_REG_CFG3_SHIFT (3U) +/*! CFG3 - CFGn + */ +#define RTC_GP_DATA_REG_CFG3(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG3_SHIFT)) & RTC_GP_DATA_REG_CFG3_MASK) + +#define RTC_GP_DATA_REG_CFG4_MASK (0x10U) +#define RTC_GP_DATA_REG_CFG4_SHIFT (4U) +/*! CFG4 - CFGn + */ +#define RTC_GP_DATA_REG_CFG4(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG4_SHIFT)) & RTC_GP_DATA_REG_CFG4_MASK) + +#define RTC_GP_DATA_REG_CFG5_MASK (0x20U) +#define RTC_GP_DATA_REG_CFG5_SHIFT (5U) +/*! CFG5 - CFGn + */ +#define RTC_GP_DATA_REG_CFG5(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG5_SHIFT)) & RTC_GP_DATA_REG_CFG5_MASK) + +#define RTC_GP_DATA_REG_CFG6_MASK (0x40U) +#define RTC_GP_DATA_REG_CFG6_SHIFT (6U) +/*! CFG6 - CFGn + */ +#define RTC_GP_DATA_REG_CFG6(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG6_SHIFT)) & RTC_GP_DATA_REG_CFG6_MASK) + +#define RTC_GP_DATA_REG_CFG7_MASK (0x80U) +#define RTC_GP_DATA_REG_CFG7_SHIFT (7U) +/*! CFG7 - CFGn + */ +#define RTC_GP_DATA_REG_CFG7(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG7_SHIFT)) & RTC_GP_DATA_REG_CFG7_MASK) + +#define RTC_GP_DATA_REG_CFG8_MASK (0x100U) +#define RTC_GP_DATA_REG_CFG8_SHIFT (8U) +/*! CFG8 - CFGn + */ +#define RTC_GP_DATA_REG_CFG8(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG8_SHIFT)) & RTC_GP_DATA_REG_CFG8_MASK) + +#define RTC_GP_DATA_REG_CFG9_MASK (0x200U) +#define RTC_GP_DATA_REG_CFG9_SHIFT (9U) +/*! CFG9 - CFGn + */ +#define RTC_GP_DATA_REG_CFG9(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG9_SHIFT)) & RTC_GP_DATA_REG_CFG9_MASK) + +#define RTC_GP_DATA_REG_CFG10_MASK (0x400U) +#define RTC_GP_DATA_REG_CFG10_SHIFT (10U) +/*! CFG10 - CFGn + */ +#define RTC_GP_DATA_REG_CFG10(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG10_SHIFT)) & RTC_GP_DATA_REG_CFG10_MASK) + +#define RTC_GP_DATA_REG_CFG11_MASK (0x800U) +#define RTC_GP_DATA_REG_CFG11_SHIFT (11U) +/*! CFG11 - CFGn + */ +#define RTC_GP_DATA_REG_CFG11(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG11_SHIFT)) & RTC_GP_DATA_REG_CFG11_MASK) + +#define RTC_GP_DATA_REG_CFG12_MASK (0x1000U) +#define RTC_GP_DATA_REG_CFG12_SHIFT (12U) +/*! CFG12 - CFGn + */ +#define RTC_GP_DATA_REG_CFG12(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG12_SHIFT)) & RTC_GP_DATA_REG_CFG12_MASK) + +#define RTC_GP_DATA_REG_CFG13_MASK (0x2000U) +#define RTC_GP_DATA_REG_CFG13_SHIFT (13U) +/*! CFG13 - CFGn + */ +#define RTC_GP_DATA_REG_CFG13(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG13_SHIFT)) & RTC_GP_DATA_REG_CFG13_MASK) + +#define RTC_GP_DATA_REG_CFG14_MASK (0x4000U) +#define RTC_GP_DATA_REG_CFG14_SHIFT (14U) +/*! CFG14 - CFGn + */ +#define RTC_GP_DATA_REG_CFG14(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG14_SHIFT)) & RTC_GP_DATA_REG_CFG14_MASK) + +#define RTC_GP_DATA_REG_CFG15_MASK (0x8000U) +#define RTC_GP_DATA_REG_CFG15_SHIFT (15U) +/*! CFG15 - CFGn + */ +#define RTC_GP_DATA_REG_CFG15(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG15_SHIFT)) & RTC_GP_DATA_REG_CFG15_MASK) +/*! @} */ + +/*! @name DST_HOUR - Daylight Saving Hour */ +/*! @{ */ + +#define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) +#define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) +/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value + */ +#define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) + +#define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) +#define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) +/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value + */ +#define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) +/*! @} */ + +/*! @name DST_MONTH - Daylight Saving Month */ +/*! @{ */ + +#define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) +#define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) +/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value + */ +#define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) + +#define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) +#define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) +/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value + */ +#define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) +/*! @} */ + +/*! @name DST_DAY - Daylight Saving Day */ +/*! @{ */ + +#define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) +#define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) +/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value + */ +#define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) + +#define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) +#define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) +/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value + */ +#define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) +/*! @} */ + +/*! @name COMPEN - Compensation */ +/*! @{ */ + +#define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) +#define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) +/*! COMPEN_VAL - Compensation Value + */ +#define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) +/*! @} */ + +/*! @name TAMPER_QSCR - Tamper Queue Status and Control */ +/*! @{ */ + +#define RTC_TAMPER_QSCR_Q_FULL_MASK (0x1U) +#define RTC_TAMPER_QSCR_Q_FULL_SHIFT (0U) +/*! Q_FULL - Q_FULL + * 0b1..The tamper queue is full. + * 0b0..The tamper queue is not full. + */ +#define RTC_TAMPER_QSCR_Q_FULL(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_FULL_SHIFT)) & RTC_TAMPER_QSCR_Q_FULL_MASK) + +#define RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK (0x2U) +#define RTC_TAMPER_QSCR_Q_FULL_INT_EN_SHIFT (1U) +/*! Q_FULL_INT_EN - Q_FULL_INT_EN + * 0b1..Queue full interrupt is enabled. + * 0b0..Queue full interrupt is disabled. + */ +#define RTC_TAMPER_QSCR_Q_FULL_INT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_FULL_INT_EN_SHIFT)) & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) + +#define RTC_TAMPER_QSCR_Q_CLEAR_MASK (0x4U) +#define RTC_TAMPER_QSCR_Q_CLEAR_SHIFT (2U) +/*! Q_CLEAR - Q_CLEAR + */ +#define RTC_TAMPER_QSCR_Q_CLEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_CLEAR_SHIFT)) & RTC_TAMPER_QSCR_Q_CLEAR_MASK) +/*! @} */ + +/*! @name TAMPER_SCR - Tamper Status and Control */ +/*! @{ */ + +#define RTC_TAMPER_SCR_TMPR_EN_MASK (0xFU) +#define RTC_TAMPER_SCR_TMPR_EN_SHIFT (0U) +/*! TMPR_EN - Tamper Control + * 0b0000..Tamper Status reporting disabled. + * 0b0001..Tamper Status reporting enabled. + */ +#define RTC_TAMPER_SCR_TMPR_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_EN_SHIFT)) & RTC_TAMPER_SCR_TMPR_EN_MASK) + +#define RTC_TAMPER_SCR_TMPR_STS_MASK (0xF00U) +#define RTC_TAMPER_SCR_TMPR_STS_SHIFT (8U) +/*! TMPR_STS - Tamper Status + * 0b0000..No Tamper Detected + * 0b0001..Tamper Event Detected + */ +#define RTC_TAMPER_SCR_TMPR_STS(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_STS_SHIFT)) & RTC_TAMPER_SCR_TMPR_STS_MASK) +/*! @} */ + +/*! @name FILTER01_CFG - Tamper 01 Filter Configuration */ +/*! @{ */ + +#define RTC_FILTER01_CFG_FIL_DUR1_MASK (0xFU) +#define RTC_FILTER01_CFG_FIL_DUR1_SHIFT (0U) +/*! FIL_DUR1 - Tamper Detect Bit 1 Filter Duration + * 0b0000..Filtering operation disabled. + * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. + */ +#define RTC_FILTER01_CFG_FIL_DUR1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR1_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR1_MASK) + +#define RTC_FILTER01_CFG_CLK_SEL1_MASK (0x70U) +#define RTC_FILTER01_CFG_CLK_SEL1_SHIFT (4U) +/*! CLK_SEL1 - Tamper Filter 1 Clock Select + * 0b000..32 kHz clock + * 0b001..512 Hz clock + * 0b010..128 Hz clock + * 0b011..64 Hz clock + * 0b100..16 Hz clock + * 0b101..8 Hz clock + * 0b110..4 Hz clock + * 0b111..2 Hz clock + */ +#define RTC_FILTER01_CFG_CLK_SEL1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL1_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL1_MASK) + +#define RTC_FILTER01_CFG_POL1_MASK (0x80U) +#define RTC_FILTER01_CFG_POL1_SHIFT (7U) +/*! POL1 - Tamper Detect Input Bit 1 Polarity Control + * 0b0..Tamper detect input bit 1 is active high. + * 0b1..Tamper detect input bit 1 is active low. + */ +#define RTC_FILTER01_CFG_POL1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL1_SHIFT)) & RTC_FILTER01_CFG_POL1_MASK) + +#define RTC_FILTER01_CFG_FIL_DUR0_MASK (0xF00U) +#define RTC_FILTER01_CFG_FIL_DUR0_SHIFT (8U) +/*! FIL_DUR0 - Tamper Detect Bit 0 Filter Duration + * 0b0000..Filtering operation disabled. + * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. + */ +#define RTC_FILTER01_CFG_FIL_DUR0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR0_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR0_MASK) + +#define RTC_FILTER01_CFG_CLK_SEL0_MASK (0x7000U) +#define RTC_FILTER01_CFG_CLK_SEL0_SHIFT (12U) +/*! CLK_SEL0 - Tamper Filter 0 Clock Select + * 0b000..32 kHz clock + * 0b001..512 Hz clock + * 0b010..128 Hz clock + * 0b011..64 Hz clock + * 0b100..16 Hz clock + * 0b101..8 Hz clock + * 0b110..4 Hz clock + * 0b111..2 Hz clock + */ +#define RTC_FILTER01_CFG_CLK_SEL0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL0_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL0_MASK) + +#define RTC_FILTER01_CFG_POL0_MASK (0x8000U) +#define RTC_FILTER01_CFG_POL0_SHIFT (15U) +/*! POL0 - Tamper Detect Input Bit 0 Polarity Control + * 0b0..Tamper detect input bit 0 is active high. + * 0b1..Tamper detect input bit 0 is active low. + */ +#define RTC_FILTER01_CFG_POL0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL0_SHIFT)) & RTC_FILTER01_CFG_POL0_MASK) +/*! @} */ + +/*! @name FILTER23_CFG - Tamper 23 Filter Configuration */ +/*! @{ */ + +#define RTC_FILTER23_CFG_FIL_DUR3_MASK (0xFU) +#define RTC_FILTER23_CFG_FIL_DUR3_SHIFT (0U) +/*! FIL_DUR3 - Tamper Detect Bit 3 Filter Duration + * 0b0000..Filtering operation disabled. + * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. + */ +#define RTC_FILTER23_CFG_FIL_DUR3(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_FIL_DUR3_SHIFT)) & RTC_FILTER23_CFG_FIL_DUR3_MASK) + +#define RTC_FILTER23_CFG_CLK_SEL3_MASK (0x70U) +#define RTC_FILTER23_CFG_CLK_SEL3_SHIFT (4U) +/*! CLK_SEL3 - Tamper Filter 3 Clock Select + * 0b000..32 kHz clock + * 0b001..512 Hz clock + * 0b010..128 Hz clock + * 0b011..64 Hz clock + * 0b100..16 Hz clock + * 0b101..8 Hz clock + * 0b110..4 Hz clock + * 0b111..2 Hz clock + */ +#define RTC_FILTER23_CFG_CLK_SEL3(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_CLK_SEL3_SHIFT)) & RTC_FILTER23_CFG_CLK_SEL3_MASK) + +#define RTC_FILTER23_CFG_POL3_MASK (0x80U) +#define RTC_FILTER23_CFG_POL3_SHIFT (7U) +/*! POL3 - Tamper Detect Input Bit 3 Polarity Control + * 0b0..Tamper detect input bit 3 is active high. + * 0b1..Tamper detect input bit 3 is active low. + */ +#define RTC_FILTER23_CFG_POL3(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_POL3_SHIFT)) & RTC_FILTER23_CFG_POL3_MASK) + +#define RTC_FILTER23_CFG_FIL_DUR2_MASK (0xF00U) +#define RTC_FILTER23_CFG_FIL_DUR2_SHIFT (8U) +/*! FIL_DUR2 - Tamper Detect Bit 2 Filter Duration + * 0b0000..Filtering operation disabled. + * 0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted. + */ +#define RTC_FILTER23_CFG_FIL_DUR2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_FIL_DUR2_SHIFT)) & RTC_FILTER23_CFG_FIL_DUR2_MASK) + +#define RTC_FILTER23_CFG_CLK_SEL2_MASK (0x7000U) +#define RTC_FILTER23_CFG_CLK_SEL2_SHIFT (12U) +/*! CLK_SEL2 - Tamper Filter 2 Clock Select + * 0b000..32 kHz clock + * 0b001..512 Hz clock + * 0b010..128 Hz clock + * 0b011..64 Hz clock + * 0b100..16 Hz clock + * 0b101..8 Hz clock + * 0b110..4 Hz clock + * 0b111..2 Hz clock + */ +#define RTC_FILTER23_CFG_CLK_SEL2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_CLK_SEL2_SHIFT)) & RTC_FILTER23_CFG_CLK_SEL2_MASK) + +#define RTC_FILTER23_CFG_POL2_MASK (0x8000U) +#define RTC_FILTER23_CFG_POL2_SHIFT (15U) +/*! POL2 - Tamper Detect Input Bit 2 Polarity Control + * 0b0..Tamper detect input bit 2 is active high. + * 0b1..Tamper detect input bit 2 is active low. + */ +#define RTC_FILTER23_CFG_POL2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_POL2_SHIFT)) & RTC_FILTER23_CFG_POL2_MASK) +/*! @} */ + +/*! @name TAMPER_QUEUE - Tamper Queue */ +/*! @{ */ + +#define RTC_TAMPER_QUEUE_TAMPER_DATA_MASK (0xFFFFU) +#define RTC_TAMPER_QUEUE_TAMPER_DATA_SHIFT (0U) +/*! TAMPER_DATA - Tamper type stamp and pin number information register + */ +#define RTC_TAMPER_QUEUE_TAMPER_DATA(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QUEUE_TAMPER_DATA_SHIFT)) & RTC_TAMPER_QUEUE_TAMPER_DATA_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define RTC_CTRL2_TAMP_CFG_OVER_MASK (0x1U) +#define RTC_CTRL2_TAMP_CFG_OVER_SHIFT (0U) +/*! TAMP_CFG_OVER - Tamper Configuration Over + * 0b0..Tamper filter processing disabled. + * 0b1..Tamper filter processing enabled. + */ +#define RTC_CTRL2_TAMP_CFG_OVER(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL2_TAMP_CFG_OVER_SHIFT)) & RTC_CTRL2_TAMP_CFG_OVER_MASK) +/*! @} */ + +/*! @name SUBSECOND_CTRL - Sub-second control */ +/*! @{ */ + +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) +/*! SUB_SECOND_CNT_EN - Sub-second counter enable bit + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) +/*! @} */ + +/*! @name SUBSECOND_CNT - Sub-second counter */ +/*! @{ */ + +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK (0xFFFFU) +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT (0U) +/*! SUBSECOND_CNT - Current sub-second counter value + */ +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CTRL - Wake timer control */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake timer status flag + * 0b0..Wake timer has not timed out. + * 0b1..Wake timer has timed out. + */ +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear wake timer + * 0b0..No effect. + * 0b1..Clears the wake counter and halt operation until a new count value is loaded. + */ +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - Enable the 5-bit clock divider to divide down the 32Khz input clock to generate + * the 1Khz clock source for the wake timer. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable interrupt when WAKE_FLAG is set. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake timer counter */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake counter + */ +#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCTimer Configuration, offset: 0x0 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT Control, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT Limit Event Select, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< Halt Event Select, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< Stop Event Select, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< Start Event Select, offset: 0x14 */ + }; + __IO uint32_t DITHER; /**< Dither Condition, offset: 0x18 */ + uint8_t RESERVED_0[36]; + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< Counter, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< State, offset: 0x44 */ + }; + __I uint32_t INPUT; /**< Input, offset: 0x48 */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< Match/Capture Mode, offset: 0x4C */ + }; + __IO uint32_t OUTPUT; /**< Output, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< Output Counter Direction Control, offset: 0x54 */ + __IO uint32_t RES; /**< Output Conflict Resolution, offset: 0x58 */ + __IO uint32_t DMAREQ0; /**< DMA Request 0, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< DMA Request 1, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< Event Interrupt Enable, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< Event Flag, offset: 0xF4 */ + __IO uint32_t CONEN; /**< Conflict Interrupt Enable, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< Conflict Flag, offset: 0xFC */ + union { /* offset: 0x100 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[16]; + __IO uint32_t CAP[16]; /**< Capture Value, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[16]; + __IO uint32_t MATCH[16]; /**< Match Value, array offset: 0x100, array step: 0x4 */ + }; + }; + __IO uint32_t FRACMAT[6]; /**< Fractional Match, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_2[168]; + union { /* offset: 0x200 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[16]; + __IO uint32_t CAPCTRL[16]; /**< Capture Control, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[16]; + __IO uint32_t MATCHREL[16]; /**< Match Reload Value, array offset: 0x200, array step: 0x4 */ + }; + }; + __IO uint32_t FRACMATREL[6]; /**< Fractional Match Reload, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_3[168]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< Event n State, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< Event n Control, array offset: 0x304, array step: 0x8 */ + } EV[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< Output n Set, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< Output n Clear, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCTimer Configuration */ +/*! @{ */ + +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT Operation + * 0b0..Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..Unified counter. The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT Clock Mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including all counters and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including all + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT Clock Select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0 + * 0b0001..Falling edges on input 0 + * 0b0010..Rising edges on input 1 + * 0b0011..Falling edges on input 1 + * 0b0100..Rising edges on input 2 + * 0b0101..Falling edges on input 2 + * 0b0110..Rising edges on input 3 + * 0b0111..Falling edges on input 3 + * 0b1000..Rising edges on input 4 + * 0b1001..Falling edges on input 4 + * 0b1010..Rising edges on input 5 + * 0b1011..Falling edges on input 5 + * 0b1100..Rising edges on input 6 + * 0b1101..Falling edges on input 6 + * 0b1110..Rising edges on input 7 + * 0b1111..Falling edges on input 7 + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - No Reload Lower Match + * 0b0..Reload. The default setting. + * 0b1..No Reload. Prevents the lower match registers from being reloaded from their respective reload registers. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - No Reload Higher Match + * 0b0..Reload. The default setting. + * 0b1..No Reload. Prevents the higher match registers from being reloaded from their respective reload registers. + */ +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + +#define SCT_CONFIG_INSYNC_MASK (0x1FE00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Input Synchronization + */ +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - Auto Limit Lower + * 0b0..Disable. + * 0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event. + */ +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - Auto Limit Higher + * 0b0..Disable. + * 0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event. + */ +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - Down Counter Low + * 0b0..Up. The L or unified counter is counting up. + * 0b1..Down. The L or unified counter is counting down. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - Stop Counter Low + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - Halt Counter Low + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Clear Counter Low + */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - Bidirectional Select Low + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Prescaler for Low Counter + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - Down Counter High + * 0b0..Up. The H counter is counting up. + * 0b1..Down. The H counter is counting down. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - Stop Counter High + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - Halt Counter High + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Clear Counter High + */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Bidirectional Select High + * 0b0..Up. The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Prescaler for High Counter + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT Control */ +/*! @{ */ + +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - Down Counter Low + * 0b0..Up. The L or unified counter is counting up. + * 0b1..Down. The L or unified counter is counting down. + */ +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - Stop Counter Low + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - Halt Counter Low + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Clear Counter Low + */ +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - Bidirectional Select Low + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Prescaler for Low Counter + */ +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - Down Counter High + * 0b0..Up. The H counter is counting up. + * 0b1..Down. The H counter is counting down. + */ +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - Stop Counter High + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - Halt Counter High + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Clear Counter High + */ +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Bidirectional Select High + * 0b0..Up. The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Prescaler for High Counter + */ +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + +/*! @name LIMIT - SCT Limit Event Select */ +/*! @{ */ + +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - Limit Event Counter Low + */ +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - Limit Event Counter High + */ +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + +/*! @name HALT - Halt Event Select */ +/*! @{ */ + +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - Halt Event Low + */ +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - Halt Event High + */ +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + +/*! @name STOP - Stop Event Select */ +/*! @{ */ + +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - Stop Event Low + */ +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - Stop Event High + */ +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + +/*! @name START - Start Event Select */ +/*! @{ */ + +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = + * bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = + * bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name DITHER - Dither Condition */ +/*! @{ */ + +#define SCT_DITHER_DITHER_L_MASK (0xFFFFU) +#define SCT_DITHER_DITHER_L_SHIFT (0U) +/*! DITHER_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = bit + * 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DITHER_DITHER_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_L_SHIFT)) & SCT_DITHER_DITHER_L_MASK) + +#define SCT_DITHER_DITHER_H_MASK (0xFFFF0000U) +#define SCT_DITHER_DITHER_H_SHIFT (16U) +/*! DITHER_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = bit + * 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DITHER_DITHER_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_H_SHIFT)) & SCT_DITHER_DITHER_H_MASK) +/*! @} */ + +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + +/*! @name COUNT - Counter */ +/*! @{ */ + +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - Counter Low + */ +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - Counter High + */ +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + +/*! @name STATE - State */ +/*! @{ */ + +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable + */ +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable + */ +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - Input */ +/*! @{ */ + +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +/*! REGMODEL + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) + +#define SCT_REGMODEL_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMOD_L_SHIFT (0U) +#define SCT_REGMODEL_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK) + +#define SCT_REGMODEL_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODEL_REGMOD_H_SHIFT (16U) +#define SCT_REGMODEL_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +/*! REGMODEH + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) + +#define SCT_REGMODEH_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMOD_L_SHIFT (0U) +#define SCT_REGMODEH_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK) + +#define SCT_REGMODEH_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODEH_REGMOD_H_SHIFT (16U) +#define SCT_REGMODEH_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK) +/*! @} */ + +/*! @name REGMODE - Match/Capture Mode */ +/*! @{ */ + +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + +#define SCT_REGMODE_REGMOD_L0_MASK (0x1U) +#define SCT_REGMODE_REGMOD_L0_SHIFT (0U) +/*! REGMOD_L0 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK) + +#define SCT_REGMODE_REGMOD_L1_MASK (0x2U) +#define SCT_REGMODE_REGMOD_L1_SHIFT (1U) +/*! REGMOD_L1 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK) + +#define SCT_REGMODE_REGMOD_L2_MASK (0x4U) +#define SCT_REGMODE_REGMOD_L2_SHIFT (2U) +/*! REGMOD_L2 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK) + +#define SCT_REGMODE_REGMOD_L3_MASK (0x8U) +#define SCT_REGMODE_REGMOD_L3_SHIFT (3U) +/*! REGMOD_L3 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK) + +#define SCT_REGMODE_REGMOD_L4_MASK (0x10U) +#define SCT_REGMODE_REGMOD_L4_SHIFT (4U) +/*! REGMOD_L4 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK) + +#define SCT_REGMODE_REGMOD_L5_MASK (0x20U) +#define SCT_REGMODE_REGMOD_L5_SHIFT (5U) +/*! REGMOD_L5 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK) + +#define SCT_REGMODE_REGMOD_L6_MASK (0x40U) +#define SCT_REGMODE_REGMOD_L6_SHIFT (6U) +/*! REGMOD_L6 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK) + +#define SCT_REGMODE_REGMOD_L7_MASK (0x80U) +#define SCT_REGMODE_REGMOD_L7_SHIFT (7U) +/*! REGMOD_L7 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK) + +#define SCT_REGMODE_REGMOD_L8_MASK (0x100U) +#define SCT_REGMODE_REGMOD_L8_SHIFT (8U) +/*! REGMOD_L8 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK) + +#define SCT_REGMODE_REGMOD_L9_MASK (0x200U) +#define SCT_REGMODE_REGMOD_L9_SHIFT (9U) +/*! REGMOD_L9 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK) + +#define SCT_REGMODE_REGMOD_L10_MASK (0x400U) +#define SCT_REGMODE_REGMOD_L10_SHIFT (10U) +/*! REGMOD_L10 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK) + +#define SCT_REGMODE_REGMOD_L11_MASK (0x800U) +#define SCT_REGMODE_REGMOD_L11_SHIFT (11U) +/*! REGMOD_L11 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK) + +#define SCT_REGMODE_REGMOD_L12_MASK (0x1000U) +#define SCT_REGMODE_REGMOD_L12_SHIFT (12U) +/*! REGMOD_L12 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK) + +#define SCT_REGMODE_REGMOD_L13_MASK (0x2000U) +#define SCT_REGMODE_REGMOD_L13_SHIFT (13U) +/*! REGMOD_L13 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK) + +#define SCT_REGMODE_REGMOD_L14_MASK (0x4000U) +#define SCT_REGMODE_REGMOD_L14_SHIFT (14U) +/*! REGMOD_L14 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK) + +#define SCT_REGMODE_REGMOD_L15_MASK (0x8000U) +#define SCT_REGMODE_REGMOD_L15_SHIFT (15U) +/*! REGMOD_L15 - Register Mode Low n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_L15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK) + +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) + +#define SCT_REGMODE_REGMOD_H0_MASK (0x10000U) +#define SCT_REGMODE_REGMOD_H0_SHIFT (16U) +/*! REGMOD_H0 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK) + +#define SCT_REGMODE_REGMOD_H1_MASK (0x20000U) +#define SCT_REGMODE_REGMOD_H1_SHIFT (17U) +/*! REGMOD_H1 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK) + +#define SCT_REGMODE_REGMOD_H2_MASK (0x40000U) +#define SCT_REGMODE_REGMOD_H2_SHIFT (18U) +/*! REGMOD_H2 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK) + +#define SCT_REGMODE_REGMOD_H3_MASK (0x80000U) +#define SCT_REGMODE_REGMOD_H3_SHIFT (19U) +/*! REGMOD_H3 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK) + +#define SCT_REGMODE_REGMOD_H4_MASK (0x100000U) +#define SCT_REGMODE_REGMOD_H4_SHIFT (20U) +/*! REGMOD_H4 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK) + +#define SCT_REGMODE_REGMOD_H5_MASK (0x200000U) +#define SCT_REGMODE_REGMOD_H5_SHIFT (21U) +/*! REGMOD_H5 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK) + +#define SCT_REGMODE_REGMOD_H6_MASK (0x400000U) +#define SCT_REGMODE_REGMOD_H6_SHIFT (22U) +/*! REGMOD_H6 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK) + +#define SCT_REGMODE_REGMOD_H7_MASK (0x800000U) +#define SCT_REGMODE_REGMOD_H7_SHIFT (23U) +/*! REGMOD_H7 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK) + +#define SCT_REGMODE_REGMOD_H8_MASK (0x1000000U) +#define SCT_REGMODE_REGMOD_H8_SHIFT (24U) +/*! REGMOD_H8 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK) + +#define SCT_REGMODE_REGMOD_H9_MASK (0x2000000U) +#define SCT_REGMODE_REGMOD_H9_SHIFT (25U) +/*! REGMOD_H9 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK) + +#define SCT_REGMODE_REGMOD_H10_MASK (0x4000000U) +#define SCT_REGMODE_REGMOD_H10_SHIFT (26U) +/*! REGMOD_H10 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK) + +#define SCT_REGMODE_REGMOD_H11_MASK (0x8000000U) +#define SCT_REGMODE_REGMOD_H11_SHIFT (27U) +/*! REGMOD_H11 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK) + +#define SCT_REGMODE_REGMOD_H12_MASK (0x10000000U) +#define SCT_REGMODE_REGMOD_H12_SHIFT (28U) +/*! REGMOD_H12 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK) + +#define SCT_REGMODE_REGMOD_H13_MASK (0x20000000U) +#define SCT_REGMODE_REGMOD_H13_SHIFT (29U) +/*! REGMOD_H13 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK) + +#define SCT_REGMODE_REGMOD_H14_MASK (0x40000000U) +#define SCT_REGMODE_REGMOD_H14_SHIFT (30U) +/*! REGMOD_H14 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK) + +#define SCT_REGMODE_REGMOD_H15_MASK (0x80000000U) +#define SCT_REGMODE_REGMOD_H15_SHIFT (31U) +/*! REGMOD_H15 - Register Mode High n + * 0b0..Match. Register n operates as a match register + * 0b1..Capture. Register n operates as a capture register + */ +#define SCT_REGMODE_REGMOD_H15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK) +/*! @} */ + +/*! @name OUTPUT - Output */ +/*! @{ */ + +#define SCT_OUTPUT_OUT0_MASK (0x1U) +#define SCT_OUTPUT_OUT0_SHIFT (0U) +/*! OUT0 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK) + +#define SCT_OUTPUT_OUT1_MASK (0x2U) +#define SCT_OUTPUT_OUT1_SHIFT (1U) +/*! OUT1 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK) + +#define SCT_OUTPUT_OUT2_MASK (0x4U) +#define SCT_OUTPUT_OUT2_SHIFT (2U) +/*! OUT2 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK) + +#define SCT_OUTPUT_OUT3_MASK (0x8U) +#define SCT_OUTPUT_OUT3_SHIFT (3U) +/*! OUT3 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK) + +#define SCT_OUTPUT_OUT4_MASK (0x10U) +#define SCT_OUTPUT_OUT4_SHIFT (4U) +/*! OUT4 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK) + +#define SCT_OUTPUT_OUT5_MASK (0x20U) +#define SCT_OUTPUT_OUT5_SHIFT (5U) +/*! OUT5 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK) + +#define SCT_OUTPUT_OUT6_MASK (0x40U) +#define SCT_OUTPUT_OUT6_SHIFT (6U) +/*! OUT6 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK) + +#define SCT_OUTPUT_OUT7_MASK (0x80U) +#define SCT_OUTPUT_OUT7_SHIFT (7U) +/*! OUT7 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK) + +#define SCT_OUTPUT_OUT8_MASK (0x100U) +#define SCT_OUTPUT_OUT8_SHIFT (8U) +/*! OUT8 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK) + +#define SCT_OUTPUT_OUT9_MASK (0x200U) +#define SCT_OUTPUT_OUT9_SHIFT (9U) +/*! OUT9 - Output n + * 0b0..Writing a 0 forces the corresponding output low + * 0b1..Writing a 1 forces the corresponding output high + */ +#define SCT_OUTPUT_OUT9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */ +/*! @{ */ + +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/Clear Operation on Output n + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + * 0b11..Reserved. Do not program this value. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +/*! @} */ + +/*! @name RES - Output Conflict Resolution */ +/*! @{ */ + +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output n + * 0b00..No change + * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field) + * 0b11..Toggle output + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +/*! @} */ + +/*! @name DMAREQ0 - DMA Request 0 */ +/*! @{ */ + +#define SCT_DMAREQ0_DEV_0_MASK (0x1U) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DEV_1_MASK (0x2U) +#define SCT_DMAREQ0_DEV_1_SHIFT (1U) +/*! DEV_1 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK) + +#define SCT_DMAREQ0_DEV_2_MASK (0x4U) +#define SCT_DMAREQ0_DEV_2_SHIFT (2U) +/*! DEV_2 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK) + +#define SCT_DMAREQ0_DEV_3_MASK (0x8U) +#define SCT_DMAREQ0_DEV_3_SHIFT (3U) +/*! DEV_3 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK) + +#define SCT_DMAREQ0_DEV_4_MASK (0x10U) +#define SCT_DMAREQ0_DEV_4_SHIFT (4U) +/*! DEV_4 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK) + +#define SCT_DMAREQ0_DEV_5_MASK (0x20U) +#define SCT_DMAREQ0_DEV_5_SHIFT (5U) +/*! DEV_5 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK) + +#define SCT_DMAREQ0_DEV_6_MASK (0x40U) +#define SCT_DMAREQ0_DEV_6_SHIFT (6U) +/*! DEV_6 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK) + +#define SCT_DMAREQ0_DEV_7_MASK (0x80U) +#define SCT_DMAREQ0_DEV_7_SHIFT (7U) +/*! DEV_7 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK) + +#define SCT_DMAREQ0_DEV_8_MASK (0x100U) +#define SCT_DMAREQ0_DEV_8_SHIFT (8U) +/*! DEV_8 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK) + +#define SCT_DMAREQ0_DEV_9_MASK (0x200U) +#define SCT_DMAREQ0_DEV_9_SHIFT (9U) +/*! DEV_9 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK) + +#define SCT_DMAREQ0_DEV_10_MASK (0x400U) +#define SCT_DMAREQ0_DEV_10_SHIFT (10U) +/*! DEV_10 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK) + +#define SCT_DMAREQ0_DEV_11_MASK (0x800U) +#define SCT_DMAREQ0_DEV_11_SHIFT (11U) +/*! DEV_11 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK) + +#define SCT_DMAREQ0_DEV_12_MASK (0x1000U) +#define SCT_DMAREQ0_DEV_12_SHIFT (12U) +/*! DEV_12 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK) + +#define SCT_DMAREQ0_DEV_13_MASK (0x2000U) +#define SCT_DMAREQ0_DEV_13_SHIFT (13U) +/*! DEV_13 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK) + +#define SCT_DMAREQ0_DEV_14_MASK (0x4000U) +#define SCT_DMAREQ0_DEV_14_SHIFT (14U) +/*! DEV_14 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK) + +#define SCT_DMAREQ0_DEV_15_MASK (0x8000U) +#define SCT_DMAREQ0_DEV_15_SHIFT (15U) +/*! DEV_15 - DMA Request Event n + */ +#define SCT_DMAREQ0_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - DMA Request 0 State + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) +/*! @} */ + +/*! @name DMAREQ1 - DMA Request 1 */ +/*! @{ */ + +#define SCT_DMAREQ1_DEV_0_MASK (0x1U) +#define SCT_DMAREQ1_DEV_0_SHIFT (0U) +/*! DEV_0 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK) + +#define SCT_DMAREQ1_DEV_1_MASK (0x2U) +#define SCT_DMAREQ1_DEV_1_SHIFT (1U) +/*! DEV_1 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DEV_2_MASK (0x4U) +#define SCT_DMAREQ1_DEV_2_SHIFT (2U) +/*! DEV_2 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK) + +#define SCT_DMAREQ1_DEV_3_MASK (0x8U) +#define SCT_DMAREQ1_DEV_3_SHIFT (3U) +/*! DEV_3 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK) + +#define SCT_DMAREQ1_DEV_4_MASK (0x10U) +#define SCT_DMAREQ1_DEV_4_SHIFT (4U) +/*! DEV_4 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK) + +#define SCT_DMAREQ1_DEV_5_MASK (0x20U) +#define SCT_DMAREQ1_DEV_5_SHIFT (5U) +/*! DEV_5 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK) + +#define SCT_DMAREQ1_DEV_6_MASK (0x40U) +#define SCT_DMAREQ1_DEV_6_SHIFT (6U) +/*! DEV_6 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK) + +#define SCT_DMAREQ1_DEV_7_MASK (0x80U) +#define SCT_DMAREQ1_DEV_7_SHIFT (7U) +/*! DEV_7 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK) + +#define SCT_DMAREQ1_DEV_8_MASK (0x100U) +#define SCT_DMAREQ1_DEV_8_SHIFT (8U) +/*! DEV_8 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK) + +#define SCT_DMAREQ1_DEV_9_MASK (0x200U) +#define SCT_DMAREQ1_DEV_9_SHIFT (9U) +/*! DEV_9 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK) + +#define SCT_DMAREQ1_DEV_10_MASK (0x400U) +#define SCT_DMAREQ1_DEV_10_SHIFT (10U) +/*! DEV_10 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK) + +#define SCT_DMAREQ1_DEV_11_MASK (0x800U) +#define SCT_DMAREQ1_DEV_11_SHIFT (11U) +/*! DEV_11 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK) + +#define SCT_DMAREQ1_DEV_12_MASK (0x1000U) +#define SCT_DMAREQ1_DEV_12_SHIFT (12U) +/*! DEV_12 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK) + +#define SCT_DMAREQ1_DEV_13_MASK (0x2000U) +#define SCT_DMAREQ1_DEV_13_SHIFT (13U) +/*! DEV_13 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK) + +#define SCT_DMAREQ1_DEV_14_MASK (0x4000U) +#define SCT_DMAREQ1_DEV_14_SHIFT (14U) +/*! DEV_14 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK) + +#define SCT_DMAREQ1_DEV_15_MASK (0x8000U) +#define SCT_DMAREQ1_DEV_15_SHIFT (15U) +/*! DEV_15 - DMA Request Event n + */ +#define SCT_DMAREQ1_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - DMA Request 1 State + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - Event Interrupt Enable */ +/*! @{ */ + +#define SCT_EVEN_IEN0_MASK (0x1U) +#define SCT_EVEN_IEN0_SHIFT (0U) +/*! IEN0 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK) + +#define SCT_EVEN_IEN1_MASK (0x2U) +#define SCT_EVEN_IEN1_SHIFT (1U) +/*! IEN1 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK) + +#define SCT_EVEN_IEN2_MASK (0x4U) +#define SCT_EVEN_IEN2_SHIFT (2U) +/*! IEN2 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK) + +#define SCT_EVEN_IEN3_MASK (0x8U) +#define SCT_EVEN_IEN3_SHIFT (3U) +/*! IEN3 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK) + +#define SCT_EVEN_IEN4_MASK (0x10U) +#define SCT_EVEN_IEN4_SHIFT (4U) +/*! IEN4 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK) + +#define SCT_EVEN_IEN5_MASK (0x20U) +#define SCT_EVEN_IEN5_SHIFT (5U) +/*! IEN5 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK) + +#define SCT_EVEN_IEN6_MASK (0x40U) +#define SCT_EVEN_IEN6_SHIFT (6U) +/*! IEN6 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK) + +#define SCT_EVEN_IEN7_MASK (0x80U) +#define SCT_EVEN_IEN7_SHIFT (7U) +/*! IEN7 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK) + +#define SCT_EVEN_IEN8_MASK (0x100U) +#define SCT_EVEN_IEN8_SHIFT (8U) +/*! IEN8 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK) + +#define SCT_EVEN_IEN9_MASK (0x200U) +#define SCT_EVEN_IEN9_SHIFT (9U) +/*! IEN9 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK) + +#define SCT_EVEN_IEN10_MASK (0x400U) +#define SCT_EVEN_IEN10_SHIFT (10U) +/*! IEN10 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK) + +#define SCT_EVEN_IEN11_MASK (0x800U) +#define SCT_EVEN_IEN11_SHIFT (11U) +/*! IEN11 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK) + +#define SCT_EVEN_IEN12_MASK (0x1000U) +#define SCT_EVEN_IEN12_SHIFT (12U) +/*! IEN12 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK) + +#define SCT_EVEN_IEN13_MASK (0x2000U) +#define SCT_EVEN_IEN13_SHIFT (13U) +/*! IEN13 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK) + +#define SCT_EVEN_IEN14_MASK (0x4000U) +#define SCT_EVEN_IEN14_SHIFT (14U) +/*! IEN14 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK) + +#define SCT_EVEN_IEN15_MASK (0x8000U) +#define SCT_EVEN_IEN15_SHIFT (15U) +/*! IEN15 - Event Interrupt Enable n + * 0b0..Disable + * 0b1..Enable + */ +#define SCT_EVEN_IEN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK) +/*! @} */ + +/*! @name EVFLAG - Event Flag */ +/*! @{ */ + +#define SCT_EVFLAG_FLAG0_MASK (0x1U) +#define SCT_EVFLAG_FLAG0_SHIFT (0U) +/*! FLAG0 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK) + +#define SCT_EVFLAG_FLAG1_MASK (0x2U) +#define SCT_EVFLAG_FLAG1_SHIFT (1U) +/*! FLAG1 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK) + +#define SCT_EVFLAG_FLAG2_MASK (0x4U) +#define SCT_EVFLAG_FLAG2_SHIFT (2U) +/*! FLAG2 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK) + +#define SCT_EVFLAG_FLAG3_MASK (0x8U) +#define SCT_EVFLAG_FLAG3_SHIFT (3U) +/*! FLAG3 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK) + +#define SCT_EVFLAG_FLAG4_MASK (0x10U) +#define SCT_EVFLAG_FLAG4_SHIFT (4U) +/*! FLAG4 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK) + +#define SCT_EVFLAG_FLAG5_MASK (0x20U) +#define SCT_EVFLAG_FLAG5_SHIFT (5U) +/*! FLAG5 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK) + +#define SCT_EVFLAG_FLAG6_MASK (0x40U) +#define SCT_EVFLAG_FLAG6_SHIFT (6U) +/*! FLAG6 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK) + +#define SCT_EVFLAG_FLAG7_MASK (0x80U) +#define SCT_EVFLAG_FLAG7_SHIFT (7U) +/*! FLAG7 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK) + +#define SCT_EVFLAG_FLAG8_MASK (0x100U) +#define SCT_EVFLAG_FLAG8_SHIFT (8U) +/*! FLAG8 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK) + +#define SCT_EVFLAG_FLAG9_MASK (0x200U) +#define SCT_EVFLAG_FLAG9_SHIFT (9U) +/*! FLAG9 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK) + +#define SCT_EVFLAG_FLAG10_MASK (0x400U) +#define SCT_EVFLAG_FLAG10_SHIFT (10U) +/*! FLAG10 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK) + +#define SCT_EVFLAG_FLAG11_MASK (0x800U) +#define SCT_EVFLAG_FLAG11_SHIFT (11U) +/*! FLAG11 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK) + +#define SCT_EVFLAG_FLAG12_MASK (0x1000U) +#define SCT_EVFLAG_FLAG12_SHIFT (12U) +/*! FLAG12 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK) + +#define SCT_EVFLAG_FLAG13_MASK (0x2000U) +#define SCT_EVFLAG_FLAG13_SHIFT (13U) +/*! FLAG13 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK) + +#define SCT_EVFLAG_FLAG14_MASK (0x4000U) +#define SCT_EVFLAG_FLAG14_SHIFT (14U) +/*! FLAG14 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK) + +#define SCT_EVFLAG_FLAG15_MASK (0x8000U) +#define SCT_EVFLAG_FLAG15_SHIFT (15U) +/*! FLAG15 - Event Flag n + * 0b0..No Flag + * 0b1..Event n Flag + */ +#define SCT_EVFLAG_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK) +/*! @} */ + +/*! @name CONEN - Conflict Interrupt Enable */ +/*! @{ */ + +#define SCT_CONEN_NCEN0_MASK (0x1U) +#define SCT_CONEN_NCEN0_SHIFT (0U) +/*! NCEN0 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK) + +#define SCT_CONEN_NCEN1_MASK (0x2U) +#define SCT_CONEN_NCEN1_SHIFT (1U) +/*! NCEN1 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK) + +#define SCT_CONEN_NCEN2_MASK (0x4U) +#define SCT_CONEN_NCEN2_SHIFT (2U) +/*! NCEN2 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK) + +#define SCT_CONEN_NCEN3_MASK (0x8U) +#define SCT_CONEN_NCEN3_SHIFT (3U) +/*! NCEN3 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK) + +#define SCT_CONEN_NCEN4_MASK (0x10U) +#define SCT_CONEN_NCEN4_SHIFT (4U) +/*! NCEN4 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK) + +#define SCT_CONEN_NCEN5_MASK (0x20U) +#define SCT_CONEN_NCEN5_SHIFT (5U) +/*! NCEN5 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK) + +#define SCT_CONEN_NCEN6_MASK (0x40U) +#define SCT_CONEN_NCEN6_SHIFT (6U) +/*! NCEN6 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK) + +#define SCT_CONEN_NCEN7_MASK (0x80U) +#define SCT_CONEN_NCEN7_SHIFT (7U) +/*! NCEN7 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK) + +#define SCT_CONEN_NCEN8_MASK (0x100U) +#define SCT_CONEN_NCEN8_SHIFT (8U) +/*! NCEN8 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK) + +#define SCT_CONEN_NCEN9_MASK (0x200U) +#define SCT_CONEN_NCEN9_SHIFT (9U) +/*! NCEN9 - No Change Conflict Event/Interrupt Enable + * 0b0..No interrupt + * 0b1..Interrupt + */ +#define SCT_CONEN_NCEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK) +/*! @} */ + +/*! @name CONFLAG - Conflict Flag */ +/*! @{ */ + +#define SCT_CONFLAG_NCFLAG0_MASK (0x1U) +#define SCT_CONFLAG_NCFLAG0_SHIFT (0U) +/*! NCFLAG0 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK) + +#define SCT_CONFLAG_NCFLAG1_MASK (0x2U) +#define SCT_CONFLAG_NCFLAG1_SHIFT (1U) +/*! NCFLAG1 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK) + +#define SCT_CONFLAG_NCFLAG2_MASK (0x4U) +#define SCT_CONFLAG_NCFLAG2_SHIFT (2U) +/*! NCFLAG2 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK) + +#define SCT_CONFLAG_NCFLAG3_MASK (0x8U) +#define SCT_CONFLAG_NCFLAG3_SHIFT (3U) +/*! NCFLAG3 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK) + +#define SCT_CONFLAG_NCFLAG4_MASK (0x10U) +#define SCT_CONFLAG_NCFLAG4_SHIFT (4U) +/*! NCFLAG4 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK) + +#define SCT_CONFLAG_NCFLAG5_MASK (0x20U) +#define SCT_CONFLAG_NCFLAG5_SHIFT (5U) +/*! NCFLAG5 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK) + +#define SCT_CONFLAG_NCFLAG6_MASK (0x40U) +#define SCT_CONFLAG_NCFLAG6_SHIFT (6U) +/*! NCFLAG6 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK) + +#define SCT_CONFLAG_NCFLAG7_MASK (0x80U) +#define SCT_CONFLAG_NCFLAG7_SHIFT (7U) +/*! NCFLAG7 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK) + +#define SCT_CONFLAG_NCFLAG8_MASK (0x100U) +#define SCT_CONFLAG_NCFLAG8_SHIFT (8U) +/*! NCFLAG8 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK) + +#define SCT_CONFLAG_NCFLAG9_MASK (0x200U) +#define SCT_CONFLAG_NCFLAG9_SHIFT (9U) +/*! NCFLAG9 - No Change Conflict Event Flag + * 0b0..No Conflict Event + * 0b1..A No Change Conflict Event occured + */ +#define SCT_CONFLAG_NCFLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK) + +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - Bus Error Low/Unified + */ +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - Bus Error High + */ +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name CAPL - SCT_CAPL register */ +/*! @{ */ + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) +/*! @} */ + +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) + +/*! @name CAPH - SCT_CAPH register */ +/*! @{ */ + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) +/*! @} */ + +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) + +/*! @name CAP - Capture Value */ +/*! @{ */ + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - Capture n Low + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - Capture n High + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) + +/*! @name MATCHL - SCT_MATCHL register */ +/*! @{ */ + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) +/*! @} */ + +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) + +/*! @name MATCHH - SCT_MATCHH register */ +/*! @{ */ + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) +/*! @} */ + +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) + +/*! @name MATCH - Match Value */ +/*! @{ */ + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - Match n Low + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - Match n High + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name FRACMAT - Fractional Match */ +/*! @{ */ + +#define SCT_FRACMAT_FRACMAT_L_MASK (0xFU) +#define SCT_FRACMAT_FRACMAT_L_SHIFT (0U) +/*! FRACMAT_L - Fractional Match Low + */ +#define SCT_FRACMAT_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_L_SHIFT)) & SCT_FRACMAT_FRACMAT_L_MASK) + +#define SCT_FRACMAT_FRACMAT_H_MASK (0xF0000U) +#define SCT_FRACMAT_FRACMAT_H_SHIFT (16U) +/*! FRACMAT_H - Fractional Match High + */ +#define SCT_FRACMAT_FRACMAT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_H_SHIFT)) & SCT_FRACMAT_FRACMAT_H_MASK) +/*! @} */ + +/* The count of SCT_FRACMAT */ +#define SCT_FRACMAT_COUNT (6U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name SCTCAPCTRL_CAPCTRL - Capture Control */ +/*! @{ */ + +#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - Capture Control n Low + */ +#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - Capture Control n High + */ +#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAPCTRL_CAPCTRL */ +#define SCT_SCTCAPCTRL_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - Match Reload Value */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - Reload n Low + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - Reload n High + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name FRACMATREL - Fractional Match Reload */ +/*! @{ */ + +#define SCT_FRACMATREL_FRACMAT_L_MASK (0xFU) +#define SCT_FRACMATREL_FRACMAT_L_SHIFT (0U) +/*! FRACMAT_L - Reload Fractional Match Low + */ +#define SCT_FRACMATREL_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_FRACMAT_L_SHIFT)) & SCT_FRACMATREL_FRACMAT_L_MASK) + +#define SCT_FRACMATREL_RELFRAC_H_MASK (0xF0000U) +#define SCT_FRACMATREL_RELFRAC_H_SHIFT (16U) +/*! RELFRAC_H - Reload Fractional Match High + */ +#define SCT_FRACMATREL_RELFRAC_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_H_SHIFT)) & SCT_FRACMATREL_RELFRAC_H_MASK) +/*! @} */ + +/* The count of SCT_FRACMATREL */ +#define SCT_FRACMATREL_COUNT (6U) + +/*! @name EV_STATE - Event n State */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - Event State Mask n + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - Event n Control */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Match Select + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - High Event + * 0b0..Low Counter + * 0b1..High Counter + */ +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/Output Select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Input/Output Signal Select + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Input/Output Condition + * 0b00..Low + * 0b01..Rise + * 0b10..Fall + * 0b11..High + */ +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Combination Mode + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) +/*! STATELD - State Load + * 0b0..Add. STATEV value is added into STATE (the carry-out is ignored). + * 0b1..Load. STATEV value is loaded into STATE. + */ +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - State Value + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - Match Mem + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + * 0b11..Reserved + */ +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) + +/*! @name OUT_SET - Output n Set */ +/*! @{ */ + +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - Set + */ +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - Output n Clear */ +/*! @{ */ + +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - Clear + */ +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SECTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SECTRL_Peripheral_Access_Layer SECTRL Peripheral Access Layer + * @{ + */ + +/** SECTRL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t FLASH_MEM_RULE; /**< Flash Memory Rule, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t ROM_MEM_RULE[4]; /**< ROM Memory Rule, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RAMX_MEM_RULE0; /**< RAMX Memory Rule 0, offset: 0x40 */ + uint8_t RESERVED_3[28]; + __IO uint32_t FLEXSPI0_REGION0_MEM_RULE[4]; /**< FLEXSPI0 Region 0 Memory Rule, array offset: 0x60, array step: 0x4 */ + struct { /* offset: 0x70, array step: 0x10 */ + __IO uint32_t FLEXSPI0_REGION_MEM_RULE0; /**< FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 4 Memory Rule 0, array offset: 0x70, array step: 0x10 */ + uint8_t RESERVED_0[12]; + } FLEXSPI0_REGION1_4_MEM_RULE[4]; + uint8_t RESERVED_4[16]; + __IO uint32_t RAM00_MEM_RULE0; /**< SRAM0 Partition 0 Memory Rule, offset: 0xC0 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RAM10_MEM_RULE0; /**< SRAM1 Partition 0 Memory Rule, offset: 0xE0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RAM20_MEM_RULE0; /**< SRAM2 Partition 0 Memory Rule, offset: 0x100 */ + uint8_t RESERVED_7[28]; + __IO uint32_t RAM30_MEM_RULE0; /**< SRAM Partition 0 Memory Rule, offset: 0x120 */ + uint8_t RESERVED_8[28]; + __IO uint32_t RAM40_MEM_RULE0; /**< SRAM4 Partition 0 Memory Rule, offset: 0x140 */ + uint8_t RESERVED_9[28]; + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0; /**< APB Bridge Group 0 Memory Rule 0, offset: 0x160 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1; /**< APB Bridge Group 0 Memory Rule 1, offset: 0x164 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2; /**< APB Bridge Group 0 Rule 2, offset: 0x168 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3; /**< APB Bridge Group 0 Memory Rule 3, offset: 0x16C */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0; /**< APB Bridge Group 1 Memory Rule 0, offset: 0x170 */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1; /**< APB Bridge Group 1 Memory Rule 1, offset: 0x174 */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2; /**< APB Bridge Group 1 Memory Rule 2, offset: 0x178 */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE3; /**< APB Bridge Group 1 Memory Rule 3, offset: 0x17C */ + uint8_t RESERVED_10[16]; + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port9 Rule 0, offset: 0x190 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 9 Rule 1, offset: 0x194 */ + uint8_t RESERVED_11[8]; + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0; /**< AHB Peripheral 1 Slave Port 10 Slave Rule 0, offset: 0x1A0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0; /**< AHB Peripheral 2 Slave Port 11 Slave Rule 0, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0; /**< AHB Secure Control Peripheral Memory Rule 0, offset: 0x1C0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t AIPS_BRIDGE_GROUP0_RULE0; /**< AIPS Bridge Group 0 Rule 0, offset: 0x1E0 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_RULE1; /**< AIPS Bridge Group 0 Rule 1, offset: 0x1E4 */ + uint8_t RESERVED_15[24]; + __IO uint32_t AIPS_BRIDGE_GROUP1_RULE0; /**< AIPS Bridge Group 1 Rule 0, offset: 0x200 */ + __IO uint32_t AIPS_BRIDGE_GROUP1_RULE1; /**< AIPS Bridge Group 1 Rule 1, offset: 0x204 */ + uint8_t RESERVED_16[3064]; + __I uint32_t SEC_VIO_ADDR[32]; /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */ + __I uint32_t SEC_VIO_MISC_INFO[32]; /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */ + __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address, offset: 0xF00 */ + uint8_t RESERVED_17[124]; + __IO uint32_t SEC_GPIO_MASK[3]; /**< GPIO Mask for Port 0..GPIO Mask for Port 2, array offset: 0xF80, array step: 0x4 */ + __IO uint32_t SEC_GPIO_MASK3; /**< GPIO Mask for Port 3, offset: 0xF8C */ + uint8_t RESERVED_18[44]; + __IO uint32_t SEC_GP_REG_LOCK; /**< Secure Mask Lock, offset: 0xFBC */ + uint8_t RESERVED_19[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level, offset: 0xFD4 */ + uint8_t RESERVED_20[20]; + __IO uint32_t CM33_LOCK_REG[3]; /**< Miscellaneous CPU0 Control Signals, array offset: 0xFEC, array step: 0x4 */ + __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< Secure Control, offset: 0xFFC */ +} SECTRL_Type; + +/* ---------------------------------------------------------------------------- + -- SECTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SECTRL_Register_Masks SECTRL Register Masks + * @{ + */ + +/*! @name FLASH_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define SECTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define SECTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define SECTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define SECTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define SECTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define SECTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define SECTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define SECTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define SECTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define SECTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name ROM_MEM_RULE - ROM Memory Rule */ +/*! @{ */ + +#define SECTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define SECTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE0_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE0_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define SECTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE1_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE1_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define SECTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE2_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE2_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define SECTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE3_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE3_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define SECTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE4_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE4_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define SECTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE5_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE5_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define SECTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE6_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE6_MASK) + +#define SECTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define SECTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE7_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of SECTRL_ROM_MEM_RULE */ +#define SECTRL_ROM_MEM_RULE_COUNT (4U) + +/*! @name RAMX_MEM_RULE0 - RAMX Memory Rule 0 */ +/*! @{ */ + +#define SECTRL_RAMX_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_RAMX_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAMX_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE0_MASK) + +#define SECTRL_RAMX_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_RAMX_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAMX_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE1_MASK) + +#define SECTRL_RAMX_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_RAMX_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAMX_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE2_MASK) + +#define SECTRL_RAMX_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_RAMX_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAMX_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name FLEXSPI0_REGION0_MEM_RULE - FLEXSPI0 Region 0 Memory Rule */ +/*! @{ */ + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK (0x3U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK (0x30U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK (0x300U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK (0x3000U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK (0x30000U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK (0x300000U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK (0x3000000U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK) + +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK (0x30000000U) +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of SECTRL_FLEXSPI0_REGION0_MEM_RULE */ +#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_COUNT (4U) + +/*! @name FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 4 Memory Rule 0 */ +/*! @{ */ + +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK) + +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK) + +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK) + +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/* The count of SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */ +#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (4U) + +/*! @name RAM00_MEM_RULE0 - SRAM0 Partition 0 Memory Rule */ +/*! @{ */ + +#define SECTRL_RAM00_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_RAM00_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM00_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE0_MASK) + +#define SECTRL_RAM00_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_RAM00_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM00_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE1_MASK) + +#define SECTRL_RAM00_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_RAM00_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM00_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE2_MASK) + +#define SECTRL_RAM00_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_RAM00_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM00_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name RAM10_MEM_RULE0 - SRAM1 Partition 0 Memory Rule */ +/*! @{ */ + +#define SECTRL_RAM10_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_RAM10_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM10_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE0_MASK) + +#define SECTRL_RAM10_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_RAM10_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM10_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE1_MASK) + +#define SECTRL_RAM10_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_RAM10_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM10_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE2_MASK) + +#define SECTRL_RAM10_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_RAM10_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM10_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name RAM20_MEM_RULE0 - SRAM2 Partition 0 Memory Rule */ +/*! @{ */ + +#define SECTRL_RAM20_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_RAM20_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM20_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE0_MASK) + +#define SECTRL_RAM20_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_RAM20_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM20_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE1_MASK) + +#define SECTRL_RAM20_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_RAM20_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM20_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE2_MASK) + +#define SECTRL_RAM20_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_RAM20_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM20_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name RAM30_MEM_RULE0 - SRAM Partition 0 Memory Rule */ +/*! @{ */ + +#define SECTRL_RAM30_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_RAM30_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM30_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE0_MASK) + +#define SECTRL_RAM30_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_RAM30_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM30_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE1_MASK) + +#define SECTRL_RAM30_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_RAM30_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM30_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE2_MASK) + +#define SECTRL_RAM30_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_RAM30_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM30_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name RAM40_MEM_RULE0 - SRAM4 Partition 0 Memory Rule */ +/*! @{ */ + +#define SECTRL_RAM40_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_RAM40_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM40_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE0_MASK) + +#define SECTRL_RAM40_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_RAM40_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM40_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE1_MASK) + +#define SECTRL_RAM40_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_RAM40_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM40_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE2_MASK) + +#define SECTRL_RAM40_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_RAM40_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_RAM40_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U) +/*! SYSCON - SYSCON + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_MASK (0x30U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_SHIFT (4U) +/*! IOCON - IOCON + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_MASK (0x300U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_SHIFT (8U) +/*! GPIO0 - GPIO0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_MASK (0x3000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_SHIFT (12U) +/*! GPIO1 - GPIO1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) +/*! PINT0 - PINT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_SHIFT (20U) +/*! PINT1 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_MASK (0x3000000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_SHIFT (24U) +/*! GINT1 - GINT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x3U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (0U) +/*! CTIMER0 - CTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x30U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (4U) +/*! CTIMER1 - CTIMER 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_MASK (0x30000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_SHIFT (16U) +/*! WWDT0 - WWDT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_SHIFT (20U) +/*! MRT - MRT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_MASK (0x3000000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_SHIFT (24U) +/*! MICRO_TICK - MICRO_TICK + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_MASK (0x30000000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_SHIFT (28U) +/*! ITRC - ITRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_MASK (0x3000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_SHIFT (12U) +/*! ANALOG_CTRL - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_SHIFT (20U) +/*! eFUSE - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_MASK (0x3000000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_SHIFT (24U) +/*! I3C0 - I3C0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_SHIFT (20U) +/*! EZH - EZH + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_MASK (0x3U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_SHIFT (0U) +/*! PMC - PMC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_MASK (0x3000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_SHIFT (12U) +/*! SYSCTL_I2S - SYSCTL(I2S Pin Sharing) + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_MASK (0x30000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_SHIFT (16U) +/*! SPI_MSFT - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_MASK (0x3U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_SHIFT (0U) +/*! CTIMER2 - CTIMER2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_MASK (0x30U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_SHIFT (4U) +/*! CTIMER3 - CTIMER3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_MASK (0x300U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_SHIFT (8U) +/*! CTIMER4 - CTIMER4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_MASK (0x30000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_SHIFT (16U) +/*! RTC - RTC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_SHIFT (20U) +/*! OS_EVENT_TIMER - OS_EVENT_TIMER + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_MASK (0x3000000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_SHIFT (24U) +/*! CACHE64_POLSEL - CACHE64_POLSEL + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x30000000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (28U) +/*! PKC - PKC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_MASK (0x3U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_SHIFT (0U) +/*! CSSV2MINI_ALIAS0 - CSSV2MINI ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_MASK (0x30U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_SHIFT (4U) +/*! CSSV2MINI_ALIAS1 - CSSV2MINI ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_MASK (0x300U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_SHIFT (8U) +/*! CSSV2MINI_ALIAS2 - CSSV2MINI ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_MASK (0x3000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_SHIFT (12U) +/*! CSSV2MINI_ALIAS3 - CSSV2MINI ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_MASK (0x30000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_SHIFT (16U) +/*! FLASH_CONTROLLER - Flash controller + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_SHIFT (20U) +/*! PRINCE0 - PRINCE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE3 - APB Bridge Group 1 Memory Rule 3 */ +/*! @{ */ + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_MASK (0x300U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_SHIFT (8U) +/*! PUF_ALIAS0 - PUF_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_MASK (0x3000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_SHIFT (12U) +/*! PUF_ALIAS1 - PUF_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_MASK (0x30000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_SHIFT (16U) +/*! PUF_ALIAS2 - PUF_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_MASK (0x300000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_SHIFT (20U) +/*! PUF_ALIAS3 - PUF_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_MASK) + +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_MASK (0x3000000U) +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_SHIFT (24U) +/*! ROM - ROM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0 - AHB Peripheral 0 Slave Port9 Rule 0 */ +/*! @{ */ + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_MASK (0x3U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_SHIFT (0U) +/*! DMA0 - DMA0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_MASK (0x30U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_SHIFT (4U) +/*! USB_FSD - USB FSD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_MASK (0x300U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_SHIFT (8U) +/*! SCTIMER - SCTIMER + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_MASK (0x3000U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_SHIFT (12U) +/*! FLEXCOMM0 - FLEXCOMM 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_MASK (0x30000U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_SHIFT (16U) +/*! FLEXCOMM1 - FLEXCOMM 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_MASK (0x300000U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_SHIFT (20U) +/*! FLEXCOMM2 - FLEXCOMM 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_MASK (0x3000000U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_SHIFT (24U) +/*! FLEXCOMM3 - FLEXCOMM 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_MASK (0x30000000U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_SHIFT (28U) +/*! FLEXCOMM4 - FLEXCOMM4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 9 Rule 1 */ +/*! @{ */ + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_MASK (0x3U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_SHIFT (0U) +/*! MAILBOX - MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_MASK) + +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_MASK (0x30U) +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_SHIFT (4U) +/*! GPIO - GPIO + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0 - AHB Peripheral 1 Slave Port 10 Slave Rule 0 */ +/*! @{ */ + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_MASK (0x3U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_SHIFT (0U) +/*! DMIC0 - DMIC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_MASK (0x30U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_SHIFT (4U) +/*! CRC - CRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_MASK (0x300U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_SHIFT (8U) +/*! FLEXCOMM5 - FLEXCOMM 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_MASK (0x3000U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_SHIFT (12U) +/*! FLEXCOMM6 - FLEXCOMM 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_MASK (0x30000U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_SHIFT (16U) +/*! FLEXCOMM7 - FLEXCOMM 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_MASK (0x300000U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_SHIFT (20U) +/*! DEBUG_MAILBOX - FLEXCOMM 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_MASK (0x3000000U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_SHIFT (24U) +/*! MCAN - FLEXCOMM 14 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_MASK) + +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_MASK (0x30000000U) +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - FLEXCOMM 15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0 - AHB Peripheral 2 Slave Port 11 Slave Rule 0 */ +/*! @{ */ + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_MASK (0x3U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_SHIFT (0U) +/*! ADC - ADC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_MASK) + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_MASK (0x30U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_SHIFT (4U) +/*! CDOG - Code Watch Dog timer + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_MASK) + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_MASK (0x300U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_SHIFT (8U) +/*! USB_FS_HOST - USB FS HOST + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_MASK) + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_MASK (0x3000U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_SHIFT (12U) +/*! POWERQUAD - POWERQUAD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_MASK) + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_MASK (0x30000U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_SHIFT (16U) +/*! DMA1 - DMA1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_MASK) + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_MASK (0x300000U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_SHIFT (20U) +/*! SECGPIO - SECGPIO + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_MASK) + +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_MASK (0x3000000U) +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_SHIFT (24U) +/*! AHB_SECURE - AHB_SECURE + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_MASK) +/*! @} */ + +/*! @name AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0 - AHB Secure Control Peripheral Memory Rule 0 */ +/*! @{ */ + +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_MASK (0x3U) +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_MASK) + +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_MASK (0x30U) +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_MASK) + +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_MASK (0x300U) +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_MASK) + +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_MASK (0x3000U) +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_RULE0 - AIPS Bridge Group 0 Rule 0 */ +/*! @{ */ + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_MASK (0x30U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_SHIFT (4U) +/*! ADC1 - ADC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_MASK (0x300U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_SHIFT (8U) +/*! DAC0 - DAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_MASK (0x3000U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_SHIFT (12U) +/*! HSCOMP0 - HSCOMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_MASK (0x30000U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_SHIFT (16U) +/*! OPAMP0 - OPAMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_MASK (0x300000U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_SHIFT (20U) +/*! VREF - VREF + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_MASK (0x3000000U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_SHIFT (24U) +/*! DAC1 - DAC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_MASK (0x30000000U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_SHIFT (28U) +/*! HSCOMP1 - HSCOMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_RULE1 - AIPS Bridge Group 0 Rule 1 */ +/*! @{ */ + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_MASK (0x3U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_SHIFT (0U) +/*! OPAMP1 - OPAMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_MASK (0x30U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_SHIFT (4U) +/*! DAC2 - DAC2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_MASK (0x300U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_SHIFT (8U) +/*! HSCOMP2 - HSCOMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_MASK (0x3000U) +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_SHIFT (12U) +/*! OPAMP2 - OPAMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_RULE0 - AIPS Bridge Group 1 Rule 0 */ +/*! @{ */ + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_MASK (0x3U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_SHIFT (0U) +/*! FLEXSPI0 - FLEXSPI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_MASK (0x30U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_SHIFT (4U) +/*! FLEXSPI_CMX - FLEXSPI_CMX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_MASK (0x300U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_SHIFT (8U) +/*! LPCAC - LPCAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_MASK (0x3000U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_SHIFT (12U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_MASK (0x30000U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_SHIFT (16U) +/*! ENC0 - FLEXSPI0 Registers + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_MASK (0x300000U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_SHIFT (20U) +/*! FLEXSPI_PWM1 - FLEXSPI_PWM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_MASK (0x3000000U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_SHIFT (24U) +/*! ENC1 - ENC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_MASK) + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_MASK (0x30000000U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_SHIFT (28U) +/*! AOI0 - AOI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_RULE1 - AIPS Bridge Group 1 Rule 1 */ +/*! @{ */ + +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_MASK (0x3U) +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_SHIFT (0U) +/*! AOI1 - RNG (Random Number Generator) + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_MASK) +/*! @} */ + +/*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */ +/*! @{ */ + +#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK (0xFFFFFFFFU) +#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator + */ +#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT)) & SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK) +/*! @} */ + +/* The count of SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR */ +#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT (32U) + +/*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */ +/*! @{ */ + +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator + * 0b0..Read access + * 0b1..Write access + */ +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access + * 0b0..Code + * 0b1..Data + */ +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level + */ +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - Security violation master number + * 0b0000..M33 Code + * 0b0001..M33 System + * 0b0010..DMA0 + * 0b0011..DMA1 + * 0b0100..USBFS Device + * 0b0101..USBFS Host + * 0b0110..EZH Instruction + * 0b0111..EZH Data + * 0b1000..CSSV2 + * 0b1001..MCAN + * 0b1010..PKC M0 + * 0b1011..GPU + * 0b1100..DSP Data + * 0b1101..DSP Instruction + * 0b1110..Reserved + * 0b1111..Reserved + */ +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */ +#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U) + +/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */ +/*! @{ */ + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) +/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) +/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) +/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) +/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) +/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) +/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) + +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U) +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U) +/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18 + * 0b0..Not valid + * 0b1..Valid + */ +#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 2 */ +/*! @{ */ + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_MASK (0x1U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO2_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_MASK (0x2U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO2_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_MASK (0x4U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO2_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_MASK (0x8U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO2_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_MASK (0x10U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO2_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_MASK (0x20U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO2_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_MASK (0x40U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO2_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_MASK (0x80U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO2_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_MASK (0x100U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO2_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_MASK (0x200U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO2_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_MASK (0x400U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO2_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_MASK (0x800U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO2_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_MASK (0x1000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO2_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_MASK (0x2000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO2_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_MASK (0x4000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO2_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_MASK (0x8000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO2_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_MASK (0x10000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO2_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_MASK (0x20000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO2_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_MASK (0x40000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO2_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_MASK (0x80000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO2_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_MASK (0x100000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO2_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_MASK (0x200000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO2_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_MASK (0x400000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO2_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_MASK (0x800000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO2_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_MASK (0x1000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO2_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_MASK (0x2000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO2_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_MASK (0x4000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO2_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_MASK (0x8000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO2_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_MASK (0x10000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO2_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_MASK (0x20000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO2_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_MASK (0x40000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO2_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_MASK (0x80000000U) +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO2_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_MASK) +/*! @} */ + +/* The count of SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK */ +#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (3U) + +/*! @name SEC_GPIO_MASK3 - GPIO Mask for Port 3 */ +/*! @{ */ + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK (0x1U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO3_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK (0x2U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO3_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK (0x4U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO3_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK (0x8U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO3_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK (0x10U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO3_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK (0x20U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO3_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK) + +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_MASK (0x40U) +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO3_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GP_REG_LOCK - Secure Mask Lock */ +/*! @{ */ + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - Secure GPIO _MASK0 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK0 cannot be written + * 0b10..SEC_GPIO_MASK0 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - Secure GPIO _MASK1 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK1 cannot be written + * 0b10..SEC_GPIO_MASK1 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U) +/*! SEC_GPIO_MASK2_LOCK - Secure GPIO _MASK2 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK2 cannot be written + * 0b10..SEC_GPIO_MASK2 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U) +/*! SEC_GPIO_MASK3_LOCK - Secure GPIO _MASK3 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK3 cannot be written + * 0b10..SEC_GPIO_MASK3 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_MASK (0x300U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT (8U) +/*! SEC_GPIO_MASK4_LOCK - SEC_GPIO_MASK4 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK4_LOCK cannot be written + * 0b10..SEC_GPIO_MASK4_LOCK can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_MASK (0xC00U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT (10U) +/*! SEC_GPIO_MASK5_LOCK - SEC_GPIO_MASK5 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK5 cannot be written + * 0b10..SEC_GPIO_MASK5 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_MASK (0x3000U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT (12U) +/*! SEC_GPIO_MASK6_LOCK - SEC_GPIO_MASK6 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK6 cannot be written + * 0b10..SEC_GPIO_MASK6 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_MASK (0xC000U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT (14U) +/*! SEC_GPIO_MASK7_LOCK - SEC_GPIO_MASK7 Lock + * 0b00..Reserved + * 0b01..SEC_GPIO_MASK7 cannot be written + * 0b10..SEC_GPIO_MASK7 can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_MASK) + +#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_MASK (0x30000U) +#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT (16U) +/*! SEC_DSP_INT_MASK_LOCK - SEC_DSP_INT_MASK Lock + * 0b00..Reserved + * 0b01..SEC_DSP_INT_MASK cannot be written + * 0b10..SEC_DSP_INT_MASK can be written + * 0b11..Reserved + */ +#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - Master Secure Level */ +/*! @{ */ + +#define SECTRL_MASTER_SEC_LEVEL_DMA0_MASK (0x30U) +#define SECTRL_MASTER_SEC_LEVEL_DMA0_SHIFT (4U) +/*! DMA0 - DMA0 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DMA0_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DMA0_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_DMA1_MASK (0xC0U) +#define SECTRL_MASTER_SEC_LEVEL_DMA1_SHIFT (6U) +/*! DMA1 - DMA1 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DMA1_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DMA1_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define SECTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USBFS Device + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00U) +#define SECTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (10U) +/*! USBFSH - USBFS Host + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_EZH_D_MASK (0x3000U) +#define SECTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT (12U) +/*! EZH_D - EZH Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_EZH_D_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_EZH_I_MASK (0xC000U) +#define SECTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT (14U) +/*! EZH_I - EZH Instruction + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_EZH_I_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_MCAN_MASK (0xC0000U) +#define SECTRL_MASTER_SEC_LEVEL_MCAN_SHIFT (18U) +/*! MCAN - MCAN + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_MCAN_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_MCAN_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK (0x300000U) +#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT (20U) +/*! POWERQUAD - POWERQUAD + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_PKC_MASK (0xC00000U) +#define SECTRL_MASTER_SEC_LEVEL_PKC_SHIFT (22U) +/*! PKC - PKC + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_PKC_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_PKC_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_DSP_D_MASK (0x3000000U) +#define SECTRL_MASTER_SEC_LEVEL_DSP_D_SHIFT (24U) +/*! DSP_D - DSP Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_DSP_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DSP_D_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DSP_D_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_DSP_I_MASK (0xC000000U) +#define SECTRL_MASTER_SEC_LEVEL_DSP_I_SHIFT (26U) +/*! DSP_I - DSP Instruction + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_LEVEL_DSP_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DSP_I_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DSP_I_MASK) + +#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - Master Security Level Lock + * 0b00..Reserved + * 0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_LOCK) bits + * 0b10..This register can be written + * 0b11..Reserved + */ +#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */ +/*! @{ */ + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK (0x30U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT (4U) +/*! DMA0 - DMA0 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK (0xC0U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT (6U) +/*! DMA1 - DMA1 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USBFS Device + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (10U) +/*! USBFSH - USBFS Host + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK (0x3000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT (12U) +/*! EZH_D - EZH Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK (0xC000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT (14U) +/*! EZH_I - EZH Instruction + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_MASK (0xC0000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_SHIFT (18U) +/*! MCAN - MCAN + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_MASK (0x300000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_SHIFT (20U) +/*! POWERQUAD - POWERQUAD + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_MASK (0xC00000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (22U) +/*! PKC - PKC + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_MASK (0x3000000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_SHIFT (24U) +/*! DSP_D - DSP Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_MASK (0xC000000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_SHIFT (26U) +/*! DSP_I - DSP Instruction + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_MASK) + +#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master Security Level Antipole Lock + * 0b00..Reserved + * 0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_ANTIPOL_LOCK) bits + * 0b10..This register can be written + * 0b11..Reserved + */ +#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CM33_LOCK_REGN_CM33_LOCK_REG - Miscellaneous CPU0 Control Signals */ +/*! @{ */ + +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - LOCK_NS_VTOR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 + * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 + * 0b11..Reserved + */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - LOCK_NS_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 + * 0b11..Reserved + */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_MASK) + +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1 + * 0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0 + * 0b11..Reserved + */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - LOCK_S_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_S_MPU is 0 + * 0b11..Reserved + */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_MASK) + +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - LOCK_SAU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_SAU is 1 + * 0b10..CM33 (CPU0) LOCK_SAU is 0 + * 0b11..Reserved + */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_MASK) + +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) +/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK + * 0b00..Reserved + * 0b01..CM33_LOCK_REG_LOCK is 1 + * 0b10..CM33_LOCK_REG_LOCK is 0 + * 0b11..Reserved + */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/* The count of SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG */ +#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_COUNT (3U) + +/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */ +/*! @{ */ + +#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enabled (restrictive mode) + * 0b10..Disabled + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enabled (restrictive mode) + * 0b10..Disabled + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enabled (restrictive mode) + * 0b10..Disabled + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..AHB master in strict mode + * 0b01..AHB master in tier mode. Can read and write to memories at same or below level. + * 0b10..AHB master in strict mode + * 0b11..AHB master in strict mode + */ +#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) + +#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - Secure Control */ +/*! @{ */ + +#define SECTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define SECTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & SECTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enabled (restrictive mode) + * 0b10..Disabled + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enabled (restrictive mode) + * 0b10..Disabled + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enabled (restrictive mode) + * 0b10..Disabled + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..AHB master in strict mode + * 0b01..AHB master in tier mode. Can read and write to memories at same or below level. + * 0b10..AHB master in strict mode + * 0b11..AHB master in strict mode + */ +#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK) + +#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SECTRL_Register_Masks */ + + +/* SECTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SECTRL0 base address */ + #define SECTRL0_BASE (0x500AC000u) + /** Peripheral SECTRL0 base address */ + #define SECTRL0_BASE_NS (0x400AC000u) + /** Peripheral SECTRL0 base pointer */ + #define SECTRL0 ((SECTRL_Type *)SECTRL0_BASE) + /** Peripheral SECTRL0 base pointer */ + #define SECTRL0_NS ((SECTRL_Type *)SECTRL0_BASE_NS) + /** Array initializer of SECTRL peripheral base addresses */ + #define SECTRL_BASE_ADDRS { SECTRL0_BASE } + /** Array initializer of SECTRL peripheral base pointers */ + #define SECTRL_BASE_PTRS { SECTRL0 } + /** Array initializer of SECTRL peripheral base addresses */ + #define SECTRL_BASE_ADDRS_NS { SECTRL0_BASE_NS } + /** Array initializer of SECTRL peripheral base pointers */ + #define SECTRL_BASE_PTRS_NS { SECTRL0_NS } +#else + /** Peripheral SECTRL0 base address */ + #define SECTRL0_BASE (0x400AC000u) + /** Peripheral SECTRL0 base pointer */ + #define SECTRL0 ((SECTRL_Type *)SECTRL0_BASE) + /** Array initializer of SECTRL peripheral base addresses */ + #define SECTRL_BASE_ADDRS { SECTRL0_BASE } + /** Array initializer of SECTRL peripheral base pointers */ + #define SECTRL_BASE_PTRS { SECTRL0 } +#endif + +/*! + * @} + */ /* end of group SECTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< Configuration Register, offset: 0x400 */ + __IO uint32_t DLY; /**< Delay Register, offset: 0x404 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x408 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Register, offset: 0x40C */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock Divider Register, offset: 0x424 */ + __I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO Configuration Register, offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO Status Register, offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO Trigger Register, offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable Register, offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear Register, offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status Register, offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO Write Data Register, offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO Read Data Register, offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with no FIFO Pop Register, offset: 0xE40 */ + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO Size Register, offset: 0xE48 */ + __IO uint32_t FIFORXTIMEOUTCFG; /**< FIFO Receive Timeout Configuration, offset: 0xE4C */ + __I uint32_t FIFORXTIMEOUTCNT; /**< FIFO Receive Timeout Counter, offset: 0xE50 */ + uint8_t RESERVED_8[424]; + __I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI Enable + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master Mode Select + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs; MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs; MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First Mode Enable + * 0b0..Standard. Data is transmitted and received in standard MSB-first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase Select + * 0b0..Change + * 0b1..Capture + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity Select + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity Select + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity Select + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity Select + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity Select + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - Delay Register */ +/*! @{ */ + +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Pre-Delay + * 0b0000..No additional time is inserted + * 0b0001..1 SPI clock time is inserted + * 0b0010..2 SPI clock times are inserted + * 0b1111..15 SPI clock times are inserted + */ +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Post-Delay + * 0b0000..No additional time is inserted + * 0b0001..1 SPI clock time is inserted + * 0b0010..2 SPI clock times are inserted + * 0b1111..15 SPI clock times are inserted + */ +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - Frame Delay + * 0b0000..No additional time is inserted + * 0b0001..1 SPI clock time is inserted + * 0b0010..2 SPI clock times are inserted + * 0b1111..15 SPI clock times are inserted + */ +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Transfer Delay + * 0b0000..The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time) + * 0b0001..The minimum time that SSEL is deasserted is 2 SPI clock times + * 0b0010..The minimum time that SSEL is deasserted is 3 SPI clock times + * 0b1111..The minimum time that SSEL is deasserted is 16 SPI clock times + */ +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert + */ +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert + */ +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled Status Flag + */ +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer Control + */ +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle Status Flag + */ +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Register */ +/*! @{ */ + +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave Select Assert Interrupt Enable + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave Select Deassert Interrupt Enable + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master Idle Interrupt Enable + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear Register */ +/*! @{ */ + +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Slave Select Assert Interrupt Enable + * 0b0..No effect + * 0b1..Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN]) + */ +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Slave Select Deassert Interrupt Enable + * 0b0..No effect + * 0b1..Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN]) + */ +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle Interrupt Enable + * 0b0..No effect + * 0b1..Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE]) + */ +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - Clock Divider Register */ +/*! @{ */ + +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate Divider Value + */ +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status Register */ +/*! @{ */ + +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle Status Flag Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO Configuration Register */ +/*! @{ */ + +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the Transmit FIFO + * 0b0..The transmit FIFO is not enabled + * 0b1..The transmit FIFO is enabled + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the Receive FIFO + * 0b0..The receive FIFO is not enabled + * 0b1..The receive FIFO is enabled + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO Size Configuration + * 0b00..FIFO is configured as 16 entries of 8 bits. + * 0b01..FIFO is configured as 8 entries of 16 bits. + * 0b10..Not used + * 0b11..Not used + */ +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA Configuration for Transmit + * 0b0..DMA is not used for the transmit function + * 0b1..Issues DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA Configuration for Receive + * 0b0..DMA is not used for the receive function. + * 0b1..Issues a DMA request for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for Transmit FIFO Level + * 0b0..Only enabled interrupts will wake up the device form reduced power modes + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for Receive FIFO Level + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by + * FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty Command for the Transmit FIFO + * 0b0..No effect + * 0b1..The TX FIFO is emptied + */ +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty Command for the Receive FIFO + * 0b0..No effect + * 0b1..The RX FIFO is emptied + */ +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) + +#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) +#define SPI_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for Debug Reads + * 0b0..Debug reads of the FIFO do not pop the FIFO + * 0b1..A debug read will cause the FIFO to pop + */ +#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO Status Register */ +/*! @{ */ + +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO Error + * 0b0..A transmit FIFO error has not occurred. + * 0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full + * FIFO, or by an underflow if the FIFO is empty when data is needed. + */ +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO Error + * 0b0..A receive FIFO overflow has not occurred + * 0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough + */ +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral Interrupt + * 0b0..The peripheral function has not asserted an interrupt + * 0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by + * reading the peripheral's status register (STAT). + */ +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO Empty + * 0b0..The transmit FIFO is not empty + * 0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data. + */ +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO is Not Full + * 0b0..The transmit FIFO is full and another write would cause it to overflow + * 0b1..The transmit FIFO is not full, so more data can be written + */ +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO is Not Empty + * 0b0..When 0, the receive FIFO is empty + * 0b1..When 1, the receive FIFO is not empty, so data can be read + */ +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO is Full + * 0b0..The receive FIFO is not full + * 0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out. + */ +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO Current Level + */ +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO Current Level + */ +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) + +#define SPI_FIFOSTAT_RXTIMEOUT_MASK (0x1000000U) +#define SPI_FIFOSTAT_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive FIFO Timeout + * 0b0..RX FIFO on + * 0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register. + */ +#define SPI_FIFOSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOSTAT_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO Trigger Register */ +/*! @{ */ + +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO Level Trigger Enable + * 0b0..Transmit FIFO level does not generate a FIFO level trigger + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the FIFOTRIG[TXLVL] field. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO Level Trigger Enable + * 0b0..Receive FIFO level does not generate a FIFO level trigger + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the FIFOTRIG[RXLVL] field. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO Level Trigger Point + * 0b0000..Trigger when the TX FIFO becomes empty + * 0b0001..Trigger when the TX FIFO level decreases to 1 entry + * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full) + */ +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO Level Trigger Point + * 0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty) + * 0b0001..Trigger when the RX FIFO has received 2 entries + * 0b1111..Trigger when the RX FIFO has received 16 entries (has become full) + */ +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO Interrupt Enable Register */ +/*! @{ */ + +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - TX Error Interrupt Enable + * 0b0..No interrupt will be generated for a transmit error + * 0b1..An interrupt will be generated when a transmit error occurs + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Receive Error Interrupt Enable + * 0b0..No interrupt will be generated for a receive error + * 0b1..An interrupt will be generated when a receive error occurs + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Enable + * 0b0..No interrupt will be generated based on the TX FIFO level + * 0b1..If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL] + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Enable + * 0b0..No interrupt will be generated based on the RX FIFO level + * 0b1..If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL] + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) + +#define SPI_FIFOINTENSET_RXTIMEOUT_MASK (0x1000000U) +#define SPI_FIFOINTENSET_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout + * 0b0..No RX interrupt will be generated. + * 0b1..Asserts RX interrupt if RX FIFO Timeout event occurs. + */ +#define SPI_FIFOINTENSET_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENSET_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear Register */ +/*! @{ */ + +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - TX Error Interrupt Enable + * 0b0..No effect + * 0b1..Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR] + */ +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Receive Error Interrupt Enable + * 0b0..No effect + * 0b1..Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR] + */ +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Enable + * 0b0..No effect + * 0b1..Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL] + */ +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Enable + * 0b0..No effect + * 0b1..Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL] + */ +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) + +#define SPI_FIFOINTENCLR_RXTIMEOUT_MASK (0x1000000U) +#define SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define SPI_FIFOINTENCLR_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENCLR_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO Interrupt Status Register */ +/*! @{ */ + +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO Error Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO Error Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) + +#define SPI_FIFOINTSTAT_RXTIMEOUT_MASK (0x1000000U) +#define SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout Status + * 0b0..Not pending + * 0b1..Pending + */ +#define SPI_FIFOINTSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOINTSTAT_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO Write Data Register */ +/*! @{ */ + +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit Data to the FIFO + */ +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit Slave Select 0 + * 0b0..SSEL0 is asserted + * 0b1..SSEL0 is not asserted + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit Slave Select 1 + * 0b0..SSEL1 is asserted + * 0b1..SSEL1 is not asserted + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit Slave Select 2 + * 0b0..SSEL2 is asserted + * 0b1..SSEL2 is not asserted + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit Slave Select 3 + * 0b0..SSEL3 is asserted + * 0b1..SSEL3 is not asserted + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of Transfer + * 0b0..SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of Frame + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore + * 0b0..Read received data. Received data must be read, to allow transmission to proceed. SPI transmit will halt + * when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not + * read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + +#define SPI_FIFOWR_TXIGNORE_MASK (0x800000U) +#define SPI_FIFOWR_TXIGNORE_SHIFT (23U) +/*! TXIGNORE - Transmit Ignore + * 0b0..Write transmit data + * 0b1..Ignore transmit data + */ +#define SPI_FIFOWR_TXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK) + +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length + * 0b0000..Reserved + * 0b0001..Reserved + * 0b0010..Reserved + * 0b0011..Data transfer is 4 bits in length + * 0b0100..Data transfer is 5 bits in length + * 0b1111..Data transfer is 16 bits in length + */ +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO Read Data Register */ +/*! @{ */ + +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select 0 for Receive + * 0b0..Slave Select 0 is active + * 0b1..Slave Select 0 is not active + */ +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select 1 for Receive + * 0b0..Slave Select 1 is active + * 0b1..Slave Select 1 is not active + */ +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select 2 for Receive + * 0b0..Slave Select 2 is active + * 0b1..Slave Select 2 is not active + */ +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select 3 for Receive + * 0b0..Slave Select 3 is active + * 0b1..Slave Select 3 is not active + */ +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer Flag + * 0b0..This is not the 1st data after the SSELs went from deasserted to asserted + * 0b1..This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previous transfer has + * ended). This information can be used to identify the 1st piece of data in cases where the transfer length is + * greater than 16 bits. + */ +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO Data Read with no FIFO Pop Register */ +/*! @{ */ + +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select 0 for Receive + * 0b0..Not selected + * 0b1..Selected + */ +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select 1 for Receive + * 0b0..Not selected + * 0b1..Selected + */ +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select 2 for Receive + * 0b0..Not selected + * 0b1..Selected + */ +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select 3 for Receive + * 0b0..Not selected + * 0b1..Selected + */ +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of Transfer Flag + * 0b0..Not active + * 0b1..Active + */ +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO Size Register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - FIFO Size + */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */ +/*! @{ */ + +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU) +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U) +/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler + */ +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK) + +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U) +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U) +/*! RXTIMEOUT_VALUE - Receive Timeout Value + */ +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK) + +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U) +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U) +/*! RXTIMEOUT_EN - Receive Timeout Enable + * 0b0..Disable RX FIFO timeout + * 0b1..Enable RX FIFO timeout + */ +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK) + +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U) +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U) +/*! RXTIMEOUT_COW - Receive Timeout Continue On Write + * 0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO. + * 0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO. + */ +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK) + +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U) +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U) +/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty + * 0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty. + * 0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty. + */ +#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK) +/*! @} */ + +/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */ +/*! @{ */ + +#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU) +#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U) +/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value + */ +#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK) +/*! @} */ + +/*! @name ID - Peripheral Identification Register */ +/*! @{ */ + +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture + */ +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation + */ +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation + */ +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function + */ +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI_FILTER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_FILTER_Peripheral_Access_Layer SPI_FILTER Peripheral Access Layer + * @{ + */ + +/** SPI_FILTER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control, offset: 0x0 */ + __I uint32_t ISR; /**< Interrupt Register, offset: 0x4 */ + __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0x8 */ + __I uint32_t SR; /**< Status Register, offset: 0xC */ + __IO uint32_t TCR; /**< Test Control Register, offset: 0x10 */ + __IO uint32_t P0FAR1; /**< Port 0 filter address region 1, offset: 0x14 */ + __IO uint32_t P0FAR2; /**< Port 0 filter address region 2, offset: 0x18 */ + __IO uint32_t P0FAR3; /**< Port 0 filter address region 3, offset: 0x1C */ + __IO uint32_t P1FAR1; /**< Port 1 filter address region 1, offset: 0x20 */ + __IO uint32_t P1FAR2; /**< Port 1 filter address region 2, offset: 0x24 */ + __IO uint32_t P1FAR3; /**< Port 1 filter address region 3, offset: 0x28 */ + uint8_t RESERVED_0[4]; + __I uint32_t VER; /**< Version, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t POPCODE0; /**< Programmable OP-Code0, offset: 0x40 */ + __IO uint32_t POPCODE1; /**< Programmable OP-Code1, offset: 0x44 */ + __IO uint32_t POPCODE2; /**< Programmable OP-Code2, offset: 0x48 */ + __IO uint32_t POPCODE3; /**< Programmable OP-Code3, offset: 0x4C */ + __IO uint32_t POPCODE4; /**< Programmable OP-Code4, offset: 0x50 */ + __I uint32_t P0BOC; /**< P0 Blocked Op Code, offset: 0x54 */ + __I uint32_t P1BOC; /**< P1 Blocked Op Code, offset: 0x58 */ + __IO uint32_t P0MAM; /**< Port 0 Max Address Mask, offset: 0x5C */ + __IO uint32_t P1MAM; /**< Port 1 Max Address Mask, offset: 0x60 */ +} SPI_FILTER_Type; + +/* ---------------------------------------------------------------------------- + -- SPI_FILTER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_FILTER_Register_Masks SPI_FILTER Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define SPI_FILTER_CR_P1_ACT_SEL_MASK (0x10000U) +#define SPI_FILTER_CR_P1_ACT_SEL_SHIFT (16U) +/*! P1_ACT_SEL - Active Chip Select for P1 filter + * 0b0..Sets CS0 as the read location for the firmware image and sets CS1 as the write location for the FW image. + * 0b1..Sets CS1 as the read location for the firmware image and sets CS0 as the write location for the FW image. + */ +#define SPI_FILTER_CR_P1_ACT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_ACT_SEL_SHIFT)) & SPI_FILTER_CR_P1_ACT_SEL_MASK) + +#define SPI_FILTER_CR_P1_BYTE_SEL_MASK (0x20000U) +#define SPI_FILTER_CR_P1_BYTE_SEL_SHIFT (17U) +/*! P1_BYTE_SEL - Address Byte Select Mode for P1 + * 0b0..Sets the filter to 4-byte address mode + * 0b1..Sets the filter to 3-byte address mode + */ +#define SPI_FILTER_CR_P1_BYTE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_BYTE_SEL_SHIFT)) & SPI_FILTER_CR_P1_BYTE_SEL_MASK) + +#define SPI_FILTER_CR_P1_BYTE_SEL_MD_MASK (0x40000U) +#define SPI_FILTER_CR_P1_BYTE_SEL_MD_SHIFT (18U) +/*! P1_BYTE_SEL_MD - Address Byte Select Mode for P1 + * 0b0..Normal Operation. The Address byte mode is determined by the Op Code Command + * 0b1..Sets the Byte Mode to 3-byte and gives control of the function to the P1_BYTE_SEL in the P1 Filter + * Control Register. In this mode, any changes to P1_BYTE_SEL are latched and the internal state of P1_BYTE_SEL + * will retain this value when P1_BYTE_SEL_MD is cleared + */ +#define SPI_FILTER_CR_P1_BYTE_SEL_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_BYTE_SEL_MD_SHIFT)) & SPI_FILTER_CR_P1_BYTE_SEL_MD_MASK) + +#define SPI_FILTER_CR_P1_DIRTY_CLR_MASK (0x80000U) +#define SPI_FILTER_CR_P1_DIRTY_CLR_SHIFT (19U) +/*! P1_DIRTY_CLR - Clear dirty state for P1 + */ +#define SPI_FILTER_CR_P1_DIRTY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_DIRTY_CLR_SHIFT)) & SPI_FILTER_CR_P1_DIRTY_CLR_MASK) + +#define SPI_FILTER_CR_P1_FLT_EN_MASK (0x100000U) +#define SPI_FILTER_CR_P1_FLT_EN_SHIFT (20U) +/*! P1_FLT_EN - Filter Enable bit for P1 filter + * 0b0..Filter Disabled. All CS Disable outputs are asserted so that host access to the flash devices is + * disabled. CS# inputs to the filter are disabled so that the filter state machine is locked in its current state. + * All register controls remain functional. + * 0b1..Filter Enabled. CS# inputs to the filter are enabled and the filter state machine controls the CS disable + * outputs. This bit takes priority over the P1_BYP_EN bit in the Test Control Register. Setting this bit + * will enable filtering and will enable communication to flash devices regardless of the state of P1_BYP_EN. + * All other register controls remain functional while filtering is enabled. + */ +#define SPI_FILTER_CR_P1_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_FLT_EN_SHIFT)) & SPI_FILTER_CR_P1_FLT_EN_MASK) + +#define SPI_FILTER_CR_P1_FLASH_MD_MASK (0x200000U) +#define SPI_FILTER_CR_P1_FLASH_MD_SHIFT (21U) +/*! P1_FLASH_MD - Flash Mode Select for P1 + * 0b0..Dual Flash Mode. Supports two separate physical flash devices as described in Section 3.1 + * 0b1..Single Flash Mode. Supports a single physical flash device as described in Section 3.2. Note that all + * Chip Erase Op Codes are blocked when in this mode. + */ +#define SPI_FILTER_CR_P1_FLASH_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_FLASH_MD_SHIFT)) & SPI_FILTER_CR_P1_FLASH_MD_MASK) + +#define SPI_FILTER_CR_P0_ACT_SEL_MASK (0x1000000U) +#define SPI_FILTER_CR_P0_ACT_SEL_SHIFT (24U) +/*! P0_ACT_SEL - Active Chip Select for P0 filter + * 0b0..Sets CS0 as the read location for the firmware image and sets CS1 as the write location for the FW image. + * 0b1..Sets CS1 as the read location for the firmware image and sets CS0 as the write location for the FW image. + */ +#define SPI_FILTER_CR_P0_ACT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_ACT_SEL_SHIFT)) & SPI_FILTER_CR_P0_ACT_SEL_MASK) + +#define SPI_FILTER_CR_P0_BYTE_SEL_MASK (0x2000000U) +#define SPI_FILTER_CR_P0_BYTE_SEL_SHIFT (25U) +/*! P0_BYTE_SEL - Address Byte Select for P0 filter + * 0b0..Sets the filter to 3-byte address mode + * 0b1..Sets the filter to 4-byte address mode + */ +#define SPI_FILTER_CR_P0_BYTE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_BYTE_SEL_SHIFT)) & SPI_FILTER_CR_P0_BYTE_SEL_MASK) + +#define SPI_FILTER_CR_P0_BYTE_SEL_MD_MASK (0x4000000U) +#define SPI_FILTER_CR_P0_BYTE_SEL_MD_SHIFT (26U) +/*! P0_BYTE_SEL_MD - Address Byte Select Mode for P0 filter + * 0b0..Normal Operation. The Address byte mode is determined by the Op Code Command + * 0b1..Sets the Byte Mode to 3-byte and gives control of the function to the P0_BYTE_SEL in the P0 Filter + * Control Register. In this mode, any changes to P0_BYTE_SEL are latched and the internal state of BYTE_SEL will + * retain this value when P0_BYTE_SEL_MD is cleared. + */ +#define SPI_FILTER_CR_P0_BYTE_SEL_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_BYTE_SEL_MD_SHIFT)) & SPI_FILTER_CR_P0_BYTE_SEL_MD_MASK) + +#define SPI_FILTER_CR_P0_DIRTY_CLR_MASK (0x8000000U) +#define SPI_FILTER_CR_P0_DIRTY_CLR_SHIFT (27U) +/*! P0_DIRTY_CLR - Clear dirty state for P0 + */ +#define SPI_FILTER_CR_P0_DIRTY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_DIRTY_CLR_SHIFT)) & SPI_FILTER_CR_P0_DIRTY_CLR_MASK) + +#define SPI_FILTER_CR_P0_FLT_EN_MASK (0x10000000U) +#define SPI_FILTER_CR_P0_FLT_EN_SHIFT (28U) +/*! P0_FLT_EN - Filter Enable bit for P0 + * 0b0..Filter Enabled. CS# inputs to the filter are enabled and the filter state machine controls the CS disable + * outputs. CS# inputs to the filter are enabled so that the filter state machine is active. All other + * register controls are functional. + * 0b1..Filter Disabled. All CS Disable outputs are asserted so that host access to the flash devices is + * disabled. CS# inputs to the filter are disabled so that the filter state machine is locked in its current state. + * All other register controls can be accessed, but have no impact on the functionality of the filter while + * the filter is disabled. + */ +#define SPI_FILTER_CR_P0_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_FLT_EN_SHIFT)) & SPI_FILTER_CR_P0_FLT_EN_MASK) + +#define SPI_FILTER_CR_P0_FLASH_MD_MASK (0x20000000U) +#define SPI_FILTER_CR_P0_FLASH_MD_SHIFT (29U) +/*! P0_FLASH_MD - Flash Mode Select for P0 + * 0b0..Dual Flash Mode. Supports two separate physical flash devices as described in Section 3.1 + * 0b1..Single Flash Mode. Supports a single physical flash device as described in Section 3.2. Note that all + * Chip Erase Op Codes are blocked when in this mode. + */ +#define SPI_FILTER_CR_P0_FLASH_MD(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_FLASH_MD_SHIFT)) & SPI_FILTER_CR_P0_FLASH_MD_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Register */ +/*! @{ */ + +#define SPI_FILTER_ISR_P0_DIRTY_INT_MASK (0x1000000U) +#define SPI_FILTER_ISR_P0_DIRTY_INT_SHIFT (24U) +/*! P0_DIRTY_INT + * 0b0..Indicates that a write has occurred to the FW Code region of the inactive Flash and that flash is now considered corrupt + * 0b1..Indicates normal operation + */ +#define SPI_FILTER_ISR_P0_DIRTY_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_DIRTY_INT_SHIFT)) & SPI_FILTER_ISR_P0_DIRTY_INT_MASK) + +#define SPI_FILTER_ISR_P1_DIRTY_INT_MASK (0x2000000U) +#define SPI_FILTER_ISR_P1_DIRTY_INT_SHIFT (25U) +/*! P1_DIRTY_INT + * 0b0..Indicates normal operation + * 0b1..indicates that a write has occurred to the FW Code region of the inactive Flash and that flash is now considered corrupt + */ +#define SPI_FILTER_ISR_P1_DIRTY_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_DIRTY_INT_SHIFT)) & SPI_FILTER_ISR_P1_DIRTY_INT_MASK) + +#define SPI_FILTER_ISR_P0_BLK_INT_MASK (0x4000000U) +#define SPI_FILTER_ISR_P0_BLK_INT_SHIFT (26U) +/*! P0_BLK_INT + * 0b0..Indicates normal operation + * 0b1..Indicates that a blocked opcode has been detected + */ +#define SPI_FILTER_ISR_P0_BLK_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_BLK_INT_SHIFT)) & SPI_FILTER_ISR_P0_BLK_INT_MASK) + +#define SPI_FILTER_ISR_P1_BLK_INT_MASK (0x8000000U) +#define SPI_FILTER_ISR_P1_BLK_INT_SHIFT (27U) +/*! P1_BLK_INT + * 0b0..Indicates normal operation + * 0b1..Indicates that a blocked opcode has been detected + */ +#define SPI_FILTER_ISR_P1_BLK_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_BLK_INT_SHIFT)) & SPI_FILTER_ISR_P1_BLK_INT_MASK) + +#define SPI_FILTER_ISR_P0_BYTEMODE_INT_MASK (0x10000000U) +#define SPI_FILTER_ISR_P0_BYTEMODE_INT_SHIFT (28U) +/*! P0_BYTEMODE_INT + * 0b0..Indicates normal operation + * 0b1..Indicates that a Bytemode change has been detected (OpCode E9 or B7) + */ +#define SPI_FILTER_ISR_P0_BYTEMODE_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_BYTEMODE_INT_SHIFT)) & SPI_FILTER_ISR_P0_BYTEMODE_INT_MASK) + +#define SPI_FILTER_ISR_P1_BYTEMODE_INT_MASK (0x20000000U) +#define SPI_FILTER_ISR_P1_BYTEMODE_INT_SHIFT (29U) +/*! P1_BYTEMODE_INT + * 0b0..Indicates normal operation + * 0b1..Indicates that a Bytemode change has been detected (OpCode E9 or B7) + */ +#define SPI_FILTER_ISR_P1_BYTEMODE_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_BYTEMODE_INT_SHIFT)) & SPI_FILTER_ISR_P1_BYTEMODE_INT_MASK) + +#define SPI_FILTER_ISR_P0_F8_INT_MASK (0x40000000U) +#define SPI_FILTER_ISR_P0_F8_INT_SHIFT (30U) +/*! P0_F8_INT + * 0b0..Indicates normal operation + * 0b1..Indicates an F8 command has been detected + */ +#define SPI_FILTER_ISR_P0_F8_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_F8_INT_SHIFT)) & SPI_FILTER_ISR_P0_F8_INT_MASK) + +#define SPI_FILTER_ISR_P1_F8_INT_MASK (0x80000000U) +#define SPI_FILTER_ISR_P1_F8_INT_SHIFT (31U) +/*! P1_F8_INT + * 0b0..Indicates normal operation + * 0b1..Indicates an F8 command has been detected + */ +#define SPI_FILTER_ISR_P1_F8_INT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_F8_INT_SHIFT)) & SPI_FILTER_ISR_P1_F8_INT_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask Register */ +/*! @{ */ + +#define SPI_FILTER_IMR_P0_DIRTY_MASK_MASK (0x1000000U) +#define SPI_FILTER_IMR_P0_DIRTY_MASK_SHIFT (24U) +/*! P0_DIRTY_MASK - Mask bit for P0_DIRTY_INT + * 0b0..Indicates P0_DIRTY_INT interrupt is disabled. + * 0b1..Indicates P0_DIRTY_INT interrupt is enabled. + */ +#define SPI_FILTER_IMR_P0_DIRTY_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_DIRTY_MASK_SHIFT)) & SPI_FILTER_IMR_P0_DIRTY_MASK_MASK) + +#define SPI_FILTER_IMR_P1_DIRTY_MASK_MASK (0x2000000U) +#define SPI_FILTER_IMR_P1_DIRTY_MASK_SHIFT (25U) +/*! P1_DIRTY_MASK - Mask bit for P1_DIRTY_INT + * 0b0..Indicates normal operation. P1_DIRTY_INT interrupt is enabled. + * 0b1..Indicates P1_DIRTY_INT interrupt is disabled. + */ +#define SPI_FILTER_IMR_P1_DIRTY_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_DIRTY_MASK_SHIFT)) & SPI_FILTER_IMR_P1_DIRTY_MASK_MASK) + +#define SPI_FILTER_IMR_P0_BLK_MASK_MASK (0x4000000U) +#define SPI_FILTER_IMR_P0_BLK_MASK_SHIFT (26U) +/*! P0_BLK_MASK - Mask bit for P0_BLK_MASK + * 0b0..Indicates P0_BLK_MASK is enabled. + * 0b1..Indicates P0_BLK_MASK is disabled. + */ +#define SPI_FILTER_IMR_P0_BLK_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_BLK_MASK_SHIFT)) & SPI_FILTER_IMR_P0_BLK_MASK_MASK) + +#define SPI_FILTER_IMR_P1_BLK_MASK_MASK (0x8000000U) +#define SPI_FILTER_IMR_P1_BLK_MASK_SHIFT (27U) +/*! P1_BLK_MASK - Mask bit for P1_BLK_MASK + * 0b0..Indicates P1_BLK_MASK is enabled. + * 0b1..Indicates P1_BLK_MASK is disabled. + */ +#define SPI_FILTER_IMR_P1_BLK_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_BLK_MASK_SHIFT)) & SPI_FILTER_IMR_P1_BLK_MASK_MASK) + +#define SPI_FILTER_IMR_P0_BYTEMODE_MASK_MASK (0x10000000U) +#define SPI_FILTER_IMR_P0_BYTEMODE_MASK_SHIFT (28U) +/*! P0_BYTEMODE_MASK - Mask bit for P0_BYTEMODE_MASK + * 0b0..Indicates P0_BYTEMODE_MASK is enabled. + * 0b1..Indicates P0_BYTEMODE_MASK is disabled. + */ +#define SPI_FILTER_IMR_P0_BYTEMODE_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_BYTEMODE_MASK_SHIFT)) & SPI_FILTER_IMR_P0_BYTEMODE_MASK_MASK) + +#define SPI_FILTER_IMR_P1_BYTEMODE_MASK_MASK (0x20000000U) +#define SPI_FILTER_IMR_P1_BYTEMODE_MASK_SHIFT (29U) +/*! P1_BYTEMODE_MASK - Mask bit for P1_BYTEMODE_MASK + * 0b0..Indicates P1_BYTEMODE_MASK is enabled. + * 0b1..Indicates P1_BYTEMODE_MASK is disabled. + */ +#define SPI_FILTER_IMR_P1_BYTEMODE_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_BYTEMODE_MASK_SHIFT)) & SPI_FILTER_IMR_P1_BYTEMODE_MASK_MASK) + +#define SPI_FILTER_IMR_P0_F8_MASK_MASK (0x40000000U) +#define SPI_FILTER_IMR_P0_F8_MASK_SHIFT (30U) +/*! P0_F8_MASK - Mask bit for P0_F8_MASK + * 0b0..Indicates P0_F8_MASK is enabled. + * 0b1..Indicates P0_F8_MASK is disabled. + */ +#define SPI_FILTER_IMR_P0_F8_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_F8_MASK_SHIFT)) & SPI_FILTER_IMR_P0_F8_MASK_MASK) + +#define SPI_FILTER_IMR_P1_F8_MASK_MASK (0x80000000U) +#define SPI_FILTER_IMR_P1_F8_MASK_SHIFT (31U) +/*! P1_F8_MASK - Mask bit for P1_F8_MASK + * 0b0..Indicates P1_F8_MASK is enabled. + * 0b1..Indicates P1_F8_MASK is disabled. + */ +#define SPI_FILTER_IMR_P1_F8_MASK(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_F8_MASK_SHIFT)) & SPI_FILTER_IMR_P1_F8_MASK_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ + +#define SPI_FILTER_SR_P1_DIRTY_MASK (0x10000U) +#define SPI_FILTER_SR_P1_DIRTY_SHIFT (16U) +/*! P1_DIRTY + * 0b1..Indicates that a write to the inactive Flash has been detected and the state of the flash should be considered "dirty". + * 0b1..Indicates normal operation. No Writes have been directed to the inactive Flash + */ +#define SPI_FILTER_SR_P1_DIRTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P1_DIRTY_SHIFT)) & SPI_FILTER_SR_P1_DIRTY_MASK) + +#define SPI_FILTER_SR_P1_BYTE_MODE_MASK (0x20000U) +#define SPI_FILTER_SR_P1_BYTE_MODE_SHIFT (17U) +/*! P1_BYTE_MODE + * 0b0..3-Byte Address Mode + * 0b1..4-Byte Address Mode + */ +#define SPI_FILTER_SR_P1_BYTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P1_BYTE_MODE_SHIFT)) & SPI_FILTER_SR_P1_BYTE_MODE_MASK) + +#define SPI_FILTER_SR_P0_DIRTY_MASK (0x1000000U) +#define SPI_FILTER_SR_P0_DIRTY_SHIFT (24U) +/*! P0_DIRTY + * 0b0..Indicates normal operation. No Writes have been directed to the inactive Flash + * 0b1..Indicates that a write to the inactive Flash has been detected and the state of the flash should be considered "dirty". + */ +#define SPI_FILTER_SR_P0_DIRTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P0_DIRTY_SHIFT)) & SPI_FILTER_SR_P0_DIRTY_MASK) + +#define SPI_FILTER_SR_P0_BYTE_MODE_MASK (0x2000000U) +#define SPI_FILTER_SR_P0_BYTE_MODE_SHIFT (25U) +/*! P0_BYTE_MODE + * 0b0..3-Byte Address Mode + * 0b1..4-Byte Address Mode + */ +#define SPI_FILTER_SR_P0_BYTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P0_BYTE_MODE_SHIFT)) & SPI_FILTER_SR_P0_BYTE_MODE_MASK) +/*! @} */ + +/*! @name TCR - Test Control Register */ +/*! @{ */ + +#define SPI_FILTER_TCR_P0_BYP_SEL_MASK (0x10000U) +#define SPI_FILTER_TCR_P0_BYP_SEL_SHIFT (16U) +/*! P0_BYP_SEL + * 0b0..CS0 + * 0b1..CS1 + */ +#define SPI_FILTER_TCR_P0_BYP_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_BYP_SEL_SHIFT)) & SPI_FILTER_TCR_P0_BYP_SEL_MASK) + +#define SPI_FILTER_TCR_P0_BYP_EN_MASK (0x20000U) +#define SPI_FILTER_TCR_P0_BYP_EN_SHIFT (17U) +/*! P0_BYP_EN + * 0b0..Filter Bypass Disabled + * 0b1..Filter Bypass Enabled + */ +#define SPI_FILTER_TCR_P0_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_BYP_EN_SHIFT)) & SPI_FILTER_TCR_P0_BYP_EN_MASK) + +#define SPI_FILTER_TCR_P1_BYP_SEL_MASK (0x40000U) +#define SPI_FILTER_TCR_P1_BYP_SEL_SHIFT (18U) +/*! P1_BYP_SEL + * 0b0..CS0 + * 0b1..CS1 + */ +#define SPI_FILTER_TCR_P1_BYP_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_BYP_SEL_SHIFT)) & SPI_FILTER_TCR_P1_BYP_SEL_MASK) + +#define SPI_FILTER_TCR_P1_BYP_EN_MASK (0x80000U) +#define SPI_FILTER_TCR_P1_BYP_EN_SHIFT (19U) +/*! P1_BYP_EN + * 0b0..Filter Bypass Disabled + * 0b1..Filter Bypass Enabled + */ +#define SPI_FILTER_TCR_P1_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_BYP_EN_SHIFT)) & SPI_FILTER_TCR_P1_BYP_EN_MASK) + +#define SPI_FILTER_TCR_P0_MFG_ID_MASK (0xF000000U) +#define SPI_FILTER_TCR_P0_MFG_ID_SHIFT (24U) +/*! P0_MFG_ID - Sets the Flash memory manufacturer + * 0b0010..Micron + * 0b0001..Windbond + * 0b0000..Macronix + */ +#define SPI_FILTER_TCR_P0_MFG_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_MFG_ID_SHIFT)) & SPI_FILTER_TCR_P0_MFG_ID_MASK) + +#define SPI_FILTER_TCR_P1_MFG_ID_MASK (0xF0000000U) +#define SPI_FILTER_TCR_P1_MFG_ID_SHIFT (28U) +/*! P1_MFG_ID - Sets the Flash memory manufacturer + * 0b0010..Micron + * 0b0001..Windbond + * 0b0000..Macronix + */ +#define SPI_FILTER_TCR_P1_MFG_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_MFG_ID_SHIFT)) & SPI_FILTER_TCR_P1_MFG_ID_MASK) +/*! @} */ + +/*! @name P0FAR1 - Port 0 filter address region 1 */ +/*! @{ */ + +#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_MASK (0xFFU) +#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_SHIFT (0U) +/*! ADDRESS_LOWER_LSBS - Address Lower LSBs + */ +#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_MASK) + +#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_MASK (0xFF00U) +#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_SHIFT (8U) +/*! ADDRESS_LOWER_MSBS - Address Lower MSBs + */ +#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_MASK) + +#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) +#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_SHIFT (16U) +/*! ADDRESS_UPPER_LSBS - Address Upper LSBs + */ +#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_MASK) + +#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) +#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_SHIFT (24U) +/*! ADDRESS_UPPER_MSBS - Address Upper MSBs + */ +#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_MASK) +/*! @} */ + +/*! @name P0FAR2 - Port 0 filter address region 2 */ +/*! @{ */ + +#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_MASK (0xFFU) +#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_SHIFT (0U) +/*! ADDRESS_LOWER_LSBS - Address Lower LSBs + */ +#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_MASK) + +#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_MASK (0xFF00U) +#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_SHIFT (8U) +/*! ADDRESS_LOWER_MSBS - Address Lower MSBs + */ +#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_MASK) + +#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) +#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_SHIFT (16U) +/*! ADDRESS_UPPER_LSBS - Address Upper LSBs + */ +#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_MASK) + +#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) +#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_SHIFT (24U) +/*! ADDRESS_UPPER_MSBS - Address Upper MSBs + */ +#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_MASK) +/*! @} */ + +/*! @name P0FAR3 - Port 0 filter address region 3 */ +/*! @{ */ + +#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_MASK (0xFFU) +#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_SHIFT (0U) +/*! ADDRESS_LOWER_LSBS - Address Lower LSBs + */ +#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_MASK) + +#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_MASK (0xFF00U) +#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_SHIFT (8U) +/*! ADDRESS_LOWER_MSBS - Address Lower MSBs + */ +#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_MASK) + +#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) +#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_SHIFT (16U) +/*! ADDRESS_UPPER_LSBS - Address Upper LSBs + */ +#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_MASK) + +#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) +#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_SHIFT (24U) +/*! ADDRESS_UPPER_MSBS - Address Upper MSBs + */ +#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_MASK) +/*! @} */ + +/*! @name P1FAR1 - Port 1 filter address region 1 */ +/*! @{ */ + +#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_MASK (0xFFU) +#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_SHIFT (0U) +/*! ADDRESS_LOWER_LSBS - Address Lower LSBs + */ +#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_MASK) + +#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_MASK (0xFF00U) +#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_SHIFT (8U) +/*! ADDRESS_LOWER_MSBS - Address Lower MSBs + */ +#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_MASK) + +#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) +#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_SHIFT (16U) +/*! ADDRESS_UPPER_LSBS - Address Upper LSBs + */ +#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_MASK) + +#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) +#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_SHIFT (24U) +/*! ADDRESS_UPPER_MSBS - Address Upper MSBs + */ +#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_MASK) +/*! @} */ + +/*! @name P1FAR2 - Port 1 filter address region 2 */ +/*! @{ */ + +#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_MASK (0xFFU) +#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_SHIFT (0U) +/*! ADDRESS_LOWER_LSBS - Address Lower LSBs + */ +#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_MASK) + +#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_MASK (0xFF00U) +#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_SHIFT (8U) +/*! ADDRESS_LOWER_MSBS - Address Lower MSBs + */ +#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_MASK) + +#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) +#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_SHIFT (16U) +/*! ADDRESS_UPPER_LSBS - Address Upper LSBs + */ +#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_MASK) + +#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) +#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_SHIFT (24U) +/*! ADDRESS_UPPER_MSBS - Address Upper MSBs + */ +#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_MASK) +/*! @} */ + +/*! @name P1FAR3 - Port 1 filter address region 3 */ +/*! @{ */ + +#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_MASK (0xFFU) +#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_SHIFT (0U) +/*! ADDRESS_LOWER_LSBS - Address Lower LSBs + */ +#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_MASK) + +#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_MASK (0xFF00U) +#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_SHIFT (8U) +/*! ADDRESS_LOWER_MSBS - Address Lower MSBs + */ +#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_MASK) + +#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_MASK (0xFF0000U) +#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_SHIFT (16U) +/*! ADDRESS_UPPER_LSBS - Address Upper LSBs + */ +#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_MASK) + +#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_MASK (0xFF000000U) +#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_SHIFT (24U) +/*! ADDRESS_UPPER_MSBS - Address Upper MSBs + */ +#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_MASK) +/*! @} */ + +/*! @name VER - Version */ +/*! @{ */ + +#define SPI_FILTER_VER_MINOR_REVISION_MASK (0xF000000U) +#define SPI_FILTER_VER_MINOR_REVISION_SHIFT (24U) +/*! MINOR_REVISION - Minor revision + */ +#define SPI_FILTER_VER_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_VER_MINOR_REVISION_SHIFT)) & SPI_FILTER_VER_MINOR_REVISION_MASK) + +#define SPI_FILTER_VER_MAJOR_REVISION_MASK (0xF0000000U) +#define SPI_FILTER_VER_MAJOR_REVISION_SHIFT (28U) +/*! MAJOR_REVISION - Major Revision + */ +#define SPI_FILTER_VER_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_VER_MAJOR_REVISION_SHIFT)) & SPI_FILTER_VER_MAJOR_REVISION_MASK) +/*! @} */ + +/*! @name POPCODE0 - Programmable OP-Code0 */ +/*! @{ */ + +#define SPI_FILTER_POPCODE0_FILTER_STATE0_MASK (0x1F0000U) +#define SPI_FILTER_POPCODE0_FILTER_STATE0_SHIFT (16U) +/*! FILTER_STATE0 - Programmable Filter state 0 + */ +#define SPI_FILTER_POPCODE0_FILTER_STATE0(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_FILTER_STATE0_SHIFT)) & SPI_FILTER_POPCODE0_FILTER_STATE0_MASK) + +#define SPI_FILTER_POPCODE0_FILTER_BIT0_MASK (0x200000U) +#define SPI_FILTER_POPCODE0_FILTER_BIT0_SHIFT (21U) +/*! FILTER_BIT0 + * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. + * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. + */ +#define SPI_FILTER_POPCODE0_FILTER_BIT0(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_FILTER_BIT0_SHIFT)) & SPI_FILTER_POPCODE0_FILTER_BIT0_MASK) + +#define SPI_FILTER_POPCODE0_PRG_OPCODE0_MASK (0xFF000000U) +#define SPI_FILTER_POPCODE0_PRG_OPCODE0_SHIFT (24U) +/*! PRG_OPCODE0 - Programmable OP Code 0 + */ +#define SPI_FILTER_POPCODE0_PRG_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_PRG_OPCODE0_SHIFT)) & SPI_FILTER_POPCODE0_PRG_OPCODE0_MASK) +/*! @} */ + +/*! @name POPCODE1 - Programmable OP-Code1 */ +/*! @{ */ + +#define SPI_FILTER_POPCODE1_FILTER_STATE1_MASK (0x1F0000U) +#define SPI_FILTER_POPCODE1_FILTER_STATE1_SHIFT (16U) +/*! FILTER_STATE1 - Programmable Filter state 1 + */ +#define SPI_FILTER_POPCODE1_FILTER_STATE1(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_FILTER_STATE1_SHIFT)) & SPI_FILTER_POPCODE1_FILTER_STATE1_MASK) + +#define SPI_FILTER_POPCODE1_FILTER_BIT1_MASK (0x200000U) +#define SPI_FILTER_POPCODE1_FILTER_BIT1_SHIFT (21U) +/*! FILTER_BIT1 + * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. + * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. + */ +#define SPI_FILTER_POPCODE1_FILTER_BIT1(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_FILTER_BIT1_SHIFT)) & SPI_FILTER_POPCODE1_FILTER_BIT1_MASK) + +#define SPI_FILTER_POPCODE1_PRG_OPCODE1_MASK (0xFF000000U) +#define SPI_FILTER_POPCODE1_PRG_OPCODE1_SHIFT (24U) +/*! PRG_OPCODE1 - Programmable OP Code 1 + */ +#define SPI_FILTER_POPCODE1_PRG_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_PRG_OPCODE1_SHIFT)) & SPI_FILTER_POPCODE1_PRG_OPCODE1_MASK) +/*! @} */ + +/*! @name POPCODE2 - Programmable OP-Code2 */ +/*! @{ */ + +#define SPI_FILTER_POPCODE2_FILTER_STATE2_MASK (0x1F0000U) +#define SPI_FILTER_POPCODE2_FILTER_STATE2_SHIFT (16U) +/*! FILTER_STATE2 - Programmable Filter state 2 + */ +#define SPI_FILTER_POPCODE2_FILTER_STATE2(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_FILTER_STATE2_SHIFT)) & SPI_FILTER_POPCODE2_FILTER_STATE2_MASK) + +#define SPI_FILTER_POPCODE2_FILTER_BIT2_MASK (0x200000U) +#define SPI_FILTER_POPCODE2_FILTER_BIT2_SHIFT (21U) +/*! FILTER_BIT2 + * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. + * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. + */ +#define SPI_FILTER_POPCODE2_FILTER_BIT2(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_FILTER_BIT2_SHIFT)) & SPI_FILTER_POPCODE2_FILTER_BIT2_MASK) + +#define SPI_FILTER_POPCODE2_PRG_OPCODE2_MASK (0xFF000000U) +#define SPI_FILTER_POPCODE2_PRG_OPCODE2_SHIFT (24U) +/*! PRG_OPCODE2 - Programmable OP Code 0 + */ +#define SPI_FILTER_POPCODE2_PRG_OPCODE2(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_PRG_OPCODE2_SHIFT)) & SPI_FILTER_POPCODE2_PRG_OPCODE2_MASK) +/*! @} */ + +/*! @name POPCODE3 - Programmable OP-Code3 */ +/*! @{ */ + +#define SPI_FILTER_POPCODE3_FILTER_STATE3_MASK (0x1F0000U) +#define SPI_FILTER_POPCODE3_FILTER_STATE3_SHIFT (16U) +/*! FILTER_STATE3 - Programmable Filter state 3 + */ +#define SPI_FILTER_POPCODE3_FILTER_STATE3(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_FILTER_STATE3_SHIFT)) & SPI_FILTER_POPCODE3_FILTER_STATE3_MASK) + +#define SPI_FILTER_POPCODE3_FILTER_BIT3_MASK (0x200000U) +#define SPI_FILTER_POPCODE3_FILTER_BIT3_SHIFT (21U) +/*! FILTER_BIT3 + * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. + * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. + */ +#define SPI_FILTER_POPCODE3_FILTER_BIT3(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_FILTER_BIT3_SHIFT)) & SPI_FILTER_POPCODE3_FILTER_BIT3_MASK) + +#define SPI_FILTER_POPCODE3_PRG_OPCODE3_MASK (0xFF000000U) +#define SPI_FILTER_POPCODE3_PRG_OPCODE3_SHIFT (24U) +/*! PRG_OPCODE3 - Programmable OP Code 3 + */ +#define SPI_FILTER_POPCODE3_PRG_OPCODE3(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_PRG_OPCODE3_SHIFT)) & SPI_FILTER_POPCODE3_PRG_OPCODE3_MASK) +/*! @} */ + +/*! @name POPCODE4 - Programmable OP-Code4 */ +/*! @{ */ + +#define SPI_FILTER_POPCODE4_FILTER_STATE4_MASK (0x1F0000U) +#define SPI_FILTER_POPCODE4_FILTER_STATE4_SHIFT (16U) +/*! FILTER_STATE4 - Programmable Filter state 4 + */ +#define SPI_FILTER_POPCODE4_FILTER_STATE4(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_FILTER_STATE4_SHIFT)) & SPI_FILTER_POPCODE4_FILTER_STATE4_MASK) + +#define SPI_FILTER_POPCODE4_FILTER_BIT4_MASK (0x200000U) +#define SPI_FILTER_POPCODE4_FILTER_BIT4_SHIFT (21U) +/*! FILTER_BIT4 + * 0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered. + * 0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address. + */ +#define SPI_FILTER_POPCODE4_FILTER_BIT4(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_FILTER_BIT4_SHIFT)) & SPI_FILTER_POPCODE4_FILTER_BIT4_MASK) + +#define SPI_FILTER_POPCODE4_PRG_OPCODE4_MASK (0xFF000000U) +#define SPI_FILTER_POPCODE4_PRG_OPCODE4_SHIFT (24U) +/*! PRG_OPCODE4 - Programmable OP Code 4 + */ +#define SPI_FILTER_POPCODE4_PRG_OPCODE4(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_PRG_OPCODE4_SHIFT)) & SPI_FILTER_POPCODE4_PRG_OPCODE4_MASK) +/*! @} */ + +/*! @name P0BOC - P0 Blocked Op Code */ +/*! @{ */ + +#define SPI_FILTER_P0BOC_P0BOC_MASK (0xFF000000U) +#define SPI_FILTER_P0BOC_P0BOC_SHIFT (24U) +/*! P0BOC - Port 0 Blocked Op Code + */ +#define SPI_FILTER_P0BOC_P0BOC(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0BOC_P0BOC_SHIFT)) & SPI_FILTER_P0BOC_P0BOC_MASK) +/*! @} */ + +/*! @name P1BOC - P1 Blocked Op Code */ +/*! @{ */ + +#define SPI_FILTER_P1BOC_P1BOC_MASK (0xFF000000U) +#define SPI_FILTER_P1BOC_P1BOC_SHIFT (24U) +/*! P1BOC - Port 1 Blocked Op Code + */ +#define SPI_FILTER_P1BOC_P1BOC(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1BOC_P1BOC_SHIFT)) & SPI_FILTER_P1BOC_P1BOC_MASK) +/*! @} */ + +/*! @name P0MAM - Port 0 Max Address Mask */ +/*! @{ */ + +#define SPI_FILTER_P0MAM_P0MAML_MASK (0xFF0000U) +#define SPI_FILTER_P0MAM_P0MAML_SHIFT (16U) +/*! P0MAML - Port 0 Max Address Mask LSB + */ +#define SPI_FILTER_P0MAM_P0MAML(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0MAM_P0MAML_SHIFT)) & SPI_FILTER_P0MAM_P0MAML_MASK) + +#define SPI_FILTER_P0MAM_P0MAMM_MASK (0xFF000000U) +#define SPI_FILTER_P0MAM_P0MAMM_SHIFT (24U) +/*! P0MAMM - Port 0 Max Address Mask MSB + */ +#define SPI_FILTER_P0MAM_P0MAMM(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0MAM_P0MAMM_SHIFT)) & SPI_FILTER_P0MAM_P0MAMM_MASK) +/*! @} */ + +/*! @name P1MAM - Port 1 Max Address Mask */ +/*! @{ */ + +#define SPI_FILTER_P1MAM_P1MAML_MASK (0xFF0000U) +#define SPI_FILTER_P1MAM_P1MAML_SHIFT (16U) +/*! P1MAML - Port 1 Max Address Mask LSB + */ +#define SPI_FILTER_P1MAM_P1MAML(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1MAM_P1MAML_SHIFT)) & SPI_FILTER_P1MAM_P1MAML_MASK) + +#define SPI_FILTER_P1MAM_P1MAMM_MASK (0xFF000000U) +#define SPI_FILTER_P1MAM_P1MAMM_SHIFT (24U) +/*! P1MAMM - Port 1 Max Address Mask MSB + */ +#define SPI_FILTER_P1MAM_P1MAMM(x) (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1MAM_P1MAMM_SHIFT)) & SPI_FILTER_P1MAM_P1MAMM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_FILTER_Register_Masks */ + + +/* SPI_FILTER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI_FILTER base address */ + #define SPI_FILTER_BASE (0x50024000u) + /** Peripheral SPI_FILTER base address */ + #define SPI_FILTER_BASE_NS (0x40024000u) + /** Peripheral SPI_FILTER base pointer */ + #define SPI_FILTER ((SPI_FILTER_Type *)SPI_FILTER_BASE) + /** Peripheral SPI_FILTER base pointer */ + #define SPI_FILTER_NS ((SPI_FILTER_Type *)SPI_FILTER_BASE_NS) + /** Array initializer of SPI_FILTER peripheral base addresses */ + #define SPI_FILTER_BASE_ADDRS { SPI_FILTER_BASE } + /** Array initializer of SPI_FILTER peripheral base pointers */ + #define SPI_FILTER_BASE_PTRS { SPI_FILTER } + /** Array initializer of SPI_FILTER peripheral base addresses */ + #define SPI_FILTER_BASE_ADDRS_NS { SPI_FILTER_BASE_NS } + /** Array initializer of SPI_FILTER peripheral base pointers */ + #define SPI_FILTER_BASE_PTRS_NS { SPI_FILTER_NS } +#else + /** Peripheral SPI_FILTER base address */ + #define SPI_FILTER_BASE (0x40024000u) + /** Peripheral SPI_FILTER base pointer */ + #define SPI_FILTER ((SPI_FILTER_Type *)SPI_FILTER_BASE) + /** Array initializer of SPI_FILTER peripheral base addresses */ + #define SPI_FILTER_BASE_ADDRS { SPI_FILTER_BASE } + /** Array initializer of SPI_FILTER peripheral base pointers */ + #define SPI_FILTER_BASE_PTRS { SPI_FILTER } +#endif + +/*! + * @} + */ /* end of group SPI_FILTER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap Control, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control, offset: 0x10 */ + __IO uint32_t AHBMATPRIO1; /**< AHB Matrix priority control, offset: 0x14 */ + uint8_t RESERVED_1[32]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + __IO uint32_t PRESETCTRL3; /**< Peripheral reset control 3, offset: 0x10C */ + uint8_t RESERVED_4[16]; + __O uint32_t PRESETCTRLSET[4]; /**< Peripheral reset control set n, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __O uint32_t PRESETCTRLCLR[4]; /**< Peripheral reset control clear n, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[16]; + __O uint32_t SWR_RESET; /**< Software Reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + __IO uint32_t AHBCLKCTRL3; /**< AHB Clock Control 3, offset: 0x20C */ + uint8_t RESERVED_8[16]; + __IO uint32_t AHBCLKCTRLSET[4]; /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[16]; + __IO uint32_t AHBCLKCTRLCLR[4]; /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[16]; + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + uint8_t RESERVED_11[4]; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + __IO uint32_t CTIMERCLKSEL[5]; /**< CTimer 0 clock source select..CTimer 4 clock source select, array offset: 0x26C, array step: 0x4 */ + __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_12[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_13[8]; + __IO uint32_t CANCLKSEL; /**< CAN clock source select, offset: 0x2A0 */ + __IO uint32_t ADC0CLKSEL; /**< ADC0 clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_14[4]; + __IO uint32_t FCCLKSEL[8]; /**< Flexcomm 0 clock source select for Fractional Rate Divider..Flexcomm 7 clock source select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */ + __IO uint32_t HSSPICLKSEL; /**< HS SPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_16[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t SYSTICKCLKDIV[1]; /**< System Tick Timer divider for CPU0, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_18[4]; + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + __IO uint32_t CANCLKDIV; /**< CAN clock divider, offset: 0x30C */ + uint8_t RESERVED_19[16]; + __IO uint32_t FRGCTRL[8]; /**< Fractional rate divider for flexcomm 0..Fractional rate divider for flexcomm 7, array offset: 0x320, array step: 0x4 */ + uint8_t RESERVED_20[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_21[4]; + __IO uint32_t ADC0CLKDIV; /**< ADC0 clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0-FS Clock divider, offset: 0x398 */ + uint8_t RESERVED_22[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_23[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_24[12]; + __IO uint32_t PLLCLKDIV; /**< PLL clock divider, offset: 0x3C4 */ + uint8_t RESERVED_25[8]; + __IO uint32_t CTIMERCLKDIV[5]; /**< CTimer 0 clock divider..CTimer 4 clock divider, array offset: 0x3D0, array step: 0x4 */ + uint8_t RESERVED_26[24]; + __IO uint32_t CLKUNLOCK; /**< Clock configuration unlock, offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration, offset: 0x400 */ + __IO uint32_t ROMCR; /**< ROM wait state, offset: 0x404 */ + uint8_t RESERVED_27[4]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0-FS need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0-FS need clock status, offset: 0x410 */ + __IO uint32_t EZHINT; /**< EZH interrupt hijack, offset: 0x414 */ + uint8_t RESERVED_28[4]; + __O uint32_t FMCFLUSH; /**< FMC flush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + uint8_t RESERVED_29[64]; + __IO uint32_t ADC1CLKSEL; /**< ADC1 clock source select, offset: 0x464 */ + __IO uint32_t ADC1CLKDIV; /**< ADC1 clock divider, offset: 0x468 */ + uint8_t RESERVED_30[4]; + __IO uint32_t RAM_INTERLEAVE; /**< Control RAM interleave integration, offset: 0x470 */ + uint8_t RESERVED_31[28]; + struct { /* offset: 0x490, array step: 0x8 */ + __IO uint32_t CLKSEL; /**< DAC0 functional clock selection..DAC2 functional clock selection, array offset: 0x490, array step: 0x8 */ + __IO uint32_t CLKDIV; /**< DAC0 functional clock divider..DAC2 functional clock divider, array offset: 0x494, array step: 0x8 */ + } DAC[3]; + __IO uint32_t FLEXSPICLKSEL; /**< FLEXSPI clock selection, offset: 0x4A8 */ + __IO uint32_t FLEXSPICLKDIV; /**< FLEXSPI clock divider, offset: 0x4AC */ + __IO uint32_t CDPA_ENABLE; /**< Enable protection, offset: 0x4B0 */ + __IO uint32_t CDPA_ENABLE_DP; /**< Enable protection duplicate, offset: 0x4B4 */ + __IO uint32_t CDPA_CONFIG; /**< CDPA base address, offset: 0x4B8 */ + uint8_t RESERVED_32[20]; + __IO uint32_t FLASH_HIDING_LOCKOUT_ADDR; /**< Flash hiding lockout address, offset: 0x4D0 */ + __IO uint32_t FLASH_HIDING_BASE_ADDR; /**< Flash hiding base address, offset: 0x4D4 */ + __IO uint32_t FLASH_HIDING_BASE_DP_ADDR; /**< Flash hiding base DP address, offset: 0x4D8 */ + __IO uint32_t FLASH_HIDING_SIZE_ADDR; /**< Hiding size address, offset: 0x4DC */ + __IO uint32_t FLASH_HIDING_SIZE_DP_ADDR; /**< Hiding size DP address, offset: 0x4E0 */ + uint8_t RESERVED_33[72]; + __IO uint32_t PLLCLKDIVSEL; /**< PLL clock divider clock selection, offset: 0x52C */ + __IO uint32_t I3CFCLKSEL; /**< I3C functional clock selection, offset: 0x530 */ + __IO uint32_t I3CFCLKSTCSEL; /**< I3C FCLK_STC clock selection, offset: 0x534 */ + __IO uint32_t I3CFCLKSTCDIV; /**< I3C FCLK_STC clock divider, offset: 0x538 */ + __IO uint32_t I3CFCLKSDIV; /**< I3C FCLKS clock divider, offset: 0x53C */ + __IO uint32_t I3CFCLKDIV; /**< I3C FCLK divider, offset: 0x540 */ + __IO uint32_t I3CFCLKSSEL; /**< I3C FCLK_S selection, offset: 0x544 */ + __IO uint32_t DMICFCLKSEL; /**< DMIC clock selection, offset: 0x548 */ + __IO uint32_t DMICFCLKDIV; /**< DMIC clock division, offset: 0x54C */ + uint8_t RESERVED_34[16]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_35[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum control 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum control 1, offset: 0x594 */ + uint8_t RESERVED_36[56]; + __IO uint32_t DAC_ISO_CTRL; /**< DAC Isolation Control, offset: 0x5D0 */ + uint8_t RESERVED_37[172]; + __IO uint32_t STARTER[4]; /**< Start logic wake-up enable, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_38[16]; + __IO uint32_t STARTERSET[4]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_39[16]; + __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_40[60]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control, offset: 0x704 */ + uint8_t RESERVED_41[120]; + __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ + uint8_t RESERVED_42[136]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_43[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC control, offset: 0x824 */ + uint8_t RESERVED_44[4]; + __IO uint32_t FC32KCLKSEL; /**< Flexcomm 32K clock select, offset: 0x82C */ + __IO uint32_t FRGCLKSEL[8]; /**< FRG Clock Source Select, array offset: 0x830, array step: 0x4 */ + __IO uint32_t FLEXCOMMCLKDIV[8]; /**< Flexcomm clock divider, array offset: 0x850, array step: 0x4 */ + uint8_t RESERVED_45[280]; + __IO uint32_t CSS_TEMPORAL_STATE; /**< CSS temporal state, offset: 0x988 */ + __IO uint32_t CSS_KDF_MASK; /**< Key derivation function mask, offset: 0x98C */ + __IO uint32_t CSS_FEATURE0; /**< CSS command feature, offset: 0x990 */ + __IO uint32_t CSS_FEATURE1; /**< CSS command feature, offset: 0x994 */ + __IO uint32_t CSS_FEATURE0_DP; /**< CSS command feature - duplicate version, offset: 0x998 */ + __IO uint32_t CSS_FEATURE1_DP; /**< CSS command feature - duplicate version, offset: 0x99C */ + uint8_t RESERVED_46[4]; + __IO uint32_t CSS_BOOT_RETRY_CNT; /**< CSS boot retry counter, offset: 0x9A4 */ + uint8_t RESERVED_47[8]; + __IO uint32_t CSS_CLK_CTRL; /**< CSS clock control, offset: 0x9B0 */ + __O uint32_t CSS_CLK_CTRL_SET; /**< CSS clock control set, offset: 0x9B4 */ + __O uint32_t CSS_CLK_CTRL_CLR; /**< CSS clock control clear, offset: 0x9B8 */ + __IO uint32_t CSS_CLK_SEL; /**< CSS clock select, offset: 0x9BC */ + uint8_t RESERVED_48[16]; + __I uint32_t CSS_AS_CFG0; /**< CSS AS configuration, offset: 0x9D0 */ + __I uint32_t CSS_AS_CFG1; /**< CSS AS configuration1, offset: 0x9D4 */ + __I uint32_t CSS_AS_CFG2; /**< CSS AS configuration2, offset: 0x9D8 */ + uint8_t RESERVED_49[4]; + __I uint32_t CSS_AS_ST0; /**< CSS AS state register, offset: 0x9E0 */ + __I uint32_t CSS_AS_ST1; /**< CSS AS state1, offset: 0x9E4 */ + __I uint32_t CSS_AS_ST2; /**< CSS AS state2, offset: 0x9E8 */ + uint8_t RESERVED_50[4]; + __I uint32_t CSS_AS_FLAG0; /**< CSS AS flag0, offset: 0x9F0 */ + uint8_t RESERVED_51[36]; + __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ + uint8_t RESERVED_52[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_53[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< GPIO Synchronization, offset: 0xE08 */ + uint8_t RESERVED_54[24]; + __IO uint32_t AUTOCLKGATEOVERRIDE1; /**< Control automatic clock gating, offset: 0xE24 */ + uint8_t RESERVED_55[8]; + __IO uint32_t ENABLE_MEM_PARITY_ECC_CHECK; /**< Memory parity ECC enable, offset: 0xE30 */ + __I uint32_t MEM_PARITY_ECC_ERROR_FLAG; /**< Memory parity ECC error flag, offset: 0xE34 */ + __IO uint32_t PWM0SUBCTL; /**< PWM0 submodule control, offset: 0xE38 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 submodule control, offset: 0xE3C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER global start enable, offset: 0xE40 */ + uint8_t RESERVED_56[348]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex debug features control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex debug features control (duplicate), offset: 0xFA8 */ + uint8_t RESERVED_57[8]; + __IO uint32_t SWD_ACCESS_CPU[1]; /**< CPU0 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ + uint8_t RESERVED_58[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON, offset: 0xFC0 */ + __IO uint32_t SWD_ACCESS_DSP; /**< DSP Software Debug Access, offset: 0xFC4 */ + uint8_t RESERVED_59[44]; + uint32_t DEVICE_TYPE; /**< Device type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap Control */ +/*! @{ */ + +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table: + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b1x..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT (8U) +/*! PRI_USB_FSD - USB0-FS Device.(USB0) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +/*! PRI_SDMA0 - DMA0 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) + +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) +/*! PRI_EZH_B_D - EZH B data bus. + */ +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) + +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) +/*! PRI_EZH_B_I - EZH B instruction bus. + */ +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +/*! PRI_PQ - PQ (HW Accelerator). + */ +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CSSV2_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_CSSV2_SHIFT (20U) +/*! PRI_CSSV2 - CSSV2 + */ +#define SYSCON_AHBMATPRIO_PRI_CSSV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CSSV2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CSSV2_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (22U) +/*! PRI_USB_FS - USB-FS host + */ +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +/*! PRI_SDMA1 - DMA1 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) + +#define SYSCON_AHBMATPRIO_PRI_MCAN_MASK (0xC000000U) +#define SYSCON_AHBMATPRIO_PRI_MCAN_SHIFT (26U) +/*! PRI_MCAN - MCAN + */ +#define SYSCON_AHBMATPRIO_PRI_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN_MASK) + +#define SYSCON_AHBMATPRIO_PKC_MASK (0xC0000000U) +#define SYSCON_AHBMATPRIO_PKC_SHIFT (30U) +/*! PKC - PKC + */ +#define SYSCON_AHBMATPRIO_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PKC_SHIFT)) & SYSCON_AHBMATPRIO_PKC_MASK) +/*! @} */ + +/*! @name AHBMATPRIO1 - AHB Matrix priority control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO1_DSP_D_MASK (0xCU) +#define SYSCON_AHBMATPRIO1_DSP_D_SHIFT (2U) +/*! DSP_D - DSP D bus + */ +#define SYSCON_AHBMATPRIO1_DSP_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO1_DSP_D_SHIFT)) & SYSCON_AHBMATPRIO1_DSP_D_MASK) + +#define SYSCON_AHBMATPRIO1_DSP_I_MASK (0x30U) +#define SYSCON_AHBMATPRIO1_DSP_I_SHIFT (4U) +/*! DSP_I - DSP I bus + */ +#define SYSCON_AHBMATPRIO1_DSP_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO1_DSP_I_SHIFT)) & SYSCON_AHBMATPRIO1_DSP_I_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: + * 0b0..TENMS value is exact + * 0b1..TENMS value is inexact, or not given + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor + * 0b0..Reference clock provided + * 0b1..No reference clock provided + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: + * 0b0..TENMS value is exact + * 0b1..TENMS value is inexact, or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: + * 0b0..Reference clock provided + * 0b1..No reference clock provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) + +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) + +#define SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT (10U) +/*! FLEXSPI_RST - FLEXSPI reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_FLEXSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK) + +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + +#define SYSCON_PRESETCTRL0_ADC0_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC0_RST_SHIFT (27U) +/*! ADC0_RST - ADC0 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC0_RST_MASK) + +#define SYSCON_PRESETCTRL0_ADC1_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL0_ADC1_RST_SHIFT (28U) +/*! ADC1_RST - ADC1 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC1_RST_MASK) + +#define SYSCON_PRESETCTRL0_DAC0_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL0_DAC0_RST_SHIFT (29U) +/*! DAC0_RST - DAC0 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL0_DAC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DAC0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DAC0_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + +#define SYSCON_PRESETCTRL1_CAN_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL1_CAN_RST_SHIFT (7U) +/*! CAN_RST - CAN reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_CAN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAN_RST_SHIFT)) & SYSCON_PRESETCTRL1_CAN_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_DMIC_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL1_DMIC_RST_SHIFT (19U) +/*! DMIC_RST - DMIC reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL1_DMIC_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0-FS DEV reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) + +#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) +/*! EZHA_RST - EZH a reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) + +#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) +#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) +/*! EZHB_RST - EZH b reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Analog comparator reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0-FS Host Master reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0-FS Host Slave reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) + +#define SYSCON_PRESETCTRL2_CSS_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_CSS_RST_SHIFT (18U) +/*! CSS_RST - CSS reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_CSS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CSS_RST_SHIFT)) & SYSCON_PRESETCTRL2_CSS_RST_MASK) + +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_PKC_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_PKC_RST_SHIFT (24U) +/*! PKC_RST - PKC reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset.g + */ +#define SYSCON_PRESETCTRL2_PKC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK) + +#define SYSCON_PRESETCTRL2_ANACTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANACTRL_RST_SHIFT (27U) +/*! ANACTRL_RST - Analog control reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_ANACTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANACTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANACTRL_RST_MASK) + +#define SYSCON_PRESETCTRL2_HS_SPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_SPI_RST_SHIFT (28U) +/*! HS_SPI_RST - HS SPI reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_SPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_SPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_SPI_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL3 - Peripheral reset control 3 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL3_I3C0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT (0U) +/*! I3C0_RST - I3C reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_I3C0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK) + +#define SYSCON_PRESETCTRL3_ENC0_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL3_ENC0_RST_SHIFT (3U) +/*! ENC0_RST - ENC0 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_ENC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC0_RST_MASK) + +#define SYSCON_PRESETCTRL3_ENC1_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL3_ENC1_RST_SHIFT (4U) +/*! ENC1_RST - ENC1 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_ENC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC1_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (5U) +/*! PWM0_RST - PWM0 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_PWM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM1_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT (6U) +/*! PWM1_RST - PWM1 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_PWM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK) + +#define SYSCON_PRESETCTRL3_AOI0_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT (7U) +/*! AOI0_RST - AOI0 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_AOI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK) + +#define SYSCON_PRESETCTRL3_AOI1_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL3_AOI1_RST_SHIFT (8U) +/*! AOI1_RST - AOI1 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_AOI1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI1_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI1_RST_MASK) + +#define SYSCON_PRESETCTRL3_FTM0_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL3_FTM0_RST_SHIFT (9U) +/*! FTM0_RST - FTM0 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_FTM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_FTM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_FTM0_RST_MASK) + +#define SYSCON_PRESETCTRL3_DAC1_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL3_DAC1_RST_SHIFT (10U) +/*! DAC1_RST - DAC1 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_DAC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC1_RST_MASK) + +#define SYSCON_PRESETCTRL3_DAC2_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL3_DAC2_RST_SHIFT (11U) +/*! DAC2_RST - DAC2 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_DAC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC2_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC2_RST_MASK) + +#define SYSCON_PRESETCTRL3_OPAMP0_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT (12U) +/*! OPAMP0_RST - OPAMP0 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_OPAMP0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP0_RST_MASK) + +#define SYSCON_PRESETCTRL3_OPAMP1_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT (13U) +/*! OPAMP1_RST - OPAMP1 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_OPAMP1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP1_RST_MASK) + +#define SYSCON_PRESETCTRL3_OPAMP2_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT (14U) +/*! OPAMP2_RST - OPAMP2 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_OPAMP2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP2_RST_MASK) + +#define SYSCON_PRESETCTRL3_HSCMP0_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL3_HSCMP0_RST_SHIFT (15U) +/*! HSCMP0_RST - HSCMP0 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_HSCMP0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP0_RST_MASK) + +#define SYSCON_PRESETCTRL3_HSCMP1_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL3_HSCMP1_RST_SHIFT (16U) +/*! HSCMP1_RST - HSCMP1 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_HSCMP1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP1_RST_MASK) + +#define SYSCON_PRESETCTRL3_HSCMP2_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL3_HSCMP2_RST_SHIFT (17U) +/*! HSCMP2_RST - HSCMP2 reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_HSCMP2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP2_RST_MASK) + +#define SYSCON_PRESETCTRL3_VREF_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL3_VREF_RST_SHIFT (18U) +/*! VREF_RST - VREF reset control + * 0b1..Block is reset. + * 0b0..Block is not reset. + */ +#define SYSCON_PRESETCTRL3_VREF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLSET - Peripheral reset control set n */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) + +#define SYSCON_PRESETCTRLSET_DATA_L_MASK (0x7FFU) +#define SYSCON_PRESETCTRLSET_DATA_L_SHIFT (0U) +/*! DATA_L - Data array value + */ +#define SYSCON_PRESETCTRLSET_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_L_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_L_MASK) + +#define SYSCON_PRESETCTRLSET_DATA_U_MASK (0xFFFFF000U) +#define SYSCON_PRESETCTRLSET_DATA_U_SHIFT (12U) +/*! DATA_U - Data array value + */ +#define SYSCON_PRESETCTRLSET_DATA_U(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_U_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_U_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (4U) + +/*! @name PRESETCTRLCLR - Peripheral reset control clear n */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) + +#define SYSCON_PRESETCTRLCLR_DATA_L_MASK (0x7FFU) +#define SYSCON_PRESETCTRLCLR_DATA_L_SHIFT (0U) +/*! DATA_L - Data array value + */ +#define SYSCON_PRESETCTRLCLR_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_L_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_L_MASK) + +#define SYSCON_PRESETCTRLCLR_DATA_U_MASK (0xFFFFF000U) +#define SYSCON_PRESETCTRLCLR_DATA_U_SHIFT (12U) +/*! DATA_U - Data array value + */ +#define SYSCON_PRESETCTRLCLR_DATA_U(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_U_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_U_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (4U) + +/*! @name SWR_RESET - Software Reset */ +/*! @{ */ + +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) + +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_FLEXSPI_MASK (0x400U) +#define SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT (10U) +/*! FLEXSPI - Enables the clock for the Flexspi. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT)) & SYSCON_AHBCLKCTRL0_FLEXSPI_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + +#define SYSCON_AHBCLKCTRL0_ADC0_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC0_SHIFT (27U) +/*! ADC0 - Enables the clock for ADC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC0_MASK) + +#define SYSCON_AHBCLKCTRL0_ADC1_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL0_ADC1_SHIFT (28U) +/*! ADC1 - Enables the clock for ADC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC1_MASK) + +#define SYSCON_AHBCLKCTRL0_DAC0_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL0_DAC0_SHIFT (29U) +/*! DAC0 - Enables the clock for DAC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DAC0_SHIFT)) & SYSCON_AHBCLKCTRL0_DAC0_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_CAN_MASK (0x80U) +#define SYSCON_AHBCLKCTRL1_CAN_SHIFT (7U) +/*! CAN - Enables the clock for the CAN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_CAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_CAN_SHIFT)) & SYSCON_AHBCLKCTRL1_CAN_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_DMIC_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL1_DMIC_SHIFT (19U) +/*! DMIC - Enables the clock for DMIC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL1_DMIC_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0-FS device. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) + +#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) +/*! EZHA - Enables the clock for the EZH a. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) + +#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) +#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) +/*! EZHB - Enables the clock for the EZH b. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Analog comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) + +#define SYSCON_AHBCLKCTRL2_PMUX1_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL2_PMUX1_SHIFT (14U) +/*! PMUX1 - Enables the clock for Peripheral Input Mux 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PMUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PMUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_PMUX1_MASK) + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0-FS Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0-FS Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) + +#define SYSCON_AHBCLKCTRL2_CSS_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_CSS_SHIFT (18U) +/*! CSS - Enables the clock for CSS. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CSS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CSS_SHIFT)) & SYSCON_AHBCLKCTRL2_CSS_MASK) + +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_PKC_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_PKC_SHIFT (24U) +/*! PKC - Enables the clock for the PKC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK) + +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the Analog Controller block. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL2_HS_SPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_SPI_SHIFT (28U) +/*! HS_SPI - Enables the clock for the HS SPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_SPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_SPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_SPI_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL3 - AHB Clock Control 3 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL3_I3C0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL3_I3C0_SHIFT (0U) +/*! I3C0 - Enables the clock for I3C0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK) + +#define SYSCON_AHBCLKCTRL3_ENC0_MASK (0x8U) +#define SYSCON_AHBCLKCTRL3_ENC0_SHIFT (3U) +/*! ENC0 - Enables the clock for ENC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_ENC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC0_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC0_MASK) + +#define SYSCON_AHBCLKCTRL3_ENC1_MASK (0x10U) +#define SYSCON_AHBCLKCTRL3_ENC1_SHIFT (4U) +/*! ENC1 - Enables the clock for ENC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_ENC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC1_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC1_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x20U) +#define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (5U) +/*! PWM0 - Enables the clock for PWM0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM1_MASK (0x40U) +#define SYSCON_AHBCLKCTRL3_PWM1_SHIFT (6U) +/*! PWM1 - Enables the clock for PWM1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK) + +#define SYSCON_AHBCLKCTRL3_AOI0_MASK (0x80U) +#define SYSCON_AHBCLKCTRL3_AOI0_SHIFT (7U) +/*! AOI0 - Enables the clock for AOI0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_AOI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_AOI0_SHIFT)) & SYSCON_AHBCLKCTRL3_AOI0_MASK) + +#define SYSCON_AHBCLKCTRL3_AOI1_MASK (0x100U) +#define SYSCON_AHBCLKCTRL3_AOI1_SHIFT (8U) +/*! AOI1 - Enables the clock for AOI1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_AOI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_AOI1_SHIFT)) & SYSCON_AHBCLKCTRL3_AOI1_MASK) + +#define SYSCON_AHBCLKCTRL3_FTM0_MASK (0x200U) +#define SYSCON_AHBCLKCTRL3_FTM0_SHIFT (9U) +/*! FTM0 - Enables the clock for FTM0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_FTM0_SHIFT)) & SYSCON_AHBCLKCTRL3_FTM0_MASK) + +#define SYSCON_AHBCLKCTRL3_DAC1_MASK (0x400U) +#define SYSCON_AHBCLKCTRL3_DAC1_SHIFT (10U) +/*! DAC1 - Enables the clock for DAC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC1_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC1_MASK) + +#define SYSCON_AHBCLKCTRL3_DAC2_MASK (0x800U) +#define SYSCON_AHBCLKCTRL3_DAC2_SHIFT (11U) +/*! DAC2 - Enables the clock for DAC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC2_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC2_MASK) + +#define SYSCON_AHBCLKCTRL3_OPAMP0_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT (12U) +/*! OPAMP0 - Enables the clock for OPAMP0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP0_MASK) + +#define SYSCON_AHBCLKCTRL3_OPAMP1_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT (13U) +/*! OPAMP1 - Enables the clock for OPAMP1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP1_MASK) + +#define SYSCON_AHBCLKCTRL3_OPAMP2_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT (14U) +/*! OPAMP2 - Enables the clock for OPAMP2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP2_MASK) + +#define SYSCON_AHBCLKCTRL3_HSCMP0_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL3_HSCMP0_SHIFT (15U) +/*! HSCMP0 - Enables the clock for HSCMP0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP0_MASK) + +#define SYSCON_AHBCLKCTRL3_HSCMP1_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL3_HSCMP1_SHIFT (16U) +/*! HSCMP1 - Enables the clock for HSCMP1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP1_MASK) + +#define SYSCON_AHBCLKCTRL3_HSCMP2_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL3_HSCMP2_SHIFT (17U) +/*! HSCMP2 - Enables the clock for HSCMP2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP2_MASK) + +#define SYSCON_AHBCLKCTRL3_VREF_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL3_VREF_SHIFT (18U) +/*! VREF - Enables the clock for VREF. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL3_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLSET - AHB Clock Control Set */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (4U) + +/*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (4U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL - CTimer 0 clock source select..CTimer 4 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSEL */ +#define SYSCON_CTIMERCLKSEL_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock source select A */ +/*! @{ */ + +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock source select A + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select B */ +/*! @{ */ + +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select B + * 0b000..Use the source selected in MAINCLKSELA. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b0000..Main clock. + * 0b0001..PLL0 clock. + * 0b0010..CLKIN clock. + * 0b0011..FRO 96 MHz clock. + * 0b0100..FRO 1MHz clock. + * 0b0101..PLL1 clock. + * 0b0110..Oscillator 32kHz clock. + * 0b0111..No clock. + * 0b1000..Reserved. + * 0b1001..Reserved. + * 0b1010..Reserved. + * 0b1011..Reserved. + * 0b1100..No clock. + * 0b1101..No clock. + * 0b1110..No clock. + * 0b1111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ + +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ + +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CANCLKSEL - CAN clock source select */ +/*! @{ */ + +#define SYSCON_CANCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CANCLKSEL_SEL_SHIFT (0U) +/*! SEL - CAN clock source select. + * 0b000..CAN divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_CANCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKSEL_SEL_SHIFT)) & SYSCON_CANCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC0CLKSEL - ADC0 clock source select */ +/*! @{ */ + +#define SYSCON_ADC0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC0CLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..XO to ADC Clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADC0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ + +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL - Flexcomm 0 clock source select for Fractional Rate Divider..Flexcomm 7 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL_SEL_SHIFT (0U) +/*! SEL - Flexcomm 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSEL */ +#define SYSCON_FCCLKSEL_COUNT (8U) + +/*! @name HSSPICLKSEL - HS SPI clock source select */ +/*! @{ */ + +#define SYSCON_HSSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS SPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSSPICLKSEL_SEL_SHIFT)) & SYSCON_HSSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ + +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..Reserved. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ + +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..PLL1 clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV - System Tick Timer divider for CPU0 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKDIV */ +#define SYSCON_SYSTICKCLKDIV_COUNT (1U) + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CANCLKDIV - CAN clock divider */ +/*! @{ */ + +#define SYSCON_CANCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CANCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_CANCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_DIV_SHIFT)) & SYSCON_CANCLKDIV_DIV_MASK) + +#define SYSCON_CANCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CANCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CANCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_RESET_SHIFT)) & SYSCON_CANCLKDIV_RESET_MASK) + +#define SYSCON_CANCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CANCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CANCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_HALT_SHIFT)) & SYSCON_CANCLKDIV_HALT_MASK) + +#define SYSCON_CANCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CANCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CANCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_UNSTAB_SHIFT)) & SYSCON_CANCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FRGCTRL - Fractional rate divider for flexcomm 0..Fractional rate divider for flexcomm 7 */ +/*! @{ */ + +#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_FRGCTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) + +#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_FRGCTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) +/*! @} */ + +/* The count of SYSCON_FRGCTRL */ +#define SYSCON_FRGCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ + +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + +#define SYSCON_WDTCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_UNSTAB_SHIFT)) & SYSCON_WDTCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name ADC0CLKDIV - ADC0 clock divider */ +/*! @{ */ + +#define SYSCON_ADC0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_ADC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK) + +#define SYSCON_ADC0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK) + +#define SYSCON_ADC0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK) + +#define SYSCON_ADC0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADC0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0-FS Clock divider */ +/*! @{ */ + +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + +#define SYSCON_USB0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_UNSTAB_SHIFT)) & SYSCON_USB0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ + +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + +#define SYSCON_MCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_MCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_UNSTAB_SHIFT)) & SYSCON_MCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ + +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + +#define SYSCON_SCTCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_UNSTAB_SHIFT)) & SYSCON_SCTCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLLCLKDIV - PLL clock divider */ +/*! @{ */ + +#define SYSCON_PLLCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLLCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK) + +#define SYSCON_PLLCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLLCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK) + +#define SYSCON_PLLCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLLCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK) + +#define SYSCON_PLLCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLLCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLLCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer 0 clock divider..CTimer 4 clock divider */ +/*! @{ */ + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running. + * 0b1..Divider clock has stopped. + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Stable divider clock. + * 0b1..Unstable clock frequency. + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT (5U) + +/*! @name CLKUNLOCK - Clock configuration unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Control clock configuration registers access (for example, xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..Update all clock configuration. + * 0b00000000000000000000000000000000..All hardware clock configruration are freeze. + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration */ +/*! @{ */ + +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. + */ +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. + */ +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) + +#define SYSCON_FMCCR_ECCABORTEN_MASK (0x300000U) +#define SYSCON_FMCCR_ECCABORTEN_SHIFT (20U) +/*! ECCABORTEN - ECC error abort enable + */ +#define SYSCON_FMCCR_ECCABORTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ECCABORTEN_SHIFT)) & SYSCON_FMCCR_ECCABORTEN_MASK) + +#define SYSCON_FMCCR_CLKDIV_MASK (0xC000000U) +#define SYSCON_FMCCR_CLKDIV_SHIFT (26U) +/*! CLKDIV - CLKDIV; default value is 00. + * 0b00..1 division + * 0b01..2 division + * 0b10..3 division + * 0b11..4 division + */ +#define SYSCON_FMCCR_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_CLKDIV_SHIFT)) & SYSCON_FMCCR_CLKDIV_MASK) +/*! @} */ + +/*! @name ROMCR - ROM wait state */ +/*! @{ */ + +#define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) +#define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) +/*! ROM_WAIT - ROM waiting Arm core and other masters. + */ +#define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKCTRL - USB0-FS need clock control */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKSTAT - USB0-FS need clock status */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal status:. + * 0b1..USB0-FS Device clock is high. + * 0b0..USB0-FS Device clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal status:. + * 0b1..USB0-FS Host clock is high. + * 0b0..USB0-FS Host clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name EZHINT - EZH interrupt hijack */ +/*! @{ */ + +#define SYSCON_EZHINT_EZHINT_MASK (0xFFFFFFFFU) +#define SYSCON_EZHINT_EZHINT_SHIFT (0U) +/*! EZHINT - EZH interrupt hijack. + */ +#define SYSCON_EZHINT_EZHINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EZHINT_EZHINT_SHIFT)) & SYSCON_EZHINT_EZHINT_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMC flush control */ +/*! @{ */ + +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action. + */ +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b0..input mode. + * 0b1..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name ADC1CLKSEL - ADC1 clock source select */ +/*! @{ */ + +#define SYSCON_ADC1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC1CLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..XO to ADC clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADC1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC1CLKDIV - ADC1 clock divider */ +/*! @{ */ + +#define SYSCON_ADC1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_ADC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK) + +#define SYSCON_ADC1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK) + +#define SYSCON_ADC1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK) + +#define SYSCON_ADC1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADC1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name RAM_INTERLEAVE - Control RAM interleave integration */ +/*! @{ */ + +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) +/*! INTERLEAVE - Control RAM access for RAM_02 and RAM_03. + * 0b1..RAM access to RAM_02 and RAM_03 is interleaved. This setting is need for PKC L0 memory access. + * 0b0..RAM access to RAM_02 and RAM_03 is consecutive. + */ +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) +/*! @} */ + +/*! @name DAC_CLKSEL - DAC0 functional clock selection..DAC2 functional clock selection */ +/*! @{ */ + +#define SYSCON_DAC_CLKSEL_SEL_MASK (0x7U) +#define SYSCON_DAC_CLKSEL_SEL_SHIFT (0U) +/*! SEL - DAC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO_HF. + * 0b100..FRO_12M. + * 0b101..PLL1 clock. + * 0b110..FRO_1M. + * 0b111..No clock. + */ +#define SYSCON_DAC_CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKSEL_SEL_SHIFT)) & SYSCON_DAC_CLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_DAC_CLKSEL */ +#define SYSCON_DAC_CLKSEL_COUNT (3U) + +/*! @name DAC_CLKDIV - DAC0 functional clock divider..DAC2 functional clock divider */ +/*! @{ */ + +#define SYSCON_DAC_CLKDIV_DIV_MASK (0x7U) +#define SYSCON_DAC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_DAC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_DIV_SHIFT)) & SYSCON_DAC_CLKDIV_DIV_MASK) + +#define SYSCON_DAC_CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_DAC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_DAC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_RESET_SHIFT)) & SYSCON_DAC_CLKDIV_RESET_MASK) + +#define SYSCON_DAC_CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_DAC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_DAC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_HALT_SHIFT)) & SYSCON_DAC_CLKDIV_HALT_MASK) + +#define SYSCON_DAC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_DAC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_DAC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_UNSTAB_SHIFT)) & SYSCON_DAC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_DAC_CLKDIV */ +#define SYSCON_DAC_CLKDIV_COUNT (3U) + +/*! @name FLEXSPICLKSEL - FLEXSPI clock selection */ +/*! @{ */ + +#define SYSCON_FLEXSPICLKSEL_SEL_MASK (0xFU) +#define SYSCON_FLEXSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - Flexspi clock select + * 0b0000..Main clock + * 0b0001..PLL0 clock + * 0b0010..No clock + * 0b0011..FRO_HF + * 0b0100..No clock + * 0b0101..PLL1 clock + * 0b0110..No clock + * 0b0111..No clock + * 0b1000..No clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_FLEXSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKSEL_SEL_SHIFT)) & SYSCON_FLEXSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXSPICLKDIV - FLEXSPI clock divider */ +/*! @{ */ + +#define SYSCON_FLEXSPICLKDIV_DIV_MASK (0x7U) +#define SYSCON_FLEXSPICLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_FLEXSPICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_DIV_SHIFT)) & SYSCON_FLEXSPICLKDIV_DIV_MASK) + +#define SYSCON_FLEXSPICLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXSPICLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FLEXSPICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_RESET_SHIFT)) & SYSCON_FLEXSPICLKDIV_RESET_MASK) + +#define SYSCON_FLEXSPICLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXSPICLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FLEXSPICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_HALT_SHIFT)) & SYSCON_FLEXSPICLKDIV_HALT_MASK) + +#define SYSCON_FLEXSPICLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FLEXSPICLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXSPICLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CDPA_ENABLE - Enable protection */ +/*! @{ */ + +#define SYSCON_CDPA_ENABLE_CDPA_ENABLE_MASK (0x3U) +#define SYSCON_CDPA_ENABLE_CDPA_ENABLE_SHIFT (0U) +/*! CDPA_ENABLE - Enable control + */ +#define SYSCON_CDPA_ENABLE_CDPA_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_ENABLE_CDPA_ENABLE_SHIFT)) & SYSCON_CDPA_ENABLE_CDPA_ENABLE_MASK) +/*! @} */ + +/*! @name CDPA_ENABLE_DP - Enable protection duplicate */ +/*! @{ */ + +#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_MASK (0x3U) +#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_SHIFT (0U) +/*! CDPA_ENABLE_DP - Enable control + */ +#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_SHIFT)) & SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_MASK) +/*! @} */ + +/*! @name CDPA_CONFIG - CDPA base address */ +/*! @{ */ + +#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE_MASK (0x1FFU) +#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE_SHIFT (0U) +/*! CDPA_START_PAGE - Specifies the size of CDPA in number of pages. + */ +#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_CONFIG_CDPA_START_PAGE_SHIFT)) & SYSCON_CDPA_CONFIG_CDPA_START_PAGE_MASK) +/*! @} */ + +/*! @name FLASH_HIDING_LOCKOUT_ADDR - Flash hiding lockout address */ +/*! @{ */ + +#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_MASK (0xFFFFFFFFU) +#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_SHIFT (0U) +/*! flash_hiding_lockout_addr - while flash hiding is disabled, register write is locked. + */ +#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_SHIFT)) & SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_MASK) +/*! @} */ + +/*! @name FLASH_HIDING_BASE_ADDR - Flash hiding base address */ +/*! @{ */ + +#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_MASK (0x3FFFFU) +#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_SHIFT (0U) +/*! flash_hiding_base_addr - Base address for flash hiding + */ +#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_SHIFT)) & SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_MASK) +/*! @} */ + +/*! @name FLASH_HIDING_BASE_DP_ADDR - Flash hiding base DP address */ +/*! @{ */ + +#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_MASK (0x3FFFFU) +#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_SHIFT (0U) +/*! flash_hiding_base_addr - Base address for flash hiding + */ +#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_SHIFT)) & SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_MASK) +/*! @} */ + +/*! @name FLASH_HIDING_SIZE_ADDR - Hiding size address */ +/*! @{ */ + +#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_MASK (0x3FFFFU) +#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_SHIFT (0U) +/*! flash_hiding_size_addr - Size address for flash hiding + */ +#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_SHIFT)) & SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_MASK) +/*! @} */ + +/*! @name FLASH_HIDING_SIZE_DP_ADDR - Hiding size DP address */ +/*! @{ */ + +#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_MASK (0x3FFFFU) +#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_SHIFT (0U) +/*! flash_hiding_size_dp_addr - Size address for flash hiding + */ +#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_SHIFT)) & SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_MASK) +/*! @} */ + +/*! @name PLLCLKDIVSEL - PLL clock divider clock selection */ +/*! @{ */ + +#define SYSCON_PLLCLKDIVSEL_SEL_MASK (0x7U) +#define SYSCON_PLLCLKDIVSEL_SEL_SHIFT (0U) +/*! SEL - Flexspi clock select + * 0b000..PLL0 clock + * 0b001..PLL1 clock + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_PLLCLKDIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK) +/*! @} */ + +/*! @name I3CFCLKSEL - I3C functional clock selection */ +/*! @{ */ + +#define SYSCON_I3CFCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3CFCLKSEL_SEL_SHIFT (0U) +/*! SEL - I3C clock select + * 0b000..Main clock + * 0b001..FRO_HF_DIV + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_I3CFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3CFCLKSTCSEL - I3C FCLK_STC clock selection */ +/*! @{ */ + +#define SYSCON_I3CFCLKSTCSEL_SEL_MASK (0x7U) +#define SYSCON_I3CFCLKSTCSEL_SEL_SHIFT (0U) +/*! SEL - I3C FCLK_STC clock select + * 0b000..I3CFCLK + * 0b001..FRO_1M + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_I3CFCLKSTCSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSTCSEL_SEL_MASK) +/*! @} */ + +/*! @name I3CFCLKSTCDIV - I3C FCLK_STC clock divider */ +/*! @{ */ + +#define SYSCON_I3CFCLKSTCDIV_DIV_MASK (0x7U) +#define SYSCON_I3CFCLKSTCDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_I3CFCLKSTCDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3CFCLKSTCDIV_DIV_MASK) + +#define SYSCON_I3CFCLKSTCDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3CFCLKSTCDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_I3CFCLKSTCDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3CFCLKSTCDIV_RESET_MASK) + +#define SYSCON_I3CFCLKSTCDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3CFCLKSTCDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_I3CFCLKSTCDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3CFCLKSTCDIV_HALT_MASK) + +#define SYSCON_I3CFCLKSTCDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3CFCLKSTCDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_I3CFCLKSTCDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKSTCDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name I3CFCLKSDIV - I3C FCLKS clock divider */ +/*! @{ */ + +#define SYSCON_I3CFCLKSDIV_DIV_MASK (0x7U) +#define SYSCON_I3CFCLKSDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_I3CFCLKSDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_DIV_SHIFT)) & SYSCON_I3CFCLKSDIV_DIV_MASK) + +#define SYSCON_I3CFCLKSDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3CFCLKSDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_I3CFCLKSDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_RESET_SHIFT)) & SYSCON_I3CFCLKSDIV_RESET_MASK) + +#define SYSCON_I3CFCLKSDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3CFCLKSDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_I3CFCLKSDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_HALT_SHIFT)) & SYSCON_I3CFCLKSDIV_HALT_MASK) + +#define SYSCON_I3CFCLKSDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3CFCLKSDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_I3CFCLKSDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKSDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name I3CFCLKDIV - I3C FCLK divider */ +/*! @{ */ + +#define SYSCON_I3CFCLKDIV_DIV_MASK (0x7U) +#define SYSCON_I3CFCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_I3CFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_DIV_SHIFT)) & SYSCON_I3CFCLKDIV_DIV_MASK) + +#define SYSCON_I3CFCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3CFCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_I3CFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_RESET_SHIFT)) & SYSCON_I3CFCLKDIV_RESET_MASK) + +#define SYSCON_I3CFCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3CFCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_I3CFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_HALT_SHIFT)) & SYSCON_I3CFCLKDIV_HALT_MASK) + +#define SYSCON_I3CFCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3CFCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_I3CFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name I3CFCLKSSEL - I3C FCLK_S selection */ +/*! @{ */ + +#define SYSCON_I3CFCLKSSEL_SEL_MASK (0x7U) +#define SYSCON_I3CFCLKSSEL_SEL_SHIFT (0U) +/*! SEL - I3C FCLK_S clock select + * 0b000..FRO_1M + * 0b001..No clock + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_I3CFCLKSSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSSEL_SEL_MASK) +/*! @} */ + +/*! @name DMICFCLKSEL - DMIC clock selection */ +/*! @{ */ + +#define SYSCON_DMICFCLKSEL_SEL_MASK (0x7U) +#define SYSCON_DMICFCLKSEL_SEL_SHIFT (0U) +/*! SEL - DMIC clock select + * 0b000..Main clock + * 0b001..PLL0 clock + * 0b010..Clock in + * 0b011..FRO_HF + * 0b100..PLL1 clock + * 0b101..MCLK in + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_DMICFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKSEL_SEL_SHIFT)) & SYSCON_DMICFCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name DMICFCLKDIV - DMIC clock division */ +/*! @{ */ + +#define SYSCON_DMICFCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_DMICFCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_DMICFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_DIV_SHIFT)) & SYSCON_DMICFCLKDIV_DIV_MASK) + +#define SYSCON_DMICFCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_DMICFCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_DMICFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_RESET_SHIFT)) & SYSCON_DMICFCLKDIV_RESET_MASK) + +#define SYSCON_DMICFCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_DMICFCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stopped. + * 0b0..Divider clock is running. + */ +#define SYSCON_DMICFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_HALT_SHIFT)) & SYSCON_DMICFCLKDIV_HALT_MASK) + +#define SYSCON_DMICFCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_DMICFCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_DMICFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_UNSTAB_SHIFT)) & SYSCON_DMICFCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ + +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. + */ +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ + +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ + +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). + */ +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. + */ +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ + +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ + +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum control 0 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. + */ +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum control 1 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. + */ +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. + */ +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + */ +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. + */ +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. + */ +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + */ +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name DAC_ISO_CTRL - DAC Isolation Control */ +/*! @{ */ + +#define SYSCON_DAC_ISO_CTRL_DAC0_ISO_MASK (0x1U) +#define SYSCON_DAC_ISO_CTRL_DAC0_ISO_SHIFT (0U) +/*! DAC0_ISO - DAC0 Isolation + * 0b0..DAC0 isolation disabled + * 0b1..DAC0 isolation enabled + */ +#define SYSCON_DAC_ISO_CTRL_DAC0_ISO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC0_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC0_ISO_MASK) + +#define SYSCON_DAC_ISO_CTRL_DAC1_ISO_MASK (0x2U) +#define SYSCON_DAC_ISO_CTRL_DAC1_ISO_SHIFT (1U) +/*! DAC1_ISO - DAC1 Isolation + * 0b0..DAC1 isolation disabled + * 0b1..DAC1 isolation enabled + */ +#define SYSCON_DAC_ISO_CTRL_DAC1_ISO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC1_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC1_ISO_MASK) + +#define SYSCON_DAC_ISO_CTRL_DAC2_ISO_MASK (0x4U) +#define SYSCON_DAC_ISO_CTRL_DAC2_ISO_SHIFT (2U) +/*! DAC2_ISO - DAC2 Isolation + * 0b0..DAC2 isolation disabled + * 0b1..DAC2 isolation enabled + */ +#define SYSCON_DAC_ISO_CTRL_DAC2_ISO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC2_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC2_ISO_MASK) +/*! @} */ + +/*! @name STARTER - Start logic wake-up enable */ +/*! @{ */ + +#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_MASK (0x1U) +#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_SHIFT (0U) +/*! FLEXPWM1_COMPARE1_IRQ - FlexPWM1 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_MASK) + +#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) +#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) +/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) + +#define SYSCON_STARTER_SYS_MASK (0x1U) +#define SYSCON_STARTER_SYS_SHIFT (0U) +/*! SYS - SYS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) + +#define SYSCON_STARTER_CSS_IRQ1_MASK (0x2U) +#define SYSCON_STARTER_CSS_IRQ1_SHIFT (1U) +/*! CSS_IRQ1 - CSS_IRQ1 (Digital Glitch Detect) + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CSS_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CSS_IRQ1_SHIFT)) & SYSCON_STARTER_CSS_IRQ1_MASK) + +#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_MASK (0x2U) +#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_SHIFT (1U) +/*! FLEXPWM1_RELOAD1_IRQ - FlexPWM1 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_MASK) + +#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) +#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) +/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) + +#define SYSCON_STARTER_SDMA0_MASK (0x2U) +#define SYSCON_STARTER_SDMA0_SHIFT (1U) +/*! SDMA0 - SDMA0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) + +#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_MASK (0x4U) +#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_SHIFT (2U) +/*! FLEXPWM1_COMPARE2_IRQ - FlexPWM1 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_MASK) + +#define SYSCON_STARTER_GINT0_MASK (0x4U) +#define SYSCON_STARTER_GINT0_SHIFT (2U) +/*! GINT0 - GINT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) + +#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) +#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) +/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) + +#define SYSCON_STARTER_TAMPER_IRQ_MASK (0x4U) +#define SYSCON_STARTER_TAMPER_IRQ_SHIFT (2U) +/*! TAMPER_IRQ - Tamper interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_TAMPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_TAMPER_IRQ_SHIFT)) & SYSCON_STARTER_TAMPER_IRQ_MASK) + +#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_MASK (0x8U) +#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_SHIFT (3U) +/*! FLEXPWM1_RELOAD2_IRQ - FlexPWM1 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_MASK) + +#define SYSCON_STARTER_GINT1_MASK (0x8U) +#define SYSCON_STARTER_GINT1_SHIFT (3U) +/*! GINT1 - GINT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) + +#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) +#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) +/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) + +#define SYSCON_STARTER_CTIMER2_MASK (0x10U) +#define SYSCON_STARTER_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) + +#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_MASK (0x10U) +#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_SHIFT (4U) +/*! FLEXPWM1_COMPARE3_IRQ - FlexPWM1 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_MASK) + +#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) +#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) +/*! PIO_INT0 - PIO_INT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) + +#define SYSCON_STARTER_CTIMER4_MASK (0x20U) +#define SYSCON_STARTER_CTIMER4_SHIFT (5U) +/*! CTIMER4 - CTIMER4 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) + +#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_MASK (0x20U) +#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_SHIFT (5U) +/*! FLEXPWM1_RELOAD3_IRQ - FlexPWM1 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_MASK) + +#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) +#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) +/*! PIO_INT1 - PIO_INT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) + +#define SYSCON_STARTER_ENCO_COMPARE_IRQ_MASK (0x40U) +#define SYSCON_STARTER_ENCO_COMPARE_IRQ_SHIFT (6U) +/*! ENCO_COMPARE_IRQ - ENC0 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENCO_COMPARE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_COMPARE_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_COMPARE_IRQ_MASK) + +#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) +#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) +/*! OS_EVENT - OS_EVENT interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) + +#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) +#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) +/*! PIO_INT2 - PIO_INT2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) + +#define SYSCON_STARTER_ENCO_HOME_IRQ_MASK (0x80U) +#define SYSCON_STARTER_ENCO_HOME_IRQ_SHIFT (7U) +/*! ENCO_HOME_IRQ - ENC0 home interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENCO_HOME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_HOME_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_HOME_IRQ_MASK) + +#define SYSCON_STARTER_FLEXSPI_MASK (0x80U) +#define SYSCON_STARTER_FLEXSPI_SHIFT (7U) +/*! FLEXSPI - FLEXSPI interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXSPI_SHIFT)) & SYSCON_STARTER_FLEXSPI_MASK) + +#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) +#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) +/*! PIO_INT3 - PIO_INT3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) + +#define SYSCON_STARTER_ENCO_WDG_IRQ_MASK (0x100U) +#define SYSCON_STARTER_ENCO_WDG_IRQ_SHIFT (8U) +/*! ENCO_WDG_IRQ - ENC0 WDOG interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENCO_WDG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_WDG_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_WDG_IRQ_MASK) + +#define SYSCON_STARTER_UTICK0_MASK (0x100U) +#define SYSCON_STARTER_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) + +#define SYSCON_STARTER_ENCO_IDX_IRQ_MASK (0x200U) +#define SYSCON_STARTER_ENCO_IDX_IRQ_SHIFT (9U) +/*! ENCO_IDX_IRQ - ENC0 IDX interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENCO_IDX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_IDX_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_IDX_IRQ_MASK) + +#define SYSCON_STARTER_MRT0_MASK (0x200U) +#define SYSCON_STARTER_MRT0_SHIFT (9U) +/*! MRT0 - MRT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) + +#define SYSCON_STARTER_CTIMER0_MASK (0x400U) +#define SYSCON_STARTER_CTIMER0_SHIFT (10U) +/*! CTIMER0 - CTIMER0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) + +#define SYSCON_STARTER_DAC0_IRQ_MASK (0x400U) +#define SYSCON_STARTER_DAC0_IRQ_SHIFT (10U) +/*! DAC0_IRQ - DAC0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_DAC0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC0_IRQ_SHIFT)) & SYSCON_STARTER_DAC0_IRQ_MASK) + +#define SYSCON_STARTER_ENC1_COMPARE_IRQ_MASK (0x400U) +#define SYSCON_STARTER_ENC1_COMPARE_IRQ_SHIFT (10U) +/*! ENC1_COMPARE_IRQ - ENC1 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENC1_COMPARE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_COMPARE_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_COMPARE_IRQ_MASK) + +#define SYSCON_STARTER_CAN0_IRQ0_MASK (0x800U) +#define SYSCON_STARTER_CAN0_IRQ0_SHIFT (11U) +/*! CAN0_IRQ0 - CAN0_IRQ0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CAN0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CAN0_IRQ0_SHIFT)) & SYSCON_STARTER_CAN0_IRQ0_MASK) + +#define SYSCON_STARTER_CTIMER1_MASK (0x800U) +#define SYSCON_STARTER_CTIMER1_SHIFT (11U) +/*! CTIMER1 - CTIMER1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) + +#define SYSCON_STARTER_DAC1_IRQ_MASK (0x800U) +#define SYSCON_STARTER_DAC1_IRQ_SHIFT (11U) +/*! DAC1_IRQ - DAC1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_DAC1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC1_IRQ_SHIFT)) & SYSCON_STARTER_DAC1_IRQ_MASK) + +#define SYSCON_STARTER_ENC1_HOME_IRQ_MASK (0x800U) +#define SYSCON_STARTER_ENC1_HOME_IRQ_SHIFT (11U) +/*! ENC1_HOME_IRQ - ENC1 home interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENC1_HOME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_HOME_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_HOME_IRQ_MASK) + +#define SYSCON_STARTER_CAN0_IRQ1_MASK (0x1000U) +#define SYSCON_STARTER_CAN0_IRQ1_SHIFT (12U) +/*! CAN0_IRQ1 - CAN0_IRQ0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CAN0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CAN0_IRQ1_SHIFT)) & SYSCON_STARTER_CAN0_IRQ1_MASK) + +#define SYSCON_STARTER_DAC2_IRQ_MASK (0x1000U) +#define SYSCON_STARTER_DAC2_IRQ_SHIFT (12U) +/*! DAC2_IRQ - DAC2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_DAC2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC2_IRQ_SHIFT)) & SYSCON_STARTER_DAC2_IRQ_MASK) + +#define SYSCON_STARTER_ENC1_WDG_IRQ_MASK (0x1000U) +#define SYSCON_STARTER_ENC1_WDG_IRQ_SHIFT (12U) +/*! ENC1_WDG_IRQ - ENC1 WDOG interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENC1_WDG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_WDG_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_WDG_IRQ_MASK) + +#define SYSCON_STARTER_SCT0_MASK (0x1000U) +#define SYSCON_STARTER_SCT0_SHIFT (12U) +/*! SCT0 - SCT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) + +#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTER_CTIMER3_SHIFT (13U) +/*! CTIMER3 - CTIMER3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) + +#define SYSCON_STARTER_ENC1_IDX_IRQ_MASK (0x2000U) +#define SYSCON_STARTER_ENC1_IDX_IRQ_SHIFT (13U) +/*! ENC1_IDX_IRQ - ENC1 IDX interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ENC1_IDX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_IDX_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_IDX_IRQ_MASK) + +#define SYSCON_STARTER_HS_CMP0_IRQ_MASK (0x2000U) +#define SYSCON_STARTER_HS_CMP0_IRQ_SHIFT (13U) +/*! HS_CMP0_IRQ - HS_CMP0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_HS_CMP0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP0_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP0_IRQ_MASK) + +#define SYSCON_STARTER_SPI_FILTER_MASK (0x2000U) +#define SYSCON_STARTER_SPI_FILTER_SHIFT (13U) +/*! SPI_FILTER - SPI_FILTER interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SPI_FILTER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPI_FILTER_SHIFT)) & SYSCON_STARTER_SPI_FILTER_MASK) + +#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) +#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) +/*! FLEXINT0 - FLEXINT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) + +#define SYSCON_STARTER_HS_CMP1_IRQ_MASK (0x4000U) +#define SYSCON_STARTER_HS_CMP1_IRQ_SHIFT (14U) +/*! HS_CMP1_IRQ - HS_CMP1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_HS_CMP1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP1_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP1_IRQ_MASK) + +#define SYSCON_STARTER_ITRC_IRQ_MASK (0x4000U) +#define SYSCON_STARTER_ITRC_IRQ_SHIFT (14U) +/*! ITRC_IRQ - ITRC interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ITRC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ITRC_IRQ_SHIFT)) & SYSCON_STARTER_ITRC_IRQ_MASK) + +#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) +#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) +/*! FLEXINT1 - FLEXINT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) + +#define SYSCON_STARTER_HS_CMP2_IRQ_MASK (0x8000U) +#define SYSCON_STARTER_HS_CMP2_IRQ_SHIFT (15U) +/*! HS_CMP2_IRQ - HS_CMP2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_HS_CMP2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP2_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP2_IRQ_MASK) + +#define SYSCON_STARTER_CSSV2_ERR_MASK (0x10000U) +#define SYSCON_STARTER_CSSV2_ERR_SHIFT (16U) +/*! CSSV2_ERR - CSSv2 error interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CSSV2_ERR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CSSV2_ERR_SHIFT)) & SYSCON_STARTER_CSSV2_ERR_MASK) + +#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) +#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) +/*! FLEXINT2 - FLEXINT2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) + +#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_MASK (0x10000U) +#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_SHIFT (16U) +/*! FLEXPWM0_CAPTURE_IRQ - FlexPWM0 capture interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_MASK) + +#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) +#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) +/*! FLEXINT3 - FLEXINT3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) + +#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_MASK (0x20000U) +#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_SHIFT (17U) +/*! FLEXPWM0_FAULT_IRQ - FlexPWM0 fault interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_MASK) + +#define SYSCON_STARTER_PKC_ERR_IRQ_MASK (0x20000U) +#define SYSCON_STARTER_PKC_ERR_IRQ_SHIFT (17U) +/*! PKC_ERR_IRQ - PKC error interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PKC_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PKC_ERR_IRQ_SHIFT)) & SYSCON_STARTER_PKC_ERR_IRQ_MASK) + +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) + +#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) +#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) +/*! FLEXINT4 - FLEXINT4 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) + +#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_MASK (0x40000U) +#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_SHIFT (18U) +/*! FLEXPWM0_RELOAD_ERR_IRQ - FlexPWM0 reload error interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_MASK) + +#define SYSCON_STARTER_PVTVF0_AMBER_IRQ_MASK (0x40000U) +#define SYSCON_STARTER_PVTVF0_AMBER_IRQ_SHIFT (18U) +/*! PVTVF0_AMBER_IRQ - PVTVF0 amber interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PVTVF0_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF0_AMBER_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF0_AMBER_IRQ_MASK) + +#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) +#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) +/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) + +#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) +#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) +/*! FLEXINT5 - FLEXINT5 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) + +#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_MASK (0x80000U) +#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_SHIFT (19U) +/*! FLEXPWM0_COMPARE0_IRQ - FlexPWM0 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_MASK) + +#define SYSCON_STARTER_PVTVF0_RED_IRQ_MASK (0x80000U) +#define SYSCON_STARTER_PVTVF0_RED_IRQ_SHIFT (19U) +/*! PVTVF0_RED_IRQ - PVTVF0 red interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PVTVF0_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF0_RED_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF0_RED_IRQ_MASK) + +#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) +#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) +/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) + +#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) +#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) +/*! FLEXINT6 - FLEXINT6 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) + +#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_MASK (0x100000U) +#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_SHIFT (20U) +/*! FLEXPWM0_RELOAD0_IRQ - FlexPWM0 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_MASK) + +#define SYSCON_STARTER_FREQ_ME_PLUS_MASK (0x100000U) +#define SYSCON_STARTER_FREQ_ME_PLUS_SHIFT (20U) +/*! FREQ_ME_PLUS - FREQME interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FREQ_ME_PLUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FREQ_ME_PLUS_SHIFT)) & SYSCON_STARTER_FREQ_ME_PLUS_MASK) + +#define SYSCON_STARTER_PVTVF1_AMBER_IRQ_MASK (0x100000U) +#define SYSCON_STARTER_PVTVF1_AMBER_IRQ_SHIFT (20U) +/*! PVTVF1_AMBER_IRQ - PVTVF1 amber interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PVTVF1_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF1_AMBER_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF1_AMBER_IRQ_MASK) + +#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) +#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) +/*! FLEXINT7 - FLEXINT7 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) + +#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_MASK (0x200000U) +#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_SHIFT (21U) +/*! FLEXPWM0_COMPARE1_IRQ - FlexPWM0 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_MASK) + +#define SYSCON_STARTER_PVTVF1_RED_IRQ_MASK (0x200000U) +#define SYSCON_STARTER_PVTVF1_RED_IRQ_SHIFT (21U) +/*! PVTVF1_RED_IRQ - PVTVF1 red interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PVTVF1_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF1_RED_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF1_RED_IRQ_MASK) + +#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) +#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) +/*! SEC_VIO - SEC_VIO interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) + +#define SYSCON_STARTER_ADC0_MASK (0x400000U) +#define SYSCON_STARTER_ADC0_SHIFT (22U) +/*! ADC0 - ADC0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) + +#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_MASK (0x400000U) +#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_SHIFT (22U) +/*! FLEXPWM0_RELOAD1_IRQ - FlexPWM0 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_MASK) + +#define SYSCON_STARTER_SHA_MASK (0x400000U) +#define SYSCON_STARTER_SHA_SHIFT (22U) +/*! SHA - SHA interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) + +#define SYSCON_STARTER_ADC1_MASK (0x800000U) +#define SYSCON_STARTER_ADC1_SHIFT (23U) +/*! ADC1 - ADC1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC1_SHIFT)) & SYSCON_STARTER_ADC1_MASK) + +#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_MASK (0x800000U) +#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_SHIFT (23U) +/*! FLEXPWM0_COMPARE2_IRQ - FlexPWM0 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_MASK) + +#define SYSCON_STARTER_PKC_MASK (0x800000U) +#define SYSCON_STARTER_PKC_SHIFT (23U) +/*! PKC - PKC interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PKC_SHIFT)) & SYSCON_STARTER_PKC_MASK) + +#define SYSCON_STARTER_ACMP_OVR_MASK (0x1000000U) +#define SYSCON_STARTER_ACMP_OVR_SHIFT (24U) +/*! ACMP_OVR - ACMP_OVR interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ACMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ACMP_OVR_SHIFT)) & SYSCON_STARTER_ACMP_OVR_MASK) + +#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_MASK (0x1000000U) +#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_SHIFT (24U) +/*! FLEXPWM0_RELOAD2_IRQ - FlexPWM0 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_MASK) + +#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) +#define SYSCON_STARTER_QDDKEY_SHIFT (24U) +/*! QDDKEY - QDDKEY interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) + +#define SYSCON_STARTER_DMIC_MASK (0x2000000U) +#define SYSCON_STARTER_DMIC_SHIFT (25U) +/*! DMIC - DMIC interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK) + +#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_MASK (0x2000000U) +#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_SHIFT (25U) +/*! FLEXPWM0_COMPARE3_IRQ - FlexPWM0 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_MASK) + +#define SYSCON_STARTER_PQ_MASK (0x2000000U) +#define SYSCON_STARTER_PQ_SHIFT (25U) +/*! PQ - PQ interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) + +#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_MASK (0x4000000U) +#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_SHIFT (26U) +/*! FLEXPWM0_RELOAD3_IRQ - FlexPWM0 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_MASK) + +#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) +#define SYSCON_STARTER_SDMA1_SHIFT (26U) +/*! SDMA1 - SDMA1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) + +#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_MASK (0x8000000U) +#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_SHIFT (27U) +/*! FLEXPWM1_CAPTURE_IRQ - FlexPWM1 capture interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_MASK) + +#define SYSCON_STARTER_SPI_HS_MASK (0x8000000U) +#define SYSCON_STARTER_SPI_HS_SHIFT (27U) +/*! SPI_HS - SPI_HS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPI_HS_SHIFT)) & SYSCON_STARTER_SPI_HS_MASK) + +#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) + +#define SYSCON_STARTER_CODE_WDG0_MASK (0x10000000U) +#define SYSCON_STARTER_CODE_WDG0_SHIFT (28U) +/*! CODE_WDG0 - CODE WDG0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CODE_WDG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CODE_WDG0_SHIFT)) & SYSCON_STARTER_CODE_WDG0_MASK) + +#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_MASK (0x10000000U) +#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_SHIFT (28U) +/*! FLEXPWM1_FAULT_IRQ - FlexPWM1 fault interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_MASK) + +#define SYSCON_STARTER_USB0_MASK (0x10000000U) +#define SYSCON_STARTER_USB0_SHIFT (28U) +/*! USB0 - USB0-FS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) + +#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_MASK (0x20000000U) +#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_SHIFT (29U) +/*! FLEXPWM1_RELOAD_ERR_IRQ - FlexPWM1 reload error interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_MASK) + +#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) +#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) +/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) + +#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) +#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) +/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) + +#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_MASK (0x40000000U) +#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_SHIFT (30U) +/*! FLEXPWM1_COMPARE0_IRQ - FlexPWM1 compare interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_MASK) + +#define SYSCON_STARTER_I3C0_MASK (0x40000000U) +#define SYSCON_STARTER_I3C0_SHIFT (30U) +/*! I3C0 - I3C0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_I3C0_SHIFT)) & SYSCON_STARTER_I3C0_MASK) + +#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_MASK (0x80000000U) +#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_SHIFT (31U) +/*! FLEXPWM1_RELOAD0_IRQ - FlexPWM1 reload interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_MASK) + +#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) +#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) +/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) +/*! @} */ + +/* The count of SYSCON_STARTER */ +#define SYSCON_STARTER_COUNT (4U) + +/*! @name STARTERSET - Set bits in STARTER */ +/*! @{ */ + +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_MASK (0x1U) +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_SHIFT (0U) +/*! FLEXPWM1_COMPARE1_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) +#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) +/*! GPIO_INT04_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) + +#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) +#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) +/*! SYS_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) + +#define SYSCON_STARTERSET_CSS_SET_MASK (0x2U) +#define SYSCON_STARTERSET_CSS_SET_SHIFT (1U) +/*! CSS_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_CSS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CSS_SET_SHIFT)) & SYSCON_STARTERSET_CSS_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_MASK (0x2U) +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_SHIFT (1U) +/*! FLEXPWM1_RELOAD1_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) +#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) +/*! GPIO_INT05_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) + +#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) +#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) +/*! SDMA0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_MASK (0x4U) +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_SHIFT (2U) +/*! FLEXPWM1_COMPARE2_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) +/*! GPIO_GLOBALINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) +#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) +/*! GPIO_INT06_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) + +#define SYSCON_STARTERSET_TAMPER_SET_MASK (0x4U) +#define SYSCON_STARTERSET_TAMPER_SET_SHIFT (2U) +/*! TAMPER_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_TAMPER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_TAMPER_SET_SHIFT)) & SYSCON_STARTERSET_TAMPER_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_MASK (0x8U) +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_SHIFT (3U) +/*! FLEXPWM1_RELOAD2_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) +/*! GPIO_GLOBALINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) +#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) +/*! GPIO_INT07_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) + +#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) +#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) +/*! CTIMER2_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_MASK (0x10U) +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_SHIFT (4U) +/*! FLEXPWM1_COMPARE3_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) +#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) +/*! GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) + +#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) +#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) +/*! CTIMER4_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_MASK (0x20U) +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_SHIFT (5U) +/*! FLEXPWM1_RELOAD3_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) +#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) +/*! GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) + +#define SYSCON_STARTERSET_ENC0_COMPARE_SET_MASK (0x40U) +#define SYSCON_STARTERSET_ENC0_COMPARE_SET_SHIFT (6U) +/*! ENC0_COMPARE_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC0_COMPARE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_COMPARE_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_COMPARE_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) +#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) +/*! GPIO_INT02_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) + +#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) +#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) +/*! OS_EVENT_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) + +#define SYSCON_STARTERSET_ENC0_HOME_SET_MASK (0x80U) +#define SYSCON_STARTERSET_ENC0_HOME_SET_SHIFT (7U) +/*! ENC0_HOME_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC0_HOME_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_HOME_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_HOME_SET_MASK) + +#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) +#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) +/*! GPIO_INT03_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) + +#define SYSCON_STARTERSET_ENC0_WDG_SET_MASK (0x100U) +#define SYSCON_STARTERSET_ENC0_WDG_SET_SHIFT (8U) +/*! ENC0_WDG_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC0_WDG_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_WDG_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_WDG_SET_MASK) + +#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) +#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) +/*! UTICK0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) + +#define SYSCON_STARTERSET_ENC0_IDX_SET_MASK (0x200U) +#define SYSCON_STARTERSET_ENC0_IDX_SET_SHIFT (9U) +/*! ENC0_IDX_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC0_IDX_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_IDX_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_IDX_SET_MASK) + +#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) +#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) +/*! MRT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) + +#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) +#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) +/*! CTIMER0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) + +#define SYSCON_STARTERSET_DAC0_SET_MASK (0x400U) +#define SYSCON_STARTERSET_DAC0_SET_SHIFT (10U) +/*! DAC0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_DAC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC0_SET_SHIFT)) & SYSCON_STARTERSET_DAC0_SET_MASK) + +#define SYSCON_STARTERSET_ENC1_COMPARE_SET_MASK (0x400U) +#define SYSCON_STARTERSET_ENC1_COMPARE_SET_SHIFT (10U) +/*! ENC1_COMPARE_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC1_COMPARE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_COMPARE_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_COMPARE_SET_MASK) + +#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) +#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) +/*! CTIMER1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) + +#define SYSCON_STARTERSET_DAC1_SET_MASK (0x800U) +#define SYSCON_STARTERSET_DAC1_SET_SHIFT (11U) +/*! DAC1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_DAC1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC1_SET_SHIFT)) & SYSCON_STARTERSET_DAC1_SET_MASK) + +#define SYSCON_STARTERSET_ENC1_HOME_SET_MASK (0x800U) +#define SYSCON_STARTERSET_ENC1_HOME_SET_SHIFT (11U) +/*! ENC1_HOME_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC1_HOME_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_HOME_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_HOME_SET_MASK) + +#define SYSCON_STARTERSET_DAC2_SET_MASK (0x1000U) +#define SYSCON_STARTERSET_DAC2_SET_SHIFT (12U) +/*! DAC2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_DAC2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC2_SET_SHIFT)) & SYSCON_STARTERSET_DAC2_SET_MASK) + +#define SYSCON_STARTERSET_ENC1_WDG_SET_MASK (0x1000U) +#define SYSCON_STARTERSET_ENC1_WDG_SET_SHIFT (12U) +/*! ENC1_WDG_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC1_WDG_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_WDG_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_WDG_SET_MASK) + +#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) +#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) +/*! SCT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) + +#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) +#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) +/*! CTIMER3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) + +#define SYSCON_STARTERSET_ENC1_IDX_SET_MASK (0x2000U) +#define SYSCON_STARTERSET_ENC1_IDX_SET_SHIFT (13U) +/*! ENC1_IDX_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ENC1_IDX_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_IDX_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_IDX_SET_MASK) + +#define SYSCON_STARTERSET_HS_CMP0_SET_MASK (0x2000U) +#define SYSCON_STARTERSET_HS_CMP0_SET_SHIFT (13U) +/*! HS_CMP0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_HS_CMP0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP0_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP0_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) +#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) +/*! FLEXINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) + +#define SYSCON_STARTERSET_HS_CMP1_SET_MASK (0x4000U) +#define SYSCON_STARTERSET_HS_CMP1_SET_SHIFT (14U) +/*! HS_CMP1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_HS_CMP1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP1_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP1_SET_MASK) + +#define SYSCON_STARTERSET_ITRC_SET_MASK (0x4000U) +#define SYSCON_STARTERSET_ITRC_SET_SHIFT (14U) +/*! ITRC_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_ITRC_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ITRC_SET_SHIFT)) & SYSCON_STARTERSET_ITRC_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) +#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) +/*! FLEXINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) + +#define SYSCON_STARTERSET_HS_CMP2_SET_MASK (0x8000U) +#define SYSCON_STARTERSET_HS_CMP2_SET_SHIFT (15U) +/*! HS_CMP2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_HS_CMP2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP2_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP2_SET_MASK) + +#define SYSCON_STARTERSET_CSSV2_ERR_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_CSSV2_ERR_SET_SHIFT (16U) +/*! CSSV2_ERR_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_CSSV2_ERR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CSSV2_ERR_SET_SHIFT)) & SYSCON_STARTERSET_CSSV2_ERR_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) +/*! FLEXINT2_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_SHIFT (16U) +/*! FLEXPWM0_CAPTURE_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) +/*! FLEXINT3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_SHIFT (17U) +/*! FLEXPWM0_FAULT_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_MASK) + +#define SYSCON_STARTERSET_PKC_ERR_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_PKC_ERR_SET_SHIFT (17U) +/*! PKC_ERR_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_PKC_ERR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PKC_ERR_SET_SHIFT)) & SYSCON_STARTERSET_PKC_ERR_SET_MASK) + +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) +/*! FLEXINT4_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_SHIFT (18U) +/*! FLEXPWM0_RELOAD_ERROR_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_MASK) + +#define SYSCON_STARTERSET_PVTVF0_AMBER_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_PVTVF0_AMBER_SET_SHIFT (18U) +/*! PVTVF0_AMBER_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_PVTVF0_AMBER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF0_AMBER_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF0_AMBER_SET_MASK) + +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) +/*! SEC_GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) +/*! FLEXINT5_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_SHIFT (19U) +/*! FLEXPWM0_COMPARE0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_MASK) + +#define SYSCON_STARTERSET_PVTVF0_RED_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_PVTVF0_RED_SET_SHIFT (19U) +/*! PVTVF0_RED_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_PVTVF0_RED_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF0_RED_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF0_RED_SET_MASK) + +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) +/*! SEC_GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) +/*! FLEXINT6_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_SHIFT (20U) +/*! FLEXPWM0_RELOAD0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_MASK) + +#define SYSCON_STARTERSET_PVTVF1_AMBER_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_PVTVF1_AMBER_SET_SHIFT (20U) +/*! PVTVF1_AMBER_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_PVTVF1_AMBER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF1_AMBER_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF1_AMBER_SET_MASK) + +#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) +/*! FLEXINT7_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_SHIFT (21U) +/*! FLEXPWM0_COMPARE1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_MASK) + +#define SYSCON_STARTERSET_PVTVF1_RED_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_PVTVF1_RED_SET_SHIFT (21U) +/*! PVTVF1_RED_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register. + */ +#define SYSCON_STARTERSET_PVTVF1_RED_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF1_RED_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF1_RED_SET_MASK) + +#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) +#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) +/*! ADC0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_MASK (0x400000U) +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_SHIFT (22U) +/*! FLEXPWM0_RELOAD1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_MASK (0x800000U) +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_SHIFT (23U) +/*! FLEXPWM0_COMPARE2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_MASK) + +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) +/*! ADC0_THCMP_OVR_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_SHIFT (24U) +/*! FLEXPWM0_RELOAD2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_MASK) + +#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) +/*! QDDKEY_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_MASK (0x2000000U) +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_SHIFT (25U) +/*! FLEXPWM0_COMPARE3_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_MASK) + +#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) +#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) +/*! PQ_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_MASK (0x4000000U) +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_SHIFT (26U) +/*! FLEXPWM0_RELOAD3_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_MASK) + +#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) +#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) +/*! SDMA1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_SHIFT (27U) +/*! FLEXPWM1_CAPTURE_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_MASK) + +#define SYSCON_STARTERSET_SPI_HS_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_SPI_HS_SET_SHIFT (27U) +/*! SPI_HS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_SPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_SPI_HS_SET_MASK) + +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) +/*! USB0_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_MASK (0x10000000U) +#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_SHIFT (28U) +/*! FLEXPWM1_FAULT_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_MASK) + +#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) +#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) +/*! USB0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_MASK (0x20000000U) +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_SHIFT (29U) +/*! FLEXPWM1_RELOAD_ERROR_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_MASK) + +#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) +#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) +/*! RTC_LITE0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) + +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) +/*! EZH_ARCH_B0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_MASK (0x40000000U) +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_SHIFT (30U) +/*! FLEXPWM1_COMPARE0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_MASK) + +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_SHIFT (31U) +/*! FLEXPWM1_RELOAD0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register. + */ +#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_MASK) + +#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) +/*! WAKEUPPADS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) + +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) +/*! WAKEUP_MAILBOX0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (4U) + +/*! @name STARTERCLR - Clear bits in STARTER */ +/*! @{ */ + +#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) +#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) +/*! GPIO_INT04_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) + +#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) +#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) +/*! SYS_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) +/*! GPIO_INT05_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) + +#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) +#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) +/*! SDMA0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) +/*! GPIO_GLOBALINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) +/*! GPIO_INT06_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) +/*! GPIO_GLOBALINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) +/*! GPIO_INT07_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) + +#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) +#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) +/*! CTIMER2_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) +/*! GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) + +#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) +#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) +/*! CTIMER4_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) +/*! GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) +/*! GPIO_INT02_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) + +#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) +#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) +/*! OS_EVENT_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) + +#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) +/*! GPIO_INT03_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) + +#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) +#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) +/*! UTICK0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) + +#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) +#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) +/*! MRT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) + +#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) +#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) +/*! CTIMER0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) + +#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) +#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) +/*! CTIMER1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) + +#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) +#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) +/*! SCT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) + +#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) +#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) +/*! CTIMER3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) +#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) +/*! FLEXINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) +#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) +/*! FLEXINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) +#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) +/*! FLEXINT2_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) +#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) +/*! FLEXINT3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) + +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) +#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) +/*! FLEXINT4_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) + +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) +/*! SEC_GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) +#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) +/*! FLEXINT5_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) + +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) +/*! SEC_GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) +#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) +/*! FLEXINT6_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) + +#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) +#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) +/*! FLEXINT7_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) + +#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) +#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) +/*! ADC0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) + +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) +/*! ADC0_THCMP_OVR_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) + +#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) +#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) +/*! QDDKEY_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) + +#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) +#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) +/*! PQ_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) + +#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) +#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) +/*! SDMA1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) + +#define SYSCON_STARTERCLR_SPI_HS_CLR_MASK (0x8000000U) +#define SYSCON_STARTERCLR_SPI_HS_CLR_SHIFT (27U) +/*! SPI_HS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_SPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_SPI_HS_CLR_MASK) + +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) +/*! USB0_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) + +#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) +#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) +/*! USB0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) + +#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) +/*! RTC_LITE0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) + +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) +/*! EZH_ARCH_B0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) + +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) +/*! WAKEUPPADS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. + */ +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) + +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) +/*! WAKEUP_MAILBOX0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. + */ +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (2U) + +/*! @name FUNCRETENTIONCTRL - Functional retention control */ +/*! @{ */ + +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b1..enable functional retention. + * 0b0..disable functional retention. + */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) +/*! @} */ + +/*! @name HARDWARESLEEP - Hardware Sleep control */ +/*! @{ */ + +#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) +#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) +/*! FORCED - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. + */ +#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) + +#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) +#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) +/*! PERIPHERALS - Wake for Flexcomms. + */ +#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) + +#define SYSCON_HARDWARESLEEP_DMIC_MASK (0x4U) +#define SYSCON_HARDWARESLEEP_DMIC_SHIFT (2U) +/*! DMIC - Wake for DMIC. + */ +#define SYSCON_HARDWARESLEEP_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_DMIC_SHIFT)) & SYSCON_HARDWARESLEEP_DMIC_MASK) + +#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) +#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) +/*! SDMA0 - Wake for DMA0. + */ +#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) + +#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) +#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) +/*! SDMA1 - Wake for DMA1. + */ +#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) + +#define SYSCON_HARDWARESLEEP_DAC_MASK (0x40U) +#define SYSCON_HARDWARESLEEP_DAC_SHIFT (6U) +/*! DAC - Wake for DAC0/1/2. + */ +#define SYSCON_HARDWARESLEEP_DAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_DAC_SHIFT)) & SYSCON_HARDWARESLEEP_DAC_MASK) + +#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_MASK (0x80000000U) +#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_SHIFT (31U) +/*! HW_ENABLE_FRO192M - Set this bit if FRO192M is diabled. + */ +#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_SHIFT)) & SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disable/enable cache function. Default value is 1. + * 0b0..Enable + * 0b1..Disable + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clear cache function. Default value is 0. + * 0b0..Unclear cache + * 0b1..Clear cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Force no allocation. Default value is 0. + * 0b0..Force allocation + * 0b1..Force no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK (0x8U) +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT (3U) +/*! PARITY_MISS_EN - Enable parity miss. Default value is 0. + * 0b0..Disable + * 0b1..Enable parity, miss on parity error + */ +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK) +/*! @} */ + +/*! @name FC32KCLKSEL - Flexcomm 32K clock select */ +/*! @{ */ + +#define SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK (0x1U) +#define SYSCON_FC32KCLKSEL_FC32KCLKSEL_SHIFT (0U) +/*! FC32KCLKSEL - Flexcomm 32K clock select + * 0b0..FRO32K + * 0b1..XTAL 32K + */ +#define SYSCON_FC32KCLKSEL_FC32KCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FC32KCLKSEL_FC32KCLKSEL_SHIFT)) & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK) +/*! @} */ + +/*! @name FRGCLKSEL - FRG Clock Source Select */ +/*! @{ */ + +#define SYSCON_FRGCLKSEL_FRG_SRC_SEL_MASK (0x7U) +#define SYSCON_FRGCLKSEL_FRG_SRC_SEL_SHIFT (0U) +/*! FRG_SRC_SEL - FRG clock source select + * 0b000..main clock + * 0b001..PLL clock + * 0b010..fro_div_hf + * 0b011..None + * 0b100..None + * 0b101..None + * 0b110..None + * 0b111..None + */ +#define SYSCON_FRGCLKSEL_FRG_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_FRG_SRC_SEL_SHIFT)) & SYSCON_FRGCLKSEL_FRG_SRC_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FRGCLKSEL */ +#define SYSCON_FRGCLKSEL_COUNT (8U) + +/*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - Flexcomm clock divider */ +/*! @{ */ + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value: + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U) +/*! HALT - Reset + * 0b0..Divider clock is running + * 0b1..Divider clock has stopped + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Reset + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (8U) + +/*! @name CSS_TEMPORAL_STATE - CSS temporal state */ +/*! @{ */ + +#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U) +/*! TEMPORAL_STATE - Temporal state + */ +#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_MASK) +/*! @} */ + +/*! @name CSS_KDF_MASK - Key derivation function mask */ +/*! @{ */ + +#define SYSCON_CSS_KDF_MASK_KDF_MASK_MASK (0xFFFFFFFFU) +#define SYSCON_CSS_KDF_MASK_KDF_MASK_SHIFT (0U) +/*! KDF_MASK - Key derivation function mask. + */ +#define SYSCON_CSS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_CSS_KDF_MASK_KDF_MASK_MASK) +/*! @} */ + +/*! @name CSS_FEATURE0 - CSS command feature */ +/*! @{ */ + +#define SYSCON_CSS_FEATURE0_CIPHER_MASK (0x3U) +#define SYSCON_CSS_FEATURE0_CIPHER_SHIFT (0U) +/*! CIPHER - Enables CIPHER command. + */ +#define SYSCON_CSS_FEATURE0_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_CIPHER_MASK) + +#define SYSCON_CSS_FEATURE0_AUTH_CIPHER_MASK (0xCU) +#define SYSCON_CSS_FEATURE0_AUTH_CIPHER_SHIFT (2U) +/*! AUTH_CIPHER - Enables AUTH_CIPHER command. + */ +#define SYSCON_CSS_FEATURE0_AUTH_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_AUTH_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_AUTH_CIPHER_MASK) + +#define SYSCON_CSS_FEATURE0_ECSIGN_MASK (0x300U) +#define SYSCON_CSS_FEATURE0_ECSIGN_SHIFT (8U) +/*! ECSIGN - Enables ECSIGN command. + */ +#define SYSCON_CSS_FEATURE0_ECSIGN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECSIGN_SHIFT)) & SYSCON_CSS_FEATURE0_ECSIGN_MASK) + +#define SYSCON_CSS_FEATURE0_ECVFY_MASK (0xC00U) +#define SYSCON_CSS_FEATURE0_ECVFY_SHIFT (10U) +/*! ECVFY - Enables ECVFY command. + */ +#define SYSCON_CSS_FEATURE0_ECVFY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECVFY_SHIFT)) & SYSCON_CSS_FEATURE0_ECVFY_MASK) + +#define SYSCON_CSS_FEATURE0_ECKXCH_MASK (0x3000U) +#define SYSCON_CSS_FEATURE0_ECKXCH_SHIFT (12U) +/*! ECKXCH - Enables ECKXCH command. + */ +#define SYSCON_CSS_FEATURE0_ECKXCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECKXCH_SHIFT)) & SYSCON_CSS_FEATURE0_ECKXCH_MASK) + +#define SYSCON_CSS_FEATURE0_KEYGEN_MASK (0x30000U) +#define SYSCON_CSS_FEATURE0_KEYGEN_SHIFT (16U) +/*! KEYGEN - Enables KEYGEN command. + */ +#define SYSCON_CSS_FEATURE0_KEYGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYGEN_SHIFT)) & SYSCON_CSS_FEATURE0_KEYGEN_MASK) + +#define SYSCON_CSS_FEATURE0_KEYIN_MASK (0xC0000U) +#define SYSCON_CSS_FEATURE0_KEYIN_SHIFT (18U) +/*! KEYIN - Enables KEYIN command. + */ +#define SYSCON_CSS_FEATURE0_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYIN_SHIFT)) & SYSCON_CSS_FEATURE0_KEYIN_MASK) + +#define SYSCON_CSS_FEATURE0_KEYOUT_MASK (0x300000U) +#define SYSCON_CSS_FEATURE0_KEYOUT_SHIFT (20U) +/*! KEYOUT - Enables KEYOUT command. + */ +#define SYSCON_CSS_FEATURE0_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYOUT_SHIFT)) & SYSCON_CSS_FEATURE0_KEYOUT_MASK) + +#define SYSCON_CSS_FEATURE0_KDELETE_MASK (0xC00000U) +#define SYSCON_CSS_FEATURE0_KDELETE_SHIFT (22U) +/*! KDELETE - Enables KDELETE command. + */ +#define SYSCON_CSS_FEATURE0_KDELETE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KDELETE_SHIFT)) & SYSCON_CSS_FEATURE0_KDELETE_MASK) +/*! @} */ + +/*! @name CSS_FEATURE1 - CSS command feature */ +/*! @{ */ + +#define SYSCON_CSS_FEATURE1_CKDF_MASK (0x3U) +#define SYSCON_CSS_FEATURE1_CKDF_SHIFT (0U) +/*! CKDF - Enables CKDF command. + */ +#define SYSCON_CSS_FEATURE1_CKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_CKDF_SHIFT)) & SYSCON_CSS_FEATURE1_CKDF_MASK) + +#define SYSCON_CSS_FEATURE1_HKDF_MASK (0xCU) +#define SYSCON_CSS_FEATURE1_HKDF_SHIFT (2U) +/*! HKDF - Enables HKDF command. + */ +#define SYSCON_CSS_FEATURE1_HKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HKDF_SHIFT)) & SYSCON_CSS_FEATURE1_HKDF_MASK) + +#define SYSCON_CSS_FEATURE1_TLS_INIT_MASK (0x30U) +#define SYSCON_CSS_FEATURE1_TLS_INIT_SHIFT (4U) +/*! TLS_INIT - Enables TLS_INIT command. + */ +#define SYSCON_CSS_FEATURE1_TLS_INIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_TLS_INIT_SHIFT)) & SYSCON_CSS_FEATURE1_TLS_INIT_MASK) + +#define SYSCON_CSS_FEATURE1_HASH_MASK (0x300U) +#define SYSCON_CSS_FEATURE1_HASH_SHIFT (8U) +/*! HASH - Enables HASH command. + */ +#define SYSCON_CSS_FEATURE1_HASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HASH_SHIFT)) & SYSCON_CSS_FEATURE1_HASH_MASK) + +#define SYSCON_CSS_FEATURE1_HMAC_MASK (0xC00U) +#define SYSCON_CSS_FEATURE1_HMAC_SHIFT (10U) +/*! HMAC - Enables HMAC command. + */ +#define SYSCON_CSS_FEATURE1_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HMAC_SHIFT)) & SYSCON_CSS_FEATURE1_HMAC_MASK) + +#define SYSCON_CSS_FEATURE1_CMAC_MASK (0x3000U) +#define SYSCON_CSS_FEATURE1_CMAC_SHIFT (12U) +/*! CMAC - Enables CMAC command. + */ +#define SYSCON_CSS_FEATURE1_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_CMAC_SHIFT)) & SYSCON_CSS_FEATURE1_CMAC_MASK) + +#define SYSCON_CSS_FEATURE1_DRBG_REQ_MASK (0x30000U) +#define SYSCON_CSS_FEATURE1_DRBG_REQ_SHIFT (16U) +/*! DRBG_REQ - Enables DRBG_REQ command. + */ +#define SYSCON_CSS_FEATURE1_DRBG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DRBG_REQ_SHIFT)) & SYSCON_CSS_FEATURE1_DRBG_REQ_MASK) + +#define SYSCON_CSS_FEATURE1_DRBG_TEST_MASK (0xC0000U) +#define SYSCON_CSS_FEATURE1_DRBG_TEST_SHIFT (18U) +/*! DRBG_TEST - Enables DRBG_TEST command. + */ +#define SYSCON_CSS_FEATURE1_DRBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DRBG_TEST_SHIFT)) & SYSCON_CSS_FEATURE1_DRBG_TEST_MASK) + +#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_MASK (0x3000000U) +#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_SHIFT (24U) +/*! DTRNG_CFG_LOAD - Enables DTRNG_CFG_LOAD command. + */ +#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_MASK) + +#define SYSCON_CSS_FEATURE1_DTRNG_EVAL_MASK (0xC000000U) +#define SYSCON_CSS_FEATURE1_DTRNG_EVAL_SHIFT (26U) +/*! DTRNG_EVAL - Enables DTRNG_EVAL command. + */ +#define SYSCON_CSS_FEATURE1_DTRNG_EVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DTRNG_EVAL_SHIFT)) & SYSCON_CSS_FEATURE1_DTRNG_EVAL_MASK) + +#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_MASK (0x30000000U) +#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_SHIFT (28U) +/*! GDET_CFG_LOAD - Enables GDET_CFG_LOAD command. + */ +#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_MASK) +/*! @} */ + +/*! @name CSS_FEATURE0_DP - CSS command feature - duplicate version */ +/*! @{ */ + +#define SYSCON_CSS_FEATURE0_DP_CIPHER_MASK (0x3U) +#define SYSCON_CSS_FEATURE0_DP_CIPHER_SHIFT (0U) +/*! CIPHER - Enables CIPHER command. + */ +#define SYSCON_CSS_FEATURE0_DP_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_DP_CIPHER_MASK) + +#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_MASK (0xCU) +#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_SHIFT (2U) +/*! AUTH_CIPHER - Enables AUTH_CIPHER command. + */ +#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_MASK) + +#define SYSCON_CSS_FEATURE0_DP_ECSIGN_MASK (0x300U) +#define SYSCON_CSS_FEATURE0_DP_ECSIGN_SHIFT (8U) +/*! ECSIGN - Enables ECSIGN command. + */ +#define SYSCON_CSS_FEATURE0_DP_ECSIGN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECSIGN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECSIGN_MASK) + +#define SYSCON_CSS_FEATURE0_DP_ECVFY_MASK (0xC00U) +#define SYSCON_CSS_FEATURE0_DP_ECVFY_SHIFT (10U) +/*! ECVFY - Enables ECSIGN command. + */ +#define SYSCON_CSS_FEATURE0_DP_ECVFY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECVFY_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECVFY_MASK) + +#define SYSCON_CSS_FEATURE0_DP_ECKXCH_MASK (0x3000U) +#define SYSCON_CSS_FEATURE0_DP_ECKXCH_SHIFT (12U) +/*! ECKXCH - Enables ECSIGN command. + */ +#define SYSCON_CSS_FEATURE0_DP_ECKXCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECKXCH_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECKXCH_MASK) + +#define SYSCON_CSS_FEATURE0_DP_KEYGEN_MASK (0x30000U) +#define SYSCON_CSS_FEATURE0_DP_KEYGEN_SHIFT (16U) +/*! KEYGEN - Enables KEYGEN command. + */ +#define SYSCON_CSS_FEATURE0_DP_KEYGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYGEN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYGEN_MASK) + +#define SYSCON_CSS_FEATURE0_DP_KEYIN_MASK (0xC0000U) +#define SYSCON_CSS_FEATURE0_DP_KEYIN_SHIFT (18U) +/*! KEYIN - Enables KEYIN command. + */ +#define SYSCON_CSS_FEATURE0_DP_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYIN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYIN_MASK) + +#define SYSCON_CSS_FEATURE0_DP_KEYOUT_MASK (0x300000U) +#define SYSCON_CSS_FEATURE0_DP_KEYOUT_SHIFT (20U) +/*! KEYOUT - Enables KEYOUT command. + */ +#define SYSCON_CSS_FEATURE0_DP_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYOUT_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYOUT_MASK) + +#define SYSCON_CSS_FEATURE0_DP_KDELETE_MASK (0xC00000U) +#define SYSCON_CSS_FEATURE0_DP_KDELETE_SHIFT (22U) +/*! KDELETE - Enables KDELETE command. + */ +#define SYSCON_CSS_FEATURE0_DP_KDELETE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KDELETE_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KDELETE_MASK) +/*! @} */ + +/*! @name CSS_FEATURE1_DP - CSS command feature - duplicate version */ +/*! @{ */ + +#define SYSCON_CSS_FEATURE1_DP_CKDF_MASK (0x3U) +#define SYSCON_CSS_FEATURE1_DP_CKDF_SHIFT (0U) +/*! CKDF - Enables CKDF command. + */ +#define SYSCON_CSS_FEATURE1_DP_CKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_CKDF_SHIFT)) & SYSCON_CSS_FEATURE1_DP_CKDF_MASK) + +#define SYSCON_CSS_FEATURE1_DP_HKDF_MASK (0xCU) +#define SYSCON_CSS_FEATURE1_DP_HKDF_SHIFT (2U) +/*! HKDF - Enables HKDF command. + */ +#define SYSCON_CSS_FEATURE1_DP_HKDF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HKDF_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HKDF_MASK) + +#define SYSCON_CSS_FEATURE1_DP_TLS_INIT_MASK (0x30U) +#define SYSCON_CSS_FEATURE1_DP_TLS_INIT_SHIFT (4U) +/*! TLS_INIT - Enables TLS_INIT command. + */ +#define SYSCON_CSS_FEATURE1_DP_TLS_INIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_TLS_INIT_SHIFT)) & SYSCON_CSS_FEATURE1_DP_TLS_INIT_MASK) + +#define SYSCON_CSS_FEATURE1_DP_HASH_MASK (0x300U) +#define SYSCON_CSS_FEATURE1_DP_HASH_SHIFT (8U) +/*! HASH - Enables HASH command. + */ +#define SYSCON_CSS_FEATURE1_DP_HASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HASH_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HASH_MASK) + +#define SYSCON_CSS_FEATURE1_DP_HMAC_MASK (0xC00U) +#define SYSCON_CSS_FEATURE1_DP_HMAC_SHIFT (10U) +/*! HMAC - Enables HMAC command. + */ +#define SYSCON_CSS_FEATURE1_DP_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HMAC_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HMAC_MASK) + +#define SYSCON_CSS_FEATURE1_DP_CMAC_MASK (0x3000U) +#define SYSCON_CSS_FEATURE1_DP_CMAC_SHIFT (12U) +/*! CMAC - Enables CMAC command. + */ +#define SYSCON_CSS_FEATURE1_DP_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_CMAC_SHIFT)) & SYSCON_CSS_FEATURE1_DP_CMAC_MASK) + +#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ_MASK (0x30000U) +#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ_SHIFT (16U) +/*! DRBG_REQ - Enables DRBG_REQ command. + */ +#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DRBG_REQ_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DRBG_REQ_MASK) + +#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST_MASK (0xC0000U) +#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST_SHIFT (18U) +/*! DRBG_TEST - Enables DRBG_TEST command. + */ +#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DRBG_TEST_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DRBG_TEST_MASK) + +#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_MASK (0x3000000U) +#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_SHIFT (24U) +/*! DTRNG_CFG_LOAD - Enables DTRNG_CFG_LOAD command. + */ +#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_MASK) + +#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_MASK (0xC000000U) +#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_SHIFT (26U) +/*! DTRNG_EVAL - Enables DTRNG_EVAL command. + */ +#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_MASK) + +#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_MASK (0x30000000U) +#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_SHIFT (28U) +/*! GDET_CFG_LOAD - Enables GDET_CFG_LOAD command. + */ +#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_MASK) +/*! @} */ + +/*! @name CSS_BOOT_RETRY_CNT - CSS boot retry counter */ +/*! @{ */ + +#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_MASK (0xFFFFFFFFU) +#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_SHIFT (0U) +/*! BOOT_RETRY_CNT - Boot retry counter bit. + */ +#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_SHIFT)) & SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_MASK) +/*! @} */ + +/*! @name CSS_CLK_CTRL - CSS clock control */ +/*! @{ */ + +#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_MASK (0x1U) +#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U) +/*! GDET_REFCLK_EN - GDET reference clock enable bit. + */ +#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_MASK) + +#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_MASK (0x2U) +#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_SHIFT (1U) +/*! DTRNG_REFCLK_EN - DTRNG reference clock enable bit. + */ +#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_SHIFT)) & SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_MASK) +/*! @} */ + +/*! @name CSS_CLK_CTRL_SET - CSS clock control set */ +/*! @{ */ + +#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U) +#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U) +/*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit. + */ +#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK) + +#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_MASK (0x2U) +#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_SHIFT (1U) +/*! DTRNG_REFCLK_EN_SET - DTRNG reference clock enable set bit. + */ +#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_MASK) +/*! @} */ + +/*! @name CSS_CLK_CTRL_CLR - CSS clock control clear */ +/*! @{ */ + +#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U) +#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U) +/*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit. + */ +#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK) + +#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_MASK (0x2U) +#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_SHIFT (1U) +/*! DTRNG_REFCLK_EN_CLR - DTRNG reference clock enable clear bit. + */ +#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_MASK) +/*! @} */ + +/*! @name CSS_CLK_SEL - CSS clock select */ +/*! @{ */ + +#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_MASK (0x3U) +#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_SHIFT (0U) +/*! GDET_REFCLK_SEL - GDET reference clock select bit. + */ +#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_SHIFT)) & SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_MASK) +/*! @} */ + +/*! @name CSS_AS_CFG0 - CSS AS configuration */ +/*! @{ */ + +#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE_MASK (0xFFU) +#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE_SHIFT (0U) +/*! CFG_LC_STATE - LC state configuration bit. + */ +#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_LC_STATE_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_MASK (0x100U) +#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_SHIFT (8U) +/*! CFG_BOD_VDDMAIN_RESET_ENABLED - When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN reset is enabled, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_MASK (0x200U) +#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_SHIFT (9U) +/*! CFG_BOD_CORE_RESET_ENABLED - When BOD CORE analog detector is turned on and BOD CORE reset is enabled, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_MASK (0x400U) +#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_SHIFT (10U) +/*! CFG_BOD_VDDMAIN_IRQ_ENABLED - When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN IRQ is enabled, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_MASK (0x1000U) +#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_SHIFT (12U) +/*! CFG_WDT_ENABLED - When WatchDog Timer is activated, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_MASK (0x2000U) +#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_SHIFT (13U) +/*! CFG_CWDT_ENABLED - When Code WatchDog Timer is activated, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_MASK (0x8000U) +#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_SHIFT (15U) +/*! CFG_CSS_GDET_ENABLED - When CSS GDET is enabled, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_MASK (0x10000U) +#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_SHIFT (16U) +/*! CFG_ANA_GDET_ENABLED - When ANALOG GDET is enabled, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U) +#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U) +/*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in RTC, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_MASK (0x40000U) +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_SHIFT (18U) +/*! CFG_FLASH_IS_REMAPPED - When FLASHREMAP_OFFSET register (0x4000_0448) is not equal to 0x0000_0000, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_MASK (0x80000U) +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_SHIFT (19U) +/*! CFG_FLASH_IS_REMAPPED_DP - When FLASHREMAP_OFFSET_DP register (0x4000_044C) is not equal to 0x0000_0000, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_MASK (0xF00000U) +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_SHIFT (20U) +/*! CFG_FLASH_BANK0_ENABLE - The state of FLASHBANK_ENABLE0 register (0x4000_0450) reflects to this register as below. + */ +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_MASK (0xF000000U) +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_SHIFT (24U) +/*! CFG_FLASH_BANK1_ENABLE - The state of FLASHBANK_ENABLE1 register (0x4000_0454) reflects to this register as below: + */ +#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U) +#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U) +/*! CFG_QK_DISABLE_ENROLL - When CONFIG[DIS_PUF_ENROLL] bit is set 1, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK) + +#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U) +#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U) +/*! CFG_QK_DISABLE_WRAP - When CONFIG[DIS_PUF_WRAP_KEY] bit is set 1, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK) +/*! @} */ + +/*! @name CSS_AS_CFG1 - CSS AS configuration1 */ +/*! @{ */ + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U) +/*! CFG_SEC_DIS_STRICT_MODE - When "CFG_SEC_ENA_SEC_CHK" indicates state 0 or when + * "DISABLE_STRICT_MODE" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_REG" on AHB secure controller, both bits are + * equal to 01, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U) +/*! CFG_SEC_DIS_VIOL_ABORT - When "DISABLE_VIOLATION_ABORT" bits in "MISC_CTRL_REG" and + * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U) +/*! CFG_SEC_ENA_NS_PRIV_CHK - When "ENABLE_NS_PRIV_CHECK" bits in "MISC_CTRL_REG" and + * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U) +/*! CFG_SEC_ENA_S_PRIV_CHK - When "ENABLE_S_PRIV_CHECK" bits in "MISC_CTRL_REG" and + * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U) +/*! CFG_SEC_ENA_SEC_CHK - When "ENABLE_SECURE_CHECKING" bits in "MISC_CTRL_REG" and + * "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U) +/*! CFG_SEC_IDAU_ALLNS - When "IDAU_ALL_NS" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_REG" on AHB + * secure controller, both bits are equal to 01, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U) +/*! CFG_SEC_LOCK_NS_MPU - When "LOCK_NS_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U) +/*! CFG_SEC_LOCK_NS_VTOR - When "LOCK_NS_VTOR" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U) +/*! CFG_SEC_LOCK_S_MPU - When "LOCK_S_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U) +/*! CFG_SEC_LOCK_S_VTAIRCR - When "LOCK_S_VTAIRCR" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK) + +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U) +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U) +/*! CFG_SEC_LOCK_SAU - When "LOCK_SAU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK) +/*! @} */ + +/*! @name CSS_AS_CFG2 - CSS AS configuration2 */ +/*! @{ */ + +#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_MASK (0xFFFFFFFFU) +#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_SHIFT (0U) +/*! CFG_CSS_CMD_EN - CSS configuration command enable bit. + */ +#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_SHIFT)) & SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_MASK) +/*! @} */ + +/*! @name CSS_AS_ST0 - CSS AS state register */ +/*! @{ */ + +#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U) +/*! ST_TEMPORAL_STATE - "TEMPORAL_STATE[3:0]" on "CSS_TEMPORAL_STATE" register reflects this register. + */ +#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_MASK) + +#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_MASK (0x10U) +#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_SHIFT (4U) +/*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_MASK) + +#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_MASK (0x20U) +#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_SHIFT (5U) +/*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_MASK) + +#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_MASK (0x40U) +#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_SHIFT (6U) +/*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_MASK) + +#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_MASK (0x80U) +#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U) +/*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_MASK) + +#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U) +#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U) +/*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK) + +#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_MASK (0x2000U) +#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_SHIFT (13U) +/*! ST_CSS_DEBUG_EN - When CSS uCode code fetch out of AHB for debug is enabled, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_MASK) + +#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U) +#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U) +/*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK) + +#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_MASK (0x8000U) +#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_SHIFT (15U) +/*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1 in PMC register block, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_MASK) +/*! @} */ + +/*! @name CSS_AS_ST1 - CSS AS state1 */ +/*! @{ */ + +#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_MASK (0xFU) +#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_SHIFT (0U) +/*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block. + */ +#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_MASK) + +#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_MASK (0x10U) +#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_SHIFT (4U) +/*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block. + */ +#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_MASK) + +#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U) +#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U) +/*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1. + */ +#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK) + +#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_MASK (0x3C0U) +#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_SHIFT (6U) +/*! ST_DCDC_VOUT - VOUT[3:0] setting on DCDC0 register in PMC block will reflect to this register. + */ +#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_MASK) + +#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE_MASK (0xC00U) +#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE_SHIFT (10U) +/*! ST_BOOT_MODE - BOOTMODE[1:0] status on STATUS register in PMC block will reflect to this register. + */ +#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_CSS_AS_ST1_ST_BOOT_MODE_MASK) + +#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U) +#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U) +/*! ST_BOOT_RETRY_CNT - "BOOT_RETRY_CNT[3:0]" on "CSS_BOOT_RETRY_CNT" register reflects this register. + */ +#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_MASK) +/*! @} */ + +/*! @name CSS_AS_ST2 - CSS AS state2 */ +/*! @{ */ + +#define SYSCON_CSS_AS_ST2_CSS_AS_ST2_MASK (0xFFFFFFFFU) +#define SYSCON_CSS_AS_ST2_CSS_AS_ST2_SHIFT (0U) +/*! CSS_AS_ST2 - "BOOT_STATE[31:0]" on "CSS_BOOT_STATE" register reflects this register. + */ +#define SYSCON_CSS_AS_ST2_CSS_AS_ST2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST2_CSS_AS_ST2_SHIFT)) & SYSCON_CSS_AS_ST2_CSS_AS_ST2_MASK) +/*! @} */ + +/*! @name CSS_AS_FLAG0 - CSS AS flag0 */ +/*! @{ */ + +#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U) +#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U) +/*! FLAG_AP_ENABLE_CPU0 - This flag bit is set 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_MASK (0x10U) +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_SHIFT (4U) +/*! FLAG_BOD_VDDMAIN_RESET_OCCURED - This flag bit is set 1 when BOD VDDMAIN reset is enabled and + * BOD VDDMAIN analog detector is tripped. This register is cleared 0 by AO domain POR. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_MASK (0x20U) +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_SHIFT (5U) +/*! FLAG_BOD_CORE_RESET_OCCURED - This flag bit is set 1 when BOD CORE reset is enabled and BOD CORE + * analog detector is tripped. This register is cleared 0 by AO domain POR. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_MASK (0x40U) +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_SHIFT (6U) +/*! FLAG_BOD_VDDMAIN_IRQ_OCCURED - This flag bit is set 1 when BOD VDDMAIN IRQ is enabled and BOD + * VDDMAIN analog detector is tripped. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_MASK (0x80U) +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_SHIFT (7U) +/*! FLAG_BOD_CORE_IRQ_OCCURED - This flag bit is set 1 when BOD CORE IRQ is enabled and BOD CORE + * analog detector is tripped. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_MASK (0x100U) +#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_SHIFT (8U) +/*! FLAG_WDT_RESET_OCCURED - This flag bit is set 1 when WatchDog Timer reset is enabled and reset + * event is triggered. This register is cleared 0 by AO domain POR. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_MASK (0x200U) +#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_SHIFT (9U) +/*! FLAG_CWDT_RESET_OCCURED - This flag bit is set 1 when Code WatchDog Timer reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_MASK (0x400U) +#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_SHIFT (10U) +/*! FLAG_WDT_IRQ_OCCURED - This flag register is set 1 when WatchDog Timer IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_MASK (0x800U) +#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_SHIFT (11U) +/*! FLAG_CWDT_IRQ_OCCURED - This flag bit is set 1 when Code WatchDog Timer IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_MASK (0x1000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_SHIFT (12U) +/*! FLAG_QK_ERROR - This flag bit is set 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_MASK (0x2000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_SHIFT (13U) +/*! FLAG_CSS_GLITCH_DETECTED - This flag bit is set 1 when GDET error is flagged from CSS. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U) +/*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set 1 when ANALOG GDET error is flagged in SYSCON block. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U) +/*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set 1 when tamper event is flagged from RTC. This + * register is cleared 0 by AO domain POR or by PMC reset event, if ranmpr detection event is + * cleared by software. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U) +/*! FLAG_FLASH_ECC_INVALID - This flag bit is set 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U) +/*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set 1 when security violation is indicated from FLASH sub-system or AHB bus matrix. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U) +/*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set 1 when CPU0 (CM33) makes non-secure code + * transactions. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK) + +#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U) +#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U) +/*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag register is set 1 when CPU0 (CM33) makes non-secure data + * transactions. This register is cleared 0 by PMC reset event. + */ +#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Clock Control */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for crystal oscillator calibration + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ + +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ + +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..No interrupt pending. + * 0b1..Interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_SHIFT (1U) +/*! RAMX - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_SHIFT (2U) +/*! RAM0 - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_SHIFT (3U) +/*! RAM1 - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_SHIFT (4U) +/*! RAM2 - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_SHIFT (5U) +/*! RAM3 - Control automatic clock gating of RAM3 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_SHIFT (6U) +/*! RAM4 - Control automatic clock gating of RAM4 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - GPIO Synchronization */ +/*! @{ */ + +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchronization inside GPIO_INT module. + * 0b1..Bypass of the first stage of synchronization inside GPIO_INT module. + * 0b0..Use the first stage of synchronization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE1 - Control automatic clock gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_SHIFT (0U) +/*! DAC0 - DAC0 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_SHIFT (1U) +/*! DAC1 - DAC1 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_SHIFT (2U) +/*! DAC2 - DAC2 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_SHIFT (3U) +/*! OPAMP0 - OPAMP0 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_SHIFT (4U) +/*! OPAMP1 - OPAMP1 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_SHIFT (5U) +/*! OPAMP2 - OPAMP2 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_SHIFT (6U) +/*! HSCMP0 - HSCMP0 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_SHIFT (7U) +/*! HSCMP1 - HSCMP0 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_SHIFT (8U) +/*! HSCMP2 - HSCMP2 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF_MASK (0x200U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF_SHIFT (9U) +/*! VREF - VREF + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_VREF_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_VREF_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_MASK (0x400U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_SHIFT (10U) +/*! PWM0 - PWM0 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_SHIFT (11U) +/*! PWM1 - PWM1 + */ +#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_MASK) +/*! @} */ + +/*! @name ENABLE_MEM_PARITY_ECC_CHECK - Memory parity ECC enable */ +/*! @{ */ + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_MASK (0x1U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_SHIFT (0U) +/*! ENABLE_RAMx - Enable RAMx parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_MASK (0x2U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_SHIFT (1U) +/*! ENABLE_RAM00 - Enable RAM00 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_MASK (0x4U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_SHIFT (2U) +/*! ENABLE_RAM01 - Enable RAM01 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_MASK (0x8U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_SHIFT (3U) +/*! ENABLE_RAMx02 - Enable RAMx02 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_MASK (0x10U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_SHIFT (4U) +/*! ENABLE_RAM03 - Enable RAM03 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_MASK (0x20U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_SHIFT (5U) +/*! ENABLE_RAM1_MBIT - Enable RAM1 ECC mbit error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_MASK (0x40U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_SHIFT (6U) +/*! ENABLE_RAM1_SBIT - Enable RAM1 ECC sbit error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_MASK (0x80U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_SHIFT (7U) +/*! ENABLE_RAM2 - Enable RAM2 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_MASK (0x100U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_SHIFT (8U) +/*! ENABLE_RAM3 - Enable RAM3 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_MASK (0x200U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_SHIFT (9U) +/*! ENABLE_RAM40 - Enable RAM40 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_MASK (0x400U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_SHIFT (10U) +/*! ENABLE_RAM41 - Enable RAM41 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_MASK (0x800U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_SHIFT (11U) +/*! ENABLE_RAM42 - Enable RAM42 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_MASK (0x1000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_SHIFT (12U) +/*! ENABLE_RAM43 - Enable RAM43 parity error check + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_MASK (0x100000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_SHIFT (20U) +/*! RAMX_PARITY_ERROR_INTEN - Interrupt enable for RAMX parity error + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAMX parity error status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_MASK (0x200000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_SHIFT (21U) +/*! RAMA_PARITY_ERROR_INTEN - Interrupt enable for RAMA parity error + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAMA parity error status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_MASK (0x400000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_SHIFT (22U) +/*! RAMB_ECC_MBIT_ERROR_INTEN - Interrupt enable for RAMB ECC mbit_err + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAMB ECC mbit_err status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_MASK (0x800000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_SHIFT (23U) +/*! RAMB_ECC_SBIT_ERROR_INTEN - Interrupt enable for RAMB ECC sbit_err + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAMB ECC sbit_err status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_MASK (0x1000000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_SHIFT (24U) +/*! RAMC_PARITY_ERROR_INTEN - Interrupt enable for RAMC parity error + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAMC parity error status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_MASK (0x2000000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_SHIFT (25U) +/*! RAMD_PARITY_ERROR_INTEN - Interrupt enable for RAMD parity error + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAMD parity error status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_MASK) + +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_MASK (0x4000000U) +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_SHIFT (26U) +/*! RAME_PARITY_ERROR_INTEN - Interrupt enable for RAME parity error + * 0b0..Disable. + * 0b1..Enable RAM error interrupt when RAME parity error status flag is set. + */ +#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_MASK) +/*! @} */ + +/*! @name MEM_PARITY_ECC_ERROR_FLAG - Memory parity ECC error flag */ +/*! @{ */ + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_MASK (0x1U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_SHIFT (0U) +/*! RAMX_PARITY_ERROR - RAMx parity error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_MASK) + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_MASK (0x2U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_SHIFT (1U) +/*! RAM0_PARITY_ERROR - RAM0 parity error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_MASK) + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_MASK (0x4U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_SHIFT (2U) +/*! RAM1_ECC_MBIT_ERROR - RAM1 ECC mbit error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_MASK) + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_MASK (0x8U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_SHIFT (3U) +/*! RAM1_ECC_SBIT_ERROR - RAM1 ECC sbit error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_MASK) + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_MASK (0x10U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_SHIFT (4U) +/*! RAM2_PARITY_ERROR - RAM2 parity error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_MASK) + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_MASK (0x20U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_SHIFT (5U) +/*! RAM3_PARITY_ERROR - RAM3 parity error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_MASK) + +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_MASK (0x40U) +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_SHIFT (6U) +/*! RAM4_PARITY_ERROR - RAM4 parity error detected + * 0b0..No error detected + * 0b1..Error detected + */ +#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 submodule control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - PWM0 SUB Clock0 enable + */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - PWM0 SUB Clock1 enable + */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - PWM0 SUB Clock2 enable + */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - PWM0 SUB Clock3 enable + */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM0 submodule 0 DMA Compare Value Done Mask + */ +#define SYSCON_PWM0SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM0 submodule 1 DMA Compare Value Done Mask + */ +#define SYSCON_PWM0SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM0 submodule 2 DMA Compare Value Done Mask + */ +#define SYSCON_PWM0SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM0 submodule 3 DMA Compare Value Done Mask + */ +#define SYSCON_PWM0SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 submodule control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - PWM1 SUB Clock0 enable + */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - PWM1 SUB Clock1 enable + */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - PWM1 SUB Clock2 enable + */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - PWM1 SUB Clock3 enable + */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM1 submodule 0 DMA Compare Value Done Mask + */ +#define SYSCON_PWM1SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM1 submodule 1 DMA Compare Value Done Mask + */ +#define SYSCON_PWM1SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM1 submodule 2 DMA Compare Value Done Mask + */ +#define SYSCON_PWM1SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM1 submodule 3 DMA Compare Value Done Mask + */ +#define SYSCON_PWM1SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER global start enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - CTIMER0 function clock enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - CTIMER1 function clock enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - CTIMER2 function clock enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) +/*! CTIMER3_CLK_EN - CTIMER3 function clock enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) +/*! CTIMER4_CLK_EN - CTIMER4 function clock enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to security registers. + * 0b1010..1010: Enable write access to all registers. + * 0b0000..Any other value than b1010: disable write access to all registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex debug features control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex debug features control (duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non Invasive Debug Control + * 0b01..Disable debug + * 0b10..Enable debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678. + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register will be read as 0x5. + */ +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK) +/*! @} */ + +/* The count of SYSCON_SWD_ACCESS_CPU */ +#define SYSCON_SWD_ACCESS_CPU_COUNT (1U) + +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_DSP - DSP Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - DSP SWD-AP: 0x12345678. + * 0b00010010001101000101011001111000..Value to write to enable DSP SWD access. Reading back register will be read as 0xA. + * 0b00000000000000000000000000000000..DSP DAP is not allowed. Reading back register will be read as 0x5. + */ +#define SYSCON_SWD_ACCESS_DSP_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. + */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. + */ +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. + */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< Write Lock Out, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Shared Signal Select for Flexcomm 0..Shared Signal Select for Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Shared Signal Set 0..Shared Signal Set 1, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[248]; + __IO uint32_t CODE_GRAY_LSB; /**< Gray Code LSB Input, offset: 0x180 */ + __IO uint32_t CODE_GRAY_MSB; /**< Gray Code MSB Input, offset: 0x184 */ + __I uint32_t CODE_BIN_LSB; /**< Binary Code LSB Input, offset: 0x188 */ + __I uint32_t CODE_BIN_MSB; /**< Binary Code MSB Input, offset: 0x18C */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - Write Lock Out */ +/*! @{ */ + +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - Lock Out + * 0b0..Normal Mode: Allow writes to all registers. + * 0b1..Protected Mode: Do not allow writes to all registers except UPDATELCKOUT. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Shared Signal Select for Flexcomm 0..Shared Signal Select for Flexcomm 7 */ +/*! @{ */ + +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - SCK Input Select + * 0b00..Selects the dedicated FCn_SCK signal + * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) + * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) + * 0b11..Reserved + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - WS Input Select + * 0b00..Selects the dedicated FCn_TXD_SCL_MISO_WS signal + * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) + * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) + * 0b11..Reserved + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - DATA Input Select + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input + * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) + * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) + * 0b11..Reserved + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - DATA Output Select + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output + * 0b01..Selects from shared signal set 0 (SHAREDCTRLSET0) + * 0b10..Selects from shared signal set 1 (SHAREDCTRLSET1) + * 0b11..Reserved + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHAREDCTRLSET - Shared Signal Set 0..Shared Signal Set 1 */ +/*! @{ */ + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - SCK Source Select + * 0b000..Flexcomm 0 + * 0b001..Flexcomm 1 + * 0b010..Flexcomm 2 + * 0b011..Reserved + * 0b100..Flexcomm 4 + * 0b101..Flexcomm 5 + * 0b110..Flexcomm 6 + * 0b111..Flexcomm 7 + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - WS Source Select + * 0b000..Flexcomm 0 + * 0b001..Flexcomm 1 + * 0b010..Flexcomm 2 + * 0b011..Reserved + * 0b100..Flexcomm 4 + * 0b101..Flexcomm 5 + * 0b110..Flexcomm 6 + * 0b111..Flexcomm 7 + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - DATA Input Source Select + * 0b000..Flexcomm 0 + * 0b001..Flexcomm 1 + * 0b010..Flexcomm 2 + * 0b011..Reserved + * 0b100..Flexcomm 4 + * 0b101..Flexcomm 5 + * 0b110..Flexcomm 6 + * 0b111..Flexcomm 7 + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - DATAOUT Enable for Flexcomm 0 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - DATAOUT Enable for Flexcomm 1 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - DATAOUT Enable for Flexcomm 2 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - DATAOUT Enable for Flexcomm 4 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - DATAOUT Enable for Flexcomm 5 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - DATAOUT Enable for Flexcomm 6 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - DATAOUT Enable for Flexcomm 7 + * 0b0..Does not contribute + * 0b1..Contributes + */ +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) + +/*! @name CODE_GRAY_LSB - Gray Code LSB Input */ +/*! @{ */ + +#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK (0xFFFFFFFFU) +#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT (0U) +/*! CODE_GRAY_LSB - Gray code (least-significant) + */ +#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT)) & SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK) +/*! @} */ + +/*! @name CODE_GRAY_MSB - Gray Code MSB Input */ +/*! @{ */ + +#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK (0x3FFU) +#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT (0U) +/*! CODE_GRAY_MSB - Gray code (most-significant) + */ +#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT)) & SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK) +/*! @} */ + +/*! @name CODE_BIN_LSB - Binary Code LSB Input */ +/*! @{ */ + +#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK (0xFFFFFFFFU) +#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT (0U) +/*! CODE_BIN_LSB - Binary converted code (least-significant) + */ +#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT)) & SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK) +/*! @} */ + +/*! @name CODE_BIN_MSB - Binary Code MSB Input */ +/*! @{ */ + +#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK (0x3FFU) +#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT (0U) +/*! CODE_BIN_MSB - Binary converted code (most-significant) + */ +#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT)) & SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration, offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control, offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status, offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Read and Set for USART (not FIFO) Status, offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator, offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt Status, offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample Selection Register for Asynchronous Communication, offset: 0x28 */ + __IO uint32_t ADDR; /**< Address Register for Automatic Address Matching, offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO Configuration, offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO Status, offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO Trigger Settings for Interrupt and DMA Request, offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable, offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear, offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status, offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO Write Data, offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO Read Data, offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */ + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO Size, offset: 0xE48 */ + __IO uint32_t FIFORXTIMEOUTCFG; /**< FIFO Receive Timeout Configuration, offset: 0xE4C */ + __I uint32_t FIFORXTIMEOUTCNT; /**< FIFO Receive Timeout Counter, offset: 0xE50 */ + uint8_t RESERVED_7[424]; + __I uint32_t ID; /**< Peripheral Identification, offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration */ +/*! @{ */ + +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable + * 0b0..Disabled + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Data Length. Selects the data size for the USART. + * 0b00..7 bit data length + * 0b01..8 bit data length + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET[CTL]. + * 0b11..Reserved + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Parity Select. Selects what type of parity is used by the USART. + * 0b00..No parity + * 0b01..Reserved + * 0b10..Even parity + * 0b11..Odd parity + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Stop Length + * 0b0..1 stop bit + * 0b1..2 stop bits. This setting should be used only for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Mode 32 kHz + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN Break Mode Enable + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Synchronous Enable. Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode + * 0b1..Synchronous mode + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Clock Polarity + * 0b0..Falling edge. RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master Select + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Loopback Mode + * 0b0..Normal operation + * 0b1..Loopback mode + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround Time Enable for RS-485 Operation. + * 0b0..Disabled + * 0b1..Enabled + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address Matching Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal is configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive Data Polarity + * 0b0..Standard + * 0b1..Inverted + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity + * 0b0..Standard + * 0b1..Inverted + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control */ +/*! @{ */ + +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable + * 0b0..Normal operation + * 0b1..Continuous break + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable Address Detect Mode + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock Generation + * 0b0..Clock on character + * 0b1..Continuous clock + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status */ +/*! @{ */ + +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle + * 0b0..The receiver is currently receiving data. + * 0b1..The receiver is not currently receiving data. + */ +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle + * 0b0..The transmitter is currently sending data. + * 0b1..The transmitter is not currently sending data. + */ +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +/*! CTS - CTS value + */ +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - Delta CTS + */ +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status Flag + * 0b0..Not Idle. Indicates that the USART transmitter is NOT fully idle after being disabled. + * 0b1..Idle. Indicates that the USART transmitter is fully idle after being disabled (CTL[TXDIS] = 1). + */ +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break + */ +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - Delta Received Break + */ +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +/*! START - Start + */ +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error Interrupt Flag + */ +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error Interrupt Flag + */ +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise Interrupt Flag + */ +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto Baud Error + */ +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Read and Set for USART (not FIFO) Status */ +/*! @{ */ + +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - Transmit Idle Flag + * 0b1..Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1). + */ +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - Delta CTS Input Flag + * 0b1..Enables an interrupt when there is a change in the state of the CTS input. + */ +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - Transmit Disabled Flag + * 0b1..Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[TXDISINT] flag. See + * the description of the STAT[TXDISINT] flag. + */ +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - Delta Receive Break Enable + * 0b1..Enable + */ +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - Start Enable + * 0b1..Enables an interrupt when a received start bit has been detected. + */ +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - Frame Error Enable + * 0b1..Enables an interrupt when a framing error has been detected. + */ +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - Parity Error Enble + * 0b1..Enables an interrupt when a parity error has been detected. + */ +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - Receive Noise Enable + * 0b1..Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEINT] bit. + */ +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - Auto Baud Error Enable + * 0b1..Enables an interrupt when an auto baud error occurs. + */ +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear */ +/*! @{ */ + +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Transmit Idle Clear + */ +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Delta CTS Clear + */ +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Transmit Disable Clear + */ +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Delta Receive Break Clear + */ +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Start Clear + */ +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Frame Error Clear + */ +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Parity Error Clear + */ +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Receive Noise Clear + */ +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Auto Baud Error Clear + */ +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator */ +/*! @{ */ + +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - Baud Rate Generator Value + * 0b0000000000000000..FCLK is used directly by the USART function. + * 0b0000000000000001..FCLK is divided by 2 before use by the USART function. + * 0b0000000000000010..FCLK is divided by 3 before use by the USART function. + * 0b1111111111111111..FCLK is divided by 65,536 before use by the USART function. + */ +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status */ +/*! @{ */ + +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle Flag + */ +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - Delta CTS Change Flag + */ +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt Flag + */ +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - Delta Receiver Break Change Flag + */ +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +/*! START - Start Detected on Receiver Flag + */ +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error Interrupt Flag + */ +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error Interrupt Flag + */ +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise Interrupt Flag + */ +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto Baud Error Interrupt Flag + */ +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample Selection Register for Asynchronous Communication */ +/*! @{ */ + +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value + * 0b0000..Not supported + * 0b0001..Not supported + * 0b0010..Not supported + * 0b0011..Not supported + * 0b0100..5 function clocks are used to transmit and receive each data bit. + * 0b0101..6 function clocks are used to transmit and receive each data bit. + * 0b1111..16 function clocks are used to transmit and receive each data bit. + */ +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address Register for Automatic Address Matching */ +/*! @{ */ + +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - Address + */ +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO Configuration */ +/*! @{ */ + +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the Transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the Receive FIFO + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO Size Configuration + * 0b00..FIFO is configured as 16 entries of 8 bits. + * 0b01..Not used + * 0b10..Not used + * 0b11..Not used + */ +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA Configuration for Transmit + * 0b0..DMA is not used for the transmit function. + * 0b1..Triggers DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA Configuration for Receive + * 0b0..DMA is not used for the receive function. + * 0b1..Triggers DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for Transmit FIFO Level + * 0b0..Only enabled interrupts will wake up the device from low power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by + * FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for Receive FIFO Level + * 0b0..Only enabled interrupts will wake up the device from low power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by + * FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty Command for the Transmit FIFO + * 0b0..No effect + * 0b1..The TX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty Command for the Receive FIFO + * 0b0..No effect + * 0b1..The RX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) + +#define USART_FIFOCFG_POPDBG_MASK (0x40000U) +#define USART_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for Debug Reads + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO Status */ +/*! @{ */ + +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO Error + * 0b0..A transmit FIFO error has not occurred. + * 0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full + * FIFO, or by an underflow if the FIFO is empty when data is needed. + */ +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO Error + * 0b0..A receive FIFO overflow has not occurred + * 0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough + */ +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral Interrupt + * 0b0..No Peripheral Interrupt + * 0b1..Peripheral Interrupt + */ +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO Empty + * 0b0..The transmit FIFO is not empty. + * 0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data. + */ +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO is Not Full + * 0b0..The transmit FIFO is full and another write would cause it to overflow. + * 0b1..The transmit FIFO is not full, so more data can be written. + */ +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO is Not Empty + * 0b0..The receive FIFO is empty. + * 0b1..The receive FIFO is not empty, so data can be read. + */ +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO is Full + * 0b0..The receive FIFO is not full. + * 0b1..The receive FIFO is full. + */ +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO Current Level + */ +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO Current Level + */ +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) + +#define USART_FIFOSTAT_RXTIMEOUT_MASK (0x1000000U) +#define USART_FIFOSTAT_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive FIFO Timeout + * 0b0..RX FIFO on + * 0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register. + */ +#define USART_FIFOSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOSTAT_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO Trigger Settings for Interrupt and DMA Request */ +/*! @{ */ + +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO Level Trigger Enable. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..A trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO Level Trigger Enable + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO Level Trigger Point + * 0b0000..Trigger when the TX FIFO becomes empty + * 0b0001..Trigger when the TX FIFO level decreases to 1 entry + * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full) + */ +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO Level Trigger Point + * 0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty) + * 0b0001..Trigger when the RX FIFO has received 2 entries + * 0b1111..Trigger when the RX FIFO has received 16 entries (has become full) + */ +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO Interrupt Enable */ +/*! @{ */ + +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Transmit Error Interrupt Enable + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Receive Error Interrupt Enable + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Enable + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL] + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Enable + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO level increases to + * the level specified by FIFOTRIG[RXLVL]. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) + +#define USART_FIFOINTENSET_RXTIMEOUT_MASK (0x1000000U) +#define USART_FIFOINTENSET_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout + * 0b0..No RX interrupt will be generated. + * 0b1..Asserts RX interrupt if RX FIFO Timeout event occurs. + */ +#define USART_FIFOINTENSET_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXTIMEOUT_SHIFT)) & USART_FIFOINTENSET_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear */ +/*! @{ */ + +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Transmit Error Interrupt Enable + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Receive Error Interrupt Enable + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Enable + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Enable + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) + +#define USART_FIFOINTENCLR_RXTIMEOUT_MASK (0x1000000U) +#define USART_FIFOINTENCLR_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout + * 0b0..No effect + * 0b1..Clear the interrupt + */ +#define USART_FIFOINTENCLR_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & USART_FIFOINTENCLR_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO Interrupt Status */ +/*! @{ */ + +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO Error Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO Error Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO Level Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO Level Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral Interrupt Status + * 0b0..Not pending + * 0b1..Pending + */ +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) + +#define USART_FIFOINTSTAT_RXTIMEOUT_MASK (0x1000000U) +#define USART_FIFOINTSTAT_RXTIMEOUT_SHIFT (24U) +/*! RXTIMEOUT - Receive Timeout Status + * 0b0..Not pending + * 0b1..Pending + */ +#define USART_FIFOINTSTAT_RXTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOINTSTAT_RXTIMEOUT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO Write Data */ +/*! @{ */ + +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO + */ +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO Read Data */ +/*! @{ */ + +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error Status Flag + */ +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error Status Flag + */ +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise Flag + */ +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */ +/*! @{ */ + +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received Data from the FIFO + */ +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error Status Flag + */ +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error Status Flag + */ +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise Flag + */ +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO Size */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - FIFO Size + */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */ +/*! @{ */ + +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU) +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U) +/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler + */ +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK) + +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U) +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U) +/*! RXTIMEOUT_VALUE - Receive Timeout Value + */ +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK) + +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U) +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U) +/*! RXTIMEOUT_EN - Receive Timeout Enable + * 0b0..Disable RX FIFO timeout + * 0b1..Enable RX FIFO timeout + */ +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK) + +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U) +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U) +/*! RXTIMEOUT_COW - Receive Timeout Continue On Write + * 0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO. + * 0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO. + */ +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK) + +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U) +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U) +/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty + * 0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty. + * 0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty. + */ +#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK) +/*! @} */ + +/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */ +/*! @{ */ + +#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU) +#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U) +/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value + */ +#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK) +/*! @} */ + +/*! @name ID - Peripheral Identification */ +/*! @{ */ + +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture + */ +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation + */ +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation + */ +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function + */ +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status */ +/*! @{ */ + +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address + */ +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable + */ +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received + */ +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Support + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect + */ +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend + */ +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend + */ +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host + */ +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change + */ +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change + */ +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change + */ +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info */ +/*! @{ */ + +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number + */ +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. + */ +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. + */ +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. + */ +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. + */ +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management */ +/*! @{ */ + +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - hardware + */ +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - software + */ +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - Data pending + */ +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USB_EPSKIP_SKIP_MASK (0xFFFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip + */ +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USB_EPINUSE_BUF_MASK (0xFFCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use + * 0b0000000000..Hardware is accessing buffer 0 + * 0b0000000001..Hardware is accessing buffer 1 + */ +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration */ +/*! @{ */ + +#define USB_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage + * 0b0000000000..Single-buffer + * 0b0000000001..Double-buffer + */ +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status */ +/*! @{ */ + +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Control EP0 OUT direction + */ +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Control EP0 IN direction + */ +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - EP1 OUT direction + */ +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - EP1 IN direction + */ +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - EP2 OUT direction + */ +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - EP2 IN direction + */ +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - EP3 OUT direction + */ +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - EP3 IN direction + */ +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - EP4 OUT direction + */ +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - EP4 IN direction + */ +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt + */ +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt + */ +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable */ +/*! @{ */ + +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - End point interrupt enable + */ +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - Frame interrupt enable + */ +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - Device interrupt enable + */ +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status */ +/*! @{ */ + +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - End point set interrupt + */ +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - Frame set interrupt + */ +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - Device set interrupt + */ +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle */ +/*! @{ */ + +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle + */ +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< Host controller revision, offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Host controller control, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< Host controller command status, offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Host controller interrupt status, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Host Controller interrupt enable, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt., offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Host controller communication area, offset: 0x18 */ + __I uint32_t HCPERIODCURRENTED; /**< Host controller period current endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Host controller control head endpoint descriptor, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Host controller control current endpoint descriptor, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Host controller bulk head endpoint descriptor, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Host controller bulk current endpoint descriptor, offset: 0x2C */ + __I uint32_t HCDONEHEAD; /**< Host controller done head, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Host controller frame interval, offset: 0x34 */ + __I uint32_t HCFMREMAINING; /**< Host controller frame remaining, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Host controller frame number, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Host controller periodic start, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Host controller low speed threshold, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< Host controller root hub descriptor A, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Host controller root hub descriptor B, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< , offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Host controller root hub port status, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Port Mode, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - Host controller revision */ +/*! @{ */ + +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision + */ +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Host controller control */ +/*! @{ */ + +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. + */ +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. + */ +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. + */ +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. + */ +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + */ +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState + * 0b00..USBRESET + * 0b01..USBRESUME + * 0b10..USBOPERATIONAL + * 0b11..USBSUSPEND + */ +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting + */ +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + */ +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - Host controller command status */ +/*! @{ */ + +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset + */ +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + */ +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + */ +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + */ +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + */ +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Host controller interrupt status */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun + */ +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead + */ +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame + */ +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected + */ +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError + */ +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow + */ +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange + */ +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Host Controller interrupt enable */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + * 0b0..No effect + * 0b1..Enables interrupt + */ +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. + */ +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt. */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. + * 0b0..No effect + * 0b1..Disables interrupt + */ +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Host controller communication area */ +/*! @{ */ + +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Host Controller Communication Area + */ +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Host controller period current endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. + */ +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Host controller control head endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. + */ +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Host controller control current endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED + */ +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Host controller bulk head endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + */ +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Host controller bulk current endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED + */ +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Host controller done head */ +/*! @{ */ + +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + */ +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Host controller frame interval */ +/*! @{ */ + +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. + */ +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle + */ +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - Host controller frame remaining */ +/*! @{ */ + +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining + */ +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle + */ +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Host controller frame number */ +/*! @{ */ + +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber + */ +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Host controller periodic start */ +/*! @{ */ + +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart + */ +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Host controller low speed threshold */ +/*! @{ */ + +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold + */ +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - Host controller root hub descriptor A */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts + */ +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode + * 0b0..All ports are powered at the same time + * 0b1..Each port is powered individually. + */ +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching + * 0b0..Ports are power switched + * 0b1..Ports are always powered on when the host controller is powered on + */ +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType + */ +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + * 0b0..Over-current status is reported collectively for all downstream ports + * 0b1..Over-current status is reported on a per-port basis + */ +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + * 0b0..Over-current status is reported collectively for all downstream ports + * 0b1..No overcurrent protection supported + */ +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime + */ +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Host controller root hub descriptor B */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable + */ +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask + */ +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - */ +/*! @{ */ + +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus (write) ClearGlobalPower + */ +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator + */ +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable (Write) SetRemoteWakeupEnable + * 0b0..ConnectStatusChange is not a remote wakeup event + * 0b1..ConnectStatusChange is a remote wakeup event + */ +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange(Write) SetGlobalPower . + */ +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange + */ +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable . + */ +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Host controller root hub port status */ +/*! @{ */ + +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - CurrentConnectStatus + * 0b0..Device is not connected + * 0b1..Device is connected + */ +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (Read)PortEnableStatus + * 0b0..Port is disabled + * 0b1..Port is enabled + */ +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (Read) PortSuspendStatus + * 0b0..Port is not suspended + * 0b1..Port is suspended + */ +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator + * 0b0..Overcurrent condition is not detected + * 0b1..Overcurrent condition is detected + */ +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + * 0b0..Port reset signal is not active + * 0b1..Port reset signal is active + */ +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus + * 0b0..Port power is off + * 0b1..Port power is on + */ +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached + * 0b0..Full speed device is attached + * 0b1..Low speed device is attached + */ +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange + * 0b0..CurrentConnectStatus has not changed + * 0b1..CurrentConnectStatus has changed + */ +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange + * 0b0..PortEnableStatus has not changed + * 0b1..PortEnableStatus has changed + */ +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange + * 0b0..Resume sequence is not complete + * 0b1..Resume sequence is complete + */ +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange + * 0b0..PortOverCurrentIndicator has not changed + * 0b1..PortOverCurrentIndicator has changed + */ +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange + * 0b0..Port reset is not complete + * 0b1..Port reset is complete + */ +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Port Mode */ +/*! @{ */ + +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. + */ +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. + */ +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - Device Enable + * 0b0..Device + * 0b1..Host + */ +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag + * 0b0..No interrupt is pending + * 0b1..An interrupt is pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer active flag + * 0b0..The Micro-Tick Timer is not active (stopped) + * 0b1..The Micro-Tick Timer is currently active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disabled + * 0b1..Enabled + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disabled + * 0b1..Enabled + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disabled + * 0b1..Enabled + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disabled + * 0b1..Enabled + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive edge capture + * 0b1..Negative edge capture + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1 + * 0b0..Positive edge capture + * 0b1..Negative edge capture + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive edge capture + * 0b1..Negative edge capture + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive edge capture + * 0b1..Negative edge capture + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0 + * 0b0..Does nothing + * 0b1..Write 1 to clear the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1 + * 0b0..Does nothing + * 0b1..Write 1 to clear the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2 + * 0b0..Does nothing + * 0b1..Write 1 to clear the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3 + * 0b0..Does nothing + * 0b1..Write 1 to clear the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured value for the related capture event + */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured value is valid + * 0b0..A valid value has been not been captured + * 0b1..A valid value has been captured, based on a transition of the related UTICK_CAPn pin + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< VREF Version ID, offset: 0x0 */ + uint32_t PARAM; /**< VREF Parameter, offset: 0x4 */ + __IO uint32_t CSR; /**< VREF Control and Status Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t UTRIM; /**< VREF User Trim, offset: 0x10 */ + uint8_t RESERVED_1[8]; + __IO uint32_t TEST_UNLOCK; /**< Unlock test registers, offset: 0x1C */ + uint8_t RESERVED_2[4]; + __IO uint32_t TRIM0; /**< VREF Test Trim 0, offset: 0x24 */ + __IO uint32_t TRIM1; /**< VREF Test Trim 1, offset: 0x28 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name VERID - VREF Version ID */ +/*! @{ */ + +#define VREF_VERID_FEATURE_MASK (0xFFFFU) +#define VREF_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - FEATURE + */ +#define VREF_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK) + +#define VREF_VERID_MINOR_MASK (0xFF0000U) +#define VREF_VERID_MINOR_SHIFT (16U) +/*! MINOR - MINOR + */ +#define VREF_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK) + +#define VREF_VERID_MAJOR_MASK (0xFF000000U) +#define VREF_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - MAJOR + */ +#define VREF_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CSR - VREF Control and Status Register */ +/*! @{ */ + +#define VREF_CSR_HCBGEN_MASK (0x1U) +#define VREF_CSR_HCBGEN_SHIFT (0U) +/*! HCBGEN - HC Bandgap enabled + * 0b0..HC Bandgap is disabled + * 0b1..HC Bandgap is enabled + */ +#define VREF_CSR_HCBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK) + +#define VREF_CSR_LPBGEN_MASK (0x2U) +#define VREF_CSR_LPBGEN_SHIFT (1U) +/*! LPBGEN - Low Power Bandgap enable + * 0b0..LP Bandgap is disabled + * 0b1..LP Bandgap is enabled + */ +#define VREF_CSR_LPBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK) + +#define VREF_CSR_LPBG_BUF_EN_MASK (0x4U) +#define VREF_CSR_LPBG_BUF_EN_SHIFT (2U) +/*! LPBG_BUF_EN + * 0b0..disable + * 0b1..enable + */ +#define VREF_CSR_LPBG_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK) + +#define VREF_CSR_CHOPEN_MASK (0x8U) +#define VREF_CSR_CHOPEN_SHIFT (3U) +/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the + * internal analog offset will be minimized. + * 0b0..Chop oscillator is disabled. + * 0b1..Chop oscillator is enabled. + */ +#define VREF_CSR_CHOPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK) + +#define VREF_CSR_ICOMPEN_MASK (0x10U) +#define VREF_CSR_ICOMPEN_SHIFT (4U) +/*! ICOMPEN - Second order curvature compensation enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define VREF_CSR_ICOMPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK) + +#define VREF_CSR_REGEN_MASK (0x20U) +#define VREF_CSR_REGEN_SHIFT (5U) +/*! REGEN - Regulator enable + * 0b0..Internal 1.75 V regulator is disabled. + * 0b1..Internal 1.75 V regulator is enabled. + */ +#define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) + +#define VREF_CSR_REFCHSELN_EN_MASK (0x40U) +#define VREF_CSR_REFCHSELN_EN_SHIFT (6U) +/*! REFCHSELN_EN + * 0b0..disable + * 0b1..enable + */ +#define VREF_CSR_REFCHSELN_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELN_EN_SHIFT)) & VREF_CSR_REFCHSELN_EN_MASK) + +#define VREF_CSR_REFCHSELP_EN_MASK (0x80U) +#define VREF_CSR_REFCHSELP_EN_SHIFT (7U) +/*! REFCHSELP_EN + * 0b0..disable + * 0b1..enable + */ +#define VREF_CSR_REFCHSELP_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELP_EN_SHIFT)) & VREF_CSR_REFCHSELP_EN_MASK) + +#define VREF_CSR_VRSEL_MASK (0x300U) +#define VREF_CSR_VRSEL_SHIFT (8U) +/*! VRSEL + * 0b00..Internal bandgap + * 0b01..Low power buffered 1v + * 0b10..Buffer 2.1v output + */ +#define VREF_CSR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VRSEL_SHIFT)) & VREF_CSR_VRSEL_MASK) + +#define VREF_CSR_REFL_GRD_SEL_MASK (0x400U) +#define VREF_CSR_REFL_GRD_SEL_SHIFT (10U) +/*! REFL_GRD_SEL + * 0b0..vrefl_3v + * 0b1..vssa + */ +#define VREF_CSR_REFL_GRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFL_GRD_SEL_SHIFT)) & VREF_CSR_REFL_GRD_SEL_MASK) + +#define VREF_CSR_HI_PWR_LV_MASK (0x800U) +#define VREF_CSR_HI_PWR_LV_SHIFT (11U) +#define VREF_CSR_HI_PWR_LV(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK) + +#define VREF_CSR_BUF21EN_MASK (0x10000U) +#define VREF_CSR_BUF21EN_SHIFT (16U) +/*! Buf21EN - Internal buf21 Enable + * 0b0..buf21 is disabled + * 0b1..buf21 is enabled + */ +#define VREF_CSR_BUF21EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK) + +#define VREF_CSR_VREFST_MASK (0x80000000U) +#define VREF_CSR_VREFST_SHIFT (31U) +/*! VREFST - Internal HC Voltage Reference stable + * 0b0..The module is disabled or not stable. + * 0b1..The module is stable. + */ +#define VREF_CSR_VREFST(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK) +/*! @} */ + +/*! @name UTRIM - VREF User Trim */ +/*! @{ */ + +#define VREF_UTRIM_TRIM2V1_MASK (0xFU) +#define VREF_UTRIM_TRIM2V1_SHIFT (0U) +/*! TRIM2V1 - VREF 2.1V Trim Bits + */ +#define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) + +#define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) +#define VREF_UTRIM_VREFTRIM_SHIFT (8U) +/*! VREFTRIM - VREF Trim bits + */ +#define VREF_UTRIM_VREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK) +/*! @} */ + +/*! @name TEST_UNLOCK - Unlock test registers */ +/*! @{ */ + +#define VREF_TEST_UNLOCK_TEST_UNLOCK_MASK (0x1U) +#define VREF_TEST_UNLOCK_TEST_UNLOCK_SHIFT (0U) +/*! test_unlock - Test_unlock status bit + * 0b0..Lock read/write into test register + * 0b1..Unlock read/write into test register + */ +#define VREF_TEST_UNLOCK_TEST_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << VREF_TEST_UNLOCK_TEST_UNLOCK_SHIFT)) & VREF_TEST_UNLOCK_TEST_UNLOCK_MASK) + +#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_MASK (0xFFFEU) +#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_SHIFT (1U) +/*! test_unlock_value - Test unlock value + */ +#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_SHIFT)) & VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_MASK) +/*! @} */ + +/*! @name TRIM0 - VREF Test Trim 0 */ +/*! @{ */ + +#define VREF_TRIM0_COMPLSB_MASK (0x7U) +#define VREF_TRIM0_COMPLSB_SHIFT (0U) +/*! COMPLSB - COMPLSB + */ +#define VREF_TRIM0_COMPLSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_COMPLSB_SHIFT)) & VREF_TRIM0_COMPLSB_MASK) + +#define VREF_TRIM0_COMPMSB_MASK (0xE0U) +#define VREF_TRIM0_COMPMSB_SHIFT (5U) +/*! COMPMSB - COMPMSB + */ +#define VREF_TRIM0_COMPMSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_COMPMSB_SHIFT)) & VREF_TRIM0_COMPMSB_MASK) + +#define VREF_TRIM0_BPLSB_MASK (0xF00U) +#define VREF_TRIM0_BPLSB_SHIFT (8U) +/*! BPLSB - BPLSB + */ +#define VREF_TRIM0_BPLSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_BPLSB_SHIFT)) & VREF_TRIM0_BPLSB_MASK) + +#define VREF_TRIM0_BPMSB_MASK (0xE000U) +#define VREF_TRIM0_BPMSB_SHIFT (13U) +/*! BPMSB - BPMSB + */ +#define VREF_TRIM0_BPMSB(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_BPMSB_SHIFT)) & VREF_TRIM0_BPMSB_MASK) + +#define VREF_TRIM0_CHOPOSCTRIM_MASK (0xF0000U) +#define VREF_TRIM0_CHOPOSCTRIM_SHIFT (16U) +/*! CHOPOSCTRIM - CHOPOSCTRIM + */ +#define VREF_TRIM0_CHOPOSCTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_CHOPOSCTRIM_SHIFT)) & VREF_TRIM0_CHOPOSCTRIM_MASK) + +#define VREF_TRIM0_P7_TRIM_MASK (0xF000000U) +#define VREF_TRIM0_P7_TRIM_SHIFT (24U) +/*! P7_TRIM - P7_TRIM + * 0b0000..VREF 2.1V is enabled + * 0b0001..VREF 2.1V is disabled + */ +#define VREF_TRIM0_P7_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_P7_TRIM_SHIFT)) & VREF_TRIM0_P7_TRIM_MASK) + +#define VREF_TRIM0_FLIP_MASK (0x80000000U) +#define VREF_TRIM0_FLIP_SHIFT (31U) +/*! FLIP - Amplifier Polarity + */ +#define VREF_TRIM0_FLIP(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_FLIP_SHIFT)) & VREF_TRIM0_FLIP_MASK) +/*! @} */ + +/*! @name TRIM1 - VREF Test Trim 1 */ +/*! @{ */ + +#define VREF_TRIM1_LP_VTRIM_MASK (0x1FU) +#define VREF_TRIM1_LP_VTRIM_SHIFT (0U) +/*! LP_VTRIM - LP Bandgap Voltage Trim + */ +#define VREF_TRIM1_LP_VTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_LP_VTRIM_SHIFT)) & VREF_TRIM1_LP_VTRIM_MASK) + +#define VREF_TRIM1_LP_TCTRIM_MASK (0x700U) +#define VREF_TRIM1_LP_TCTRIM_SHIFT (8U) +/*! LP_TCTRIM - LP_TCTRIM + */ +#define VREF_TRIM1_LP_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_LP_TCTRIM_SHIFT)) & VREF_TRIM1_LP_TCTRIM_MASK) + +#define VREF_TRIM1_IREF_TRIM_MASK (0x70000U) +#define VREF_TRIM1_IREF_TRIM_SHIFT (16U) +/*! IREF_TRIM - IREF_TRIM + */ +#define VREF_TRIM1_IREF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_IREF_TRIM_SHIFT)) & VREF_TRIM1_IREF_TRIM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF base address */ + #define VREF_BASE (0x500B5000u) + /** Peripheral VREF base address */ + #define VREF_BASE_NS (0x400B5000u) + /** Peripheral VREF base pointer */ + #define VREF ((VREF_Type *)VREF_BASE) + /** Peripheral VREF base pointer */ + #define VREF_NS ((VREF_Type *)VREF_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF_NS } +#else + /** Peripheral VREF base address */ + #define VREF_BASE (0x400B5000u) + /** Peripheral VREF base pointer */ + #define VREF ((VREF_Type *)VREF_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF } +#endif + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Stop. The Watchdog timer is stopped. + * 0b1..Run. The Watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt. A Watchdog timeout will not cause a chip reset. + * 0b1..Reset. A Watchdog timeout will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Clear. + * 0b1..Reset. Causes a chip reset if WDRESET = 1. + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag. + * 0b1..Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer greater than the value specified by WARNINT. + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value + */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value + */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value + */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value + */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value. + */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** AHB Secure Control */ +#if defined(SECTRL0) + #define AHB_SECURE_CTRL SECTRL0 +#endif + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S36_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36_features.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36_features.h new file mode 100644 index 0000000000000000000000000000000000000000..3107d843947a7c4d19a6cd9334916046c4823c02 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/LPC55S36_features.h @@ -0,0 +1,624 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2021-08-04 +** Build: b220118 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-04-12) +** Initial version based on RM DraftF +** - rev. 1.1 (2021-08-04) +** Initial version based on RM DraftG +** +** ################################################################### +*/ + +#ifndef _LPC55S36_FEATURES_H_ +#define _LPC55S36_FEATURES_H_ + +/* SOC module features */ + +#if defined(CPU_LPC55S36JBD100) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (2) + /* @brief CACHE64_CTRL availability on the SoC. */ + #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) + /* @brief CACHE64_POLSEL availability on the SoC. */ + #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) + /* @brief LPC_CAN availability on the SoC. */ + #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief CTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_CTIMER_COUNT (5) + /* @brief CDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_CDOG_COUNT (1) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (2) + /* @brief DMIC availability on the SoC. */ + #define FSL_FEATURE_SOC_DMIC_COUNT (1) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (2) + /* @brief FLASH availability on the SoC. */ + #define FSL_FEATURE_SOC_FLASH_COUNT (1) + /* @brief FLEXCOMM availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) + /* @brief FLEXSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) + /* @brief FREQME availability on the SoC. */ + #define FSL_FEATURE_SOC_FREQME_COUNT (1) + /* @brief GINT availability on the SoC. */ + #define FSL_FEATURE_SOC_GINT_COUNT (2) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (1) + /* @brief SECGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (8) + /* @brief I3C availability on the SoC. */ + #define FSL_FEATURE_SOC_I3C_COUNT (1) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (8) + /* @brief INPUTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) + /* @brief IOCON availability on the SoC. */ + #define FSL_FEATURE_SOC_IOCON_COUNT (1) + /* @brief LPADC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPADC_COUNT (2) + /* @brief LPCMP availability on the SoC. */ + #define FSL_FEATURE_SOC_LPCMP_COUNT (3) + /* @brief LPDAC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPDAC_COUNT (3) + /* @brief MAILBOX availability on the SoC. */ + #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) + /* @brief MRT availability on the SoC. */ + #define FSL_FEATURE_SOC_MRT_COUNT (1) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (3) + /* @brief OSTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) + /* @brief PINT availability on the SoC. */ + #define FSL_FEATURE_SOC_PINT_COUNT (1) + /* @brief SECPINT availability on the SoC. */ + #define FSL_FEATURE_SOC_SECPINT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief POWERQUAD availability on the SoC. */ + #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (2) + /* @brief PUF availability on the SoC. */ + #define FSL_FEATURE_SOC_PUF_COUNT (1) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (2) + /* @brief SCT availability on the SoC. */ + #define FSL_FEATURE_SOC_SCT_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (9) + /* @brief SYSCON availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSCON_COUNT (1) + /* @brief USART availability on the SoC. */ + #define FSL_FEATURE_SOC_USART_COUNT (8) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBFSH availability on the SoC. */ + #define FSL_FEATURE_SOC_USBFSH_COUNT (1) + /* @brief UTICK availability on the SoC. */ + #define FSL_FEATURE_SOC_UTICK_COUNT (1) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WWDT availability on the SoC. */ + #define FSL_FEATURE_SOC_WWDT_COUNT (1) +#elif defined(CPU_LPC55S36JHI48) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (2) + /* @brief CACHE64_CTRL availability on the SoC. */ + #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) + /* @brief CACHE64_POLSEL availability on the SoC. */ + #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) + /* @brief LPC_CAN availability on the SoC. */ + #define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief CTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_CTIMER_COUNT (5) + /* @brief CDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_CDOG_COUNT (1) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (2) + /* @brief DMIC availability on the SoC. */ + #define FSL_FEATURE_SOC_DMIC_COUNT (1) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (2) + /* @brief FLASH availability on the SoC. */ + #define FSL_FEATURE_SOC_FLASH_COUNT (1) + /* @brief FLEXCOMM availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) + /* @brief FLEXSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) + /* @brief FREQME availability on the SoC. */ + #define FSL_FEATURE_SOC_FREQME_COUNT (1) + /* @brief GINT availability on the SoC. */ + #define FSL_FEATURE_SOC_GINT_COUNT (2) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (1) + /* @brief SECGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (8) + /* @brief I3C availability on the SoC. */ + #define FSL_FEATURE_SOC_I3C_COUNT (1) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (8) + /* @brief INPUTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) + /* @brief IOCON availability on the SoC. */ + #define FSL_FEATURE_SOC_IOCON_COUNT (1) + /* @brief LPADC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPADC_COUNT (2) + /* @brief LPCMP availability on the SoC. */ + #define FSL_FEATURE_SOC_LPCMP_COUNT (3) + /* @brief LPDAC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPDAC_COUNT (3) + /* @brief MAILBOX availability on the SoC. */ + #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) + /* @brief MRT availability on the SoC. */ + #define FSL_FEATURE_SOC_MRT_COUNT (1) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (3) + /* @brief OSTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) + /* @brief PINT availability on the SoC. */ + #define FSL_FEATURE_SOC_PINT_COUNT (1) + /* @brief SECPINT availability on the SoC. */ + #define FSL_FEATURE_SOC_SECPINT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief POWERQUAD availability on the SoC. */ + #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (2) + /* @brief PUF availability on the SoC. */ + #define FSL_FEATURE_SOC_PUF_COUNT (1) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (2) + /* @brief SCT availability on the SoC. */ + #define FSL_FEATURE_SOC_SCT_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (9) + /* @brief SYSCON availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSCON_COUNT (1) + /* @brief USART availability on the SoC. */ + #define FSL_FEATURE_SOC_USART_COUNT (8) + /* @brief UTICK availability on the SoC. */ + #define FSL_FEATURE_SOC_UTICK_COUNT (1) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WWDT availability on the SoC. */ + #define FSL_FEATURE_SOC_WWDT_COUNT (1) +#endif + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has trigger status (register TSTAT). */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (768.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (292.7f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.7f) +/* @brief Temperature sensor need calibration. */ +#define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) +/* @brief the address of temperature sensor parameter A (slope) in Flash. */ +#define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) +/* @brief the address of temperature sensor parameter B (offset) in Flash. */ +#define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* ANACTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) +/* @brief Has FREQ_ME_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL (1) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (0) +/* @brief ANACTRL control VDDMAIN. */ +#define FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN (1) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* CAN module features */ + +/* @brief Support CANFD or not */ +#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + +/* CTIMER module features */ + +/* No feature definitions */ + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) \ + (((x) == DMA0) ? (52) : \ + (((x) == DMA1) ? (16) : (-1))) +/* @brief Max channels */ +#define FSL_FEATURE_DMA_MAX_CHANNELS (52) +/* @brief All channels */ +#define FSL_FEATURE_DMA_ALL_CHANNELS (68U) +/* @brief Align size of DMA0 descriptor */ +#define FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE (1024) +/* @brief Align size of DMA1 descriptor */ +#define FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE (256) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(x) \ + (((x) == DMA0) ? (1024) : \ + (((x) == DMA1) ? (256) : (-1))) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* DMIC module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMIC_CHANNEL_NUM (2) +/* @brief DMIC channel FIFO register support sign extended */ +#define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1) +/* @brief DMIC has no IOCFG register */ +#define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1) +/* @brief DMIC has decimator reset function */ +#define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1) +/* @brief DMIC has global channel synchronization function */ +#define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ + (((x) == FLEXCOMM0) ? (0) : \ + (((x) == FLEXCOMM1) ? (0) : \ + (((x) == FLEXCOMM2) ? (0) : \ + (((x) == FLEXCOMM3) ? (0) : \ + (((x) == FLEXCOMM4) ? (0) : \ + (((x) == FLEXCOMM5) ? (0) : \ + (((x) == FLEXCOMM6) ? (0) : \ + (((x) == FLEXCOMM7) ? (1) : \ + (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) +/* @brief I2S support dual channel transfer */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ + (((x) == FLEXCOMM0) ? (0) : \ + (((x) == FLEXCOMM1) ? (0) : \ + (((x) == FLEXCOMM2) ? (0) : \ + (((x) == FLEXCOMM3) ? (0) : \ + (((x) == FLEXCOMM4) ? (0) : \ + (((x) == FLEXCOMM5) ? (0) : \ + (((x) == FLEXCOMM6) ? (1) : \ + (((x) == FLEXCOMM7) ? (1) : \ + (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no IPCR1 IPAREN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) +/* @brief FlexSPI has no AHBCR APAREN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (1) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) +/* @brief I2S has DMIC interconnection. */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN reigster. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) + +/* INPUTMUX module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (1) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has Reset in system level. */ +#define FSL_FEATURE_RTC_HAS_RESET (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (1) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 reigster. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904) + +/* SYSCTL module features */ + +/* @brief SYSCTRL has Code Gray feature. */ +#define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) + +/* USB module features */ + +#if defined(CPU_LPC55S36JBD100) + /* @brief USB version */ + #define FSL_FEATURE_USB_VERSION (200) + /* @brief Number of the endpoint in USB FS */ + #define FSL_FEATURE_USB_EP_NUM (5) +#endif /* defined(CPU_LPC55S36JBD100) */ + +/* USBFSH module features */ + +#if defined(CPU_LPC55S36JBD100) + /* @brief USBFSH version */ + #define FSL_FEATURE_USBFSH_VERSION (200) +#endif /* defined(CPU_LPC55S36JBD100) */ + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (0) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (0) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (0) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* WWDT module features */ + +/* No feature definitions */ + +#endif /* _LPC55S36_FEATURES_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_256.FLM b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_256.FLM new file mode 100644 index 0000000000000000000000000000000000000000..a2d5023499b34b17399d5a4e2787cdc42e96fe72 Binary files /dev/null and b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_256.FLM differ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI.FLM b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI.FLM new file mode 100644 index 0000000000000000000000000000000000000000..5e1761e5449bed83dd892ddad0d272d3671f547c Binary files /dev/null and b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI.FLM differ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI_S.FLM b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI_S.FLM new file mode 100644 index 0000000000000000000000000000000000000000..a98a90d28e8d19e64e2d007f963ee8847a9912a5 Binary files /dev/null and b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_FLEXSPI_S.FLM differ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_S_256.FLM b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_S_256.FLM new file mode 100644 index 0000000000000000000000000000000000000000..a1c8df323a3be92ea3e597cdebc8ac02484020f2 Binary files /dev/null and b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC553XX_S_256.FLM differ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_flash.scf b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_flash.scf new file mode 100644 index 0000000000000000000000000000000000000000..7e54ddd6c459431516f0e3fe726f1cee97a785fb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_flash.scf @@ -0,0 +1,88 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#if (defined(__pkc__)) + #define retention_RAMsize 0x00004000 /* SRAM A(16K) reserved for pkc */ +#elif (defined(__power_down__)) + #define retention_RAMsize 0x00000604 /* The first 0x604 bytes reserved to CPU retention for power down mode */ +#else + #define retention_RAMsize 0x00000000 +#endif + +#if (defined(__powerquad__)) + #define powerquad_RAMsize 0x00004000 /* SRAM E(16K) reserved for powerquad */ +#else + #define powerquad_RAMsize 0x00000000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0003D400 + +#define m_data_start 0x20000000 + retention_RAMsize +#define m_data_size 0x0001C000 - retention_RAMsize - powerquad_RAMsize + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00004000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_ram.scf b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_ram.scf new file mode 100644 index 0000000000000000000000000000000000000000..5ef0aa1795c00303e5e750849ec59cb16452560f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55S36_ram.scf @@ -0,0 +1,84 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#if (defined(__pkc__)) + #define retention_RAMsize 0x00004000 /* SRAM A(16K) reserved for pkc */ +#elif (defined(__power_down__)) + #define retention_RAMsize 0x00000604 /* The first 0x604 bytes reserved to CPU retention for power down mode */ +#else + #define retention_RAMsize 0x00000000 +#endif + +#if (defined(__powerquad__)) + #define powerquad_RAMsize 0x00004000 /* SRAM E(16K) reserved for powerquad */ +#else + #define powerquad_RAMsize 0x00000000 +#endif + +#define m_interrupts_start 0x20000000 + retention_RAMsize +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x20000400 + retention_RAMsize +#define m_text_size 0x0001BC00 - retention_RAMsize - powerquad_RAMsize + +#define m_data_start 0x04000000 +#define m_data_size 0x00004000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55xx.dbgconf b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55xx.dbgconf new file mode 100644 index 0000000000000000000000000000000000000000..a59776c19893a689cabe4a42ae03f377ad101762 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/LPC55xx.dbgconf @@ -0,0 +1,18 @@ +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO pin +// The SWO (Serial Wire Output) pin optionally provides data from the ITM +// for an external debug tool to evaluate. +// <0=> PIO0_10 +// <1=> PIO0_8 +SWO_Pin = 0; +// + +// Debug Configuration +// StopAfterBootloader Stop after Bootloader +// +Dbg_CR = 0x00000001; +// + + +// <<< end of configuration section >>> diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/startup_LPC55S36.S b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/startup_LPC55S36.S new file mode 100644 index 0000000000000000000000000000000000000000..154a194ae12c8399c67d95809c07958928c8167d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/arm/startup_LPC55S36.S @@ -0,0 +1,1461 @@ +/* --------------------------------------------------------------------------------------- + * @file: startup_LPC55S36.s + * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S36 + * @version: 1.1 + * @date: 2021-8-4 + * ---------------------------------------------------------------------------------------*/ +/* + * Copyright 1997-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + .syntax unified + .arch armv8-m.main + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __Vectors + +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long ADC1_IRQHandler /* ADC1 */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long DMIC_IRQHandler /* Digital microphone and DMIC subsystem */ + .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long EZH_ARCH_B0_IRQHandler /* EZH interrupt */ + .long WAKEUP_IRQHandler /* Wakeup interrupt */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + .long FlexSPI0_IRQHandler /* FlexSPI interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long Reserved58_IRQHandler /* Reserved interrupt */ + .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ + .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ + .long SPI_FILTER_IRQHandler /* SPI Filter interrupt */ + .long Reserved62_IRQHandler /* Reserved interrupt */ + .long Reserved63_IRQHandler /* Reserved interrupt */ + .long Reserved64_IRQHandler /* Reserved interrupt */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT00 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT01 interrupt */ + .long Freqme_IRQHandler /* frequency measure interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long SHA_IRQHandler /* SHA interrupt */ + .long PKC_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long POWERQUAD_IRQHandler /* PowerQuad interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* LSPI_HS interrupt */ + .long CDOG_IRQHandler /* CodeWDG interrupt */ + .long Reserved77_IRQHandler /* Reserved interrupt */ + .long I3C0_IRQHandler /* I3C interrupt */ + .long Reserved79_IRQHandler /* Reserved interrupt */ + .long Reserved80_IRQHandler /* Reserved interrupt */ + .long CSS_IRQ1_IRQHandler /* CSS_IRQ1 */ + .long Tamper_IRQHandler /* Tamper */ + .long Analog_Glitch_IRQHandler /* Analog_Glitch */ + .long Reserved84_IRQHandler /* Reserved interrupt */ + .long Reserved85_IRQHandler /* Reserved interrupt */ + .long Reserved86_IRQHandler /* Reserved interrupt */ + .long Reserved87_IRQHandler /* Reserved interrupt */ + .long Reserved88_IRQHandler /* Reserved interrupt */ + .long Reserved89_IRQHandler /* Reserved interrupt */ + .long DAC0_IRQHandler /* dac0 interrupt */ + .long DAC1_IRQHandler /* dac1 interrupt */ + .long DAC2_IRQHandler /* dac2 interrupt */ + .long HSCMP0_IRQHandler /* hscmp0 interrupt */ + .long HSCMP1_IRQHandler /* hscmp1 interrupt */ + .long HSCMP2_IRQHandler /* hscmp2 interrupt */ + .long FLEXPWM0_CAPTURE_IRQHandler /* flexpwm0_capture interrupt */ + .long FLEXPWM0_FAULT_IRQHandler /* flexpwm0_fault interrupt */ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* flexpwm0_reload_error interrupt */ + .long FLEXPWM0_COMPARE0_IRQHandler /* flexpwm0_compare0 interrupt */ + .long FLEXPWM0_RELOAD0_IRQHandler /* flexpwm0_reload0 interrupt */ + .long FLEXPWM0_COMPARE1_IRQHandler /* flexpwm0_compare1 interrupt */ + .long FLEXPWM0_RELOAD1_IRQHandler /* flexpwm0_reload1 interrupt */ + .long FLEXPWM0_COMPARE2_IRQHandler /* flexpwm0_compare2 interrupt */ + .long FLEXPWM0_RELOAD2_IRQHandler /* flexpwm0_reload2 interrupt */ + .long FLEXPWM0_COMPARE3_IRQHandler /* flexpwm0_compare3 interrupt */ + .long FLEXPWM0_RELOAD3_IRQHandler /* flexpwm0_reload3 interrupt */ + .long FLEXPWM1_CAPTURE_IRQHandler /* flexpwm1_capture interrupt */ + .long FLEXPWM1_FAULT_IRQHandler /* flexpwm1_fault interrupt */ + .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* flexpwm1_reload_error interrupt */ + .long FLEXPWM1_COMPARE0_IRQHandler /* flexpwm1_compare0 interrupt */ + .long FLEXPWM1_RELOAD0_IRQHandler /* flexpwm1_reload0 interrupt */ + .long FLEXPWM1_COMPARE1_IRQHandler /* flexpwm1_compare1 interrupt */ + .long FLEXPWM1_RELOAD1_IRQHandler /* flexpwm1_reload1 interrupt */ + .long FLEXPWM1_COMPARE2_IRQHandler /* flexpwm1_compare2 interrupt */ + .long FLEXPWM1_RELOAD2_IRQHandler /* flexpwm1_reload2 interrupt */ + .long FLEXPWM1_COMPARE3_IRQHandler /* flexpwm1_compare3 interrupt */ + .long FLEXPWM1_RELOAD3_IRQHandler /* flexpwm1_reload3 interrupt */ + .long ENC0_COMPARE_IRQHandler /* enc0_compare interrupt */ + .long ENC0_HOME_IRQHandler /* enc0_home interrupt */ + .long ENC0_WDG_IRQHandler /* enc0_wdg interrupt */ + .long ENC0_IDX_IRQHandler /* enc0_idx interrupt */ + .long ENC1_COMPARE_IRQHandler /* enc1_compare interrupt */ + .long ENC1_HOME_IRQHandler /* enc1_home interrupt */ + .long ENC1_WDG_IRQHandler /* enc1_wdg interrupt */ + .long ENC1_IDX_IRQHandler /* enc1_idx interrupt */ + .long ITRC0_IRQHandler /* itrc0 interrupt */ + .long Reserved127_IRQHandler /* Reserved interrupt */ + .long CSSV2_ERR_IRQHandler /* cssv2_err interrupt */ + .long PKC_ERR_IRQHandler /* pkc_err interrupt */ + .long Reserved130_IRQHandler /* Reserved interrupt */ + .long Reserved131_IRQHandler /* Reserved interrupt */ + .long Reserved132_IRQHandler /* Reserved interrupt */ + .long Reserved133_IRQHandler /* Reserved interrupt */ + .long FLASH_IRQHandler /* flash interrupt */ + .long RAM_PARITY_ECC_ERR_IRQHandler /* ram_parity_ecc_err interrupt */ + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Base + msr msplim, r0 + ldr r0,=SystemInit + blx r0 + cpsie i /* Unmask interrupts */ + ldr r0,=__main + bx r0 + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak DMIC_IRQHandler + .type DMIC_IRQHandler, %function +DMIC_IRQHandler: + ldr r0,=DMIC_DriverIRQHandler + bx r0 + .size DMIC_IRQHandler, . - DMIC_IRQHandler + + .align 1 + .thumb_func + .weak HWVAD0_IRQHandler + .type HWVAD0_IRQHandler, %function +HWVAD0_IRQHandler: + ldr r0,=HWVAD0_DriverIRQHandler + bx r0 + .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak EZH_ARCH_B0_IRQHandler + .type EZH_ARCH_B0_IRQHandler, %function +EZH_ARCH_B0_IRQHandler: + ldr r0,=EZH_ARCH_B0_DriverIRQHandler + bx r0 + .size EZH_ARCH_B0_IRQHandler, . - EZH_ARCH_B0_IRQHandler + + .align 1 + .thumb_func + .weak WAKEUP_IRQHandler + .type WAKEUP_IRQHandler, %function +WAKEUP_IRQHandler: + ldr r0,=WAKEUP_DriverIRQHandler + bx r0 + .size WAKEUP_IRQHandler, . - WAKEUP_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak FlexSPI0_IRQHandler + .type FlexSPI0_IRQHandler, %function +FlexSPI0_IRQHandler: + ldr r0,=FlexSPI0_DriverIRQHandler + bx r0 + .size FlexSPI0_IRQHandler, . - FlexSPI0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak Reserved58_IRQHandler + .type Reserved58_IRQHandler, %function +Reserved58_IRQHandler: + ldr r0,=Reserved58_DriverIRQHandler + bx r0 + .size Reserved58_IRQHandler, . - Reserved58_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ0_IRQHandler + .type CAN0_IRQ0_IRQHandler, %function +CAN0_IRQ0_IRQHandler: + ldr r0,=CAN0_IRQ0_DriverIRQHandler + bx r0 + .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ1_IRQHandler + .type CAN0_IRQ1_IRQHandler, %function +CAN0_IRQ1_IRQHandler: + ldr r0,=CAN0_IRQ1_DriverIRQHandler + bx r0 + .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak SPI_FILTER_IRQHandler + .type SPI_FILTER_IRQHandler, %function +SPI_FILTER_IRQHandler: + ldr r0,=SPI_FILTER_DriverIRQHandler + bx r0 + .size SPI_FILTER_IRQHandler, . - SPI_FILTER_IRQHandler + + .align 1 + .thumb_func + .weak Reserved62_IRQHandler + .type Reserved62_IRQHandler, %function +Reserved62_IRQHandler: + ldr r0,=Reserved62_DriverIRQHandler + bx r0 + .size Reserved62_IRQHandler, . - Reserved62_IRQHandler + + .align 1 + .thumb_func + .weak Reserved63_IRQHandler + .type Reserved63_IRQHandler, %function +Reserved63_IRQHandler: + ldr r0,=Reserved63_DriverIRQHandler + bx r0 + .size Reserved63_IRQHandler, . - Reserved63_IRQHandler + + .align 1 + .thumb_func + .weak Reserved64_IRQHandler + .type Reserved64_IRQHandler, %function +Reserved64_IRQHandler: + ldr r0,=Reserved64_DriverIRQHandler + bx r0 + .size Reserved64_IRQHandler, . - Reserved64_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak Freqme_IRQHandler + .type Freqme_IRQHandler, %function +Freqme_IRQHandler: + ldr r0,=Freqme_DriverIRQHandler + bx r0 + .size Freqme_IRQHandler, . - Freqme_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak SHA_IRQHandler + .type SHA_IRQHandler, %function +SHA_IRQHandler: + ldr r0,=SHA_DriverIRQHandler + bx r0 + .size SHA_IRQHandler, . - SHA_IRQHandler + + .align 1 + .thumb_func + .weak PKC_IRQHandler + .type PKC_IRQHandler, %function +PKC_IRQHandler: + ldr r0,=PKC_DriverIRQHandler + bx r0 + .size PKC_IRQHandler, . - PKC_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak POWERQUAD_IRQHandler + .type POWERQUAD_IRQHandler, %function +POWERQUAD_IRQHandler: + ldr r0,=POWERQUAD_DriverIRQHandler + bx r0 + .size POWERQUAD_IRQHandler, . - POWERQUAD_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + + .align 1 + .thumb_func + .weak CDOG_IRQHandler + .type CDOG_IRQHandler, %function +CDOG_IRQHandler: + ldr r0,=CDOG_DriverIRQHandler + bx r0 + .size CDOG_IRQHandler, . - CDOG_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved79_IRQHandler + .type Reserved79_IRQHandler, %function +Reserved79_IRQHandler: + ldr r0,=Reserved79_DriverIRQHandler + bx r0 + .size Reserved79_IRQHandler, . - Reserved79_IRQHandler + + .align 1 + .thumb_func + .weak Reserved80_IRQHandler + .type Reserved80_IRQHandler, %function +Reserved80_IRQHandler: + ldr r0,=Reserved80_DriverIRQHandler + bx r0 + .size Reserved80_IRQHandler, . - Reserved80_IRQHandler + + .align 1 + .thumb_func + .weak CSS_IRQ1_IRQHandler + .type CSS_IRQ1_IRQHandler, %function +CSS_IRQ1_IRQHandler: + ldr r0,=CSS_IRQ1_DriverIRQHandler + bx r0 + .size CSS_IRQ1_IRQHandler, . - CSS_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak Tamper_IRQHandler + .type Tamper_IRQHandler, %function +Tamper_IRQHandler: + ldr r0,=Tamper_DriverIRQHandler + bx r0 + .size Tamper_IRQHandler, . - Tamper_IRQHandler + + .align 1 + .thumb_func + .weak Analog_Glitch_IRQHandler + .type Analog_Glitch_IRQHandler, %function +Analog_Glitch_IRQHandler: + ldr r0,=Analog_Glitch_DriverIRQHandler + bx r0 + .size Analog_Glitch_IRQHandler, . - Analog_Glitch_IRQHandler + + .align 1 + .thumb_func + .weak Reserved84_IRQHandler + .type Reserved84_IRQHandler, %function +Reserved84_IRQHandler: + ldr r0,=Reserved84_DriverIRQHandler + bx r0 + .size Reserved84_IRQHandler, . - Reserved84_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak Reserved87_IRQHandler + .type Reserved87_IRQHandler, %function +Reserved87_IRQHandler: + ldr r0,=Reserved87_DriverIRQHandler + bx r0 + .size Reserved87_IRQHandler, . - Reserved87_IRQHandler + + .align 1 + .thumb_func + .weak Reserved88_IRQHandler + .type Reserved88_IRQHandler, %function +Reserved88_IRQHandler: + ldr r0,=Reserved88_DriverIRQHandler + bx r0 + .size Reserved88_IRQHandler, . - Reserved88_IRQHandler + + .align 1 + .thumb_func + .weak Reserved89_IRQHandler + .type Reserved89_IRQHandler, %function +Reserved89_IRQHandler: + ldr r0,=Reserved89_DriverIRQHandler + bx r0 + .size Reserved89_IRQHandler, . - Reserved89_IRQHandler + + .align 1 + .thumb_func + .weak DAC0_IRQHandler + .type DAC0_IRQHandler, %function +DAC0_IRQHandler: + ldr r0,=DAC0_DriverIRQHandler + bx r0 + .size DAC0_IRQHandler, . - DAC0_IRQHandler + + .align 1 + .thumb_func + .weak DAC1_IRQHandler + .type DAC1_IRQHandler, %function +DAC1_IRQHandler: + ldr r0,=DAC1_DriverIRQHandler + bx r0 + .size DAC1_IRQHandler, . - DAC1_IRQHandler + + .align 1 + .thumb_func + .weak DAC2_IRQHandler + .type DAC2_IRQHandler, %function +DAC2_IRQHandler: + ldr r0,=DAC2_DriverIRQHandler + bx r0 + .size DAC2_IRQHandler, . - DAC2_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP0_IRQHandler + .type HSCMP0_IRQHandler, %function +HSCMP0_IRQHandler: + ldr r0,=HSCMP0_DriverIRQHandler + bx r0 + .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP1_IRQHandler + .type HSCMP1_IRQHandler, %function +HSCMP1_IRQHandler: + ldr r0,=HSCMP1_DriverIRQHandler + bx r0 + .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP2_IRQHandler + .type HSCMP2_IRQHandler, %function +HSCMP2_IRQHandler: + ldr r0,=HSCMP2_DriverIRQHandler + bx r0 + .size HSCMP2_IRQHandler, . - HSCMP2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_CAPTURE_IRQHandler + .type FLEXPWM0_CAPTURE_IRQHandler, %function +FLEXPWM0_CAPTURE_IRQHandler: + ldr r0,=FLEXPWM0_CAPTURE_DriverIRQHandler + bx r0 + .size FLEXPWM0_CAPTURE_IRQHandler, . - FLEXPWM0_CAPTURE_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE0_IRQHandler + .type FLEXPWM0_COMPARE0_IRQHandler, %function +FLEXPWM0_COMPARE0_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE0_IRQHandler, . - FLEXPWM0_COMPARE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD0_IRQHandler + .type FLEXPWM0_RELOAD0_IRQHandler, %function +FLEXPWM0_RELOAD0_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD0_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD0_IRQHandler, . - FLEXPWM0_RELOAD0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE1_IRQHandler + .type FLEXPWM0_COMPARE1_IRQHandler, %function +FLEXPWM0_COMPARE1_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE1_IRQHandler, . - FLEXPWM0_COMPARE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD1_IRQHandler + .type FLEXPWM0_RELOAD1_IRQHandler, %function +FLEXPWM0_RELOAD1_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD1_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD1_IRQHandler, . - FLEXPWM0_RELOAD1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE2_IRQHandler + .type FLEXPWM0_COMPARE2_IRQHandler, %function +FLEXPWM0_COMPARE2_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE2_IRQHandler, . - FLEXPWM0_COMPARE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD2_IRQHandler + .type FLEXPWM0_RELOAD2_IRQHandler, %function +FLEXPWM0_RELOAD2_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD2_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD2_IRQHandler, . - FLEXPWM0_RELOAD2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE3_IRQHandler + .type FLEXPWM0_COMPARE3_IRQHandler, %function +FLEXPWM0_COMPARE3_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE3_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE3_IRQHandler, . - FLEXPWM0_COMPARE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD3_IRQHandler + .type FLEXPWM0_RELOAD3_IRQHandler, %function +FLEXPWM0_RELOAD3_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD3_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD3_IRQHandler, . - FLEXPWM0_RELOAD3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_CAPTURE_IRQHandler + .type FLEXPWM1_CAPTURE_IRQHandler, %function +FLEXPWM1_CAPTURE_IRQHandler: + ldr r0,=FLEXPWM1_CAPTURE_DriverIRQHandler + bx r0 + .size FLEXPWM1_CAPTURE_IRQHandler, . - FLEXPWM1_CAPTURE_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_FAULT_IRQHandler + .type FLEXPWM1_FAULT_IRQHandler, %function +FLEXPWM1_FAULT_IRQHandler: + ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD_ERROR_IRQHandler + .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function +FLEXPWM1_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE0_IRQHandler + .type FLEXPWM1_COMPARE0_IRQHandler, %function +FLEXPWM1_COMPARE0_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE0_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE0_IRQHandler, . - FLEXPWM1_COMPARE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD0_IRQHandler + .type FLEXPWM1_RELOAD0_IRQHandler, %function +FLEXPWM1_RELOAD0_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD0_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD0_IRQHandler, . - FLEXPWM1_RELOAD0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE1_IRQHandler + .type FLEXPWM1_COMPARE1_IRQHandler, %function +FLEXPWM1_COMPARE1_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE1_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE1_IRQHandler, . - FLEXPWM1_COMPARE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD1_IRQHandler + .type FLEXPWM1_RELOAD1_IRQHandler, %function +FLEXPWM1_RELOAD1_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD1_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD1_IRQHandler, . - FLEXPWM1_RELOAD1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE2_IRQHandler + .type FLEXPWM1_COMPARE2_IRQHandler, %function +FLEXPWM1_COMPARE2_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE2_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE2_IRQHandler, . - FLEXPWM1_COMPARE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD2_IRQHandler + .type FLEXPWM1_RELOAD2_IRQHandler, %function +FLEXPWM1_RELOAD2_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD2_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD2_IRQHandler, . - FLEXPWM1_RELOAD2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE3_IRQHandler + .type FLEXPWM1_COMPARE3_IRQHandler, %function +FLEXPWM1_COMPARE3_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE3_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE3_IRQHandler, . - FLEXPWM1_COMPARE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD3_IRQHandler + .type FLEXPWM1_RELOAD3_IRQHandler, %function +FLEXPWM1_RELOAD3_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD3_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD3_IRQHandler, . - FLEXPWM1_RELOAD3_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_COMPARE_IRQHandler + .type ENC0_COMPARE_IRQHandler, %function +ENC0_COMPARE_IRQHandler: + ldr r0,=ENC0_COMPARE_DriverIRQHandler + bx r0 + .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_HOME_IRQHandler + .type ENC0_HOME_IRQHandler, %function +ENC0_HOME_IRQHandler: + ldr r0,=ENC0_HOME_DriverIRQHandler + bx r0 + .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_WDG_IRQHandler + .type ENC0_WDG_IRQHandler, %function +ENC0_WDG_IRQHandler: + ldr r0,=ENC0_WDG_DriverIRQHandler + bx r0 + .size ENC0_WDG_IRQHandler, . - ENC0_WDG_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_IDX_IRQHandler + .type ENC0_IDX_IRQHandler, %function +ENC0_IDX_IRQHandler: + ldr r0,=ENC0_IDX_DriverIRQHandler + bx r0 + .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_COMPARE_IRQHandler + .type ENC1_COMPARE_IRQHandler, %function +ENC1_COMPARE_IRQHandler: + ldr r0,=ENC1_COMPARE_DriverIRQHandler + bx r0 + .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_HOME_IRQHandler + .type ENC1_HOME_IRQHandler, %function +ENC1_HOME_IRQHandler: + ldr r0,=ENC1_HOME_DriverIRQHandler + bx r0 + .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_WDG_IRQHandler + .type ENC1_WDG_IRQHandler, %function +ENC1_WDG_IRQHandler: + ldr r0,=ENC1_WDG_DriverIRQHandler + bx r0 + .size ENC1_WDG_IRQHandler, . - ENC1_WDG_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_IDX_IRQHandler + .type ENC1_IDX_IRQHandler, %function +ENC1_IDX_IRQHandler: + ldr r0,=ENC1_IDX_DriverIRQHandler + bx r0 + .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ITRC0_IRQHandler + .type ITRC0_IRQHandler, %function +ITRC0_IRQHandler: + ldr r0,=ITRC0_DriverIRQHandler + bx r0 + .size ITRC0_IRQHandler, . - ITRC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved127_IRQHandler + .type Reserved127_IRQHandler, %function +Reserved127_IRQHandler: + ldr r0,=Reserved127_DriverIRQHandler + bx r0 + .size Reserved127_IRQHandler, . - Reserved127_IRQHandler + + .align 1 + .thumb_func + .weak CSSV2_ERR_IRQHandler + .type CSSV2_ERR_IRQHandler, %function +CSSV2_ERR_IRQHandler: + ldr r0,=CSSV2_ERR_DriverIRQHandler + bx r0 + .size CSSV2_ERR_IRQHandler, . - CSSV2_ERR_IRQHandler + + .align 1 + .thumb_func + .weak PKC_ERR_IRQHandler + .type PKC_ERR_IRQHandler, %function +PKC_ERR_IRQHandler: + ldr r0,=PKC_ERR_DriverIRQHandler + bx r0 + .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler + + .align 1 + .thumb_func + .weak Reserved130_IRQHandler + .type Reserved130_IRQHandler, %function +Reserved130_IRQHandler: + ldr r0,=Reserved130_DriverIRQHandler + bx r0 + .size Reserved130_IRQHandler, . - Reserved130_IRQHandler + + .align 1 + .thumb_func + .weak Reserved131_IRQHandler + .type Reserved131_IRQHandler, %function +Reserved131_IRQHandler: + ldr r0,=Reserved131_DriverIRQHandler + bx r0 + .size Reserved131_IRQHandler, . - Reserved131_IRQHandler + + .align 1 + .thumb_func + .weak Reserved132_IRQHandler + .type Reserved132_IRQHandler, %function +Reserved132_IRQHandler: + ldr r0,=Reserved132_DriverIRQHandler + bx r0 + .size Reserved132_IRQHandler, . - Reserved132_IRQHandler + + .align 1 + .thumb_func + .weak Reserved133_IRQHandler + .type Reserved133_IRQHandler, %function +Reserved133_IRQHandler: + ldr r0,=Reserved133_DriverIRQHandler + bx r0 + .size Reserved133_IRQHandler, . - Reserved133_IRQHandler + + .align 1 + .thumb_func + .weak FLASH_IRQHandler + .type FLASH_IRQHandler, %function +FLASH_IRQHandler: + ldr r0,=FLASH_DriverIRQHandler + bx r0 + .size FLASH_IRQHandler, . - FLASH_IRQHandler + + .align 1 + .thumb_func + .weak RAM_PARITY_ECC_ERR_IRQHandler + .type RAM_PARITY_ECC_ERR_IRQHandler, %function +RAM_PARITY_ECC_ERR_IRQHandler: + ldr r0,=RAM_PARITY_ECC_ERR_DriverIRQHandler + bx r0 + .size RAM_PARITY_ECC_ERR_IRQHandler, . - RAM_PARITY_ECC_ERR_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ + def_irq_handler ADC1_DriverIRQHandler /* ADC1 */ + def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ + def_irq_handler DMIC_DriverIRQHandler /* Digital microphone and DMIC subsystem */ + def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler EZH_ARCH_B0_DriverIRQHandler /* EZH interrupt */ + def_irq_handler WAKEUP_DriverIRQHandler /* Wakeup interrupt */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler OS_EVENT_DriverIRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + def_irq_handler FlexSPI0_DriverIRQHandler /* FlexSPI interrupt */ + def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved58_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ + def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ + def_irq_handler SPI_FILTER_DriverIRQHandler /* SPI Filter interrupt */ + def_irq_handler Reserved62_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved63_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved64_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT00 interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT01 interrupt */ + def_irq_handler Freqme_DriverIRQHandler /* frequency measure interrupt */ + def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ + def_irq_handler SHA_DriverIRQHandler /* SHA interrupt */ + def_irq_handler PKC_DriverIRQHandler /* CASPER interrupt */ + def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ + def_irq_handler POWERQUAD_DriverIRQHandler /* PowerQuad interrupt */ + def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ + def_irq_handler FLEXCOMM8_DriverIRQHandler /* LSPI_HS interrupt */ + def_irq_handler CDOG_DriverIRQHandler /* CodeWDG interrupt */ + def_irq_handler Reserved77_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler I3C0_DriverIRQHandler /* I3C interrupt */ + def_irq_handler Reserved79_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved80_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler CSS_IRQ1_DriverIRQHandler /* CSS_IRQ1 */ + def_irq_handler Tamper_DriverIRQHandler /* Tamper */ + def_irq_handler Analog_Glitch_DriverIRQHandler /* Analog_Glitch */ + def_irq_handler Reserved84_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved85_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved86_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved87_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved88_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved89_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler DAC0_DriverIRQHandler /* dac0 interrupt */ + def_irq_handler DAC1_DriverIRQHandler /* dac1 interrupt */ + def_irq_handler DAC2_DriverIRQHandler /* dac2 interrupt */ + def_irq_handler HSCMP0_DriverIRQHandler /* hscmp0 interrupt */ + def_irq_handler HSCMP1_DriverIRQHandler /* hscmp1 interrupt */ + def_irq_handler HSCMP2_DriverIRQHandler /* hscmp2 interrupt */ + def_irq_handler FLEXPWM0_CAPTURE_DriverIRQHandler /* flexpwm0_capture interrupt */ + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler /* flexpwm0_fault interrupt */ + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler /* flexpwm0_reload_error interrupt */ + def_irq_handler FLEXPWM0_COMPARE0_DriverIRQHandler /* flexpwm0_compare0 interrupt */ + def_irq_handler FLEXPWM0_RELOAD0_DriverIRQHandler /* flexpwm0_reload0 interrupt */ + def_irq_handler FLEXPWM0_COMPARE1_DriverIRQHandler /* flexpwm0_compare1 interrupt */ + def_irq_handler FLEXPWM0_RELOAD1_DriverIRQHandler /* flexpwm0_reload1 interrupt */ + def_irq_handler FLEXPWM0_COMPARE2_DriverIRQHandler /* flexpwm0_compare2 interrupt */ + def_irq_handler FLEXPWM0_RELOAD2_DriverIRQHandler /* flexpwm0_reload2 interrupt */ + def_irq_handler FLEXPWM0_COMPARE3_DriverIRQHandler /* flexpwm0_compare3 interrupt */ + def_irq_handler FLEXPWM0_RELOAD3_DriverIRQHandler /* flexpwm0_reload3 interrupt */ + def_irq_handler FLEXPWM1_CAPTURE_DriverIRQHandler /* flexpwm1_capture interrupt */ + def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler /* flexpwm1_fault interrupt */ + def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler /* flexpwm1_reload_error interrupt */ + def_irq_handler FLEXPWM1_COMPARE0_DriverIRQHandler /* flexpwm1_compare0 interrupt */ + def_irq_handler FLEXPWM1_RELOAD0_DriverIRQHandler /* flexpwm1_reload0 interrupt */ + def_irq_handler FLEXPWM1_COMPARE1_DriverIRQHandler /* flexpwm1_compare1 interrupt */ + def_irq_handler FLEXPWM1_RELOAD1_DriverIRQHandler /* flexpwm1_reload1 interrupt */ + def_irq_handler FLEXPWM1_COMPARE2_DriverIRQHandler /* flexpwm1_compare2 interrupt */ + def_irq_handler FLEXPWM1_RELOAD2_DriverIRQHandler /* flexpwm1_reload2 interrupt */ + def_irq_handler FLEXPWM1_COMPARE3_DriverIRQHandler /* flexpwm1_compare3 interrupt */ + def_irq_handler FLEXPWM1_RELOAD3_DriverIRQHandler /* flexpwm1_reload3 interrupt */ + def_irq_handler ENC0_COMPARE_DriverIRQHandler /* enc0_compare interrupt */ + def_irq_handler ENC0_HOME_DriverIRQHandler /* enc0_home interrupt */ + def_irq_handler ENC0_WDG_DriverIRQHandler /* enc0_wdg interrupt */ + def_irq_handler ENC0_IDX_DriverIRQHandler /* enc0_idx interrupt */ + def_irq_handler ENC1_COMPARE_DriverIRQHandler /* enc1_compare interrupt */ + def_irq_handler ENC1_HOME_DriverIRQHandler /* enc1_home interrupt */ + def_irq_handler ENC1_WDG_DriverIRQHandler /* enc1_wdg interrupt */ + def_irq_handler ENC1_IDX_DriverIRQHandler /* enc1_idx interrupt */ + def_irq_handler ITRC0_DriverIRQHandler /* itrc0 interrupt */ + def_irq_handler Reserved127_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler CSSV2_ERR_DriverIRQHandler /* cssv2_err interrupt */ + def_irq_handler PKC_ERR_DriverIRQHandler /* pkc_err interrupt */ + def_irq_handler Reserved130_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved131_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved132_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved133_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler FLASH_DriverIRQHandler /* flash interrupt */ + def_irq_handler RAM_PARITY_ECC_ERR_DriverIRQHandler /* ram_parity_ecc_err interrupt */ + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..9e387ff1840ea760915b4b90a60c49ea4f992d72 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash.h @@ -0,0 +1,624 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_FLASH_H_ +#define _FSL_FLASH_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 0, 1)) /*!< Version 1.0.1. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 1, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 1 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash driver support feature + * @{ + */ +/*! @brief IAP driver support non-block erase function */ +#define FSL_SUPPORT_ERASE_SECTOR_NON_BLOCKING 1U + +#define FSL_FEATURE_SYSCON_HAS_FLASH_HIDING 1U + +#define FSL_FEATURE_SYSCON_HAS_CDPA 1U +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ + kStatus_FLASH_CfpaScratchPageInvalid = + MAKE_STATUS(kStatusGroupFlashDriver, 0x30), /*!< CFPA Scratch Page is invalid*/ + kStatus_FLASH_CfpaVersionRollbackDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x31), /*!< CFPA version rollback is not allowed */ + kStatus_FLASH_ReadHidingAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x32), /*!< Flash hiding read is not allowed */ + kStatus_FLASH_ModifyProtectedAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x33), /*!< Flash firewall page locked erase and program are not allowed */ + kStatus_FLASH_CommandOperationInProgress = MAKE_STATUS( + kStatusGroupFlashDriver, 0x34), /*!< The flash state is busy, indicate that a flash command in progress. */ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4U, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512U, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4U,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16U /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0U, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1U /*! ECC is off */ +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0U, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1U, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2U, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3U /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0U, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1U /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0U, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1U, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2U, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3U /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; + uint32_t *nbootCtx; + bool useAhbRead; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Init(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * NOTE: The start address need to be 4 Bytes-aligned. + * + * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. + * + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! + * @brief Non-blocking Erases the flash sectors encompassed by parameters passed into function. + * + * This is a non-blocking function, which returns right away. + * This function erases the appropriate number of flash sectors based on the desired start + * address and length, and get the command execute status from the "FLASH_GetCommandState". + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * NOTE: The start address need be 4 Bytes-aligned. + * + * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. + * + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + */ +status_t FLASH_EraseNonBlocking(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +/*! + * @name flash status + * @{ + */ +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + * + * @param config A pointer to the storage for the driver runtime state. + * @param startAddress The start address of the desired flash memory to be verified. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +#endif + +#if defined(FSL_FEATURE_SYSCON_HAS_CDPA) && (FSL_FEATURE_SYSCON_HAS_CDPA == 1) +/*! + * @brief Validates the given address range is loaded in the Flash firewall page locked region. + * + * @param config A pointer to the storage for the driver runtime state. + * @param startAddress The start address of the desired flash memory to be verified. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash hiding read is not allowed. + */ +status_t FLASH_IsFlashAreaModifiable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +#endif + +/*@}*/ + +/*! + * @name command status + * @{ + */ +/*! + * @brief Get flash command execute status. + * + * This function is used to obtain the status after the command "FLASH_EraseNonBlocking" is executed. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_CommandOperationInProgress Indicate that a flash command in progress. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_Success API was executed successfully. + */ +status_t FLASH_GetCommandState(flash_config_t *config); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FLASH_FLASH_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash_ffr.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash_ffr.h new file mode 100644 index 0000000000000000000000000000000000000000..67d4296d70d5078ba7b727fb000d71c8d72a4ee4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flash_ffr.h @@ -0,0 +1,568 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_FLASH_FFR_H_ +#define _FSL_FLASH_FFR_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup flash_ffr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512U) +#define FLASH_FFR_HASH_DIGEST_SIZE (32U) +#define FLASH_FFR_IV_CODE_SIZE (52U) + +enum flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0U, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_Scratch = 0U, /*!< CFPA Scratch page */ + kFfrPageOffset_CFPA_CfgPing = 1U, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 2U, /*!< Same as CFPA page (Pong page)*/ + +#if defined(LPC55S36_SERIES) + kFfrPageOffset_CMPA = 3U, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3U, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Csr_Key = 4U, /*!< Customer Key Store Area (Part of CMPA)*/ + + kFfrPageOffset_NMPA_Key = 5U, /*!< Key Store area (Part of NMPA)*/ + kFfrPageOffset_NMPA = 5U, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 8U, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 10U, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 16U, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 17U, /*!< Reserved (Part of NMPA)*/ +#else + kFfrPageOffset_CMPA = 3U, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3U, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Key = 4U, /*!< Key Store area (Part of CMPA)*/ + + kFfrPageOffset_NMPA = 7U, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 7U, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 9U, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 15U, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 16U, /*!< Reserved (Part of NMPA)*/ +#endif + +}; + +enum flash_ffr_page_num +{ + kFfrPageNum_CFPA = 3U, /*!< Customer In-Field programmed area*/ +#if defined(LPC55S36_SERIES) + kFfrPageNum_CMPA = 2U, /*!< Customer Manufacturing programmed area*/ +#else + kFfrPageNum_CMPA = 4U, /*!< Customer Manufacturing programmed area*/ +#endif + kFfrPageNum_NMPA = 13U, /*!< NXP Manufacturing programmed area*/ + + kFfrPageNum_CMPA_Cfg = 1U, + kFfrPageNum_NMPA_Romcp = 2U, + + kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, + kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), +}; + +enum flash_ffr_block_size +{ + kFfrBlockSize_Key = 52U, +#if defined(LPC55S36_SERIES) + kFfrBlockSize_ActivationCode = 996U, +#else + kFfrBlockSize_ActivationCode = 1192U, +#endif +}; + +enum cfpa_cfg_cmpa_prog_status +{ + kFfrCmpaProgStatus_Idle = 0x0U, + kFfrCmpaProgStatus_InProgress = 0x5CC55AA5U, +}; + +typedef enum +{ + kFfrCmpaProgProcess_Pre = 0x0U, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFU, +} cmpa_prog_process_t; + +typedef struct +{ + uint32_t header; /*!< [0x000-0x003] */ + uint32_t version; /*!< [0x004-0x007] */ + uint32_t secureFwVersion; /*!< [0x008-0x00b] */ + uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ + uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ + uint32_t ivPrince[3]; /*!< [0x014-0x01f] */ + uint32_t ivIped[4]; /*!< [0x020-0x02f] */ + uint32_t custCtr[8]; /*!< [0x030-0x03f] */ + uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ + uint32_t vendorUsage; /*!< [0x050-0x053] */ + uint32_t dcfgNsPin; /*!< [0x058-0x05b] */ + uint32_t dcfgNsDflt; /*!< [0x05c-0x05f] */ + uint32_t enableFaMode; /*!< [0x060-0x063] */ + uint32_t cmpaProgInProgress; /*!< [0x064-0x067] */ + uint32_t imageCmacUpdateEn; /*!< [0x068-0x06b] */ + uint32_t cfpaVersion; /*!< [0x06c-0x06f] */ + uint32_t img0Cmac[4]; /*!< [0x070-0x07f] */ + uint32_t img1Cmac[4]; /*!< [0x080-0x08f] */ + uint8_t reserved2[348]; /*!< [0x090-0x1eb] */ + uint32_t cfpaCrc; /*!< [0x1eb-0x1ef] */ + uint32_t cfpaCmac[4]; /*!< [0x1f0-0x1ff] */ +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_USBSPEED_SHIFT (9U) +#define FFR_BOOTCFG_USBSPEED_MASK (0x3u << FFR_BOOTCFG_USBSPEED_SHIFT) +#define FFR_BOOTCFG_USBSPEED_NMPASEL0 (0x0U) +#define FFR_BOOTCFG_USBSPEED_FS (0x1U) +#define FFR_BOOTCFG_USBSPEED_HS (0x2U) +#define FFR_BOOTCFG_USBSPEED_NMPASEL3 (0x3U) + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_NMPASEL (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x1U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x2U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +#define FFR_IMAGE0_CMAC_UPDATE_MASK (0x1U) +#define FFR_IMAGE1_CMAC_UPDATE_MASK (0x2U) + +typedef struct +{ + uint32_t bootCfg; /*!< [0x000-0x003] */ + uint32_t spiFlashCanCfg; /*!< [0x004-0x007] */ + struct + { + uint16_t vid; + uint16_t pid; + } usbId; /*!< [0x008-0x00b] */ + uint32_t sdioCfg; /*!< [0x00c-0x00f] */ + uint32_t dcfgPin; /*!< [0x010-0x013] */ + uint32_t dcfgDflt; /*!< [0x014-0x017] */ + uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ + uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ + uint32_t princeBaseAddr; /*!< [0x020-0x023] */ + uint32_t princeSr[3]; /*!< [0x024-0x02f] */ + uint32_t xtal32kCapBankTrim; /*!< [0x030-0x033] */ + uint32_t xtal16mCapBankTrim; /*!< [0x034-0x037] */ + uint32_t flashRemapSize; /*!< [0x038-0x03b] */ + uint32_t flashRemapOffset; /*!< [0x03c-0x03f] */ + uint32_t princeXom[3]; /*!< [0x040-0x04b] */ + uint32_t rokthUsage; /*!< [0x04c-0x04f] */ + uint32_t rotkh[12]; /*!< [0x050-0x07f] */ + uint32_t flexspiCfg0; /*!< [0x080-0x083] */ + uint32_t flexspiCfg1; /*!< [0x084-0x087] */ + uint8_t reserved1[8]; /*!< [0x088-0x08f] */ + struct + { + uint32_t ipedStartAddr; /*!< [0x090-0x093] */ + uint32_t ipedEndAddr; /*!< [0x094-0x097] */ + } ipedRegions[4]; + + uint8_t reserved2[320]; /*!< [0x0b0-0x1ef] */ + uint32_t cmpaCmac[4]; /*!< [0x1f0-0x1ff] */ +} cmpa_cfg_info_t; + +typedef struct +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_USBCFG_USBSPEED_HS (0x0U) +#define FFR_USBCFG_USBSPEED_FS (0x1U) +#define FFR_USBCFG_USBSPEED_NO (0x2U) + +#define FFR_MCAN_BAUDRATE_MASK (0xF0000U) +#define FFR_MCAN_BAUDRATE_SHIFT (16U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +#define FFR_PUF_SRAM_CONFIG_MASK (0x3FFFF07) +#define FFR_PUF_SRAM_CONFIG_MASK_SHIFT (0U) +#define FFR_PUF_SRAM_VALID_MASK (0x1U) +#define FFR_PUF_SRAM_VALID_SHIFT (0U) +#define FFR_PUF_SRAM_MODE_MASK (0x2U) +#define FFR_PUF_SRAM_MODE_SHIFT (1U) +#define FFR_PUF_SRAM_CKGATING_MASK (0x4U) +#define FFR_PUF_SRAM_CKGATING_SHIFT (2U) +#define FFR_PUF_SRAM_SMB_MASK (0x300U) +#define FFR_PUF_SRAM_SMB_SHIFT (8U) +#define FFR_PUF_SRAM_RM_MASK (0x1C00U) +#define FFR_PUF_SRAM_RM_SHIFT (10U) +#define FFR_PUF_SRAM_WM_MASK (0xE000U) +#define FFR_PUF_SRAM_WM_SHIFT (13U) +#define FFR_PUF_SRAM_WRME_MASK (0x10000U) +#define FFR_PUF_SRAM_WRME_SHIFT (16U) +#define FFR_PUF_SRAM_RAEN_MASK (0x20000U) +#define FFR_PUF_SRAM_RAEN_SHIFT (17U) +#define FFR_PUF_SRAM_RAM_MASK (0x3C0000U) +#define FFR_PUF_SRAM_RAM_SHIFT (18U) +#define FFR_PUF_SRAM_WAEN_MASK (0x400000U) +#define FFR_PUF_SRAM_WAEN_SHIFT (22U) +#define FFR_PUF_SRAM_WAM_MASK (0x1800000U) +#define FFR_PUF_SRAM_WAM_SHIFT (23U) +#define FFR_PUF_SRAM_STBP_MASK (0x2000000U) +#define FFR_PUF_SRAM_STBP_SHIFT (25U) + +typedef struct +{ + uint32_t fro32kCfg; /*!< [0x000-0x003] */ + uint32_t puf_cfg; /*!< [0x004-0x007] */ + uint32_t bod; /*!< [0x008-0x00b] */ + uint32_t trim; /*!< [0x00c-0x00f] */ + uint32_t deviceID; /*!< [0x010-0x03f] */ + uint32_t peripheralCfg; /*!< [0x014-0x017] */ + uint32_t dcdPowerProFileLOW[2]; /*!< [0x018-0x01f] */ + uint32_t deviceType; /*!< [0x020-0x023] */ + uint32_t ldo_ao; /*!< [0x024-0x027] */ + uint32_t gdetDelayCfg; /*!< [0x028-0x02b] */ + uint32_t gdetMargin; /*!< [0x02c-0x02f] */ + uint32_t gdetTrim1; /*!< [0x030-0x033] */ + uint32_t gdetEanble1; /*!< [0x034-0x037] */ + uint32_t gdetCtrl1; /*!< [0x038-0x03b] */ + uint32_t gdetUpdateTimer; /*!< [0x03c-0x03f] */ + uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ + uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ + uint32_t ecidBackup[4]; /*!< [0x060-0x06f] */ + uint32_t uuid[4]; /*!< [0x070-0x07f] */ + uint32_t reserved1[7]; /*!< [0x080-0x09b] */ + struct + { + uint8_t xo32mReadyTimeoutInMs; + uint8_t usbSpeed; + uint8_t reserved[2]; + } usbCfg; /*!< [0x09c-0x09f] */ + uint32_t reserved2[80]; /*!< [0x0a0-0x1df] */ + uint8_t cmac[16]; /*!< [0x1e0-0x1ef] */ + uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ +} nmpa_cfg_info_t; + +typedef struct +{ + uint8_t reserved[1][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum +{ + kFFR_BankTypeBank0_NMPA = 0x00U, + kFFR_BankTypeBank1_CMPA = 0x01U, + kFFR_BankTypeBank2_CFPA = 0x02U +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + */ +status_t FFR_Lock(flash_config_t *config); + +/*! + * @brief Initialize the Security Library for FFR driver. + * + * @param config A pointer to the storage for the driver runtime state. + * @param context A pointer to the storage for the nboot data. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_SecLibInit(flash_config_t *config, uint32_t *context); + +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CfpaScratchPageInvalid CFPA Scratch Page is invalid + * @retval #kStatus_FLASH_CfpaVersionRollbackDisallowed CFPA version rollback is not allowed + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline + * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_CustomerPagesInit(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_SizeError Error size + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_Fail Generic status for Fail. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 C 0x3e600), + * and the API should be called after the FLASH_Init and FFR_Init. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A pointer to the source buffer of data that is to be programmed + * into the "Key store". + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. + * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data, + * + * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + * 2.Optional routines to set individual data members (activation code, key codes etc) to construct + * the key store structure in RAM before committing it to IFR/FFR. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. + * that will be written to 'customer factory page'. + * + * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! _FSL_FLASH_FFR_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flexspi_nor_flash.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flexspi_nor_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..e5fc3740cb5c555a549fcd2163b24a6dd664a33d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/fsl_flexspi_nor_flash.h @@ -0,0 +1,709 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_FLEXSPI_NOR_FLASH_H__ +#define _FSL_FLEXSPI_NOR_FLASH_H__ + +#include "fsl_common.h" +/*! + * @addtogroup flexspi_nor_flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 0 /*!< FLEXSPI Feature related definitions */ + +#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +#define CMD_SDR 0x01U +#define CMD_DDR 0x21U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x22U +#define CADDR_SDR 0x03U +#define CADDR_DDR 0x23U +#define MODE1_SDR 0x04U +#define MODE1_DDR 0x24U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x25U +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x26U +#define MODE8_SDR 0x07U +#define MODE8_DDR 0x27U +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x28U +#define READ_SDR 0x09U +#define READ_DDR 0x29U +#define LEARN_SDR 0x0AU +#define LEARN_DDR 0x2AU +#define DATSZ_SDR 0x0BU +#define DATSZ_DDR 0x2BU +#define DUMMY_SDR 0x0CU +#define DUMMY_DDR 0x2CU +#define DUMMY_RWDS_SDR 0x0DU +#define DUMMY_RWDS_DDR 0x2DU +#define JMP_ON_CS 0x1FU +#define FLEXSPI_STOP 0U + +#define FLEXSPI_1PAD 0U +#define FLEXSPI_2PAD 1U +#define FLEXSPI_4PAD 2U +#define FLEXSPI_8PAD 3U + +/*! + * @brief NOR LUT sequence index used for default LUT assignment + * NOTE: + * The will take effect if the lut sequences are not customized. + */ +#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READID 7U +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */ + +/*! @brief FLEXSPI status group numbers. */ +enum _flexspi_status_groups +{ + kStatusROMGroup_FLEXSPI = 60, /*!< Group number for ROM FLEXSPI status codes. */ + kStatusROMGroup_FLEXSPINOR = 201, /*!< ROM FLEXSPI NOR status group number.*/ +}; + +/*! @brief FLEXSPI NOR status */ +enum _flexspi_nor_status +{ + kStatus_FLEXSPINOR_ProgramFail = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 0), /*!< Status for Page programming failure */ + kStatus_FLEXSPINOR_EraseSectorFail = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 1), /*!< Status for Sector Erase failure */ + kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 2), /*!< Status for Chip Erase failure */ + kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 3), /*!< Status for timeout */ + kStatus_FlexSPINOR_NotSupported = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 4), // Status for PageSize overflow */ + kStatus_FlexSPINOR_WriteAlignmentError = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 5), /*!< Status for Alignement error */ + kStatus_FlexSPINOR_CommandFailure = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 6), /*!< Status for Erase/Program Verify Error */ + kStatus_FlexSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ + kStatus_FLEXSPINOR_Unsupported_SFDP_Version = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 8), /*!< Status for Unrecognized SFDP version */ + kStatus_FLEXSPINOR_Flash_NotFound = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ + kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ + + kStatus_FLEXSPI_SequenceExecutionTimeout = + MAKE_STATUS(kStatusROMGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ + kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ + kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 2), /*!< Status for Device timeout */ + +}; + +/*! @brief Configure the device_type of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorCfgOption_Tag = 0x0cU, + kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0U, + kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1U, + kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2U, + kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3U, + kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4U, + kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5U, + kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6U, + kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7U, + kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8U, + kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9U, +}; + +/*! @brief Configure the quad_mode_setting of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorQuadMode_NotConfig = 0U, + kSerialNorQuadMode_StatusReg1_Bit6 = 1U, + kSerialNorQuadMode_StatusReg2_Bit1 = 2U, + kSerialNorQuadMode_StatusReg2_Bit7 = 3U, + kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4U, +}; + +/*! @brief FLEXSPI NOR Octal mode */ +enum +{ + kSerialNorOctaldMode_NoOctalEnableBit = 0U, + kSerialNorOctaldMode_HasOctalEnableBit = 1U, +}; + +/*! @brief miscellaneous mode */ +enum +{ + kSerialNorEnhanceMode_Disabled = 0U, + kSerialNorEnhanceMode_0_4_4_Mode = 1U, + kSerialNorEnhanceMode_0_8_8_Mode = 2U, + kSerialNorEnhanceMode_DataOrderSwapped = 3U, + kSerialNorEnhanceMode_2ndPinMux = 4U, + kSerialNorEnhanceMode_InternalLoopback = 5U, + kSerialNorEnhanceMode_SpiMode = 6U, + kSerialNorEnhanceMode_ExtDqs = 8U, +}; + +/*! @brief FLEXSPI NOR reset logic options */ +enum +{ + kFlashResetLogic_Disabled = 0U, + kFlashResetLogic_ResetPin = 1U, + kFlashResetLogic_JedecHwReset = 2U, +}; + +/*! @brief Configure the flash_connection of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorConnection_SinglePortA, + kSerialNorConnection_Parallel, + kSerialNorConnection_SinglePortB, + kSerialNorConnection_BothPorts +}; + +/*! @brief + * FLEXSPI ROOT clock soruce related definitions + */ +enum +{ + kFLEXSPIClkSrc_MainClk = 0U, + kFLEXSPIClkSrc_Pll0 = 1U, + kFLEXSPIClkSrc_FroHf = 3U, + kFLEXSPIClkSrc_Pll1 = 5U, +}; + +/*! @brief Restore sequence options + * Configure the restore_sequence of "flash_run_context_t" structure + */ +enum +{ + kRestoreSequence_None = 0U, + kRestoreSequence_HW_Reset = 1U, + kRestoreSequence_QPI_4_0xFFs = 2U, + kRestoreSequence_QPI_Mode_0x00 = 3U, + kRestoreSequence_8QPI_FF = 4U, + kRestoreSequence_Send_F0 = 5U, + kRestoreSequence_Send_66_99 = 6U, + kRestoreSequence_Send_6699_9966 = 7U, + kRestoreSequence_Send_06_FF = 8U, /*!< Adesto EcoXIP */ + kRestoreSequence_QPI_5_0xFFs = 9U, + kRestoreSequence_Send_QPI_8_0xFFs = 10U, + kRestoreSequence_Wakeup_0xAB = 11U, + kRestoreSequence_Wakeup_0xAB_54 = 12U, +}; + +/*! @brief Port mode options*/ +enum +{ + kFlashInstMode_ExtendedSpi = 0x00U, + kFlashInstMode_0_4_4_SDR = 0x01U, + kFlashInstMode_0_4_4_DDR = 0x02U, + kFlashInstMode_DPI_SDR = 0x21U, + kFlashInstMode_DPI_DDR = 0x22U, + kFlashInstMode_QPI_SDR = 0x41U, + kFlashInstMode_QPI_DDR = 0x42U, + kFlashInstMode_OPI_SDR = 0x81U, + kFlashInstMode_OPI_DDR = 0x82U, +}; + +/*! + * @name Support for init FLEXSPI NOR configuration + * @{ + */ +/*! @brief Flash Pad Definitions */ +enum +{ + kSerialFlash_1Pad = 1U, + kSerialFlash_2Pads = 2U, + kSerialFlash_4Pads = 4U, + kSerialFlash_8Pads = 8U, +}; + +/*! @brief FLEXSPI clock configuration type */ +enum +{ + kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ + kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */ +}; + +/*! @brief FLEXSPI Read Sample Clock Source definition */ +enum _flexspi_read_sample_clk +{ + kFLEXSPIReadSampleClk_LoopbackInternally = 0U, + kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, + kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, + kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, +}; + +/*! @brief Flash Type Definition */ +enum +{ + kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ +}; + +/*! @brief Flash Configuration Command Type */ +enum +{ + kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */ + kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ + kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ + kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ + kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ + kDeviceConfigCmdType_Reset, /*!< Reset device command */ +}; + +/*! @brief Defintions for FLEXSPI Serial Clock Frequency */ +enum _flexspi_serial_clk_freq +{ + kFLEXSPISerialClk_NoChange = 0U, + kFLEXSPISerialClk_30MHz = 1U, + kFLEXSPISerialClk_50MHz = 2U, + kFLEXSPISerialClk_60MHz = 3U, + kFLEXSPISerialClk_75MHz = 4U, + kFLEXSPISerialClk_80MHz = 5U, + kFLEXSPISerialClk_100MHz = 6U, + kFLEXSPISerialClk_133MHz = 7U, + kFLEXSPISerialClk_166MHz = 8U, +}; + +/*! @brief Misc feature bit definitions */ +enum +{ + kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ + kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ + kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ + kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ + kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ + kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ + kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */ + kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ +}; + +/*@}*/ + +/*! @brief Manufacturer ID */ +enum +{ + kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ + kSerialFlash_Adesto_ManufacturerID = 0x1FU, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ + kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ + kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ +}; + +/*! @brief + * Serial NOR configuration option + */ +typedef struct _serial_nor_config_option +{ + union + { + struct + { + uint32_t max_freq : 4; /*!< Maximum supported Frequency */ + uint32_t misc_mode : 4; /*!< miscellaneous mode */ + uint32_t quad_mode_setting : 4; /*!< Quad mode setting */ + uint32_t cmd_pads : 4; /*!< Command pads */ + uint32_t query_pads : 4; /*!< SFDP read pads */ + uint32_t device_type : 4; /*!< Device type */ + uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */ + uint32_t tag : 4; /*!< Tag, must be 0x0E */ + } B; + uint32_t U; + } option0; + + union + { + struct + { + uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */ + uint32_t status_override : 8; /*!< Override status register value during device mode configuration */ + uint32_t pinmux_group : 4; /*!< The pinmux group selection */ + uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */ + uint32_t drive_strength : 4; /*!< The Drive Strength of FLEXSPI Pads */ + uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - */ + /*!< Parallel mode, 2 - Single Flash connected to Port B */ + } B; + uint32_t U; + } option1; + +} serial_nor_config_option_t; + +typedef union +{ + struct + { + uint8_t por_mode; + uint8_t current_mode; + uint8_t exit_no_cmd_sequence; + uint8_t restore_sequence; + } B; + uint32_t U; +} flash_run_context_t; + +/*! @brief + * FLEXSPI LUT Sequence structure + */ +typedef struct _lut_sequence +{ + uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +typedef struct +{ + uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; + +/*! @brief + * FLEXSPI Memory Configuration Block + */ +typedef struct _FlexSPIConfig +{ + uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ + uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ + uint8_t csHoldTime; /*!< [0x00d-0x00d] CS hold time, default value: 3 */ + uint8_t csSetupTime; /*!< [0x00e-0x00e] CS setup time, default value: 3 */ + uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + Serial NAND, need to refer to datasheet */ + uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ + uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + Generic configuration, etc. */ + uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + DPI/QPI/OPI switch or reset command */ + flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + sequence number, [31:16] Reserved */ + uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ + uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ + flexspi_lut_seq_t + configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ + uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + details */ + uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ + uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ + uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + Chapter for more details */ + uint8_t lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ + uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ + flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ + uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + busy flag is 0 when flash device is busy */ + uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ + flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ + uint32_t dll0CrVal; //!> [0x1b0-0x1b3] Customizable DLL0CR setting */ + uint32_t dll1CrVal; //!> [0x1b4-0x1b7] Customizable DLL1CR setting */ + uint32_t reserved4[2]; /*!< [0x1b8-0x1bf] Reserved for future use */ +} flexspi_mem_config_t; + +/*! @brief + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ + uint32_t pageSize; /*!< Page size of Serial NOR */ + uint32_t sectorSize; /*!< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /*!< Reserved for future use */ + uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ + uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */ + uint32_t blockSize; /*!< Block size */ + uint32_t flashStateCtx; /*!< Flash State Context */ + uint32_t reserve2[10]; /*!< Reserved for future use */ +} flexspi_nor_config_t; + +typedef enum _flexspi_operation +{ + kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ + kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ + kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ + kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPIOperation_End = kFLEXSPIOperation_Read, +} flexspi_operation_t; + +/*! @brief FLEXSPI Transfer Context */ +typedef struct _flexspi_xfer +{ + flexspi_operation_t operation; /*!< FLEXSPI operation */ + uint32_t baseAddress; /*!< FLEXSPI operation base address */ + uint32_t seqId; /*!< Sequence Id */ + uint32_t seqNum; /*!< Sequence Number */ + bool isParallelModeEnable; /*!< Is a parallel transfer */ + uint32_t *txBuffer; /*!< Tx buffer */ + uint32_t txSize; /*!< Tx size in bytes */ + uint32_t *rxBuffer; /*!< Rx buffer */ + uint32_t rxSize; /*!< Rx size in bytes */ +} flexspi_xfer_t; + +/*! @brief + * FLEXSPI Clock Type + */ +typedef enum +{ + kFlexSpiClock_CoreClock, /*!< ARM Core Clock */ + kFlexSpiClock_AhbClock, /*!< AHB clock */ + kFlexSpiClock_SerialRootClock, /*!< Serial Root Clock */ + kFlexSpiClock_IpgClock, /*!< IPG clock */ +} flexspi_clock_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize Serial NOR devices via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); + +/*! + * @brief Program data to Serial NOR via FLEXSPI. + * + * This function programs the NOR flash memory with the dest address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst_addr A pointer to the desired flash memory to be programmed. + * NOTE: + * It is recommended that use page aligned access; + * If the dst_addr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src); + +/*! + * @brief Erase all the Serial NOR devices connected on FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); + +/*! + * @brief Erase one sector specified by address + * + * This function erases one of NOR flash sectors based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param address The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,The driver automatically + * aligns address down with the sector address. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + +/*! + * @brief Erase one block specified by address + * + * This function erases one block of NOR flash based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use block-aligned access nor device; + * If dstAddr is not aligned with the block,The driver automatically + * aligns address down with the block address. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Erase_Block(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + +/*! + * @brief Get FLEXSPI NOR Configuration Block based on specified option. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param option A pointer to the storage Serial NOR Configuration Option Context. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, + flexspi_nor_config_t *config, + serial_nor_config_option_t *option); + +/*! + * @brief Erase Flash Region specified by address and length + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,the driver automatically + * aligns address down with the sector address. + * @param length The length, given in bytes to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If length is not aligned with the sector,the driver automatically + * aligns up with the sector. + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + +/*! + * @brief Read data from Serial NOR via FLEXSPI. + * + * This function read the NOR flash memory with the start address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst A pointer to the dest buffer of data that is to be read from the NOR flash. + * NOTE: + * It is recommended that use page aligned access; + * If the dstAddr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param start The start address of the desired NOR flash memory to be read. + * @param lengthInBytes The length, given in bytes to be read. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + +/*! + * @brief FLEXSPI command + * + * This function is used to perform the command write sequence to the NOR device. + * + * @param instance storage the index of FLEXSPI. + * @param xfer A pointer to the storage FLEXSPI Transfer Context. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); + +/*! + * @brief Configure FLEXSPI Lookup table + * + * @param instance storage the index of FLEXSPI. + * @param seqIndex storage the sequence Id. + * @param lutBase A pointer to the look-up-table for command sequences. + * @param seqNumber storage sequence number. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber); + +/*! + * @brief Set the clock source for FLEXSPI NOR + * + * @param clockSource Clock source for FLEXSPI NOR. See to "_flexspi_nor_clock_source". + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + */ +status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource); + +#ifdef __cplusplus +} +#endif + +#endif /*! _FSL_FLEXSPI_NOR_FLASH_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/src/fsl_flash.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/src/fsl_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..74ee539e537ba65c6b482e932987183ec27c358d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/flash/src/fsl_flash.c @@ -0,0 +1,511 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.niobe4analog_iap" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1302FC00U) + +/*! + * @name flash, ffr, flexspi nor flash Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); + status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +} function_command_option_t; + +/*! + * @brief Structure of version property. + * + * @ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number. */ + /* Flash driver */ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program_with_checker)(flash_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); + status_t (*flash_verify_program_with_checker)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + /*!< Flash FFR driver */ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t reserved0; + status_t reserved1; + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + status_t (*ffr_seclib_init)(flash_config_t *config, uint32_t *context); + status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_erase_non_blocking)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_get_command_state)(flash_config_t *config); +} flash_driver_interface_t; + +/*! @brief FLEXSPI Flash driver API Interface */ +typedef struct +{ + uint32_t version; + status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); + status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); + status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); + status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); + status_t (*set_clock_source)(uint32_t clockSrc); + void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); +} flexspi_nor_flash_driver_t; + +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t reserved2; /*!< reserved*/ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************** + * Internal Flash driver API + *******************************************************************************/ +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_init(config); +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase(config, start, lengthInBytes, key); +} + +status_t FLASH_EraseNonBlocking(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_non_blocking(config, start, lengthInBytes, key); + +} + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program(config, start, src, lengthInBytes); +} + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_read(config, start, dest, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program(config, start, lengthInBytes, expectedData, + failedAddress, failedData); +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); +} + +#if defined(BL_FEATURE_HAS_BUS_CRYPTO_ENGINE) && BL_FEATURE_HAS_BUS_CRYPTO_ENGINE +status_t FLASH_ErasePrologue(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_with_checker(config, start, lengthInBytes, key); +} + +status_t FLASH_ProgramPrologue(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program_with_checker(config, start, src, lengthInBytes); +} + +status_t FLASH_VerifyProgramPrologue(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program_with_checker( + config, start, lengthInBytes, expectedData, failedAddress, failedData); +} + +#endif // BL_FEATURE_HAS_BUS_CRYPTO_ENGINE + +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) +{ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x13028c41U; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.isFlashAreaReadable(config, startAddress, lengthInBytes); +} +#endif + +#if defined(FSL_FEATURE_SYSCON_HAS_CDPA) && (FSL_FEATURE_SYSCON_HAS_CDPA == 1) +/*! + * @brief Validates the given address range is loaded in the Flash firewall page locked region. + */ +status_t FLASH_IsFlashAreaModifiable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) +{ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x13028ca1U; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.isFlashAreaModifiable(config, startAddress, lengthInBytes); +} +#endif + +/*! + * @brief Get flash command execute status. + */ +status_t FLASH_GetCommandState(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_command_state(config); +} + +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +/*! + * @brief Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_init(config); +} + +/*! + * @brief Enable firewall for all flash banks. + */ +status_t FFR_Lock(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_lock(config); +} + +/*! + * @brief APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_factory_page_write(config, page_data, seal_part); +} + +/*! + * @brief See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_uuid(config, uuid); +} + +/*! + * @brief APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_data(config, pData, offset, len); +} + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_keystore_write(config, pKeyStore); +} + +/*! + * @brief APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_infield_page_write(config, page_data, valid_len); +} + +/*! + * @brief APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_infield_data(config, pData, offset, len); +} + +/*! + * @brief Initialize the Security Library for FFR driver + */ +status_t FFR_SecLibInit(flash_config_t *config, uint32_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_seclib_init(config, context); +} + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 C 0x3e600), + * and the API should be called after the FLASH_Init and FFR_Init. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +/******************************************************************************** + * FlexSPI NOR FLASH Driver API + *******************************************************************************/ +/*! + * @brief Initialize Serial NOR devices via FLEXSPI. + */ +status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->init(instance, config); +} + +/*! + * @brief Program data to Serial NOR via FlexSPI + */ +status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->page_program(instance, config, dstAddr, src); +} + +/*! + * @brief Erase all the Serial NOR devices connected on FlexSPI + */ +status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_all(instance, config); +} + +/*! + * @brief Erase Flash Region specified by address and length + */ +status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase(instance, config, start, length); +} + +/*! + * @brief Erase one sector specified by address + */ +status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_sector(instance, config, address); +} + +/*! + * @brief Erase one block specified by address + */ +status_t FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_block(instance, config, address); +} + +/*! + * @brief Get FlexSPI NOR Configuration Block based on specified option + */ +status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->get_config(instance, config, option); +} + +/*! + * @brief Read data from Serial NOR + */ +status_t FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->read(instance, config, dst, start, bytes); +} + +/*! + * @brief Perform FlexSPI command + */ +status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->xfer(instance, xfer); +} + +/*! + * @brief Configure FlexSPI Lookup table + */ +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->update_lut(instance, seqIndex, lutBase, numberOfSeq); +} + +/*! + * @brief Set flexspi clock source + */ +status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->set_clock_source(clockSource); +} + +/*! + * @brief config flexspi clock + */ +void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->config_clock(instance, freqOption, sampleClkMode); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.c new file mode 100644 index 0000000000000000000000000000000000000000..68175b880a326b6cc5137267ba884138a9adddc8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.c @@ -0,0 +1,251 @@ +/* + * Copyright 2018-2021, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_anactrl.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.anactrl" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ANACTRL module. + * + * @param base ANACTRL peripheral base address + */ +static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ANACTRL bases for each instance. */ +static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ANACTRL clocks for each instance. */ +static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the ANACTRL instance from peripheral base address. + * + * param base ANACTRL peripheral base address. + * return ANACTRL instance. + */ +static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) + { + if (s_anactrlBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_anactrlBases)); + + return instance; +} + +/*! + * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. + * + * param base ANACTRL peripheral base address. + */ +void ANACTRL_Init(ANACTRL_Type *base) +{ + assert(NULL != base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for ANACTRL instance. */ + CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. + * + * param base ANACTRL peripheral base address. + */ +void ANACTRL_Deinit(ANACTRL_Type *base) +{ + assert(NULL != base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock for ANACTRL instance. */ + CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output + * and enable/disable 96MHZ clock output. + * + * param base ANACTRL peripheral base address. + * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. + */ +void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = base->FRO192M_CTRL; + + tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); + + if (config->enable12MHzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; + } + if (config->enable96MHzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + } + + base->FRO192M_CTRL |= tmp32; +} + +/*! + * brief Gets the default configuration of FRO192M. + * The default values are: + * code + config->enable12MHzClk = true; + config->enable96MHzClk = false; + endcode + * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. + */ +void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enable12MHzClk = true; + config->enable96MHzClk = false; +} + +/*! + * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU + * system, and so on. + * + * param base ANACTRL peripheral base address. + * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. + */ +void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = base->XO32M_CTRL; + + tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); + + /* Set XO32M CTRL. */ +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; + if (config->enablePllUsbOutput) + { + tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; + } +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + + if (config->enableACBufferBypass) + { + tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; + } + + if (config->enableSysCLkOutput) + { + tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; + } + base->XO32M_CTRL = tmp32; + +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + if (config->enableADCOutput) + { + base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; + } + else + { + base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; + } +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ +} + +/*! + * brief Gets the default configuration of XO32M. + * The default values are: + * code + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; + endcode + * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. + */ +void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + config->enablePllUsbOutput = false; +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + config->enableADCOutput = true; +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ +} + +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) +/*! + * brief Measures the frequency of the target clock source. + * + * This function measures target frequency according to a accurate reference frequency.The formula is: + * Ftarget = (CAPVAL * Freference) / ((1<= 2U); + + uint32_t targetClkFreq = 0U; + uint32_t capval = 0U; + + /* Init a measurement cycle. */ + base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); + while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) + { + } + + /* Calculate the target clock frequency. */ + capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); + targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); + + return targetClkFreq; +} +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.h new file mode 100644 index 0000000000000000000000000000000000000000..4ca845b5a9a3bb1f00ce93f619db02cb556df3bb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_anactrl.h @@ -0,0 +1,377 @@ +/* + * Copyright 2018-2021, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_ANACTRL_H__ +#define __FSL_ANACTRL_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup anactrl + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief ANACTRL driver version. */ +#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` + +/*! + * @brief ANACTRL interrupt flags + */ +enum _anactrl_interrupt_flags +{ +#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) + kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status + before Interrupt Enable. */ + kANACTRL_BodVDDMainInterruptFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status + after Interrupt Enable. */ + kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN + power status output. */ +#else + kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before + Interrupt Enable. */ + kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status + after Interrupt Enable. */ + kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power + status output. */ +#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ + kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before + Interrupt Enable. */ + kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status + after Interrupt Enable. */ + kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power + status output. */ + kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before + Interrupt Enable. */ + kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after + Interrupt Enable. */ + kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power + status output. */ +}; + +/*! + * @brief ANACTRL interrupt control + */ +enum _anactrl_interrupt +{ +#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) + kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN + interrupt control. */ +#else + kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt + control. */ +#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ + kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt + control. */ + kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ +}; + +/*! + * @brief ANACTRL status flags + */ +enum _anactrl_flags +{ + kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ + kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization + error status. */ +}; + +/*! + * @brief ANACTRL FRO192M and XO32M status flags + */ +enum _anactrl_osc_flags +{ + kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ + kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector + output (signal vcco_ok). */ + kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out + frequency statibilty. */ +}; + +/*! + * @brief Configuration for FRO192M + * + * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize + * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_fro192M_config +{ + bool enable12MHzClk; /*!< Enable 12MHz clock. */ + bool enable96MHzClk; /*!< Enable 96MHz clock. */ +} anactrl_fro192M_config_t; + +/*! + * @brief Configuration for XO32M + * + * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this + * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_xo32M_config +{ + bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ +} anactrl_xo32M_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Init(ANACTRL_Type *base); + +/*! + * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Deinit(ANACTRL_Type *base); +/* @} */ + +/*! + * @name Set oscillators + * @{ + */ + +/*! + * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock + * output and enable/disable 96MHZ clock output. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. + */ +void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); + +/*! + * @brief Gets the default configuration of FRO192M. + * The default values are: + * @code + config->enable12MHzClk = true; + config->enable96MHzClk = false; + @endcode + * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. + */ +void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); + +/*! + * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU + * system, and so on. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. + */ +void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); + +/*! + * @brief Gets the default configuration of XO32M. + * The default values are: + * @code + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; + @endcode + * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. + */ +void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); + +/* @} */ + +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) +/*! + * @name Measure Frequency + * @{ + */ + +/*! + * @brief Measures the frequency of the target clock source. + * + * This function measures target frequency according to a accurate reference frequency.The formula is: + * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); +} + +/*! + * @brief Disables the ANACTRL interrupts. + * + * @param base ANACTRL peripheral base address. + * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. + */ +static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) +{ + base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); +} + +/*! + * @brief Clears the ANACTRL interrupts. + * + * @param base ANACTRL peripheral base address. + * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. + */ +static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) +{ + base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); +} +/* @} */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets ANACTRL status flags. + * + * This function gets Analog control status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_flags. + * For example, to check whether the flash is in power down mode: + * @code + * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. + */ +static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) +{ + return base->ANALOG_CTRL_STATUS; +} + +/*! + * @brief Gets ANACTRL oscillators status flags. + * + * This function gets Anactrl oscillators status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_osc_flags. + * For example, to check whether the FRO192M clock output is valid: + * @code + * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. + */ +static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) +{ + return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); +} + +/*! + * @brief Gets ANACTRL interrupt status flags. + * + * This function gets Anactrl interrupt status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. + * For example, to check whether the VBAT voltage level is above the threshold: + * @code + * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. + */ +static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) +{ + return base->BOD_DCDC_INT_STATUS & 0x1FFU; +} +/* @} */ + +#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) +/*! + * @brief Aux_Bias Control Interfaces + * @{ + */ + +/*! + * @brief Enables/disabless 1V reference voltage buffer. + * + * @param base ANACTRL peripheral base address. + * @param enable Used to enable or disable 1V reference voltage buffer. + */ +static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) +{ + if (enable) + { + base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; + } + else + { + base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; + } +} + +/* @} */ +#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ + +#if defined(__cplusplus) +} +#endif + +/* @}*/ + +#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.c new file mode 100644 index 0000000000000000000000000000000000000000..a8f1f29ddb4381e54fcd23aae4db035d1d04eacd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_aoi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aoi" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to aoi bases for each instance. */ +static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to aoi clocks for each instance. */ +static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for AOI module. + * + * @param base AOI peripheral base address + * + * @return The AOI instance + */ +static uint32_t AOI_GetInstance(AOI_Type *base); +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t AOI_GetInstance(AOI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++) + { + if (s_aoiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_aoiBases)); + + return instance; +} + +/*! + * brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * param base AOI peripheral address. + */ +void AOI_Init(AOI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock gate from clock manager. */ + CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * param base AOI peripheral address. + */ +void AOI_Deinit(AOI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock gate from clock manager */ + CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Index of the event which will be set of type aoi_event_t. + * param config Selected input configuration . + */ +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config) +{ + assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT); + assert(config != NULL); + + uint16_t value; + uint16_t temp; + /* Read BFCRT01 register at event index. */ + value = base->BFCRT[event].BFCRT01; + + temp = (value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT; + config->PT0AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT; + config->PT0BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT; + config->PT0CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT; + config->PT0DC = (aoi_input_config_t)temp; + + temp = (value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT; + config->PT1AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT; + config->PT1BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT; + config->PT1CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT; + config->PT1DC = (aoi_input_config_t)temp; + + /* Read BFCRT23 register at event index. */ + value = base->BFCRT[event].BFCRT23; + + temp = (value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT; + config->PT2AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT; + config->PT2BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT; + config->PT2CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT; + config->PT2DC = (aoi_input_config_t)temp; + + temp = (value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT; + config->PT3AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT; + config->PT3BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT; + config->PT3CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT; + config->PT3DC = (aoi_input_config_t)temp; +} + +/*! + * brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Event which will be configured of type aoi_event_t. + * param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) +{ + assert(eventConfig != NULL); + assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT); + + uint16_t value; + /* Calculate value to configure product term 0, 1 */ + value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) | + AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) | + AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) | + AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC); + /* Write value to register */ + base->BFCRT[event].BFCRT01 = value; + + /* Reset and calculate value to configure product term 2, 3 */ + value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) | + AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) | + AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) | + AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC); + /* Write value to register */ + base->BFCRT[event].BFCRT23 = value; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.h new file mode 100644 index 0000000000000000000000000000000000000000..6d905b9d64392d17c84ba6a36cb2f4c244d0f9ec --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_aoi.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_AOI_H_ +#define _FSL_AOI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup aoi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef AOI +#define AOI AOI0 /*!< AOI peripheral address */ +#endif + +/*! @name Driver version */ +/*@{*/ +#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +/*! + * @brief AOI input configurations. + * + * The selection item represents the Boolean evaluations. + */ +typedef enum _aoi_input_config +{ + kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ + kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ + kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ + kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ +} aoi_input_config_t; + +/*! + * @brief AOI event indexes, where an event is the collection of the four product + * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). + */ +typedef enum _aoi_event +{ + kAOI_Event0 = 0x0U, /*!< Event 0 index */ + kAOI_Event1 = 0x1U, /*!< Event 1 index */ + kAOI_Event2 = 0x2U, /*!< Event 2 index */ + kAOI_Event3 = 0x3U /*!< Event 3 index */ +} aoi_event_t; + +/*! + * @brief AOI event configuration structure + * + * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make + * whole event configuration. + */ +typedef struct _aoi_event_config +{ + aoi_input_config_t PT0AC; /*!< Product term 0 input A */ + aoi_input_config_t PT0BC; /*!< Product term 0 input B */ + aoi_input_config_t PT0CC; /*!< Product term 0 input C */ + aoi_input_config_t PT0DC; /*!< Product term 0 input D */ + aoi_input_config_t PT1AC; /*!< Product term 1 input A */ + aoi_input_config_t PT1BC; /*!< Product term 1 input B */ + aoi_input_config_t PT1CC; /*!< Product term 1 input C */ + aoi_input_config_t PT1DC; /*!< Product term 1 input D */ + aoi_input_config_t PT2AC; /*!< Product term 2 input A */ + aoi_input_config_t PT2BC; /*!< Product term 2 input B */ + aoi_input_config_t PT2CC; /*!< Product term 2 input C */ + aoi_input_config_t PT2DC; /*!< Product term 2 input D */ + aoi_input_config_t PT3AC; /*!< Product term 3 input A */ + aoi_input_config_t PT3BC; /*!< Product term 3 input B */ + aoi_input_config_t PT3CC; /*!< Product term 3 input C */ + aoi_input_config_t PT3DC; /*!< Product term 3 input D */ +} aoi_event_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name AOI Initialization + * @{ + */ + +/*! + * @brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * @param base AOI peripheral address. + */ +void AOI_Init(AOI_Type *base); + +/*! + * @brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * @param base AOI peripheral address. + */ +void AOI_Deinit(AOI_Type *base); + +/*@}*/ + +/*! + * @name AOI Get Set Operation + * @{ + */ + +/*! + * @brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Index of the event which will be set of type aoi_event_t. + * @param config Selected input configuration . + */ +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config); + +/*! + * @brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Event which will be configured of type aoi_event_t. + * @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*@}*/ + +/*!* @} */ + +#endif /* _FSL_AOI_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.c new file mode 100644 index 0000000000000000000000000000000000000000..6fbd07f753f54886a6c7604242f8650200e911d6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.c @@ -0,0 +1,372 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_cache64" +#endif + +#if (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0) +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of CACHE64_CTRL peripheral base address. */ +static CACHE64_CTRL_Type *const s_cache64ctrlBases[] = CACHE64_CTRL_BASE_PTRS; +/* Array of CACHE64_POLSEL peripheral base address. */ +static CACHE64_POLSEL_Type *const s_cache64polselBases[] = CACHE64_POLSEL_BASE_PTRS; + +/* Array of CACHE64 physical memory base address. */ +static uint32_t const s_cache64PhymemBases[] = CACHE64_CTRL_PHYMEM_BASES; +/* Array of CACHE64 physical memory size. */ +static uint32_t const s_cache64PhymemSizes[] = CACHE64_CTRL_PHYMEM_SIZES; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of CACHE64_CTRL clock name. */ +static const clock_ip_name_t s_cache64Clocks[] = CACHE64_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Returns an instance number given periphearl base address. + * + * param base The peripheral base address. + * return CACHE64_POLSEL instance number starting from 0. + */ +uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base) +{ + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(s_cache64polselBases); i++) + { + if (base == s_cache64polselBases[i]) + { + break; + } + } + + assert(i < ARRAY_SIZE(s_cache64polselBases)); + + return i; +} +/*! + * brief Returns an instance number given physical memory address. + * + * param address The physical memory address. + * return CACHE64_CTRL instance number starting from 0. + */ +uint32_t CACHE64_GetInstanceByAddr(uint32_t address) +{ + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(s_cache64ctrlBases); i++) + { + if ((address >= s_cache64PhymemBases[i]) && (address < s_cache64PhymemBases[i] + s_cache64PhymemSizes[i])) + { + break; + } + } + + return i; +} + +/*! + * @brief Initializes an CACHE64 instance with the user configuration structure. + * + * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * + * @param base CACHE64_POLSEL peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @retval kStatus_Success CACHE64 initialize succeed + */ +status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config) +{ + volatile uint32_t *topReg = &base->REG0_TOP; + uint32_t i; + uint32_t polsel = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = CACHE64_GetInstance(base); + + /* Enable CACHE64 clock */ + CLOCK_EnableClock(s_cache64Clocks[instance]); +#endif + + for (i = 0; i < CACHE64_REGION_NUM - 1U; i++) + { + assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1U)) == 0U); + ((volatile uint32_t *)topReg)[i] = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ? + config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT : + 0U; + } + + for (i = 0; i < CACHE64_REGION_NUM; i++) + { + polsel |= (((uint32_t)config->policy[i]) << (2U * i)); + } + base->POLSEL = polsel; + + return kStatus_Success; +} + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the CACHE64 configuration structure to a default value. The default + * values are first region covers whole cacheable area, and policy set to write back. + * + * @param config Pointer to a configuration structure. + */ +void CACHE64_GetDefaultConfig(cache64_config_t *config) +{ + (void)memset(config, 0, sizeof(cache64_config_t)); + + config->boundaryAddr[0] = s_cache64PhymemSizes[0]; + config->policy[0] = kCACHE64_PolicyWriteBack; +} + +/*! + * brief Enables the cache. + * + */ +void CACHE64_EnableCache(CACHE64_CTRL_Type *base) +{ + /* First, invalidate the entire cache. */ + CACHE64_InvalidateCache(base); + + /* Now enable the cache. */ + base->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; +} + +/*! + * brief Disables the cache. + * + */ +void CACHE64_DisableCache(CACHE64_CTRL_Type *base) +{ + /* First, push any modified contents. */ + CACHE64_CleanCache(base); + + /* Now disable the cache. */ + base->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; +} + +/*! + * brief Invalidates the cache. + * + */ +void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base) +{ + /* Invalidate all lines in both ways and initiate the cache command. */ + base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); +} + +/*! + * brief Invalidates cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be invalidated. + * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); + uint32_t instance = CACHE64_GetInstanceByAddr(address); + uint32_t endLim; + CACHE64_CTRL_Type *base; + + if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) + { + return; + } + base = s_cache64ctrlBases[instance]; + endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance]; + endAddr = endAddr > endLim ? endLim : endAddr; + + /* Set the invalidate by line command and use the physical address. */ + pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK; + base->CLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + { + } + startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans the cache. + * + */ +void CACHE64_CleanCache(CACHE64_CTRL_Type *base) +{ + /* Enable the to push all modified lines. */ + base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); +} + +/*! + * brief Cleans cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be cleaned. + * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". + * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); + uint32_t instance = CACHE64_GetInstanceByAddr(address); + uint32_t endLim; + CACHE64_CTRL_Type *base; + + if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) + { + return; + } + base = s_cache64ctrlBases[instance]; + endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance]; + endAddr = endAddr > endLim ? endLim : endAddr; + + /* Set the push by line command. */ + pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK; + base->CLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + { + } + startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans and invalidates the cache. + * + */ +void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base) +{ + /* Push and invalidate all. */ + base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK | + CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK | + CACHE64_CTRL_CCR_INVW1_MASK); +} + +/*! + * brief Cleans and invalidate cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be Cleaned and Invalidated. + * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". + * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); + uint32_t instance = CACHE64_GetInstanceByAddr(address); + uint32_t endLim; + CACHE64_CTRL_Type *base; + + if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) + { + return; + } + base = s_cache64ctrlBases[instance]; + endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance]; + endAddr = endAddr > endLim ? endLim : endAddr; + + /* Set the push by line command. */ + pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK; + base->CLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + { + } + startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; + } +} + +/*! + * brief Enable the cache write buffer. + * + */ +void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable) +{ + if (enable) + { + base->CCR |= CACHE64_CTRL_CCR_ENWRBUF_MASK; + } + else + { + base->CCR &= ~CACHE64_CTRL_CCR_ENWRBUF_MASK; + } +} + +#endif /* FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0 */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..3e708ae4546e278ce1e13ee6eeea4daacd8918ae --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache.h @@ -0,0 +1,267 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache64 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.4. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief cache line size. */ +#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE) +/*! @brief cache region number. */ +#define CACHE64_REGION_NUM (3U) +/*! @brief cache region alignment. */ +#define CACHE64_REGION_ALIGNMENT (0x400U) + +/*! @brief Level 2 cache controller way size. */ +typedef enum _cache64_policy +{ + kCACHE64_PolicyNonCacheable = 0, /*!< Non-cacheable */ + kCACHE64_PolicyWriteThrough = 1, /*!< Write through */ + kCACHE64_PolicyWriteBack = 2, /*!< Write back */ +} cache64_policy_t; + +/*! @brief CACHE64 configuration structure. */ +typedef struct _cache64_config +{ + /*!< The cache controller can divide whole memory into 3 regions. + * Boundary address is the FlexSPI internal address (start from 0) instead of system + * address (start from FlexSPI AMBA base) to split adjacent regions and must be 1KB + * aligned. The boundary address itself locates in upper region. */ + uint32_t boundaryAddr[CACHE64_REGION_NUM - 1]; + /*!< Cacheable policy for each region. */ + cache64_policy_t policy[CACHE64_REGION_NUM]; +} cache64_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name cache control for cache64 + *@{ + */ + +/*! + * @brief Returns an instance number given periphearl base address. + * + * @param base The peripheral base address. + * @return CACHE64_POLSEL instance number starting from 0. + */ +uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base); + +/*! + * brief Returns an instance number given physical memory address. + * + * param address The physical memory address. + * @return CACHE64_CTRL instance number starting from 0. + */ +uint32_t CACHE64_GetInstanceByAddr(uint32_t address); + +/*! + * @brief Initializes an CACHE64 instance with the user configuration structure. + * + * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * + * @param base CACHE64_POLSEL peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @retval kStatus_Success CACHE64 initialize succeed + */ +status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the CACHE64 configuration structure to a default value. The default + * values are first region covers whole cacheable area, and policy set to write back. + * + * @param config Pointer to a configuration structure. + */ +void CACHE64_GetDefaultConfig(cache64_config_t *config); + +/*! + * @brief Enables the cache. + * + * @param base CACHE64_CTRL peripheral base address. + * + */ +void CACHE64_EnableCache(CACHE64_CTRL_Type *base); + +/*! + * @brief Disables the cache. + * + * @param base CACHE64_CTRL peripheral base address. + * + */ +void CACHE64_DisableCache(CACHE64_CTRL_Type *base); + +/*! + * @brief Invalidates the cache. + * + * @param base CACHE64_CTRL peripheral base address. + * + */ +void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base); + +/*! + * @brief Invalidates cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". + * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the cache. + * + * @param base CACHE64_CTRL peripheral base address. + * + */ +void CACHE64_CleanCache(CACHE64_CTRL_Type *base); + +/*! + * @brief Cleans cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". + * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the cache. + * + * @param base CACHE64_CTRL peripheral base address. + * + */ +void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base); + +/*! + * @brief Cleans and invalidate cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be Cleaned and Invalidated. + * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". + * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables/disables the write buffer. + * + * @param base CACHE64_CTRL peripheral base address. + * @param enable The enable or disable flag. + * true - enable the write buffer. + * false - disable the write buffer. + */ +void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable); + +/*@}*/ + +/*! + * @name Unified Cache Control for all caches + *@{ + */ + +/*! + * @brief Invalidates instruction cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit + * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + CACHE64_InvalidateCacheByRange(address, size_byte); +} + +/*! + * @brief Invalidates data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit + * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + CACHE64_InvalidateCacheByRange(address, size_byte); +} + +/*! + * @brief Clean data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit + * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + CACHE64_CleanCacheByRange(address, size_byte); +} + +/*! + * @brief Cleans and Invalidates data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be Cleaned and Invalidated. + * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit + * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + CACHE64_CleanInvalidateCacheByRange(address, size_byte); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.c new file mode 100644 index 0000000000000000000000000000000000000000..376cbea6110e12985698a6aa918a3248350ec73e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.c @@ -0,0 +1,20 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache_n4a.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_lpcac" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.h new file mode 100644 index 0000000000000000000000000000000000000000..61f763be8a6046fbf55e25fa2203dba49608b9d6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cache_n4a.h @@ -0,0 +1,110 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_lpcac + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name cache control for the L1 low power cache controller + *@{ + */ + +/*! + * @brief Enables the processor code bus cache. + * + */ +static inline void L1CACHE_EnableCodeCache(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; +} + +/*! + * @brief Disables the processor code bus cache. + * + */ +static inline void L1CACHE_DisableCodeCache(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; +} + +/*! + * @brief Clears cache. + * + */ +static inline void L1CACHE_InvalidateCodeCache(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; +} + +/*! + * @brief Enables allocation. + * + */ +static inline void L1CACHE_EnableAllocation(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; +} + +/*! + * @brief Disables allocation. + * + */ +static inline void L1CACHE_DisableAllocation(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; +} + +/*! + * @brief Enables parity. + * + */ +static inline void L1CACHE_EnableParity(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; +} + +/*! + * @brief Disable parity. + * + */ +static inline void L1CACHE_DisableParity(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.c new file mode 100644 index 0000000000000000000000000000000000000000..e06c1b6274e48bbdca53b999c3c9cd6c90ccd5ae --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.c @@ -0,0 +1,310 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cdog.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cdog" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf) +{ + /* Default configuration after reset */ + conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ + conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ + conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ + conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ + conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ + conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ + conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ + conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ + return; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers for instruction timer. + * + * param base CDOG peripheral base address + * param reload reload value + * param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) +{ + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state of CDOG to IDLE. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop) +{ + base->STOP = stop; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + * param reload reload value for instruction timer + * param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) +{ + base->STOP = stop; + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add) +{ + base->ADD = (secure_counter_t)add; +} + +/*! + * brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add1(CDOG_Type *base) +{ + base->ADD1 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add16(CDOG_Type *base) +{ + base->ADD16 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add256(CDOG_Type *base) +{ + base->ADD256 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub) +{ + base->SUB = (secure_counter_t)sub; +} + +/*! + * brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base) +{ + base->SUB1 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base) +{ + base->SUB16 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base) +{ + base->SUB256 = (secure_counter_t)0x1U; +} + +/*! + * brief Checks secure counter. + * + * This function compares stop value with secure counter value + * by writting to RELOAD refister. + * + * param base CDOG peripheral base address + * param check expected (stop) value. + */ +void CDOG_Check(CDOG_Type *base, uint32_t check) +{ + base->RESTART = check; +} + +/*! + * brief Set the CDOG persistent word. + * + * param base CDOG peripheral base address. + * param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) +{ + base->PERSISTENT = value; +} + +/*! + * brief Get the CDOG persistent word. + * + * param base CDOG peripheral base address. + * return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base) +{ + return base->PERSISTENT; +} + +/*! + * brief Initialize CDOG + * + * This function initializes CDOG block and setting. + * + * param base CDOG peripheral base address + * param conf CDOG configuration structure + * return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) +{ + /* Ungate clock to CDOG engine and reset it */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Cdog); +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + + if (base->CONTROL == 0x0U) + { + /* CDOG is not in IDLE mode, which may be cause after SW reset. */ + /* Writing to CONTROL register will trigger fault. */ + return kStatus_Fail; + } + + /* Clear pending errors, otherwise the device will reset */ + /* itself immediately after enable Code Watchdog */ + if ((uint32_t)kCDOG_LockCtrl_Lock == + ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) + + { + CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | + CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | + CDOG_FLAGS_POR_FLAG(1U); + } + else + { + CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | + CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | + CDOG_FLAGS_POR_FLAG(0U); + } + + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL( + conf->debug_halt) | /* Halt CDOG timer during debug so we have chance to debug code */ + CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */ + + NVIC_EnableIRQ(CDOG_IRQn); + + return kStatus_Success; +} + +/*! + * brief Deinitialize CDOG + * + * This function stops CDOG secure counter. + * + * param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base) +{ + NVIC_DisableIRQ(CDOG_IRQn); + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Cdog); +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.h new file mode 100644 index 0000000000000000000000000000000000000000..b93c8dbdfe7de2804e5312d2b8514f8ea7ea3afd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cdog.h @@ -0,0 +1,325 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CDOG_H_ +#define _FSL_CDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup CDOG + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines CDOG driver version 2.1.1. + * + * Change log: + * - Version 2.1.1 + * - Remove bit CONTROL[CONTROL_CTRL] + * - Version 2.1.0 + * - Rename CWT to CDOG + * - Version 2.0.2 + * - Fix MISRA-2012 issues + * - Version 2.0.1 + * - Fix doxygen issues + * - Version 2.0.0 + * - initial version + */ +#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +typedef struct +{ + uint8_t lock : 2; + uint8_t timeout : 3; + uint8_t miscompare : 3; + uint8_t sequence : 3; + uint8_t state : 3; + uint8_t address : 3; + uint8_t reserved : 8; + uint8_t irq_pause : 2; + uint8_t debug_halt : 2; +} cdog_config_t; + +enum __cdog_debug_Action_ctrl_enum +{ + kCDOG_DebugHaltCtrl_Run = 0x1, + kCDOG_DebugHaltCtrl_Pause = 0x2, +}; + +enum __cdog_irq_pause_ctrl_enum +{ + kCDOG_IrqPauseCtrl_Run = 0x1, + kCDOG_IrqPauseCtrl_Pause = 0x2, +}; + +enum __cdog_fault_ctrl_enum +{ + kCDOG_FaultCtrl_EnableReset = 0x1U, + kCDOG_FaultCtrl_EnableInterrupt = 0x2U, + kCDOG_FaultCtrl_NoAction = 0x4U, +}; + +enum __code_lock_ctrl_enum +{ + kCDOG_LockCtrl_Lock = 0x1, + kCDOG_LockCtrl_Unlock = 0x2, +}; + +typedef uint32_t secure_counter_t; + +#define SC_ADD(add) \ + do \ + { \ + CDOG->ADD = (secure_counter_t)(add); \ + } while (0) + +#define SC_ADD1 \ + do \ + { \ + CDOG->ADD1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD16 \ + do \ + { \ + CDOG->ADD16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD256 \ + do \ + { \ + CDOG->ADD256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB(sub) \ + do \ + { \ + CDOG->SUB = (secure_counter_t)(sub); \ + } while (0) + +#define SC_SUB1 \ + do \ + { \ + CDOG->SUB1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB16 \ + do \ + { \ + CDOG->SUB16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB256 \ + do \ + { \ + CDOG->SUB256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_CHECK(val) \ + do \ + { \ + CDOG->RESTART = (secure_counter_t)val; \ + } while (0) + +/******************************************************************************* + * API + *******************************************************************************/ + +extern void CDOG_DriverIRQHandler(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CDOG Functional Operation + * @{ + */ + +/*! + * @brief Initialize CDOG + * + * This function initializes CDOG block and setting. + * + * @param base CDOG peripheral base address + * @param conf CDOG configuration structure + * @return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); + +/*! + * @brief Deinitialize CDOG + * + * This function deinitializes CDOG secure counter. + * + * @param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base); + +/*! + * @brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * @param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf); + +/*! + * @brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state od CDOG to IDLE. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers + * for instruction timer and secure counter + * + * @param base CDOG peripheral base address + * @param reload reload value + * @param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); + +/*! + * @brief Checks secure counter. + * + * This function compares stop value in handler with secure counter value + * by writting to RELOAD refister. + * + * @param base CDOG peripheral base address + * @param check expected (stop) value + */ +void CDOG_Check(CDOG_Type *base, uint32_t check); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + * @param reload reload value for instruction timer + * @param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); + +/*! + * @brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * @param base CDOG peripheral base address. + * @param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add); + +/*! + * @brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add1(CDOG_Type *base); + +/*! + * @brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add16(CDOG_Type *base); + +/*! + * @brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add256(CDOG_Type *base); + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub); + +/*! + * @brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base); + +/*! + * @brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base); + +/*! + * @brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base); + +/*! + * @brief Set the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); + +/*! + * @brief Get the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group cdog */ + +#endif /* _FSL_CDOG_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..0e66bf5b60151261e36599d98f91349a4f406179 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.c @@ -0,0 +1,2447 @@ +/* + * Copyright 2017 - 2020 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ +#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control1 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) + +/* PLL0 SSCG control1 */ +#define PLL0_SSCG_MD_FRACT_P 0U +#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) + +#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) + +/* Peripheral FLASH_NMPA base address */ +#define FLASH_NMPA_BASE (0x3FC00u) +/* Return values from Config (N-2) page of flash */ +#define GET_HFXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC0U)) // (0x3FCC0) +#define GET_32KXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC4U)) // (0x3FCC4) + +#define XO_SLAVE_EN (1) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll0_Freq; +static uint32_t s_Pll1_Freq; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void); +/* Get postdivider (P) from PLL1 PDEC setting. */ +static uint32_t findPll1PostDiv(void); +/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ +static float findPll0MMult(void); +/* Get multiplier (M) from PLL1 MDEC. */ +static uint32_t findPll1MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); +/* Update local PLL1 rate variable */ +static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup); +/* Compensate for discontinuity in the capacitor banks */ +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); +/* Enables and sets LDO for High Frequency crystal oscillator */ +static void CLOCK_SetXtalHfLdo(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint16_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = (uint16_t)GET_ID_ITEM_MUX(item); + sel = (uint8_t)GET_ID_ITEM_SEL(item); + if (mux == CM_RTCOSC32KCLKSEL) + { + PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); + } + else if (mux == CM_OSTIMERCLKSEL) + { + PMC->OSEVENTTIMER = + (PMC->OSEVENTTIMER & ~PMC_OSEVENTTIMER_SELCLOCK_MASK) | PMC_OSEVENTTIMER_SELCLOCK(sel); + } + else + { + ((volatile uint32_t *)pClkSel)[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint16_t mux; + uint32_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = (uint16_t)GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_RTCOSC32KCLKSEL) + { + actualSel = ((PMC->RTCOSC32K) & PMC_RTCOSC32K_SEL_MASK) >> PMC_RTCOSC32K_SEL_SHIFT; + } + else if (mux == CM_OSTIMERCLKSEL) + { + actualSel = ((PMC->OSEVENTTIMER) & PMC_OSEVENTTIMER_SELCLOCK_MASK) >> PMC_OSEVENTTIMER_SELCLOCK_SHIFT; + } + else + { + actualSel = (uint32_t)((volatile uint32_t *)pClkSel)[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) + { + /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ + ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = + SYSCON_FRGCTRL_DIV_MASK | SYSCON_FRGCTRL_MULT(divided_by_value); + } + else + { + if (reset) + { + ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = 1UL << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint16_t)div_name] = (divided_by_value - 1U); + } + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + if ((iFreq != 12000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Enable Analog Control module */ + SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_ANACTRL_RST_MASK; + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; + + /* Initialize FRO192 trim */ + CLOCK_FroHfTrim(); + + /* Power up the FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + + if (iFreq == 96000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); + } + /* always enable + else if (iFreq == 48000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); + }*/ + else + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); + } + return kStatus_Success; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq: Input frequency + * return Nothing + */ +typedef struct +{ + uint32_t waitstate; + uint32_t freqMax; +} WaitStateInterval_t; + +/* clang-format off */ +/* Wait state if frequency is inferior to the one specified */ +static const WaitStateInterval_t IntervalList[] = { + {0, 11000000}, + {1, 22000000}, + {2, 33000000}, + {3, 44000000}, + {4, 55000000}, + {5, 66000000}, + {6, 77000000}, + {7, 88000000}, + {8, 100000000}, + {11, 130000000}, + {12, 150000000} /* Maximum allowed frequency (150 MHz) */ +}; +/* clang-format on */ + +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz) +{ + /* Flash Controller & FMC internal number of Wait States (minus 1) */ + uint32_t num_wait_states = 15UL; /* Default to the maximum number of wait states */ + + for (size_t cnt = 0; cnt < (sizeof(IntervalList) / sizeof(WaitStateInterval_t)); cnt++) + { + if (system_freq_hz <= IntervalList[cnt].freqMax) + { + num_wait_states = IntervalList[cnt].waitstate; + break; + } + } + + FLASH->INTSTAT_CLR = 0xF; /* Clear all status flags */ + + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | (num_wait_states & 0xFUL); + + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + + /* Wait until the cmd is completed (without error) */ + while ((FLASH->INTSTAT & FLASH_INTSTAT_DONE_MASK) == 0UL) + { + } + + /* Adjust FMC waiting time cycles (num_wait_states) */ + SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0FFFUL) | ((num_wait_states & 0xFUL) << 12UL); +} + +/* Set EXT OSC Clk */ +/** + * brief Initialize the external osc clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + if (iFreq >= 32000000U) + { + return kStatus_Fail; + } + /* Turn on power for crystal 32 MHz */ + POWER_DisablePD(kPDRUNCFG_PD_XTALHF); + POWER_DisablePD(kPDRUNCFG_PD_LDOXTALHF); + /* Enable clock_in clock for clock module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; + + s_Ext_Clk_Freq = iFreq; + return kStatus_Success; +} + +/* Set I2S MCLK Clk */ +/** + * brief Initialize the I2S MCLK clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) +{ + s_I2S_Mclk_Freq = iFreq; + return kStatus_Success; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get CAN Clk */ +/*! brief Return Frequency of Can Clock + * return Frequency of Can. + */ +uint32_t CLOCK_GetMCanClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CANCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CANCLKDIV & SYSCON_CANCLKDIV_DIV_MASK) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0) ? (SYSCON->ADC0CLKSEL) : (SYSCON->ADC1CLKSEL)) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + default: + freq = 0U; + break; + } + + div = ((id == 0) ? ((SYSCON->ADC0CLKDIV & SYSCON_ADC0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->ADC1CLKDIV & SYSCON_ADC1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); +} + +/* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); +} + +/* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void) +{ + return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + return s_Pll0_Freq; +} + +/* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + return s_Pll1_Freq; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0UL; +} + +/* Get Flexcomm 32K Clk */ +/*! brief Return Frequency of Flexcomm 32kHz + * return Frequency of Flexcomm 32kHz + */ +uint32_t CLOCK_GetFC32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (SYSCON->FC32KCLKSEL & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + ((SYSCON->FC32KCLKSEL & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0UL; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetFro1MFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + /* Added comments to avoid the violation of MISRA C-2012 rule 15.7 */ + } + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +/* Get PLLClkDiv Clk */ +uint32_t CLOCK_GetPllClkDivFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->PLLCLKDIVSEL) + { + case 0U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); + break; + case 1U: + freq = CLOCK_GetPll1OutFreq() / + ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); // register name should be checked + break; + default: + freq = 0U; + break; + } + /* todo: pll_clk_div = pll_clk/div*/ + return freq; +} + +/* Get FRG Clk */ +uint32_t CLOCK_GetFrgFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FRGCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllClkDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + default: + freq = 0U; + break; + } + return (uint32_t)(((uint64_t)freq * (SYSCON_FRGCTRL_DIV_MASK + 1U)) / + ((SYSCON_FRGCTRL_DIV_MASK + 1U) + + ((SYSCON->FRGCTRL[id] & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT))); +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetFrgFreq(id); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXCOMMCLKDIV[id] & 0xffU) + 1U); +} + +/* Get HS_LPSI Clk */ +uint32_t CLOCK_GetHsLspiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->HSSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLLCLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->CTIMERCLKDIV[id] & 0xffU) + 1U); +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSEL0) + { + case 0U: + /*Niobe4mini just has one SYSTICKSEL and SYSTICKDIV register, Fix coverity problem in this way temporarily + */ + freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[0]) & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get DAC Clk */ +/*! brief Return Frequency of DAC Clock + * return Frequency of DAC. + */ +uint32_t CLOCK_GetDacClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->DAC[id].CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 6U: + freq = CLOCK_GetFro1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->DAC[id].CLKDIV & SYSCON_DAC_CLKDIV_DIV_MASK) + 1U); +} + +/* Get FlexSpi Clk */ +/*! brief Return Frequency of FlexSpi clock + * return Frequency of FlexSpi Clock + */ +uint32_t CLOCK_GetFlexSpiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->FLEXSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXSPICLKDIV & SYSCON_FLEXSPICLKDIV_DIV_MASK) + 1U); +} + +/* Get DMIC Clk */ +/*! brief Return Frequency of DMIC clock + * return Frequency of DMIC Clock + */ +uint32_t CLOCK_GetDmicClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->DMICFCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->DMICFCLKDIV & SYSCON_DMICFCLKDIV_DIV_MASK) + 1U); +} + +/* Get I3C function Clk */ +/*! brief Return Frequency of I3C function clock + * return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->I3CFCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->I3CFCLKDIV & SYSCON_I3CFCLKDIV_DIV_MASK) + 1U); +} + +/* Get I3C function slow TC Clk */ +/*! brief Return Frequency of I3C function Slow TC clock + * return Frequency of I3C function slow TC Clock + */ +uint32_t CLOCK_GetI3cSTCClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->I3CFCLKSTCSEL) + { + case 0U: + freq = CLOCK_GetI3cClkFreq(); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->I3CFCLKSTCDIV & SYSCON_I3CFCLKSTCDIV_DIV_MASK) + 1U); +} + +/* Get I3C function slow Clk */ +/*! brief Return Frequency of I3C function Slow clock + * return Frequency of I3C function slow Clock + */ +uint32_t CLOCK_GetI3cSClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->I3CFCLKSSEL) + { + case 0U: + freq = CLOCK_GetFro1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->I3CFCLKSDIV & SYSCON_I3CFCLKSDIV_DIV_MASK) + 1U); +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_Fro1M: + freq = CLOCK_GetFro1MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0UL; + } + else + { + /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting. */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = + (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get multiplier (M) from PLL1 MDEC. */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1UL; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0UL) + { + mMult = 1UL; + } + + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL0 output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllsscg[1] = + (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0UL; + pllSelI = 0UL; + pllSelP = 0UL; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ + (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ + (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); +} + +/* Update local PLL1 rate variable */ +static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll1_Freq = CLOCK_GetPLL1OutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL0 output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Return PLL1 output clock rate from setup structure */ +/*! brief Return PLL1 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint32_t workRate = 0UL; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL1InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) + { + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = clkRate * findPll1MMult(); + workRate /= postdiv; + } + + return workRate; +} + +/* Set the current PLL0 Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) +{ + s_Pll0_Freq = rate; +} + +/* Return PLL0 output clock rate */ +/*! brief Return PLL0 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL0 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll0_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL0CTRL; + Setup.pllndec = SYSCON->PLL0NDEC; + Setup.pllpdec = SYSCON->PLL0PDEC; + Setup.pllsscg[0] = SYSCON->PLL0SSCG0; + Setup.pllsscg[1] = SYSCON->PLL0SSCG1; + + CLOCK_GetPLL0OutFromSetupUpdate(&Setup); + } + + rate = s_Pll0_Freq; + + return rate; +} + +/*! brief Return PLL1 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL1 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL1OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll1_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL1CTRL; + Setup.pllndec = SYSCON->PLL1NDEC; + Setup.pllpdec = SYSCON->PLL1PDEC; + Setup.pllmdec = SYSCON->PLL1MDEC; + CLOCK_GetPLL1OutFromSetupUpdate(&Setup); + } + + rate = s_Pll1_Freq; + + return rate; +} + +/* Set PLL0 output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0UL) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetPLL0InClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL0 output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + uint32_t inRate, clkRate, prediv; + + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetPLL0OutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0UL) + { + POWER_SetVoltageForFreq(s_Pll0_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL1); + + /* Write PLL setup data */ + SYSCON->PLL1CTRL = pSetup->pllctrl; + SYSCON->PLL1NDEC = pSetup->pllndec; + SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec; + SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec; + SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) + { + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL1Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll1_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set PLL0 clock based on the input frequency and multiplier */ +/*! brief Set PLL0 output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + + selr = 0U; + + if (multiply_by >= 8000UL) + { + seli = 1UL; + } + else if (multiply_by >= 122UL) + { + seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63U) + { + seli = 63U; + } + + { + selp = 31U; + } + + if (pdec > 1U) + { + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + } + + mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); + ndec = 0x1U; /* pre divide by 1 (hardcoded) */ + + SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | + SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | + (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); + SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0SSCG1 = + mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTALHF); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXTALHF); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbd0); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTALHF); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXTALHF); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + + return ret; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + PMC->OSEVENTTIMER |= PMC_OSEVENTTIMER_CLOCKENABLE_MASK; +} + +/* Sets board-specific trim values for High Frequency crystal oscillator */ +/*! brief Sets board-specific trim values for High Frequency crystal oscillator. + * param pi32_hfXtalIecLoadpF_x100 : Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * param pi32_hfXtalPPcbParCappF_x100 : PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * param pi32_hfXtalNPcbParCappF_x100 : PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * return none + * note Following default Values can be used: + * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 + * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + * Sets board-specific trim values for High Frequency crystal oscillator. + */ +void CLOCK_XtalHfCapabankTrim(int32_t pi32_hfXtalIecLoadpF_x100, + int32_t pi32_hfXtalPPcbParCappF_x100, + int32_t pi32_hfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + + /* Enable and set LDO, if not already done */ + CLOCK_SetXtalHfLdo(); + /* Get Cal values from Flash */ + u32XOTrimValue = GET_HFXO_TRIM(); + /* Check validity and apply */ + if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1)) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (u32XOTrimValue >> 1) & 0x7f; + u8IECXinCapCal8pF = (u32XOTrimValue >> 8) & 0x7f; + u8IECXoutCapCal6pF = (u32XOTrimValue >> 16) & 0x7f; + u8IECXoutCapCal8pF = (u32XOTrimValue >> 23) & 0x7f; + /* This field is 1 bit */ + u8XOSlave = (u32XOTrimValue >> 30) & 0x1; + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 20; // gain in LSB/pF + ibXin = -9; // offset in LSB + iaXout_x4 = 20; // gain in LSB/pF + ibXout = -13; // offset in LSB + u8XOSlave = 0; + } + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = + 2 * pi32_hfXtalIecLoadpF_x100 - pi32_hfXtalNPcbParCappF_x100 + 39 * (XO_SLAVE_EN - u8XOSlave) - 15; + iXOCapOutpF_x100 = 2 * pi32_hfXtalIecLoadpF_x100 - pi32_hfXtalPPcbParCappF_x100 - 21; + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400); + u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400); + /* Read register and clear fields to be written */ + u32RegVal = ANACTRL->XO32M_CTRL; + u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); + /* Configuration of 32 MHz XO output buffers */ +#if (XO_SLAVE_EN == 0) + u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); +#else + u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; +#endif + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; + u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; + /* Write back to register */ + ANACTRL->XO32M_CTRL = u32RegVal; +} + +/* Sets board-specific trim values for 32kHz XTAL */ +/*! brief Sets board-specific trim values for 32kHz XTAL. + * param pi32_32kfXtalIecLoadpF_x100 : Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * param pi32_32kfXtalPPcbParCappF_x100 : PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * param pi32_32kfXtalNPcbParCappF_x100 : PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * return none + * note Following default Values can be used: + * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 + * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + * Sets board-specific trim values for 32kHz XTAL. + */ +void CLOCK_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + /* Get Cal values from Flash */ + u32XOTrimValue = GET_32KXO_TRIM(); + /* check validity and apply */ + if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1)) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (u32XOTrimValue >> 1) & 0x7f; + u8IECXinCapCal8pF = (u32XOTrimValue >> 8) & 0x7f; + u8IECXoutCapCal6pF = (u32XOTrimValue >> 16) & 0x7f; + u8IECXoutCapCal8pF = (u32XOTrimValue >> 23) & 0x7f; + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 16; // gain in LSB/pF + ibXin = 12; // offset in LSB + iaXout_x4 = 16; // gain in LSB/pF + ibXout = 11; // offset in LSB + } + + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; + iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; + + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400); + u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400); + + /* Read register and clear fields to be written */ + u32RegVal = PMC->XTAL32K; + u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); + + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; + u32RegVal |= CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; + + /* Write back to register */ + PMC->XTAL32K = u32RegVal; +} + +/* Enables and sets LDO for High Frequency crystal oscillator. */ +/*! brief Enables and sets LDO for High Frequency crystal oscillator. + * return none + * Sets Enables and sets LDO for High Frequency crystal oscillator. + */ +void CLOCK_SetXtalHfLdo(void) +{ + uint32_t temp; + const uint32_t u32Mask = + (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); + + const uint32_t u32Value = + (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); + + /* Enable & set-up XTAL 32 MHz clock LDO */ + temp = ANACTRL->LDO_XO32M; + + if ((temp & u32Mask) != u32Value) + { + temp &= ~u32Mask; + + /* + * Enable the XTAL32M LDO + * Adjust the output voltage level, 0x5 for 1.1V + * Adjust the biasing current, 0x2 value + * Stability configuration, 0x1 default mode + */ + temp |= u32Value; + + ANACTRL->LDO_XO32M = temp; + + /* Delay for LDO to be up */ + // CLOCK_uDelay(20); + } + + /* Enable LDO XO32M */ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK; +} + +/** + * @brief + * @param + * @return + */ +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) +{ + /* Compensate for discontinuity in the capacitor banks */ + if (u8OscCap < 64) + { + if (u8OscCap >= u8CapBankDiscontinuity) + { + u8OscCap -= u8CapBankDiscontinuity; + } + else + { + u8OscCap = 0; + } + } + else + { + if (u8OscCap <= (127 - u8CapBankDiscontinuity)) + { + u8OscCap += u8CapBankDiscontinuity; + } + else + { + u8OscCap = 127; + } + } + return u8OscCap; +} + +/*! + * brief Initialize the trim value for FRO HF . + */ +void CLOCK_FroHfTrim(void) +{ + volatile unsigned int Fro192mCtrlEfuse = 0; + Fro192mCtrlEfuse = ANACTRL->FRO192M_CTRL; + ANACTRL->ANALOG_CTRL_CFG = ANACTRL->ANALOG_CTRL_CFG | ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK; + ANACTRL->FRO192M_CTRL = ANACTRL_FRO192M_CTRL_WRTRIM_MASK | Fro192mCtrlEfuse; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..11e0d51f5d8db375741dcafed97efd6ceb79db87 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_clock.h @@ -0,0 +1,1579 @@ +/* + * Copyright 2017 - 2021 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.3.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } +/*! @brief Clock ip name array for Mailbox. */ +#define MAILBOX_CLOCKS \ + { \ + kCLOCK_Mailbox \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } +/*! @brief Clock ip name array for DAC. */ +#define LPDAC_CLOCKS \ + { \ + kCLOCK_Dac0, kCLOCK_Dac1, kCLOCK_Dac2 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_Ostimer \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct \ + } +/*! @brief Clock ip name array for MCAN. */ +#define MCAN_CLOCKS \ + { \ + kCLOCK_Mcan \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for COMP */ +#define COMP_CLOCKS \ + { \ + kCLOCK_Comp \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for CDOG. */ +#define CDOG_CLOCKS \ + { \ + kCLOCK_Cdog \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for ANALOGCTRL. */ +#define ANALOGCTRL_CLOCKS \ + { \ + kCLOCK_AnalogCtrl \ + } +/*! @brief Clock ip name array for HS_LSPI. */ +#define HS_LSPI_CLOCKS \ + { \ + kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for GPIO_SEC. */ +#define GPIO_SEC_CLOCKS \ + { \ + kCLOCK_Gpio_Sec \ + } +/*! @brief Clock ip name array for GPIO_SEC_INT. */ +#define GPIO_SEC_INT_CLOCKS \ + { \ + kCLOCK_Gpio_Sec_Int \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0 \ + } +/*! @brief Clock ip name array for SYSCTL. */ +#define SYSCTL_CLOCKS \ + { \ + kCLOCK_Sysctl \ + } +/*! @brief Clock ip name array for DMIC. */ +#define DMIC_CLOCKS \ + { \ + kCLOCK_Dmic \ + } +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0}, \ + { \ + kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \ + } \ + } +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_Enc0, kCLOCK_Enc1 \ + } +/*! @brief Clock ip name array for OPAMP. */ +#define OPAMP_CLOCKS \ + { \ + kCLOCK_Opamp0, kCLOCK_Opamp1, kCLOCK_Opamp2 \ + } +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref \ + } +/*! @brief Clock ip name array for FLEXSPI */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_Flexspi \ + } +/*! @brief Clock ip name array for Cache64 */ +#define CACHE64_CLOCKS \ + { \ + kCLOCK_Flexspi \ + } +/*! @brief Clock ip name array for I3C */ +#define I3C_CLOCKS \ + { \ + kCLOCK_I3c0 \ + } +/*! @brief Clock ip name array for HSCMP */ +#define HSCMP_CLOCKS \ + { \ + kCLOCK_Hscmp0, kCLOCK_Hscmp1, kCLOCK_Hscmp2 \ + } +/*! @brief Clock ip name array for PowerQuad. */ +#define POWERQUAD_CLOCKS \ + { \ + kCLOCK_PowerQuad \ + } +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_Aoi0, kCLOCK_Aoi1 \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 +#define AHB_CLK_CTRL3 3 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid IP name. */ + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */ + + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3U), /*!< Clock gate name: Sram1. */ + + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Sram2. */ + + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5U), /*!< Clock gate name: Sram3. */ + + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Sram4. */ + + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Flash. */ + + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8U), /*!< Clock gate name: Fmc. */ + + kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Flexspi. */ + + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11U), /*!< Clock gate name: InputMux. */ + + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Iocon. */ + + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Gpio0. */ + + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Gpio1. */ + + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16U), /*!< Clock gate name: Gpio2. */ + + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Gpio3. */ + + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Pint. */ + + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Gint. */ + + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20U), /*!< Clock gate name: Dma0. */ + + kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21U), /*!< Clock gate name: Crc. */ + + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22U), /*!< Clock gate name: Wwdt. */ + + kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23U), /*!< Clock gate name: Rtc0. */ + + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26U), /*!< Clock gate name: Mailbox. */ + + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27U), /*!< Clock gate name: Adc0. */ + + kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28U), /*!< Clock gate name: Adc1. */ + + kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29U), /*!< Clock gate name: Dac0. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0U), /*!< Clock gate name: Mrt. */ + + kCLOCK_Ostimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1U), /*!< Clock gate name: Ostimer. */ + + kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2U), /*!< Clock gate name: Sct. */ + + kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7U), /*!< Clock gate name: Mcan. */ + + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10U), /*!< Clock gate name: Utick. */ + + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11U), /*!< Clock gate name: FlexComm0. */ + + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12U), /*!< Clock gate name: FlexComm1. */ + + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13U), /*!< Clock gate name: FlexComm2. */ + + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14U), /*!< Clock gate name: FlexComm3. */ + + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15U), /*!< Clock gate name: FlexComm4. */ + + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16U), /*!< Clock gate name: FlexComm5. */ + + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17U), /*!< Clock gate name: FlexComm6. */ + + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18U), /*!< Clock gate name: FlexComm7. */ + + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ + + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ + + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ + + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ + + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ + + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ + + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ + + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ + + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ + + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ + + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ + + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ + + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ + + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ + + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ + + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ + + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ + + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ + + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ + + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ + + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ + + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ + + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ + + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ + + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ + + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ + + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ + + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ + + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ + + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ + + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ + + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ + + kCLOCK_Dmic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19U), /*!< Clock gate name: Dmic. */ + + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22U), /*!< Clock gate name: Timer2. */ + + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25U), /*!< Clock gate name: Usbd0. */ + + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26U), /*!< Clock gate name: Timer0. */ + + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27U), /*!< Clock gate name: Timer1. */ + + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1U), /*!< Clock gate name: Dma1. */ + + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2U), /*!< Clock gate name: Comp. */ + + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8U), /*!< Clock gate name: Freqme. */ + + kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11U), /*!< Clock gate name: Cdog. */ + + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13U), /*!< Clock gate name: Rng. */ + + kCLOCK_Pmux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14U), /*!< Clock gate name: Pmux1. */ + + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15U), /*!< Clock gate name: Sysctl. */ + + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16U), /*!< Clock gate name: Usbhmr0. */ + + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17U), /*!< Clock gate name: Usbhsl0. */ + + kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18U), /*!< Clock gate name: Css. */ + + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19U), /*!< Clock gate name: PowerQuad. */ + + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21U), /*!< Clock gate name: Timer3. */ + + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22U), /*!< Clock gate name: Timer4. */ + + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23U), /*!< Clock gate name: Puf. */ + + kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24U), /*!< Clock gate name: Pkc. */ + + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27U), /*!< Clock gate name: AnalogCtrl. */ + + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28U), /*!< Clock gate name: Lspi. */ + + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29U), /*!< Clock gate name: Sec. */ + + kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30U), /*!< Clock gate name: Int. */ + + kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0U), /*!< Clock gate name: I3c0. */ + + kCLOCK_Enc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3U), /*!< Clock gate name: Enc0. */ + + kCLOCK_Enc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4U), /*!< Clock gate name: Enc1. */ + + kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5U), /*!< Clock gate name: Pwm0. */ + + kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6U), /*!< Clock gate name: Pwm1. */ + + kCLOCK_Aoi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7U), /*!< Clock gate name: Aoi0. */ + + kCLOCK_Aoi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8U), /*!< Clock gate name: Aoi1. */ + + kCLOCK_Ftm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 9U), /*!< Clock gate name: Ftm0. */ + + kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 10U), /*!< Clock gate name: Dac1. */ + + kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11U), /*!< Clock gate name: Dac2. */ + + kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12U), /*!< Clock gate name: Opamp0. */ + + kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13U), /*!< Clock gate name: Opamp1. */ + + kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14U), /*!< Clock gate name: Opamp2. */ + + kCLOCK_Hscmp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15U), /*!< Clock gate name: Hscmp0. */ + + kCLOCK_Hscmp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 16U), /*!< Clock gate name: Hscmp1. */ + + kCLOCK_Hscmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 17U), /*!< Clock gate name: Hscmp2. */ + + kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18U) /*!< Clock gate name: Vref. */ + +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Fro1M, /*!< FRO1M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_PllClkDiv, /*!< PLLCLKDIV clock */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U) +#define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 (0) +#define CM_TRACECLKSEL (2) +#define CM_CTIMERCLKSEL0 (3) +#define CM_CTIMERCLKSEL1 (4) +#define CM_CTIMERCLKSEL2 (5) +#define CM_CTIMERCLKSEL3 (6) +#define CM_CTIMERCLKSEL4 (7) +#define CM_MAINCLKSELA (8) +#define CM_MAINCLKSELB (9) +#define CM_CLKOUTCLKSEL (10) +#define CM_PLL0CLKSEL (12) +#define CM_PLL1CLKSEL (13) +#define CM_MCANCLKSEL (16) +#define CM_ADC0CLKSEL (17) +#define CM_USB0CLKSEL (18) +#define CM_FXCOMCLKSEL0 (20) +#define CM_FXCOMCLKSEL1 (21) +#define CM_FXCOMCLKSEL2 (22) +#define CM_FXCOMCLKSEL3 (23) +#define CM_FXCOMCLKSEL4 (24) +#define CM_FXCOMCLKSEL5 (25) +#define CM_FXCOMCLKSEL6 (26) +#define CM_FXCOMCLKSEL7 (27) +#define CM_HSLSPICLKSEL (28) +#define CM_MCLKCLKSEL (32) +#define CM_SCTCLKSEL (36) + +#define CM_ADC1CLKSEL ((0x464 - 0x260) / 4) +#define CM_DAC0CLKSEL ((0x490 - 0x260) / 4) +#define CM_DAC1CLKSEL ((0x498 - 0x260) / 4) +#define CM_DAC2CLKSEL ((0x4A0 - 0x260) / 4) +#define CM_FLEXSPICLKSEL ((0x4A8 - 0x260) / 4) +#define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4) +#define CM_I3CFCLKSEL ((0x530 - 0x260) / 4) +#define CM_I3CFCLKSTCSEL ((0x534 - 0x260) / 4) +#define CM_I3CFCLKSSEL ((0x534 - 0x260) / 4) +#define CM_DMICFCLKSEL ((0x548 - 0x260) / 4) +#define CM_FC32KCLKSEL ((0x82C - 0x260) / 4) +#define CM_FRGCLKSEL0 ((0x830 - 0x260) / 4) +#define CM_FRGCLKSEL1 ((0x834 - 0x260) / 4) +#define CM_FRGCLKSEL2 ((0x838 - 0x260) / 4) +#define CM_FRGCLKSEL3 ((0x83C - 0x260) / 4) +#define CM_FRGCLKSEL4 ((0x840 - 0x260) / 4) +#define CM_FRGCLKSEL5 ((0x844 - 0x260) / 4) +#define CM_FRGCLKSEL6 ((0x848 - 0x260) / 4) +#define CM_FRGCLKSEL7 ((0x84C - 0x260) / 4) + +#define CM_OSTIMERCLKSEL (252U) +#define CM_RTCOSC32KCLKSEL (253U) + +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ + + kSYSTICK_DIV_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV to SYSTICK0. */ + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + kPLL1_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1 to CTIMER0. */ + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ + kMCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + kPLL1_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1 to CTIMER1. */ + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ + kMCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK_IN to CTIMER1. */ + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + kPLL1_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1 to CTIMER2. */ + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ + kMCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK_IN to CTIMER2. */ + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + kPLL1_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1 to CTIMER3. */ + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ + kMCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK_IN to CTIMER3. */ + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + kPLL1_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1 to CTIMER4. */ + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ + kMCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK_IN to CTIMER4. */ + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to CLKOUT. */ + + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ + + kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */ + kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */ + kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */ + kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */ + + kMAIN_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 0), /*!< Attach MAIN_CLK to ADC0. */ + kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ + kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ + kEXT_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach XO to ADC0. */ + kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ + + kMAIN_CLK_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 0), /*!< Attach MAIN_CLK to ADC1. */ + kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ + kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ + kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ + + kMAIN_CLK_to_USB0 = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0. */ + kPLL0_to_USB0 = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0. */ + kFRO_HF_to_USB0 = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0. */ + kPLL1_to_USB0 = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0. */ + kNONE_to_USB0 = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0. */ + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ + kMAIN_CLK_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 0, 0), /*!< Attach Main clock + to FlexComm0. */ + kPLL_CLK_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm0. */ + kFRO_HF_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm0. */ + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ + kMCLK_IN_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK_IN to FLEXCOMM0. */ + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ + kMAIN_CLK_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 0, 0), /*!< Attach Main clock + to FlexComm1. */ + kPLL_CLK_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm1. */ + kFRO_HF_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm1. */ + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ + kMCLK_IN_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK_IN to FLEXCOMM1. */ + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ + kMAIN_CLK_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 0, 0), /*!< Attach Main clock + to FlexComm2. */ + kPLL_CLK_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm2. */ + kFRO_HF_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm2. */ + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ + kMCLK_IN_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK_IN to FLEXCOMM2. */ + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ + kMAIN_CLK_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 0, 0), /*!< Attach Main clock + to FlexComm3. */ + kPLL_CLK_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm3. */ + kFRO_HF_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm3. */ + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ + kMCLK_IN_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK_IN to FLEXCOMM3. */ + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ + kMAIN_CLK_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 0, 0), /*!< Attach Main clock + to FlexComm4. */ + kPLL_CLK_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm4. */ + kFRO_HF_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm4. */ + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ + kMCLK_IN_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK_IN to FLEXCOMM4. */ + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ + kMAIN_CLK_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 0, 0), /*!< Attach Main clock + to FlexComm5. */ + kPLL_CLK_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm5. */ + kFRO_HF_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm5. */ + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ + kMCLK_IN_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK_IN to FLEXCOMM5. */ + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ + kMAIN_CLK_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 0, 0), /*!< Attach Main clock + to FlexComm6. */ + kPLL_CLK_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm6. */ + kFRO_HF_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 2, 0), /*!< Attach FRO HF DIV + FRG to FlexComm6. */ + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ + kMCLK_IN_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK_IN to FLEXCOMM6. */ + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ + kMAIN_CLK_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 0, 0), /*!< Attach Main clock + to FlexComm7. */ + kPLL_CLK_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 1, 0), /*!< Attach PLL clock + DIV Frg to FlexComm7. */ + kFRO_HF_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 2, 0), /*!< Attach PLL clock + DIV Frg to FlexComm7. */ + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ + kMCLK_IN_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK_IN to FLEXCOMM7. */ + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ + kPLL_CLK_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL_CLK_DIV to HSLSPI. */ + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ + + kMAIN_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT. */ + kPLL0_to_SCT = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT. */ + kEXT_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT. */ + kFRO_HF_to_SCT = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT. */ + kPLL1_to_SCT = MUX_A(CM_SCTCLKSEL, 4), /*!< Attach PLL1 to SCT. */ + kMCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK_IN to SCT. */ + kNONE_to_SCT = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT. */ + + kMAIN_CLK_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 0), /*!< Attach MAIN_CLK to DAC0. */ + kPLL0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 1), /*!< Attach PLL0 to DAC0. */ + kFRO_HF_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 3), /*!< Attach FRO_HF to DAC0. */ + kFRO12M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 4), /*!< Attach FRO12M to DAC0. */ + kPLL1_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 5), /*!< Attach PLL1 to DAC0. */ + kFRO1M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 6), /*!< Attach FRO1M to DAC0. */ + kNONE_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 7), /*!< Attach NONE to DAC0. */ + + kMAIN_CLK_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 0), /*!< Attach MAIN_CLK to DAC1. */ + kPLL0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 1), /*!< Attach PLL0 to DAC1. */ + kFRO_HF_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 3), /*!< Attach FRO_HF to DAC1. */ + kFRO12M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 4), /*!< Attach FRO12M to DAC1. */ + kPLL1_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 5), /*!< Attach PLL1 to DAC1. */ + kFRO1M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 6), /*!< Attach FRO1M to DAC1. */ + kNONE_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 7), /*!< Attach NONE to DAC1. */ + + kMAIN_CLK_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 0), /*!< Attach MAIN_CLK to DAC2. */ + kPLL0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 1), /*!< Attach PLL0 to DAC2. */ + kFRO_HF_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 3), /*!< Attach FRO_HF to DAC2. */ + kFRO12M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 4), /*!< Attach FRO12M to DAC2. */ + kPLL1_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 5), /*!< Attach PLL1 to DAC2. */ + kFRO1M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 6), /*!< Attach FRO1M to DAC2. */ + kNONE_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 7), /*!< Attach NONE to DAC2. */ + + kMAIN_CLK_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 0), /*!< Attach MAIN_CLK to FLEXSPI. */ + kPLL0_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 1), /*!< Attach PLL0 to FLEXSPI. */ + kFRO_HF_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 3), /*!< Attach FRO_HF to FLEXSPI. */ + kPLL1_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 5), /*!< Attach PLL1 to FLEXSPI. */ + kNONE_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 7), /*!< Attach NONE to FLEXSPI. */ + + kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ + kPLL1_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach PLL1 to PLLCLKDIV. */ + kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 7), /*!< Attach NONE to PLLCLKDIV. */ + + kMAIN_CLK_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 0), /*!< Attach MAIN_CLK to I3CFCLK. */ + kFRO_HF_DIV_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 1), /*!< Attach FRO_HF_DIV to I3CFCLK. */ + kNONE_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 7), /*!< Attach NONE to I3CFCLK. */ + + kI3CFCLKSEL_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 0), /*!< Attach I3CFCLKSEL to I3CFCLKSTC. */ + kFRO1M_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 1), /*!< Attach FRO1M to I3CFCLKSTC. */ + kNONE_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 7), /*!< Attach NONE to I3CFCLKSTC. */ + + kMAIN_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 0), /*!< Attach MAIN_CLK to DMIC. */ + kPLL0_to_DMIC = MUX_A(CM_DMICFCLKSEL, 1), /*!< Attach PLL0 to DMIC. */ + kEXT_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), /*!< Attach EXT_CLK to DMIC. */ + kFRO_HF_to_DMIC = MUX_A(CM_DMICFCLKSEL, 3), /*!< Attach FRO_HF to DMIC. */ + kPLL1_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), /*!< Attach PLL1 to DMIC. */ + kMCLK_IN_to_DMIC = MUX_A(CM_DMICFCLKSEL, 5), /*!< Attach MCLK_IN to DMIC. */ + kNONE_to_DMIC = MUX_A(CM_DMICFCLKSEL, 7), /*!< Attach NONE to DMIC. */ + + kFRO32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 0), /*!< Attach FRO32K to FCOSC32K. */ + kXTAL32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 1), /*!< Attach XTAL32K to FCOSC32K. */ + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ + kFRO32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 0), /*!< Attach FRO32K to FC32K. */ + kXTAL32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 1), /*!< Attach XTAL32K to FC32K. */ + + kFRO32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach FRO32K to OSTIMER. */ + kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach OSC32K to OSTIMER. */ + kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach FRO1M to OSTIMER. */ + kAHB_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach AHB_CLK to OSTIMER. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/* Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk = (0), /*!< Systick Clock Divider. */ + kCLOCK_DivArmTrClkDiv = ((0x308 - 0x300) / 4), /*!< Trace Clock Divider. */ + kCLOCK_DivCanClk = ((0x30C - 0x300) / 4), /*!< Can Clock Divider. */ + kCLOCK_DivFlexFrg0 = ((0x320 - 0x300) / 4), /*!< FRGCTRL0 register. */ + kCLOCK_DivFlexFrg1 = ((0x324 - 0x300) / 4), /*!< FRGCTRL1 register. */ + kCLOCK_DivFlexFrg2 = ((0x328 - 0x300) / 4), /*!< FRGCTRL2 register. */ + kCLOCK_DivFlexFrg3 = ((0x32C - 0x300) / 4), /*!< FRGCTRL3 register. */ + kCLOCK_DivFlexFrg4 = ((0x330 - 0x300) / 4), /*!< FRGCTRL4 register. */ + kCLOCK_DivFlexFrg5 = ((0x334 - 0x300) / 4), /*!< FRGCTRL5 register. */ + kCLOCK_DivFlexFrg6 = ((0x338 - 0x300) / 4), /*!< FRGCTRL6 register. */ + kCLOCK_DivFlexFrg7 = ((0x33C - 0x300) / 4), /*!< FRGCTRL7 register. */ + kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clock Divider. */ + kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< Clk Out Divider. */ + kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Divider. */ + kCLOCK_DivWdtClk = ((0x38C - 0x300) / 4), /*!< Wdt Clock Divider. */ + kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clock Divider. */ + kCLOCK_DivUsb0Clk = ((0x398 - 0x300) / 4), /*!< Usb0 Clock Divider. */ + kCLOCK_DivMclk = ((0x3AC - 0x300) / 4), /*!< Mclk Divider. */ + kCLOCK_DivSctClk = ((0x3B4 - 0x300) / 4), /*!< Sct Clock Divider. */ + kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll0 Clock Divider. */ + kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clock Divider. */ + kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clock Divider. */ + kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clock Divider. */ + kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clock Divider. */ + kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clock Divider. */ + kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clock Divider. */ + kCLOCK_DivDac0Clk = ((0x494 - 0x300) / 4), /*!< Dac0 Clock Divider. */ + kCLOCK_DivDac1Clk = ((0x49C - 0x300) / 4), /*!< Dac1 Clock Divider. */ + kCLOCK_DivDac2Clk = ((0x4A4 - 0x300) / 4), /*!< Dac2 Clock Divider. */ + kCLOCK_DivFlexSpiClk = ((0x4AC - 0x300) / 4), /*!< Flex Spi Clock Divider. */ + kCLOCK_DivI3cFclkStc = ((0x538 - 0x300) / 4), /*!< I3c Fclk Stc Divider. */ + kCLOCK_DivI3cFclkS = ((0x53C - 0x300) / 4), /*!< I3c Fclk S Divider. */ + kCLOCK_DivI3cFclk = ((0x540 - 0x300) / 4), /*!< I3c Fclk Divider. */ + kCLOCK_DivDmicClk = ((0x54C - 0x300) / 4), /*!< Dmic Clock Divider. */ + kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clock Divider. */ + kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clock Divider. */ + kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clock Divider. */ + kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clock Divider. */ + kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clock Divider. */ + kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clock Divider. */ + kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clock Divider. */ + kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clock Divider. */ +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Set the flash wait states for the input freuqency. + * @param system_freq_hz : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz); +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the I2S MCLK clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Initialize the PLU CLKIN clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of FRO 1MHz + * @return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Can Clock + * @return Frequency of Can. + */ +uint32_t CLOCK_GetMCanClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); +/*! @brief Return Frequency of PLL_CLK_DIV + * @return Frequency of PLL_CLK_DIV + */ +uint32_t CLOCK_GetPllClkDivFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Flexcomm 32kHz osc + * @return Frequency of Flexcomm 32kHz osc + */ +uint32_t CLOCK_GetFC32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of FRG Clock + * @return Frequency of FRG Clock + */ +uint32_t CLOCK_GetFrgFreq(uint32_t id); +/*! @brief Return Frequency of FlexComm Clock + * @return Frequency of FlexComm Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of High speed SPI Clock + * @return Frequency of High speed SPI Clock + */ +uint32_t CLOCK_GetHsLspiClkFreq(void); +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); +/*! @brief Return Frequency of SystickClock + * @return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(void); + +/*! @brief Return Frequency of FlexSPI + * @return Frequency of FlexSPI Clock + */ +uint32_t CLOCK_GetFlexSpiClkFreq(void); + +/*! @brief Return Frequency of DMIC + * @return Frequency of DMIC Clock + */ +uint32_t CLOCK_GetDmicClkFreq(void); + +/*! @brief Return Frequency of DAC Clock + * @return Frequency of DAC Clock + */ +uint32_t CLOCK_GetDacClkFreq(uint32_t id); +/*! @brief Return Frequency of I3C function slow TC Clock + * @return Frequency of I3C function slow TC Clock + */ +uint32_t CLOCK_GetI3cSTCClkFreq(void); +/*! @brief Return Frequency of I3C function slow Clock + * @return Frequency of I3C function slow Clock + */ +uint32_t CLOCK_GetI3cSClkFreq(void); +/*! @brief Return Frequency of I3C function Clock + * @return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(void); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Return PLL0 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL0 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); + +/*! @brief Return PLL1 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL1 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); + +/*! @brief Enables and disables PLL0 bypass mode + * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass + * @return PLL0 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) +{ + if (bypass) + { + SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Enables and disables PLL1 bypass mode + * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass + * @return PLL1 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) +{ + if (bypass) + { + SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Store the current PLL0 rate + * @param rate: Current rate of the PLL0 + * @return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_RECC = (2 << 26), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ + uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ + uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ + uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB FS clock source definition. */ +typedef enum _clock_usbfs_src +{ + kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ + kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ + kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ + + kCLOCK_UsbfsSrcNone = + SYSCON_USB0CLKSEL_SEL(7) /*!COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | + PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); + + if (true == config->enableLowPower) + { + tmpReg |= PMC_COMP_LOWPOWER_MASK; + } + else + { + tmpReg &= ~PMC_COMP_LOWPOWER_MASK; + } + + if (true == config->enableHysteresis) + { + tmpReg |= PMC_COMP_HYST_MASK; + } + else + { + tmpReg &= ~PMC_COMP_HYST_MASK; + } + + tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | + PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); + + PMC->COMP = tmpReg; +} + +/*! + * @brief CMP deinitialization. + * + * This function gates the clock for CMP module. + */ +void CMP_Deinit(void) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Comp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * @code + * config->enableHysteresis = true; + * config->enableLowPower = true; + * config->filterClockDivider = kCMP_FilterClockDivide1; + * config->filterSampleMode = kCMP_FilterSampleMode0; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableHysteresis = true; + config->enableLowPower = true; + config->filterClockDivider = kCMP_FilterClockDivide1; + config->filterSampleMode = kCMP_FilterSampleMode0; +} + +/*! + * @brief Configures the VREFINPUT. + * + * @param config Pointer to the configuration structure. + */ +void CMP_SetVREF(const cmp_vref_config_t *config) +{ + assert(NULL != config); + assert(config->vrefValue < 32U); + + uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); + + tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); + + PMC->COMP = tmpReg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cmp.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cmp.h new file mode 100644 index 0000000000000000000000000000000000000000..1afdc9728088a2924735454222a81b0bd453a4d8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_cmp.h @@ -0,0 +1,291 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_CMP_H_ +#define __FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp_1 + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.2.1. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) +/*@}*/ + +/*! @brief CMP input mux for positive and negative sides. */ +enum _cmp_input_mux +{ + kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ + kCMP_Input1 = 1U, /*!< Cmp input source 1. */ + kCMP_Input2 = 2U, /*!< Cmp input source 2. */ + kCMP_Input3 = 3U, /*!< Cmp input source 3. */ + kCMP_Input4 = 4U, /*!< Cmp input source 4. */ + kCMP_Input5 = 5U, /*!< Cmp input source 5. */ +}; + +/*! @brief CMP interrupt type. */ +enum _cmp_interrupt_type +{ + kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ + kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ + kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ + kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ + + kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ + kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ + kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ +}; + +/*! @brief CMP Voltage Reference source. */ +typedef enum _cmp_vref_source +{ + KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ + KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ +} cmp_vref_source_t; + +typedef struct _cmp_vref_config +{ + cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ + uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ +} cmp_vref_config_t; + +/*! @brief CMP Filter sample mode. */ +typedef enum _cmp_filtercgf_samplemode +{ + kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ + kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ + kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ + kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ +} cmp_filtercgf_samplemode_t; + +/*! @brief CMP Filter clock divider. */ +typedef enum _cmp_filtercgf_clkdiv +{ + kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ + kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ + kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ + kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ + kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ + kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ + kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ +} cmp_filtercgf_clkdiv_t; + +/*! @brief CMP configuration structure. */ +typedef struct _cmp_config +{ + bool enableHysteresis; /*!< Enable hysteresis. */ + bool enableLowPower; /*!< Enable low power mode. */ + cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock + divided by 2^FILTERCGF_CLKDIV. */ + cmp_filtercgf_samplemode_t + filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ +} cmp_config_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief CMP initialization. + * + * This function enables the CMP module and do necessary settings. + * + * @param config Pointer to the configuration structure. + */ +void CMP_Init(const cmp_config_t *config); + +/*! + * @brief CMP deinitialization. + * + * This function gates the clock for CMP module. + */ +void CMP_Deinit(void); + +/*! + * @brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * @code + * config->enableHysteresis = true; + * config->enableLowPower = true; + * config->filterClockDivider = kCMP_FilterClockDivide1; + * config->filterSampleMode = kCMP_FilterSampleMode0; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/* @} */ + +/*! + * @name Compare Interface + * @{ + */ + +/* + * @brief Set the input channels for the comparator. + * + * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". + * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". + */ +static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) +{ + PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); + PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); +} + +/*! + * @brief Configures the VREFINPUT. + * + * @param config Pointer to the configuration structure. + */ +void CMP_SetVREF(const cmp_vref_config_t *config); + +/*! + * @brief Get CMP compare output. + * + * @return The output result. true: voltage on positive side is greater than negative side. + * false: voltage on positive side is lower than negative side. + */ +static inline bool CMP_GetOutput(void) +{ + return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); +} + +/* @} */ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief CMP enable interrupt. + * + * @param type CMP interrupt type. See "_cmp_interrupt_type". + */ +static inline void CMP_EnableInterrupt(uint32_t type) +{ + SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); +} + +/*! + * @brief CMP disable interrupt. + * + */ +static inline void CMP_DisableInterrupt(void) +{ + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; +} + +/*! + * @brief CMP clear interrupt. + * + */ +static inline void CMP_ClearInterrupt(void) +{ + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; +} + +/*! + * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. + * + * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. + * true: Select Analog Comparator filtered output as input for interrupt detection. + * + * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the + * interupt source, that is, call this function and set parameter enable to false. + */ +static inline void CMP_EnableFilteredInterruptSource(bool enable) +{ + if (enable) + { + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } + else + { + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } +} +/* @} */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get CMP interrupt status before interupt enable. + * + * @return Interrupt status. true: interrupt pending, + * false: no interrupt pending. + */ +static inline bool CMP_GetPreviousInterruptStatus(void) +{ + return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); +} + +/*! + * @brief Get CMP interrupt status after interupt enable. + * + * @return Interrupt status. true: interrupt pending, + * false: no interrupt pending. + */ +static inline bool CMP_GetInterruptStatus(void) +{ + return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); +} +/* @} */ + +/*! + * @name Filter Interface + * @{ + */ + +/*! + * @brief CMP Filter Sample Config. + * + * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. + * + * @param filterSampleMode CMP Select filter sample mode + * @param filterClockDivider CMP Set fileter clock divider + */ +static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, + cmp_filtercgf_clkdiv_t filterClockDivider) +{ + uint32_t comp = PMC->COMP; + + comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); + comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | + ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); + + PMC->COMP = comp; +} +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ +#endif /* __FSL_CMP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.c new file mode 100644 index 0000000000000000000000000000000000000000..8b17fc366844bd37146d7e98a542f6b2348676e9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc(alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.h new file mode 100644 index 0000000000000000000000000000000000000000..ff075086c8a9239e533a20222111cfd8fda0d937 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ + kStatusGroup_IPED = 158, /*!< Group number for IPED status codes. */ + kStatusGroup_CSS_PKC = 159, /*!< Group number for CSS PKC status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); + +/*! +* @brief Delay at least for some time. +* Please note that, this API uses while loop for delay, different run-time environments make the time not precise, +* if precise delay count was needed, please implement a new delay function with hardware timer. +* +* @param delayTime_us Delay time in unit of microsecond. +* @param coreClock_Hz Core clock frequency with Hz. +*/ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XCC__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.c new file mode 100644 index 0000000000000000000000000000000000000000..e77a265ce43f868c03b1e621e4100e09f97ec782 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +/* Use WDT. */ +static void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +static uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.h new file mode 100644 index 0000000000000000000000000000000000000000..8b28aa888715b2fdd074d510037b8d71fc65188b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_common_arm.h @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_ARM_H_ +#define _FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile uint8_t*)(volatile void*)(addr), (val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t*)(volatile void*)(addr), (val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void*)(addr), (val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t*)(volatile void*)(addr), (clearBits), (setBits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t*)(volatile void*)(addr), (clearBits), (setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void*)(addr), (clearBits), (setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) +_Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if(defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/* @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ + +#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ + +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func + +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..037dd41689c214c74f6fe4ed07b70dafeeb30f90 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.crc" +#endif + +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! + * @brief CRC module configuration. + * + * This structure holds the configuration for the CRC module. + */ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0U | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + CRC_SetProtocolConfig(base, config); + } + else + { + CRC_SetRawProtocolConfig(base, config); + } +} + +/*! + * brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * endcode + * + * param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)(uint32_t)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize != 0U) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +/*! + * brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +/*! + * brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..04270b83dc301d87f5fb6d74baba82f79f441905 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_crc.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.3. + * + * Current version: 2.0.3 + * + * Change log: + * + * - Version 2.0.3 + * - Fix MISRA issues + * + * - Version 2.0.2 + * - Fix MISRA issues + * + * - Version 2.0.1 + * - move DATA and DATALL macro definition from header file to source file + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! + * @brief CRC protocol configuration. + * + * This structure holds the configuration for the CRC protocol. + * + */ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This function disables the clock gate in the SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base); + +/*! + * @brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.c new file mode 100644 index 0000000000000000000000000000000000000000..d15e5b66a99b612cfcd38498c9783de68d5fbaf9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.c @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for PWM pulse channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.h new file mode 100644 index 0000000000000000000000000000000000000000..e3a7d922a2b2688900c2f3a6b20f38a8f23f8048 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ctimer.h @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ +} ctimer_external_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..63ebc8c5683f8ae8cb00772ec5c2361143805213 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dac.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dac_1" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DAC module. + * + * @param base DAC peripheral base address + */ +static uint32_t DAC_GetInstance(LPDAC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DAC bases for each instance. */ +static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to DAC clocks for each instance. */ +static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DAC_GetInstance(LPDAC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++) + { + if (s_dacBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dacBases)); + + return instance; +} + +/*! + * brief Initialize the DAC module with common configuartion. + * + * The clock will be enabled in this function. + * + * param base DAC peripheral base address. + * param config Pointer to configuration structure. + */ +void DAC_Init(LPDAC_Type *base, const dac_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the logic. */ + DAC_SetReset(base, kDAC_ResetLogic); + DAC_ClearReset(base, kDAC_ResetLogic); + + /* Reset the FIFO. */ + DAC_SetReset(base, kDAC_ResetFIFO); + DAC_ClearReset(base, kDAC_ResetFIFO); + + /* Configuration. */ + if (kDAC_FIFOTriggerBySoftwareMode == config->fifoTriggerMode) + { + tmp32 |= LPDAC_GCR_TRGSEL_MASK; /* Software trigger. */ + } + switch (config->fifoWorkMode) + { + case kDAC_FIFOWorkAsNormalMode: /* Normal FIFO. */ + tmp32 |= LPDAC_GCR_FIFOEN_MASK; + break; + case kDAC_FIFOWorkAsSwingMode: + tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_SWMD_MASK; /* Enable swing mode. */ + break; +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + case kDAC_FIFOWorkAsPeriodTriggerMode: + tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK; /* Enable period trigger mode. */ + /* Set trigger number and width. */ + base->PCR = + LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth); + break; + case kDAC_FIFOWorkAsPeriodTriggerAndSwingMode: + tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK | LPDAC_GCR_SWMD_MASK; + /* Set trigger number and width. */ + base->PCR = + LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth); + break; +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ + default: /* kDAC_FIFODisabled. */ + break; + } + +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG + if (config->enableExternalTriggerSource) + { + tmp32 |= LPDAC_GCR_RCV_TRG_MASK; /* Use trigger source from another DAC. */ + } +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL + if (false == config->enableLowerLowPowerMode) + { + tmp32 |= LPDAC_GCR_BUF_SPD_CTRL_MASK; /* Enable low power. */ + } +#else + if (config->enableLowPowerMode) + { + tmp32 |= LPDAC_GCR_LPEN_MASK; /* Enable low power. */ + } +#endif /* LPDAC_GCR_BUF_SPD_CTRL_MASK */ + +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN + tmp32 |= LPDAC_GCR_BUF_EN_MASK; /* Opamp is used as buffer. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC + /* Configure DAC sync cycles. */ + tmp32 |= LPDAC_GCR_LATCH_CYC(config->syncTime); +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT + tmp32 |= config->referenceCurrentSource; +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + /* Set reference voltage source. */ + tmp32 |= LPDAC_GCR_DACRFS(config->referenceVoltageSource); + + base->GCR = tmp32; + base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel); + + /* Now, the DAC is disabled. It needs to be enabled in application. */ +} + +/*! + * brief Get the default settings for initialization's configuration. + * + * This function initializes the user configuration structure to a default value. The default values are: + * code + * config->fifoWatermarkLevel = 0U; + * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; + * config->fifoWorkMode = kDAC_FIFODisabled; + * config->enableLowPowerMode = false; + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; + * endcode + * + * param config Pointer to configuration structure. + * param + */ +void DAC_GetDefaultConfig(dac_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->fifoWatermarkLevel = 0U; + config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; + config->fifoWorkMode = kDAC_FIFODisabled; + +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG + config->enableExternalTriggerSource = false; +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL + config->enableLowerLowPowerMode = true; +#else + config->enableLowPowerMode = false; +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + config->periodicTriggerNumber = 0UL; + config->periodicTriggerWidth = 0UL; +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC + /* Configure DAC sync cycles. */ + config->syncTime = 1U; +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT + config->referenceCurrentSource = kDAC_ReferenceCurrentSourcePtat; +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; +} + +/*! + * brief De-initialize the DAC module. + * + * The clock will be disabled in this function. + * + * param base DAC peripheral base address. + * param + */ +void DAC_Deinit(LPDAC_Type *base) +{ + /* Disable the module. */ + DAC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..3241e08cb61a9ff5307ca6d853e03a7a35510915 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dac.h @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DAC_H_ +#define _FSL_DAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dac + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DAC driver version 2.1.0. */ +#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! + * @brief DAC reset control. + */ +enum +{ + kDAC_ResetFIFO = LPDAC_RCR_FIFORST_MASK, /*!< Resets the FIFO pointers and flags. */ + kDAC_ResetLogic = LPDAC_RCR_SWRST_MASK, /*!< Resets all DAC registers and internal logic. */ +}; + +/*! + * @brief DAC interrupts. + */ +enum +{ + kDAC_FIFOFullInterruptEnable = LPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */ + kDAC_FIFOEmptyInterruptEnable = LPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */ + kDAC_FIFOWatermarkInterruptEnable = LPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */ + kDAC_SwingBackInterruptEnable = LPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */ + kDAC_FIFOOverflowInterruptEnable = LPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */ + kDAC_FIFOUnderflowInterruptEnable = LPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + kDAC_PeriodTriggerCompleteInterruptEnable = + LPDAC_IER_PTGCOCO_IE_MASK, /*!< Period trigger mode conversion complete interrupt enable */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +}; + +/*! + * @brief DAC DMA switchers. + */ +enum +{ + kDAC_FIFOEmptyDMAEnable = LPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */ + kDAC_FIFOWatermarkDMAEnable = LPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */ +}; + +/*! + * @brief DAC status flags. + */ +enum +{ + kDAC_FIFOUnderflowFlag = LPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is +empty. The FIFO read pointer will not +increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1 +to it. */ + + kDAC_FIFOOverflowFlag = + LPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the +buffer is full. The writer pointer will +not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it. +*/ + + kDAC_FIFOSwingBackFlag = LPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of +conversion in swing back mode. It means +that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For +example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the +read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is +cleared by writing a 1 to it. */ + + kDAC_FIFOWatermarkFlag = LPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or + equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is + cleared automatically when the data in FIFO is more than the setting value of watermark. */ + + kDAC_FIFOEmptyFlag = LPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag. */ + kDAC_FIFOFullFlag = LPDAC_FSR_FULL_MASK, /*!< FIFO full flag. */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + kDAC_PeriodTriggerCompleteFlag = LPDAC_FSR_PTGCOCO_MASK, /*!< Period trigger mode conversion complete flag. */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +}; + +/*! + * @brief DAC FIFO trigger mode. + */ +typedef enum _dac_fifo_trigger_mode +{ + kDAC_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ + kDAC_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ +} dac_fifo_trigger_mode_t; + +/*! + * @brief DAC FIFO work mode. + */ +typedef enum _dac_fifo_work_mode +{ + kDAC_FIFODisabled = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes + to buffer then goes to conversion. */ + kDAC_FIFOWorkAsNormalMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to + conversion. */ + kDAC_FIFOWorkAsSwingMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That + is, the trigger increases the read pointer till reach the writer pointer and + decreases the read pointer till zero, and so on. The FIFO empty/full/watermark + flag will not update during swing back mode. */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + kDAC_FIFOWorkAsPeriodTriggerMode = + 3U, /*!< In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1] + RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal + triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can + terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion + is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero, + there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is + cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST. */ + kDAC_FIFOWorkAsPeriodTriggerAndSwingMode = 4U, /*!< Periodically trigger DAC and swing back. */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +} dac_fifo_work_mode_t; + +/*! + * @brief DAC reference voltage source. + */ +typedef enum _dac_reference_voltage_source +{ +#if defined(FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC) && (FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC == 3) + kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VDD_ANA as the reference voltage. */ + kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREF_OUT as the reference voltage. */ + kDAC_ReferenceVoltageSourceAlt3 = 2U, /*!< THe DAC selects VREFH as the reference voltage. */ +#else + kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VREFH_INT as the reference voltage. */ + kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREFH_EXT as the reference voltage. */ +#endif /* FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC */ +} dac_reference_voltage_source_t; + +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT +/* + * @brief DAC internal reference current source + */ +typedef enum _dac_reference_current_source +{ + kDAC_ReferenceCurrentSourcePtat = LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK, /* Internal PTAT Current Reference selected */ + kDAC_ReferenceCurrentSourceZtc = LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK, /* Internal ZTC Current Reference selected */ +} dac_reference_current_source_t; +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + +/*! + * @brief DAC configuration structure. + */ +typedef struct _dac_config +{ + uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ + dac_fifo_trigger_mode_t fifoTriggerMode; /*!< Select the trigger mode for FIFO. */ + dac_fifo_work_mode_t fifoWorkMode; /*!< Select the work mode for FIFO. */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN + bool enableOpampBuffer; /*!< Opamp is used as buffer. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG + bool enableExternalTriggerSource; /* DAC uses another DAC's hardware/software trigger as its trigger source. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL + bool enableLowerLowPowerMode; /*!< Enable the lower low power mode. */ +#else + bool enableLowPowerMode; /*!< Enable the low power mode. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + uint32_t periodicTriggerNumber; /*!< There will be 'periodicTriggerNumber' internal triggers following the first + hardware/software trigger. So there will be 'periodicTriggerNumber + 1' + conversions in total. If set to zero, there will be infinite triggers following + the first hw/sw trigger, until the GCR[PTGEN] is cleared. */ + uint32_t periodicTriggerWidth; /*!< Control the periodic trigger frequency. There will be 'periodicTriggerWidth + 1' + RCLK cycles between each periodic trigger. The periodic trigger frequency should + be configured to not larger than the analog conversion speed. */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC + uint32_t syncTime; /*!< RCLK cycles before data latch. accessible range is 0-15. It is used to configure the DAC + sync cycles which is helpful to reduce glitch on the output. The sync time is (LATCH_CYC+1) + RCLK cycles. User should configure this register according to the RCLK frequency. The + recommended sync time is at least 40ns.*/ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT + dac_reference_current_source_t referenceCurrentSource; /*!< Select the internal reference current source. */ +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ +} dac_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief Initialize the DAC module with common configuartion. + * + * The clock will be enabled in this function. + * + * @param base DAC peripheral base address. + * @param config Pointer to configuration structure. + */ +void DAC_Init(LPDAC_Type *base, const dac_config_t *config); + +/*! + * @brief Get the default settings for initialization's configuration. + * + * This function initializes the user configuration structure to a default value. The default values are: + * @code + * config->fifoWatermarkLevel = 0U; + * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; + * config->fifoWorkMode = kDAC_FIFODisabled; + * config->enableLowPowerMode = false; + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; + * @endcode + * + * @param config Pointer to configuration structure. + */ +void DAC_GetDefaultConfig(dac_config_t *config); + +/*! + * @brief De-initialize the DAC module. + * + * The clock will be disabled in this function. + * + * @param base DAC peripheral base address. + */ +void DAC_Deinit(LPDAC_Type *base); + +/*! + * @brief Assert the reset control to part hardware. + * + * This function is to assert the reset control to part hardware. Responding part hardware would remain reset untill + * cleared by software. + * + * @param base DAC peripheral base address. + * @param mask The reset control mask, see to _dac_reset_control_t. + */ +static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask) +{ + base->RCR |= mask; +} + +/*! + * @brief Clear the reset control to part hardware. + * + * This function is to clear the reset control to part hardware. Responding part hardware would work after the reset + * control is cleared by software. + * + * @param base DAC peripheral base address. + * @param mask The reset control mask, see to _dac_reset_control_t. + */ +static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask) +{ + base->RCR &= ~mask; +} + +/*! + * @brief Enable the DAC hardware system or not. + * + * This function is to start the Programmable Reference Generator operation or not. + * + * @param base DAC peripheral base address. + * @param enable Assertion of indicated event. + */ +static inline void DAC_Enable(LPDAC_Type *base, bool enable) +{ + if (enable) + { + base->GCR |= LPDAC_GCR_DACEN_MASK; + } + else + { + base->GCR &= ~LPDAC_GCR_DACEN_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base DAC peripheral base address. + * @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable. + */ +static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disable the interrupts. + * + * @param base DAC peripheral base address. + * @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable. + */ +static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/* @} */ + +/*! + * @name DMA control + * @{ + */ + +/*! + * @brief Enable the DMA switchers or not. + * + * @param base DAC peripheral base address. + * @param mask Mask value of indicated DMA requeset. See to _dac_dma_enable. + * @param enable Enable the DMA or not. + */ +static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->DER |= mask; + } + else + { + base->DER &= ~mask; + } +} + +/* @} */ + +/*! + * @name Status flags + * @{ + */ + +/*! + * @brief Get status flags of DAC module. + * + * @param base DAC peripheral base address. + * @return Mask value of status flags. See to _dac_status_flags. + */ +static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base) +{ + return base->FSR; +} + +/*! + * @brief Clear status flags of DAC module. + * + * @param base DAC peripheral base address. + * @param flags Mask value of status flags to be cleared. See to _dac_status_flags. + */ +static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags) +{ + base->FSR = flags; +} + +/* @} */ + +/*! + * @name Functional feature + * @{ + */ + +/*! + * @brief Set data into the entry of FIFO buffer. + * + * @param base DAC peripheral base address. + * @param value Setting value into FIFO buffer. + */ +static inline void DAC_SetData(LPDAC_Type *base, uint32_t value) +{ + base->DATA = LPDAC_DATA_DATA(value); +} + +/*! + * @brief Get the value of the FIFO write pointer. + * + * @param base DAC peripheral base address. + * @return Current value of the FIFO write pointer. + */ + +static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base) +{ + return (LPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_WPT_SHIFT; +} + +/*! + * @brief Get the value of the FIFO read pointer. + * + * @param base DAC peripheral base address. + * @return Current value of the FIFO read pointer. + */ + +static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base) +{ + return (LPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_RPT_SHIFT; +} + +/*! + * @brief Do software trigger to FIFO when in software mode. + * + * @param base DAC peripheral base address. + */ + +static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base) +{ + base->TCR = LPDAC_TCR_SWTRG_MASK; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _FSL_DAC12_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..c0664e4b5c7d24565467fa6cb5de310961ae05a3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.c @@ -0,0 +1,1074 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) +#include "fsl_memory.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetInstance(DMA_Type *base); + +/*! + * @brief Get virtual channel number. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) +/*! @brief Pointers to DMA resets for each instance. */ +static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; +#endif /*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; + +/*! @brief DMA driver internal descriptor table */ +#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); +#else +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#else +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ +#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ + +#if defined(DMA1) +#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); +#else +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#else +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ +#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; +#else +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t DMA_GetInstance(DMA_Type *base) +{ + uint32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + + return instance; +} + +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) +{ + uint32_t startChannel = 0, instance = 0; + uint32_t i = 0; + + instance = DMA_GetInstance(base); + + /* Compute start channel */ + for (i = 0; i < instance; i++) + { + startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + } + + return startChannel; +} + +/*! + * brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base) +{ + uint32_t instance = DMA_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable dma clock gate */ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) + /* Reset the DMA module */ + RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); +#endif + /* set descriptor table */ +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); +#else + base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; +#endif + /* enable dma peripheral */ + base->CTRL |= DMA_CTRL_ENABLE_MASK; +} + +/*! + * brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base) +{ + /* Disable DMA peripheral */ + base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Set trigger settings of DMA channel. + * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) +{ + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); + + uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmpReg; +} + +/*! + * brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + * impossible to distinguish between: + * - transfer finishes (represented by value '0x3FF') + * - and remaining 1024 bytes to transfer (value 0x3FF) + * for all descriptor in chain, except the last one. + * If you decide to use this function, please use 1023 transfers as maximal value */ + + /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ + if ((!DMA_ChannelIsActive(base, channel)) && + (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + { + return 0UL; + } + + return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + + 1UL; +} + +/* Verify and convert dma_xfercfg_t to XFERCFG register */ +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) +{ + assert(xfercfg != NULL); + /* check source increment */ + assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && + (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); + /* check data width */ + assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); + /* check transfer count */ + assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); + + uint32_t xfer = 0; + + /* set valid flag - descriptor is ready now */ + xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); + /* set reload - allow link to next descriptor */ + xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); + /* set swtrig flag - start transfer */ + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); + /* set INTA */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); + /* set INTB */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); + /* set data width */ + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); + /* set source increment value */ + xfer |= DMA_CHANNEL_XFERCFG_SRCINC( + (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); + /* set destination increment value */ + xfer |= DMA_CHANNEL_XFERCFG_DSTINC( + (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); + + /* store xferCFG */ + *xfercfg_addr = xfer; +} + +/*! + * brief setup dma descriptor + * Note: This function do not support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) + { + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } +} + +/*! + * brief setup dma channel descriptor + * Note: This function support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + * param wrapType burst wrap type. + * param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) + { + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + + if (wrapType == kDMA_NoWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ + if (wrapType == kDMA_SrcWrap) + { + desc->srcEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + if (wrapType == kDMA_DstWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); + } + if (wrapType == kDMA_SrcAndDstWrap) + { + desc->srcEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); + } + + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } +} + +/*! + * brief Create application specific DMA descriptor + * to be used in a chain in transfer + * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcAddr Address of last item to transmit + * param dstAddr Address of last item to receive. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); + + uint32_t xfercfg_reg = 0; + + DMA_SetupXferCFG(xfercfg, &xfercfg_reg); + + /* Set descriptor structure */ + DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); +} + +/*! + * brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + DMA_DisableChannel(handle->base, handle->channel); + while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & + (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) + { + } + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); + DMA_EnableChannel(handle->base, handle->channel); +} + +/*! + * brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * param base DMA peripheral base address. + * param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + uint32_t dmaInstance; + uint32_t startChannel = 0; + /* base address is invalid DMA instance */ + dmaInstance = DMA_GetInstance(base); + startChannel = DMA_GetVirtualStartChannel(base); + + (void)memset(handle, 0, sizeof(*handle)); + handle->base = base; + handle->channel = (uint8_t)channel; + s_DMAHandle[startChannel + channel] = handle; + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); + /* Enable channel interrupt */ + DMA_EnableChannelInterrupts(handle->base, channel); +} + +/*! + * brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * param handle DMA handle pointer. + * param callback DMA callback function pointer. + * param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Prepares the DMA transfer structure. + * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and + * DMA_PrepareChannelXfer. + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type dma_transfer_t. + * param srcAddr DMA transfer source address. + * param dstAddr DMA transfer destination address. + * param byteWidth DMA transfer destination address width(bytes). + * param transferBytes DMA transfer bytes to be transferred. + * param type DMA transfer type. + * param nextDesc Chain custom descriptor to transfer. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) +{ + uint32_t xfer_count; + assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); + assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + + /* check max */ + xfer_count = transferBytes / byteWidth; + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); + + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) + { + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + } + + else if (type == kDMA_PeripheralToMemory) + { + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->xfercfg.transferCount = (uint16_t)xfer_count; + config->xfercfg.byteWidth = (uint8_t)byteWidth; + config->xfercfg.intA = true; + config->xfercfg.reload = nextDesc != NULL; + config->xfercfg.valid = true; +} + +/*! + * brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * param base DMA base address. + * param channel DMA channel number. + * param config channel configurations structure. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); + + uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; + + if (trigger != NULL) + { + tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | + DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; + } + + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + + if (trigger != NULL) + { + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + } + + tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); + + base->CHANNEL[channel].CFG = tmpReg; +} + +/*! + * brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * param config Pointer to DMA channel transfer configuration structure. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param type transfer type. + * param trigger DMA channel trigger configurations. + * param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc) +{ + assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + + /* check max */ + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) + { + config->isPeriph = false; + } + else if (type == kDMA_PeripheralToMemory) + { + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->isPeriph = true; + } + + config->dstStartAddr = (uint8_t *)dstStartAddr; + config->srcStartAddr = (uint8_t *)srcStartAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->trigger = trigger; + config->xferCfg = xferCfg; +} + +/*! + * brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * endcode + * + * param base DMA base address. + * param channel DMA channel. + * param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) +{ + assert(NULL != descriptor); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + uint32_t instance = DMA_GetInstance(base); + dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); + + channelDescriptor->xfercfg = descriptor->xfercfg; + channelDescriptor->srcEndAddr = descriptor->srcEndAddr; + channelDescriptor->dstEndAddr = descriptor->dstEndAddr; + channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; + + /* Set channel XFERCFG register according first channel descriptor. */ + base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; +} + +/*! + * brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. + * + * param handle Pointer to DMA channel transfer handle. + * param addr DMA descriptor address + * param num DMA descriptor number. + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) +{ + assert(addr != NULL); + +#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); +#else + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); +#endif + /* reconfigure the DMA descriptor base address */ + base->SRAMBASE = (uint32_t)(uint32_t *)addr; +} + +/*! + * brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; +} + +/*! + * brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) +{ + assert((NULL != handle) && (NULL != descriptor)); + + DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); +} + +/*! + * brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* setup channgel trigger configurations */ + DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); + + DMA_SetupChannelDescriptor( + descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, + config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, + (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : + ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> + DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; + + return kStatus_Success; +} + +/*! + * brief Submits the DMA transfer request. + * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* enable/disable peripheral request */ + if (config->isPeriph) + { + DMA_EnableChannelPeriphRq(handle->base, handle->channel); + } + else + { + DMA_DisableChannelPeriphRq(handle->base, handle->channel); + } + + DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; + + return kStatus_Success; +} + +/*! + * brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + + uint32_t channel = handle->channel; + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + /* enable channel */ + DMA_EnableChannel(handle->base, channel); + + /* Do software trigger only when HW trigger is not enabled. */ + if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) + { + handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + } +} + +void DMA_IRQHandle(DMA_Type *base) +{ + dma_handle_t *handle; + uint8_t channel_index; + uint32_t startChannel = DMA_GetVirtualStartChannel(base); + uint32_t i = 0; + + /* Find channels that have completed transfer */ + for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) + { + handle = s_DMAHandle[i + startChannel]; + /* Handle is not present */ + if (NULL == handle) + { + continue; + } + channel_index = DMA_CHANNEL_INDEX(base, handle->channel); + /* Channel uses INTA flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL) + { + /* Clear INTA flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntA); + } + } + /* Channel uses INTB flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL) + { + /* Clear INTB flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntB); + } + } + /* Error flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) + { + /* Clear error flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } + } +} + +void DMA0_DriverIRQHandler(void); +void DMA0_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA0); + SDK_ISR_EXIT_BARRIER; +} + +#if defined(DMA1) +void DMA1_DriverIRQHandler(void); +void DMA1_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA1); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..c6a7c1a209f26a063a22c0fe3668874c6c665080 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dma.h @@ -0,0 +1,892 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*!< Version 2.4.3. */ +/*@}*/ + +/*! @brief DMA max transfer size */ +#define DMA_MAX_TRANSFER_COUNT 0x400U +/*! @brief DMA channel numbers */ +#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#endif +/*! @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) +/*! @brief DMA head descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA head descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA transfer buffer address need to align with the transfer width */ +#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) +/* Channel group consists of 32 channels. channel_group = 0 */ +#define DMA_CHANNEL_GROUP(channel) (0U) +/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ +#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) % FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) +/*! @brief DMA linked descriptor address algin size */ +#define DMA_COMMON_REG_GET(base, channel, reg) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ + (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_REG_SET(base, channel, reg, value) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) + +/*! @brief DMA descriptor end address calculate + * @param start start address + * @param inc address interleave size + * @param bytes transfer bytes + * @param width transfer width + */ +#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ + ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) + +/*! @brief DMA channel transfer configurations macro + * @param reload true is reload link descriptor after current exhaust, false is not + * @param clrTrig true is clear trigger status, wait software trigger, false is not + * @param intA enable interruptA + * @param intB enable interruptB + * @param width transfer width + * @param srcInc source address interleave size + * @param dstInc destination address interleave size + * @param bytes transfer bytes + */ +#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ + DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ + DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ + DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ + DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ + DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ + DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) + +/*! @brief _dma_transfer_status DMA transfer status */ +enum +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief _dma_addr_interleave_size dma address interleave size */ +enum +{ + kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ + kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ + kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ + kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ +}; + +/*! @brief _dma_transfer_width dma transfer width */ +enum +{ + kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ + kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ + kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ +}; + +/*! @brief DMA descriptor structure */ +typedef struct _dma_descriptor +{ + volatile uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +} dma_descriptor_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_xfercfg +{ + bool valid; /*!< Descriptor is ready to transfer */ + bool reload; /*!< Reload channel configuration register after + current descriptor is exhausted */ + bool swtrig; /*!< Perform software trigger. Transfer if fired + when 'valid' is set */ + bool clrtrig; /*!< Clear trigger */ + bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ + bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ + uint8_t byteWidth; /*!< Byte width of data to transfer */ + uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ + uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ + uint16_t transferCount; /*!< Number of transfers */ +} dma_xfercfg_t; + +/*! @brief DMA channel priority */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +} dma_priority_t; + +/*! @brief DMA interrupt flags */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ +} dma_irq_t; + +/*! @brief DMA trigger type*/ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ + kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ +} dma_trigger_type_t; + +/*! @brief _dma_burst_size DMA burst size*/ +enum +{ + kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ + kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ + kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ + kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ + kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ + kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ + kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ + kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ + kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ + kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ + kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ +}; + +/*! @brief DMA trigger burst */ +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; + +/*! @brief DMA burst wrapping */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +} dma_burst_wrap_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ + kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ + kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ + kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ +} dma_transfer_type_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ +} dma_channel_trigger_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_config +{ + void *srcStartAddr; /*!< Source data address */ + void *dstStartAddr; /*!< Destination data address */ + void *nextDesc; /*!< Chain custom descriptor */ + uint32_t xferCfg; /*!< channel transfer configurations */ + dma_channel_trigger_t *trigger; /*!< DMA trigger type */ + bool isPeriph; /*!< select the request type */ +} dma_channel_config_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_transfer_config +{ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ +} dma_transfer_config_t; + +/*! @brief Callback for DMA */ +struct _dma_handle; + +/*! @brief Define Callback function for DMA. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); + +/*! @brief DMA transfer handle structure */ +typedef struct _dma_handle +{ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ +} dma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/*! + * @brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * + * @param base DMA base address. + * @param addr DMA descriptor address + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); + +/* @} */ + +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! + * @brief Return whether DMA channel is processing transfer + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for active state, false otherwise. + */ +static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; +} + +/*! + * @brief Return whether DMA channel is busy + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for busy state, false otherwise. + */ +static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; +} + +/*! + * @brief Enables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Disables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Enable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Disable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Set PERIPHREQEN of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Get PERIPHREQEN value of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for enabled PeriphRq, false for disabled. + */ +static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Set trigger settings of DMA channel. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); + +/*! + * @brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * @param base DMA base address. + * @param channel DMA channel number. + * @param trigger channel configurations structure. + * @param isPeriph true is periph request, false is not. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Set priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param priority Channel priority value. + */ +static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); +} + +/*! + * @brief Get priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return Channel priority value. + */ +static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); +} + +/*! + * @brief Set channel configuration valid. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; +} + +/*! + * @brief Do software trigger for the channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; +} + +/*! + * @brief Load channel transfer configurations. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param xfer transfer configurations. + */ +static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) +{ + base->CHANNEL[channel].XFERCFG = xfer; +} + +/*! + * @brief Create application specific DMA descriptor + * to be used in a chain in transfer + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcAddr Address of last item to transmit + * @param dstAddr Address of last item to receive. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); + +/*! + * @brief setup dma descriptor + * + * Note: This function do not support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief setup dma channel descriptor + * + * Note: This function support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + * @param wrapType burst wrap type. + * @param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize); + +/*! + * @brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. + * @code + * DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * @endcode + * + * @param base DMA base address. + * @param channel DMA channel. + * @param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); + +/* @} */ + +/*! + * @name DMA Transactional Operation + * @{ + */ + +/*! + * @brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer structure. + * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type dma_transfer_t. + * @param srcAddr DMA transfer source address. + * @param dstAddr DMA transfer destination address. + * @param byteWidth DMA transfer destination address width(bytes). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + * @param nextDesc Chain custom descriptor to transfer. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); + +/*! + * @brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * @param config Pointer to DMA channel transfer configuration structure. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param type transfer type. + * @param trigger DMA channel trigger configurations. + * @param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc); + +/*! + * @brief Submits the DMA transfer request. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); + +/*! + * @brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); + +/*! + * @brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); + +/*! + * @brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * @param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for descriptor transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + * + * @param base DMA base address. + */ +void DMA_IRQHandle(DMA_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.c new file mode 100644 index 0000000000000000000000000000000000000000..5782d85195b28fbe4ff2941e43af26ebffbaeb48 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.c @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dmic.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmic" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of DMIC peripheral base address. */ +static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of DMIC clock name. */ +static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* Array of DMIC IRQ number. */ +static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS; + +/*! @brief Callback function array for DMIC(s). */ +static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT]; + +/* Array of HWVAD IRQ number. */ +static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS; + +/*! @brief Callback function array for HWVAD(s). */ +static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT]; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the DMIC instance from peripheral base address. + * + * @param base DMIC peripheral base address. + * @return DMIC instance. + */ +/*! + * brief Get the DMIC instance from peripheral base address. + * + * param base DMIC peripheral base address. + * return DMIC instance. + */ +uint32_t DMIC_GetInstance(DMIC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++) + { + if (s_dmicBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dmicBases)); + + return instance; +} + +/*! + * brief Turns DMIC Clock on + * param base : DMIC base + * return Nothing + */ +void DMIC_Init(DMIC_Type *base) +{ + assert(base != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /* reset FIFO configuration */ + base->CHANNEL[0].FIFO_CTRL = 0U; + base->CHANNEL[1].FIFO_CTRL = 0U; +#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) + base->CHANNEL[3].FIFO_CTRL = 0U; + base->CHANNEL[4].FIFO_CTRL = 0U; + base->CHANNEL[5].FIFO_CTRL = 0U; + base->CHANNEL[6].FIFO_CTRL = 0U; + base->CHANNEL[7].FIFO_CTRL = 0U; +#endif +} + +/*! + * brief Turns DMIC Clock off + * param base : DMIC base + * return Nothing + */ +void DMIC_DeInit(DMIC_Type *base) +{ + assert(base != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG) +/*! + * brief Configure DMIC io + * @deprecated Do not use this function. It has been superceded by @ref DMIC_SetIOCFG + * param base : The base address of DMIC interface + * param config : DMIC io configuration + * return Nothing + */ +void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config) +{ + base->IOCFG = (uint32_t)config; +} +#endif + +/*! + * brief Set DMIC operating mode + * deprecated Do not use this function. It has been superceded by @ref + * DMIC_EnableChannelInterrupt/DMIC_EnableChannelDma + * param base : The base address of DMIC interface + * param mode : DMIC mode + * return Nothing + */ +void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) +{ + if (mode == kDMIC_OperationModeInterrupt) + { + /* Enable DMIC interrupt. */ + base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); + base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); + } + if (mode == kDMIC_OperationModeDma) + { + /* enable DMA request*/ + base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); + base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); + } +} + +/*! + * brief Configure DMIC channel + * + * param base : The base address of DMIC interface + * param channel : DMIC channel + * param side : stereo_side_t, choice of left or right + * param channel_config : Channel configuration + * return Nothing + */ +void DMIC_ConfigChannel(DMIC_Type *base, + dmic_channel_t channel, + stereo_side_t side, + dmic_channel_config_t *channel_config) +{ + base->CHANNEL[channel].DIVHFCLK = (uint32_t)channel_config->divhfclk; + base->CHANNEL[channel].OSR = channel_config->osr; + base->CHANNEL[channel].GAINSHIFT = (uint32_t)channel_config->gainshft; + base->CHANNEL[channel].PREAC2FSCOEF = (uint32_t)channel_config->preac2coef; + base->CHANNEL[channel].PREAC4FSCOEF = (uint32_t)channel_config->preac4coef; + base->CHANNEL[channel].PHY_CTRL = + DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate); + base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) | + DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) | + DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit); + +#if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) + base->CHANNEL[channel].DC_CTRL |= DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(channel_config->enableSignExtend); +#endif +} + +/*! + * brief Configure DMIC channel + * param base : The base address of DMIC interface + * param channel : DMIC channel + * param dc_cut_level : dc_removal_t, Cut off Frequency + * param post_dc_gain_reduce : Fine g!y!9 + * param saturate16bit : If selects 16-bit saturation. + */ +void DMIC_CfgChannelDc(DMIC_Type *base, + dmic_channel_t channel, + dc_removal_t dc_cut_level, + uint32_t post_dc_gain_reduce, + bool saturate16bit) +{ + base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) | + DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) | + DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit); +} + +/*! + * brief Configure Clock scaling + * param base : The base address of DMIC interface + * param use2fs : clock scaling + * return Nothing + */ +void DMIC_Use2fs(DMIC_Type *base, bool use2fs) +{ + base->USE2FS = (use2fs) ? 0x1UL : 0x0UL; +} + +/*! + * brief Enable a particualr channel + * param base : The base address of DMIC interface + * param channelmask : Channel selection + * return Nothing + */ +void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask) +{ + base->CHANEN |= channelmask; +} + +/*! + * brief Configure fifo settings for DMIC channel + * param base : The base address of DMIC interface + * param channel : DMIC channel + * param trig_level : FIFO trigger level + * param enable : FIFO level + * param resetn : FIFO reset + * return Nothing + */ +void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn) +{ + base->CHANNEL[channel].FIFO_CTRL = + ((base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) | + DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) | + DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn)); +} + +#if defined(FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC) && FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC +/*! + * brief DMIC channel Decimator reset + * param base : The base address of DMIC interface + * param channelMask : DMIC channel mask, reference _dmic_channel_mask + * param reset : true is reset decimator, false is release decimator. + */ +void DMIC_ResetChannelDecimator(DMIC_Type *base, uint32_t channelMask, bool reset) +{ + uint32_t decReset = 0U; + + if ((channelMask & ((uint32_t)kDMIC_EnableChannel1 | (uint32_t)kDMIC_EnableChannel0)) != 0U) + { + decReset |= 1U; + } +#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) + if ((channelMask & ((uint32_t)kDMIC_EnableChannel3 | (uint32_t)kDMIC_EnableChannel2)) != 0U) + { + decReset |= 2U; + } + + if ((channelMask & ((uint32_t)kDMIC_EnableChannel5 | (uint32_t)kDMIC_EnableChannel4)) != 0U) + { + decReset |= 4U; + } + + if ((channelMask & ((uint32_t)kDMIC_EnableChannel7 | (uint32_t)kDMIC_EnableChannel6)) != 0U) + { + decReset |= 8U; + } +#endif + + if (reset) + { + base->DECRESET |= decReset; + } + else + { + base->DECRESET &= ~decReset; + } +} +#endif + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * param base Base address of the DMIC peripheral. + * param cb callback Pointer to store callback function. + * retval None. + */ +void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); + /* Save callback pointer */ + s_dmicCallback[instance] = cb; + (void)EnableIRQ(s_dmicIRQ[instance]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected DMIC peripheral. + * + * param base Base address of the DMIC peripheral. + * param cb callback Pointer to store callback function.. + * retval None. + */ +void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + (void)DisableIRQ(s_dmicIRQ[instance]); + s_dmicCallback[instance] = NULL; + NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); +} + +/*! + * brief Enable hwvad callback. + + * This function enables the hwvad interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * param base Base address of the DMIC peripheral. + * param vadcb callback Pointer to store callback function. + * retval None. + */ +void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); + /* Save callback pointer */ + s_dmicHwvadCallback[instance] = vadcb; + (void)EnableIRQ(s_dmicHwvadIRQ[instance]); +} + +/*! + * brief Disable callback. + + * This function disables the hwvad interrupt for the selected DMIC peripheral. + * + * param base Base address of the DMIC peripheral. + * param vadcb callback Pointer to store callback function.. + * retval None. + */ +void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + (void)DisableIRQ(s_dmicHwvadIRQ[instance]); + s_dmicHwvadCallback[instance] = NULL; + NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(DMIC0) +/*DMIC0 IRQ handler */ +void DMIC0_DriverIRQHandler(void); +void DMIC0_DriverIRQHandler(void) +{ + if (s_dmicCallback[0] != NULL) + { + s_dmicCallback[0](); + } + SDK_ISR_EXIT_BARRIER; +} +/*DMIC0 HWVAD IRQ handler */ +void HWVAD0_DriverIRQHandler(void); +void HWVAD0_DriverIRQHandler(void) +{ + if (s_dmicHwvadCallback[0] != NULL) + { + s_dmicHwvadCallback[0](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.h new file mode 100644 index 0000000000000000000000000000000000000000..46811c67379bf500e957ccd4cd7de8c6e08ec747 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic.h @@ -0,0 +1,629 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DMIC_H_ +#define _FSL_DMIC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmic_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name DMIC version + * @{ + */ + +/*! @brief DMIC driver version 2.3.0. */ +#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief _dmic_status DMIC transfer status.*/ +enum +{ + kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */ + kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */ + kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */ + kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */ +}; + +/*! @brief DMIC different operation modes. */ +typedef enum _operation_mode +{ + kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */ + kDMIC_OperationModeDma = 2U, /*!< DMA mode */ +} operation_mode_t; + +/*! @brief DMIC left/right values. */ +typedef enum _stereo_side +{ + kDMIC_Left = 0U, /*!< Left Stereo channel */ + kDMIC_Right = 1U, /*!< Right Stereo channel */ +} stereo_side_t; + +/*! @brief DMIC Clock pre-divider values. */ +typedef enum +{ + kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */ + kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */ + kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */ + kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */ + kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */ + kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */ + kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */ + kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/ + kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/ + kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */ + kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */ + kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/ + kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/ + kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */ +} pdm_div_t; + +/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */ +typedef enum _compensation +{ + kDMIC_CompValueZero = 0U, /*!< Compensation 0 */ + kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */ + kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */ + kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */ +} compensation_t; + +/*! @brief DMIC DC filter control values. */ +typedef enum _dc_removal +{ + kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */ + kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */ + kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */ + kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */ +} dc_removal_t; + +#if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG) +/*! @brief DMIC IO configiration. */ +typedef enum _dmic_io +{ + kDMIC_PdmDual = 0, /*!< Two separate pairs of PDM wires */ + kDMIC_PdmStereo = 4, /*!< Stereo data0 */ + +#if !(defined(FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS) && (FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS)) + kDMIC_PdmBypass = 3, /*!< Clk Bypass clocks both channels */ + kDMIC_PdmBypassClk0 = 1, /*!< Clk Bypass clocks only channel0 */ + kDMIC_PdmBypassClk1 = 2, /*!< Clk Bypas clocks only channel1 */ +#endif + +#if defined(FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6) && (FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6) + kDMIC_PdmStereo2 = 8, /*!< Stereo data2 */ + kDMIC_PdmStereo4 = 16, /*!< Stereo data4 */ + kDMIC_PdmStereo6 = 32, /*!< Stereo data6 */ +#endif +} dmic_io_t; +#endif + +/*! @brief DMIC Channel number. */ +typedef enum _dmic_channel +{ + kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */ + kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */ +#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) + kDMIC_Channel2 = 2U, /*!< DMIC channel 2 */ + kDMIC_Channel3 = 3U, /*!< DMIC channel 3 */ + kDMIC_Channel4 = 4U, /*!< DMIC channel 4 */ + kDMIC_Channel5 = 5U, /*!< DMIC channel 5 */ + kDMIC_Channel6 = 6U, /*!< DMIC channel 6 */ + kDMIC_Channel7 = 7U, /*!< DMIC channel 7 */ +#endif +} dmic_channel_t; + +/*! @brief _dmic_channel_mask DMIC Channel mask. */ +enum +{ + kDMIC_EnableChannel0 = 1 << 0U, /*!< DMIC channel 0 mask */ + kDMIC_EnableChannel1 = 1 << 1U, /*!< DMIC channel 1 mask */ +#if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U) + kDMIC_EnableChannel2 = 1 << 2U, /*!< DMIC channel 2 mask */ + kDMIC_EnableChannel3 = 1 << 3U, /*!< DMIC channel 3 mask */ + kDMIC_EnableChannel4 = 1 << 4U, /*!< DMIC channel 4 mask */ + kDMIC_EnableChannel5 = 1 << 5U, /*!< DMIC channel 5 mask */ + kDMIC_EnableChannel6 = 1 << 6U, /*!< DMIC channel 6 mask */ + kDMIC_EnableChannel7 = 1 << 7U, /*!< DMIC channel 7 mask */ +#endif +}; + +/*! @brief DMIC and decimator sample rates. */ +typedef enum _dmic_phy_sample_rate +{ + kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */ + kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */ +} dmic_phy_sample_rate_t; + +/*! @brief DMIC Channel configuration structure. */ +typedef struct _dmic_channel_config +{ + pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */ + uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */ + int32_t gainshft; /*!< 4FS PCM data gain control */ + compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */ + compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */ + dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */ + uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */ + dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */ + bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate. + 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and + 0x8000 for negative overflow.*/ +#if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) + bool enableSignExtend; /*!< sign extend feature which allows processing of 24bit audio data on 32bit machine */ +#endif +} dmic_channel_config_t; + +/*! @brief DMIC Callback function. */ +typedef void (*dmic_callback_t)(void); + +/*! @brief HWVAD Callback function. */ +typedef void (*dmic_hwvad_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Get the DMIC instance from peripheral base address. + * + * @param base DMIC peripheral base address. + * @return DMIC instance. + */ +uint32_t DMIC_GetInstance(DMIC_Type *base); + +/*! + * @brief Turns DMIC Clock on + * @param base : DMIC base + * @return Nothing + */ +void DMIC_Init(DMIC_Type *base); + +/*! + * @brief Turns DMIC Clock off + * @param base : DMIC base + * @return Nothing + */ +void DMIC_DeInit(DMIC_Type *base); + +#if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG) +/*! + * @brief Configure DMIC io + * @deprecated Do not use this function. It has been superceded by @ref DMIC_SetIOCFG + * @param base : The base address of DMIC interface + * @param config : DMIC io configuration + * @return Nothing + */ +void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config); + +/*! + * @brief Stereo PDM select. + * @param base : The base address of DMIC interface + * @param sel : Reference dmic_io_t, can be a single or combination value of dmic_io_t. + * @return Nothing + */ +static inline void DMIC_SetIOCFG(DMIC_Type *base, uint32_t sel) +{ + base->IOCFG = sel; +} +#endif + +/*! + * @brief Set DMIC operating mode + * @deprecated Do not use this function. It has been superceded by + * @ref DMIC_EnableChannelInterrupt, @ref DMIC_EnableChannelDma. + * @param base : The base address of DMIC interface + * @param mode : DMIC mode + * @return Nothing + */ +void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode); + +/*! + * @brief Configure Clock scaling + * @param base : The base address of DMIC interface + * @param use2fs : clock scaling + * @return Nothing + */ +void DMIC_Use2fs(DMIC_Type *base, bool use2fs); + +/*! @} */ + +/*! + * @name Channel configuration + * @{ + */ + +/*! + * @brief Configure DMIC channel + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param dc_cut_level : dc_removal_t, Cut off Frequency + * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift. + * @param saturate16bit : If selects 16-bit saturation. + */ +void DMIC_CfgChannelDc(DMIC_Type *base, + dmic_channel_t channel, + dc_removal_t dc_cut_level, + uint32_t post_dc_gain_reduce, + bool saturate16bit); + +#if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) +/*! + * @brief Enbale channel sign extend which allows processing of 24bit audio data on 32bit machines. + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param enable : true is enable sign extend, false is disable sign extend + */ +static inline void DMIC_EnableChannelSignExtend(DMIC_Type *base, dmic_channel_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].DC_CTRL |= DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK; + } + else + { + base->CHANNEL[channel].DC_CTRL &= ~DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK; + } +} +#endif + +/*! + * @brief Configure DMIC channel + * + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param side : stereo_side_t, choice of left or right + * @param channel_config : Channel configuration + * @return Nothing + */ +void DMIC_ConfigChannel(DMIC_Type *base, + dmic_channel_t channel, + stereo_side_t side, + dmic_channel_config_t *channel_config); + +/*! + * @brief Enable a particualr channel + * @param base : The base address of DMIC interface + * @param channelmask reference _dmic_channel_mask + * @return Nothing + */ +void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask); + +/*! + * @brief Configure fifo settings for DMIC channel + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param trig_level : FIFO trigger level + * @param enable : FIFO level + * @param resetn : FIFO reset + * @return Nothing + */ +void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn); + +/*! + * @brief Enable a particualr channel interrupt request. + * @param base : The base address of DMIC interface + * @param channel : Channel selection + * @param enable : true is enable, false is disable + */ +static inline void DMIC_EnableChannelInterrupt(DMIC_Type *base, dmic_channel_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK; + } + else + { + base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK; + } +} + +/*! + * @brief Enable a particualr channel dma request. + * @param base : The base address of DMIC interface + * @param channel : Channel selection + * @param enable : true is enable, false is disable + */ +static inline void DMIC_EnableChannelDma(DMIC_Type *base, dmic_channel_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK; + } + else + { + base->CHANNEL[channel].FIFO_CTRL &= DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK; + } +} + +/*! + * @brief Enable a particualr channel fifo. + * @param base : The base address of DMIC interface + * @param channel : Channel selection + * @param enable : true is enable, false is disable + */ +static inline void DMIC_EnableChannelFifo(DMIC_Type *base, dmic_channel_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK; + } + else + { + base->CHANNEL[channel].FIFO_CTRL &= DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK; + } +} + +/*! + * @brief Channel fifo reset. + * @param base : The base address of DMIC interface + * @param channel : Channel selection + */ +static inline void DMIC_DoFifoReset(DMIC_Type *base, dmic_channel_t channel) +{ + /* reset FIFO */ + base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK; + /* normal operation */ + base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK; +} + +/*! + * @brief Get FIFO status + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @return FIFO status + */ +static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel) +{ + return base->CHANNEL[channel].FIFO_STATUS; +} + +/*! + * @brief Clear FIFO status + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param mask : Bits to be cleared + * @return FIFO status + */ +static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask) +{ + base->CHANNEL[channel].FIFO_STATUS = mask; +} + +/*! + * @brief Get FIFO data + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @return FIFO data + */ +static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel) +{ + return base->CHANNEL[channel].FIFO_DATA; +} + +/*! + * @brief Get FIFO address + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @return FIFO data + */ +static inline uint32_t DMIC_FifoGetAddress(DMIC_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->CHANNEL[channel].FIFO_DATA)); +} + +#if defined(FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC) && FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC +/*! + * @brief DMIC channel Decimator reset + * @param base : The base address of DMIC interface + * @param channelMask : DMIC channel mask, reference _dmic_channel_mask + * @param reset : true is reset decimator, false is release decimator. + */ +void DMIC_ResetChannelDecimator(DMIC_Type *base, uint32_t channelMask, bool reset); +#endif + +#if defined(FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC) && FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC +/*! + * @brief Enable DMIC channel global sync function. + * @param base : The base address of DMIC interface + * @param channelMask : DMIC channel mask, reference _dmic_channel_mask + * @param syncCounter :sync counter will trigger a pulse whenever count reaches CCOUNTVAL. If CCOUNTVAL is set to 0, + * there will be a pulse on every cycle + */ +static inline void DMIC_EnableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask, uint32_t syncCounter) +{ + base->GLOBAL_COUNT_VAL = syncCounter; + base->GLOBAL_SYNC_EN = channelMask; +} + +/*! + * @brief Disbale DMIC channel global sync function. + * @param base : The base address of DMIC interface + * @param channelMask : DMIC channel mask, reference _dmic_channel_mask + */ +static inline void DMIC_DisableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask) +{ + base->GLOBAL_SYNC_EN &= ~channelMask; +} +#endif + +/*! @} */ + +/*! + * @name Register callback. + * @{ + */ + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * @param base Base address of the DMIC peripheral. + * @param cb callback Pointer to store callback function. + * @retval None. + */ +void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected DMIC peripheral. + * + * @param base Base address of the DMIC peripheral. + * @param cb callback Pointer to store callback function.. + * @retval None. + */ +void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb); +/*! @} */ + +/*! + * @name HWVAD + * @{ + */ + +/*! + * @brief Sets the gain value for the noise estimator. + * + * @param base DMIC base pointer + * @param value gain value for the noise estimator. + * @retval None. + */ +static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADTHGN = value & 0xFUL; +} + +/*! + * @brief Sets the gain value for the signal estimator. + * + * @param base DMIC base pointer + * @param value gain value for the signal estimator. + * @retval None. + */ +static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADTHGS = value & 0xFUL; +} + +/*! + * @brief Sets the hwvad filter cutoff frequency parameter. + * + * @param base DMIC base pointer + * @param value cut off frequency value. + * @retval None. + */ +static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADHPFS = value & 0x3UL; +} + +/*! + * @brief Sets the input gain of hwvad. + * + * @param base DMIC base pointer + * @param value input gain value for hwvad. + * @retval None. + */ +static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADGAIN = value & 0xFUL; +} + +/*! + * @brief Clears hwvad internal interrupt flag. + * + * @param base DMIC base pointer + * @param st10 bit value. + * @retval None. + */ +static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10) +{ + assert(NULL != base); + base->HWVADST10 = (st10) ? 0x1UL : 0x0UL; +} + +/*! + * @brief Resets hwvad filters. + * + * @param base DMIC base pointer + * @param rstt Reset bit value. + * @retval None. + */ +static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt) +{ + assert(NULL != base); + base->HWVADRSTT = (rstt) ? 0x1UL : 0x0UL; +} + +/*! + * @brief Gets the value from output of the filter z7. + * + * @param base DMIC base pointer + * @retval output of filter z7. + */ +static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base) +{ + assert(NULL != base); + return (uint16_t)(base->HWVADLOWZ & 0xFFFFU); +} + +/*! + * @brief Enable hwvad callback. + + * This function enables the hwvad interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * @param base Base address of the DMIC peripheral. + * @param vadcb callback Pointer to store callback function. + * @retval None. + */ +void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); + +/*! + * @brief Disable callback. + + * This function disables the hwvad interrupt for the selected DMIC peripheral. + * + * @param base Base address of the DMIC peripheral. + * @param vadcb callback Pointer to store callback function.. + * @retval None. + */ +void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __FSL_DMIC_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..72dbfa6dbaaca975aa9250a7f71ffcb792cba2c1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dmic_dma.h" +#include "fsl_dmic.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmic_dma" +#endif + +/*! @brief _dmic_dma_states_t DMIC transfer state, which is used for DMIC transactiaonl APIs' internal state. */ +enum +{ + kDMIC_Idle = 0x0, /*!< DMIC is idle state */ + kDMIC_Busy /*!< DMIC is busy tranferring data. */ +}; +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ********************************************************************************/ + +static void DMIC_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) +{ + assert(handle != NULL); + assert(param != NULL); + + dmic_dma_handle_t *dmicHandle = (dmic_dma_handle_t *)param; + + /* if no link transfer, dmic status set to IDLE. */ + if (dmicHandle->desLink == NULL) + { + dmicHandle->state = kDMIC_Idle; + } + + if (dmicHandle->callback != NULL) + { + dmicHandle->callback(dmicHandle->base, dmicHandle, kStatus_DMIC_Idle, dmicHandle->userData); + } +} + +/*! + * brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space. + * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. + * + * param handle Pointer to DMA channel transfer handle. + * param linkAddr DMA link descriptor address. + * param num DMA link descriptor number. + */ +void DMIC_InstallDMADescriptorMemory(dmic_dma_handle_t *handle, void *linkAddr, size_t linkNum) +{ + assert(handle != NULL); + + handle->desLink = (dma_descriptor_t *)linkAddr; + handle->linkNum = linkNum; +} + +/*! + * brief Initializes the DMIC handle which is used in transactional functions. + * param base DMIC peripheral base address. + * param handle Pointer to dmic_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, + dmic_dma_handle_t *handle, + dmic_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *rxDmaHandle) +{ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != rxDmaHandle); + + (void)memset(handle, 0, sizeof(*handle)); + + handle->callback = callback; + handle->userData = userData; + handle->rxDmaHandle = rxDmaHandle; + + /* Set DMIC state to idle */ + handle->state = kDMIC_Idle; + /* register callback. */ + DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, handle); + + return kStatus_Success; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer DMIC DMA transfer structure. See #dmic_transfer_t. + * param dmic_channel DMIC start channel number + * retval kStatus_Success + */ +status_t DMIC_TransferReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle, dmic_transfer_t *xfer, uint32_t channel) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + + dma_channel_config_t transferConfig = {0U}; + uint32_t srcAddr = (uint32_t)&base->CHANNEL[channel].FIFO_DATA; + uint32_t desNum = 0U; + dma_descriptor_t *linkDesc = (handle->desLink != NULL) ? &(handle->desLink[desNum + 1U]) : NULL; + dmic_transfer_t *currentTransfer = xfer->linkTransfer; + bool loopEnd = false, intA = true; + uint32_t interleaveWidth = kDMA_AddressInterleave0xWidth; + + if ((xfer->linkTransfer != NULL) && (handle->desLink == NULL)) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint8_t)kDMIC_Busy) + { + return kStatus_DMIC_Busy; + } + + while (currentTransfer != NULL) + { + /* set up linked descriptor */ + DMA_SetupDescriptor(&handle->desLink[desNum], + DMA_CHANNEL_XFER(currentTransfer->linkTransfer != NULL ? 1UL : 0UL, 0UL, intA, !intA, + currentTransfer->dataWidth, interleaveWidth, + currentTransfer->dataAddrInterleaveSize, currentTransfer->dataSize), + (uint32_t *)srcAddr, currentTransfer->data, linkDesc); + + intA = intA == true ? false : true; + /* break for wrap transfer */ + if (loopEnd) + { + break; + } + + if (++desNum == handle->linkNum) + { + return kStatus_Fail; + } + + linkDesc = &handle->desLink[desNum + 1U]; + + currentTransfer = currentTransfer->linkTransfer; + /* if current transfer need wrap, then create one more descriptor, since the first descriptor cannot be used + * anymore, this is + * the limitation of the DMA module + */ + if (currentTransfer == xfer) + { + linkDesc = handle->desLink; /* point to the first one */ + loopEnd = true; + continue; + } + } + /* transferSize make sense to non link transfer only */ + handle->transferSize += xfer->dataSize; + + /* code to keep compatibility for the case that not use link transfer */ + if ((xfer->dataWidth != (uint8_t)kDMA_Transfer16BitWidth) && (xfer->dataWidth != (uint8_t)kDMA_Transfer32BitWidth)) + { + xfer->dataWidth = kDMA_Transfer16BitWidth; /* use 16bit width as default value */ + } + /* code to keep compatibility for the case that not use link transfer*/ + if ((xfer->dataAddrInterleaveSize == (uint8_t)kDMA_AddressInterleave0xWidth) || + (xfer->dataAddrInterleaveSize > (uint8_t)kDMA_AddressInterleave4xWidth)) + { + xfer->dataAddrInterleaveSize = kDMA_AddressInterleave1xWidth; /* use interleave1Xwidth as default value. */ + } + + /* prepare channel tranfer */ + DMA_PrepareChannelTransfer( + &transferConfig, (uint32_t *)srcAddr, xfer->data, + DMA_CHANNEL_XFER(xfer->linkTransfer == NULL ? 0UL : 1UL, 0UL, intA, !intA, xfer->dataWidth, interleaveWidth, + xfer->dataAddrInterleaveSize, xfer->dataSize), + kDMA_PeripheralToMemory, NULL, handle->desLink); + /* Submit transfer. */ + if (DMA_SubmitChannelTransfer(handle->rxDmaHandle, &transferConfig) == kStatus_DMA_Busy) + { + return kStatus_DMIC_Busy; + } + + /* enable channel */ + DMIC_EnableChannnel(DMIC0, 1UL << channel); + /* enable dmic channel dma request */ + DMIC_EnableChannelDma(DMIC0, (dmic_channel_t)channel, true); + + /* start transfer */ + DMA_StartTransfer(handle->rxDmaHandle); + + handle->state = kDMIC_Busy; + + return kStatus_Success; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base DMIC peripheral base address + * param handle Pointer to dmic_dma_handle_t structure + */ +void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->state = kDMIC_Idle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * Note: Do not trying to use this api to get the number of received bytes, it make no sense to link transfer. + * param base DMIC peripheral base address. + * param handle DMIC handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter count; + */ +status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kDMIC_Idle == handle->state) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..40c05bac16d6a7758b7879e93c6ddf3fb4784711 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_dmic_dma.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DMIC_DMA_H_ +#define _FSL_DMIC_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" + +/*! + * @addtogroup dmic_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name DMIC DMA version + * @{ + */ + +/*! @brief DMIC DMA driver version 2.3.0 */ +#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief DMIC transfer structure. */ +typedef struct _dmic_transfer +{ + void *data; /*!< The buffer of data to be transfer.*/ + uint8_t dataWidth; /*!< DMIC support 16bit/32bit */ + size_t dataSize; /*!< The byte count to be transfer. */ + uint8_t dataAddrInterleaveSize; /*!< destination address interleave size */ + + struct _dmic_transfer *linkTransfer; /*!< use to support link transfer */ +} dmic_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _dmic_dma_handle dmic_dma_handle_t; + +/*! @brief DMIC transfer callback function. */ +typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base, + dmic_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief DMIC DMA handle + */ +struct _dmic_dma_handle +{ + DMIC_Type *base; /*!< DMIC peripheral base address. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + dmic_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< DMIC callback function parameter.*/ + size_t transferSize; /*!< Size of the data to receive. */ + volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */ + + dma_descriptor_t *desLink; /*!< descriptor pool pointer */ + size_t linkNum; /*!< number of descriptor in descriptors pool */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the DMIC handle which is used in transactional functions. + * @param base DMIC peripheral base address. + * @param handle Pointer to dmic_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, + dmic_dma_handle_t *handle, + dmic_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t. + * @param channel DMIC start channel number. + * @retval kStatus_Success + */ +status_t DMIC_TransferReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle, dmic_transfer_t *xfer, uint32_t channel); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base DMIC peripheral base address + * @param handle Pointer to dmic_dma_handle_t structure + */ +void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base DMIC peripheral base address. + * @param handle DMIC handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter count; + */ +status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, it should be called after + * DMIC_TransferCreateHandleDMA. + * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. + * + * @param handle Pointer to DMA channel transfer handle. + * @param linkAddr DMA link descriptor address. + * @param linkNum DMA link descriptor number. + */ +void DMIC_InstallDMADescriptorMemory(dmic_dma_handle_t *handle, void *linkAddr, size_t linkNum); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_DMIC_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.c new file mode 100644 index 0000000000000000000000000000000000000000..8117df1332065f3f126a405d83972102cd2e37c0 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.c @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_enc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enc" +#endif + +#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ENC module. + * + * @param base ENC peripheral base address + */ +static uint32_t ENC_GetInstance(ENC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ENC bases for each instance. */ +static ENC_Type *const s_encBases[] = ENC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ENC clocks for each instance. */ +static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ENC_GetInstance(ENC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++) + { + if (s_encBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_encBases)); + + return instance; +} + +/*! + * brief Initialization for the ENC module. + * + * This function is to make the initialization for the ENC module. It should be called firstly before any operation to + * the ENC with the operations like: + * - Enable the clock for ENC module. + * - Configure the ENC's working attributes. + * + * param base ENC peripheral base address. + * param config Pointer to configuration structure. See to "enc_config_t". + */ +void ENC_Init(ENC_Type *base, const enc_config_t *config) +{ + assert(NULL != config); + + uint16_t tmp16; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* ENC_CTRL. */ + tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK | + ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK)); + /* For HOME trigger. */ + if (kENC_HOMETriggerDisabled != config->HOMETriggerMode) + { + tmp16 |= ENC_CTRL_HIP_MASK; + if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) + { + tmp16 |= ENC_CTRL_HNE_MASK; + } + } + /* For encoder work mode. */ + if (config->enableReverseDirection) + { + tmp16 |= ENC_CTRL_REV_MASK; + } + if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) + { + tmp16 |= ENC_CTRL_PH1_MASK; + } + /* For INDEX trigger. */ + if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode) + { + tmp16 |= ENC_CTRL_XIP_MASK; + if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) + { + tmp16 |= ENC_CTRL_XNE_MASK; + } + } + /* Watchdog. */ + if (config->enableWatchdog) + { + tmp16 |= ENC_CTRL_WDE_MASK; + base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ + } + base->CTRL = tmp16; + + /* ENC_FILT. */ + base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod); + + /* ENC_CTRL2. */ + tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK | + ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK)); + if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) + { + tmp16 |= ENC_CTRL2_OUTCTL_MASK; + } + if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) + { + tmp16 |= ENC_CTRL2_REVMOD_MASK; + } + if (config->enableModuloCountMode) + { + tmp16 |= ENC_CTRL2_MOD_MASK; + /* Set modulus value. */ + base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ + base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ + } + if (config->enableTRIGGERClearPositionCounter) + { + tmp16 |= ENC_CTRL2_UPDPOS_MASK; + } + if (config->enableTRIGGERClearHoldPositionCounter) + { + tmp16 |= ENC_CTRL2_UPDHLD_MASK; + } + base->CTRL2 = tmp16; + + /* ENC_UCOMP & ENC_LCOMP. */ + base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ + base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ + + /* ENC_UINIT & ENC_LINIT. */ + base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ + base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ +} + +/*! + * brief De-initialization for the ENC module. + * + * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * the operations like: + * - Disable the clock for ENC module. + * + * param base ENC peripheral base address. + */ +void ENC_Deinit(ENC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get an available pre-defined settings for ENC's configuration. + * + * This function initializes the ENC configuration structure with an available settings, the default value are: + * code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kENC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * endcode + * param config Pointer to a variable of configuration structure. See to "enc_config_t". + */ +void ENC_GetDefaultConfig(enc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableReverseDirection = false; + config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kENC_HOMETriggerDisabled; + config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; + config->enableTRIGGERClearHoldPositionCounter = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; +} + +/*! + * brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * param base ENC peripheral base address. + */ +void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); + + tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ + base->CTRL = tmp16; +} + +/*! + * brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * param base ENC peripheral base address. + * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + */ +void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) +{ + uint16_t tmp16 = 0U; + + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + tmp16 = 0U; + } + else + { + tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) | + ENC_TST_TEST_COUNT(config->signalCount); + if (kENC_SelfTestDirectionNegative == config->signalDirection) + { + tmp16 |= ENC_TST_QDN_MASK; + } + } + + base->TST = tmp16; +} + +/*! + * brief Enable watchdog for ENC module. + * + * param base ENC peripheral base address + * param enable Enables or disables the watchdog + */ +void ENC_EnableWatchdog(ENC_Type *base, bool enable) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); + + if (enable) + { + tmp16 |= ENC_CTRL_WDE_MASK; + } + base->CTRL = tmp16; +} + +/*! + * brief Get the status flags. + * + * param base ENC peripheral base address. + * + * return Mask value of status flags. For available mask, see to "_enc_status_flags". + */ +uint32_t ENC_GetStatusFlags(ENC_Type *base) +{ + uint32_t ret32 = 0U; + + /* ENC_CTRL. */ + if (0U != (ENC_CTRL_HIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_HOMETransitionFlag; + } + if (0U != (ENC_CTRL_XIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_INDEXPulseFlag; + } + if (0U != (ENC_CTRL_DIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_WatchdogTimeoutFlag; + } + if (0U != (ENC_CTRL_CMPIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_PositionCompareFlag; + } + + /* ENC_CTRL2. */ + if (0U != (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_SimultBothPhaseChangeFlag; + } + if (0U != (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_PositionRollOverFlag; + } + if (0U != (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_PositionRollUnderFlag; + } + if (0U != (ENC_CTRL2_DIR_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_LastCountDirectionFlag; + } + + return ret32; +} + +/*! + * brief Clear the status flags. + * + * param base ENC peripheral base address. + * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + */ +void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (0U != ((uint32_t)kENC_HOMETransitionFlag & mask)) + { + tmp16 |= ENC_CTRL_HIRQ_MASK; + } + if (0U != ((uint32_t)kENC_INDEXPulseFlag & mask)) + { + tmp16 |= ENC_CTRL_XIRQ_MASK; + } + if (0U != ((uint32_t)kENC_WatchdogTimeoutFlag & mask)) + { + tmp16 |= ENC_CTRL_DIRQ_MASK; + } + if (0U != ((uint32_t)kENC_PositionCompareFlag & mask)) + { + tmp16 |= ENC_CTRL_CMPIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16); + } + + /* ENC_CTRL2. */ + tmp16 = 0U; + if (0U != ((uint32_t)kENC_SimultBothPhaseChangeFlag & mask)) + { + tmp16 |= ENC_CTRL2_SABIRQ_MASK; + } + if (0U != ((uint32_t)kENC_PositionRollOverFlag & mask)) + { + tmp16 |= ENC_CTRL2_ROIRQ_MASK; + } + if (0U != ((uint32_t)kENC_PositionRollUnderFlag & mask)) + { + tmp16 |= ENC_CTRL2_RUIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Enable the interrupts. + * + * param base ENC peripheral base address. + * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= ENC_CTRL_CMPIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16); + } + /* ENC_CTRL2. */ + tmp16 = 0U; + if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_SABIE_MASK; + } + if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Disable the interrupts. + * + * param base ENC peripheral base address. + * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) +{ + uint16_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= ENC_CTRL_CMPIE_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); + } + /* ENC_CTRL2. */ + tmp16 = 0U; + if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_SABIE_MASK; + } + if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); + } +} + +/*! + * brief Get the enabled interrupts' flags. + * + * param base ENC peripheral base address. + * + * return Mask value of enabled interrupts. + */ +uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) +{ + uint32_t ret32 = 0U; + + /* ENC_CTRL. */ + if (0U != (ENC_CTRL_HIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_HOMETransitionInterruptEnable; + } + if (0U != (ENC_CTRL_XIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_INDEXPulseInterruptEnable; + } + if (0U != (ENC_CTRL_DIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_WatchdogTimeoutInterruptEnable; + } + if (0U != (ENC_CTRL_CMPIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kENC_PositionCompareInerruptEnable; + } + /* ENC_CTRL2. */ + if (0U != (ENC_CTRL2_SABIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_SimultBothPhaseChangeInterruptEnable; + } + if (0U != (ENC_CTRL2_ROIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_PositionRollOverInterruptEnable; + } + if (0U != (ENC_CTRL2_RUIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kENC_PositionRollUnderInterruptEnable; + } + return ret32; +} + +/*! + * brief Set initial position value for ENC module. + * + * param base ENC peripheral base address + * param value Positive initial value + */ +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) +{ + base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ + base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ +} + +/*! + * brief Get the current position counter's value. + * + * param base ENC peripheral base address. + * + * return Current position counter's value. + */ +uint32_t ENC_GetPositionValue(ENC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} + +/*! + * brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * param base ENC peripheral base address. + * + * return Hold position counter's value. + */ +uint32_t ENC_GetHoldPositionValue(ENC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.h new file mode 100644 index 0000000000000000000000000000000000000000..07c49307b00b81fdce65c0c2d128d3a7cc3d1f37 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_enc.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ENC_H_ +#define _FSL_ENC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup enc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FSL_ENC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) + +/*! + * @brief Interrupt enable/disable mask. + */ +enum _enc_interrupt_enable +{ + kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ + kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ + kENC_SimultBothPhaseChangeInterruptEnable = + (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ + kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ +}; + +/*! + * @brief Status flag mask. + * + * These flags indicate the counter's events. + */ +enum _enc_status_flags +{ + kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ + kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ + kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ +}; + +/*! + * @brief Signal status flag mask. + * + * These flags indicate the counter's signal. + */ +enum _enc_signal_status_flags +{ + kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ +}; + +/*! + * @brief Define HOME signal's trigger mode. + * + * The ENC would count the trigger from HOME signal line. + */ +typedef enum _enc_home_trigger_mode +{ + kENC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ + kENC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kENC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} enc_home_trigger_mode_t; + +/*! + * @brief Define INDEX signal's trigger mode. + * + * The ENC would count the trigger from INDEX signal line. + */ +typedef enum _enc_index_trigger_mode +{ + kENC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ + kENC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kENC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} enc_index_trigger_mode_t; + +/*! + * @brief Define type for decoder work mode. + * + * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, + * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction + * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 + * means counting down. Otherwise, the direction is reversed. + */ +typedef enum _enc_decoder_work_mode +{ + kENC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ + kENC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the + direction. */ +} enc_decoder_work_mode_t; + +/*! + * @brief Define type for the condition of POSMATCH pulses. + */ +typedef enum _enc_position_match_mode +{ + kENC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the + position counters (POS) and the compare value (COMP). */ + kENC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ +} enc_position_match_mode_t; + +/*! + * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. + */ +typedef enum _enc_revolution_count_condition +{ + kENC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kENC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + counter. */ +} enc_revolution_count_condition_t; + +/*! + * @brief Define type for direction of self test generated signal. + */ +typedef enum _enc_self_test_direction +{ + kENC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ + kENC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ +} enc_self_test_direction_t; + +/*! + * @brief Define user configuration structure for ENC module. + */ +typedef struct _enc_config +{ + /* Basic counter. */ + bool enableReverseDirection; /*!< Enable reverse direction counting. */ + enc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ + + /* Signal detection. */ + enc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ + enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ + bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ + bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. + */ + + /* Watchdog. */ + bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ + uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature + decoder module watchdog timer. This field is only available when + "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ + + /* Filter for PHASEA, PHASEB, INDEX and HOME. */ + uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of + noisy samples causing an incorrect transition to be recognized. The value represent the + number of consecutive samples that must agree prior to the input filter accepting an + input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 + samples. The Available range is 0 - 7.*/ + uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period + is larger than the period of the expected noise. This value represents the + sampling period (in IPBus clock cycles) of the decoder input signals. + The available range is 0 - 255. */ + + /* Position compare. */ + enc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ + uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ + + /* Modulus counting. */ + enc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ + bool enableModuloCountMode; /*!< Enable Modulo Counting. */ + uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when + "enableModuloCountMode" = true. The available value is a 32-bit number. */ + uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ +} enc_config_t; + +/*! + * @brief Define configuration structure for self test module. + * + * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. + * This is a factory test feature. It is also useful to customers' software development and testing. + */ +typedef struct _enc_self_test_config +{ + enc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ + uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ + uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. + The available range is 0 - 31. */ +} enc_self_test_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initialization for the ENC module. + * + * This function is to make the initialization for the ENC module. It should be called firstly before any operation to + * the ENC with the operations like: + * - Enable the clock for ENC module. + * - Configure the ENC's working attributes. + * + * @param base ENC peripheral base address. + * @param config Pointer to configuration structure. See to "enc_config_t". + */ +void ENC_Init(ENC_Type *base, const enc_config_t *config); + +/*! + * @brief De-initialization for the ENC module. + * + * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * the operations like: + * - Disable the clock for ENC module. + * + * @param base ENC peripheral base address. + */ +void ENC_Deinit(ENC_Type *base); + +/*! + * @brief Get an available pre-defined settings for ENC's configuration. + * + * This function initializes the ENC configuration structure with an available settings, the default value are: + * @code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kENC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * @endcode + * @param config Pointer to a variable of configuration structure. See to "enc_config_t". + */ +void ENC_GetDefaultConfig(enc_config_t *config); + +/*! + * @brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * @param base ENC peripheral base address. + */ +void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); + +/*! + * @brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * @param base ENC peripheral base address. + * @param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + */ +void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); + +/*! + * @brief Enable watchdog for ENC module. + * + * @param base ENC peripheral base address + * @param enable Enables or disables the watchdog + */ +void ENC_EnableWatchdog(ENC_Type *base, bool enable); + +/*! + * @brief Set initial position value for ENC module. + * + * @param base ENC peripheral base address + * @param value Positive initial value + */ +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the status flags. + * + * @param base ENC peripheral base address. + * + * @return Mask value of status flags. For available mask, see to "_enc_status_flags". + */ +uint32_t ENC_GetStatusFlags(ENC_Type *base); + +/*! + * @brief Clear the status flags. + * + * @param base ENC peripheral base address. + * @param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + */ +void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask); + +/*! + * @brief Get the signals' real-time status. + * + * @param base ENC peripheral base address. + * + * @return Mask value of signals' real-time status. For available mask, see to "_enc_signal_status_flags" + */ +static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) +{ + return base->IMR; +} +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base ENC peripheral base address. + * @param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask); + +/*! + * @brief Disable the interrupts. + * + * @param base ENC peripheral base address. + * @param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask); + +/*! + * @brief Get the enabled interrupts' flags. + * + * @param base ENC peripheral base address. + * + * @return Mask value of enabled interrupts. + */ +uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); + +/* @} */ + +/*! + * @name Value Operation + * @{ + */ + +/*! + * @brief Get the current position counter's value. + * + * @param base ENC peripheral base address. + * + * @return Current position counter's value. + */ +uint32_t ENC_GetPositionValue(ENC_Type *base); + +/*! + * @brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position counter's value. + */ +uint32_t ENC_GetHoldPositionValue(ENC_Type *base); + +/*! + * @brief Get the position difference counter's value. + * + * @param base ENC peripheral base address. + * + * @return The position difference counter's value. + */ +static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) +{ + return base->POSD; +} + +/*! + * @brief Get the hold position difference counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position difference counter's value. + */ +static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) +{ + return base->POSDH; +} + +/*! + * @brief Get the position revolution counter's value. + * + * @param base ENC peripheral base address. + * + * @return The position revolution counter's value. + */ +static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) +{ + return base->REV; +} +/*! + * @brief Get the hold position revolution counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position revolution counter's value. + */ +static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base) +{ + return base->REVH; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* _FSL_ENC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.c new file mode 100644 index 0000000000000000000000000000000000000000..7a21a1ce0ea8f79710b5397df03474c98731bb9e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/*! + * @brief Used for conversion between `void*` and `uint32_t`. + */ +typedef union pvoid_to_u32 +{ + void *pvoid; + uint32_t u32; +} pvoid_to_u32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + pvoid_to_u32_t BaseAddr; + BaseAddr.pvoid = base; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); + return i; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + uint32_t idx = FLEXCOMM_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = flexcommHandle; + s_flexcommIrqHandler[instance] = handler; + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void); +void FLEXCOMM0_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM0); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void); +void FLEXCOMM1_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM1); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void); +void FLEXCOMM2_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM2); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void); +void FLEXCOMM3_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM3); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void); +void FLEXCOMM4_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM4); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void); +void FLEXCOMM5_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM5); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void); +void FLEXCOMM6_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM6); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void); +void FLEXCOMM7_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM7); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void); +void FLEXCOMM8_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM8); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void); +void FLEXCOMM9_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM9); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void); +void FLEXCOMM10_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM10); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void); +void FLEXCOMM11_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM11); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void); +void FLEXCOMM12_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM12); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void); +void FLEXCOMM13_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM13); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void); +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void); +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM15); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void); +void FLEXCOMM16_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM16); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.h new file mode 100644 index 0000000000000000000000000000000000000000..f96086fdecc02e2f158da81ab3bb82913cd49b6d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.2. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.c new file mode 100644 index 0000000000000000000000000000000000000000..7964163917f82fa7f94d411bb049033adb81cb17 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.c @@ -0,0 +1,1180 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexspi" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FREQ_1MHz (1000000UL) +#define FLEXSPI_DLLCR_DEFAULT (0x100UL) +#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0UL) + +enum +{ + kFLEXSPI_DelayCellUnitMin = 75, /* 75ps. */ + kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */ +}; + +enum +{ + kFLEXSPI_FlashASampleClockSlaveDelayLocked = + FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */ + kFLEXSPI_FlashASampleClockRefDelayLocked = + FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */ +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) + kFLEXSPI_FlashBSampleClockSlaveDelayLocked = + FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */ +#endif +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) + kFLEXSPI_FlashBSampleClockRefDelayLocked = + FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */ +#endif +}; + +/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */ +enum +{ + /*! IRQ sources enabled by the non-blocking transactional API. */ + kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExecutionDoneFlag, + + /*! Errors to check for. */ + kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag, +}; + +/* FLEXSPI transfer state, _flexspi_transfer_state. */ +enum +{ + kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ + kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ + kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void FLEXSPI_Memset(void *src, uint8_t value, size_t length); + +/*! + * @brief Calculate flash A/B sample clock DLL. + * + * @param base FLEXSPI base pointer. + * @param config Flash configuration parameters. + */ +static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexspi bases for each instance. */ +static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; + +/*! @brief Pointers to flexspi IRQ number for each instance. */ +static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +/*! @brief Pointers to flexspi handles for each instance. */ +static flexspi_handle_t *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)]; +#endif + +#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET +/*! @brief Pointers to FLEXSPI resets for each instance. */ +static const reset_ip_name_t s_flexspiResets[] = FLEXSPI_RSTS; +#endif + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +/*! @brief Pointer to flexspi IRQ handler. */ +static flexspi_isr_t s_flexspiIsr; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +/* To avoid compiler opitimizing this API into memset() in library. */ +#if defined(__ICCARM__) +#pragma optimize = none +#endif /* defined(__ICCARM__) */ +static void FLEXSPI_Memset(void *src, uint8_t value, size_t length) +{ + assert(src != NULL); + uint8_t *p = src; + + for (uint32_t i = 0U; i < length; i++) + { + *p = value; + p++; + } +} + +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++) + { + if (s_flexspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexspiBases)); + + return instance; +} + +static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config) +{ + bool isUnifiedConfig = true; + uint32_t flexspiDllValue; + uint32_t dllValue; + uint32_t temp; +#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_PS) && FSL_FEATURE_FLEXSPI_DQS_DELAY_PS + uint32_t internalDqsDelayPs = FSL_FEATURE_FLEXSPI_DQS_DELAY_PS; +#endif + uint32_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT; + switch (rxSampleClock) + { + case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackInternally: + case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromDqsPad: + case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromSckPad: + isUnifiedConfig = true; + break; + case (uint32_t)kFLEXSPI_ReadSampleClkExternalInputFromDqsPad: + if (config->isSck2Enabled) + { + isUnifiedConfig = true; + } + else + { + isUnifiedConfig = false; + } + break; + default: + assert(false); + break; + } + + if (isUnifiedConfig) + { + flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */ + } + else + { + if (config->flexspiRootClk >= 100U * FREQ_1MHz) + { +#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN) && FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN + /* DLLEN = 1, SLVDLYTARGET = 0x0, */ + flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x00); +#else + /* DLLEN = 1, SLVDLYTARGET = 0xF, */ + flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F); +#endif + } + else + { + temp = (uint32_t)config->dataValidTime * 1000U; /* Convert data valid time in ns to ps. */ + dllValue = temp / (uint32_t)kFLEXSPI_DelayCellUnitMin; + if (dllValue * (uint32_t)kFLEXSPI_DelayCellUnitMin < temp) + { + dllValue++; + } + flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue); + } + } + return flexspiDllValue; +} + +status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. */ + status &= (uint32_t)kErrorFlags; + if (0U != status) + { + /* Select the correct error code.. */ + if (0U != (status & (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag)) + { + result = kStatus_FLEXSPI_SequenceExecutionTimeout; + } + else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag)) + { + result = kStatus_FLEXSPI_IpCommandSequenceError; + } + else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag)) + { + result = kStatus_FLEXSPI_IpCommandGrantTimeout; + } + else + { + assert(false); + } + + /* Clear the flags. */ + FLEXSPI_ClearInterruptStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + } + + return result; +} + +/*! + * brief Initializes the FLEXSPI module and internal state. + * + * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the + * input configure parameters. Users should call this function before any FLEXSPI operations. + * + * param base FLEXSPI peripheral base address. + * param config FLEXSPI configure structure. + */ +void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) +{ + uint32_t configValue = 0; + uint8_t i = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the flexspi clock */ + (void)CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET + /* Reset the FLEXSPI module */ + RESET_PeripheralReset(s_flexspiResets[FLEXSPI_GetInstance(base)]); +#endif + + /* Reset peripheral before configuring it. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + FLEXSPI_SoftwareReset(base); + + /* Configure MCR0 configuration items. */ + configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) | + FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) | + FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) | + FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) | + FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) | +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) + FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) | +#endif +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) + FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) | +#endif +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) + FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | +#endif + FLEXSPI_MCR0_MDIS_MASK; + base->MCR0 = configValue; + + /* Configure MCR1 configurations. */ + configValue = + FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle); + base->MCR1 = configValue; + + /* Configure MCR2 configurations. */ + configValue = base->MCR2; + configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + FLEXSPI_MCR2_SCKBDIFFOPT_MASK | +#endif + FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); + configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | +#endif + FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | + FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); + + base->MCR2 = configValue; + + /* Configure AHB control items. */ + configValue = base->AHBCR; + configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | + FLEXSPI_AHBCR_CACHABLEEN_MASK); + configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | + FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | + FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | + FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); + base->AHBCR = configValue; + + /* Configure AHB rx buffers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + configValue = base->AHBRXBUFCR0[i]; + + configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | + FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); + configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) | + FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | + FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | + FLEXSPI_AHBRXBUFCR0_BUFSZ((uint32_t)config->ahbConfig.buffer[i].bufferSize / 8U); + base->AHBRXBUFCR0[i] = configValue; + } + + /* Configure IP Fifo watermarks. */ + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK((uint32_t)config->rxWatermark / 8U - 1U); + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U); + + /* Reset flash size on all ports */ + for (i = 0; i < (uint32_t)kFLEXSPI_PortCount; i++) + { + base->FLSHCR0[i] = 0; + } +} + +/*! + * brief Gets default settings for FLEXSPI. + * + * param config FLEXSPI configuration structure. + */ +void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) +{ + /* Initializes the configure structure to zero. */ + FLEXSPI_Memset(config, 0, sizeof(*config)); + + config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; + config->enableSckFreeRunning = false; +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) + config->enableCombination = false; +#endif + config->enableDoze = true; + config->enableHalfSpeedAccess = false; +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + config->enableSckBDiffOpt = false; +#endif + config->enableSameConfigForAll = false; + config->seqTimeoutCycle = 0xFFFFU; + config->ipGrantTimeoutCycle = 0xFFU; + config->txWatermark = 8; + config->rxWatermark = 8; +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) + config->ahbConfig.enableAHBWriteIpTxFifo = false; +#endif +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) + config->ahbConfig.enableAHBWriteIpRxFifo = false; +#endif + config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; + config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; + config->ahbConfig.resumeWaitCycle = 0x20U; + FLEXSPI_Memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); + /* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */ + for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++) + { + config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ + config->ahbConfig.buffer[i].masterIndex = 0xFU; /* Invalid master index which is not used, so will never hit. */ + config->ahbConfig.buffer[i].bufferSize = + 0; /* Default buffer size 0 for buffer0 to buffer(FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 3U)*/ + } + + for (uint8_t i = ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); + i < (uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ + config->ahbConfig.buffer[i].bufferSize = 256U; /* Default buffer size 256 bytes. */ + } + config->ahbConfig.enableClearAHBBufferOpt = false; + config->ahbConfig.enableReadAddressOpt = false; + config->ahbConfig.enableAHBPrefetch = false; + config->ahbConfig.enableAHBBufferable = false; + config->ahbConfig.enableAHBCachable = false; +} + +/*! + * brief Deinitializes the FLEXSPI module. + * + * Clears the FLEXSPI state and FLEXSPI module registers. + * param base FLEXSPI peripheral base address. + */ +void FLEXSPI_Deinit(FLEXSPI_Type *base) +{ + /* Reset peripheral. */ + FLEXSPI_SoftwareReset(base); +} + +/*! + * brief Update FLEXSPI DLL value depending on currently flexspi root clock. + * + * param base FLEXSPI peripheral base address. + * param config Flash configuration parameters. + * param port FLEXSPI Operation port. + */ +void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) +{ + uint32_t configValue = 0; + uint32_t statusValue = 0; + uint8_t index = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */ + + /* Wait for bus to be idle before changing flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Configure DLL. */ + configValue = FLEXSPI_CalculateDll(base, config); + base->DLLCR[index] = configValue; + + /* Exit stop mode. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ + if (index == 0U) + { + statusValue = + ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked); + } +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) + else + { + statusValue = + ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked); + } +#endif + if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK)) + { + /* Wait slave delay line locked and slave reference delay line locked. */ + while ((base->STS2 & statusValue) != statusValue) + { + } + + /* Wait at least 100 NOPs*/ + for (uint8_t delay = 100U; delay > 0U; delay--) + { + __NOP(); + } + } +} + +/*! + * brief Configures the connected device parameter. + * + * This function configures the connected device relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * connected device. + * + * param base FLEXSPI peripheral base address. + * param config Flash configuration parameters. + * param port FLEXSPI Operation port. + */ +void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) +{ + uint32_t configValue = 0; + uint8_t index = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */ + + /* Wait for bus to be idle before changing flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Configure flash size. */ + base->FLSHCR0[port] = config->flashSize; + + /* Configure flash parameters. */ + base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) | + FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) | + FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) | + FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress); + + /* Configure AHB operation items. */ + configValue = base->FLSHCR2[port]; + + configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK | + FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_ARDSEQID_MASK); + + configValue |= + FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval); + + if (config->AWRSeqNumber > 0U) + { + configValue |= FLEXSPI_FLSHCR2_AWRSEQID((uint32_t)config->AWRSeqIndex) | + FLEXSPI_FLSHCR2_AWRSEQNUM((uint32_t)config->AWRSeqNumber - 1U); + } + + if (config->ARDSeqNumber > 0U) + { + configValue |= FLEXSPI_FLSHCR2_ARDSEQID((uint32_t)config->ARDSeqIndex) | + FLEXSPI_FLSHCR2_ARDSEQNUM((uint32_t)config->ARDSeqNumber - 1U); + } + + base->FLSHCR2[port] = configValue; + + /* Configure DLL. */ + FLEXSPI_UpdateDllValue(base, config, port); + + /* Step into stop mode. */ + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; + + /* Configure write mask. */ + if (config->enableWriteMask) + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + else + { + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + + if (index == 0U) /*PortA*/ + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask); + } +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) + else + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK; + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask); + } +#endif + + /* Exit stop mode. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* Wait for bus to be idle before use it access to external flash. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } +} + +/*! brief Updates the LUT table. + * + * param base FLEXSPI peripheral base address. + * param index From which index start to update. It could be any index of the LUT table, which + * also allows user to update command content inside a command. Each command consists of up to + * 8 instructions and occupy 4*32-bit memory. + * param cmd Command sequence array. + * param count Number of sequences. + */ +void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) +{ + assert(index < 64U); + + uint32_t i = 0; + volatile uint32_t *lutBase; + + /* Wait for bus to be idle before changing flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Unlock LUT for update. */ +#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) + base->LUTKEY = FLEXSPI_LUT_KEY_VAL; +#endif + base->LUTCR = 0x02; + + lutBase = &base->LUT[index]; + for (i = 0; i < count; i++) + { + *lutBase++ = *cmd++; + } + + /* Lock LUT. */ +#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) + base->LUTKEY = FLEXSPI_LUT_KEY_VAL; +#endif + base->LUTCR = 0x01; +} + +/*! brief Update read sample clock source + * + * param base FLEXSPI peripheral base address. + * param clockSource clockSource of type #flexspi_read_sample_clock_t + */ +void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource) +{ + uint32_t mcr0Val; + + /* Wait for bus to be idle before changing flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + mcr0Val = base->MCR0; + mcr0Val &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; + mcr0Val |= FLEXSPI_MCR0_RXCLKSRC(clockSource); + base->MCR0 = mcr0Val; + + /* Reset peripheral. */ + FLEXSPI_SoftwareReset(base); +} + +/*! + * brief Sends a buffer of data bytes using blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base FLEXSPI peripheral base address + * param buffer The data bytes to send + * param size The number of data bytes to send + * retval kStatus_Success write success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U; + uint32_t status; + status_t result = kStatus_Success; + uint32_t i = 0; + + /* Send data buffer */ + while (0U != size) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) + { + } + + result = FLEXSPI_CheckAndClearError(base, status); + + if (kStatus_Success != result) + { + return result; + } + + /* Write watermark level data into tx fifo . */ + if (size >= 8U * txWatermark) + { + for (i = 0U; i < 2U * txWatermark; i++) + { + base->TFDR[i] = *buffer++; + } + + size = size - 8U * txWatermark; + } + else + { + for (i = 0U; i < ((size + 3U) / 4U); i++) + { + base->TFDR[i] = *buffer++; + } + size = 0U; + } + + /* Push a watermark level data into IP TX FIFO. */ + base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; + } + + return result; +} + +/*! + * brief Receives a buffer of data bytes using a blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base FLEXSPI peripheral base address + * param buffer The data bytes to send + * param size The number of data bytes to receive + * retval kStatus_Success read success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint32_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U; + uint32_t status; + status_t result = kStatus_Success; + uint32_t i = 0; + bool isReturn = false; + + /* Send data buffer */ + while (0U != size) + { + if (size >= 8U * rxWatermark) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) + { + result = FLEXSPI_CheckAndClearError(base, status); + + if (kStatus_Success != result) + { + isReturn = true; + break; + } + } + } + else + { + /* Wait fill level. This also checks for errors. */ + while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U)) + { + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + if (kStatus_Success != result) + { + isReturn = true; + break; + } + } + } + + if (isReturn) + { + break; + } + + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + if (kStatus_Success != result) + { + break; + } + + /* Read watermark level data from rx fifo . */ + if (size >= 8U * rxWatermark) + { + for (i = 0U; i < 2U * rxWatermark; i++) + { + *buffer++ = base->RFDR[i]; + } + + size = size - 8U * rxWatermark; + } + else + { + for (i = 0U; i < ((size + 3U) / 4U); i++) + { + *buffer++ = base->RFDR[i]; + } + size = 0; + } + + /* Pop out a watermark level datas from IP RX FIFO. */ + base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + } + + return result; +} + +/*! + * brief Execute command to transfer a buffer data bytes using a blocking method. + * param base FLEXSPI peripheral base address + * param xfer pointer to the transfer structure. + * retval kStatus_Success command transfer success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this transfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base address. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= + FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U); + base->IPCR1 = configValue; + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + result = FLEXSPI_WriteBlocking(base, xfer->data, xfer->dataSize); + } + else if (xfer->cmdType == kFLEXSPI_Read) + { + result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize); + } + else + { + /* Empty else. */ + } + + /* Wait for bus to be idle before changing flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + if (xfer->cmdType == kFLEXSPI_Command) + { + result = FLEXSPI_CheckAndClearError(base, base->INTR); + } + + return result; +} + +/*! + * brief Initializes the FLEXSPI handle which is used in transactional functions. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ +void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, + flexspi_handle_t *handle, + flexspi_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance = FLEXSPI_GetInstance(base); + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ + /* Save the context in global variables to support the double weak mechanism. */ + s_flexspiHandle[instance] = handle; + s_flexspiIsr = FLEXSPI_TransferHandleIRQ; +#endif + + /* Enable NVIC interrupt. */ + (void)EnableIRQ(s_flexspiIrqs[instance]); +} + +/*! + * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. + * + * note Calling the API returns immediately after transfer initiates. The user needs + * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer + * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or + * FLEXSPI could not read data properly. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state. + * param xfer pointer to flexspi_transfer_t structure. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_FLEXSPI_Busy Previous transmission still not finished. + */ +status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + assert(NULL != handle); + assert(NULL != xfer); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != (uint32_t)kFLEXSPI_Idle) + { + result = kStatus_FLEXSPI_Busy; + } + else + { + handle->data = xfer->data; + handle->dataSize = xfer->dataSize; + handle->transferTotalSize = xfer->dataSize; + handle->state = (xfer->cmdType == kFLEXSPI_Read) ? (uint32_t)kFLEXSPI_BusyRead : (uint32_t)kFLEXSPI_BusyWrite; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this transfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base address. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= + FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U); + base->IPCR1 = configValue; + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + if (handle->state == (uint32_t)kFLEXSPI_BusyRead) + { + FLEXSPI_EnableInterrupts(base, (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag | + (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag | + (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | + (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag | + (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag); + } + else + { + FLEXSPI_EnableInterrupts( + base, (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag | (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag | + (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag | + (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag); + } + } + + return result; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->state == (uint32_t)kFLEXSPI_Idle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferTotalSize - handle->dataSize; + } + + return result; +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state + */ +void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) +{ + assert(NULL != handle); + + FLEXSPI_DisableInterrupts(base, (uint32_t)kIrqFlags); + handle->state = (uint32_t)kFLEXSPI_Idle; +} + +/*! + * brief Master interrupt handler. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure. + */ +void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) +{ + uint32_t status; + status_t result; + uint32_t intEnableStatus; + uint32_t txWatermark; + uint32_t rxWatermark; + uint8_t i = 0; + + status = base->INTR; + intEnableStatus = base->INTEN; + + /* Check if interrupt is enabled and status is alerted. */ + if ((status & intEnableStatus) != 0U) + { + result = FLEXSPI_CheckAndClearError(base, status); + + if ((result != kStatus_Success) && (handle->completionCallback != NULL)) + { + FLEXSPI_TransferAbort(base, handle); + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } + else + { + if ((0U != (status & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) && + (handle->state == (uint32_t)kFLEXSPI_BusyRead)) + { + rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U; + + /* Read watermark level data from rx fifo . */ + if (handle->dataSize >= 8U * rxWatermark) + { + /* Read watermark level data from rx fifo . */ + for (i = 0U; i < 2U * rxWatermark; i++) + { + *handle->data++ = base->RFDR[i]; + } + + handle->dataSize = handle->dataSize - 8U * rxWatermark; + } + else + { + for (i = 0; i < (handle->dataSize + 3U) / 4U; i++) + { + *handle->data++ = base->RFDR[i]; + } + handle->dataSize = 0; + } + /* Pop out a watermark level data from IP RX FIFO. */ + base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + } + + if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag)) + { + base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; + + FLEXSPI_TransferAbort(base, handle); + + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + } + + /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */ + if ((0U != (status & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) && + (handle->state == (uint32_t)kFLEXSPI_BusyWrite)) + { + if (0U != handle->dataSize) + { + txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U; + /* Write watermark level data into tx fifo . */ + if (handle->dataSize >= 8U * txWatermark) + { + for (i = 0; i < 2U * txWatermark; i++) + { + base->TFDR[i] = *handle->data++; + } + + handle->dataSize = handle->dataSize - 8U * txWatermark; + } + else + { + for (i = 0; i < (handle->dataSize + 3U) / 4U; i++) + { + base->TFDR[i] = *handle->data++; + } + handle->dataSize = 0; + } + + /* Push a watermark level data into IP TX FIFO. */ + base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; + } + } + else + { + /* Empty else */ + } + } + } + else + { + /* Empty else */ + } +} + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#if defined(FLEXSPI) +void FLEXSPI_DriverIRQHandler(void); +void FLEXSPI_DriverIRQHandler(void) +{ + s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXSPI0) +void FLEXSPI0_DriverIRQHandler(void); +void FLEXSPI0_DriverIRQHandler(void) +{ + s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(FLEXSPI1) +void FLEXSPI1_DriverIRQHandler(void); +void FLEXSPI1_DriverIRQHandler(void) +{ + s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(LSIO__FLEXSPI0) +void LSIO_OCTASPI0_INT_DriverIRQHandler(void); +void LSIO_OCTASPI0_INT_DriverIRQHandler(void) +{ + s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(LSIO__FLEXSPI1) +void LSIO_OCTASPI1_INT_DriverIRQHandler(void); +void LSIO_OCTASPI1_INT_DriverIRQHandler(void) +{ + s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 + +void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void); +void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_flexspiHandle[0]) + { + s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); + } + if (NULL != s_flexspiHandle[1]) + { + s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]); + } +} +#endif + +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.h new file mode 100644 index 0000000000000000000000000000000000000000..5269d439daf1e6726703386ab602722046e2df6a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi.h @@ -0,0 +1,874 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_FLEXSPI_H_ +#define __FSL_FLEXSPI_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/*! + * @addtogroup flexspi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLEXSPI driver version 2.3.5. */ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) +/*@}*/ + +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) + +/*! @brief Formula to form FLEXSPI instructions in LUT table. */ +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/*! @brief Status structure of FLEXSPI.*/ +enum +{ + kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ + kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout + error occurred during FLEXSPI transfer. */ + kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution + timeout error occurred during FLEXSPI transfer. */ + kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error + occurred during FLEXSPI transfer. */ +}; + +/*! @brief CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command. */ +enum +{ + kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ + kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ + kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ + kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ + kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ + kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ + kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ + kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, + dummy cycles decided by RWDS. */ + kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ + kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ + kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ + kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ + kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ + kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ + kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, + dummy cycles decided by RWDS. */ + kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the + instruction start pointer for next sequence */ +}; + +/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */ +typedef enum _flexspi_pad +{ + kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */ + kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */ + kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */ + kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */ +} flexspi_pad_t; + +/*! @brief FLEXSPI interrupt status flags.*/ +typedef enum _flexspi_flags +{ + kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ +#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN + kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */ +#else + kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ +#endif + kFLEXSPI_SckStoppedBecauseTxEmptyFlag = + FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command + sequence because Async TX FIFO empty. */ + kFLEXSPI_SckStoppedBecauseRxFullFlag = + FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command + sequence because Async RX FIFO full. */ +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) + kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ +#endif + kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ + kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ + kFLEXSPI_AhbCommandSequenceErrorFlag = + FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ + kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */ + kFLEXSPI_AhbCommandGrantTimeoutFlag = + FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */ + kFLEXSPI_IpCommandGrantTimeoutFlag = + FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */ + kFLEXSPI_IpCommandExecutionDoneFlag = + FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */ + kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */ +} flexspi_flags_t; + +/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/ +typedef enum _flexspi_read_sample_clock +{ + kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller + and loopback internally. */ + kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller + and loopback from DQS pad. */ + kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ + kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ +} flexspi_read_sample_clock_t; + +/*! @brief FLEXSPI interval unit for flash device select.*/ +typedef enum _flexspi_cs_interval_cycle_unit +{ + kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ + kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ +} flexspi_cs_interval_cycle_unit_t; + +/*! @brief FLEXSPI AHB wait interval unit for writing.*/ +typedef enum _flexspi_ahb_write_wait_unit +{ + kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ +} flexspi_ahb_write_wait_unit_t; + +/*! @brief Error Code when IP command Error detected.*/ +typedef enum _flexspi_ip_error_code +{ + kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ + kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR + used in DDR sequence. */ + kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR + used in SDR sequence. */ + kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole + flash address range (A1/A2/B1/B2). */ + kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ + kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ +} flexspi_ip_error_code_t; + +/*! @brief Error Code when AHB command Error detected.*/ +typedef enum _flexspi_ahb_error_code +{ + kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction + used in the sequence. */ + kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used + in DDR sequence. */ + kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR + used in SDR sequence. */ + kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */ +} flexspi_ahb_error_code_t; + +/*! @brief FLEXSPI operation port select.*/ +typedef enum _flexspi_port +{ + kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ + kFLEXSPI_PortA2, /*!< Access flash on A2 port. */ +#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) + kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ + kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ +#endif + kFLEXSPI_PortCount +} flexspi_port_t; + +/*! @brief Trigger source of current command sequence granted by arbitrator.*/ +typedef enum _flexspi_arb_command_source +{ + kFLEXSPI_AhbReadCommand = 0x0U, + kFLEXSPI_AhbWriteCommand = 0x1U, + kFLEXSPI_IpCommand = 0x2U, + kFLEXSPI_SuspendedCommand = 0x3U, +} flexspi_arb_command_source_t; + +/*! @brief Command type. */ +typedef enum _flexspi_command_type +{ + kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */ + kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */ + kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */ +} flexspi_command_type_t; + +typedef struct _flexspi_ahbBuffer_config +{ + uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ + uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ + uint16_t bufferSize; /*!< AHB buffer size in byte. */ + bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows + prefetch disable/enable separately for each master. */ +} flexspi_ahbBuffer_config_t; + +/*! @brief FLEXSPI configuration structure. */ +typedef struct _flexspi_config +{ + flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */ + bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */ +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) + bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins + (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ +#endif + bool enableDoze; /*!< Enable/disable doze mode support. */ + bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half + speed commands. */ +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock + output, when enable, Port B flash access is not available. */ +#endif + bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices + when enabled, same configuration in FLASHA1CRx is applied to all. */ + uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, + timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */ + uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after + ipGrantTimeoutCycle*1024 AHB clock cycles. */ + uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */ + uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */ + struct + { +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) + bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */ +#endif +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) + bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */ +#endif + uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant, + timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */ + uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access, + timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ + uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence + resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ + flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ + bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer + when FLEXSPI returns STOP mode ACK. */ + bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. + when enable, there is no AHB read burst start address alignment limitation. */ + bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI + will fetch more data than current AHB burst. */ + bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, + FLEXSPI return before waiting for command execution finished. */ + bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */ + } ahbConfig; +} flexspi_config_t; + +/*! @brief External device configuration items. */ +typedef struct _flexspi_device_config +{ + uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */ + bool isSck2Enabled; /*!< FLEXSPI use SCK2. */ + uint32_t flashSize; /*!< Flash size in KByte. */ + flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */ + uint16_t CSInterval; /*!< CS line assert interval, multiply CS interval unit to + get the CS line assert interval cycles. */ + uint8_t CSHoldTime; /*!< CS line hold time. */ + uint8_t CSSetupTime; /*!< CS line setup time. */ + uint8_t dataValidTime; /*!< Data valid time for external device. */ + uint8_t columnspace; /*!< Column space size. */ + bool enableWordAddress; /*!< If enable word address.*/ + uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */ + uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */ + uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */ + uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */ + flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */ + uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, multiply AHB write interval + unit to get the AHB write wait cycles. */ + bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask + when writing to external device. */ +} flexspi_device_config_t; + +/*! @brief Transfer structure for FLEXSPI. */ +typedef struct _flexspi_transfer +{ + uint32_t deviceAddress; /*!< Operation device address. */ + flexspi_port_t port; /*!< Operation port. */ + flexspi_command_type_t cmdType; /*!< Execution command type. */ + uint8_t seqIndex; /*!< Sequence ID for command. */ + uint8_t SeqNumber; /*!< Sequence number for command. */ + uint32_t *data; /*!< Data buffer. */ + size_t dataSize; /*!< Data size in bytes. */ +} flexspi_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexspi_handle flexspi_handle_t; + +/*! @brief FLEXSPI transfer callback function. */ +typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, + flexspi_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Transfer handle structure for FLEXSPI. */ +struct _flexspi_handle +{ + uint32_t state; /*!< Internal state for FLEXSPI transfer */ + uint32_t *data; /*!< Data buffer. */ + size_t dataSize; /*!< Remaining Data size in bytes. */ + size_t transferTotalSize; /*!< Total Data size in bytes. */ + flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */ + void *userData; /*!< FLEXSPI callback function parameter.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Get the instance number for FLEXSPI. + * + * @param base FLEXSPI base pointer. + */ +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); + +/*! + * @brief Check and clear IP command execution errors. + * + * @param base FLEXSPI base pointer. + * @param status interrupt status. + */ +status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); + +/*! + * @brief Initializes the FLEXSPI module and internal state. + * + * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the + * input configure parameters. Users should call this function before any FLEXSPI operations. + * + * @param base FLEXSPI peripheral base address. + * @param config FLEXSPI configure structure. + */ +void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); + +/*! + * @brief Gets default settings for FLEXSPI. + * + * @param config FLEXSPI configuration structure. + */ +void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); + +/*! + * @brief Deinitializes the FLEXSPI module. + * + * Clears the FLEXSPI state and FLEXSPI module registers. + * @param base FLEXSPI peripheral base address. + */ +void FLEXSPI_Deinit(FLEXSPI_Type *base); + +/*! + * @brief Update FLEXSPI DLL value depending on currently flexspi root clock. + * + * @param base FLEXSPI peripheral base address. + * @param config Flash configuration parameters. + * @param port FLEXSPI Operation port. + */ +void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); + +/*! + * @brief Configures the connected device parameter. + * + * This function configures the connected device relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * connected device. + * + * @param base FLEXSPI peripheral base address. + * @param config Flash configuration parameters. + * @param port FLEXSPI Operation port. + */ +void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); + +/*! + * @brief Software reset for the FLEXSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * @param base FLEXSPI peripheral base address. + */ +static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) +{ + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)) + { + } +} + +/*! + * @brief Enables or disables the FLEXSPI module. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable FLEXSPI, false means disable. + */ +static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + } + else + { + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ +/*! + * @brief Enables the FLEXSPI interrupts. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disable the FLEXSPI interrupts. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/* @} */ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. + * + * @param base FLEXSPI peripheral base address. + * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. + */ +static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; + } + else + { + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; + } +} + +/*! + * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests. + * + * @param base FLEXSPI peripheral base address. + * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; + } + else + { + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; + } +} + +/*! + * @brief Gets FLEXSPI IP tx fifo address for DMA transfer. + * + * @param base FLEXSPI peripheral base address. + * @retval The tx fifo address. + */ +static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) +{ + return (uint32_t)&base->TFDR[0]; +} + +/*! + * @brief Gets FLEXSPI IP rx fifo address for DMA transfer. + * + * @param base FLEXSPI peripheral base address. + * @retval The rx fifo address. + */ +static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) +{ + return (uint32_t)&base->RFDR[0]; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! @brief Clears the FLEXSPI IP FIFO logic. + * + * @param base FLEXSPI peripheral base address. + * @param txFifo Pass true to reset TX FIFO. + * @param rxFifo Pass true to reset RX FIFO. + */ +static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) +{ + if (txFifo) + { + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + } + if (rxFifo) + { + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + } +} + +/*! + * @brief Gets the valid data entries in the FLEXSPI FIFOs. + * + * @param base FLEXSPI peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) +{ + if (NULL != txCount) + { + *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U; + } + if (NULL != rxCount) + { + *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; + } +} + +/*@}*/ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the FLEXSPI interrupt status flags. + * + * @param base FLEXSPI peripheral base address. + * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. + */ +static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Get the FLEXSPI interrupt status flags. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) +/*! @brief Gets the sampling clock phase selection after Data Learning. + * + * @param base FLEXSPI peripheral base address. + * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA. + * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB. + */ +static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase) +{ + if (portAPhase != NULL) + { + *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT); + } + +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) + if (portBPhase != NULL) + { + *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT); + } +#endif +} +#endif + +/*! @brief Gets the trigger source of current command sequence granted by arbitrator. + * + * @param base FLEXSPI peripheral base address. + * @retval trigger source of current command sequence. + */ +static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) +{ + return (flexspi_arb_command_source_t)( + (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT)); +} + +/*! @brief Gets the error code when IP command error detected. + * + * @param base FLEXSPI peripheral base address. + * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. + * @retval error code when IP command error detected. + */ +static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +{ + *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT); + return (flexspi_ip_error_code_t)( + (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT)); +} + +/*! @brief Gets the error code when AHB command error detected. + * + * @param base FLEXSPI peripheral base address. + * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. + * @retval error code when AHB command error detected. + */ +static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +{ + *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; + return (flexspi_ahb_error_code_t)( + (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)); +} + +/*! @brief Returns whether the bus is idle. + * + * @param base FLEXSPI peripheral base address. + * @retval true Bus is idle. + * @retval false Bus is busy. + */ +static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) +{ + return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)); +} +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! @brief Update read sample clock source + * + * @param base FLEXSPI peripheral base address. + * @param clockSource clockSource of type #flexspi_read_sample_clock_t + */ +void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource); + +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) +/*! @brief Enables/disables the FLEXSPI IP command parallel mode. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; + } + else + { + base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; + } +} +#endif + +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) +/*! @brief Enables/disables the FLEXSPI AHB command parallel mode. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK; + } + else + { + base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; + } +} +#endif + +/*! @brief Updates the LUT table. + * + * @param base FLEXSPI peripheral base address. + * @param index From which index start to update. It could be any index of the LUT table, which + * also allows user to update command content inside a command. Each command consists of up to + * 8 instructions and occupy 4*32-bit memory. + * @param cmd Command sequence array. + * @param count Number of sequences. + */ +void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); + +/*! + * @brief Writes data into FIFO. + * + * @param base FLEXSPI peripheral base address + * @param data The data bytes to send + * @param fifoIndex Destination fifo index. + */ +static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) +{ + base->TFDR[fifoIndex] = data; +} + +/*! + * @brief Receives data from data FIFO. + * + * @param base FLEXSPI peripheral base address + * @param fifoIndex Source fifo index. + * @return The data in the FIFO. + */ +static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) +{ + return base->RFDR[fifoIndex]; +} + +/*! + * @brief Sends a buffer of data bytes using blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base FLEXSPI peripheral base address + * @param buffer The data bytes to send + * @param size The number of data bytes to send + * @retval kStatus_Success write success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receives a buffer of data bytes using a blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base FLEXSPI peripheral base address + * @param buffer The data bytes to send + * @param size The number of data bytes to receive + * @retval kStatus_Success read success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Execute command to transfer a buffer data bytes using a blocking method. + * @param base FLEXSPI peripheral base address + * @param xfer pointer to the transfer structure. + * @retval kStatus_Success command transfer success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXSPI handle which is used in transactional functions. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, + flexspi_handle_t *handle, + flexspi_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer + * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or + * FLEXSPI could not read data properly. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state. + * @param xfer pointer to flexspi_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished. + */ +status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state + */ +void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure. + */ +void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* __FSL_FLEXSPI_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..7a06f6fc540c8a0b842c616730f26d991845f207 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.c @@ -0,0 +1,646 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexspi_dma" +#endif + +/* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE) ? \ + FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE : \ + FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE) +#endif +#if defined(__ICCARM__) +#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE +static dma_descriptor_t s_flexspiDes[FLEXSPI_DMA_DES_COUNT]; +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__(( + aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t s_flexspiDes[FLEXSPI_DMA_DES_COUNT]; +#elif defined(__GNUC__) +__attribute__(( + aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t s_flexspiDes[FLEXSPI_DMA_DES_COUNT]; +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief FLEXSPI DMA transfer finished callback function. + * + * This function is called when FLEXSPI DMA transfer finished. It disables the FLEXSPI + * TX/RX DMA request and sends status to FLEXSPI callback. + * + * @param handle The DMA handle. + * @param param Callback function parameter. + */ +static void FLEXSPI_TransferDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief FLEXSPI Write DMA data. + * + * This function is called in FLEXSPI DMA transfer. It configures Write DMA and prepare DMA data transfer. + * + * @param base FLEXSPI peripheral base address. + * @param handle The DMA handle. + * @param data pointer to data buffer which stores the transmit data + * @param dataSize size for transmit data buffer . + */ +static status_t FLEXSPI_WriteDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize); + +/*! + * @brief FLEXSPI Read DMA data. + * + * This function is called in FLEXSPI DMA transfer. It configures Read DMA and prepare DMA data transfer. + * + * @param base FLEXSPI peripheral base address. + * @param handle The DMA handle. + * @param data pointer to data buffer which stores the receive data + * @param dataSize size for receive data buffer . + */ +static status_t FLEXSPI_ReadDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize); +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) && FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) +static uint8_t FLEXSPI_CalculatePower(uint8_t value) +{ + uint8_t power = 0; + while (value >> 1 != 0U) + { + power++; + value = value >> 1; + } + + return power; +} +#endif + +static void FLEXSPI_TransferDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + flexspi_dma_private_handle_t *flexspiPrivateHandle = (flexspi_dma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(flexspiPrivateHandle->base)) + { + } + /* Disable transfer. */ + FLEXSPI_TransferAbortDMA(flexspiPrivateHandle->base, flexspiPrivateHandle->handle); + + if (flexspiPrivateHandle->handle->completionCallback != NULL) + { + flexspiPrivateHandle->handle->completionCallback(flexspiPrivateHandle->base, flexspiPrivateHandle->handle, + kStatus_Success, flexspiPrivateHandle->handle->userData); + } + } +} + +static status_t FLEXSPI_WriteDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize) +{ + void *txFifoBase = (void *)(uint32_t *)FLEXSPI_GetTxFifoAddress(base); + void *nextDesc = NULL; + dma_channel_trigger_t dmaTxTriggerConfig; + dma_channel_config_t txChannelConfig; + uint32_t bytesPerDes; + uint8_t desCount; + uint8_t remains; + uint32_t srcInc; + uint32_t dstInc; + + /* Source address interleave size */ + srcInc = kDMA_AddressInterleave1xWidth; + /* Destination address interleave size */ + dstInc = kDMA_AddressInterleave1xWidth; + + /* Check the xfer->data start address follows the alignment */ + if (((uint32_t)data & ((uint32_t)handle->nsize - 1U)) != 0U) + { + return kStatus_InvalidArgument; + } + + handle->count = + 8U * ((uint8_t)(((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U)); + + /* Check the handle->count is power of 2 */ + if (((handle->count) & (handle->count - 1U)) != 0U) + { + return kStatus_InvalidArgument; + } + +#if defined(FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) && FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES + if (dataSize < handle->count) + { + handle->nsize = kFLEXPSI_DMAnSize1Bytes; + handle->nbytes = (uint8_t)dataSize; + } + else + { + /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ + handle->nbytes = handle->count; + } + + handle->transferSize = dataSize; + dmaTxTriggerConfig.burst = kDMA_SingleTransfer; + dmaTxTriggerConfig.type = kDMA_HighLevelTrigger; + dmaTxTriggerConfig.wrap = kDMA_NoWrap; + + /* Configure linked descriptors to start FLEXSPI Tx DMA transfer to provide software workaround for + ERRATA FLEXSPI.1: Using FLEXSPI register interface, TX buffer fill / RX buffer drain by DMA with a + single DMA descriptor cannot be performed. */ + desCount = (uint8_t)(dataSize / (uint32_t)handle->nbytes); + bytesPerDes = handle->nbytes; + remains = (uint8_t)(dataSize - (uint32_t)desCount * (uint32_t)handle->nbytes); + if (remains > 0U) + { + uint32_t width = (uint32_t)kFLEXPSI_DMAnSize1Bytes; + DMA_SetupDescriptor(&s_flexspiDes[desCount - 1U], + DMA_CHANNEL_XFER(false, true, true, false, width, srcInc, dstInc, remains), + (void *)(uint64_t *)((uint32_t)data + desCount * bytesPerDes), txFifoBase, NULL); + nextDesc = &s_flexspiDes[desCount - 1U]; + } + + remains = (uint8_t)bytesPerDes; +#else + uint32_t dmaTriggerBurst; + dmaTxTriggerConfig.type = kDMA_RisingEdgeTrigger; + bytesPerDes = dataSize; + + if (dataSize < handle->count) + { + handle->nsize = kFLEXPSI_DMAnSize1Bytes; + handle->nbytes = (uint8_t)(dataSize / (uint32_t)handle->nsize); + dmaTxTriggerConfig.wrap = kDMA_NoWrap; + + /* Check the handle->nbytes is power of 2 */ + if (((handle->nbytes) & (handle->nbytes - 1U)) != 0U) + { + handle->nbytes = 2U * ((handle->nbytes) & (handle->nbytes - 1U)); + } + + desCount = 1U; + } + else + { + dmaTxTriggerConfig.wrap = kDMA_DstWrap; + remains = (uint8_t)(dataSize % (uint32_t)handle->count); + if (remains == 0U) + { + desCount = 1U; + } + else + { + desCount = 2U; + bytesPerDes = dataSize - remains; + if ((remains & 3U) == 0U) + { + handle->nsize = kFLEXPSI_DMAnSize4Bytes; + } + else if ((remains & 1U) == 0U) + { + handle->nsize = kFLEXPSI_DMAnSize2Bytes; + } + else + { + handle->nsize = kFLEXPSI_DMAnSize1Bytes; + } + } + /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ + handle->nbytes = handle->count / (uint8_t)handle->nsize; + + /* Check if dataSize exceeds the maximum transfer count supported by the driver. */ + if ((dataSize - handle->count + 1U) / ((uint32_t)handle->nsize) > 1024U) + { + return kStatus_InvalidArgument; + } + } + + /* xfer->dataSize needs to be larger than 1 due to hardware limitation */ + if (dataSize / (uint8_t)handle->nsize == 1U) + { + return kStatus_InvalidArgument; + } + + dmaTriggerBurst = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(FLEXSPI_CalculatePower(handle->nbytes)); + dmaTxTriggerConfig.burst = (dma_trigger_burst_t)dmaTriggerBurst; + handle->transferSize = dataSize; +#endif + + for (uint8_t i = desCount - 1U; i > 0U; i--) + { + DMA_SetupDescriptor(&s_flexspiDes[i - 1U], + DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, + false, (uint32_t)handle->nsize, srcInc, dstInc, remains), + (void *)(uint64_t *)((uint32_t)data + i * bytesPerDes), txFifoBase, nextDesc); + nextDesc = &s_flexspiDes[i - 1U]; + } + + DMA_PrepareChannelTransfer( + &txChannelConfig, (void *)data, txFifoBase, + DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, false, + (uint32_t)handle->nsize, srcInc, dstInc, bytesPerDes), + kDMA_MemoryToMemory, &dmaTxTriggerConfig, nextDesc); + + (void)DMA_SubmitChannelTransfer(handle->txDmaHandle, &txChannelConfig); + + DMA_SetCallback(handle->txDmaHandle, FLEXSPI_TransferDMACallback, &s_dmaPrivateHandle[FLEXSPI_GetInstance(base)]); + DMA_StartTransfer(handle->txDmaHandle); + + /* Enable FLEXSPI TX DMA. */ + FLEXSPI_EnableTxDMA(base, true); + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + return kStatus_Success; +} + +static status_t FLEXSPI_ReadDataDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, uint32_t *data, size_t dataSize) +{ + dma_channel_trigger_t dmaRxTriggerConfig; + void *rxFifoBase = (void *)(uint32_t *)FLEXSPI_GetRxFifoAddress(base); + void *nextDesc = NULL; + dma_channel_config_t rxChannelConfig; + uint32_t bytesPerDes; + uint8_t remains; + uint8_t desCount; + uint32_t srcInc; + uint32_t dstInc; + + /* Source address interleave size */ + srcInc = kDMA_AddressInterleave1xWidth; + /* Destination address interleave size */ + dstInc = kDMA_AddressInterleave1xWidth; + + handle->count = + 8U * (uint8_t)(((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U); + + /* Check the watermark is power of 2U */ + if ((handle->count & (handle->count - 1U)) != 0U) + { + return kStatus_InvalidArgument; + } + +#if defined(FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES) && FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES + if (dataSize < handle->count) + { + handle->nsize = kFLEXPSI_DMAnSize1Bytes; + handle->nbytes = (uint8_t)dataSize; + } + else + { + /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ + handle->nbytes = handle->count; + } + + dmaRxTriggerConfig.burst = kDMA_SingleTransfer; + dmaRxTriggerConfig.type = kDMA_HighLevelTrigger; + dmaRxTriggerConfig.wrap = kDMA_NoWrap; + + /* Configure linked descriptors to start FLEXSPI Tx DMA transfer to provide software workaround for + ERRATA FLEXSPI.1: Using FLEXSPI register interface, TX buffer fill / RX buffer drain by DMA with a + single DMA descriptor cannot be performed. */ + desCount = (uint8_t)(dataSize / (uint32_t)handle->nbytes); + bytesPerDes = handle->nbytes; + remains = (uint8_t)(dataSize - (uint32_t)desCount * (uint32_t)handle->nbytes); + + if (remains > 0U) + { + uint32_t width = (uint32_t)kFLEXPSI_DMAnSize1Bytes; + DMA_SetupDescriptor(&s_flexspiDes[desCount - 1U], + DMA_CHANNEL_XFER(false, true, true, false, width, srcInc, dstInc, remains), rxFifoBase, + (void *)(uint64_t *)((uint32_t)data + desCount * bytesPerDes), NULL); + nextDesc = &s_flexspiDes[desCount - 1U]; + } + remains = (uint8_t)bytesPerDes; + +#else + uint32_t dmaTriggerBurst; + dmaRxTriggerConfig.type = kDMA_RisingEdgeTrigger; + bytesPerDes = dataSize; + + if (dataSize < handle->count) + { + handle->nsize = kFLEXPSI_DMAnSize1Bytes; + handle->nbytes = (uint8_t)(dataSize / (uint32_t)handle->nsize); + dmaRxTriggerConfig.wrap = kDMA_NoWrap; + /* Check the handle->nbytes is power of 2 */ + if (((handle->nbytes) & (handle->nbytes - 1U)) != 0U) + { + handle->nbytes = 2U * ((handle->nbytes) & (handle->nbytes - 1U)); + } + desCount = 1U; + } + else + { + dmaRxTriggerConfig.wrap = kDMA_SrcWrap; + remains = (uint8_t)(dataSize % (uint32_t)handle->count); + if (remains == 0U) + { + desCount = 1U; + } + else + { + desCount = 2U; + bytesPerDes = dataSize - remains; + if ((remains & 3U) == 0U) + { + handle->nsize = kFLEXPSI_DMAnSize4Bytes; + } + else if ((remains & 1U) == 0U) + { + handle->nsize = kFLEXPSI_DMAnSize2Bytes; + } + else + { + handle->nsize = kFLEXPSI_DMAnSize1Bytes; + } + } + /* Store the initially configured dma minor byte transfer count into the FLEXSPI handle */ + handle->nbytes = handle->count / (uint8_t)handle->nsize; + + /* Check dataSize exceeds the maximum transfer count supported by the driver. */ + if ((dataSize - handle->count + 1U) / ((uint32_t)handle->nsize) > 1024U) + { + return kStatus_InvalidArgument; + } + } + + dmaTriggerBurst = + DMA_CHANNEL_CFG_TRIGBURST(1U) | DMA_CHANNEL_CFG_BURSTPOWER(FLEXSPI_CalculatePower(handle->nbytes)); + dmaRxTriggerConfig.burst = (dma_trigger_burst_t)(dmaTriggerBurst); +#endif + + for (uint8_t i = desCount - 1U; i > 0U; i--) + { + DMA_SetupDescriptor(&s_flexspiDes[i - 1U], + DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, + false, (uint32_t)handle->nsize, srcInc, dstInc, remains), + rxFifoBase, (void *)(uint64_t *)((uint32_t)data + i * bytesPerDes), nextDesc); + nextDesc = &s_flexspiDes[i - 1U]; + } + + DMA_PrepareChannelTransfer( + &rxChannelConfig, rxFifoBase, (void *)data, + DMA_CHANNEL_XFER((nextDesc == NULL) ? false : true, true, (nextDesc == NULL) ? true : false, false, + (uint32_t)handle->nsize, srcInc, dstInc, bytesPerDes), + kDMA_MemoryToMemory, &dmaRxTriggerConfig, nextDesc); + + (void)DMA_SubmitChannelTransfer(handle->rxDmaHandle, &rxChannelConfig); + + DMA_SetCallback(handle->rxDmaHandle, FLEXSPI_TransferDMACallback, &s_dmaPrivateHandle[FLEXSPI_GetInstance(base)]); + DMA_StartTransfer(handle->rxDmaHandle); + + /* Enable FLEXSPI RX DMA. */ + FLEXSPI_EnableRxDMA(base, true); + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + return kStatus_Success; +} + +/*! + * brief Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback. + * + * param base FLEXSPI peripheral base address + * param handle Pointer to flexspi_dma_handle_t structure + * param callback FLEXSPI callback, NULL means no callback. + * param userData User callback function data. + * param txDmaHandle User requested DMA handle for TX DMA transfer. + * param rxDmaHandle User requested DMA handle for RX DMA transfer. + */ +void FLEXSPI_TransferCreateHandleDMA(FLEXSPI_Type *base, + flexspi_dma_handle_t *handle, + flexspi_dma_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + assert(handle); + + uint32_t instance = FLEXSPI_GetInstance(base); + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->state = kFLEXSPI_Idle; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->nsize = kFLEXPSI_DMAnSize4Bytes; + + handle->completionCallback = callback; + handle->userData = userData; +} + +/*! + * brief Update FLEXSPI DMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE). + * + * param base FLEXSPI peripheral base address + * param handle Pointer to flexspi_dma_handle_t structure + * param nsize FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is + * kFLEXPSI_DMAnSize1Bytes(one byte). + * see flexspi_dma_transfer_nsize_t . + */ +void FLEXSPI_TransferUpdateSizeDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, flexspi_dma_transfer_nsize_t nsize) +{ + handle->nsize = nsize; +} + +/*! + * brief Transfers FLEXSPI data using an dma non-blocking method. + * + * This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking. + * param base FLEXSPI peripheral base address. + * param handle Pointer to flexspi_dma_handle_t structure + * param xfer FLEXSPI transfer structure. + * retval kStatus_FLEXSPI_Busy FLEXSPI is busy transfer. + * retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark should be power of + 2 to do successfully DMA transfer. + * retval kStatus_Success FLEXSPI successfully start dma transfer. + */ +status_t FLEXSPI_TransferDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + assert(handle); + assert(xfer); + + /* Check if the FLEXSPI bus is idle - if not return busy status. */ + if (handle->state != (uint32_t)kFLEXSPI_Idle) + { + result = kStatus_FLEXSPI_Busy; + } + else + { + handle->transferSize = xfer->dataSize; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this transfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base address. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U); + base->IPCR1 = configValue; + + if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + handle->state = kFLEXSPI_Busy; + result = FLEXSPI_WriteDataDMA(base, handle, xfer->data, xfer->dataSize); + } + else if (xfer->cmdType == kFLEXSPI_Read) + { + handle->state = kFLEXSPI_Busy; + result = FLEXSPI_ReadDataDMA(base, handle, xfer->data, xfer->dataSize); + } + else + { + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + handle->state = kFLEXSPI_Idle; + + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } + } + + return result; +} + +/*! + * brief Aborts the transfer data using dma. + * + * This function aborts the transfer data using dma. + * + * param base FLEXSPI peripheral base address. + * param handle Pointer to flexspi_dma_handle_t structure + */ +void FLEXSPI_TransferAbortDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle) +{ + assert(handle != NULL); + + if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) + { + FLEXSPI_EnableTxDMA(base, false); + DMA_AbortTransfer(handle->txDmaHandle); + } + + if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) + { + FLEXSPI_EnableRxDMA(base, false); + DMA_AbortTransfer(handle->rxDmaHandle); + } + + handle->state = kFLEXSPI_Idle; +} + +status_t FLEXSPI_TransferGetTransferCountDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, size_t *count) +{ + assert(handle); + assert(count); + + status_t result = kStatus_Success; + + if (handle->state != (uint32_t)kFLEXSPI_Busy) + { + result = kStatus_NoTransferInProgress; + } + else + { + if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) + { + *count = + (handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel)); + } + else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) + { + *count = + (handle->transferSize - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel)); + } + else + { + ; /* Intentional empty for MISRA C-2012 rule 15.7. */ + } + } + + return result; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..7ad6ba7a8a8db11947e2872dfaf42820cad62e5d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_flexspi_dma.h @@ -0,0 +1,144 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXSPI_DMA_H_ +#define _FSL_FLEXSPI_DMA_H_ + +#include "fsl_flexspi.h" +#include "fsl_dma.h" + +/*! + * @addtogroup flexspi_dma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLEXSPI DMA driver version. */ +#define FSL_FLEXSPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 5)) +/*@}*/ + +typedef struct _flexspi_dma_handle flexspi_dma_handle_t; + +/*! @brief FLEXSPI dma transfer callback function for finish and error */ +typedef void (*flexspi_dma_callback_t)(FLEXSPI_Type *base, + flexspi_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief dma transfer configuration */ +typedef enum _flexspi_dma_ntransfer_size +{ + kFLEXPSI_DMAnSize1Bytes = 0x1U, /*!< Source/Destination data transfer size is 1 byte every time */ + kFLEXPSI_DMAnSize2Bytes = 0x2U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kFLEXPSI_DMAnSize4Bytes = 0x4U, /*!< Source/Destination data transfer size is 4 bytes every time */ +} flexspi_dma_transfer_nsize_t; + +/*! @brief FLEXSPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _flexspi_dma_handle +{ + dma_handle_t *txDmaHandle; /*!< dma handler for FLEXSPI Tx. */ + dma_handle_t *rxDmaHandle; /*!< dma handler for FLEXSPI Rx. */ + size_t transferSize; /*!< Bytes need to transfer. */ + flexspi_dma_transfer_nsize_t nsize; /*!< dma SSIZE/DSIZE in each transfer. */ + uint8_t nbytes; /*!< dma minor byte transfer count initially configured. */ + uint8_t count; /*!< The transfer data count in a DMA request. */ + uint32_t state; /*!< Internal state for FLEXSPI dma transfer. */ + flexspi_dma_callback_t completionCallback; /*!< A callback function called after the dma transfer is finished. */ + void *userData; /*!< User callback parameter */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FLEXSPI dma Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback. + * + * @param base FLEXSPI peripheral base address + * @param handle Pointer to flexspi_dma_handle_t structure + * @param callback FLEXSPI callback, NULL means no callback. + * @param userData User callback function data. + * @param txDmaHandle User requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User requested DMA handle for RX DMA transfer. + */ +void FLEXSPI_TransferCreateHandleDMA(FLEXSPI_Type *base, + flexspi_dma_handle_t *handle, + flexspi_dma_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Update FLEXSPI DMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE). + * + * @param base FLEXSPI peripheral base address + * @param handle Pointer to flexspi_dma_handle_t structure + * @param nsize FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is + * kFLEXPSI_DMAnSize1Bytes(one byte). + * @see flexspi_dma_transfer_nsize_t . + */ +void FLEXSPI_TransferUpdateSizeDMA(FLEXSPI_Type *base, + flexspi_dma_handle_t *handle, + flexspi_dma_transfer_nsize_t nsize); + +/*! + * @brief Transfers FLEXSPI data using an dma non-blocking method. + * + * This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking. + * @param base FLEXSPI peripheral base address. + * @param handle Pointer to flexspi_dma_handle_t structure + * @param xfer FLEXSPI transfer structure. + * @retval kStatus_FLEXSPI_Busy FLEXSPI is busy transfer. + * @retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark should be power of + 2 to do successfully DMA transfer. + * @retval kStatus_Success FLEXSPI successfully start dma transfer. + */ +status_t FLEXSPI_TransferDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, flexspi_transfer_t *xfer); + +/*! + * @brief Aborts the transfer data using dma. + * + * This function aborts the transfer data using dma. + * + * @param base FLEXSPI peripheral base address. + * @param handle Pointer to flexspi_dma_handle_t structure + */ +void FLEXSPI_TransferAbortDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle); + +/*! + * @brief Gets the transferred counts of transfer. + * + * @param base FLEXSPI peripheral base address. + * @param handle Pointer to flexspi_dma_handle_t structure. + * @param count Bytes transfer. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXSPI_TransferGetTransferCountDMA(FLEXSPI_Type *base, flexspi_dma_handle_t *handle, size_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* _FSL_FLEXSPI_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.c new file mode 100644 index 0000000000000000000000000000000000000000..709bc80f2f093243bedf109e7a6fb4dc87d207c4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.c @@ -0,0 +1,143 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_freqme.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t FREQME_GetInstance(FREQME_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map freqme instance number to base address. */ +static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FREQME clocks for each instance. */ +static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FREQME_GetInstance(FREQME_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_freqmeBases); instance++) + { + if (s_freqmeBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_freqmeBases)); + + return instance; +} + +/*! + * brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. + * + * param base FREQME peripheral base address. + * param config The pointer to module basic configuration, please refer to freq_measure_config_t. + */ +void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config) +{ + assert(config); + + uint32_t tmp32 = 0UL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable FREQME clock. */ + CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + if (config->startMeasurement) + { + tmp32 |= FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK; + } + tmp32 |= FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | + FREQME_FREQMECTRL_W_PULSE_MODE(config->operateMode); + if (config->operateMode == kFREQME_FreqMeasurementMode) + { + tmp32 |= FREQME_FREQMECTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); + } + else + { + tmp32 |= FREQME_FREQMECTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity); + } + + base->FREQMECTRL_W = tmp32; +} + +/*! + * brief Get default configuration. + * + * code + * config->operateMode = kFREQME_FreqMeasurementMode; + * config->operateModeAttribute.refClkScaleFactor = 0U; + * config->enableContinuousMode = false; + * config->startMeasurement = false; + * endcode + * + * param config The pointer to module basic configuration, please refer to freq_measure_config_t. + */ +void FREQME_GetDefaultConfig(freq_measure_config_t *config) +{ + assert(config); + + (void)memset(config, 0, sizeof(*config)); + + config->operateMode = kFREQME_FreqMeasurementMode; + config->operateModeAttribute.refClkScaleFactor = 0U; + config->enableContinuousMode = false; + config->startMeasurement = false; +} + +/*! + * brief Calculate the frequency of selected target clock. + * + * note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. + * + * note This function only useful when the operate mode is selected as frequency measurement mode. + * + * param base FREQME peripheral base address. + * param refClkFrequency The frequency of reference clock. + * return The frequency of target clock, if the output result is 0, please check the module's operate mode. + */ +uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency) +{ + uint64_t measureResult = 0ULL; + uint32_t targetFreq = 0ULL; + uint64_t tmp64 = 0ULL; + + while ((base->FREQMECTRL_R & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL) + { + } + + if (!FREQME_CheckOperateMode(base)) + { + measureResult = (uint64_t)(base->FREQMECTRL_R & FREQME_FREQMECTRL_R_RESULT_MASK); + tmp64 = (measureResult - 2ULL) * (uint64_t)refClkFrequency; + targetFreq = (uint32_t)(tmp64 / (1UL << (uint32_t)FREQME_GetReferenceClkScaleValue(base))); + } + + return targetFreq; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.h new file mode 100644 index 0000000000000000000000000000000000000000..dae1c2b81eee8f1ed89b6532b499e0217f7d6b6c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_freqme.h @@ -0,0 +1,440 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FREQME_ +#define _FSL_FREQME_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_freqme + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FREQME driver version 2.0.0. */ +#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief The enumeration of interrupt status flags. + * @anchor _freqme_interrupt_status_flags + */ +enum _freqme_interrupt_status_flags +{ + kFREQME_UnderflowInterruptStatusFlag = FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK, /*!< Indicate the measurement is + just done and the result is less + than minimun value. */ + kFREQME_OverflowInterruptStatusFlag = FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK, /*!< Indicate the measurement is + just done and the result is greater + than maximum value. */ + kFREQME_ReadyInterruptStatusFlag = FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is + just done and the result is ready to + read. */ + kFREQME_AllInterruptStatusFlags = FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | + FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt + status flags. */ +}; + +/*! + * @brief The enumeration of interrupts, including underflow interrupt, overflow interrupt, + * and result ready interrupt. + * @anchor _freqme_interrupt_enable + */ +enum _freqme_interrupt_enable +{ + kFREQME_UnderflowInterruptEnable = FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is + less than minimum value. */ + kFREQME_OverflowInterruptEnable = FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is + greater than maximum value. */ + kFREQME_ReadyInterruptEnable = FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a + measurement completes and the result + is ready. */ +}; + +/*! + * @brief FREQME module operate mode enumeration, including frequency measurement mode + * and pulse width measurement mode. + */ +typedef enum _freqme_operate_mode +{ + kFREQME_FreqMeasurementMode = 0U, /*!< The module works in the frequency measurement mode. */ + kFREOME_PulseWidthMeasurementMode, /*!< The module works in the pulse width measurement mode. */ +} freqme_operate_mode_t; + +/*! + * @brief The enumeration of pulse polarity. + */ +typedef enum _freqme_pulse_polarity +{ + kFREQME_PulseHighPeriod = 0U, /*!< Select high period of the reference clock. */ + kFREQME_PulseLowPeriod, /*!< Select low period of the reference clock. */ +} freqme_pulse_polarity_t; + +/*! + * @brief The union of operate mode attribute. + * @note If the operate mode is selected as frequency measurement mode the member \b refClkScaleFactor should be used, + * if the operate mode is selected as pulse width measurement mode the member \b pulsePolarity should be used. + */ +typedef union _freqme_mode_attribute +{ + uint8_t refClkScaleFactor; /*!< Only useful in frequency measurement operate mode, + used to set the reference clock counter scaling factor. */ + freqme_pulse_polarity_t pulsePolarity; /*!< Only Useful in pulse width measurement operate mode, + used to set period polarity. */ +} freqme_mode_attribute_t; + +/*! + * @brief The structure of freqme module basic configuration, + * including operate mode, operate mode attribute and so on. + */ +typedef struct _freq_measure_config +{ + freqme_operate_mode_t operateMode; /*!< Select operate mode, please refer to @ref freqme_operate_mode_t. */ + freqme_mode_attribute_t operateModeAttribute; /*!< Used to set the attribute of the selected operate mode, if + the operate mode is selected as @ref kFREQME_FreqMeasurementMode + set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is + selected as @ref kFREOME_PulseWidthMeasurementMode, please set + freqme_mode_attribute_t::pulsePolarity. */ + + bool enableContinuousMode; /*!< Enable/disable continuous mode, if continuous mode is enable, + the measurement is performed continuously and the result for the + last completed measurement is available in the result register. */ + bool startMeasurement; +} freq_measure_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Basic Control APIs + * @{ + */ +/*! + * @brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. + * + * @param base FREQME peripheral base address. + * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. + */ +void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config); + +/*! + * @brief Get default configuration. + * + * @code + * config->operateMode = kFREQME_FreqMeasurementMode; + * config->operateModeAttribute.refClkScaleFactor = 0U; + * config->enableContinuousMode = false; + * config->startMeasurement = false; + * @endcode + * + * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. + */ +void FREQME_GetDefaultConfig(freq_measure_config_t *config); + +/*! + * @brief Start frequency or pulse width measurement process. + * + * @param base FREQME peripheral base address. + */ +static inline void FREQME_StartMeasurementCycle(FREQME_Type *base) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 |= FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK; + base->FREQMECTRL_W = tmp32; +} + +/*! + * @brief Force the termination of any measurement cycle currently in progress and resets RESULT or just reset + * RESULT if the module in idle state. + * + * @param base FREQME peripheral base address. + */ +static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + base->FREQMECTRL_W = tmp32; +} + +/*! + * @brief Enable/disable Continuous mode. + * + * @param base FREQME peripheral base address. + * @param enable Used to enable/disable continuous mode, + * - \b true Enable Continuous mode. + * - \b false Disable Continuous mode. + */ +static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK | + FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + if (enable) + { + tmp32 |= FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK; + } + + base->FREQMECTRL_W = tmp32; +} + +/*! + * @brief Check whether continuous mode is enabled. + * + * @param base FREQME peripheral base address. + * @retval True Continuous mode is enabled, the measurement is performed continuously. + * @retval False Continuous mode is disabled. + */ +static inline bool FREQME_CheckContinuousMode(FREQME_Type *base) +{ + return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL); +} + +/*! + * @brief Set operate mode of freqme module. + * + * @param base FREQME peripheral base address. + * @param operateMode The operate mode to be set, please refer to @ref freqme_operate_mode_t. + */ +static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK | + FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + if (operateMode == kFREOME_PulseWidthMeasurementMode) + { + tmp32 |= FREQME_FREQMECTRL_W_PULSE_MODE_MASK; + } + + base->FREQMECTRL_W = tmp32; +} + +/*! + * @brief Check module's operate mode. + * + * @param base FREQME peripheral base address. + * @retval True Pulse width measurement mode. + * @retval False Frequency measurement mode. + */ +static inline bool FREQME_CheckOperateMode(FREQME_Type *base) +{ + return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK) != 0UL); +} + +/*! + * @brief Set the minimum expected value for the measurement result. + * + * @param base FREQME peripheral base address. + * @param minValue The minimum value to set, please note that this value is 31 bits width. + */ +static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue) +{ + base->FREQMEMIN = minValue; +} + +/*! + * @brief Set the maximum expected value for the measurement result. + * + * @param base FREQME peripheral base address. + * @param maxValue The maximum value to set, please note that this value is 31 bits width. + */ +static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue) +{ + base->FREQMEMAX = maxValue; +} + +/*! @} */ + +/*! + * @name Frequency Measurement Mode Control APIs + * @{ + */ + +/*! + * @brief Calculate the frequency of selected target clock。 + * + * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. + * + * @note This function only useful when the operate mode is selected as frequency measurement mode. + * + * @param base FREQME peripheral base address. + * @param refClkFrequency The frequency of reference clock. + * @return The frequency of target clock the unit is Hz, if the output result is 0, please check the module's + * operate mode. + */ +uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency); + +/*! + * @brief Get reference clock scaling factor. + * + * @param base FREQME peripheral base address. + * @return Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale. + */ +static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base) +{ + return (uint8_t)(base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_REF_SCALE_MASK); +} + +/*! @} */ + +/*! + * @name Pulse Width Measurement Mode Control APIs + * @{ + */ + +/*! + * @brief Set pulse polarity when operate mode is selected as Pulse Width Measurement mode. + * + * @param base FREQME peripheral base address. + * @param pulsePolarity The pulse polarity to be set, please refer to @ref freqme_pulse_polarity_t. + */ +static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_PULSE_POL_MASK | + FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + + if (pulsePolarity != kFREQME_PulseHighPeriod) + { + tmp32 |= FREQME_FREQMECTRL_W_PULSE_POL_MASK; + } + + base->FREQMECTRL_W = tmp32; +} + +/*! + * @brief Check pulse polarity when the operate mode is selected as pulse width measurement mode. + * + * @param base FREQME peripheral base address. + * @retval True Low period. + * @retval False High period. + */ +static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base) +{ + return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_PULSE_POL_MASK) != 0UL); +} + +/*! + * @brief Get measurement result, if operate mode is selected as pulse width measurement mode this function can + * be used to calculate pulse width. + * + * @note Pulse width = counter result / Frequency of target clock. + * + * @param base FREQME peripheral base address. + * @return Measurement result. + */ +static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base) +{ + return base->FREQMECTRL_R & FREQME_FREQMECTRL_R_RESULT_MASK; +} + +/*! @} */ + +/*! + * @name Status Control APIs + * @{ + */ + +/*! + * @brief Get interrupt status flags, such as overflow interrupt status flag, + * underflow interrupt status flag, and so on. + * + * @param base FREQME peripheral base address. + * @return Current interrupt status flags, should be the OR'ed value of @ref _freqme_interrupt_status_flags. + */ +static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base) +{ + return (base->FREQMECTRLSTAT & kFREQME_AllInterruptStatusFlags); +} + +/*! + * @brief Clear interrupt status flags. + * + * @param base FREQME peripheral base address. + * @param statusFlags The combination of interrupt status flags to clear, + * should be the OR'ed value of @ref _freqme_interrupt_status_flags. + */ +static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags) +{ + base->FREQMECTRLSTAT |= statusFlags; +} + +/*! @} */ + +/*! + * @name Interrupt Control APIs + * @{ + */ + +/*! + * @brief Enable interrupts, such as result ready interrupt, overflow interrupt and so on. + * + * @param base FREQME peripheral base address. + * @param masks The mask of interrupts to enable, should be the OR'ed value of @ref _freqme_interrupt_enable. + */ +static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK | + FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK | + FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + + tmp32 |= masks; + base->FREQMECTRL_W = tmp32; +} + +/*! + * @brief Disable interrupts, such as result ready interrupt, overflow interrupt and so on. + * + * @param base FREQME peripheral base address. + * @param masks The mask of interrupts to disable, should be the OR'ed value of @ref _freqme_interrupt_enable. + */ +static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) +{ + uint32_t tmp32; + + tmp32 = base->FREQMECTRLSTAT; + tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | + FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK | masks); + + base->FREQMECTRL_W = tmp32; +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* __FSL_FREQME_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_fro_calib.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_fro_calib.h new file mode 100644 index 0000000000000000000000000000000000000000..9662444a52661de9f5891cc532fa1eca4ab882f5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_fro_calib.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FRO_CALIB_H_ +#define _FSL_FRO_CALIB_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FRO_CALIB driver version 1.0.0. */ +#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.fro_calib" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Returns the version of the FRO Calibration library */ +unsigned int fro_calib_Get_Lib_Ver(void); + +/* ctimer instance */ +/* ctimer clock frquency in KHz */ +void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); + +/* USB_SOF_Event */ +/* Application software should be written to make sure the USB_SOF_EVENT() is */ +/* being called with lower interrupt latency for calibration to work properly */ +void USB_SOF_Event(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.c new file mode 100644 index 0000000000000000000000000000000000000000..9dc2e5eff0d1c6f54769954099b902d7a4d6b1e8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GINT bases for each instance. */ +static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clocks for each instance. */ +static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/*! @brief Resets for each instance. */ +static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* @brief Irq number for each instance */ +static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; + +/*! @brief Callback function array for GINT(s). */ +static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GINT_GetInstance(GINT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) + { + if (s_gintBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gintBases)); + + return instance; +} + +/*! + * brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_Init(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +} + +/*! + * brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * param callback This function is called when configured group interrupt is generated. + * + * retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); + + /* Save callback pointer */ + s_gintCallback[instance] = callback; +} + +/*! + * brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Pointer to store combine input value. + * param trig Pointer to store trigger value. + * param callback Pointer to store callback function. + * + * retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) +{ + uint32_t instance; + uint32_t combValue; + uint32_t trigValue; + + instance = GINT_GetInstance(base); + + combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; + *comb = (gint_comb_t)combValue; + trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; + *trig = (gint_trig_t)trigValue; + *callback = s_gintCallback[instance]; +} + +/*! + * brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) +{ + base->PORT_POL[port] = polarityMask; + base->PORT_ENA[port] = enableMask; +} + +/*! + * brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) +{ + *polarityMask = base->PORT_POL[port]; + *enableMask = base->PORT_ENA[port]; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_EnableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + /* If GINT is configured in "AND" mode a spurious interrupt is generated. + Clear status and pending interrupt before enabling the irq in NVIC. */ + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); + (void)EnableIRQ(s_gintIRQ[instance]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void GINT_DisableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + (void)DisableIRQ(s_gintIRQ[instance]); + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); +} + +/*! + * brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_Deinit(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + /* Cleanup */ + GINT_DisableCallback(base); + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the peripheral clock */ + CLOCK_DisableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(GINT0) +void GINT0_DriverIRQHandler(void); +void GINT0_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[0] != NULL) + { + s_gintCallback[0](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT1) +void GINT1_DriverIRQHandler(void); +void GINT1_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[1] != NULL) + { + s_gintCallback[1](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT2) +void GINT2_DriverIRQHandler(void); +void GINT2_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[2] != NULL) + { + s_gintCallback[2](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT3) +void GINT3_DriverIRQHandler(void); +void GINT3_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[3] != NULL) + { + s_gintCallback[3](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT4) +void GINT4_DriverIRQHandler(void); +void GINT4_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[4] != NULL) + { + s_gintCallback[4](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT5) +void GINT5_DriverIRQHandler(void); +void GINT5_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[5] != NULL) + { + s_gintCallback[5](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT6) +void GINT6_DriverIRQHandler(void); +void GINT6_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[6] != NULL) + { + s_gintCallback[6](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT7) +void GINT7_DriverIRQHandler(void); +void GINT7_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[7] != NULL) + { + s_gintCallback[7](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.h new file mode 100644 index 0000000000000000000000000000000000000000..adc301a9e0d7625d28bb8a7d12d1e7758f5f41ef --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gint.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GINT_H_ +#define _FSL_GINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ +/*@}*/ + +/*! @brief GINT combine inputs type */ +typedef enum _gint_comb +{ + kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ + kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ +} gint_comb_t; + +/*! @brief GINT trigger type */ +typedef enum _gint_trig +{ + kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ + kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ +} gint_trig_t; + +/* @brief GINT port type */ +typedef enum _gint_port +{ + kGINT_Port0 = 0U, + kGINT_Port1 = 1U, +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) + kGINT_Port2 = 2U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) + kGINT_Port3 = 3U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) + kGINT_Port4 = 4U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) + kGINT_Port5 = 5U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) + kGINT_Port6 = 6U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) + kGINT_Port7 = 7U, +#endif +} gint_port_t; + +/*! @brief GINT Callback function. */ +typedef void (*gint_cb_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Init(GINT_Type *base); + +/*! + * @brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * @param callback This function is called when configured group interrupt is generated. + * + * @retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); + +/*! + * @brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Pointer to store combine input value. + * @param trig Pointer to store trigger value. + * @param callback Pointer to store callback function. + * + * @retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); + +/*! + * @brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); + +/*! + * @brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_EnableCallback(GINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void GINT_DisableCallback(GINT_Type *base); + +/*! + * @brief Clear GINT status. + + * This function clears the GINT status bit. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +static inline void GINT_ClrStatus(GINT_Type *base) +{ + base->CTRL |= GINT_CTRL_INT_MASK; +} + +/*! + * @brief Get GINT status. + + * This function returns the GINT status. + * + * @param base Base address of the GINT peripheral. + * + * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. + */ +static inline uint32_t GINT_GetStatus(GINT_Type *base) +{ + return (base->CTRL & GINT_CTRL_INT_MASK); +} + +/*! + * @brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Deinit(GINT_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_GINT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..be100d5e9e3332dacb70b5ce87fdae8305e2ce9f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ +/*! + * @brief Enable GPIO port clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ + GPIO_EnablePortClock(base, port); + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + GPIO_EnablePortClock(base, port); + + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1UL << pin; +#else + base->DIR[port] &= ~(1UL << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1UL << pin); + } + else + { + base->SET[port] = (1UL << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1UL << pin; +#else + base->DIR[port] |= 1UL << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); + + base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if ((uint32_t)kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1UL << pin; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1UL << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..50a33f89208e773e9e4decaaa6505043c2dbc643 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_gpio.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.c new file mode 100644 index 0000000000000000000000000000000000000000..5fa11bca85f01d644de6915936a3f61edcab2e8c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.c @@ -0,0 +1,237 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_hscmp.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.hscmp" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(HSCMP_CLOCKS) +/*! + * @brief Get instance number for HSCMP module. + * + * @param base HSCMP peripheral base address + */ +static uint32_t HSCMP_GetInstance(HSCMP_Type *base); +#endif /* HSCMP_CLOCKS */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(HSCMP_CLOCKS) +/*! @brief Pointers to HSCMP bases for each instance. */ +static HSCMP_Type *const s_hscmpBases[] = HSCMP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to HSCMP clocks for each instance. */ +static const clock_ip_name_t s_hscmpClocks[] = HSCMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* HSCMP_CLOCKS */ + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if defined(HSCMP_CLOCKS) +static uint32_t HSCMP_GetInstance(HSCMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_hscmpBases); instance++) + { + if (s_hscmpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_hscmpBases)); + + return instance; +} +#endif /* HSCMP_CLOCKS */ + +/*! + * brief Initialize the HSCMP + * + * This function initializes the HSCMP module. The operations included are: + * - Enabling the clock for HSCMP module. + * - Configuring the comparator. + * - Enabling the HSCMP module. + * Note: For some devices, multiple HSCMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the HSCMPs. Check the chip reference manual for the clock assignment of the HSCMP. + * + * param base HSCMP peripheral base address. + * param config Pointer to "hscmp_config_t" structure. + */ +void HSCMP_Init(HSCMP_Type *base, const hscmp_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + +#if defined(HSCMP_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_hscmpClocks[HSCMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* HSCMP_CLOCKS */ + + /* Configure. */ + HSCMP_Enable(base, false); + /* CCR0 register. */ + if (config->enableStopMode) + { + base->CCR0 |= HSCMP_CCR0_CMP_STOP_EN_MASK; + } + else + { + base->CCR0 &= ~HSCMP_CCR0_CMP_STOP_EN_MASK; + } + /* CCR1 register. */ + tmp32 = base->CCR1 & ~(HSCMP_CCR1_COUT_PEN_MASK | HSCMP_CCR1_COUT_SEL_MASK | HSCMP_CCR1_COUT_INV_MASK); + if (config->enableOutputPin) + { + tmp32 |= HSCMP_CCR1_COUT_PEN_MASK; + } + if (config->useUnfilteredOutput) + { + tmp32 |= HSCMP_CCR1_COUT_SEL_MASK; + } + if (config->enableInvertOutput) + { + tmp32 |= HSCMP_CCR1_COUT_INV_MASK; + } + base->CCR1 = tmp32; + /* CCR2 register. */ + tmp32 = base->CCR2 & ~(HSCMP_CCR2_HYSTCTR_MASK | HSCMP_CCR2_CMP_NPMD_MASK | HSCMP_CCR2_CMP_HPMD_MASK); + tmp32 |= HSCMP_CCR2_HYSTCTR(config->hysteresisMode); + tmp32 |= ((uint32_t)(config->powerMode) << HSCMP_CCR2_CMP_HPMD_SHIFT); + base->CCR2 = tmp32; + + HSCMP_Enable(base, true); /* Enable the HSCMP module. */ +} + +/*! + * brief De-initializes the HSCMP module. + * + * This function de-initializes the HSCMP module. The operations included are: + * - Disabling the HSCMP module. + * - Disabling the clock for HSCMP module. + * + * This function disables the clock for the HSCMP. + * Note: For some devices, multiple HSCMP instance shares the same clock gate. In this case, before disabling the + * clock for the HSCMP, ensure that all the HSCMP instances are not used. + * + * param base HSCMP peripheral base address. + */ +void HSCMP_Deinit(HSCMP_Type *base) +{ + /* Disable the HSCMP module. */ + HSCMP_Enable(base, false); +#if defined(HSCMP_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_hscmpClocks[HSCMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* HSCMP_CLOCKS */ +} + +/*! + * brief Gets an available pre-defined settings for the comparator's configuration. + * + * This function initializes the comparator configuration structure to these default values: + * code + * config->enableStopMode = false; + * config->enableOutputPin = false; + * config->useUnfilteredOutput = false; + * config->enableInvertOutput = false; + * config->hysteresisMode = kHSCMP_HysteresisLevel0; + * config->powerMode = kHSCMP_LowSpeedPowerMode; + * endcode + * param config Pointer to "hscmp_config_t" structure. + */ +void HSCMP_GetDefaultConfig(hscmp_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableStopMode = false; + config->enableOutputPin = false; + config->useUnfilteredOutput = false; + config->enableInvertOutput = false; + config->hysteresisMode = kHSCMP_HysteresisLevel0; + config->powerMode = kHSCMP_LowSpeedPowerMode; +} + +/*! + * brief Select the input channels for HSCMP. This function determines which input + * is selected for the negative and positive mux. + * + * param base HSCMP peripheral base address. + * param positiveChannel Positive side input channel number. Available range is 0-7. + * param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void HSCMP_SetInputChannels(HSCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) +{ + uint32_t tmp32; + + tmp32 = base->CCR2 & ~(HSCMP_CCR2_PSEL_MASK | HSCMP_CCR2_MSEL_MASK); + tmp32 |= HSCMP_CCR2_PSEL(positiveChannel) | HSCMP_CCR2_MSEL(negativeChannel); + base->CCR2 = tmp32; +} + +/*! + * brief Configures the filter. + * + * param base HSCMP peripheral base address. + * param config Pointer to "hscmp_filter_config_t" structure. + */ +void HSCMP_SetFilterConfig(HSCMP_Type *base, const hscmp_filter_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + + tmp32 = base->CCR1 & ~(HSCMP_CCR1_FILT_PER_MASK | HSCMP_CCR1_FILT_CNT_MASK | HSCMP_CCR1_SAMPLE_EN_MASK); + if (config->enableSample) + { + tmp32 |= HSCMP_CCR1_SAMPLE_EN_MASK; + } + tmp32 |= HSCMP_CCR1_FILT_PER(config->filterSamplePeriod) | HSCMP_CCR1_FILT_CNT(config->filterSampleCount); + base->CCR1 = tmp32; +} + +/*! + * brief Configure the internal DAC module. + * + * param base HSCMP peripheral base address. + * param config Pointer to "hscmp_dac_config_t" structure. If config is "NULL", disable internal DAC. + */ +void HSCMP_SetDACConfig(HSCMP_Type *base, const hscmp_dac_config_t *config) +{ + uint32_t tmp32; + if (config == NULL) + { + tmp32 = 0U; /* Disable internal DAC. */ + } + else + { + tmp32 = HSCMP_DCR_VRSEL(config->referenceVoltageSource) | HSCMP_DCR_DAC_DATA(config->DACValue); + if (config->enableLowPowerMode) + { + tmp32 |= HSCMP_DCR_DAC_HPMD_MASK; + } + tmp32 |= HSCMP_DCR_DAC_EN_MASK; + } + base->DCR = tmp32; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.h new file mode 100644 index 0000000000000000000000000000000000000000..37d9cd1754c9441ebc70081ea1906743c49552d5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_hscmp.h @@ -0,0 +1,302 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_HSCMP_H_ +#define _FSL_HSCMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup hscmp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief HSCMP driver version 2.0.3. */ +#define FSL_HSCMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! + * @brief HSCMP status falgs mask. + */ +enum _hscmp_status_flags +{ + kHSCMP_OutputRisingEventFlag = HSCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kHSCMP_OutputFallingEventFlag = HSCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ + kHSCMP_OutputAssertEventFlag = HSCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. + The flag does not support W1C. */ +}; + +/*! + * @brief HSCMP interrupt enable/disable mask. + */ +enum _hscmp_interrupt_enable +{ + kHSCMP_OutputRisingInterruptEnable = HSCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ + kHSCMP_OutputFallingInterruptEnable = HSCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ +}; +/*! + * @brief HSCMP hysteresis mode. See chip data sheet to get the actual hystersis + * value with each level + */ +typedef enum _hscmp_hysteresis_mode +{ + kHSCMP_HysteresisLevel0 = 0U, /*!< The hard block output has level 0 hysteresis internally. */ + kHSCMP_HysteresisLevel1 = 1U, /*!< The hard block output has level 1 hysteresis internally. */ + kHSCMP_HysteresisLevel2 = 2U, /*!< The hard block output has level 2 hysteresis internally. */ + kHSCMP_HysteresisLevel3 = 3U, /*!< The hard block output has level 3 hysteresis internally. */ +} hscmp_hysteresis_mode_t; + +/*! + * @brief HSCMP nano mode. + */ +typedef enum _hscmp_power_mode +{ + kHSCMP_LowSpeedPowerMode = 0U, /*!< Low speed comparison mode is selected. */ + kHSCMP_HighSpeedPowerMode = 1U, /*!< High speed comparison mode is selected. */ + kHSCMP_NanoPowerMode = 2U, /*!< Nano power comparator is enabled. */ +} hscmp_power_mode_t; + +/*! + * @brief Internal DAC reference voltage source. + */ +typedef enum _hscmp_dac_reference_voltage_source +{ + kHSCMP_VrefSourceVin1 = 0U, /*!< vrefh_int is selected as resistor ladder network supply reference Vin. */ + kHSCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ +} hscmp_dac_reference_voltage_source_t; + +/*! + * @brief Configure the filter. + */ +typedef struct _hscmp_filter_config +{ + bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ + uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ + uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The + sampling clock must be at least 4 times slower than the system clock to the comparator. + So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ +} hscmp_filter_config_t; + +/*! + * @brief configure the internal DAC. + */ +typedef struct _hscmp_dac_config +{ + bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ + hscmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ +} hscmp_dac_config_t; + +/*! + * @brief Configures the comparator. + */ +typedef struct _hscmp_config +{ + bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ + bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ + bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ + bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ + hscmp_hysteresis_mode_t hysteresisMode; /*!< HSCMP hysteresis mode. */ + hscmp_power_mode_t powerMode; /*!< HSCMP power mode. */ +} hscmp_config_t; +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize the HSCMP + * + * This function initializes the HSCMP module. The operations included are: + * - Enabling the clock for HSCMP module. + * - Configuring the comparator. + * - Enabling the HSCMP module. + * Note: For some devices, multiple HSCMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the HSCMPs. Check the chip reference manual for the clock assignment of the HSCMP. + * + * @param base HSCMP peripheral base address. + * @param config Pointer to "hscmp_config_t" structure. + */ +void HSCMP_Init(HSCMP_Type *base, const hscmp_config_t *config); + +/*! + * @brief De-initializes the HSCMP module. + * + * This function de-initializes the HSCMP module. The operations included are: + * - Disabling the HSCMP module. + * - Disabling the clock for HSCMP module. + * + * This function disables the clock for the HSCMP. + * Note: For some devices, multiple HSCMP instance shares the same clock gate. In this case, before disabling the + * clock for the HSCMP, ensure that all the HSCMP instances are not used. + * + * @param base HSCMP peripheral base address. + */ +void HSCMP_Deinit(HSCMP_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the comparator's configuration. + * + * This function initializes the comparator configuration structure to these default values: + * @code + * config->enableStopMode = false; + * config->enableOutputPin = false; + * config->useUnfilteredOutput = false; + * config->enableInvertOutput = false; + * config->hysteresisMode = kHSCMP_HysteresisLevel0; + * config->powerMode = kHSCMP_LowSpeedPowerMode; + * @endcode + * @param config Pointer to "hscmp_config_t" structure. + */ +void HSCMP_GetDefaultConfig(hscmp_config_t *config); + +/*! + * @brief Enable/Disable HSCMP module. + * + * @param base HSCMP peripheral base address. + * @param enable "true" means enable the module, and "false" means disable the module. + */ +static inline void HSCMP_Enable(HSCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR0 |= HSCMP_CCR0_CMP_EN_MASK; + } + else + { + base->CCR0 &= ~HSCMP_CCR0_CMP_EN_MASK; + } +} + +/*! + * @brief Select the input channels for HSCMP. This function determines which input + * is selected for the negative and positive mux. + * + * @param base HSCMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void HSCMP_SetInputChannels(HSCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel); + +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * Normally, the HSCMP generates a CPU interrupt if there is a rising/falling event. When + * DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling + * event forces a DMA transfer request rather than a CPU interrupt instead. + * + * @param base HSCMP peripheral base address. + * @param enable "true" means enable DMA support, and "false" means disable DMA support. + */ +static inline void HSCMP_EnableDMA(HSCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= HSCMP_CCR1_DMA_EN_MASK; + } + else + { + base->CCR1 &= ~HSCMP_CCR1_DMA_EN_MASK; + } +} + +/*! + * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by + * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. + * The optionally inverted comparator output COUT_RAW is sampled on every bus clock + * when WINDOW=1 to generate COUTA. + * + * @param base HSCMP peripheral base address. + * @param enable "true" means enable window mode, and "false" means disable window mode. + */ +static inline void HSCMP_EnableWindowMode(HSCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= HSCMP_CCR1_WINDOW_EN_MASK; + } + else + { + base->CCR1 &= ~HSCMP_CCR1_WINDOW_EN_MASK; + } +} + +/*! + * @brief Configures the filter. + * + * @param base HSCMP peripheral base address. + * @param config Pointer to "hscmp_filter_config_t" structure. + */ +void HSCMP_SetFilterConfig(HSCMP_Type *base, const hscmp_filter_config_t *config); + +/*! + * @brief Configure the internal DAC module. + * + * @param base HSCMP peripheral base address. + * @param config Pointer to "hscmp_dac_config_t" structure. If config is "NULL", disable internal DAC. + */ +void HSCMP_SetDACConfig(HSCMP_Type *base, const hscmp_dac_config_t *config); + +/*! + * @brief Enable the interrupts. + * + * @param base HSCMP peripheral base address. + * @param mask Mask value for interrupts. See "_hscmp_interrupt_enable". + */ +static inline void HSCMP_EnableInterrupts(HSCMP_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disable the interrupts. + * + * @param base HSCMP peripheral base address. + * @param mask Mask value for interrupts. See "_hscmp_interrupt_enable". + */ +static inline void HSCMP_DisableInterrupts(HSCMP_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Get the HSCMP status flags. + * + * @param base HSCMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_hscmp_status_flags". + */ +static inline uint32_t HSCMP_GetStatusFlags(HSCMP_Type *base) +{ + return base->CSR; +} + +/*! + * @brief Clear the HSCMP status flags + * + * @param base HSCMP peripheral base address. + * @param mask Mask value for the flags. See "_hscmp_status_flags". + */ +static inline void HSCMP_ClearStatusFlags(HSCMP_Type *base, uint32_t mask) +{ + base->CSR = mask; +} + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_HSCMP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..b26dbe75bdcdcd9eea6bd42d923dfe36e9d26a20 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.c @@ -0,0 +1,2085 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" +#endif + +/*! @brief Common sets of flags used by the driver's transactional layer internally. */ +enum _i2c_flag_constants +{ + kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, + kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, +}; + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and + * `flexcomm_i2c_slave_irq_handler_t`. + */ +typedef union i2c_to_flexcomm +{ + flexcomm_i2c_master_irq_handler_t i2c_master_handler; + flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} i2c_to_flexcomm_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Waits for Master Pending status bit to set and check for bus error status. + * + * @param base The I2C peripheral base address. + * @return Bus status. + */ +static status_t I2C_PendingStatusWait(I2C_Type *base); + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param xfer The I2C transfer configuration structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Resets the slave hardware state machine. + * According to documentation, after disabling slave to rest the slave hardware state machine, the register + * configuration remains unchanged. + * @param base The I2C peripheral base address. + */ +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); + +/*! + * @brief Compute CLKDIV + * + * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. + * This setting is used by hardware during slave clock stretching. + * + * @param base The I2C peripheral base address. + * @return status of the operation + */ +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); + +/*! + * @brief Poll wait for the SLVPENDING flag. + * + * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. + * + * @param base The I2C peripheral base address. + * @return status register at time the SLVPENDING bit is read as set + */ +static uint32_t I2C_SlavePollPending(I2C_Type *base); + +/*! + * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). + * + * Sets the event type to transfer structure and invokes the event callback, if it has been + * enabled by eventMask. + * + * @param base The I2C peripheral base address. + * @param handle The I2C slave handle for non-blocking APIs. + * @param event The I2C slave event to invoke. + */ +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); + +/*! + * @brief Handle slave address match event. + * + * Called by Slave interrupt routine to ACK or NACK the matched address. + * It also determines master direction (read or write). + * + * @param base The I2C peripheral base address. + * @return true if the matched address is ACK'ed + * @return false if the matched address is NACK'ed + */ +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. + * @param txSize Size of txData buffer in bytes. + * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL + * if slave TX only. + * @param rxSize Size of rxData buffer in bytes. + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask); + +/*! + * @brief Execute master transfer software state machine until FIFOs are exhausted. + * + * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState + * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> + * kWaitForCompletionState + * + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief Checks the slave response to master's start signal. + * + * @param base I2C peripheral base address. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. + */ +static status_t I2C_MasterCheckStartResponse(I2C_Type *base); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The I2C peripheral base address. + * return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t i; + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) + { + if ((uint32_t)base == s_i2cBaseAddrs[i]) + { + break; + } + } + assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); + return i; +} + +/*! + * brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->baudRate_Bps = 100000U; + masterConfig->enableTimeout = false; + masterConfig->timeout_Ms = 35; +} + +/*! + * brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(base, masterConfig->enableMaster); + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); +} + +/*! + * brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base) +{ + I2C_MasterEnable(base, false); +} + +/*! + * brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * param base The I2C peripheral base address. + * return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base) +{ + uint32_t statusMask = base->STAT; + if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_MasterIdleFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; + } + return statusMask; +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I2C peripheral base address. + * param srcClock_Hz I2C functional clock frequency in Hertz. + * param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t scl, divider; + uint32_t mindivider; + uint32_t err, best_err; + uint32_t best_scl = 0U; + uint32_t best_div = 0U; + +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + /* + * RFT1717/RFT1437: workaround for hardware bug when using DMA + * I2C peripheral clock frequency has to be fixed at 8MHz + * source clock is 32MHz or 48MHz so divider is a round integer value + */ + best_div = srcClock_Hz / 8000000U; + best_scl = 8000000U / baudRate_Bps; + + if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) + { + best_scl = best_scl + 1U; + } + + /* + * Fallback to usual baudrate computation method, when: + * 1.Master SCL frequency does not fit in workaround range, + * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz + */ + if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) + { +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + + /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ + /* This is required in RM in order to generate 400kHz baudrate */ + mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; + /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, + update mindivider */ + if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) + { + mindivider = srcClock_Hz / 4U / baudRate_Bps; + } + /* Calculate the ideal div and scl value*/ + best_err = 0U; + for (divider = mindivider; divider <= 0x10000U; divider++) + { + /* Calculte ideal scl value, round up the value */ + scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; + + /* adjust it if it is out of range */ + scl = (scl > 18U) ? 18U : scl; + + /* calculate error */ + err = srcClock_Hz - (baudRate_Bps * scl * divider); + if ((err < best_err) || (best_err == 0U)) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if ((err == 0U) || (scl <= 4U)) + { + /* either exact value was found + or scl is at its min (it would be even smaller in the next iteration for sure) */ + break; + } + } +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + } +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); + if (best_scl % 2U == 0U) + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } + else + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } +} + +/*! + * brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * param base The I2C peripheral base address. + * param timeout_Ms Timeout value in millisecond. + * param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) +{ + assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); + + /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times + the I2C functional clock, we only need to calculate the high bits. */ + uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; + if (timeoutValue > 0x1000UL) + { + timeoutValue = 0x1000UL; + } + timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; + base->TIMEOUT = timeoutValue; +} + +static status_t I2C_PendingStatusWait(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint32_t status; + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + do + { + status = I2C_GetStatusFlags(base); + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + result = kStatus_I2C_EventTimeout; + } + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + result = kStatus_I2C_SclLowTimeout; + } +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + if (result != kStatus_Success) + { + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); + break; + } +#endif +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); + + if (waitTimes == 0U) + { +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); +#endif + return (uint32_t)kStatus_I2C_Timeout; + } +#else + } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); +#endif + + if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) + { + result = kStatus_I2C_ArbitrationLost; + } + + if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) + { + result = kStatus_I2C_StartStopError; + } + + /* Clear controller state. */ + I2C_ClearStatusFlags( + base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); + + return result; +} + +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) + { + return result; + } + + /* Write Address and RW bit to data register */ + base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); + /* Start the transfer */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + + return kStatus_Success; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) + { + return result; + } + + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + return kStatus_Success; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was sent successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + uint32_t master_state; + status_t err; + + const uint8_t *buf = (const uint8_t *)txBuff; + + assert(txBuff != NULL); + + err = kStatus_Success; + while (txSize != 0U) + { + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_TXREADY: + /* ready to send next byte */ + base->MSTDAT = *buf++; + txSize--; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + err = kStatus_I2C_Nak; + /* Issue nack signal when nacked by slave. */ + (void)I2C_MasterStop(base); + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + +#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Nak; + } +#endif + + if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Initiate stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + if (err != kStatus_Success) + { + return err; + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was received successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + uint32_t master_state; + status_t err; + + uint8_t *buf = (uint8_t *)(rxBuff); + + assert(rxBuff != NULL); + + err = kStatus_Success; + while (rxSize != 0U) + { + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_RXREADY: + /* ready to send next byte */ + *(buf++) = (uint8_t)base->MSTDAT; + if (--rxSize != 0U) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) + { + /* initiate NAK and stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + } + } + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + return kStatus_Success; +} + +static status_t I2C_MasterCheckStartResponse(I2C_Type *base) +{ + /* Wait for start signal to be transmitted. */ + status_t result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + return result; + } + + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + uint32_t subaddress; + uint8_t subaddrBuf[4]; + i2c_direction_t direction; + int i; + + assert(xfer != NULL); + + /* If start signal is requested, send start signal. */ + if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + if ((xfer->subaddressSize) != 0U) + { + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + /* Send subaddress. */ + result = + I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + } + else if (xfer->direction == kI2C_Read) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + } + } + else + { + /* Empty else block to avoid MISRA 14.1 violation. */ + } + } + } + } + + if (result == kStatus_Success) + { + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) + { + /* Transmit data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else + { + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) + { + /* Receive Data. */ + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + } + } + + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param xfer The pointer to the transfer descriptor. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + /* Clear error flags. */ + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success + * retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * retval kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + status_t result = kStatus_Success; + uint32_t master_state; + + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Wait until module is ready */ + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + handle->state = (uint8_t)kIdleState; + return result; + } + + /* Get the state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until the STOP is completed */ + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + handle->state = (uint8_t)kIdleState; + return result; + } + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + handle->checkAddrNack = false; + } + return kStatus_Success; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + struct _i2c_master_transfer *transfer; + + handle->transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytes = transfer->dataSize; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + handle->checkAddrNack = false; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (uint8_t)kReceiveDataBeginState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0U) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; + } + + return kStatus_Success; +} + +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + status_t err; + + transfer = &(handle->transfer); + bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) +#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ + || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) +#endif + ; + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) + { + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + return kStatus_I2C_ArbitrationLost; + } + + if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) + { + I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + return kStatus_I2C_StartStopError; + } + + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + return kStatus_I2C_SclLowTimeout; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) + { + return kStatus_I2C_Busy; + } + + /* Get the hardware state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || + (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && + (ignoreNak != true)) + { + /* Slave NACKed last byte, issue stop and return error */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) + { + return kStatus_I2C_Addr_Nak; + } + else /* Otherwise just return kStatus_I2C_Nak */ + { + return kStatus_I2C_Nak; + } + } + + err = kStatus_Success; + switch (handle->state) + { + case (uint8_t)kStartState: + if (handle->remainingSubaddr != 0U) + { + /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; + handle->state = (uint8_t)kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; + } + else + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; + } + /* Send start condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + break; + + case (uint8_t)kTransmitSubaddrState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + /* Most significant subaddress byte comes first */ + base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--(handle->remainingSubaddr) != 0U) + { + /* There are still subaddress bytes to be transmitted */ + break; + } + if (handle->remainingBytes != 0U) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kTransmitDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + base->MSTDAT = *(handle->buf)++; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--handle->remainingBytes == 0U) + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + handle->transferCount++; + break; + + case (uint8_t)kReceiveDataBeginState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + (void)base->MSTDAT; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + handle->state = (uint8_t)kReceiveDataState; + break; + + case (uint8_t)kReceiveDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + *(handle->buf)++ = (uint8_t)base->MSTDAT; + if (--handle->remainingBytes != 0U) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + /* No more data expected, issue NACK and STOP right away */ + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; + } + handle->transferCount++; + break; + + case (uint8_t)kStopState: + handle->checkAddrNack = false; + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + + case (uint8_t)kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I2C_RunTransferStateMachine(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ +} + +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) +{ + uint32_t dataSetupTime_ns; + + switch ((uint8_t)(busSpeed)) + { + case (uint8_t)kI2C_SlaveStandardMode: + dataSetupTime_ns = 250U; + break; + + case (uint8_t)kI2C_SlaveFastMode: + dataSetupTime_ns = 100U; + break; + + case (uint8_t)kI2C_SlaveFastModePlus: + dataSetupTime_ns = 50U; + break; + + case (uint8_t)kI2C_SlaveHsMode: + dataSetupTime_ns = 10U; + break; + + default: + dataSetupTime_ns = 0U; + break; + } + + if (0U == dataSetupTime_ns) + { + return kStatus_InvalidArgument; + } + + /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ + *divVal = srcClock_Hz / 1000U; + *divVal = (*divVal) * dataSetupTime_ns; + *divVal = (*divVal) / 1000000U; + + if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) + { + *divVal = I2C_CLKDIV_DIVVAL_MASK; + } + + return kStatus_Success; +} + +static uint32_t I2C_SlavePollPending(I2C_Type *base) +{ + uint32_t stat; + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + stat = base->STAT; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); + + if (waitTimes == 0U) + { + return (uint32_t)kStatus_I2C_Timeout; + } +#else + } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif + + return stat; +} + +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) +{ + uint32_t eventMask = handle->transfer.eventMask; + handle->transfer.event = event; + if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) + { + handle->callback(base, &handle->transfer, handle->userData); + + size_t txSize = handle->transfer.txSize; + size_t rxSize = handle->transfer.rxSize; + /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ + if (false == handle->isBusy) + { + if (((handle->transfer.txData != NULL) && (txSize != 0U)) || + ((handle->transfer.rxData != NULL) && (rxSize != 0U))) + { + handle->isBusy = true; + } + } + + /* Clear the transferred count now that we have a new buffer. */ + if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) + { + handle->transfer.transferredCount = 0; + } + } +} + +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint8_t addressByte0; + size_t txSize; + size_t rxSize; + + addressByte0 = (uint8_t)base->SLVDAT; + + /* store the matched address */ + handle->transfer.receivedAddress = addressByte0; + + /* R/nW */ + if ((addressByte0 & 1U) != 0U) + { + txSize = handle->transfer.txSize; + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + txSize = handle->transfer.txSize; + /* NACK if we have no data in this transfer. */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants to read, so slave transmit is next state */ + handle->slaveFsm = kI2C_SlaveFsmTransmit; + } + else + { + rxSize = handle->transfer.rxSize; + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + rxSize = handle->transfer.rxSize; + /* NACK if we have no data in this transfer */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants write, so slave receive is next state */ + handle->slaveFsm = kI2C_SlaveFsmReceive; + } + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + return true; +} + +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask) +{ + assert(handle != NULL); + + status_t status; + status = kStatus_Success; + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + status = kStatus_I2C_Busy; + } + + /* Save transfer into handle. */ + handle->transfer.txData = (const uint8_t *)txData; + handle->transfer.txSize = txSize; + handle->transfer.rxData = (uint8_t *)rxData; + handle->transfer.rxSize = rxSize; + handle->transfer.transferredCount = 0; + handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; + handle->isBusy = true; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* Clear w1c flags. */ + base->STAT |= 0u; + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + return status; +} + +/*! + * brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param txData Pointer to data to send to master. + * param txSize Size of txData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); +} + +/*! + * brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param rxData Pointer to data to store data from master. + * param rxSize Size of rxData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); +} + +/*! + * brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * param base The I2C peripheral base address. + * param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * param address The slave address to be stored to the address register for matching. + * param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable) +{ + base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); +} + +/*! + * brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a + * address0.address member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + i2c_slave_config_t mySlaveConfig = {0}; + + /* default config enables slave address 0 match to general I2C call address zero */ + mySlaveConfig.enableSlave = true; + mySlaveConfig.address1.addressDisable = true; + mySlaveConfig.address2.addressDisable = true; + mySlaveConfig.address3.addressDisable = true; + + *slaveConfig = mySlaveConfig; +} + +/*! + * brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * param base The I2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + status_t status; + uint32_t divVal = 0; + + /* configure data setup time used when slave stretches clock */ + status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); + if (kStatus_Success != status) + { + return status; + } + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + + /* I2C Clock Divider register */ + base->CLKDIV = divVal; + + /* set Slave address */ + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, + slaveConfig->address0.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, + slaveConfig->address1.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, + slaveConfig->address2.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, + slaveConfig->address3.addressDisable); + + /* set Slave address 0 qual */ + base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); + + /* set Slave enable */ + base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); + + return status; +} + +/*! + * brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been sent. + * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + const uint8_t *buf = txBuff; + uint32_t stat; + bool slaveAddress; + bool slaveTransmit; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); + + /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ + if (!(slaveAddress || slaveTransmit)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* send bytes up to txSize */ + while (txSize != 0U) + { + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); + + if (!slaveTransmit) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Write 8 bits of data to the SLVDAT register */ + base->SLVDAT = I2C_SLVDAT_DATA(*buf); + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + txSize--; + + if (txSize != 0U) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been received. + * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + uint8_t *buf = rxBuff; + uint32_t stat; + bool slaveAddress; + bool slaveReceive; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); + + /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ + if (!(slaveAddress || slaveReceive)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* receive bytes up to rxSize */ + while (rxSize != 0U) + { + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); + + if (!slaveReceive) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Read 8 bits of data from the SLVDAT register */ + *buf = (uint8_t)base->SLVDAT; + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + rxSize--; + + if (rxSize != 0U) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* initialize fsm */ + handle->slaveFsm = kI2C_SlaveFsmAddressMatch; + + /* store pointer to handle into transfer struct */ + handle->transfer.handle = handle; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); +} + +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * retval kStatus_Success + * retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + /* Set the SLVEN bit to 0 in the CFG register. */ + I2C_SlaveEnable(base, false); + + handle->isBusy = false; + handle->transfer.txSize = 0U; + handle->transfer.rxSize = 0U; +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint32_t i2cStatus = base->STAT; + uint8_t tmpdata; + size_t txSize; + size_t rxSize; + + if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); + I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); + } + + /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ + if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) + { + bool slaveAddress = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + + if (slaveAddress) + { + (void)I2C_SlaveAddressIRQ(base, handle); + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); + } + else + { + switch (handle->slaveFsm) + { + case kI2C_SlaveFsmReceive: + { + bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_RX); + + if (slaveReceive) + { + rxSize = handle->transfer.rxSize; + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + rxSize = handle->transfer.rxSize; + /* receive a byte */ + if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) + { + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + tmpdata = (uint8_t)base->SLVDAT; + *(handle->transfer.rxData) = tmpdata; + (handle->transfer.rxSize)--; + (handle->transfer.rxData)++; + (handle->transfer.transferredCount)++; + } + + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; + /* is this last transaction for this transfer? allow next transaction */ + if ((0U == rxSize) && (0U == txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + case kI2C_SlaveFsmTransmit: + { + bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_TX); + + if (slaveTransmit) + { + txSize = handle->transfer.txSize; + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + txSize = handle->transfer.txSize; + /* transmit a byte */ + if ((handle->transfer.txData != NULL) && (txSize != 0U)) + { + base->SLVDAT = *(handle->transfer.txData); + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + (handle->transfer.txSize)--; + (handle->transfer.txData)++; + (handle->transfer.transferredCount)++; + } + + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; + /* is this last transaction for this transfer? allow next transaction */ + if ((0U == rxSize) && (0U == txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + default: + /* incorrect state, slv_abort()? */ + break; + } + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..b521a1ad7568b880c7e4742ea080eaf62dd2d190 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c.h @@ -0,0 +1,1148 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define I2C_CFG_MASK 0x1f + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ +#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK +#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ + 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ +#endif + +/* definitions for MSTCODE bits in I2C Status register STAT */ +#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ + +/* definitions for SLVSTATE bits in I2C Status register STAT */ +#define I2C_STAT_SLVST_ADDR (0) +#define I2C_STAT_SLVST_RX (1) +#define I2C_STAT_SLVST_TX (2) + +/*! @brief I2C status return codes. */ +enum +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ + kStatus_I2C_Nak = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_I2C_InvalidParameter = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ + kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ + kStatus_I2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ + kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ + kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ + kStatus_I2C_Timeout = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, + 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ + kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ + kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! + * @brief I2C status flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_status_flags +{ + kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ + kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ + kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ + kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ + kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ + kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ + kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ + kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 + = yes, 1 = no). bit 11 */ + kI2C_SlaveSelected = + I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ + kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event + took place, w1c). bit 15 */ + kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ + kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ + kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ + kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ + kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ + kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ + kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ + kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ + kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ + kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ + kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ + kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ + kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ + + /* All master flags that can be cleared by software */ + kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, + /* All slave flags that can be cleared by software */ + kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, + /* All common flags that can be cleared by software */ + kI2C_CommonAllClearFlags = + kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, +}; + +/*! + * @brief I2C interrupt enable. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_interrupt_enable +{ + kI2C_MasterPendingInterruptEnable = + I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ + kI2C_MasterArbitrationLostInterruptEnable = + I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ + kI2C_MasterStartStopErrorInterruptEnable = + I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ + kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ + kI2C_SlaveNotStretchingInterruptEnable = + I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when + this interrupt occurs. */ + kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ + kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ + kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ + kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ + kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ + kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ + + /* All master interrupt sources */ + kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | + kI2C_MasterStartStopErrorInterruptEnable, + /* All slave interrupt sources */ + kI2C_SlaveAllInterruptEnable = + kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, + /* All common interrupt sources */ + kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | + kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | + kI2C_SclTimeoutInterruptEnable, +}; +/*! @} */ + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0U, /*!< Master transmit. */ + kI2C_Read = 1U /*!< Master receive. */ +} i2c_direction_t; + +/*! + * @brief Structure with settings to initialize the I2C master module. + * + * This structure holds configuration settings for the I2C peripheral. To initialize this + * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ + bool enableTimeout; /*!< Enable internal timeout function. */ + uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ +} i2c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief I2C master transfer typedef */ +typedef struct _i2c_master_transfer i2c_master_transfer_t; + +/*! @brief I2C master handle typedef */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to I2C_MasterTransferCreateHandle(). + * + * @param base The I2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i2c_master_transfer::flags field. + */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i2c_transfer_states +{ + kIdleState = 0, + kTransmitSubaddrState, + kTransmitDataState, + kReceiveDataBeginState, + kReceiveDataState, + kReceiveLastDataState, + kStartState, + kStopState, + kWaitForCompletionState +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. + */ +struct _i2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available + options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ + i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ +/*! @brief I2C slave address register. */ +typedef enum _i2c_slave_address_register +{ + kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ + kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ + kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ + kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ +} i2c_slave_address_register_t; + +/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ +typedef struct _i2c_slave_address +{ + uint8_t address; /*!< 7-bit Slave address SLVADR. */ + bool addressDisable; /*!< Slave address disable SADISABLE. */ +} i2c_slave_address_t; + +/*! @brief I2C slave address match options. */ +typedef enum _i2c_slave_address_qual_mode +{ + kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ + kI2C_QualModeExtend = + 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ +} i2c_slave_address_qual_mode_t; + +/*! @brief I2C slave bus speed options. */ +typedef enum _i2c_slave_bus_speed +{ + kI2C_SlaveStandardMode = 0U, + kI2C_SlaveFastMode = 1U, + kI2C_SlaveFastModePlus = 2U, + kI2C_SlaveHsMode = 3U, +} i2c_slave_bus_speed_t; + +/*! + * @brief Structure with settings to initialize the I2C slave module. + * + * This structure holds configuration settings for the I2C slave peripheral. To initialize this + * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_slave_config +{ + i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ + i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ + uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ + i2c_slave_bus_speed_t + busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must + provide sufficient data setup time to the master before releasing the stretched clock. + This is accomplished by inserting one clock time of CLKDIV at that point. + The #busSpeed value is used to configure CLKDIV + such that one clock time is greater than the tSU;DAT value noted + in the I2C bus specification for the I2C mode that is being used. + If the #busSpeed mode is unknown at compile time, use the longest data setup time + kI2C_SlaveStandardMode (250 ns) */ + bool enableSlave; /*!< Enable slave mode. */ +} i2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ + kI2C_SlaveDeselectedEvent = + 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | + kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave transfer structure */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint8_t *rxData; /*!< Transfer buffer for receive data */ + const uint8_t *txData; /*!< Transfer buffer for transmit data */ + size_t txSize; /*!< Transfer size */ + size_t rxSize; /*!< Transfer size */ + size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ +} i2c_slave_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the I2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the I2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief I2C slave software finite state machine states. + */ +typedef enum _i2c_slave_fsm +{ + kI2C_SlaveFsmAddressMatch = 0u, + kI2C_SlaveFsmReceive = 2u, + kI2C_SlaveFsmTransmit = 3u, +} i2c_slave_fsm_t; + +/*! + * @brief I2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_slave_handle +{ + volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ + volatile bool isBusy; /*!< Whether transfer is busy. */ + volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the I2C master peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +static inline void I2C_MasterReset(I2C_Type *base) +{ +} + +/*! + * @brief Enables or disables the I2C module as master. + * + * @param base The I2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified I2C as master. + */ +static inline void I2C_MasterEnable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; + } + else + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; + } +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ +/*! + * @brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see @ref _i2c_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base); + +/*! + * @brief Clears the I2C status flag state. + * + * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see + * the clearable flags. Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in + * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass + * the result of a previous call to I2C_GetStatusFlags(). + * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. + */ +static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Only deal with the clearable flags */ + statusMask &= + ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); + base->STAT = statusMask; +} + +/*! + * @brief Clears the I2C master status flag state. + * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags + * The following status register flags can be cleared: + * - #kI2C_MasterArbitrationLostFlag + * - #kI2C_MasterStartStopErrorFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_GetStatusFlags(). + * @see _i2c_status_flags. + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just master status flags */ + base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENSET = interruptMask; +} + +/*! + * @brief Disables the I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) +{ + return base->INTSTAT; +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I2C peripheral base address. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + * @param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * @param base The I2C peripheral base address. + * @param timeout_Ms Timeout value in millisecond. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) +{ + /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ + return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); +} + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + return I2C_MasterStart(base, address, direction); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param xfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ /* end of i2c_master_driver */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a + * address0.address member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * @param base The I2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * @param base The I2C peripheral base address. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * @param address The slave address to be stored to the address register for matching. + * @param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable); + +/*! + * @brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Enables or disables the I2C module as slave. + * + * @param base The I2C peripheral base address. + * @param enable True to enable or flase to disable. + */ +static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) +{ + /* Set or clear the SLVEN bit in the CFG register. */ + base->CFG = I2C_CFG_SLVEN(enable); +} + +/*@}*/ /* end of Slave initialization and deinitialization */ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: + * - slave deselected flag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_SlaveGetStatusFlags(). + * @see _i2c_slave_flags. + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just slave status flags */ + base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; +} + +/*@}*/ /* end of Slave status */ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been sent. + * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been received. + * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*@}*/ /* end of Slave bus operations */ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param txData Pointer to data to send to master. + * @param txSize Size of txData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); + +/*! + * @brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param rxData Pointer to data to store data from master. + * @param rxSize Size of rxData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. + * + * @param base The I2C peripheral base address. + * @param transfer The I2C slave transfer. + * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) +{ + return transfer->receivedAddress; +} + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*@}*/ /* end of Slave non-blocking */ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*@}*/ /* end of Slave IRQ handler */ + +/*! @} */ /* end of i2c_slave_driver */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2C_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..45d47e59073ecfd17b6665c593f884fc501f34ea --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c_dma.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" +#endif + +/*transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0U; + handle->remainingBytesDMA = 0U; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0U; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + handle->checkAddrNack = false; + /* Start condition shall not be ommited, switch directly to next phase */ + if (transfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0U) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; + } + + return kStatus_Success; +} + +static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + uint32_t transfer_size; + dma_transfer_config_t xferConfig; + uint32_t address; + address = (uint32_t)&base->MSTDAT; + + /* Update transfer count */ + int32_t count = handle->buf - (uint8_t *)handle->transfer.data; + assert(count >= 0); + handle->transferCount = (uint32_t)count; + + /* Check if there is anything to be transferred at all */ + if (handle->remainingBytesDMA == 0U) + { + /* No data to be transferrred, disable DMA */ + base->MSTCTL = 0; + return; + } + + /* Calculate transfer size */ + transfer_size = handle->remainingBytesDMA; + if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) + { + transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; + } + + switch (handle->transfer.direction) + { + case kI2C_Write: + DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, + kDMA_MemoryToPeripheral, NULL); + break; + + case kI2C_Read: + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, + kDMA_PeripheralToMemory, NULL); + break; + + default: + /* This should never happen */ + assert(0); + break; + } + + (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + + handle->remainingBytesDMA -= transfer_size; + handle->buf += transfer_size; + handle->checkAddrNack = false; +} + +static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + dma_transfer_config_t xferConfig; + status_t err; + uint32_t start_flag = 0U; + uint32_t address; + address = (uint32_t)&base->MSTDAT; + + transfer = &(handle->transfer); + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_ArbitrationLost; + } + + if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_StartStopError; + } + + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_SclLowTimeout; + } + + if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) + { + return kStatus_I2C_Busy; + } + + /* Get the state of the I2C module */ + master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) + { + /* Slave NACKed last byte, issue stop and return error */ + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) + { + return kStatus_I2C_Addr_Nak; + } + else + { + return kStatus_I2C_Nak; + } + } + + err = kStatus_Success; + + if (handle->state == (uint8_t)kStartState) + { + /* set start flag for later use */ + start_flag = I2C_MSTCTL_MSTSTART_MASK; + + if (handle->remainingSubaddr != 0U) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = (uint8_t)kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + if (transfer->dataSize == 0U) + { + /* No data to be transferred, initiate start and schedule stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = (uint8_t)kStopState; + return err; + } + handle->state = (uint8_t)kTransmitDataState; + } + else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + if (transfer->dataSize == 1U) + { + /* The very last byte is always received by means of SW */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = (uint8_t)kReceiveLastDataState; + return err; + } + handle->state = (uint8_t)kReceiveDataState; + } + else + { + handle->state = (uint8_t)kIdleState; + err = kStatus_I2C_UnexpectedState; + return err; + } + } + + switch (handle->state) + { + case (uint8_t)kTransmitSubaddrState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + + /* Prepare and submit DMA transfer. */ + DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), + handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); + (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + handle->remainingSubaddr = 0; + if (transfer->dataSize != 0U) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kTransmitDataState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize; + + I2C_RunDMATransfer(base, handle); + + /* Schedule stop condition */ + handle->state = (uint8_t)kStopState; + handle->checkAddrNack = false; + break; + + case (uint8_t)kReceiveDataState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) + { + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + return kStatus_I2C_UnexpectedState; + } + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize - 1U; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* Read the master data register to avoid the data be read again */ + (void)base->MSTDAT; + } + I2C_RunDMATransfer(base, handle); + + /* Schedule reception of last data byte */ + handle->state = (uint8_t)kReceiveLastDataState; + handle->checkAddrNack = false; + break; + + case (uint8_t)kReceiveLastDataState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + + ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; + handle->transferCount++; + + /* No more data expected, issue NACK and STOP right away */ + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kStopState: + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + + case (uint8_t)kStartState: + case (uint8_t)kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + i2c_master_dma_private_handle_t *dmaPrivateHandle; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; + I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); +} + +/*! + * brief Init the I2C handle which is used in transactional functions + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param callback pointer to user callback function + * param userData user param passed to the callback function + * param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + assert(handle != NULL); + assert(dmaHandle != NULL); + + uint32_t instance; + i2c_dma_to_flexcomm_t handler; + handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + (void)EnableIRQ(s_i2cIRQ[instance]); + + /* Set the handle for DMA. */ + handle->dmaHandle = dmaHandle; + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); +} + +/*! + * brief Performs a master dma non-blocking transfer on the I2C bus + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param xfer pointer to transfer structure of i2c_master_transfer_t + * retval kStatus_Success Sucessully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachineDMA(base, handle, xfer); + + /* Clear error flags. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources */ + /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. + The master pending flag is not set during dma transfer. */ + I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + + return result; +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Abort a master dma non-blocking transfer in a early time + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + uint32_t status; + uint32_t master_state; + + if (handle->state != (uint8_t)kIdleState) + { + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA */ + base->MSTCTL = 0; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Get the state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + } + + /* Reset the state to idle. */ + handle->state = (uint8_t)kIdleState; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..07899f9c7c9ba33d1a70f987a3fcb2d44c40d331 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2c_dma.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dma.h" + +/*! + * @addtogroup i2c_dma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C DMA driver version. */ +#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ +#define I2C_MAX_DMA_TRANSFER_COUNT 1024 + +/*! @brief I2C master dma handle typedef. */ +typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; + +/*! @brief I2C master dma transfer callback typedef. */ +typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, + i2c_master_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Typedef for master dma handler. */ +typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/*! @brief I2C master dma transfer structure. */ +struct _i2c_master_dma_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + dma_handle_t *dmaHandle; /*!< The DMA handler used. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block DMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transactional functions + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param callback pointer to user callback function + * @param userData user param passed to the callback function + * @param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Performs a master dma non-blocking transfer on the I2C bus + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param xfer pointer to transfer structure of i2c_master_transfer_t + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a dma non-blocking transfer + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master dma non-blocking transfer in a early time + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..28a36b3ce6fcacbfe7d6c67cd07891f3d3f7688e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.c @@ -0,0 +1,1163 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2s.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" +#endif + +/* TODO - absent in device header files, should be there */ +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +/*! @brief _i2s_state I2S states. */ +enum +{ + kI2S_StateIdle = 0x0, /*!< Not performing transfer */ + kI2S_StateTx, /*!< Performing transmit */ + kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ + kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ + kI2S_StateRx, /*!< Performing receive */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config); +static void I2S_TxEnable(I2S_Type *base, bool enable); +static void I2S_RxEnable(I2S_Type *base, bool enable); +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2S peripheral base address. + * @return I2S instance number starting from 0. + */ +static uint32_t I2S_GetInstance(I2S_Type *base) +{ + uint32_t i; + for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) + { + if ((uint32_t)base == s_i2sBaseAddrs[i]) + { + return i; + } + } + assert(false); + return 0; +} + +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void I2S_SetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; + + assert(bitClockDivider >= 1U); + base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); +} + +/*! + * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ + cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ + trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +/*! + * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ + trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +/*! + * brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ +void I2S_TxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalMaster; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + config->pdmData = false; +#endif + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = true; + config->pack48 = false; +} + +/*! + * brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ +void I2S_RxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalSlave; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + config->pdmData = false; +#endif + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = false; + config->pack48 = false; +} + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config) +{ + assert(config != NULL); + + uint32_t cfg1 = 0U; + uint32_t cfg2 = 0U; + + /* set master/slave configuration */ + cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); + + /* set I2S mode */ + cfg1 |= I2S_CFG1_MODE(config->mode); + + /* set right low (channel swap) */ + cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); + + /* set data justification */ + cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); + +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) + { + /* set source to PDM dmic */ + cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); + } +#endif + + /* set SCLK polarity */ + cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); + + /* set WS polarity */ + cfg1 |= I2S_CFG1_WS_POL(config->wsPol); + + /* set mono mode */ + cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); + + /* set data length */ + cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); + + /* set frame length */ + cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); + + /* set data position of this channel pair within the frame */ + cfg2 |= I2S_CFG2_POSITION(config->position); + + /* write to registers */ + base->CFG1 = cfg1; + base->CFG2 = cfg2; + + /* set the clock divider */ + base->DIV = I2S_DIV_DIV(config->divider - 1UL); +} + +/*! + * brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * param base I2S base pointer. + */ +void I2S_Deinit(I2S_Type *base) +{ + /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ +} + +static void I2S_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_Enable(base); + I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + } + else + { + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_Enable(base); + I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + } + else + { + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) +{ + assert(transfer->data != NULL); + + if (transfer->data == NULL) + { + return kStatus_InvalidArgument; + } + + assert(transfer->dataSize > 0U); + if (transfer->dataSize <= 0U) + { + return kStatus_InvalidArgument; + } + + if (handle->dataLength == 4U) + { + /* No alignment and data length requirements */ + } + else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) + { + assert((((uint32_t)transfer->data) % 2U) == 0U); + if ((((uint32_t)transfer->data) % 2U) != 0U) + { + /* Data not 2-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 2U) == 0U); + if ((transfer->dataSize % 2U) != 0U) + { + /* Data not in pairs of left/right channel bytes */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) + { + assert((transfer->dataSize % 6U) == 0U); + if ((transfer->dataSize % 6U) != 0U) + { + /* Data lenght not multiply of 6 */ + return kStatus_InvalidArgument; + } + + assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); + if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + } + else /* if (handle->dataLength >= 25U) */ + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + if (handle->oneChannel) + { + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else + { + assert((transfer->dataSize % 8U) == 0U); + if ((transfer->dataSize % 8U) != 0U) + { + /* Data lenght not multiply of 8 */ + return kStatus_InvalidArgument; + } + } + } + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +/*! + * brief Enables I2S secondary channel. + * + * param base I2S base pointer. + * param channel seondary channel channel number, reference _i2s_secondary_channel. + * param oneChannel true is treated as single channel, functionality left channel for this pair. + * param position define the location within the frame of the data, should not bigger than 0x1FFU. + */ +void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) +{ + assert(channel <= (uint32_t)kI2S_SecondaryChannel3); +#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn + assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); +#endif + + uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; + uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; + + pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; + pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); + + pcfg2 &= ~I2S_CFG2_POSITION_MASK; + pcfg2 |= I2S_CFG2_POSITION(position); + + base->SECCHANNEL[channel].PCFG1 = pcfg1; + base->SECCHANNEL[channel].PCFG2 = pcfg2; +} +#endif + +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + + /* Clear out the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2S_GetInstance(base); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; + handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + (void)EnableIRQ(s_i2sIRQ[instance]); +} + +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle != NULL); + + status_t result; + + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->state = (uint32_t)kI2S_StateTx; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); + I2S_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts sending of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable I2S operation and interrupts */ + I2S_TxEnable(base, false); + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Clear transfer queue */ + (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + + /* Clear out the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2S_GetInstance(base); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; + handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + + (void)EnableIRQ(s_i2sIRQ[instance]); +} + +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle != NULL); + + status_t result; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->state = (uint32_t)kI2S_StateRx; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); + I2S_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts receiving of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable I2S operation and interrupts */ + I2S_RxEnable(base, false); + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Clear transfer queue */ + (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +/*! + * brief Returns number of bytes transferred so far. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->transferCount; + + return kStatus_Success; +} + +/*! + * brief Returns number of buffer underruns or overruns. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->errorCount; + + return kStatus_Success; +} + +/*! + * brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + uint8_t queueDriverIndex = handle->queueDriver; + uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; + uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; + + if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) + { + handle->errorCount++; + + /* Clear TX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); + } + + if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) + { + if (handle->state == (uint32_t)kI2S_StateTx) + { + /* Send data */ + + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) + { + /* Write output data */ + if (handle->dataLength == 4U) + { + data = *((uint8_t *)dataAddr); + base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); + dataAddr++; + handle->transferCount++; + dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = *((volatile uint16_t *)dataAddr); + if (handle->oneChannel) + { + base->FIFOWR = (data & 0xFFU); + dataAddr += sizeof(uint8_t); + handle->transferCount += sizeof(uint8_t); + dataSize -= sizeof(uint8_t); + } + else + { + base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + } + else if (handle->dataLength <= 16U) + { + data = *((volatile uint32_t *)(dataAddr)); + if (handle->oneChannel) + { + base->FIFOWR = data & 0xFFFFU; + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + base->FIFOWR = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + handle->useFifo48H = false; + } + else + { + base->FIFOWR = *((volatile uint32_t *)(dataAddr)); + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + handle->useFifo48H = true; + } + } + else + { + data = (uint32_t)(*(uint8_t *)(dataAddr++)); + data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; + data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; + if ((handle->useFifo48H) && (handle->oneChannel == false)) + { + base->FIFOWR48H = data; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = data; + handle->useFifo48H = true; + } + handle->transferCount += 3U; + dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + base->FIFOWR = *((volatile uint32_t *)(dataAddr)); + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + + if (dataSize == 0U) + { + handle->i2sQueue[queueDriverIndex].dataSize = 0U; + /* Actual data buffer sent out, switch to a next one */ + handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + /* Check if the next buffer contains anything to send */ + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Everything has been written to FIFO */ + handle->state = kI2S_StateTxWaitToWriteDummyData; + break; + } + } + else + { + handle->i2sQueue[queueDriverIndex].dataSize = dataSize; + handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; + } + } + } + else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) + { + /* Write dummy data */ + if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = 0U; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = 0U; + base->FIFOWR48H = 0U; + } + } + else + { + base->FIFOWR = 0U; + } + + /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ + base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; + handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; + } + else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) + { + /* FIFO, including additional dummy data, has been emptied now, + * all relevant data should have been output from peripheral */ + + /* Stop transfer */ + I2S_Disable(base); + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + } + else + { + /* Do nothing */ + } + + /* Clear TX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); + } +} + +/*! + * brief Invoked from interrupt handler when receive FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + uint8_t queueDriverIndex = handle->queueDriver; + uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; + uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; + + if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) + { + handle->errorCount++; + + /* Clear RX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); + } + + if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) + { + while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) + { + /* Read input data */ + if (handle->dataLength == 4U) + { + data = base->FIFORD; + *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); + dataAddr++; + handle->transferCount++; + dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = base->FIFORD; + + if (handle->oneChannel) + { + *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); + dataAddr += sizeof(uint8_t); + handle->transferCount += sizeof(uint8_t); + dataSize -= sizeof(uint8_t); + } + else + { + *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + } + else if (handle->dataLength <= 16U) + { + data = base->FIFORD; + + if (handle->oneChannel) + { + *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + + *((volatile uint16_t *)dataAddr) = (uint16_t)data; + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + } + else + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + } + + *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); + *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); + *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); + handle->transferCount += 3U; + dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + data = base->FIFORD; + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + + if (dataSize == 0U) + { + handle->i2sQueue[queueDriverIndex].dataSize = 0U; + /* Actual data buffer filled with input data, switch to a next one */ + handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* No other buffer prepared to receive data into */ + + /* Disable I2S operation and interrupts */ + I2S_Disable(base); + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + + return; + } + } + else + { + handle->i2sQueue[queueDriverIndex].dataSize = dataSize; + handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; + } + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..dd93f9d08abf758d90cf9b195e54b9ef15407a0a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s.h @@ -0,0 +1,505 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2S_H_ +#define _FSL_I2S_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ + +/*! @brief I2S driver version 2.2.2. */ +#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*@}*/ + +#ifndef I2S_NUM_BUFFERS + +/*! @brief Number of buffers . */ +#define I2S_NUM_BUFFERS (4U) + +#endif + +/*! @brief _i2s_status I2S status codes. */ +enum +{ + kStatus_I2S_BufferComplete = + MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ + kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ + kStatus_I2S_Busy = + MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ +}; + +/*! + * @brief I2S flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +typedef enum _i2s_flags +{ + kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ + kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ + kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ + kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ +} i2s_flags_t; + +/*! @brief Master / slave mode. */ +typedef enum _i2s_master_slave +{ + kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ + kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ + kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ + kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ +} i2s_master_slave_t; + +/*! @brief I2S mode. */ +typedef enum _i2s_mode +{ + kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ + kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ + kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ + kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ +} i2s_mode_t; + +/*! @brief _i2s_secondary_channel I2S secondary channel. */ +enum +{ + kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ + kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ + kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ +}; + +/*! @brief I2S configuration structure. */ +typedef struct _i2s_config +{ + i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ + i2s_mode_t mode; /*!< I2S mode */ + bool rightLow; /*!< Right channel data in low portion of FIFO */ + bool leftJust; /*!< Left justify data in FIFO */ +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + bool pdmData; /*!< Data source is the D-Mic subsystem */ +#endif + bool sckPol; /*!< SCK polarity */ + bool wsPol; /*!< WS polarity */ + uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + uint16_t frameLength; /*!< Frame width (4 - 512) */ + uint16_t position; /*!< Data position in the frame */ + uint8_t watermark; /*!< FIFO trigger level */ + bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ +} i2s_config_t; + +/*! @brief Buffer to transfer from or receive audio data into. */ +typedef struct _i2s_transfer +{ + uint8_t *data; /*!< Pointer to data buffer. */ + size_t dataSize; /*!< Buffer size in bytes. */ +} i2s_transfer_t; + +/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ +typedef struct _i2s_handle i2s_handle_t; + +/*! + * @brief Callback function invoked from transactional API + * on completion of a single buffer transfer. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_transfer_callback_t)(I2S_Type *base, + i2s_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! @brief Members not to be accessed / modified outside of the driver. */ +struct _i2s_handle +{ + volatile uint32_t state; /*!< State of transfer */ + i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ + uint8_t watermark; /*!< FIFO trigger level */ + bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ + + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ + volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ + volatile uint32_t transferCount; /*!< Number of bytes transferred */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + @code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_TxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + @code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_RxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * @param base I2S base pointer. + */ +void I2S_Deinit(I2S_Type *base); + +/*! + * @brief Transmitter/Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth audio data bitWidth. + * @param channelNumbers audio channel numbers. + */ +void I2S_SetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! @} */ + +/*! + * @name Non-blocking API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts sending of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts receiving of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! + * @brief Returns number of buffer underruns or overruns. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! @} */ + +/*! + * @name Enable / disable + * @{ + */ + +/*! + * @brief Enables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Enable(I2S_Type *base) +{ + base->CFG1 |= I2S_CFG1_MAINENABLE(1U); +} + +#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +/*! + * @brief Enables I2S secondary channel. + * + * @param base I2S base pointer. + * @param channel seondary channel channel number, reference _i2s_secondary_channel. + * @param oneChannel true is treated as single channel, functionality left channel for this pair. + * @param position define the location within the frame of the data, should not bigger than 0x1FFU. + */ +void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); + +/*! + * @brief Disables I2S secondary channel. + * + * @param base I2S base pointer. + * @param channel seondary channel channel number, reference _i2s_secondary_channel. + */ +static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) +{ +#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn + assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); +#endif + + base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; +} +#endif +/*! + * @brief Disables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Disable(I2S_Type *base) +{ + base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENSET = interruptMask; +} + +/*! + * @brief Disables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2S FIFO interrupts. + * + * @param base I2S base pointer. + * + * @return A bitmask composed of #i2s_flags_t enumerators OR'd together + * to indicate the set of enabled interrupts. + */ +static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Invoked from interrupt handler when receive FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..eb5e430eb63f6879872518db038a3e6677a43f2f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.c @@ -0,0 +1,647 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" +#include "fsl_i2s_dma.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" +#endif + +#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) +#define DMA_DESCRIPTORS (2U) + +/*i2sQueue[handle->queueUser].dataSize != 0UL) + { + /* Previously prepared buffers not processed yet, reject request */ + return kStatus_I2S_Busy; + } + + /* Enqueue data */ + privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; + privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + return kStatus_Success; +} + +static uint32_t I2S_GetInstance(I2S_Type *base) +{ + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) + { + if ((uint32_t)base == s_I2sBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0U; +} + +static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) +{ + DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); +} + +static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) +{ + if (handle->state != (uint32_t)kI2S_DmaStateIdle) + { + DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); + } +} + +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + assert(dmaHandle != NULL); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + (void)memset(handle, 0, sizeof(*handle)); + handle->state = (uint32_t)kI2S_DmaStateIdle; + handle->dmaHandle = dmaHandle; + handle->completionCallback = callback; + handle->userData = userData; + + handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); + /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is + * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 + */ + if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) + { + handle->bytesPerFrame = 4U; + } + /* since DMA do not support 24bit transfer width, use 32bit instead */ + if (handle->bytesPerFrame == 3U) + { + handle->bytesPerFrame = 4U; + } + + (void)memset(privateHandle, 0, sizeof(*privateHandle)); + privateHandle->base = base; + privateHandle->handle = handle; + + DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); +} + +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateIdle) + { + handle->state = (uint32_t)kI2S_DmaStateTx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +/*! + * brief Aborts transfer of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + assert(handle != NULL); + assert(handle->dmaHandle != NULL); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + I2S_DisableDMAInterrupts(handle); + + /* Abort operation */ + DMA_AbortTransfer(handle->dmaHandle); + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + /* Wait until all transmitted data get out of FIFO */ + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) + { + } + /* The last piece of valid data can be still being transmitted from I2S at this moment */ + + /* Write additional data to FIFO */ + base->FIFOWR = 0U; + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) + { + } + /* At this moment the additional data are out of FIFO, starting being transmitted. + * This means the preceding valid data has been just transmitted and we can stop I2S. */ + I2S_TxEnableDMA(base, false); + } + else + { + I2S_RxEnableDMA(base, false); + } + + I2S_Disable(base); + + /* Reset state */ + handle->state = (uint32_t)kI2S_DmaStateIdle; + + /* Clear transfer queue */ + (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); + handle->queueDriver = 0U; + handle->queueUser = 0U; + + /* Clear internal state */ + (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); + (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); + privateHandle->enqueuedBytesStart = 0U; + privateHandle->enqueuedBytesEnd = 0U; + privateHandle->dmaDescriptorsUsed = 0U; + privateHandle->descriptor = 0U; + privateHandle->queueDescriptor = 0U; + privateHandle->intA = false; +} + +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); +} + +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateIdle) + { + handle->state = (uint32_t)kI2S_DmaStateRx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +static void I2S_TxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) +{ + assert(transfer != NULL); + + uint16_t transferBytes; + + if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) + { + transferBytes = DMA_MAX_TRANSFER_BYTES; + } + else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) + { + transferBytes = (uint16_t)(transfer->dataSize / 2U); + if ((transferBytes % 4U) != 0U) + { + transferBytes -= (transferBytes % 4U); + } + } + else + { + transferBytes = (uint16_t)transfer->dataSize; + } + + return transferBytes; +} + +static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + uint16_t transferBytes = I2S_GetTransferBytes(transfer); + uint32_t i = 0U; + uint32_t xferConfig = 0U; + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)transfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)transfer->data; + srcInc = 0U; + destInc = 1UL; + } + /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ + privateHandle->dmaDescriptorsUsed = 1U; + privateHandle->intA = false; + + /* submit transfer parameter directly */ + xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); + + DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, + (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); + + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + transfer->dataSize -= transferBytes; + transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); + + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + + /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes + * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten + * when another transfer request comes before the previous finished. + * To make sure the audio data transfer continuously, application must request another transfer by call + * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. + */ + for (i = 0; i < DMA_DESCRIPTORS; i++) + { + /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ + DMA_SetupDescriptor( + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, + ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), + ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); + } + + /* Submit and start initial DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + I2S_TxEnableDMA(base, true); + } + else + { + I2S_RxEnableDMA(base, true); + } + /* enable I2S peripheral request and put the channel into triggered status */ + DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); + DMA_StartTransfer(handle->dmaHandle); + + I2S_Enable(base); + + return kStatus_Success; +} + +static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + volatile i2s_transfer_t *transfer; + uint16_t transferBytes; + uint32_t instance; + i2s_dma_private_handle_t *privateHandle; + dma_descriptor_t *descriptor; + dma_descriptor_t *nextDescriptor; + uint32_t xferConfig = 0U; + bool intA = false; + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + + instance = I2S_GetInstance(base); + privateHandle = &(s_DmaPrivateHandle[instance]); + + while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) + { + transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + intA = privateHandle->intA; + if (transfer->dataSize == 0U) + { + /* Nothing to be added */ + return; + } + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)transfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)transfer->data; + srcInc = 0U; + destInc = 1UL; + } + + /* Determine currently configured descriptor and the other which it will link to */ + descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; + nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + + transferBytes = I2S_GetTransferBytes(transfer); + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + xferConfig = + DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); + + DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); + + /* Advance internal state */ + privateHandle->dmaDescriptorsUsed++; + privateHandle->intA = !privateHandle->intA; + + transfer->dataSize -= transferBytes; + transfer->data += transferBytes; + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + } +} + +/*! + * brief Invoked from DMA interrupt handler. + * + * param handle pointer to DMA handle structure. + * param userData argument for user callback. + * param transferDone if transfer was done. + * param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; + i2s_dma_handle_t *i2sHandle = privateHandle->handle; + I2S_Type *base = privateHandle->base; + uint8_t queueDriverIndex = i2sHandle->queueDriver; + uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; + + if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) + { + return; + } + + if (privateHandle->dmaDescriptorsUsed > 0U) + { + /* Finished descriptor, decrease amount of data to be processed */ + + i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; + i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; + privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; + privateHandle->dmaDescriptorsUsed--; + } + + if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) + { + /* Entire user buffer sent or received - advance to next one */ + i2sHandle->i2sQueue[queueDriverIndex].data = NULL; + i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; + /* Notify user about buffer completion */ + if (i2sHandle->completionCallback != NULL) + { + (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); + } + } + /* check next buffer queue is avaliable or not */ + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + /* All user buffers processed */ + I2S_TransferAbortDMA(base, i2sHandle); + } + else + { + /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ + I2S_AddTransferDMA(base, i2sHandle); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..469e1f8ede17c349e1b1f7971011a03b767740da --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i2s_dma.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2S_DMA_H_ +#define _FSL_I2S_DMA_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +#include "fsl_dma.h" +#include "fsl_i2s.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_dma_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2S DMA driver version 2.2.2. */ +#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*@}*/ + +/*! @brief Members not to be accessed / modified outside of the driver. */ +typedef struct _i2s_dma_handle i2s_dma_handle_t; + +/*! + * @brief Callback function invoked from DMA API on completion. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, + i2s_dma_handle_t *handle, + status_t completionStatus, + void *userData); +/*! @brief i2s dma handle */ +struct _i2s_dma_handle +{ + uint32_t state; /*!< Internal state of I2S DMA transfer */ + uint8_t bytesPerFrame; /*!< bytes per frame */ + i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + dma_handle_t *dmaHandle; /*!< DMA handle */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! @} */ + +/*! + * @name DMA API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts transfer of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Invoked from DMA interrupt handler. + * + * @param handle pointer to DMA handle structure. + * @param userData argument for user callback. + * @param transferDone if transfer was done. + * @param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.c new file mode 100644 index 0000000000000000000000000000000000000000..257db3ed26cc30c89d271bf01bf890ef6f6d7dc2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.c @@ -0,0 +1,2823 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c" +#endif + +#define I3C_BROADCASE_ADDR (0x7EU) + +#define NSEC_PER_SEC (1000000000UL) +#define FSL_I3C_ERROR_RATE_MAX (10U) +#define FSL_I3C_PPBAUD_DIV_MAX ((I3C_MCONFIG_PPBAUD_MASK >> I3C_MCONFIG_PPBAUD_SHIFT) + 1U) +#define FSL_I3C_ODBAUD_DIV_MAX ((I3C_MCONFIG_ODBAUD_MASK >> I3C_MCONFIG_ODBAUD_SHIFT) + 1U) +#define FSL_I3C_I2CBAUD_DIV_MAX (((I3C_MCONFIG_I2CBAUD_MASK >> I3C_MCONFIG_I2CBAUD_SHIFT) + 1U) / 2U) + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterRxReadyFlag /* | kI3C_MasterTxReadyFlag */ | kI3C_MasterArbitrationWonFlag | + kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag | kI3C_SlaveRxReadyFlag | + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*i3c_slave_isr_t)(I3C_Type *base, i3c_slave_handle_t *handle); + +/*! + * @brief Used for conversion between `uint8_t*` and `uint32_t`. + */ +typedef union i3c_puint8_to_u32 +{ + uint8_t *puint8; + uint32_t u32; + const uint8_t *cpuint8; +} i3c_puint8_to_u32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* Not static so it can be used from fsl_i3c_dma.c. */ +static status_t I3C_MasterWaitForTxReady(I3C_Type *base, uint8_t byteCounts); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map I3C instance number to base pointer. */ +static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS; + +/*! @brief Array to map I3C instance number to IRQ number. */ +IRQn_Type const kI3cIrqs[] = I3C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map I3C instance number to clock gate enum. */ +static clock_ip_name_t const kI3cClocks[] = I3C_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) +/*! @brief Pointers to I3C resets for each instance. */ +static const reset_ip_name_t kI3cResets[] = I3C_RSTS; +#endif + +static i3c_device_info_t devList[I3C_MAX_DEVCNT]; /*!< I3C slave record list */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +i3c_master_isr_t s_i3cMasterIsr; + +/*! @brief Pointers to master handles for each instance. */ +void *s_i3cMasterHandle[ARRAY_SIZE(kI3cBases)]; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i3c_slave_isr_t s_i3cSlaveIsr; + +/*! @brief Pointers to slave handles for each instance. */ +i3c_slave_handle_t *s_i3cSlaveHandle[ARRAY_SIZE(kI3cBases)]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I3C peripheral base address. + * @return I3C instance number starting from 0. + */ +uint32_t I3C_GetInstance(I3C_Type *base) +{ + uint32_t instance; + for (instance = 0; instance < ARRAY_SIZE(kI3cBases); ++instance) + { + if (kI3cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(kI3cBases)); + + return instance; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The I3C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Nak + * @retval #kStatus_I3C_WriteAbort + * @retval #kStatus_I3C_Term + * @retval #kStatus_I3C_HdrParityError + * @retval #kStatus_I3C_CrcError + * @retval #kStatus_I3C_ReadFifoError + * @retval #kStatus_I3C_WriteFifoError + * @retval #kStatus_I3C_MsgError + * @retval #kStatus_I3C_InvalidReq + * @retval #kStatus_I3C_Timeout + */ +/* Not static so it can be used from fsl_i3c_edma.c. */ +status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kMasterErrorFlags; + if (0UL != (status)) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0UL != (status & (uint32_t)kI3C_MasterErrorTimeoutFlag)) + { + result = kStatus_I3C_Timeout; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorNackFlag)) + { + result = kStatus_I3C_Nak; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorWriteAbortFlag)) + { + result = kStatus_I3C_WriteAbort; + } +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + else if (0UL != (status & (uint32_t)kI3C_MasterErrorTermFlag)) + { + result = kStatus_I3C_Term; + } +#endif + else if (0UL != (status & (uint32_t)kI3C_MasterErrorParityFlag)) + { + result = kStatus_I3C_HdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorCrcFlag)) + { + result = kStatus_I3C_CrcError; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorMsgFlag)) + { + result = kStatus_I3C_MsgError; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorReadFlag)) + { + result = kStatus_I3C_ReadFifoError; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorWriteFlag)) + { + result = kStatus_I3C_WriteFifoError; + } + else if (0UL != (status & (uint32_t)kI3C_MasterErrorInvalidReqFlag)) + { + result = kStatus_I3C_InvalidReq; + } + else + { + assert(false); + } + + /* Clear the flags. */ + I3C_MasterClearErrorStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + } + + return result; +} + +static status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) +{ + status_t result = kStatus_Success; + uint32_t status, errStatus; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + +#if I3C_RETRY_TIMES + while ((result == kStatus_Success) && (--waitTimes)) +#else + while (result == kStatus_Success) +#endif + { + status = I3C_MasterGetStatusFlags(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + /* Check for error flags. */ + result = I3C_MasterCheckAndClearError(base, errStatus); + /* Check if the control finishes. */ + if (0UL != (status & (uint32_t)kI3C_MasterControlDoneFlag)) + { + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + if (!waitIdle) + { + break; + } + } + /* kI3C_MasterControlDoneFlag only indicates ACK got, need to wait for SDA high. */ + if (waitIdle && I3C_MasterGetState(base) == kI3C_MasterStateIdle) + { + break; + } + } + +#if I3C_RETRY_TIMES + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + + return result; +} + +static status_t I3C_MasterWaitForTxReady(I3C_Type *base, uint8_t byteCounts) +{ + uint32_t errStatus; + status_t result; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + I3C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } +#if I3C_RETRY_TIMES + } while ((txCount < byteCounts) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#else + } while (txCount < byteCounts); +#endif + + return kStatus_Success; +} + +static status_t I3C_MasterWaitForComplete(I3C_Type *base, bool waitIdle) +{ + uint32_t status, errStatus; + status_t result = kStatus_Success; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + status = I3C_MasterGetStatusFlags(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); +#if I3C_RETRY_TIMES + } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && + (result == kStatus_Success) && --waitTimes); +#else + } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && + (result == kStatus_Success)); +#endif + + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); + +#if I3C_RETRY_TIMES + if (waitTimes == 0UL) + { + return kStatus_I3C_Timeout; + } +#endif + + if (waitIdle) + { +#if I3C_RETRY_TIMES + while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) +#else + while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) +#endif + { + } + } + + return result; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The I3C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_I3C_OverrunError + * @retval #kStatus_I3C_UnderrunError + * @retval #kStatus_I3C_UnderrunNak + * @retval #kStatus_I3C_Term + * @retval #kStatus_I3C_InvalidStart + * @retval #kStatus_I3C_SdrParityError + * @retval #kStatus_I3C_HdrParityError + * @retval #kStatus_I3C_CrcError + * @retval #kStatus_I3C_S0S1Error + * @retval #kStatus_I3C_ReadFifoError + * @retval #kStatus_I3C_WriteFifoError + */ +static status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kSlaveErrorFlags; + if (0UL != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverrunFlag)) + { + result = kStatus_I3C_OverrunError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunFlag)) + { + result = kStatus_I3C_UnderrunError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunNakFlag)) + { + result = kStatus_I3C_UnderrunNak; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorTermFlag)) + { + result = kStatus_I3C_Term; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorInvalidStartFlag)) + { + result = kStatus_I3C_InvalidStart; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorSdrParityFlag)) + { + result = kStatus_I3C_SdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrParityFlag)) + { + result = kStatus_I3C_HdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrCRCFlag)) + { + result = kStatus_I3C_CrcError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorS0S1Flag)) + { + result = kStatus_I3C_S0S1Error; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverreadFlag)) + { + result = kStatus_I3C_ReadFifoError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverwriteFlag)) + { + result = kStatus_I3C_WriteFifoError; + } + else + { + assert(false); + } + + /* Clear the flags. */ + I3C_SlaveClearErrorStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } + + return result; +} + +static status_t I3C_SlaveWaitForTxReady(I3C_Type *base) +{ + uint32_t errStatus; + status_t result; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + I3C_SlaveGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + errStatus = I3C_SlaveGetErrorStatusFlags(base); + result = I3C_SlaveCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } +#if I3C_RETRY_TIMES + } while ((txCount == 0UL) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#else + } while (txCount == 0UL); +#endif + + return kStatus_Success; +} + +static status_t I3C_MasterEmitStop(I3C_Type *base, bool waitIdle) +{ + status_t result = kStatus_Success; + + /* Return an error if the bus is not in transaction. */ + if (I3C_MasterGetState(base) != kI3C_MasterStateNormAct) + { + return kStatus_I3C_InvalidReq; + } + + /* Send the STOP signal */ + base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | + I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); + + /* Wait for the stop operation finishes. */ + /* Also check for errors while waiting. */ + result = I3C_MasterWaitForCtrlDone(base, waitIdle); + + return result; +} + +static i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base) +{ + uint32_t ibiValue = (base->MSTATUS & I3C_MSTATUS_IBITYPE_MASK) >> I3C_MSTATUS_IBITYPE_SHIFT; + i3c_ibi_type_t ibiType = kI3C_IbiNormal; + + switch (ibiValue) + { + case 3L: + ibiType = kI3C_IbiHotJoin; + break; + case 2L: + ibiType = kI3C_IbiMasterRequest; + break; + default: + ibiType = kI3C_IbiNormal; + break; + } + + return ibiType; +} + +static inline uint8_t I3C_GetIBIAddress(I3C_Type *base) +{ + return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT); +} +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The I3C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Busy + */ +/* Not static so it can be used from fsl_i3c_edma.c. */ +status_t I3C_CheckForBusyBus(I3C_Type *base) +{ + return (I3C_MasterGetBusIdleState(base) == true) ? kStatus_Success : kStatus_I3C_Busy; +} + +/* brief Provides a default configuration for the I3C peripheral. + * + */ +void I3C_GetDefaultConfig(i3c_config_t *config) +{ + assert(NULL != config); + + (void)memset(config, 0, sizeof(*config)); + + config->enableMaster = kI3C_MasterCapable; + config->disableTimeout = false; + config->hKeep = kI3C_MasterHighKeeperNone; + config->enableOpenDrainStop = true; + config->enableOpenDrainHigh = true; + config->baudRate_Hz.i2cBaud = 400000U; + config->baudRate_Hz.i3cPushPullBaud = 12500000U; + config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; + config->masterDynamicAddress = 0x0AU; /* Default master dynamic address. */ + config->slowClock_Hz = 1000000U; /* Default slow timer clock 1MHz. */ + config->enableSlave = true; + config->vendorID = 0x11BU; + config->enableRandomPart = false; + config->partNumber = 0; + config->dcr = 0; /* Generic device. */ + config->bcr = 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR + Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, + device is offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI + Request Capable, capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ + config->hdrMode = (uint8_t)kI3C_HDRModeDDR; + config->nakAllRequest = false; + config->ignoreS0S1Error = false; + config->offline = false; + config->matchSlaveStartStop = false; + config->maxWriteLength = 256U; + config->maxReadLength = 256U; +} + +/*! + * @brief Initializes the I3C peripheral. + * + */ +void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz) +{ + uint32_t instance = I3C_GetInstance(base); + uint32_t configValue; + uint8_t matchCount; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + + if ((config->masterDynamicAddress != 0U) && (config->enableMaster == kI3C_MasterOn)) + { + base->MDYNADDR &= ~I3C_MDYNADDR_DADDR_MASK; + base->MDYNADDR |= I3C_MDYNADDR_DADDR(config->masterDynamicAddress) | I3C_MDYNADDR_DAVALID_MASK; + } + + base->MCONFIG = I3C_MCONFIG_MSTENA(config->enableMaster) | I3C_MCONFIG_DISTO(config->disableTimeout) | + I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) | + I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh); + + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); + + I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz); + + /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ + matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL); + + configValue = base->SCONFIG; + + configValue &= ~(I3C_SCONFIG_SADDR_MASK | I3C_SCONFIG_BAMATCH_MASK | I3C_SCONFIG_OFFLINE_MASK | + I3C_SCONFIG_IDRAND_MASK | I3C_SCONFIG_DDROK_MASK | I3C_SCONFIG_S0IGNORE_MASK | + I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); + configValue |= I3C_SCONFIG_SADDR(config->staticAddr) | I3C_SCONFIG_BAMATCH(matchCount) | + I3C_SCONFIG_OFFLINE(config->offline) | I3C_SCONFIG_IDRAND(config->enableRandomPart) | + I3C_SCONFIG_DDROK((0U != (config->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | + I3C_SCONFIG_S0IGNORE(config->ignoreS0S1Error) | I3C_SCONFIG_MATCHSS(config->matchSlaveStartStop) | + I3C_SCONFIG_NACK(config->nakAllRequest) | I3C_SCONFIG_SLVENA(config->enableSlave); + + base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; + base->SVENDORID |= I3C_SVENDORID_VID(config->vendorID); + + if (!config->enableRandomPart) + { + base->SIDPARTNO = config->partNumber; + } + + base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); + base->SIDEXT |= I3C_SIDEXT_BCR(config->bcr) | I3C_SIDEXT_DCR(config->dcr); + + base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); + base->SMAXLIMITS |= (I3C_SMAXLIMITS_MAXRD(config->maxReadLength) | I3C_SMAXLIMITS_MAXWR(config->maxWriteLength)); + + base->SCONFIG = configValue; +} + +/*! + * brief Provides a default configuration for the I3C master peripheral. + * + * This function provides the following default configuration for the I3C master peripheral: + * code + * masterConfig->enableMaster = kI3C_MasterOn; + * masterConfig->disableTimeout = false; + * masterConfig->hKeep = kI3C_MasterHighKeeperNone; + * masterConfig->enableOpenDrainStop = true; + * masterConfig->enableOpenDrainHigh = true; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busType = kI3C_TypeI2C; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I3C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. + */ +void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig) +{ + masterConfig->enableMaster = kI3C_MasterOn; + masterConfig->disableTimeout = false; + masterConfig->hKeep = kI3C_MasterHighKeeperNone; + masterConfig->enableOpenDrainStop = true; + masterConfig->enableOpenDrainHigh = true; + masterConfig->baudRate_Hz.i2cBaud = 400000U; + masterConfig->baudRate_Hz.i3cPushPullBaud = 12500000U; + masterConfig->baudRate_Hz.i3cOpenDrainBaud = 2500000U; +} + +/*! + * brief Initializes the I3C master peripheral. + * + * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I3C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of + * defaults that you can override. + * param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t instance = I3C_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + base->MCONFIG = I3C_MCONFIG_MSTENA(masterConfig->enableMaster) | I3C_MCONFIG_DISTO(masterConfig->disableTimeout) | + I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) | + I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh); + + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); + + I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz); +} + +/*! + * @brief Gets the I3C master state. + * + * @param base The I3C peripheral base address. + * @return I3C master state. + */ +i3c_master_state_t I3C_MasterGetState(I3C_Type *base) +{ + uint32_t masterState = (base->MSTATUS & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT; + i3c_master_state_t returnCode; + + switch (masterState) + { + case (uint32_t)kI3C_MasterStateIdle: + returnCode = kI3C_MasterStateIdle; + break; + case (uint32_t)kI3C_MasterStateSlvReq: + returnCode = kI3C_MasterStateSlvReq; + break; + case (uint32_t)kI3C_MasterStateMsgSdr: + returnCode = kI3C_MasterStateMsgSdr; + break; + case (uint32_t)kI3C_MasterStateNormAct: + returnCode = kI3C_MasterStateNormAct; + break; + case (uint32_t)kI3C_MasterStateDdr: + returnCode = kI3C_MasterStateDdr; + break; + case (uint32_t)kI3C_MasterStateDaa: + returnCode = kI3C_MasterStateDaa; + break; + case (uint32_t)kI3C_MasterStateIbiAck: + returnCode = kI3C_MasterStateIbiAck; + break; + case (uint32_t)kI3C_MasterStateIbiRcv: + returnCode = kI3C_MasterStateIbiRcv; + break; + default: + returnCode = kI3C_MasterStateIdle; + break; + } + + return returnCode; +} + +/*! + * brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I3C peripheral base address. + */ +void I3C_MasterDeinit(I3C_Type *base) +{ + uint32_t idx = I3C_GetInstance(base); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[idx]); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + CLOCK_DisableClock(kI3cClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset handle pointer. */ + s_i3cMasterHandle[idx] = NULL; +} + +static uint32_t I3C_CalcErrorRatio(uint32_t curFreq, uint32_t desiredFreq) +{ + if (curFreq > desiredFreq) + { + return (curFreq - desiredFreq) * 100UL / desiredFreq; + } + else + { + return (desiredFreq - curFreq) * 100UL / desiredFreq; + } +} + +/*! + * brief Sets the I3C bus frequency for master transactions. + * + * The I3C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I3C peripheral base address. + * param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. + * param sourceClock_Hz I3C functional clock frequency in Hertz. + */ +void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz) +{ + uint32_t div, freq; + uint32_t divEven, divOdd; + uint32_t ppBaud, odBaud, i2cBaud; + uint32_t errRate0, errRate1; + uint32_t i3cPPBaud_HZ = baudRate_Hz->i3cPushPullBaud; + uint32_t i3cPPBaudMax_HZ = i3cPPBaud_HZ / 10U + i3cPPBaud_HZ; /* max is 1.1*i3cPPBaud_HZ */ + uint32_t i3cODBaud_HZ = baudRate_Hz->i3cOpenDrainBaud; + uint32_t i3cODBaudMax_HZ = i3cODBaud_HZ / 10U + i3cODBaud_HZ; /* max is 1.1*i3cODBaud_HZ */ + uint32_t i2cBaud_HZ = baudRate_Hz->i2cBaud; + uint32_t i3cPPLow_Ns, i3cOdLow_Ns; + bool isODHigh = (0U != (base->MCONFIG & I3C_MCONFIG_ODHPP_MASK)) ? true : false; + + /* Find out the div to generate target freq */ + freq = sourceClock_Hz / 2UL; + /* ppFreq = FCLK / 2 / (PPBAUD + 1)), 0 <= PPBAUD <= 15 */ + /* We need PPBAUD generate 12.5MHz or so. */ + div = freq / i3cPPBaud_HZ; + div = (div == 0UL) ? 1UL : div; + if (freq / div > i3cPPBaudMax_HZ) + { + div++; + } + assert(div <= FSL_I3C_PPBAUD_DIV_MAX); + ppBaud = div - 1UL; + freq /= div; + + i3cPPLow_Ns = (uint32_t)(NSEC_PER_SEC / (2UL * freq)); + + /* We need ODBAUD generate 2.5MHz or so. */ + if (isODHigh) + { + /* odFreq = (2*freq) / (ODBAUD + 2), 1 <= ODBAUD <= 255 */ + div = (2UL * freq) / i3cODBaud_HZ; + div = div < 2UL ? 2UL : div; + if ((2UL * freq / div) > i3cODBaudMax_HZ) + { + div++; + } + odBaud = div - 2UL; + freq = (2UL * freq) / div; + } + else + { + /* odFreq = ppFreq / (ODBAUD + 1), 1 <= ODBAUD <= 255 */ + div = freq / i3cODBaud_HZ; + div = div < 1UL ? 1UL : div; + if (freq / div > i3cODBaudMax_HZ) + { + div++; + } + odBaud = div - 1UL; + freq /= div; + } + + i3cOdLow_Ns = (odBaud + 1UL) * i3cPPLow_Ns; + + /* i2cFreq = odFreq / (I2CBAUD + 1), 0 <= I2CBAUD <= 7 (I2CBAUD need << 1 in register) */ + /* i2cFreq = NSEC_PER_SEC / (I2CBAUD + 1)*i3cOdLow_Ns */ + divEven = (sourceClock_Hz / i2cBaud_HZ) / (2UL * (ppBaud + 1UL) * (odBaud + 1UL)); + divEven = divEven == 0UL ? 1UL : divEven; + errRate0 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / (2UL * divEven * i3cOdLow_Ns)), i2cBaud_HZ); + + divOdd = ((sourceClock_Hz / i2cBaud_HZ) / ((ppBaud + 1UL) * (odBaud + 1UL) - 1UL)) / 2UL; + divOdd = divOdd == 0UL ? 1UL : divOdd; + errRate1 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / ((2UL * divOdd + 1UL) * i3cOdLow_Ns)), i2cBaud_HZ); + + if (errRate0 < FSL_I3C_ERROR_RATE_MAX || errRate1 < FSL_I3C_ERROR_RATE_MAX) + { + /* Use this div */ + i2cBaud = errRate0 < errRate1 ? (divEven - 1UL) * 2UL : (divOdd - 1UL) * 2UL + 1UL; + } + else + { + /* Use div + 1, unless current freq is already lower than desired. */ + i2cBaud = freq / divEven < i2cBaud_HZ ? (divEven - 1UL) * 2UL : divEven * 2UL; + } + + base->MCONFIG = (base->MCONFIG & ~(I3C_MCONFIG_PPBAUD_MASK | I3C_MCONFIG_PPLOW_MASK | I3C_MCONFIG_ODBAUD_MASK | + I3C_MCONFIG_I2CBAUD_MASK)) | + I3C_MCONFIG_PPBAUD(ppBaud) | I3C_MCONFIG_ODBAUD(odBaud) | I3C_MCONFIG_I2CBAUD(i2cBaud); +} + +/*! + * brief Sends a START signal and slave address on the I2C/I3C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) +{ + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + return I3C_MasterRepeatedStart(base, type, address, dir); +} + +/*! + * brief Sends a repeated START signal and slave address on the I2C/I3C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. + * + * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize if dir is #kI3C_Read, this assigns bytes to read. Otherwise set to 0. + * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) +{ + uint32_t mctrlVal; + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Issue start command. */ + mctrlVal = base->MCTRL; + mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | + I3C_MCTRL_RDTERM_MASK); + mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | + I3C_MCTRL_ADDR(address); + + base->MCTRL = mctrlVal; + + return kStatus_Success; +} + +/*! + * brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read + * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer + * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize + * configuration. + * + * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) +{ + uint32_t mctrlVal; + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Issue start command. */ + mctrlVal = base->MCTRL; + mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | + I3C_MCTRL_RDTERM_MASK); + mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | + I3C_MCTRL_ADDR(address) | I3C_MCTRL_RDTERM(rxSize); + + base->MCTRL = mctrlVal; + + return kStatus_Success; +} +/*! + * brief Sends a STOP signal on the I2C/I3C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The I3C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterStop(I3C_Type *base) +{ + return I3C_MasterEmitStop(base, true); +} + +/*! + * brief I3C master emit request. + * + * param base The I3C peripheral base address. + * param masterReq I3C master request of type #i3c_bus_request_t + */ +void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq) +{ + uint32_t mctrlReg = base->MCTRL; + mctrlReg &= ~I3C_MCTRL_REQUEST_MASK; + mctrlReg |= I3C_MCTRL_REQUEST(masterReq); + + base->MCTRL = mctrlReg; +} + +/*! + * brief I3C master register IBI rule. + * + * param base The I3C peripheral base address. + * param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t + */ +void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) +{ + assert(NULL != ibiRule); + uint32_t ruleValue = I3C_MIBIRULES_MSB0_MASK; + + for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) + { + ruleValue |= ((uint32_t)ibiRule->address[count]) << (count * I3C_MIBIRULES_ADDR1_SHIFT); + } + + ruleValue &= ~I3C_MIBIRULES_NOBYTE_MASK; + + if (!ibiRule->ibiHasPayload) + { + ruleValue |= I3C_MIBIRULES_NOBYTE_MASK; + } + + base->MIBIRULES = ruleValue; +} + +/*! + * brief I3C master get IBI rule. + * + * param base The I3C peripheral base address. + * param ibiRule Pointer to store the read out ibi rule description. + */ +void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) +{ + assert(NULL != ibiRule); + + uint32_t ruleValue = base->MIBIRULES; + + for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) + { + ibiRule->address[count] = + (uint8_t)(ruleValue >> (count * I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK; + } + + ibiRule->ibiHasPayload = (0U == (ruleValue & I3C_MIBIRULES_NOBYTE_MASK)); +} + +/*! + * brief Performs a polling receive transfer on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + uint32_t status; + bool completed = false; + uint8_t *buf; + + assert(NULL != rxBuff); + + /* Handle empty read. */ + if (rxSize == 0UL) + { + return kStatus_Success; + } + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + + while ((rxSize != 0UL) || !completed) + { +#if I3C_RETRY_TIMES + if (--waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + /* Check for errors. */ + result = I3C_MasterCheckAndClearError(base, I3C_MasterGetErrorStatusFlags(base)); + if (kStatus_Success != result) + { + return result; + } + + /* Check complete flag */ + if (!completed) + { + status = I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterCompleteFlag; + if (0UL != status) + { + completed = true; + /* Clear complete flag */ + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); + /* Send stop if needed */ + if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { + if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + result = I3C_MasterEmitStop(base, false); + } + if (kStatus_Success != result) + { + return result; + } + } + } + } + + /* Check RX data */ + if ((0UL != rxSize) && (0UL != (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK))) + { + *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + rxSize--; + if (rxSize == 1U) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1U); + } + } + } + + /* Wait idle if stop is sent. */ + if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { +#if I3C_RETRY_TIMES + while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) +#else + while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) +#endif + { + } + } + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C/I3C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I3C_Nak. + * + * param base The I3C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or over run. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + i3c_puint8_to_u32_t buf; + buf.cpuint8 = (const uint8_t *)((const void *)txBuff); + status_t result = kStatus_Success; + bool enableWord = ((flags & (uint32_t)kI3C_TransferWordsFlag) == (uint32_t)kI3C_TransferWordsFlag) ? true : false; + uint8_t byteCounts = enableWord ? 2U : 1U; + + assert(NULL != txBuff); + if (enableWord) + { + assert(txSize % 2UL == 0UL); + } + + /* Send data buffer */ + while (0UL != txSize) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = I3C_MasterWaitForTxReady(base, byteCounts); + if (kStatus_Success != result) + { + return result; + } + + /* Write byte into I3C master data register. */ + if (txSize > byteCounts) + { + if (enableWord) + { + base->MWDATAH = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; + } + else + { + base->MWDATAB = *buf.cpuint8; + } + } + else + { + if (enableWord) + { + base->MWDATAHE = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; + } + else + { + base->MWDATABE = *buf.cpuint8; + } + } + + buf.u32 = buf.u32 + byteCounts; + txSize = txSize - byteCounts; + } + + result = I3C_MasterWaitForComplete(base, false); + if ((result == kStatus_Success) && ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL)) + { + if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + result = I3C_MasterEmitStop(base, true); + } + } + + return result; +} +/*! + * brief Performs a DAA in the i3c bus + * + * param base The I3C peripheral base address. + * param addressList The pointer for address list which is used to do DAA. + * param count The address count in the address list. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count) +{ + status_t result = kStatus_Success; + uint32_t status; + uint32_t errStatus; + size_t rxCount; + uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; + uint8_t rxSize = 0; + uint32_t devCount = 0; + + /* Return an error if the bus is already in use not by us. */ + result = I3C_CheckForBusyBus(base); + if (kStatus_Success != result) + { + return result; + } + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Disable I3C IRQ sources while we configure stuff. */ + uint32_t enabledInts = I3C_MasterGetEnabledInterrupts(base); + I3C_MasterDisableInterrupts(base, enabledInts); + + /* Emit process DAA */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + do + { + do + { + status = I3C_MasterGetStatusFlags(base); + I3C_MasterGetFifoCounts(base, &rxCount, NULL); + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } + + if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U)) + { + rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + } + } while ((status & (uint32_t)kI3C_MasterControlDoneFlag) != (uint32_t)kI3C_MasterControlDoneFlag); + + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + + if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && + (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) + { + rxSize = 0; + if ((devCount > (count - 1UL)) || ((devCount + 1UL) > I3C_MAX_DEVCNT)) + { + return kStatus_I3C_SlaveCountExceed; + } + + devList[devCount].dynamicAddr = *addressList++; + devList[devCount].vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; + devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | + (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); + devList[devCount].bcr = rxBuffer[6]; + devList[devCount].dcr = rxBuffer[7]; + base->MWDATAB = devList[devCount].dynamicAddr; + /* Emit process DAA again. */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + devCount++; + } + } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); + + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Enable I3C IRQ sources while we configure stuff. */ + I3C_MasterEnableInterrupts(base, enabledInts); + + return result; +} + +/*! + * brief Performs a master polling transfer on the I2C/I3C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The I3C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer) +{ + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + i3c_direction_t direction = transfer->direction; + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + if (transfer->busType != kI3C_TypeI3CDdr) + { + direction = (0UL != transfer->subaddressSize) ? kI3C_Write : transfer->direction; + } + + if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); + /* Wait tx fifo empty. */ + size_t txCount = 0xFFUL; + + while (txCount != 0U) + { + I3C_MasterGetFifoCounts(base, NULL, &txCount); + } + + /* Check if device request wins arbitration. */ + if (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterArbitrationWonFlag)) + { + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Enable I3C IRQ sources. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + return kStatus_I3C_IBIWon; + } + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0UL != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8UL * subaddressRemaining)) & 0xFFUL); + + result = I3C_MasterWaitForTxReady(base, 1U); + + if ((0UL == subaddressRemaining) && ((transfer->direction == kI3C_Read) || (0UL == transfer->dataSize)) && + (transfer->busType != kI3C_TypeI3CDdr)) + { + base->MWDATABE = subaddressByte; + result = I3C_MasterWaitForComplete(base, false); + if (kStatus_Success != result) + { + if (result == kStatus_I3C_Nak) + { + (void)I3C_MasterEmitStop(base, true); + } + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Enable I3C IRQ sources. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + return result; + } + } + else + { + base->MWDATAB = subaddressByte; + } + } + /* Need to send repeated start if switching directions to read. */ + if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read)) + { + result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read); + if (kStatus_Success != result) + { + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Enable I3C IRQ sources. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + return result; + } + } + } + + /* Transmit data. */ + if ((transfer->direction == kI3C_Write) && (transfer->dataSize > 0UL)) + { + /* Send Data. */ + result = I3C_MasterSend(base, transfer->data, transfer->dataSize, transfer->flags); + } + /* Receive Data. */ + else if ((transfer->direction == kI3C_Read) && (transfer->dataSize > 0UL)) + { + if (transfer->dataSize == 1U) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1U); + } + result = I3C_MasterReceive(base, transfer->data, transfer->dataSize, transfer->flags); + } + else + { + if ((transfer->flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { + result = I3C_MasterEmitStop(base, true); + } + } + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Enable I3C IRQ sources. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + + return result; +} + +/*! + * brief Creates a new handle for the I3C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The I3C peripheral base address. + * param[out] handle Pointer to the I3C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I3C_MasterTransferCreateHandle(I3C_Type *base, + i3c_master_handle_t *handle, + const i3c_master_transfer_callback_t *callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferHandleIRQ; + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); +} + +static status_t I3C_RunTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t errStatus; + status_t result = kStatus_Success; + i3c_master_transfer_t *xfer; + size_t txCount; + size_t rxCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + bool state_complete = false; + i3c_puint8_to_u32_t dataBuff; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, status); + + i3c_master_state_t masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } + + if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return result; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + /* Get fifo counts and compute room in tx fifo. */ + I3C_MasterGetFifoCounts(base, &rxCount, &txCount); + txCount = txFifoSize - txCount; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + state_complete = true; + break; + + case (uint8_t)kIBIWonState: + if (masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + rxCount--; + break; + } + else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + state_complete = true; + result = kStatus_I3C_IBIWon; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kSendCommandState: + { + I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + /* Make sure there is room in the tx fifo for the next command. */ + if (0UL == txCount--) + { + state_complete = true; + break; + } + if (xfer->subaddressSize > 1U) + { + xfer->subaddressSize--; + base->MWDATAB = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); + } + else if (xfer->subaddressSize == 1U) + { + xfer->subaddressSize--; + + if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize)) + { + base->MWDATABE = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* Next state, receive data begin. */ + handle->state = (uint8_t)kTransferDataState; + base->MWDATAB = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); + } + + if ((xfer->busType != kI3C_TypeI3CDdr) && (xfer->direction == kI3C_Read)) + { + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + /* Eliminate misra 15.7*/ + } + break; + } + + case (uint8_t)kWaitRepeatedStartCompleteState: + /* We stay in this state until the master complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kTransferDataState; + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + + if (handle->remainingBytes < 256U) + { + handle->isReadTerm = true; + result = I3C_MasterRepeatedStartWithRxSize(base, xfer->busType, xfer->slaveAddress, kI3C_Read, + (uint8_t)handle->remainingBytes); + } + else + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read); + } + } + + state_complete = true; + break; + + case (uint8_t)kTransferDataState: + + if (xfer->direction == kI3C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (0UL == txCount--) + { + state_complete = true; + break; + } + + /* Put byte to send in fifo. */ + dataBuff.puint8 = (uint8_t *)xfer->data; + if (xfer->dataSize > 1U) + { + base->MWDATAB = *dataBuff.puint8; + } + else + { + base->MWDATABE = *dataBuff.puint8; + } + dataBuff.u32 = dataBuff.u32 + 1U; + xfer->dataSize--; + xfer->data = (void *)(dataBuff.puint8); + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0UL) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + } + else + { + /* Make sure there is data in the rx fifo. */ + if (0UL == rxCount--) + { + state_complete = true; + break; + } + + /* Read byte from fifo. */ + dataBuff.puint8 = (uint8_t *)xfer->data; + *dataBuff.puint8 = (uint8_t)base->MRDATAB; + dataBuff.u32 = dataBuff.u32 + 1U; + xfer->data = (void *)(dataBuff.puint8); + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0UL) + { + handle->isReadTerm = false; + handle->state = (uint8_t)kWaitForCompletionState; + } + + if (!handle->isReadTerm && (handle->remainingBytes == 1UL)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1UL); + } + } + + break; + + case (uint8_t)kWaitForCompletionState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + state_complete = true; + } + + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0UL == txCount--) + { + state_complete = true; + break; + } + if (xfer->busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + (void)I3C_MasterEmitStop(base, false); + } + } + *isDone = true; + state_complete = true; + break; + + default: + assert(false); + break; + } + } + return result; +} + +static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + if (xfer->busType != kI3C_TypeI3CDdr) + { + direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction; + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransferDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + I3C_MasterTransferHandleIRQ(base, handle); + return result; + } + /* If repeated start is requested, send repeated start. */ + else if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + + if (xfer->subaddressSize > 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + handle->state = (uint8_t)kTransferDataState; + } + + if ((handle->remainingBytes < 256U) && (direction == kI3C_Read)) + { + handle->isReadTerm = true; + base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); + } + + return result; +} + +/*! + * brief Performs a non-blocking transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + handle->remainingBytes = transfer->dataSize; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Generate commands to send. */ + (void)I3C_InitTransferStateMachine(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + + if (transfer->direction == kI3C_Write) + { + I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + } + + return kStatus_Success; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint8_t state; + uint32_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = I3C_MasterGetEnabledInterrupts(base); + I3C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + I3C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I3C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I3C peripheral's IRQ priority. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. + */ +void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferHandleIRQ(I3C_Type *base, i3c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_RunTransferStateMachine(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + (void)I3C_MasterEmitStop(base, false); + } + + /* Disable internal IRQ enables. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Provides a default configuration for the I3C slave peripheral. + * + * This function provides the following default configuration for the I3C slave peripheral: + * code + * slaveConfig->enableslave = true; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the slave driver with I3C_SlaveInit(). + * + * param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. + */ +void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig) +{ + assert(NULL != slaveConfig); + + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->isHotJoin = false; + slaveConfig->vendorID = 0x11BU; + slaveConfig->enableRandomPart = false; + slaveConfig->partNumber = 0; + slaveConfig->dcr = 0; /* Generic device. */ + slaveConfig->bcr = + 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR + Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, device is + offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI Request Capable, + capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ + slaveConfig->hdrMode = (uint8_t)kI3C_HDRModeDDR; + slaveConfig->nakAllRequest = false; + slaveConfig->ignoreS0S1Error = true; + slaveConfig->offline = false; + slaveConfig->matchSlaveStartStop = false; + slaveConfig->maxWriteLength = 256U; + slaveConfig->maxReadLength = 256U; +} + +/*! + * brief Initializes the I3C slave peripheral. + * + * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user + * provided configuration. + * + * param base The I3C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of + * defaults that you can override. + * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + */ +void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz) +{ + assert(NULL != slaveConfig); + assert(0UL != slowClock_Hz); + + uint32_t configValue = base->SCONFIG; + uint8_t matchCount; + uint32_t instance = I3C_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + + /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ + matchCount = (uint8_t)(slowClock_Hz / 1000000UL); + + configValue &= ~(I3C_SCONFIG_SADDR_MASK | I3C_SCONFIG_BAMATCH_MASK | I3C_SCONFIG_OFFLINE_MASK | + I3C_SCONFIG_IDRAND_MASK | I3C_SCONFIG_DDROK_MASK | I3C_SCONFIG_S0IGNORE_MASK | + I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); + configValue |= I3C_SCONFIG_SADDR(slaveConfig->staticAddr) | I3C_SCONFIG_BAMATCH(matchCount) | + I3C_SCONFIG_OFFLINE(slaveConfig->offline) | I3C_SCONFIG_IDRAND(slaveConfig->enableRandomPart) | + I3C_SCONFIG_DDROK((0U != (slaveConfig->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | + I3C_SCONFIG_S0IGNORE(slaveConfig->ignoreS0S1Error) | + I3C_SCONFIG_MATCHSS(slaveConfig->matchSlaveStartStop) | + I3C_SCONFIG_NACK(slaveConfig->nakAllRequest) | I3C_SCONFIG_SLVENA(slaveConfig->enableSlave); + + base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; + base->SVENDORID |= I3C_SVENDORID_VID(slaveConfig->vendorID); + + if (!slaveConfig->enableRandomPart) + { + base->SIDPARTNO = slaveConfig->partNumber; + } + + base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); + base->SIDEXT |= I3C_SIDEXT_BCR(slaveConfig->bcr) | I3C_SIDEXT_DCR(slaveConfig->dcr); + + base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); + base->SMAXLIMITS |= + (I3C_SMAXLIMITS_MAXRD(slaveConfig->maxReadLength) | I3C_SMAXLIMITS_MAXWR(slaveConfig->maxWriteLength)); + + if (slaveConfig->isHotJoin) + { + I3C_SlaveRequestEvent(base, kI3C_SlaveEventHotJoinReq); + } + base->SCONFIG = configValue; +} + +/*! + * brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I3C peripheral base address. + */ +void I3C_SlaveDeinit(I3C_Type *base) +{ + uint32_t idx = I3C_GetInstance(base); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[idx]); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + CLOCK_DisableClock(kI3cClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset handle pointer */ + s_i3cSlaveHandle[idx] = NULL; +} + +/*! + * @brief Gets the I3C slave state. + * + * @param base The I3C peripheral base address. + * @return I3C slave activity state, refer #i3c_slave_activity_state_t. + */ +i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base) +{ + uint8_t activeState = (uint8_t)((base->SSTATUS & I3C_SSTATUS_ACTSTATE_MASK) >> I3C_SSTATUS_ACTSTATE_SHIFT); + i3c_slave_activity_state_t returnCode; + switch (activeState) + { + case (uint8_t)kI3C_SlaveNoLatency: + returnCode = kI3C_SlaveNoLatency; + break; + case (uint8_t)kI3C_SlaveLatency1Ms: + returnCode = kI3C_SlaveLatency1Ms; + break; + case (uint8_t)kI3C_SlaveLatency100Ms: + returnCode = kI3C_SlaveLatency100Ms; + break; + case (uint8_t)kI3C_SlaveLatency10S: + returnCode = kI3C_SlaveLatency10S; + break; + default: + returnCode = kI3C_SlaveNoLatency; + break; + } + + return returnCode; +} + +/*! + * brief I3C slave request event. + * + * param base The I3C peripheral base address. + * param event I3C slave event of type #i3c_slave_event_t + * param data IBI data if In-band interrupt has data, only applicable for event type #kI3C_SlaveEventIBI + */ +void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event) +{ + uint32_t ctrlValue = base->SCTRL; + + ctrlValue &= ~I3C_SCTRL_EVENT_MASK; + ctrlValue |= I3C_SCTRL_EVENT(event); + + base->SCTRL = ctrlValue; +} + +/*! + * brief I3C slave request event. + * + * param base The I3C peripheral base address. + * param data IBI data pointer + * param dataSize IBI data length + */ +void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize) +{ + uint32_t ctrlValue = base->SCTRL; + + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(*data); + + if (dataSize > 1U) + { + handle->ibiData = &data[1]; + handle->ibiDataSize = dataSize - 1U; + } + + base->SCTRL = ctrlValue; +} + +/*! + * brief Performs a polling send transfer on the I3C bus. + * + * param base The I3C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return Error or success status returned by API. + */ +status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize) +{ + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + status_t result = kStatus_Success; + + assert(NULL != txBuff); + + /* Send data buffer */ + while (0UL != txSize--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = I3C_SlaveWaitForTxReady(base); + if (kStatus_Success != result) + { + return result; + } + + /* Write byte into I3C slave data register. */ + if (0UL != txSize) + { + base->SWDATAB = *buf++; + } + else + { + base->SWDATABE = *buf++; + } + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I3C bus. + * + * param base The I3C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return Error or success status returned by API. + */ +status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf; + + assert(NULL != rxBuff); + + /* Handle empty read. */ + if (0UL == rxSize) + { + return kStatus_Success; + } + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0UL != rxSize) + { +#if I3C_RETRY_TIMES + if (--waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + /* Check for errors. */ + result = I3C_SlaveCheckAndClearError(base, I3C_SlaveGetErrorStatusFlags(base)); + if (kStatus_Success != result) + { + return result; + } + + /* Check RX data */ + if (0UL != (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK)) + { + *buf++ = (uint8_t)(base->SRDATAB & I3C_SRDATAB_DATA0_MASK); + rxSize--; + } + } + + return result; +} + +/*! + * brief Creates a new handle for the I3C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The I3C peripheral base address. + * param[out] handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I3C_SlaveTransferCreateHandle(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + (void)EnableIRQ(kI3cIrqs[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. + */ +status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kI3C_SlaveTransmitEvent | (uint32_t)kI3C_SlaveReceiveEvent; + + /* Clear all flags. */ + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + return kStatus_Success; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The I3C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_I3C_Idle + */ +void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle) +{ + assert(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable I3C IRQ sources. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + */ +void I3C_SlaveTransferHandleIRQ(I3C_Type *base, i3c_slave_handle_t *handle) +{ + uint32_t flags; + uint32_t errFlags; + uint32_t pendingInts; + uint32_t enabledInts; + size_t rxCount; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + i3c_slave_transfer_t *xfer; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + pendingInts = I3C_SlaveGetPendingInterrupts(base); + enabledInts = I3C_SlaveGetEnabledInterrupts(base); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, flags); + + if (0UL != (flags & (uint32_t)kI3C_SlaveBusStartFlag)) + { + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK; + xfer->txDataSize = 0; + I3C_SlaveEnableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + pendingInts |= (uint32_t)kI3C_SlaveTxReadyFlag; + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if (handle->ibiData != NULL) + { + size_t count = 0U; + while (count < handle->ibiDataSize) + { + base->SCTRL = (base->SCTRL & ~I3C_SCTRL_IBIDATA_MASK) | I3C_SCTRL_IBIDATA(handle->ibiData[count]) | + I3C_SCTRL_EVENT(1U); + count++; + } + } + + /* Reset IBI data buffer. */ + handle->ibiData = NULL; + + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + if (handle->isBusy == true) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + handle->isBusy = false; + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that I3C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = false; + } + + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + else + { + return; + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + /* Get fifo counts and compute room in tx fifo. */ + I3C_SlaveGetFifoCounts(base, &rxCount, &txCount); + txCount = txFifoSize - txCount; + + /* Handle transmit and receive. */ + if ((0UL != (flags & (uint32_t)kI3C_SlaveTxReadyFlag)) && (0UL != (pendingInts & (uint32_t)kI3C_SlaveTxReadyFlag))) + { + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->txData) || (0UL == xfer->txDataSize)) + { + xfer->event = (uint32_t)kI3C_SlaveTransmitEvent; + if (0UL != (flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) + { + xfer->event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + } + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + if ((NULL == xfer->txData) || (0UL == xfer->txDataSize)) + { + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; + } + + /* Transmit a byte. */ + while ((xfer->txDataSize != 0UL) && (txCount != 0U)) + { + if (xfer->txDataSize > 1UL) + { + base->SWDATAB = *xfer->txData++; + } + else + { + base->SWDATABE = *xfer->txData++; + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + } + --xfer->txDataSize; + ++handle->transferredCount; + txCount--; + } + } + if ((0UL != (flags & (uint32_t)kI3C_SlaveRxReadyFlag)) && (0UL != (enabledInts & (uint32_t)kI3C_SlaveRxReadyFlag))) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == xfer->rxData) || (0UL == xfer->rxDataSize)) + { + xfer->event = (uint32_t)kI3C_SlaveReceiveEvent; + if (0UL != (flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) + { + xfer->event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + } + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + handle->transferredCount = 0; + } + + /* Receive a byte. */ + if ((I3C_SlaveGetEnabledInterrupts(base) & (uint32_t)kI3C_SlaveRxReadyFlag) != 0U) + { + while ((rxCount != 0U) && ((xfer->rxData != NULL) && (xfer->rxDataSize != 0UL))) + { + *xfer->rxData++ = (uint8_t)base->SRDATAB; + --xfer->rxDataSize; + ++handle->transferredCount; + rxCount--; + } + } + } +} + +static void I3C_CommonIRQHandler(I3C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if (((uint32_t)kI3C_MasterOn == (base->MCONFIG & I3C_MCONFIG_MSTENA_MASK)) && (NULL != s_i3cMasterIsr)) + { + /* Master mode. */ + s_i3cMasterIsr(base, s_i3cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((I3C_SCONFIG_SLVENA_MASK == (base->SCONFIG & I3C_SCONFIG_SLVENA_MASK)) && (NULL != s_i3cSlaveIsr)) + { + /* Slave mode. */ + s_i3cSlaveIsr(base, s_i3cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(I3C) +/* Implementation of I3C handler named in startup code. */ +void I3C0_DriverIRQHandler(void); +void I3C0_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C, 0); +} +#endif + +#if defined(I3C0) +/* Implementation of I3C0 handler named in startup code. */ +void I3C0_DriverIRQHandler(void); +void I3C0_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C0, 0); +} +#endif + +#if defined(I3C1) +/* Implementation of I3C1 handler named in startup code. */ +void I3C1_DriverIRQHandler(void); +void I3C1_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C1, 1); +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.h new file mode 100644 index 0000000000000000000000000000000000000000..560a02261d75bf30af8f187803d6633cbcacdcc9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_i3c.h @@ -0,0 +1,1752 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I3C_H_ +#define _FSL_I3C_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i3c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I3C driver version */ +#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 5, 2)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef I3C_RETRY_TIMES +#define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define I3C_MAX_DEVCNT 10U + +#ifndef I3C_IBI_BUFF_SIZE +#define I3C_IBI_BUFF_SIZE 10U +#endif + +/*! @brief I3C status return codes. */ +enum +{ + kStatus_I3C_Busy = MAKE_STATUS(kStatusGroup_I3C, 0), /*!< The master is already performing a transfer. */ + kStatus_I3C_Idle = MAKE_STATUS(kStatusGroup_I3C, 1), /*!< The slave driver is idle. */ + kStatus_I3C_Nak = MAKE_STATUS(kStatusGroup_I3C, 2), /*!< The slave device sent a NAK in response to an address. */ + kStatus_I3C_WriteAbort = + MAKE_STATUS(kStatusGroup_I3C, 3), /*!< The slave device sent a NAK in response to a write. */ + kStatus_I3C_Term = MAKE_STATUS(kStatusGroup_I3C, 4), /*!< The master terminates slave read. */ + kStatus_I3C_HdrParityError = MAKE_STATUS(kStatusGroup_I3C, 5), /*!< Parity error from DDR read. */ + kStatus_I3C_CrcError = MAKE_STATUS(kStatusGroup_I3C, 6), /*!< CRC error from DDR read. */ + kStatus_I3C_ReadFifoError = MAKE_STATUS(kStatusGroup_I3C, 7), /*!< Read from M/SRDATAB register when FIFO empty. */ + kStatus_I3C_WriteFifoError = MAKE_STATUS(kStatusGroup_I3C, 8), /*!< Write to M/SWDATAB register when FIFO full. */ + kStatus_I3C_MsgError = + MAKE_STATUS(kStatusGroup_I3C, 9), /*!< Message SDR/DDR mismatch or read/write message in wrong state */ + kStatus_I3C_InvalidReq = MAKE_STATUS(kStatusGroup_I3C, 10), /*!< Invalid use of request. */ + kStatus_I3C_Timeout = MAKE_STATUS(kStatusGroup_I3C, 11), /*!< The module has stalled too long in a frame. */ + kStatus_I3C_SlaveCountExceed = + MAKE_STATUS(kStatusGroup_I3C, 12), /*!< The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */ + kStatus_I3C_IBIWon = MAKE_STATUS( + kStatusGroup_I3C, 13), /*!< The I3C slave event IBI or MR or HJ won the arbitration on a header address. */ + kStatus_I3C_OverrunError = MAKE_STATUS(kStatusGroup_I3C, 14), /*!< Slave internal from-bus buffer/FIFO overrun. */ + kStatus_I3C_UnderrunError = MAKE_STATUS(kStatusGroup_I3C, 15), /*!< Slave internal to-bus buffer/FIFO underrun */ + kStatus_I3C_UnderrunNak = + MAKE_STATUS(kStatusGroup_I3C, 16), /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */ + kStatus_I3C_InvalidStart = MAKE_STATUS(kStatusGroup_I3C, 17), /*!< Slave invalid start flag */ + kStatus_I3C_SdrParityError = MAKE_STATUS(kStatusGroup_I3C, 18), /*!< SDR parity error */ + kStatus_I3C_S0S1Error = MAKE_STATUS(kStatusGroup_I3C, 19), /*!< S0 or S1 error */ +}; + +/*! @brief I3C HDR modes. */ +typedef enum _i3c_hdr_mode +{ + kI3C_HDRModeNone = 0x00U, /* Do not support HDR mode. */ + kI3C_HDRModeDDR = 0x01U, /* HDR-DDR Mode. */ + kI3C_HDRModeTSP = 0x02U, /* HDR-TSP Mode. */ + kI3C_HDRModeTSL = 0x04U, /* HDR-TSL Mode. */ +} i3c_hdr_mode_t; + +/*! @brief I3C device information. */ +typedef struct _i3c_device_info +{ + uint8_t dynamicAddr; /*!< Device dynamic address. */ + uint8_t staticAddr; /*!< Static address. */ + uint8_t dcr; /*!< Device characteristics register information. */ + uint8_t bcr; /*!< Bus characteristics register information. */ + uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */ + uint32_t partNumber; /*!< Device part number info */ + uint16_t maxReadLength; /*!< Maximum read length. */ + uint16_t maxWriteLength; /*!< Maximum write length. */ + uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in i3c_hdr_mode. */ +} i3c_device_info_t; + +/*! @} */ + +/*! + * @addtogroup i3c_master_driver + * @{ + */ + +/*! + * @brief I3C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kI3C_MasterSlaveStartFlag + * - #kI3C_MasterControlDoneFlag + * - #kI3C_MasterCompleteFlag + * - #kI3C_MasterArbitrationWonFlag + * - #kI3C_MasterSlave2MasterFlag + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_master_flags +{ + kI3C_MasterBetweenFlag = I3C_MSTATUS_BETWEEN_MASK, /*!< Between messages/DAAs flag */ + kI3C_MasterNackDetectFlag = I3C_MSTATUS_NACKED_MASK, /*!< NACK detected flag */ + kI3C_MasterSlaveStartFlag = I3C_MSTATUS_SLVSTART_MASK, /*!< Slave request start flag */ + kI3C_MasterControlDoneFlag = I3C_MSTATUS_MCTRLDONE_MASK, /*!< Master request complete flag */ + kI3C_MasterCompleteFlag = I3C_MSTATUS_COMPLETE_MASK, /*!< Transfer complete flag */ + kI3C_MasterRxReadyFlag = I3C_MSTATUS_RXPEND_MASK, /*!< Rx data ready in Rx buffer flag */ + kI3C_MasterTxReadyFlag = I3C_MSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */ + kI3C_MasterArbitrationWonFlag = I3C_MSTATUS_IBIWON_MASK, /*!< Header address won arbitration flag */ + kI3C_MasterErrorFlag = I3C_MSTATUS_ERRWARN_MASK, /*!< Error occurred flag */ + kI3C_MasterSlave2MasterFlag = I3C_MSTATUS_NOWMASTER_MASK, /*!< Switch from slave to master flag */ + kI3C_MasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, +}; + +/*! + * @brief I3C master error flags to indicate the causes. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_master_error_flags +{ + kI3C_MasterErrorNackFlag = I3C_MERRWARN_NACK_MASK, /*!< Slave NACKed the last address */ + kI3C_MasterErrorWriteAbortFlag = I3C_MERRWARN_WRABT_MASK, /*!< Slave NACKed the write data */ +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag = I3C_MERRWARN_TERM_MASK, /*!< Master terminates slave read */ +#endif + kI3C_MasterErrorParityFlag = I3C_MERRWARN_HPAR_MASK, /*!< Parity error from DDR read */ + kI3C_MasterErrorCrcFlag = I3C_MERRWARN_HCRC_MASK, /*!< CRC error from DDR read */ + kI3C_MasterErrorReadFlag = I3C_MERRWARN_OREAD_MASK, /*!< Read from MRDATAB register when FIFO empty */ + kI3C_MasterErrorWriteFlag = I3C_MERRWARN_OWRITE_MASK, /*!< Write to MWDATAB register when FIFO full */ + kI3C_MasterErrorMsgFlag = I3C_MERRWARN_MSGERR_MASK, /*!< Message SDR/DDR mismatch or + read/write message in wrong state */ + kI3C_MasterErrorInvalidReqFlag = I3C_MERRWARN_INVREQ_MASK, /*!< Invalid use of request */ + kI3C_MasterErrorTimeoutFlag = I3C_MERRWARN_TIMEOUT_MASK, /*!< The module has stalled too long in a frame */ + kI3C_MasterAllErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, /*!< All error flags */ +}; + +/*! @brief I3C working master state. */ +typedef enum _i3c_master_state +{ + kI3C_MasterStateIdle = 0U, /*!< Bus stopped. */ + kI3C_MasterStateSlvReq = 1U, /*!< Bus stopped but slave holding SDA low. */ + kI3C_MasterStateMsgSdr = 2U, /*!< In SDR Message mode from using MWMSG_SDR. */ + kI3C_MasterStateNormAct = 3U, /*!< In normal active SDR mode. */ + kI3C_MasterStateDdr = 4U, /*!< In DDR Message mode. */ + kI3C_MasterStateDaa = 5U, /*!< In ENTDAA mode. */ + kI3C_MasterStateIbiAck = 6U, /*!< Waiting on IBI ACK/NACK decision. */ + kI3C_MasterStateIbiRcv = 7U, /*!< receiving IBI. */ +} i3c_master_state_t; + +/*! @brief I3C master enable configuration. */ +typedef enum _i3c_master_enable +{ + kI3C_MasterOff = 0U, /*!< Master off. */ + kI3C_MasterOn = 1U, /*!< Master on. */ + kI3C_MasterCapable = 2U /*!< Master capable. */ +} i3c_master_enable_t; + +/*! @brief I3C high keeper configuration. */ +typedef enum _i3c_master_hkeep +{ + kI3C_MasterHighKeeperNone = 0U, /*!< Use PUR to hold SCL high. */ + kI3C_MasterHighKeeperWiredIn = 1U, /*!< Use pin_HK controls. */ + kI3C_MasterPassiveSDA = 2U, /*!< Hi-Z for Bus Free and hold SDA. */ + kI3C_MasterPassiveSDASCL = 3U /*!< Hi-Z both for Bus Free, and can Hi-Z SDA for hold. */ +} i3c_master_hkeep_t; + +/*! @brief Emits the requested operation when doing in pieces vs. by message. */ +typedef enum _i3c_bus_request +{ + kI3C_RequestNone = 0U, /*!< No request. */ + kI3C_RequestEmitStartAddr = 1U, /*!< Request to emit start and address on bus. */ + kI3C_RequestEmitStop = 2U, /*!< Request to emit stop on bus. */ + kI3C_RequestIbiAckNack = 3U, /*!< Manual IBI ACK or NACK. */ + kI3C_RequestProcessDAA = 4U, /*!< Process DAA. */ + kI3C_RequestForceExit = 6U, /*!< Request to force exit. */ + kI3C_RequestAutoIbi = 7U, /*!< Hold in stopped state, but Auto-emit START,7E. */ +} i3c_bus_request_t; + +/*! @brief Bus type with EmitStartAddr. */ +typedef enum _i3c_bus_type +{ + kI3C_TypeI3CSdr = 0U, /*!< SDR mode of I3C. */ + kI3C_TypeI2C = 1U, /*!< Standard i2c protocol. */ + kI3C_TypeI3CDdr = 2U, /*!< HDR-DDR mode of I3C. */ +} i3c_bus_type_t; + +/*! @brief IBI response. */ +typedef enum _i3c_ibi_response +{ + kI3C_IbiRespAck = 0U, /*!< ACK with no mandatory byte. */ + kI3C_IbiRespNack = 1U, /*!< NACK. */ + kI3C_IbiRespAckMandatory = 2U, /*!< ACK with mandatory byte. */ + kI3C_IbiRespManual = 3U, /*!< Reserved. */ +} i3c_ibi_response_t; + +/*! @brief IBI type. */ +typedef enum _i3c_ibi_type +{ + kI3C_IbiNormal = 0U, /*!< In-band interrupt. */ + kI3C_IbiHotJoin = 1U, /*!< slave hot join. */ + kI3C_IbiMasterRequest = 2U, /*!< slave master ship request. */ +} i3c_ibi_type_t; + +/*! @brief IBI state. */ +typedef enum _i3c_ibi_state +{ + kI3C_IbiReady = 0U, /*!< In-band interrupt ready state, ready for user to handle. */ + kI3C_IbiDataBuffNeed = 1U, /*!< In-band interrupt need data buffer for data receive. */ + kI3C_IbiAckNackPending = 2U, /*!< In-band interrupt Ack/Nack pending for decision. */ +} i3c_ibi_state_t; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i3c_direction +{ + kI3C_Write = 0U, /*!< Master transmit. */ + kI3C_Read = 1U /*!< Master receive. */ +} i3c_direction_t; + +/*! @brief Watermark of TX int/dma trigger level. */ +typedef enum _i3c_tx_trigger_level +{ + kI3C_TxTriggerOnEmpty = 0U, /*!< Trigger on empty. */ + kI3C_TxTriggerUntilOneQuarterOrLess = 1U, /*!< Trigger on 1/4 full or less. */ + kI3C_TxTriggerUntilOneHalfOrLess = 2U, /*!< Trigger on 1/2 full or less. */ + kI3C_TxTriggerUntilOneLessThanFull = 3U, /*!< Trigger on 1 less than full or less. */ +} i3c_tx_trigger_level_t; + +/*! @brief Watermark of RX int/dma trigger level. */ +typedef enum _i3c_rx_trigger_level +{ + kI3C_RxTriggerOnNotEmpty = 0U, /*!< Trigger on not empty. */ + kI3C_RxTriggerUntilOneQuarterOrMore = 1U, /*!< Trigger on 1/4 full or more. */ + kI3C_RxTriggerUntilOneHalfOrMore = 2U, /*!< Trigger on 1/2 full or more. */ + kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */ +} i3c_rx_trigger_level_t; + +/*! @brief Structure with setting master IBI rules and slave registry. */ +typedef struct _i3c_register_ibi_addr +{ + uint8_t address[5]; /*!< Address array for registry. */ + bool ibiHasPayload; /*!< Whether the address array has mandatory IBI byte. */ +} i3c_register_ibi_addr_t; + +/*! @brief Structure with I3C baudrate settings. */ +typedef struct _i3c_baudrate +{ + uint32_t i2cBaud; /*!< Desired I2C baud rate in Hertz. */ + uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */ + uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */ +} i3c_baudrate_hz_t; + +/*! + * @brief Structure with settings to initialize the I3C master module. + * + * This structure holds configuration settings for the I3C peripheral. To initialize this + * structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i3c_master_config +{ + i3c_master_enable_t enableMaster; /*!< Enable master mode. */ + bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */ + i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */ + bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */ + bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */ + i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */ +} i3c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_transfer i3c_master_transfer_t; +typedef struct _i3c_master_handle i3c_master_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_transfer_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_handle_t *handle, + status_t completionStatus, + void *userData); /*!< Transfer complete callback */ +} i3c_master_transfer_callback_t; +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i3c_master_transfer::flags field. + */ +enum _i3c_master_transfer_flags +{ + kI3C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI3C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ + kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. + */ +struct _i3c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available + options. Set to 0 or #kI3C_TransferDefaultFlag for normal transfers. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ + i3c_direction_t direction; /*!< Either #kI3C_Read or #kI3C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ + i3c_bus_type_t busType; /*!< bus type. */ + i3c_ibi_response_t ibiResponse; /*!< ibi response during transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + bool isReadTerm; /*!< Is readterm configured. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ + i3c_master_transfer_callback_t callback; /*!< Callback functions pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*i3c_master_isr_t)(I3C_Type *base, i3c_master_handle_t *handle); + +/*! @} */ + +/*! + * @addtogroup i3c_slave_driver + * @{ + */ + +/*! + * @brief I3C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * + * Only below flags can be enabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_slave_flags +{ + kI3C_SlaveNotStopFlag = I3C_SSTATUS_STNOTSTOP_MASK, /*!< Slave status not stop flag */ + kI3C_SlaveMessageFlag = I3C_SSTATUS_STMSG_MASK, /*!< Slave status message, indicating slave is + listening to the bus traffic or responding */ + kI3C_SlaveRequiredReadFlag = I3C_SSTATUS_STREQRD_MASK, /*!< Slave status required, either is master doing SDR + read from slave, or is IBI pushing out. */ + kI3C_SlaveRequiredWriteFlag = I3C_SSTATUS_STREQWR_MASK, /*!< Slave status request write, master is doing SDR + write to slave, except slave in ENTDAA mode */ + kI3C_SlaveBusDAAFlag = I3C_SSTATUS_STDAA_MASK, /*!< I3C bus is in ENTDAA mode */ + kI3C_SlaveBusHDRModeFlag = I3C_SSTATUS_STHDR_MASK, /*!< I3C bus is in HDR mode */ + kI3C_SlaveBusStartFlag = I3C_SSTATUS_START_MASK, /*!< Start/Re-start event is seen since the bus was last cleared */ + kI3C_SlaveMatchedFlag = I3C_SSTATUS_MATCHED_MASK, /*!< Slave address(dynamic/static) matched since last cleared */ + kI3C_SlaveBusStopFlag = I3C_SSTATUS_STOP_MASK, /*!enableMaster = kI3C_MasterCapable; + * config->disableTimeout = false; + * config->hKeep = kI3C_MasterHighKeeperNone; + * config->enableOpenDrainStop = true; + * config->enableOpenDrainHigh = true; + * config->baudRate_Hz.i2cBaud = 400000U; + * config->baudRate_Hz.i3cPushPullBaud = 12500000U; + * config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; + * config->masterDynamicAddress = 0x0AU; + * config->slowClock_Hz = 1000000U; + * config->enableSlave = true; + * config->vendorID = 0x11BU; + * config->enableRandomPart = false; + * config->partNumber = 0; + * config->dcr = 0; + * config->bcr = 0; + * config->hdrMode = (uint8_t)kI3C_HDRModeDDR; + * config->nakAllRequest = false; + * config->ignoreS0S1Error = false; + * config->offline = false; + * config->matchSlaveStartStop = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the common I3C driver with I3C_Init(). + * + * @param[out] config User provided configuration structure for default values. Refer to #i3c_config_t. + */ +void I3C_GetDefaultConfig(i3c_config_t *config); + +/*! + * @brief Initializes the I3C peripheral. + * This function enables the peripheral clock and initializes the I3C peripheral as described by the user + * provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C + * module could work as pure master, pure slave or secondary master, etc. + * A software reset is performed prior to configuration. + * + * @param base The I3C peripheral base address. + * @param config User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of + * defaults that you can override. + * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz); + +/*! @} */ + +/*! + * @addtogroup i3c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I3C master peripheral. + * + * This function provides the following default configuration for the I3C master peripheral: + * @code + * masterConfig->enableMaster = kI3C_MasterOn; + * masterConfig->disableTimeout = false; + * masterConfig->hKeep = kI3C_MasterHighKeeperNone; + * masterConfig->enableOpenDrainStop = true; + * masterConfig->enableOpenDrainHigh = true; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busType = kI3C_TypeI2C; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I3C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. + */ +void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I3C master peripheral. + * + * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I3C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of + * defaults that you can override. + * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I3C peripheral base address. + */ +void I3C_MasterDeinit(I3C_Type *base); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_CheckForBusyBus(I3C_Type *base); + +/*! + * @brief Set I3C module master mode. + * + * @param base The I3C peripheral base address. + * @param enable Enable master mode. + */ +static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable) +{ + base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the I3C master status flags. + * + * A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_master_flags + */ +static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base) +{ + return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK); +} + +/*! + * @brief Clears the I3C master status flag state. + * + * The following status register flags can be cleared: + * - #kI3C_MasterSlaveStartFlag + * - #kI3C_MasterControlDoneFlag + * - #kI3C_MasterCompleteFlag + * - #kI3C_MasterArbitrationWonFlag + * - #kI3C_MasterSlave2MasterFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i3c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_MasterGetStatusFlags(). + * @see _i3c_master_flags. + */ +static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->MSTATUS = statusMask; +} + +/*! + * @brief Gets the I3C master error status flags. + * + * A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the error status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_master_error_flags + */ +static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base) +{ + return base->MERRWARN; +} + +/*! + * @brief Clears the I3C master error status flag state. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of + * #_i3c_master_error_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_MasterGetStatusFlags(). + * @see _i3c_master_error_flags. + */ +static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->MERRWARN = statusMask; + while ((base->MERRWARN & statusMask) != 0U) + { + } +} + +/*! + * @brief Gets the I3C master state. + * + * @param base The I3C peripheral base address. + * @return I3C master state. + */ +i3c_master_state_t I3C_MasterGetState(I3C_Type *base); + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I3C master interrupt requests. + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i3c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->MINTSET |= interruptMask; +} + +/*! + * @brief Disables the I3C master interrupt requests. + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i3c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->MINTCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I3C master interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base) +{ + return base->MINTSET; +} + +/*! + * @brief Returns the set of pending I3C master interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the + * set of pending interrupts. + */ +static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base) +{ + return base->MINTMASKED; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables I3C master DMA requests. + * + * @param base The I3C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + * @param width DMA read/write unit in bytes. + */ +static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) +{ + assert(width <= 2U); + base->MDMACTRL = + I3C_MDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width); +} + +/*! + * @brief Gets I3C master transmit data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Master Transmit Data Register address. + */ +static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB); +} + +/*! + * @brief Gets I3C master receive data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Master Receive Data Register address. + */ +static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB); +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for I3C master FIFOs. + * + * @param base The I3C peripheral base address. + * @param txLvl Transmit FIFO watermark level. The #kI3C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO reaches @a txLvl. + * @param rxLvl Receive FIFO watermark level. The #kI3C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO reaches @a rxLvl. + * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. + * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. + */ +static inline void I3C_MasterSetWatermarks( + I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) +{ + base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(rxLvl) | + (flushTx ? I3C_MDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_MDATACTRL_FLUSHFB_MASK : 0U); +} + +/*! + * @brief Gets the current number of bytes in the I3C master FIFOs. + * + * @param base The I3C peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I3C bus frequency for master transactions. + * + * The I3C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I3C peripheral base address. + * @param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. + * @param sourceClock_Hz I3C functional clock frequency in Hertz. + */ +void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I3C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I3C_MasterGetBusIdleState(I3C_Type *base) +{ + return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false); +} + +/*! + * @brief Sends a START signal and slave address on the I2C/I3C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read + * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer + * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize + * configuration. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); + +/*! + * @brief Performs a polling send transfer on the I2C/I3C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I3C_Nak. + * + * @param base The I3C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * @retval #kStatus_Success Data was sent successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. + * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C/I3C bus. + * + * @param base The I3C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Term The master terminates slave read. + * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. + * @retval #kStatus_I3C_CrcError CRC error from DDR read. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Sends a STOP signal on the I2C/I3C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The I3C peripheral base address. + * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterStop(I3C_Type *base); + +/*! + * @brief I3C master emit request. + * + * @param base The I3C peripheral base address. + * @param masterReq I3C master request of type #i3c_bus_request_t + */ +void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq); + +/*! + * @brief I3C master emit request. + * + * @param base The I3C peripheral base address. + * @param ibiResponse I3C master emit IBI response of type #i3c_ibi_response_t + */ +static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse) +{ + uint32_t ctrlVal = base->MCTRL; + ctrlVal &= ~(I3C_MCTRL_IBIRESP_MASK | I3C_MCTRL_REQUEST_MASK); + ctrlVal |= I3C_MCTRL_IBIRESP((uint32_t)ibiResponse) | I3C_MCTRL_REQUEST(kI3C_RequestIbiAckNack); + base->MCTRL = ctrlVal; +} + +/*! + * @brief I3C master register IBI rule. + * + * @param base The I3C peripheral base address. + * @param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t + */ +void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); + +/*! + * @brief I3C master get IBI rule. + * + * @param base The I3C peripheral base address. + * @param ibiRule Pointer to store the read out ibi rule description. + */ +void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); + +/*! + * @brief Performs a DAA in the i3c bus + * + * @param base The I3C peripheral base address. + * @param addressList The pointer for address list which is used to do DAA. + * @param count The address count in the address list. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count); + +/*! + * @brief Performs a master polling transfer on the I2C/I3C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The I3C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_IBIWon The I3C slave event IBI or MR or HJ won the arbitration on a header address. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. + * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. + * @retval #kStatus_I3C_Term The master terminates slave read. + * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. + * @retval #kStatus_I3C_CrcError CRC error from DDR read. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. + * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I3C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The I3C peripheral base address. + * @param[out] handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I3C_MasterTransferCreateHandle(I3C_Type *base, + i3c_master_handle_t *handle, + const i3c_master_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C/I3C bus. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I3C peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. + */ +void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferHandleIRQ(I3C_Type *base, i3c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I3C slave peripheral. + * + * This function provides the following default configuration for the I3C slave peripheral: + * @code + * slaveConfig->enableslave = true; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the slave driver with I3C_SlaveInit(). + * + * @param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. + */ +void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I3C slave peripheral. + * + * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user + * provided configuration. + * + * @param base The I3C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of + * defaults that you can override. + * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + */ +void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz); + +/*! + * @brief Deinitializes the I3C slave peripheral. + * + * This function disables the I3C slave peripheral and gates the clock. + * + * @param base The I3C peripheral base address. + */ +void I3C_SlaveDeinit(I3C_Type *base); + +/*! + * @brief Enable/Disable Slave. + * + * @param base The I3C peripheral base address. + * @param isEnable Enable or disable. + */ +static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable) +{ + base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the I3C slave status flags. + * + * A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_slave_flags + */ +static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base) +{ + return base->SSTATUS & ~(I3C_SSTATUS_EVDET_MASK | I3C_SSTATUS_ACTSTATE_MASK | I3C_SSTATUS_TIMECTRL_MASK); +} + +/*! + * @brief Clears the I3C slave status flag state. + * + * The following status register flags can be cleared: + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i3c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_SlaveGetStatusFlags(). + * @see _i3c_slave_flags. + */ +static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->SSTATUS = statusMask; +} + +/*! + * @brief Gets the I3C slave error status flags. + * + * A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the error status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_slave_error_flags + */ +static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base) +{ + return base->SERRWARN; +} + +/*! + * @brief Clears the I3C slave error status flag state. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of + * #_i3c_slave_error_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_SlaveGetErrorStatusFlags(). + * @see _i3c_slave_error_flags. + */ +static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->SERRWARN = statusMask; +} + +/*! + * @brief Gets the I3C slave state. + * + * @param base The I3C peripheral base address. + * @return I3C slave activity state, refer #i3c_slave_activity_state_t. + */ +i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base); +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I3C slave interrupt requests. + * + * Only below flags can be enabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i3c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->SINTSET |= interruptMask; +} + +/*! + * @brief Disables the I3C slave interrupt requests. + * + * Only below flags can be disabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i3c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->SINTCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I3C slave interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base) +{ + return base->SINTSET; +} + +/*! + * @brief Returns the set of pending I3C slave interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the + * set of pending interrupts. + */ +static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base) +{ + return base->SINTMASKED; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables I3C slave DMA requests. + * + * @param base The I3C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + * @param width DMA read/write unit in bytes. + */ +static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) +{ + assert(width <= 2U); + base->SDMACTRL = + I3C_SDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_SDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_SDMACTRL_DMAWIDTH(width); +} + +/*! + * @brief Gets I3C slave transmit data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Slave Transmit Data Register address. + */ +static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->SWDATAH : &base->SWDATAB); +} + +/*! + * @brief Gets I3C slave receive data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Slave Receive Data Register address. + */ +static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB); +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for I3C slave FIFOs. + * + * @param base The I3C peripheral base address. + * @param txLvl Transmit FIFO watermark level. The #kI3C_SlaveTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO reaches @a txLvl. + * @param rxLvl Receive FIFO watermark level. The #kI3C_SlaveRxReadyFlag flag is set whenever + * the number of words in the receive FIFO reaches @a rxLvl. + * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. + * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. + */ +static inline void I3C_SlaveSetWatermarks( + I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) +{ + base->SDATACTRL = I3C_SDATACTRL_UNLOCK_MASK | I3C_SDATACTRL_TXTRIG(txLvl) | I3C_SDATACTRL_RXTRIG(rxLvl) | + (flushTx ? I3C_SDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_SDATACTRL_FLUSHFB_MASK : 0U); +} + +/*! + * @brief Gets the current number of bytes in the I3C slave FIFOs. + * + * @param base The I3C peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->SDATACTRL & I3C_SDATACTRL_TXCOUNT_MASK) >> I3C_SDATACTRL_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK) >> I3C_SDATACTRL_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief I3C slave request event. + * + * @param base The I3C peripheral base address. + * @param event I3C slave event of type #i3c_slave_event_t + */ +void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event); + +/*! + * @brief Performs a polling send transfer on the I3C bus. + * + * @param base The I3C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I3C bus. + * + * @param base The I3C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I3C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The I3C peripheral base address. + * @param[out] handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I3C_SlaveTransferCreateHandle(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. + */ +status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The I3C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress + */ +status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Idle + */ +void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + */ +void I3C_SlaveTransferHandleIRQ(I3C_Type *base, i3c_slave_handle_t *handle); + +/*! + * @brief I3C slave request IBI event with payload. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @param data Pointer to IBI data to be sent in the request. + * @param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize); +/*@}*/ +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I3C_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.c new file mode 100644 index 0000000000000000000000000000000000000000..5ef935985fbf543b08a606b809eaf4f90600a987 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_EnableClock(kCLOCK_Sct); + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param index Destination peripheral to attach the signal to. + * param connection Selects connection. + * + * retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; + uint32_t bit_offset; + +#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX + uint32_t chmux_offset; + uint32_t chmux_value; + + /* Only enable need to update channel mux */ + if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) + { + chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); + chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); + *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; + } + ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; +#endif + /* extract enable register to be used */ + ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; + /* extract enable bit offset */ + bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_DisableClock(kCLOCK_Sct); + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.h new file mode 100644 index 0000000000000000000000000000000000000000..ddb9e26c55f0a91dc1a95e874ace58815d25eb93 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_H_ +#define _FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index Destination peripheral to attach the signal to. + * @param connection Selects connection. + * + * @retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux_connections.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux_connections.h new file mode 100644 index 0000000000000000000000000000000000000000..4b6bcc93587f157e8c27c54d62f48ab5eeefe76f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_inputmux_connections.h @@ -0,0 +1,2686 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define SCT0_INMUX0 0x00U +#define TIMER0CAPTSEL0 0x20U +#define TIMER0TRIGIN 0x30U +#define TIMER1CAPTSEL0 0x40U +#define TIMER1TRIGIN 0x50U +#define TIMER2CAPTSEL0 0x60U +#define TIMER2TRIGIN 0x70U +#define PINTSEL_PMUX_ID 0xC0U +#define PINTSEL0 0xC0U +#define DMA0_ITRIG_INMUX0 0xE0U +#define DMA0_OTRIG_INMUX0 0x160U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TARGET_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER3TRIGIN 0x1B0U +#define TIMER4CAPTSEL0 0x1C0U +#define TIMER4TRIGIN 0x1D0U +#define PINTSECSEL0 0x1E0U +#define DMA1_ITRIG_INMUX0 0x200U +#define DMA1_OTRIG_INMUX0 0x240U +#define HSCMP0_TRIGIN 0x260U +#define ADC0_TRIG0 0x280U +#define ADC1_TRIG0 0x2C0U +#define DAC0_TRIGIN 0x300U +#define DAC1_TRIGIN 0x320U +#define DAC2_TRIGIN 0x340U +#define ENC0TRIG 0x360U +#define ENC0HOME 0x364U +#define ENC0INDEX 0x368U +#define ENC0PHASEB 0x36CU +#define ENC0PHASEA 0x370U +#define ENC1TRIG 0x380U +#define ENC1HOME 0x384U +#define ENC1INDEX 0x388U +#define ENC1PHASEB 0x38CU +#define ENC1PHASEA 0x390U +#define PWM0_EXTSYNC0 0x3A0U +#define PWM0_EXTA0 0x3B0U +#define PWM0_EXTFORCETRIG 0x3C0U +#define PWM0_FAULT0 0x3C4U +#define PWM1_EXTSYNC0 0x3E0U +#define PWM1_EXTA0 0x3F0U +#define PWM1_EXTFORCETRIG 0x400U +#define PWM1_FAULT0 0x404U +#define PWM0_EXTCLKTRIG 0x420U +#define PWM1_EXTCLKTRIG 0x424U +#define AOI0_IN0 0x440U +#define AOI1_IN0 0x480U +#define AOI_EXT_TRIG0 0x4C0U +#define HSCMP1_TRIGIN 0x4E0U +#define HSCMP2_TRIGIN 0x500U +#define DMA0_ITRIG_INMUX_32 0x520U + +#define DMA0_REQ_EN0_ID 0x740U +#define DMA0_REQ_EN1_ID 0x744U +#define DMA1_REQ_EN_ID 0x760U +#define DMA0_ITRIG_EN0_ID 0x780U +#define DMA0_ITRIG_EN1_ID 0x784U +#define DMA1_ITRIG_EN_ID 0x7A0U +#define ENA_SHIFT 8U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< SCT0 INMUX. */ + kINPUTMUX_SctGpioInAToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInBToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInCToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInDToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInEToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInFToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInGToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpioInHToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToSct0 = 24U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0tcomp0ToSct0 = 25U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0tcomp1ToSct0 = 26U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0tcomp2ToSct0 = 27U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0tcomp3ToSct0 = 28U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1tcomp0ToSct0 = 29U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1tcomp1ToSct0 = 30U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1tcomp2ToSct0 = 31U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1tcomp3ToSct0 = 32U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToSct0 = 33U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToSct0 = 34U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToSct0 = 35U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToSct0 = 36U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToSct0 = 37U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToSct0 = 38U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToSct0 = 39U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToSct0 = 40U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToSct0 = 41U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToSct0 = 42U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToSct0 = 43U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToSct0 = 44U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToSct0 = 45U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToSct0 = 46U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToSct0 = 47U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToSct0 = 48U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToSct0 = 49U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToSct0 = 50U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToSct0 = 51U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToSct0 = 52U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToSct0 = 53U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Fc3SckToSct0 = 54U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Fc3RxdSdaMosiDataToSct0 = 55U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Fc3TxdSclMisoWsToSct0 = 55U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Fc3CtsDsaSsel0ToSct0 = 57U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToSct0 = 58U + (SCT0_INMUX0 << PMUX_SHIFT), + + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer0Captsel = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer0Captsel = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 0U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer0Trigger = 29U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer0Trigger = 48U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer1Captsel = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer1Captsel = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 0U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer1Trigger = 29U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer1Trigger = 48U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer2Captsel = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer2Captsel = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 0U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer2Trigger = 29U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer2Trigger = 48U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< DMA0 Input trigger. */ + kINPUTMUX_FlexSpiRxToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexSpiTxToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt0ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigAToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigBToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigCToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigDToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctDma0ToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctDma1ToDma0 = 22U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToDma0 = 23U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToDma0 = 24U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0ToDma0 = 25U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1ToDma0 = 26U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2ToDma0 = 27U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDma0 = 28U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDma0 = 29U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDma0 = 30U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDma0 = 31U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDma0 = 32U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDma0 = 33U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDma0 = 34U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDma0 = 35U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma0 = 36U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma0 = 37U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma0 = 38U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma0 = 39U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma0 = 40U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma0 = 41U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma0 = 42U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma0 = 43U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma0 = 44U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma0 = 45U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma0 = 46U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma0 = 47U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma0 = 48U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma0 = 49U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma0 = 50U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma0 = 51U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToDma0 = 52U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA0 output trigger. */ + kINPUTMUX_Dma0FlexSpiRxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexSpiTxTrigoutToTriginChannels = 1U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0PinInt0TrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0PinInt1TrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0PinInt2TrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0PinInt3TrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer0M0TrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer0M1TrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer1M0TrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer1M1TrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer2M0TrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer2M1TrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer3M0TrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer3M1TrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer4M0TrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Ctimer4M1TrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0CompOutTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0OtrigATrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0OtrigBTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0OtrigCTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0OtrigDTrigoutToTriginChannels = 20U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0SctDma0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0SctDma1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Tcomp0TrigoutToTriginChannels = 23U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc1Tcomp0TrigoutToTriginChannels = 24U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Hscmp0TrigoutToTriginChannels = 25U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Hscmp1TrigoutToTriginChannels = 26U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Hscmp2TrigoutToTriginChannels = 27U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi0Out0TrigoutToTriginChannels = 28U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi0Out1TrigoutToTriginChannels = 29U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi0Out2TrigoutToTriginChannels = 30U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi0Out3TrigoutToTriginChannels = 31U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi1Out0TrigoutToTriginChannels = 32U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi1Out1TrigoutToTriginChannels = 33U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi1Out2TrigoutToTriginChannels = 34U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Aoi1Out3TrigoutToTriginChannels = 35U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqCapt0TrigoutToTriginChannels = 36U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqCapt1TrigoutToTriginChannels = 37U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqCapt2TrigoutToTriginChannels = 38U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqCapt3TrigoutToTriginChannels = 39U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqVal0TrigoutToTriginChannels = 40U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqVal1TrigoutToTriginChannels = 41U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqVal2TrigoutToTriginChannels = 42U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm0ReqVal3TrigoutToTriginChannels = 43U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqCapt0TrigoutToTriginChannels = 44U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqCapt1TrigoutToTriginChannels = 45U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqCapt2TrigoutToTriginChannels = 46U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqCapt3TrigoutToTriginChannels = 47U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqVal0TrigoutToTriginChannels = 48U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqVal1TrigoutToTriginChannels = 49U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqVal2TrigoutToTriginChannels = 50U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0FlexPwm1ReqVal3TrigoutToTriginChannels = 51U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_TmprOutTrigoutToTriginChannels = 52U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_Xtal32MhzToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_WdoscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_MainSysClockToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClkAToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClkBToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_Xtal32MhzToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_WdoscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_MainSysClockToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClkAToFreqmeasTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClkBToFreqmeasTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFreqmeasTarget = 8u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFreqmeasTarget = 9u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer3Captsel = 29U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer3Captsel = 48U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 0U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer3Trigger = 29U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer3Trigger = 48U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer4Captsel = 29U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer4Captsel = 48U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 0U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToTimer4Trigger = 29U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TmprOutToTimer4Trigger = 48U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*Pin interrupt secure select */ + kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), + + /*!< DMA1 Input trigger. */ + kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigAToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigBToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigCToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OtrigDToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexSpiRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexSpiTxToDma1 = 15U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDma1 = 16U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDma1 = 17U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDma1 = 18U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDma1 = 19U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDma1 = 20U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDma1 = 21U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDma1 = 22U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDma1 = 23U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToDma1 = 24U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA1 output trigger. */ + kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcom0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcom0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcom1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcom1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcom3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcom3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Dmic0Ch0TrigoutToTriginChannels = 10U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Dmic0Ch1TrigoutToTriginChannels = 11U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1I3c0RxTrigoutToTriginChannels = 12U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1I3c0TxTrigoutToTriginChannels = 13U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + + /*!< HSCMP0 trigger. */ + kINPUTMUX_PinInt0ToHscmp0Trigger = 0U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_PinInt6ToHscmp0Trigger = 1U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut4ToHscmp0Trigger = 2U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut5ToHscmp0Trigger = 3U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut6ToHscmp0Trigger = 4U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToHscmp0Trigger = 5U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToHscmp0Trigger = 6U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToHscmp0Trigger = 7U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToHscmp0Trigger = 8U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToHscmp0Trigger = 9U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_ArmTxevToHscmp0Trigger = 11U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToHscmp0Trigger = 12U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToHscmp0Trigger = 13U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToHscmp0Trigger = 14U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToHscmp0Trigger = 17U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToHscmp0Trigger = 18U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToHscmp0Trigger = 19U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToHscmp0Trigger = 20U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToHscmp0Trigger = 21U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToHscmp0Trigger = 22U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToHscmp0Trigger = 23U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToHscmp0Trigger = 24U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToHscmp0Trigger = 25U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToHscmp0Trigger = 26U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToHscmp0Trigger = 27U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToHscmp0Trigger = 28U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToHscmp0Trigger = 29U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToHscmp0Trigger = 30U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToHscmp0Trigger = 31U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToHscmp0Trigger = 32U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToHscmp0Trigger = 33U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToHscmp0Trigger = 34U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToHscmp0Trigger = 35U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToHscmp0Trigger = 36U + (HSCMP0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToHscmp0Trigger = 37U + (HSCMP0_TRIGIN << PMUX_SHIFT), + + /*!< ADC0 trigger. */ + kINPUTMUX_PinInt0ToAdc0Trigger = 0U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAdc0Trigger = 1U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToAdc0Trigger = 2U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToAdc0Trigger = 3U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_SctOut9ToAdc0Trigger = 4U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc0Trigger = 5U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc0Trigger = 6U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc0Trigger = 7U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAdc0Trigger = 8U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAdc0Trigger = 9U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_CompOutToAdc0Trigger = 10U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc0Trigger = 11U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToAdc0Trigger = 12U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc0Trigger = 13U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc0Trigger = 14U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc0Trigger = 15U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc0Trigger = 16U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 17U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 18U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 19U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 20U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToAdc0Trigger = 21U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToAdc0Trigger = 22U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToAdc0Trigger = 23U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToAdc0Trigger = 24U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToAdc0Trigger = 25U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToAdc0Trigger = 27U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToAdc0Trigger = 29U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToAdc0Trigger = 30U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToAdc0Trigger = 31U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToAdc0Trigger = 32U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToAdc0Trigger = 33U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToAdc0Trigger = 34U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToAdc0Trigger = 35U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToAdc0Trigger = 36U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToAdc0Trigger = 37U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToAdc0Trigger = 38U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToAdc0Trigger = 39U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc0Trigger = 42U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc0Trigger = 43U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc0Trigger = 44U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc0Trigger = 45U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc0Trigger = 46U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc0Trigger = 47U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc0Trigger = 48U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc0Trigger = 49U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToAdc0Trigger = 50U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToAdc0Trigger = 51U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToAdc0Trigger = 52U + (ADC0_TRIG0 << PMUX_SHIFT), + + /*!< ADC1 trigger. */ + kINPUTMUX_PinInt0ToAdc1Trigger = 0U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToAdc1Trigger = 1U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToAdc1Trigger = 2U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToAdc1Trigger = 3U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_SctOut3ToAdc1Trigger = 4U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc1Trigger = 5U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc1Trigger = 6U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc1Trigger = 7U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAdc1Trigger = 8U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 9U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_CompOutToAdc1Trigger = 10U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc1Trigger = 11U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToAdc1Trigger = 12U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 13U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 14U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 15U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 16U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc1Trigger = 17U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc1Trigger = 18U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc1Trigger = 19U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc1Trigger = 20U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToAdc1Trigger = 21U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToAdc1Trigger = 22U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToAdc1Trigger = 23U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToAdc1Trigger = 24U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToAdc1Trigger = 25U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToAdc1Trigger = 26U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToAdc1Trigger = 27U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToAdc1Trigger = 28U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToAdc1Trigger = 29U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToAdc1Trigger = 30U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToAdc1Trigger = 31U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToAdc1Trigger = 32U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToAdc1Trigger = 33U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToAdc1Trigger = 34U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToAdc1Trigger = 35U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToAdc1Trigger = 36U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToAdc1Trigger = 37U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToAdc1Trigger = 38U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToAdc1Trigger = 39U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc1Trigger = 42U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc1Trigger = 43U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc1Trigger = 44U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc1Trigger = 45U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc1Trigger = 46U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc1Trigger = 47U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc1Trigger = 48U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc1Trigger = 49U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToAdc1Trigger = 50U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToAdc1Trigger = 51U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToAdc1Trigger = 52U + (ADC1_TRIG0 << PMUX_SHIFT), + + /*!< DAC0 trigger. */ + kINPUTMUX_PinInt0ToDac0Trigger = 0U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDac0Trigger = 1U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut4ToDac0Trigger = 2U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut5ToDac0Trigger = 3U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut0ToDac0Trigger = 4U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToDac0Trigger = 5U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToDac0Trigger = 6U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToDac0Trigger = 7U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDac0Trigger = 8U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDac0Trigger = 9U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToDac0Trigger = 10U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_ArmTxevToDac0Trigger = 11U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToDac0Trigger = 12U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToDac0Trigger = 13U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToDac0Trigger = 14U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToDac0Trigger = 15U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToDac0Trigger = 16U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToDac0Trigger = 17U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDac0Trigger = 18U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDac0Trigger = 19U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDac0Trigger = 20U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDac0Trigger = 21U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDac0Trigger = 22U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDac0Trigger = 23U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDac0Trigger = 24U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDac0Trigger = 25U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToDac0Trigger = 26U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToDac0Trigger = 27U + (DAC0_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToDac0Trigger = 28U + (DAC0_TRIGIN << PMUX_SHIFT), + + /*!< DAC1 trigger. */ + kINPUTMUX_PinInt0ToDac1Trigger = 0U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_PinInt4ToDac1Trigger = 1U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut4ToDac1Trigger = 2U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut5ToDac1Trigger = 3U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut1ToDac1Trigger = 4U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToDac1Trigger = 5U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToDac1Trigger = 6U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToDac1Trigger = 7U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDac1Trigger = 8U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDac1Trigger = 9U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToDac1Trigger = 10U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_ArmTxevToDac1Trigger = 11U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToDac1Trigger = 12U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToDac1Trigger = 13U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToDac1Trigger = 14U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToDac1Trigger = 15U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToDac1Trigger = 16U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToDac1Trigger = 17U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDac1Trigger = 18U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDac1Trigger = 19U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDac1Trigger = 20U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDac1Trigger = 21U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDac1Trigger = 22U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDac1Trigger = 23U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDac1Trigger = 24U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDac1Trigger = 25U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToDac1Trigger = 26U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToDac1Trigger = 27U + (DAC1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToDac1Trigger = 28U + (DAC1_TRIGIN << PMUX_SHIFT), + + /*!< DAC2 trigger. */ + kINPUTMUX_PinInt0ToDac2Trigger = 0U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_PinInt5ToDac2Trigger = 1U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut4ToDac2Trigger = 2U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut5ToDac2Trigger = 3U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut2ToDac2Trigger = 4U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToDac2Trigger = 5U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToDac2Trigger = 6U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToDac2Trigger = 7U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToDac2Trigger = 8U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToDac2Trigger = 9U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_CompOutToDac2Trigger = 10U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_ArmTxevToDac2Trigger = 11U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToDac2Trigger = 12U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToDac2Trigger = 13U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToDac2Trigger = 14U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToDac2Trigger = 15U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToDac2Trigger = 16U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToDac2Trigger = 17U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDac2Trigger = 18U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDac2Trigger = 19U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDac2Trigger = 20U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDac2Trigger = 21U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDac2Trigger = 22U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDac2Trigger = 23U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDac2Trigger = 24U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDac2Trigger = 25U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToDac2Trigger = 26U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToDac2Trigger = 27U + (DAC2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToDac2Trigger = 28U + (DAC2_TRIGIN << PMUX_SHIFT), + + /*!< ENC0 TRIG. */ + kINPUTMUX_PinInt0ToEnc0Trigger = 0U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToEnc0Trigger = 1U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc0Trigger = 2U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc0Trigger = 3U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToEnc0Trigger = 4U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc0Trigger = 5U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc0Trigger = 6U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc0Trigger = 7U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToEnc0Trigger = 8U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToEnc0Trigger = 9U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc0Trigger = 10U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc0Trigger = 11U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc0Trigger = 12U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc0Trigger = 13U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc0Trigger = 14U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc0Trigger = 15U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc0Trigger = 16U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc0Trigger = 17U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc0Trigger = 18U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc0Trigger = 19U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc0Trigger = 20U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc0Trigger = 21U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc0Trigger = 22U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc0Trigger = 23U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Trigger = 24U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Trigger = 25U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Trigger = 26U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Trigger = 27U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Trigger = 28U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Trigger = 29U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Trigger = 30U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Trigger = 31U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc0Trigger = 32U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc0Trigger = 33U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc0Trigger = 34U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc0Trigger = 35U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc0Trigger = 36U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc0Trigger = 37U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc0Trigger = 38U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc0Trigger = 39U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc0Trigger = 40U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc0Trigger = 41U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc0Trigger = 42U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc0Trigger = 43U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc0Trigger = 44U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc0Trigger = 45U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc0Trigger = 46U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc0Trigger = 47U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc0Trigger = 48U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc0Trigger = 49U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc0Trigger = 50U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc0Trigger = 51U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc0Trigger = 52U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc0Trigger = 53U + (ENC0TRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc0Trigger = 54U + (ENC0TRIG << PMUX_SHIFT), + + /*!< ENC0 HOME. */ + kINPUTMUX_PinInt0ToEnc0Home = 0U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_PinInt4ToEnc0Home = 1U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc0Home = 2U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc0Home = 3U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_SctOut1ToEnc0Home = 4U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc0Home = 5U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc0Home = 6U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc0Home = 7U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToEnc0Home = 8U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToEnc0Home = 9U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc0Home = 10U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc0Home = 11U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc0Home = 12U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc0Home = 13U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc0Home = 14U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc0Home = 15U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc0Home = 16U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc0Home = 17U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc0Home = 18U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc0Home = 19U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc0Home = 20U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc0Home = 21U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc0Home = 22U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc0Home = 23U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Home = 24U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Home = 25U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Home = 26U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Home = 27U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Home = 28U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Home = 29U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Home = 30U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Home = 31U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc0Home = 32U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc0Home = 33U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc0Home = 34U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc0Home = 35U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc0Home = 36U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc0Home = 37U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc0Home = 38U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc0Home = 39U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc0Home = 40U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc0Home = 41U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc0Home = 42U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc0Home = 43U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc0Home = 44U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc0Home = 45U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc0Home = 46U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc0Home = 47U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc0Home = 48U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc0Home = 49U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc0Home = 50U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc0Home = 51U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc0Home = 52U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc0Home = 53U + (ENC0HOME << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc0Home = 54U + (ENC0HOME << PMUX_SHIFT), + + /*!< ENC0 INDEX. */ + kINPUTMUX_PinInt0ToEnc0Index = 0U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_PinInt4ToEnc0Index = 1U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc0Index = 2U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc0Index = 3U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_SctOut1ToEnc0Index = 4U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc0Index = 5U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc0Index = 6U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc0Index = 7U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToEnc0Index = 8U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToEnc0Index = 9U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc0Index = 10U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc0Index = 11U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc0Index = 12U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc0Index = 13U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc0Index = 14U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc0Index = 15U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc0Index = 16U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc0Index = 17U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc0Index = 18U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc0Index = 19U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc0Index = 20U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc0Index = 21U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc0Index = 22U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc0Index = 23U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Index = 24U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Index = 25U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Index = 26U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Index = 27U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Index = 28U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Index = 29U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Index = 30U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Index = 31U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc0Index = 32U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc0Index = 33U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc0Index = 34U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc0Index = 35U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc0Index = 36U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc0Index = 37U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc0Index = 38U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc0Index = 39U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc0Index = 40U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc0Index = 41U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc0Index = 42U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc0Index = 43U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc0Index = 44U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc0Index = 45U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc0Index = 46U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc0Index = 47U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc0Index = 48U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc0Index = 49U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc0Index = 50U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc0Index = 51U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc0Index = 52U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc0Index = 53U + (ENC0INDEX << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc0Index = 54U + (ENC0INDEX << PMUX_SHIFT), + + /*!< ENC0 PHASEB. */ + kINPUTMUX_PinInt0ToEnc0Phaseb = 0U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_PinInt4ToEnc0Phaseb = 1U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc0Phaseb = 2U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc0Phaseb = 3U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_SctOut1ToEnc0Phaseb = 4U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc0Phaseb = 5U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc0Phaseb = 6U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc0Phaseb = 7U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToEnc0Phaseb = 8U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToEnc0Phaseb = 9U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc0Phaseb = 10U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc0Phaseb = 11U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc0Phaseb = 12U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc0Phaseb = 13U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc0Phaseb = 14U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc0Phaseb = 15U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc0Phaseb = 16U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc0Phaseb = 17U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc0Phaseb = 18U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc0Phaseb = 19U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc0Phaseb = 20U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc0Phaseb = 21U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc0Phaseb = 22U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc0Phaseb = 23U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Phaseb = 24U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Phaseb = 25U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Phaseb = 26U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Phaseb = 27U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Phaseb = 28U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Phaseb = 29U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Phaseb = 30U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Phaseb = 31U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc0Phaseb = 32U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc0Phaseb = 33U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc0Phaseb = 34U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc0Phaseb = 35U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc0Phaseb = 36U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc0Phaseb = 37U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc0Phaseb = 38U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc0Phaseb = 39U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc0Phaseb = 40U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc0Phaseb = 41U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc0Phaseb = 42U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc0Phaseb = 43U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc0Phaseb = 44U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc0Phaseb = 45U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc0Phaseb = 46U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc0Phaseb = 47U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc0Phaseb = 48U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc0Phaseb = 49U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc0Phaseb = 50U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc0Phaseb = 51U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc0Phaseb = 52U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc0Phaseb = 53U + (ENC0PHASEB << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc0Phaseb = 54U + (ENC0PHASEB << PMUX_SHIFT), + + /*!< ENC0 PHASEA. */ + kINPUTMUX_PinInt0ToEnc0Phasea = 0U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_PinInt4ToEnc0Phasea = 1U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc0Phasea = 2U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc0Phasea = 3U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_SctOut1ToEnc0Phasea = 4U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc0Phasea = 5U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc0Phasea = 6U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc0Phasea = 7U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToEnc0Phasea = 8U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToEnc0Phasea = 9U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc0Phasea = 10U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc0Phasea = 11U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc0Phasea = 12U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc0Phasea = 13U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc0Phasea = 14U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc0Phasea = 15U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc0Phasea = 16U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc0Phasea = 17U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc0Phasea = 18U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc0Phasea = 19U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc0Phasea = 20U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc0Phasea = 21U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc0Phasea = 22U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc0Phasea = 23U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc0Phasea = 24U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc0Phasea = 25U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc0Phasea = 26U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc0Phasea = 27U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc0Phasea = 28U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc0Phasea = 29U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc0Phasea = 30U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc0Phasea = 31U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc0Phasea = 32U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc0Phasea = 33U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc0Phasea = 34U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc0Phasea = 35U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc0Phasea = 36U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc0Phasea = 37U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc0Phasea = 38U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc0Phasea = 39U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc0Phasea = 40U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc0Phasea = 41U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc0Phasea = 42U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc0Phasea = 43U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc0Phasea = 44U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc0Phasea = 45U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc0Phasea = 46U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc0Phasea = 47U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc0Phasea = 48U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc0Phasea = 49U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc0Phasea = 50U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc0Phasea = 51U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc0Phasea = 52U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc0Phasea = 53U + (ENC0PHASEA << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc0Phasea = 54U + (ENC0PHASEA << PMUX_SHIFT), + + /*!< ENC1 TRIG. */ + kINPUTMUX_PinInt0ToEnc1Trigger = 0U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToEnc1Trigger = 1U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc1Trigger = 2U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc1Trigger = 3U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_SctOut7ToEnc1Trigger = 4U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc1Trigger = 5U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc1Trigger = 6U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc1Trigger = 7U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToEnc1Trigger = 8U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToEnc1Trigger = 9U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc1Trigger = 10U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc1Trigger = 11U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc1Trigger = 12U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc1Trigger = 13U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc1Trigger = 14U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc1Trigger = 15U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc1Trigger = 16U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc1Trigger = 17U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc1Trigger = 18U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc1Trigger = 19U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc1Trigger = 20U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc1Trigger = 21U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc1Trigger = 22U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc1Trigger = 23U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Trigger = 24U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Trigger = 25U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Trigger = 26U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Trigger = 27U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Trigger = 28U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Trigger = 29U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Trigger = 30U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Trigger = 31U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc1Trigger = 32U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc1Trigger = 33U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc1Trigger = 34U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc1Trigger = 35U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc1Trigger = 36U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc1Trigger = 37U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc1Trigger = 38U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc1Trigger = 39U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc1Trigger = 40U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc1Trigger = 41U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc1Trigger = 42U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc1Trigger = 43U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc1Trigger = 44U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc1Trigger = 45U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc1Trigger = 46U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc1Trigger = 47U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc1Trigger = 48U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc1Trigger = 49U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc1Trigger = 50U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc1Trigger = 51U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc1Trigger = 52U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc1Trigger = 53U + (ENC1TRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc1Trigger = 54U + (ENC1TRIG << PMUX_SHIFT), + + /*!< ENC1 HOME. */ + kINPUTMUX_PinInt0ToEnc1Home = 0U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_PinInt5ToEnc1Home = 1U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc1Home = 2U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc1Home = 3U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_SctOut7ToEnc1Home = 4U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc1Home = 5U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc1Home = 6U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc1Home = 7U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToEnc1Home = 8U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToEnc1Home = 9U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc1Home = 10U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc1Home = 11U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc1Home = 12U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc1Home = 13U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc1Home = 14U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc1Home = 15U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc1Home = 16U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc1Home = 17U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc1Home = 18U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc1Home = 19U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc1Home = 20U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc1Home = 21U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc1Home = 22U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc1Home = 23U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Home = 24U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Home = 25U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Home = 26U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Home = 27U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Home = 28U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Home = 29U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Home = 30U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Home = 31U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc1Home = 32U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc1Home = 33U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc1Home = 34U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc1Home = 35U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc1Home = 36U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc1Home = 37U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc1Home = 38U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc1Home = 39U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc1Home = 40U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc1Home = 41U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc1Home = 42U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc1Home = 43U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc1Home = 44U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc1Home = 45U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc1Home = 46U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc1Home = 47U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc1Home = 48U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc1Home = 49U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc1Home = 50U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc1Home = 51U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc1Home = 52U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc1Home = 53U + (ENC1HOME << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc1Home = 54U + (ENC1HOME << PMUX_SHIFT), + + /*!< ENC1 INDEX. */ + kINPUTMUX_PinInt0ToEnc1Index = 0U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_PinInt5ToEnc1Index = 1U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc1Index = 2U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc1Index = 3U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_SctOut7ToEnc1Index = 4U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc1Index = 5U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc1Index = 6U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc1Index = 7U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToEnc1Index = 8U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToEnc1Index = 9U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc1Index = 10U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc1Index = 11U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc1Index = 12U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc1Index = 13U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc1Index = 14U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc1Index = 15U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc1Index = 16U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc1Index = 17U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc1Index = 18U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc1Index = 19U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc1Index = 20U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc1Index = 21U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc1Index = 22U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc1Index = 23U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Index = 24U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Index = 25U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Index = 26U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Index = 27U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Index = 28U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Index = 29U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Index = 30U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Index = 31U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc1Index = 32U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc1Index = 33U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc1Index = 34U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc1Index = 35U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc1Index = 36U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc1Index = 37U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc1Index = 38U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc1Index = 39U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc1Index = 40U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc1Index = 41U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc1Index = 42U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc1Index = 43U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc1Index = 44U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc1Index = 45U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc1Index = 46U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc1Index = 47U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc1Index = 48U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc1Index = 49U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc1Index = 50U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc1Index = 51U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc1Index = 52U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc1Index = 53U + (ENC1INDEX << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc1Index = 54U + (ENC1INDEX << PMUX_SHIFT), + + /*!< ENC1 PHASEB. */ + kINPUTMUX_PinInt0ToEnc1Phaseb = 0U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_PinInt5ToEnc1Phaseb = 1U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc1Phaseb = 2U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc1Phaseb = 3U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_SctOut7ToEnc1Phaseb = 4U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc1Phaseb = 5U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc1Phaseb = 6U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc1Phaseb = 7U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToEnc1Phaseb = 8U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToEnc1Phaseb = 9U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc1Phaseb = 10U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc1Phaseb = 11U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc1Phaseb = 12U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc1Phaseb = 13U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc1Phaseb = 14U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc1Phaseb = 15U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc1Phaseb = 16U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc1Phaseb = 17U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc1Phaseb = 18U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc1Phaseb = 19U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc1Phaseb = 20U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc1Phaseb = 21U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc1Phaseb = 22U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc1Phaseb = 23U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Phaseb = 24U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Phaseb = 25U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Phaseb = 26U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Phaseb = 27U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Phaseb = 28U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Phaseb = 29U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Phaseb = 30U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Phaseb = 31U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc1Phaseb = 32U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc1Phaseb = 33U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc1Phaseb = 34U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc1Phaseb = 35U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc1Phaseb = 36U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc1Phaseb = 37U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc1Phaseb = 38U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc1Phaseb = 39U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc1Phaseb = 40U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc1Phaseb = 41U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc1Phaseb = 42U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc1Phaseb = 43U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc1Phaseb = 44U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc1Phaseb = 45U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc1Phaseb = 46U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc1Phaseb = 47U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc1Phaseb = 48U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc1Phaseb = 49U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc1Phaseb = 50U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc1Phaseb = 51U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc1Phaseb = 52U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc1Phaseb = 53U + (ENC1PHASEB << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc1Phaseb = 54U + (ENC1PHASEB << PMUX_SHIFT), + + /*!< ENC1 PHASEA. */ + kINPUTMUX_PinInt0ToEnc1Phasea = 0U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_PinInt5ToEnc1Phasea = 1U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_SctOut4ToEnc1Phasea = 2U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_SctOut5ToEnc1Phasea = 3U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_SctOut7ToEnc1Phasea = 4U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEnc1Phasea = 5U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEnc1Phasea = 6U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEnc1Phasea = 7U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToEnc1Phasea = 8U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToEnc1Phasea = 9U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_CompOutToEnc1Phasea = 10U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ArmTxevToEnc1Phasea = 11U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToEnc1Phasea = 12U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEnc1Phasea = 13U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEnc1Phasea = 14U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEnc1Phasea = 15U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEnc1Phasea = 16U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEnc1Phasea = 17U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEnc1Phasea = 18U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEnc1Phasea = 19U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEnc1Phasea = 20U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToEnc1Phasea = 21U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToEnc1Phasea = 22U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToEnc1Phasea = 23U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToEnc1Phasea = 24U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToEnc1Phasea = 25U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToEnc1Phasea = 26U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToEnc1Phasea = 27U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToEnc1Phasea = 28U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToEnc1Phasea = 29U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToEnc1Phasea = 30U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToEnc1Phasea = 31U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToEnc1Phasea = 32U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToEnc1Phasea = 33U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToEnc1Phasea = 34U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToEnc1Phasea = 35U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToEnc1Phasea = 36U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToEnc1Phasea = 37U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToEnc1Phasea = 38U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToEnc1Phasea = 39U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToEnc1Phasea = 40U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToEnc1Phasea = 41U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToEnc1Phasea = 42U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToEnc1Phasea = 43U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToEnc1Phasea = 44U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToEnc1Phasea = 45U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToEnc1Phasea = 46U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToEnc1Phasea = 47U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToEnc1Phasea = 48U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToEnc1Phasea = 49U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToEnc1Phasea = 50U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToEnc1Phasea = 51U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToEnc1Phasea = 52U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToEnc1Phasea = 53U + (ENC1PHASEA << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToEnc1Phasea = 54U + (ENC1PHASEA << PMUX_SHIFT), + + /*!< PWM0 external synchronization trigger. */ + kINPUTMUX_PinInt0ToPwm0ExtSyncTrigger = 0U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_PinInt5ToPwm0ExtSyncTrigger = 1U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm0ExtSyncTrigger = 2U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm0ExtSyncTrigger = 3U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_SctOut2ToPwm0ExtSyncTrigger = 4U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm0ExtSyncTrigger = 5U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm0ExtSyncTrigger = 6U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm0ExtSyncTrigger = 7U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToPwm0ExtSyncTrigger = 8U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToPwm0ExtSyncTrigger = 9U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm0ExtSyncTrigger = 10U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm0ExtSyncTrigger = 11U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm0ExtSyncTrigger = 12U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm0ExtSyncTrigger = 13U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm0ExtSyncTrigger = 14U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm0ExtSyncTrigger = 15U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm0ExtSyncTrigger = 16U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm0ExtSyncTrigger = 17U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm0ExtSyncTrigger = 18U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm0ExtSyncTrigger = 19U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm0ExtSyncTrigger = 20U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm0ExtSyncTrigger = 21U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm0ExtSyncTrigger = 22U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm0ExtSyncTrigger = 23U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtSyncTrigger = 24U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtSyncTrigger = 25U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtSyncTrigger = 26U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtSyncTrigger = 27U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtSyncTrigger = 28U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtSyncTrigger = 29U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtSyncTrigger = 30U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtSyncTrigger = 31U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm0ExtSyncTrigger = 32U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm0ExtSyncTrigger = 33U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtSyncTrigger = 34U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtSyncTrigger = 35U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm0ExtSyncTrigger = 36U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm0ExtSyncTrigger = 37U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtSyncTrigger = 38U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtSyncTrigger = 39U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm0ExtSyncTrigger = 40U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm0ExtSyncTrigger = 41U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm0ExtSyncTrigger = 42U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm0ExtSyncTrigger = 43U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm0ExtSyncTrigger = 44U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm0ExtSyncTrigger = 45U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm0ExtSyncTrigger = 46U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm0ExtSyncTrigger = 47U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm0ExtSyncTrigger = 48U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm0ExtSyncTrigger = 49U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm0ExtSyncTrigger = 50U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm0ExtSyncTrigger = 51U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm0ExtSyncTrigger = 52U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm0ExtSyncTrigger = 53U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm0ExtSyncTrigger = 54U + (PWM0_EXTSYNC0 << PMUX_SHIFT), + + /*!< PWM0 input trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm0ExtATrigger = 0U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_PinInt5ToPwm0ExtATrigger = 1U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm0ExtATrigger = 2U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm0ExtATrigger = 3U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_SctOut2ToPwm0ExtATrigger = 4U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm0ExtATrigger = 5U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm0ExtATrigger = 6U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm0ExtATrigger = 7U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToPwm0ExtATrigger = 8U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToPwm0ExtATrigger = 9U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm0ExtATrigger = 10U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm0ExtATrigger = 11U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm0ExtATrigger = 12U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm0ExtATrigger = 13U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm0ExtATrigger = 14U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm0ExtATrigger = 15U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm0ExtATrigger = 16U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm0ExtATrigger = 17U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm0ExtATrigger = 18U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm0ExtATrigger = 19U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm0ExtATrigger = 20U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm0ExtATrigger = 21U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm0ExtATrigger = 22U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm0ExtATrigger = 23U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtATrigger = 24U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtATrigger = 25U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtATrigger = 26U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtATrigger = 27U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtATrigger = 28U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtATrigger = 29U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtATrigger = 30U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtATrigger = 31U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm0ExtATrigger = 32U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm0ExtATrigger = 33U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtATrigger = 34U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtATrigger = 35U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm0ExtATrigger = 36U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm0ExtATrigger = 37U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtATrigger = 38U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtATrigger = 39U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm0ExtATrigger = 40U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm0ExtATrigger = 41U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm0ExtATrigger = 42U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm0ExtATrigger = 43U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm0ExtATrigger = 44U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm0ExtATrigger = 45U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm0ExtATrigger = 46U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm0ExtATrigger = 47U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm0ExtATrigger = 48U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm0ExtATrigger = 49U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm0ExtATrigger = 50U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm0ExtATrigger = 51U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm0ExtATrigger = 52U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm0ExtATrigger = 53U + (PWM0_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm0ExtATrigger = 54U + (PWM0_EXTA0 << PMUX_SHIFT), + + /*!< PWM0 external force trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm0ExtForceTrigger = 0U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToPwm0ExtForceTrigger = 1U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm0ExtForceTrigger = 2U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm0ExtForceTrigger = 3U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_SctOut2ToPwm0ExtForceTrigger = 4U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm0ExtForceTrigger = 5U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm0ExtForceTrigger = 6U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm0ExtForceTrigger = 7U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToPwm0ExtForceTrigger = 8U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToPwm0ExtForceTrigger = 9U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm0ExtForceTrigger = 10U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm0ExtForceTrigger = 11U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm0ExtForceTrigger = 12U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm0ExtForceTrigger = 13U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm0ExtForceTrigger = 14U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm0ExtForceTrigger = 15U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm0ExtForceTrigger = 16U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm0ExtForceTrigger = 17U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm0ExtForceTrigger = 18U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm0ExtForceTrigger = 19U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm0ExtForceTrigger = 20U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm0ExtForceTrigger = 21U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm0ExtForceTrigger = 22U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm0ExtForceTrigger = 23U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtForceTrigger = 24U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtForceTrigger = 25U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtForceTrigger = 26U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtForceTrigger = 27U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtForceTrigger = 28U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtForceTrigger = 29U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtForceTrigger = 30U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtForceTrigger = 31U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm0ExtForceTrigger = 32U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm0ExtForceTrigger = 33U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtForceTrigger = 34U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtForceTrigger = 35U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm0ExtForceTrigger = 36U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm0ExtForceTrigger = 37U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtForceTrigger = 38U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtForceTrigger = 39U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm0ExtForceTrigger = 40U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm0ExtForceTrigger = 41U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm0ExtForceTrigger = 42U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm0ExtForceTrigger = 43U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm0ExtForceTrigger = 44U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm0ExtForceTrigger = 45U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm0ExtForceTrigger = 46U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm0ExtForceTrigger = 47U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm0ExtForceTrigger = 48U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm0ExtForceTrigger = 49U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm0ExtForceTrigger = 50U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm0ExtForceTrigger = 51U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm0ExtForceTrigger = 52U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm0ExtForceTrigger = 53U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm0ExtForceTrigger = 54U + (PWM0_EXTFORCETRIG << PMUX_SHIFT), + + /*!< PWM0 fault input trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm0FaultTrigger = 0U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_PinInt5ToPwm0FaultTrigger = 1U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm0FaultTrigger = 2U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm0FaultTrigger = 3U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_SctOut2ToPwm0FaultTrigger = 4U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm0FaultTrigger = 5U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm0FaultTrigger = 6U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm0FaultTrigger = 7U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToPwm0FaultTrigger = 8U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToPwm0FaultTrigger = 9U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm0FaultTrigger = 10U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm0FaultTrigger = 11U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm0FaultTrigger = 12U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm0FaultTrigger = 13U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm0FaultTrigger = 14U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm0FaultTrigger = 15U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm0FaultTrigger = 16U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm0FaultTrigger = 17U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm0FaultTrigger = 18U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm0FaultTrigger = 19U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm0FaultTrigger = 20U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm0FaultTrigger = 21U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm0FaultTrigger = 22U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm0FaultTrigger = 23U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0FaultTrigger = 24U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0FaultTrigger = 25U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0FaultTrigger = 26U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0FaultTrigger = 27U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0FaultTrigger = 28U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0FaultTrigger = 29U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0FaultTrigger = 30U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0FaultTrigger = 31U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm0FaultTrigger = 32U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm0FaultTrigger = 33U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0FaultTrigger = 34U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0FaultTrigger = 35U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm0FaultTrigger = 36U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm0FaultTrigger = 37U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0FaultTrigger = 38U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0FaultTrigger = 39U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm0FaultTrigger = 40U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm0FaultTrigger = 41U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm0FaultTrigger = 42U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm0FaultTrigger = 43U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm0FaultTrigger = 44U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm0FaultTrigger = 45U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm0FaultTrigger = 46U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm0FaultTrigger = 47U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm0FaultTrigger = 48U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm0FaultTrigger = 49U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm0FaultTrigger = 50U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm0FaultTrigger = 51U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm0FaultTrigger = 52U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm0FaultTrigger = 53U + (PWM0_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm0FaultTrigger = 54U + (PWM0_FAULT0 << PMUX_SHIFT), + + /*!< PWM0 extclk input trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm0ExtClkTrigger = 0U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToPwm0ExtClkTrigger = 1U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm0ExtClkTrigger = 2U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm0ExtClkTrigger = 3U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_SctOut2ToPwm0ExtClkTrigger = 4U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm0ExtClkTrigger = 5U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm0ExtClkTrigger = 6U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm0ExtClkTrigger = 7U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToPwm0ExtClkTrigger = 8U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToPwm0ExtClkTrigger = 9U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm0ExtClkTrigger = 10U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm0ExtClkTrigger = 11U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm0ExtClkTrigger = 12U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm0ExtClkTrigger = 13U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm0ExtClkTrigger = 14U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm0ExtClkTrigger = 15U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm0ExtClkTrigger = 16U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm0ExtClkTrigger = 17U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm0ExtClkTrigger = 18U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm0ExtClkTrigger = 19U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm0ExtClkTrigger = 20U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm0ExtClkTrigger = 21U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm0ExtClkTrigger = 22U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm0ExtClkTrigger = 23U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToPwm0ExtClkTrigger = 24U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToPwm0ExtClkTrigger = 25U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToPwm0ExtClkTrigger = 26U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToPwm0ExtClkTrigger = 27U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToPwm0ExtClkTrigger = 28U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToPwm0ExtClkTrigger = 29U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToPwm0ExtClkTrigger = 30U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToPwm0ExtClkTrigger = 31U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm0ExtClkTrigger = 32U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm0ExtClkTrigger = 33U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtClkTrigger = 34U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtClkTrigger = 35U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm0ExtClkTrigger = 36U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm0ExtClkTrigger = 37U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtClkTrigger = 38U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtClkTrigger = 39U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm0ExtClkTrigger = 40U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm0ExtClkTrigger = 41U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm0ExtClkTrigger = 42U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm0ExtClkTrigger = 43U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm0ExtClkTrigger = 44U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm0ExtClkTrigger = 45U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm0ExtClkTrigger = 46U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm0ExtClkTrigger = 47U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm0ExtClkTrigger = 48U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm0ExtClkTrigger = 49U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm0ExtClkTrigger = 50U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm0ExtClkTrigger = 51U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm0ExtClkTrigger = 52U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm0ExtClkTrigger = 53U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm0ExtClkTrigger = 54U + (PWM0_EXTCLKTRIG << PMUX_SHIFT), + + /*!< PWM1 external synchronization trigger. */ + kINPUTMUX_PinInt0ToPwm1ExtSyncTrigger = 0U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToPwm1ExtSyncTrigger = 1U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm1ExtSyncTrigger = 2U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm1ExtSyncTrigger = 3U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_SctOut3ToPwm1ExtSyncTrigger = 4U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm1ExtSyncTrigger = 5U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm1ExtSyncTrigger = 6U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm1ExtSyncTrigger = 7U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToPwm1ExtSyncTrigger = 8U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToPwm1ExtSyncTrigger = 9U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm1ExtSyncTrigger = 10U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm1ExtSyncTrigger = 11U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm1ExtSyncTrigger = 12U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm1ExtSyncTrigger = 13U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm1ExtSyncTrigger = 14U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm1ExtSyncTrigger = 15U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm1ExtSyncTrigger = 16U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm1ExtSyncTrigger = 17U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm1ExtSyncTrigger = 18U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm1ExtSyncTrigger = 19U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm1ExtSyncTrigger = 20U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm1ExtSyncTrigger = 21U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm1ExtSyncTrigger = 22U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm1ExtSyncTrigger = 23U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtSyncTrigger = 24U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtSyncTrigger = 25U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtSyncTrigger = 26U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtSyncTrigger = 27U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtSyncTrigger = 28U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtSyncTrigger = 29U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtSyncTrigger = 30U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtSyncTrigger = 31U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm1ExtSyncTrigger = 32U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm1ExtSyncTrigger = 33U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtSyncTrigger = 34U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtSyncTrigger = 35U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm1ExtSyncTrigger = 36U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm1ExtSyncTrigger = 37U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtSyncTrigger = 38U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtSyncTrigger = 39U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm1ExtSyncTrigger = 40U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm1ExtSyncTrigger = 41U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm1ExtSyncTrigger = 42U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm1ExtSyncTrigger = 43U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm1ExtSyncTrigger = 44U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm1ExtSyncTrigger = 45U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm1ExtSyncTrigger = 46U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm1ExtSyncTrigger = 47U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm1ExtSyncTrigger = 48U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm1ExtSyncTrigger = 49U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm1ExtSyncTrigger = 50U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm1ExtSyncTrigger = 51U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm1ExtSyncTrigger = 52U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm1ExtSyncTrigger = 53U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm1ExtSyncTrigger = 54U + (PWM1_EXTSYNC0 << PMUX_SHIFT), + + /*!< PWM1 input trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm1ExtATrigger = 0U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToPwm1ExtATrigger = 1U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm1ExtATrigger = 2U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm1ExtATrigger = 3U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_SctOut3ToPwm1ExtATrigger = 4U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm1ExtATrigger = 5U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm1ExtATrigger = 6U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm1ExtATrigger = 7U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToPwm1ExtATrigger = 8U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToPwm1ExtATrigger = 9U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm1ExtATrigger = 10U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm1ExtATrigger = 11U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm1ExtATrigger = 12U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm1ExtATrigger = 13U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm1ExtATrigger = 14U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm1ExtATrigger = 15U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm1ExtATrigger = 16U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm1ExtATrigger = 17U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm1ExtATrigger = 18U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm1ExtATrigger = 19U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm1ExtATrigger = 20U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm1ExtATrigger = 21U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm1ExtATrigger = 22U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm1ExtATrigger = 23U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtATrigger = 24U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtATrigger = 25U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtATrigger = 26U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtATrigger = 27U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtATrigger = 28U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtATrigger = 29U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtATrigger = 30U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtATrigger = 31U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm1ExtATrigger = 32U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm1ExtATrigger = 33U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtATrigger = 34U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtATrigger = 35U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm1ExtATrigger = 36U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm1ExtATrigger = 37U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtATrigger = 38U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtATrigger = 39U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm1ExtATrigger = 40U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm1ExtATrigger = 41U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm1ExtATrigger = 42U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm1ExtATrigger = 43U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm1ExtATrigger = 44U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm1ExtATrigger = 45U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm1ExtATrigger = 46U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm1ExtATrigger = 47U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm1ExtATrigger = 48U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm1ExtATrigger = 49U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm1ExtATrigger = 50U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm1ExtATrigger = 51U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm1ExtATrigger = 52U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm1ExtATrigger = 53U + (PWM1_EXTA0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm1ExtATrigger = 54U + (PWM1_EXTA0 << PMUX_SHIFT), + + /*!< PWM1 external force trigger connections. */ + kINPUTMUX_PinInt0ToPwm1ExtForceTrigger = 0U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToPwm1ExtForceTrigger = 1U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm1ExtForceTrigger = 2U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm1ExtForceTrigger = 3U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToPwm1ExtForceTrigger = 4U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm1ExtForceTrigger = 5U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm1ExtForceTrigger = 6U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm1ExtForceTrigger = 7U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToPwm1ExtForceTrigger = 8U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToPwm1ExtForceTrigger = 9U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm1ExtForceTrigger = 10U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm1ExtForceTrigger = 11U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm1ExtForceTrigger = 12U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm1ExtForceTrigger = 13U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm1ExtForceTrigger = 14U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm1ExtForceTrigger = 15U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm1ExtForceTrigger = 16U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm1ExtForceTrigger = 17U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm1ExtForceTrigger = 18U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm1ExtForceTrigger = 19U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm1ExtForceTrigger = 20U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm1ExtForceTrigger = 21U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm1ExtForceTrigger = 22U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm1ExtForceTrigger = 23U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtForceTrigger = 24U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtForceTrigger = 25U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtForceTrigger = 26U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtForceTrigger = 27U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtForceTrigger = 28U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtForceTrigger = 29U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtForceTrigger = 30U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtForceTrigger = 31U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm1ExtForceTrigger = 32U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm1ExtForceTrigger = 33U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtForceTrigger = 34U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtForceTrigger = 35U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm1ExtForceTrigger = 36U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm1ExtForceTrigger = 37U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtForceTrigger = 38U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtForceTrigger = 39U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm1ExtForceTrigger = 40U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm1ExtForceTrigger = 41U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm1ExtForceTrigger = 42U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm1ExtForceTrigger = 43U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm1ExtForceTrigger = 44U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm1ExtForceTrigger = 45U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm1ExtForceTrigger = 46U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm1ExtForceTrigger = 47U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm1ExtForceTrigger = 48U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm1ExtForceTrigger = 49U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm1ExtForceTrigger = 50U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm1ExtForceTrigger = 51U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm1ExtForceTrigger = 52U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm1ExtForceTrigger = 53U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm1ExtForceTrigger = 54U + (PWM1_EXTFORCETRIG << PMUX_SHIFT), + + /*!< PWM1 fault input trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm1FaultTrigger = 0U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToPwm1FaultTrigger = 1U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm1FaultTrigger = 2U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm1FaultTrigger = 3U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_SctOut3ToPwm1FaultTrigger = 4U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm1FaultTrigger = 5U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm1FaultTrigger = 6U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm1FaultTrigger = 7U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToPwm1FaultTrigger = 8U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToPwm1FaultTrigger = 9U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm1FaultTrigger = 10U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm1FaultTrigger = 11U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm1FaultTrigger = 12U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm1FaultTrigger = 13U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm1FaultTrigger = 14U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm1FaultTrigger = 15U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm1FaultTrigger = 16U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm1FaultTrigger = 17U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm1FaultTrigger = 18U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm1FaultTrigger = 19U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm1FaultTrigger = 20U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm1FaultTrigger = 21U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm1FaultTrigger = 22U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm1FaultTrigger = 23U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1FaultTrigger = 24U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1FaultTrigger = 25U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1FaultTrigger = 26U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1FaultTrigger = 27U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1FaultTrigger = 28U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1FaultTrigger = 29U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1FaultTrigger = 30U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1FaultTrigger = 31U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm1FaultTrigger = 32U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm1FaultTrigger = 33U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1FaultTrigger = 34U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1FaultTrigger = 35U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm1FaultTrigger = 36U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm1FaultTrigger = 37U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1FaultTrigger = 38U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1FaultTrigger = 39U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm1FaultTrigger = 40U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm1FaultTrigger = 41U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm1FaultTrigger = 42U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm1FaultTrigger = 43U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm1FaultTrigger = 44U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm1FaultTrigger = 45U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm1FaultTrigger = 46U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm1FaultTrigger = 47U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm1FaultTrigger = 48U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm1FaultTrigger = 49U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm1FaultTrigger = 50U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm1FaultTrigger = 51U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm1FaultTrigger = 52U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm1FaultTrigger = 53U + (PWM1_FAULT0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm1FaultTrigger = 54U + (PWM1_FAULT0 << PMUX_SHIFT), + + /*!< PWM1 extclk input trigger connections trigger. */ + kINPUTMUX_PinInt0ToPwm1ExtClkTrigger = 0U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToPwm1ExtClkTrigger = 1U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToPwm1ExtClkTrigger = 2U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToPwm1ExtClkTrigger = 3U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToPwm1ExtClkTrigger = 4U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToPwm1ExtClkTrigger = 5U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToPwm1ExtClkTrigger = 6U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToPwm1ExtClkTrigger = 7U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToPwm1ExtClkTrigger = 8U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToPwm1ExtClkTrigger = 9U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_CompOutToPwm1ExtClkTrigger = 10U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToPwm1ExtClkTrigger = 11U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToPwm1ExtClkTrigger = 12U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToPwm1ExtClkTrigger = 13U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToPwm1ExtClkTrigger = 14U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToPwm1ExtClkTrigger = 15U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToPwm1ExtClkTrigger = 16U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToPwm1ExtClkTrigger = 17U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToPwm1ExtClkTrigger = 18U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToPwm1ExtClkTrigger = 19U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToPwm1ExtClkTrigger = 20U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToPwm1ExtClkTrigger = 21U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToPwm1ExtClkTrigger = 22U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToPwm1ExtClkTrigger = 23U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToPwm1ExtClkTrigger = 24U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToPwm1ExtClkTrigger = 25U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToPwm1ExtClkTrigger = 26U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToPwm1ExtClkTrigger = 27U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToPwm1ExtClkTrigger = 28U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToPwm1ExtClkTrigger = 29U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToPwm1ExtClkTrigger = 30U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToPwm1ExtClkTrigger = 31U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToPwm1ExtClkTrigger = 32U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToPwm1ExtClkTrigger = 33U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtClkTrigger = 34U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtClkTrigger = 35U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToPwm1ExtClkTrigger = 36U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToPwm1ExtClkTrigger = 37U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtClkTrigger = 38U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtClkTrigger = 39U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToPwm1ExtClkTrigger = 40U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToPwm1ExtClkTrigger = 41U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToPwm1ExtClkTrigger = 42U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToPwm1ExtClkTrigger = 43U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToPwm1ExtClkTrigger = 44U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToPwm1ExtClkTrigger = 45U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn4ToPwm1ExtClkTrigger = 46U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn5ToPwm1ExtClkTrigger = 47U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn6ToPwm1ExtClkTrigger = 48U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn7ToPwm1ExtClkTrigger = 49U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn8ToPwm1ExtClkTrigger = 50U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn9ToPwm1ExtClkTrigger = 51U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToPwm1ExtClkTrigger = 52U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToPwm1ExtClkTrigger = 53U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToPwm1ExtClkTrigger = 54U + (PWM1_EXTCLKTRIG << PMUX_SHIFT), + + /*!< AOI0 trigger. */ + kINPUTMUX_PinInt0ToAoi0InTrigger = 0U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAoi0InTrigger = 1U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut0ToAoi0InTrigger = 2U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut1ToAoi0InTrigger = 3U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut2ToAoi0InTrigger = 4U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut3ToAoi0InTrigger = 5U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi0InTrigger = 6U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi0InTrigger = 7U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi0InTrigger = 8U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi0InTrigger = 9U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi0InTrigger = 10U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi0InTrigger = 11U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_CompOutToAoi0InTrigger = 12U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToAoi0InTrigger = 13U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToAoi0InTrigger = 14U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToAoi0InTrigger = 15U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAoi0InTrigger = 16U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi0InTrigger = 17U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi0InTrigger = 18U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi0InTrigger = 19U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi0InTrigger = 20U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi0InTrigger = 21U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi0InTrigger = 22U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi0InTrigger = 23U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToAoi0InTrigger = 24U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToAoi0InTrigger = 25U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToAoi0InTrigger = 26U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToAoi0InTrigger = 27U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToAoi0InTrigger = 28U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToAoi0InTrigger = 29U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToAoi0InTrigger = 30U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToAoi0InTrigger = 31U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToAoi0InTrigger = 32U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToAoi0InTrigger = 33U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToAoi0InTrigger = 34U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToAoi0InTrigger = 35U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToAoi0InTrigger = 36U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToAoi0InTrigger = 37U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToAoi0InTrigger = 38U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToAoi0InTrigger = 39U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToAoi0InTrigger = 40U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToAoi0InTrigger = 41U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToAoi0InTrigger = 42U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToAoi0InTrigger = 43U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToAoi0InTrigger = 44U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToAoi0InTrigger = 45U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToAoi0InTrigger = 46U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToAoi0InTrigger = 47U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToAoi0InTrigger = 48U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToAoi0InTrigger = 51U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToAoi0InTrigger = 52U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToAoi0InTrigger = 53U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout3ToAoi0InTrigger = 54U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout4ToAoi0InTrigger = 55U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout5ToAoi0InTrigger = 56U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout6ToAoi0InTrigger = 57U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma1Trigout0ToAoi0InTrigger = 58U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma1Trigout1ToAoi0InTrigger = 59U + (AOI0_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma1Trigout2ToAoi0InTrigger = 60U + (AOI0_IN0 << PMUX_SHIFT), + + /*!< AOI1 trigger. */ + kINPUTMUX_PinInt0ToAoi1InTrigger = 0U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAoi1InTrigger = 1U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut0ToAoi1InTrigger = 2U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut1ToAoi1InTrigger = 3U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut2ToAoi1InTrigger = 4U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_SctOut3ToAoi1InTrigger = 5U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi1InTrigger = 6U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi1InTrigger = 7U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi1InTrigger = 8U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi1InTrigger = 9U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi1InTrigger = 10U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi1InTrigger = 11U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_CompOutToAoi1InTrigger = 12U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToAoi1InTrigger = 13U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToAoi1InTrigger = 14U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToAoi1InTrigger = 15U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAoi1InTrigger = 16U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi1InTrigger = 17U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi1InTrigger = 18U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi1InTrigger = 19U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi1InTrigger = 20U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi1InTrigger = 21U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi1InTrigger = 22U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi1InTrigger = 23U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Hscmp0OutToAoi1InTrigger = 24U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Hscmp1OutToAoi1InTrigger = 25U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Hscmp2OutToAoi1InTrigger = 26U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig0ToAoi1InTrigger = 27U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig1ToAoi1InTrigger = 28U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig0ToAoi1InTrigger = 29U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig1ToAoi1InTrigger = 30U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig0ToAoi1InTrigger = 31U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig1ToAoi1InTrigger = 32U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig0ToAoi1InTrigger = 33U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig1ToAoi1InTrigger = 34U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig0ToAoi1InTrigger = 35U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig1ToAoi1InTrigger = 36U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig0ToAoi1InTrigger = 37U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig1ToAoi1InTrigger = 38U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig0ToAoi1InTrigger = 39U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig1ToAoi1InTrigger = 40U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig0ToAoi1InTrigger = 41U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig1ToAoi1InTrigger = 42U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToAoi1InTrigger = 43U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToAoi1InTrigger = 44U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn0ToAoi1InTrigger = 45U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn1ToAoi1InTrigger = 46U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn2ToAoi1InTrigger = 47U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_ExtTrigIn3ToAoi1InTrigger = 48U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToAoi1InTrigger = 51U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToAoi1InTrigger = 52U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToAoi1InTrigger = 53U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout3ToAoi1InTrigger = 54U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout4ToAoi1InTrigger = 55U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout5ToAoi1InTrigger = 56U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout6ToAoi1InTrigger = 57U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma1Trigout0ToAoi1InTrigger = 58U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma1Trigout1ToAoi1InTrigger = 59U + (AOI1_IN0 << PMUX_SHIFT), + kINPUTMUX_Dma1Trigout2ToAoi1InTrigger = 60U + (AOI1_IN0 << PMUX_SHIFT), + + /*!< AOI External trigger. */ + kINPUTMUX_PinInt0ToAoiExtTrigger = 0U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAoiExtTrigger = 1U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToAoiExtTrigger = 2U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToAoiExtTrigger = 3U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAoiExtTrigger = 4U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoiExtTrigger = 5U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToAoiExtTrigger = 6U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToAoiExtTrigger = 7U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToAoiExtTrigger = 8U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToAoiExtTrigger = 9U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToAoiExtTrigger = 10U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToAoiExtTrigger = 11U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToAoiExtTrigger = 12U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToAoiExtTrigger = 13U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToAoiExtTrigger = 14U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToAoiExtTrigger = 15U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAoiExtTrigger = 16U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAoiExtTrigger = 17U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAoiExtTrigger = 18U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAoiExtTrigger = 19U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAoiExtTrigger = 20U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAoiExtTrigger = 21U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAoiExtTrigger = 22U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAoiExtTrigger = 23U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + kINPUTMUX_TmprOutToAoiExtTrigger = 24U + (AOI_EXT_TRIG0 << PMUX_SHIFT), + + /*!< HSCMP1 trigger. */ + kINPUTMUX_PinInt0ToHscmp1Trigger = 0U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_PinInt7ToHscmp1Trigger = 1U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut4ToHscmp1Trigger = 2U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut5ToHscmp1Trigger = 3U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut7ToHscmp1Trigger = 4U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToHscmp1Trigger = 5U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToHscmp1Trigger = 6U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToHscmp1Trigger = 7U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToHscmp1Trigger = 8U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToHscmp1Trigger = 9U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_ArmTxevToHscmp1Trigger = 11U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToHscmp1Trigger = 12U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToHscmp1Trigger = 13U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToHscmp1Trigger = 14U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToHscmp1Trigger = 17U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToHscmp1Trigger = 18U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToHscmp1Trigger = 19U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToHscmp1Trigger = 20U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToHscmp1Trigger = 21U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToHscmp1Trigger = 22U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToHscmp1Trigger = 23U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToHscmp1Trigger = 24U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToHscmp1Trigger = 25U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToHscmp1Trigger = 26U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToHscmp1Trigger = 27U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToHscmp1Trigger = 28U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToHscmp1Trigger = 29U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToHscmp1Trigger = 30U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToHscmp1Trigger = 31U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToHscmp1Trigger = 32U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToHscmp1Trigger = 33U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToHscmp1Trigger = 34U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToHscmp1Trigger = 35U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToHscmp1Trigger = 36U + (HSCMP1_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToHscmp1Trigger = 37U + (HSCMP1_TRIGIN << PMUX_SHIFT), + + /*!< HSCMP2 trigger. */ + kINPUTMUX_PinInt0ToHscmp2Trigger = 0U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_PinInt4ToHscmp2Trigger = 1U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut4ToHscmp2Trigger = 2U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut5ToHscmp2Trigger = 3U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_SctOut8ToHscmp2Trigger = 4U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToHscmp2Trigger = 5U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToHscmp2Trigger = 6U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToHscmp2Trigger = 7U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToHscmp2Trigger = 8U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToHscmp2Trigger = 9U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_ArmTxevToHscmp2Trigger = 11U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToHscmp2Trigger = 12U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToHscmp2Trigger = 13U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToHscmp2Trigger = 14U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0MuxTrig01ToHscmp2Trigger = 17U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1MuxTrig01ToHscmp2Trigger = 18U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2MuxTrig01ToHscmp2Trigger = 19U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3MuxTrig01ToHscmp2Trigger = 20U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0MuxTrig01ToHscmp2Trigger = 21U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1MuxTrig01ToHscmp2Trigger = 22U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2MuxTrig01ToHscmp2Trigger = 23U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3MuxTrig01ToHscmp2Trigger = 24U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc0CmpPosMatchToHscmp2Trigger = 25U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Enc1CmpPosMatchToHscmp2Trigger = 26U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToHscmp2Trigger = 27U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToHscmp2Trigger = 28U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToHscmp2Trigger = 29U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToHscmp2Trigger = 30U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToHscmp2Trigger = 31U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToHscmp2Trigger = 32U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToHscmp2Trigger = 33U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToHscmp2Trigger = 34U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout0ToHscmp2Trigger = 35U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout1ToHscmp2Trigger = 36U + (HSCMP2_TRIGIN << PMUX_SHIFT), + kINPUTMUX_Dma0Trigout2ToHscmp2Trigger = 37U + (HSCMP2_TRIGIN << PMUX_SHIFT), + +} inputmux_connection_t; + +/*! @brief INPUTMUX signal enable/disable type */ +typedef enum _inputmux_signal_t +{ + /*!< DMA0 REQ(DMA0_REQEN0) signal. */ + kINPUTMUX_FlexSpiRxToDmac0Ch0RequestEna = 0U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_FlexSpiTxToDmac0Ch1RequestEna = 1U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_PinInt0ToDmac0Ch2RequestEna = 2U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_PinInt1ToDmac0Ch3RequestEna = 3U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_PinInt2ToDmac0Ch4RequestEna = 4U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_PinInt3ToDmac0Ch5RequestEna = 5U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDmac0Ch6RequestEna = 6U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDmac0Ch7RequestEna = 7U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDmac0Ch8RequestEna = 8U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDmac0Ch9RequestEna = 9U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDmac0Ch10RequestEna = 10U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDmac0Ch11RequestEna = 11U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDmac0Ch12RequestEna = 12U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDmac0Ch13RequestEna = 13U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDmac0Ch14RequestEna = 14U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDmac0Ch15RequestEna = 15U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_CompOutToDmac0Ch16RequestEna = 16U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_OtrigAToDmac0Ch17RequestEna = 17U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_OtrigBToDmac0Ch18RequestEna = 18U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_OtrigCToDmac0Ch19RequestEna = 19U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_OtrigDToDmac0Ch20RequestEna = 20U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_SctDma0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_SctDma1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Adc0Tcomp0ToDmac23Ch0RequestEna = 23U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Adc1Tcomp0ToDmac24Ch0RequestEna = 24U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Hscmp0ToDmac0Ch25RequestEna = 25U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Hscmp1ToDmac0Ch26RequestEna = 26U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Hscmp2ToDmac0Ch27RequestEna = 27U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Aoi0Out0ToDmac0Ch28RequestEna = 28U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Aoi0Out1ToDmac0Ch29RequestEna = 29U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Aoi0Out2ToDmac0Ch30RequestEna = 30U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + kINPUTMUX_Aoi0Out3ToDmac0Ch31RequestEna = 31U + (DMA0_REQ_EN0_ID << ENA_SHIFT), + + /*!< DMA0 REQ(DMA0_REQEN0) signal. */ + kINPUTMUX_Aoi1Out0ToDmac0Ch32RequestEna = 0U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_Aoi1Out1ToDmac0Ch33RequestEna = 1U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_Aoi1Out2ToDmac0Ch34RequestEna = 2U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_Aoi1Out3ToDmac0Ch35RequestEna = 3U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDmac0Ch36RequestEna = 4U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDmac0Ch37RequestEna = 5U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDmac0Ch38RequestEna = 6U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDmac0Ch39RequestEna = 7U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDmac0Ch40RequestEna = 8U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDmac0Ch41RequestEna = 9U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDmac0Ch42RequestEna = 10U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDmac0Ch43RequestEna = 11U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDmac0Ch44RequestEna = 12U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDmac0Ch45RequestEna = 13U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDmac0Ch46RequestEna = 14U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDmac0Ch47RequestEna = 15U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDmac0Ch48RequestEna = 16U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDmac0Ch49RequestEna = 17U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDmac0Ch50RequestEna = 18U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDmac0Ch51RequestEna = 19U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + kINPUTMUX_TmprOutToDmac0Ch52RequestEna = 20U + (DMA0_REQ_EN1_ID << ENA_SHIFT), + + /*!< DMA1 REQ(DMA1_REQEN) signal. */ + kINPUTMUX_HsLspiRxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_HsLspiTxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Flexcom0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Flexcom0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Flexcom1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Flexcom1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Flexcom3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Flexcom3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmic0Ch0ToDmac1Ch10RequestEna = 10U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmic0Ch1ToDmac1Ch11RequestEna = 11U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_I3c0RxToDmac1Ch12RequestEna = 12U + (DMA1_REQ_EN_ID << ENA_SHIFT), + kINPUTMUX_I3c0TxToDmac1Ch13RequestEna = 13U + (DMA1_REQ_EN_ID << ENA_SHIFT), + + /*!< DMA0 input trigger(DMA0_ITRIGEN0) source enable. */ + kINPUTMUX_Dmac0InputTriggerFlexSpiRxEna = 0U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexSpiTxEna = 1U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPinInt0Ena = 2U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPinInt1Ena = 3U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPinInt2Ena = 4U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPinInt3Ena = 5U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 6U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 7U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 8U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 9U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 10U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 11U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 12U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 13U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 14U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 15U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCompOutEna = 16U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerOtrigAEna = 17U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerOtrigBEna = 18U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerOtrigCEna = 19U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerOtrigDEna = 20U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerSctDma0Ena = 21U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerSctDma1Ena = 22U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAdc0Tcomp0Ena = 23U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAdc1Tcomp0Ena = 24U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerHscmp0Ena = 25U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerHscmp1Ena = 26U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerHscmp2Ena = 27U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi0Out0Ena = 28U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi0Out1Ena = 29U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi0Out2Ena = 30U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi0Out3Ena = 31U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), + + /*!< DMA0 input trigger(DMA0_ITRIGEN1) source enable. */ + kINPUTMUX_Dmac0InputTriggerAoi1Out0Ena = 0U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi1Out1Ena = 1U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi1Out2Ena = 2U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerAoi1Out3Ena = 3U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt0Ena = 4U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt1Ena = 5U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt2Ena = 6U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqCapt3Ena = 7U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal0Ena = 8U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal1Ena = 9U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal2Ena = 10U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm0ReqVal3Ena = 11U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt0Ena = 12U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt1Ena = 13U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt2Ena = 14U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqCapt3Ena = 15U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal0Ena = 16U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal1Ena = 17U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal2Ena = 18U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerFlexPwm1ReqVal3Ena = 19U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerTmprOutEna = 20U + (DMA0_ITRIG_EN1_ID << ENA_SHIFT), + + /*!< DMA1 input trigger(DMA1_ITRIGEN) source enable. */ + kINPUTMUX_Dmac1InputTriggerHsLspiRxEna = 2U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerHsLspiTxEna = 3U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerFlexcom0RxEna = 4U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerFlexcom0TxEna = 5U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerFlexcom1RxEna = 6U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerFlexcom1TxEna = 7U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerFlexcom3RxEna = 8U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerFlexcom3TxEna = 9U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDmic0Ch0Ena = 10U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDmic0Ch1Ena = 11U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerI3c0RxEna = 12U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerI3c0TxEna = 13U + (DMA1_ITRIG_EN_ID << ENA_SHIFT), +} inputmux_signal_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_iocon.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_iocon.h new file mode 100644 index 0000000000000000000000000000000000000000..e705e91f66c4843139565872e9ad49c21b769bb2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_iocon.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint8_t port; /* Pin port */ + uint8_t pin; /* Pin number */ + uint8_t ionumber; /* IO number */ + uint16_t modefunc; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.c new file mode 100644 index 0000000000000000000000000000000000000000..8c194af9329aad3d53407357313236fef8c40690 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.c @@ -0,0 +1,655 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_irtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.irtc" +#endif + +#define IRTC_BASE_YEAR (2112U) +#define YEAR_RANGE_START (1984U) /* Valid values for year range from -128 to 127; 2112 - 128 */ +#define YEAR_RANGE_END (2239U) /* Valid values for year range from -128 to 127; 2112 + 127 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + bool fgRet = true; + + /* Table of days in a month for a non leap year */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->weekDay >= 7U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || + (datetime->second >= 60U)) + { + /* If not correct then error*/ + fgRet = false; + } + else + { + /* Adjust the days in February for a leap year */ + if (((0U == (datetime->year & 3U)) && (0U != (datetime->year % 100U))) || (0U == (datetime->year % 400U))) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + fgRet = false; + } + } + return fgRet; +} + +/*! + * brief Ungates the IRTC clock and configures the peripheral for basic operation. + * + * This function initiates a soft-reset of the IRTC module, this has not effect on DST, + * calendaring, standby time and tamper detect registers. + * + * note This API should be called at the beginning of the application using the IRTC driver. + * + * param base IRTC peripheral base address + * param config Pointer to user's IRTC config structure. + * + * return kStatus_Fail if we cannot disable register write protection + */ +status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) +{ + assert(NULL != config); + + uint16_t reg; + status_t status = kStatus_Success; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Rtc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET + RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); +#endif + + /* Unlock to allow register write operation */ + if (kStatus_Success == IRTC_SetWriteProtection(base, false)) + { + /* Issue a software reset */ + IRTC_Reset(base); + +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + /* Setup the wakeup pin select */ + if (config->wakeupSelect) + { + base->CTRL2 |= RTC_CTRL2_WAKEUP_MODE_MASK; + } + else + { + base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; + } +#endif + /* Setup alarm match operation and sampling clock operation in standby mode */ + reg = base->CTRL; + reg &= ~((uint16_t)RTC_CTRL_TIMER_STB_MASK_MASK | (uint16_t)RTC_CTRL_ALM_MATCH_MASK); + reg |= (RTC_CTRL_TIMER_STB_MASK(config->timerStdMask) | RTC_CTRL_ALM_MATCH(config->alrmMatch)); + base->CTRL = reg; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Fill in the IRTC config struct with the default settings + * + * The default values are: + * code + * config->wakeupSelect = true; + * config->timerStdMask = false; + * config->alrmMatch = kRTC_MatchSecMinHr; + * endcode + * param config Pointer to user's IRTC config structure. + */ +void IRTC_GetDefaultConfig(irtc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + /* Tamper pin 0 is used as a wakeup/hibernation pin */ + config->wakeupSelect = true; +#endif + + /* Sampling clock are not gated when in standby mode */ + config->timerStdMask = false; + + /* Only seconds, minutes and hours are matched when generating an alarm */ + config->alrmMatch = kRTC_MatchSecMinHr; +} + +/*! + * brief Sets the IRTC date and time according to the given time structure. + * + * The IRTC counter is started after the time is set. + * + * param base IRTC peripheral base address + * param datetime Pointer to structure where the date and time details to set are stored + * + * return kStatus_Success: success in setting the time and starting the IRTC + * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. + */ +status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + status_t status = kStatus_Success; + + /* Return error if the time provided is not valid */ + if (IRTC_CheckDatetimeFormat(datetime)) + { + /* The register stores the offset in years from the base year of 2112 */ + if (datetime->year < IRTC_BASE_YEAR) + { + /* Values for years less than the base year range from -128 to 1 */ + base->YEARMON = + RTC_YEARMON_YROFST(0x100U + datetime->year - IRTC_BASE_YEAR) | RTC_YEARMON_MON_CNT(datetime->month); + } + else + { + /* Values for years greater or equal to the base year range from 0 to 127 */ + base->YEARMON = RTC_YEARMON_YROFST(datetime->year - IRTC_BASE_YEAR) | RTC_YEARMON_MON_CNT(datetime->month); + } + /* Update the Day Count and Day of the week field */ + base->DAYS = RTC_DAYS_DOW(datetime->weekDay) | RTC_DAYS_DAY_CNT(datetime->day); + + /* Update hour and minute field */ + base->HOURMIN = RTC_HOURMIN_HOUR_CNT(datetime->hour) | RTC_HOURMIN_MIN_CNT(datetime->minute); + + /* Update the seconds register */ + base->SECONDS = RTC_SECONDS_SEC_CNT(datetime->second); + } + else + { + status = kStatus_InvalidArgument; + } + + return status; +} + +/*! + * brief Gets the IRTC time and stores it in the given time structure. + * + * param base IRTC peripheral base address + * param datetime Pointer to structure where the date and time details are stored. + */ +void IRTC_GetDatetime(RTC_Type *base, irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + uint16_t temp = base->YEARMON; + + datetime->year = + (uint16_t)IRTC_BASE_YEAR + (uint16_t)((int8_t)(uint8_t)((temp >> RTC_YEARMON_YROFST_SHIFT) & 0xFFU)); + datetime->month = (uint8_t)temp & RTC_YEARMON_MON_CNT_MASK; + + temp = base->DAYS; + datetime->weekDay = (uint8_t)((temp & RTC_DAYS_DOW_MASK) >> RTC_DAYS_DOW_SHIFT); + datetime->day = (uint8_t)temp & RTC_DAYS_DAY_CNT_MASK; + + temp = base->HOURMIN; + datetime->hour = (uint8_t)((temp & RTC_HOURMIN_HOUR_CNT_MASK) >> RTC_HOURMIN_HOUR_CNT_SHIFT); + datetime->minute = (uint8_t)temp & RTC_HOURMIN_MIN_CNT_MASK; + + datetime->second = (uint8_t)(base->SECONDS) & RTC_SECONDS_SEC_CNT_MASK; +} + +/*! + * brief Sets the IRTC alarm time + * + * param base RTC peripheral base address + * param alarmTime Pointer to structure where the alarm time is stored. + * + * note weekDay field of alarmTime is not used during alarm match and should be set to 0 + * + * return kStatus_Success: success in setting the alarm + * kStatus_InvalidArgument: error in setting the alarm. Error occurs because the alarm + * datetime format is incorrect. + */ +status_t IRTC_SetAlarm(RTC_Type *base, const irtc_datetime_t *alarmTime) +{ + assert(NULL != alarmTime); + + status_t status = kStatus_Success; + + /* Return error if the alarm time provided is not valid */ + if (IRTC_CheckDatetimeFormat(alarmTime)) + { + /* Set the alarm year */ + if (alarmTime->year < IRTC_BASE_YEAR) + { + base->ALM_YEARMON = RTC_ALM_YEARMON_ALM_YEAR(0x100U + alarmTime->year - IRTC_BASE_YEAR) | + RTC_ALM_YEARMON_ALM_MON(alarmTime->month); + } + else + { + base->ALM_YEARMON = + RTC_ALM_YEARMON_ALM_YEAR(alarmTime->year - IRTC_BASE_YEAR) | RTC_ALM_YEARMON_ALM_MON(alarmTime->month); + } + + /* Set the alarm day */ + base->ALM_DAYS = RTC_ALM_DAYS_ALM_DAY(alarmTime->day); + + /* Set the alarm hour and minute */ + base->ALM_HOURMIN = RTC_ALM_HOURMIN_ALM_HOUR(alarmTime->hour) | RTC_ALM_HOURMIN_ALM_MIN(alarmTime->minute); + + /* Set the alarm seconds */ + base->ALM_SECONDS = RTC_ALM_SECONDS_ALM_SEC(alarmTime->second); + } + else + { + status = kStatus_InvalidArgument; + } + + return status; +} + +/*! + * brief Returns the IRTC alarm time. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the alarm date and time details are stored. + */ +void IRTC_GetAlarm(RTC_Type *base, irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + uint16_t temp = base->ALM_YEARMON; + + datetime->year = + (uint16_t)IRTC_BASE_YEAR + (uint16_t)((int8_t)(uint8_t)((temp >> RTC_ALM_YEARMON_ALM_YEAR_SHIFT) & 0xFFU)); + datetime->month = (uint8_t)temp & RTC_ALM_YEARMON_ALM_MON_MASK; + + datetime->day = (uint8_t)(base->ALM_DAYS) & RTC_ALM_DAYS_ALM_DAY_MASK; + + temp = base->ALM_HOURMIN; + datetime->hour = (uint8_t)((temp & RTC_ALM_HOURMIN_ALM_HOUR_MASK) >> RTC_ALM_HOURMIN_ALM_HOUR_SHIFT); + datetime->minute = (uint8_t)temp & RTC_ALM_HOURMIN_ALM_MIN_MASK; + + datetime->second = (uint8_t)(base->ALM_SECONDS) & RTC_ALM_SECONDS_ALM_SEC_MASK; +} + +/*! + * brief Locks or unlocks IRTC registers for write access. + * + * note When the registers are unlocked, they remain in unlocked state for + * 2 seconds, after which they are locked automatically. After + * power-on-reset, the registers come out unlocked and they are locked + * automatically 15 seconds after power on. + * + * param base IRTC peripheral base address + * param lock true: Lock IRTC registers; false: Unlock IRTC registers. + * + * return kStatus_Success: if lock or unlock operation is successful + * kStatus_Fail: if lock or unlock operation fails even after multiple retry attempts + */ +status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock) +{ + /* Retry before giving up */ + uint8_t repeatProtectSequence = 0xFFU; + status_t status = kStatus_Success; + + if (!lock) + { + /* Unlock IRTC registers */ + while ((0U != (base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK)) && (0U != repeatProtectSequence)) + { + /* Access in 8-bit mode while storing the value */ + *(__IO uint8_t *)(&base->STATUS) = 0U; + *(__IO uint8_t *)(&base->STATUS) = 0x40U; + *(__IO uint8_t *)(&base->STATUS) = 0xC0U; + *(__IO uint8_t *)(&base->STATUS) = 0x80U; + repeatProtectSequence--; + } + } + else + { + /* Lock IRTC registers */ + while ((0U == ((base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK) >> RTC_STATUS_WRITE_PROT_EN_SHIFT)) && + (0U != repeatProtectSequence)) + { + *(__IO uint8_t *)(&base->STATUS) = 0x80U; + repeatProtectSequence--; + } + } + + /* Lock/unlock was not successful even after trying 256 times */ + if (0U == repeatProtectSequence) + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Sets the IRTC daylight savings start and stop date and time. + * + * It also enables the daylight saving bit in the IRTC control register + * + * param base IRTC peripheral base address + * param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime) +{ + assert(NULL != datetime); + + /* Disable daylight saving time */ + base->CTRL &= ~(uint16_t)RTC_CTRL_DST_EN_MASK; + + /* Set the daylight saving time start month and end month value */ + base->DST_MONTH = + RTC_DST_MONTH_DST_START_MONTH(datetime->startMonth) | RTC_DST_MONTH_DST_END_MONTH(datetime->endMonth); + + /* Set the daylight saving time start day and end day value */ + base->DST_DAY = RTC_DST_DAY_DST_START_DAY(datetime->startDay) | RTC_DST_DAY_DST_END_DAY(datetime->endDay); + + /* Set the daylight saving time start hour and end hour value */ + base->DST_HOUR = RTC_DST_HOUR_DST_START_HOUR(datetime->startHour) | RTC_DST_HOUR_DST_END_HOUR(datetime->endHour); + + /* Enable daylight saving time */ + base->CTRL |= RTC_CTRL_DST_EN_MASK; +} + +/*! + * brief Gets the IRTC daylight savings time and stores it in the given time structure. + * + * param base IRTC peripheral base address + * param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime) +{ + assert(NULL != datetime); + + uint16_t temp = base->DST_MONTH; + + /* Get the daylight savings time start and end month value */ + datetime->startMonth = + (uint8_t)((temp & RTC_DST_MONTH_DST_START_MONTH_MASK) >> RTC_DST_MONTH_DST_START_MONTH_SHIFT); + datetime->endMonth = (uint8_t)((temp & RTC_DST_MONTH_DST_END_MONTH_MASK) >> RTC_DST_MONTH_DST_END_MONTH_SHIFT); + + /* Get the daylight savings time start and end day value */ + temp = base->DST_DAY; + datetime->startDay = (uint8_t)((temp & RTC_DST_DAY_DST_START_DAY_MASK) >> RTC_DST_DAY_DST_START_DAY_SHIFT); + datetime->endDay = (uint8_t)((temp & RTC_DST_DAY_DST_END_DAY_MASK) >> RTC_DST_DAY_DST_END_DAY_SHIFT); + + /* Get the daylight savings time start and end hour value */ + temp = base->DST_HOUR; + datetime->startHour = (uint8_t)((temp & RTC_DST_HOUR_DST_START_HOUR_MASK) >> RTC_DST_HOUR_DST_START_HOUR_SHIFT); + datetime->endHour = (uint8_t)((temp & RTC_DST_HOUR_DST_END_HOUR_MASK) >> RTC_DST_HOUR_DST_END_HOUR_SHIFT); +} + +/*! + * brief Enables the coarse compensation and sets the value in the IRTC compensation register. + * + * param base IRTC peripheral base address + * param compensationValue Compensation value is a 2's complement value. + * param compensationInterval Compensation interval. + */ +void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8_t compensationInterval) +{ + uint16_t reg; + + /* Set the compensation value and interval */ + base->COMPEN = (uint16_t)compensationValue | ((uint16_t)compensationInterval << 8U); + + /* Disable fine and enable coarse compensation */ + reg = base->CTRL; + reg &= ~(uint16_t)RTC_CTRL_FINEEN_MASK; + reg |= RTC_CTRL_COMP_EN_MASK; + base->CTRL = reg; +} + +/*! + * brief Enables the fine compensation and sets the value in the IRTC compensation register. + * + * param base The IRTC peripheral base address + * param integralValue Compensation integral value; twos complement value of the integer part + * param fractionValue Compensation fraction value expressed as number of clock cycles of a + * fixed 4.194304Mhz clock that have to be added. + * param accumulateFractional Flag indicating if we want to add to previous fractional part; + * true: Add to previously accumulated fractional part, + * false: Start afresh and overwrite current value + */ +void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional) +{ + if (!accumulateFractional) + { + /* Disable compensation to clear previous accumulated fractional part */ + base->CTRL &= ~(((uint16_t)1U << RTC_CTRL_COMP_EN_SHIFT) | ((uint16_t)1U << RTC_CTRL_FINEEN_SHIFT)); + } + + /* Set the compensation fractional and integral parts */ + base->COMPEN = ((uint16_t)fractionValue & 0x7FU) | (((uint16_t)integralValue & 0xFU) << 12U); + /* Enable fine compensation */ + base->CTRL |= (RTC_CTRL_COMP_EN_MASK | RTC_CTRL_FINEEN_MASK); +} + +/*! + * brief This function allows configuring the four tamper inputs. + * + * The function configures the filter properties for the three external tampers. + * It also sets up active/passive and direction of the tamper bits, which are not available + * on all platforms. + * note This function programs the tamper filter parameters. The user must gate the 32K clock to + * the RTC before calling this function. It is assumed that the time and date are set after this + * and the tamper parameters do not require to be changed again later. + * + * param base The IRTC peripheral base address + * param tamperNumber The IRTC tamper input to configure + * param tamperConfig The IRTC tamper properties + */ +void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const irtc_tamper_config_t *tamperConfig) +{ + assert(NULL != tamperConfig); + + uint16_t reg = 0; + +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION) && (FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION) + reg = base->TAMPER_DIRECTION; + /* Set whether tamper pin is active or passive */ + if (tamperConfig->activePassive) + { + /* In case of active tamper, set the direction */ + reg |= (1U << tamperNumber); + if (tamperConfig->direction) + { + /* Tamper direction is output */ + reg |= (1U << (RTC_TAMPER_DIRECTION_I_O_TAMP_SHIFT + tamperNumber)); + } + else + { + /* Tamper direction is input */ + reg &= ~(1U << (RTC_TAMPER_DIRECTION_I_O_TAMP_SHIFT + tamperNumber)); + } + } + else + { + /* Passive tampers are input only and the direction bit is read only in this case */ + reg &= ~(1U << tamperNumber); + } + base->TAMPER_DIRECTION = reg; +#endif /* FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION */ + + /* Set the filter properties for the external tamper pins */ + switch (tamperNumber) + { + case kIRTC_Tamper_0: + /* Set the pin for Tamper 0 */ +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; +#endif + reg = base->FILTER01_CFG; + reg &= ~((uint16_t)RTC_FILTER01_CFG_POL0_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR0_MASK | + (uint16_t)RTC_FILTER01_CFG_CLK_SEL0_MASK); + reg |= (RTC_FILTER01_CFG_POL0(tamperConfig->pinPolarity) | + RTC_FILTER01_CFG_FIL_DUR0(tamperConfig->filterDuration) | + RTC_FILTER01_CFG_CLK_SEL0(tamperConfig->filterClk)); + base->FILTER01_CFG = reg; + break; + case kIRTC_Tamper_1: + reg = base->FILTER01_CFG; + reg &= ~((uint16_t)RTC_FILTER01_CFG_POL1_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR1_MASK | + (uint16_t)RTC_FILTER01_CFG_CLK_SEL1_MASK); + reg |= (RTC_FILTER01_CFG_POL1(tamperConfig->pinPolarity) | + RTC_FILTER01_CFG_FIL_DUR1(tamperConfig->filterDuration) | + RTC_FILTER01_CFG_CLK_SEL1(tamperConfig->filterClk)); + base->FILTER01_CFG = reg; + break; +#if defined(FSL_FEATURE_RTC_HAS_FILTER23_CFG) && FSL_FEATURE_RTC_HAS_FILTER23_CFG + case kIRTC_Tamper_2: + reg = base->FILTER23_CFG; + reg &= ~((uint16_t)RTC_FILTER23_CFG_POL2_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR2_MASK | + (uint16_t)RTC_FILTER23_CFG_CLK_SEL2_MASK); + reg |= (RTC_FILTER23_CFG_POL2(tamperConfig->pinPolarity) | + RTC_FILTER23_CFG_FIL_DUR2(tamperConfig->filterDuration) | + RTC_FILTER23_CFG_CLK_SEL2(tamperConfig->filterClk)); + base->FILTER23_CFG = reg; + break; + case kIRTC_Tamper_3: + reg = base->FILTER23_CFG; + reg &= ~((uint16_t)RTC_FILTER23_CFG_POL3_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR3_MASK | + (uint16_t)RTC_FILTER23_CFG_CLK_SEL3_MASK); + reg |= (RTC_FILTER23_CFG_POL3(tamperConfig->pinPolarity) | + RTC_FILTER23_CFG_FIL_DUR3(tamperConfig->filterDuration) | + RTC_FILTER23_CFG_CLK_SEL3(tamperConfig->filterClk)); + base->FILTER23_CFG = reg; + break; +#else + case kIRTC_Tamper_2: + reg = base->FILTER2_CFG; + reg &= ~((uint16_t)RTC_FILTER2_CFG_POL2_MASK | (uint16_t)RTC_FILTER2_CFG_FIL_DUR2_MASK | + (uint16_t)RTC_FILTER2_CFG_CLK_SEL2_MASK); + reg |= (RTC_FILTER2_CFG_POL2(tamperConfig->pinPolarity) | + RTC_FILTER2_CFG_FIL_DUR2(tamperConfig->filterDuration) | + RTC_FILTER2_CFG_CLK_SEL2(tamperConfig->filterClk)); + base->FILTER2_CFG = reg; + break; +#endif + + default: + /* Internal tamper, does not have filter configuration. */ + break; + } +} + +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + +/*! + * brief This function reads the tamper timestamp and returns the associated tamper pin. + * + * The tamper timestamp has month, day, hour, minutes, and seconds. Ignore the year field as this + * information is not available in the tamper queue. The user should look at the RTC_YEARMON register + * for this because the expectation is that the queue is read at least once a year. + * Return the tamper pin number associated with the timestamp. + * + * param base The IRTC peripheral base address + * param tamperTimestamp The tamper timestamp + * + * return The tamper pin number + */ +uint8_t IRTC_ReadTamperQueue(RTC_Type *base, irtc_datetime_t *tamperTimestamp) +{ + assert(NULL != tamperTimestamp); + + /* Read the register 2 times to get a entry*/ + uint16_t temp1 = base->TAMPER_QUEUE; + uint16_t temp2 = base->TAMPER_QUEUE; + uint8_t tamperNum; + + /* + * Tamper queue does not store the year field as this value can be read from RTC_YEARMON. + * It is expected that the queue will be read at least once in a year. + */ + tamperTimestamp->year = 0; + /* From the first read; TAMPER_DATA[4:0] is the hour field */ + tamperTimestamp->hour = (uint8_t)temp1 & 0x1FU; + /* From the first read; TAMPER_DATA[9:5] is the day field */ + tamperTimestamp->day = (uint8_t)(temp1 >> 5U) & 0x1FU; + /* From the first read; TAMPER_DATA[13:10] is the month field */ + tamperTimestamp->month = (uint8_t)(temp1 >> 10U) & 0xFU; + + /* From the second read; TAMPER_DATA[5:0] is the seconds field */ + tamperTimestamp->second = (uint8_t)temp2 & 0x3FU; + /* From the second read; TAMPER_DATA[11:6] is the minutes field */ + tamperTimestamp->minute = (uint8_t)(temp2 >> 6U) & 0x3FU; + /* From the second read; TAMPER_DATA[14:12] is the tamper index */ + tamperNum = (uint8_t)(temp2 >> 12U) & 0x7U; + + return tamperNum; +} + +#endif /* FSL_FEATURE_RTC_HAS_TAMPER_QUEUE */ + +/*! + * brief Select which clock to output from RTC. + * + * Select which clock to output from RTC for other modules to use inside SoC, for example, + * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. + * + * param base IRTC peripheral base address + * param cloOut select clock to use for output + */ +void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut) +{ + uint16_t ctrlVal = base->CTRL; + + ctrlVal &= ~RTC_CTRL_CLKOUT_MASK; + + ctrlVal |= RTC_CTRL_CLKOUT((uint16_t)clkOut); + if (clkOut == kIRTC_ClkoutCoarse1Hz) + { + ctrlVal |= RTC_CTRL_COMP_EN_MASK; + } + else if (clkOut == kIRTC_ClkoutFine1Hz) + { + ctrlVal |= RTC_CTRL_FINEEN_MASK; + } + else + { + /* empty else */ + } + + base->CTRL = ctrlVal; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.h new file mode 100644 index 0000000000000000000000000000000000000000..4f73f23894eda57114cc6b13af03c8738b7db11d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_irtc.h @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IRTC_H_ +#define _FSL_IRTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup irtc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version. */ +/*@}*/ + +/*! @brief IRTC filter clock source options. */ +typedef enum _irtc_filter_clock_source +{ + kIRTC_32K = 0x0U, /*!< Use 32 kHz clock source for the tamper filter.*/ + kIRTC_512 = 0x1U, /*!< Use 512 Hz clock source for the tamper filter.*/ + kIRTC_128 = 0x2U, /*!< Use 128 Hz clock source for the tamper filter.*/ + kIRTC_64 = 0x3U, /*!< Use 64 Hz clock source for the tamper filter.*/ + kIRTC_16 = 0x4U, /*!< Use 16 Hz clock source for the tamper filter.*/ + kIRTC_8 = 0x5U, /*!< Use 8 Hz clock source for the tamper filter.*/ + kIRTC_4 = 0x6U, /*!< Use 4 Hz clock source for the tamper filter.*/ + kIRTC_2 = 0x7U /*!< Use 2 Hz clock source for the tamper filter.*/ +} irtc_filter_clock_source_t; + +/*! @brief IRTC Tamper pins. */ +typedef enum _irtc_tamper_pins +{ + kIRTC_Tamper_0 = 0U, /*!< External Tamper 0 */ + kIRTC_Tamper_1, /*!< External Tamper 1 */ + kIRTC_Tamper_2, /*!< External Tamper 2 */ + kIRTC_Tamper_3 /*!< Internal tamper, does not have filter configuration */ +} irtc_tamper_pins_t; + +/*! @brief List of IRTC interrupts */ +typedef enum _irtc_interrupt_enable +{ + kIRTC_TamperInterruptEnable = RTC_IER_TAMPER_IE_MASK, /*!< Tamper Interrupt Enable */ + kIRTC_AlarmInterruptEnable = RTC_IER_ALM_IE_MASK, /*!< Alarm Interrupt Enable */ + kIRTC_DayInterruptEnable = RTC_IER_DAY_IE_MASK, /*!< Days Interrupt Enable */ + kIRTC_HourInterruptEnable = RTC_IER_HOUR_IE_MASK, /*!< Hours Interrupt Enable */ + kIRTC_MinInterruptEnable = RTC_IER_MIN_IE_MASK, /*!< Minutes Interrupt Enable */ + kIRTC_1hzInterruptEnable = RTC_IER_IE_1HZ_MASK, /*!< 1 Hz interval Interrupt Enable */ + kIRTC_2hzInterruptEnable = RTC_IER_IE_2HZ_MASK, /*!< 2 Hz interval Interrupt Enable */ + kIRTC_4hzInterruptEnable = RTC_IER_IE_4HZ_MASK, /*!< 4 Hz interval Interrupt Enable */ + kIRTC_8hzInterruptEnable = RTC_IER_IE_8HZ_MASK, /*!< 8 Hz interval Interrupt Enable */ + kIRTC_16hzInterruptEnable = RTC_IER_IE_16HZ_MASK, /*!< 16 Hz interval Interrupt Enable */ + kIRTC_32hzInterruptEnable = RTC_IER_IE_32HZ_MASK, /*!< 32 Hz interval Interrupt Enable */ + kIRTC_64hzInterruptEnable = RTC_IER_IE_64HZ_MASK, /*!< 64 Hz interval Interrupt Enable */ + kIRTC_128hzInterruptEnable = RTC_IER_IE_128HZ_MASK, /*!< 128 Hz interval Interrupt Enable */ + kIRTC_256hzInterruptEnable = RTC_IER_IE_256HZ_MASK, /*!< 256 Hz interval Interrupt Enable */ + kIRTC_512hzInterruptEnable = RTC_IER_IE_512HZ_MASK, /*!< 512 Hz interval Interrupt Enable */ +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + kIRTC_WakeTimerInterruptEnable = (RTC_WAKE_TIMER_CTRL_INTR_EN_MASK << 16U), /*!< Wake timer Interrupt Enable */ +#endif +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE + kIRTC_TamperQueueFullInterruptEnable = + (RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK << 24U), /*!< Tamper queue full Interrupt Enable */ +#endif +} irtc_interrupt_enable_t; + +/*! @brief List of IRTC flags */ +typedef enum _irtc_status_flags +{ + kIRTC_TamperFlag = RTC_ISR_TAMPER_IS_MASK, /*!< Tamper Status flag*/ + kIRTC_AlarmFlag = RTC_ISR_ALM_IS_MASK, /*!< Alarm Status flag */ + kIRTC_DayFlag = RTC_ISR_DAY_IS_MASK, /*!< Days Status flag */ + kIRTC_HourFlag = RTC_ISR_HOUR_IS_MASK, /*!< Hour Status flag */ + kIRTC_MinFlag = RTC_ISR_MIN_IS_MASK, /*!< Minutes Status flag */ + kIRTC_1hzFlag = RTC_ISR_IS_1HZ_MASK, /*!< 1 Hz interval status flag */ + kIRTC_2hzFlag = RTC_ISR_IS_2HZ_MASK, /*!< 2 Hz interval status flag*/ + kIRTC_4hzFlag = RTC_ISR_IS_4HZ_MASK, /*!< 4 Hz interval status flag*/ + kIRTC_8hzFlag = RTC_ISR_IS_8HZ_MASK, /*!< 8 Hz interval status flag*/ + kIRTC_16hzFlag = RTC_ISR_IS_16HZ_MASK, /*!< 16 Hz interval status flag*/ + kIRTC_32hzFlag = RTC_ISR_IS_32HZ_MASK, /*!< 32 Hz interval status flag*/ + kIRTC_64hzFlag = RTC_ISR_IS_64HZ_MASK, /*!< 64 Hz interval status flag*/ + kIRTC_128hzFlag = RTC_ISR_IS_128HZ_MASK, /*!< 128 Hz interval status flag*/ + kIRTC_256hzFlag = RTC_ISR_IS_256HZ_MASK, /*!< 256 Hz interval status flag*/ + kIRTC_512hzFlag = RTC_ISR_IS_512HZ_MASK, /*!< 512 Hz interval status flag*/ + kIRTC_InvalidFlag = (RTC_STATUS_INVAL_BIT_MASK << 16U), /*!< Indicates if time/date counters are invalid */ + kIRTC_WriteProtFlag = (RTC_STATUS_WRITE_PROT_EN_MASK << 16U), /*!< Write protect enable status flag */ + kIRTC_CpuLowVoltFlag = (RTC_STATUS_CPU_LOW_VOLT_MASK << 16U), /*!< CPU low voltage warning flag */ + kIRTC_ResetSrcFlag = (RTC_STATUS_RST_SRC_MASK << 16U), /*!< Reset source flag */ + kIRTC_CmpIntFlag = (RTC_STATUS_CMP_INT_MASK << 16U), /*!< Compensation interval status flag */ + kIRTC_BusErrFlag = (RTC_STATUS_BUS_ERR_MASK << 16U), /*!< Bus error flag */ + kIRTC_CmpDoneFlag = (RTC_STATUS_CMP_DONE_MASK << 16U), /*!< Compensation done flag */ +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + kIRTC_WakeTimerFlag = (RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK << 28U) /*!< Wake timer status flag */ +#endif +} irtc_status_flags_t; + +/*! @brief IRTC alarm match options */ +typedef enum _irtc_alarm_match +{ + kRTC_MatchSecMinHr = 0U, /*!< Only match second, minute and hour */ + kRTC_MatchSecMinHrDay = 1U, /*!< Only match second, minute, hour and day */ + kRTC_MatchSecMinHrDayMnth = 2U, /*!< Only match second, minute, hour, day and month */ + kRTC_MatchSecMinHrDayMnthYr = 3U /*!< Only match second, minute, hour, day, month and year */ +} irtc_alarm_match_t; + +/*! @brief List of RTC Oscillator capacitor load settings */ +typedef enum _irtc_osc_cap_load +{ + kIRTC_Capacitor2p = (1U << 1U), /*!< 2pF capacitor load */ + kIRTC_Capacitor4p = (1U << 2U), /*!< 4pF capacitor load */ + kIRTC_Capacitor8p = (1U << 3U), /*!< 8pF capacitor load */ + kIRTC_Capacitor16p = (1U << 4U) /*!< 16pF capacitor load */ +} irtc_osc_cap_load_t; + +/*! @brief IRTC clockout select. */ +typedef enum _irtc_clockout_sel +{ + kIRTC_ClkoutNo = 0U, /*!< No clock out */ + kIRTC_ClkoutFine1Hz, /*!< clock out fine 1Hz */ + kIRTC_Clkout32kHz, /*!< clock out 32.768kHz */ + kIRTC_ClkoutCoarse1Hz /*!< clock out coarse 1Hz */ +} irtc_clockout_sel_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _irtc_datetime +{ + uint16_t year; /*!< Range from 1984 to 2239.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t weekDay; /*!< Range from 0(Sunday) to 6(Saturday). */ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} irtc_datetime_t; + +/*! @brief Structure is used to hold the daylight saving time */ +typedef struct _irtc_daylight_time +{ + uint8_t startMonth; /*!< Range from 1 to 12 */ + uint8_t endMonth; /*!< Range from 1 to 12 */ + uint8_t startDay; /*!< Range from 1 to 31 (depending on month) */ + uint8_t endDay; /*!< Range from 1 to 31 (depending on month) */ + uint8_t startHour; /*!< Range from 0 to 23 */ + uint8_t endHour; /*!< Range from 0 to 23 */ +} irtc_daylight_time_t; + +/*! @brief Structure is used to define the parameters to configure a RTC tamper event. */ +typedef struct _irtc_tamper_config +{ +#if FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION + bool activePassive; /*!< true: configure tamper as active; false: passive tamper */ + bool direction; /*!< true: configure tamper direction as output; false: configure as input; + this is only used if a tamper pin is defined as active */ +#endif + bool pinPolarity; /*!< true: tamper has active low polarity; + false: active high polarity */ + irtc_filter_clock_source_t filterClk; /*!< Clock source for the tamper filter */ + uint8_t filterDuration; /*!< Tamper filter duration.*/ +} irtc_tamper_config_t; + +/*! + * @brief RTC config structure + * + * This structure holds the configuration settings for the RTC peripheral. To initialize this + * structure to reasonable defaults, call the IRTC_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _irtc_config +{ +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + bool wakeupSelect; /*!< true: Tamper pin 0 is used to wakeup the chip; + false: Tamper pin 0 is used as the tamper pin */ +#endif + bool timerStdMask; /*!< true: Sampling clocks gated in standby mode; + false: Sampling clocks not gated */ + irtc_alarm_match_t alrmMatch; /*!< Pick one option from enumeration :: irtc_alarm_match_t */ +} irtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the IRTC clock and configures the peripheral for basic operation. + * + * This function initiates a soft-reset of the IRTC module, this has not effect on DST, + * calendaring, standby time and tamper detect registers. + * + * @note This API should be called at the beginning of the application using the IRTC driver. + * + * @param base IRTC peripheral base address + * @param config Pointer to user's IRTC config structure. + * + * @return kStatus_Fail if we cannot disable register write protection + */ +status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config); + +/*! + * @brief Gate the IRTC clock + * + * @param base IRTC peripheral base address + */ +static inline void IRTC_Deinit(RTC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Rtc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Fill in the IRTC config struct with the default settings + * + * The default values are: + * @code + * config->wakeupSelect = true; + * config->timerStdMask = false; + * config->alrmMatch = kRTC_MatchSecMinHr; + * @endcode + * @param config Pointer to user's IRTC config structure. + */ +void IRTC_GetDefaultConfig(irtc_config_t *config); + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the IRTC date and time according to the given time structure. + * + * The IRTC counter is started after the time is set. + * + * @param base IRTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: success in setting the time and starting the IRTC + * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. + */ +status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime); + +/*! + * @brief Gets the IRTC time and stores it in the given time structure. + * + * @param base IRTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void IRTC_GetDatetime(RTC_Type *base, irtc_datetime_t *datetime); + +/*! + * @brief Sets the IRTC alarm time + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @note weekDay field of alarmTime is not used during alarm match and should be set to 0 + * + * @return kStatus_Success: success in setting the alarm + * kStatus_InvalidArgument: error in setting the alarm. Error occurs because the alarm + * datetime format is incorrect. + */ +status_t IRTC_SetAlarm(RTC_Type *base, const irtc_datetime_t *alarmTime); + +/*! + * @brief Returns the IRTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void IRTC_GetAlarm(RTC_Type *base, irtc_datetime_t *datetime); +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected IRTC interrupts. + * + * @param base IRTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::irtc_interrupt_enable_t + */ +static inline void IRTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER |= (uint16_t)mask; +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + if (0U != (mask & kIRTC_WakeTimerInterruptEnable)) + { + base->WAKE_TIMER_CTRL |= RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; + } +#endif +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE + if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) + { + base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; + } +#endif +} + +/*! + * @brief Disables the selected IRTC interrupts. + * + * @param base IRTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::irtc_interrupt_enable_t + */ +static inline void IRTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER &= ~(uint16_t)mask; +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + if (0U != (mask & kIRTC_WakeTimerInterruptEnable)) + { + base->WAKE_TIMER_CTRL &= ~RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; + } +#endif +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE + if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) + { + base->TAMPER_QSCR &= ~RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; + } +#endif +} + +/*! + * @brief Gets the enabled IRTC interrupts. + * + * @param base IRTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::irtc_interrupt_enable_t + */ +static inline uint32_t IRTC_GetEnabledInterrupts(RTC_Type *base) +{ + uint32_t intsEnabled = base->IER; +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + intsEnabled |= (base->WAKE_TIMER_CTRL & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; +#endif +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE + intsEnabled |= (base->TAMPER_QSCR & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; +#endif + + return intsEnabled; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the IRTC status flags + * + * @param base IRTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::irtc_status_flags_t + */ +static inline uint32_t IRTC_GetStatusFlags(RTC_Type *base) +{ +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + return (base->ISR | ((uint32_t)base->STATUS << 16U) | ((uint32_t)base->WAKE_TIMER_CTRL << 28U)); +#else + return (base->ISR | ((uint32_t)base->STATUS << 16U)); +#endif +} + +/*! + * @brief Clears the IRTC status flags. + * + * @param base IRTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::irtc_status_flags_t + */ +static inline void IRTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + base->ISR = (uint16_t)mask; + base->STATUS = (base->STATUS & ~((uint16_t)RTC_STATUS_BUS_ERR_MASK | (uint16_t)RTC_STATUS_CMP_DONE_MASK)) | + ((uint16_t)(mask >> 16U)); +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + if (0U != (mask & kIRTC_WakeTimerFlag)) + { + base->WAKE_TIMER_CTRL |= RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK; + } +#endif +} + +/*! @}*/ + +/*! + * @brief This function sets the specified capacitor configuration for the RTC oscillator. + * + * @param base IRTC peripheral base address + * @param capLoad Oscillator loads to enable. This is a logical OR of members of the + * enumeration ::irtc_osc_cap_load_t + */ +static inline void IRTC_SetOscCapLoad(RTC_Type *base, uint16_t capLoad) +{ + uint16_t reg = base->GP_DATA_REG; + + reg &= ~((uint16_t)kIRTC_Capacitor2p | (uint16_t)kIRTC_Capacitor4p | (uint16_t)kIRTC_Capacitor8p | + (uint16_t)kIRTC_Capacitor16p); + reg |= capLoad; + + base->GP_DATA_REG = reg; +} + +/*! + * @brief Locks or unlocks IRTC registers for write access. + * + * @note When the registers are unlocked, they remain in unlocked state for + * 2 seconds, after which they are locked automatically. After + * power-on-reset, the registers come out unlocked and they are locked + * automatically 15 seconds after power on. + * + * @param base IRTC peripheral base address + * @param lock true: Lock IRTC registers; false: Unlock IRTC registers. + * + * @return kStatus_Success: if lock or unlock operation is successful + * kStatus_Fail: if lock or unlock operation fails even after multiple retry attempts + */ +status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock); + +/*! + * @brief Performs a software reset on the IRTC module. + * + * Clears contents of alarm, interrupt (status and enable except tamper interrupt enable bit) + * registers, STATUS[CMP_DONE] and STATUS[BUS_ERR]. This has no effect on DST, calendaring, standby time + * and tamper detect registers. + * + * @param base IRTC peripheral base address + */ +static inline void IRTC_Reset(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_SWR_MASK; +} + +/*! + * @brief Enable/disable 32 kHz RTC OSC clock during RTC register write + * + * @param base IRTC peripheral base address + * @param enable Enable/disable 32 kHz RTC OSC clock. + * - true: Enables the oscillator. + * - false: Disables the oscillator. + * + */ +static inline void IRTC_Enable32kClkDuringRegisterWrite(RTC_Type *base, bool enable) +{ + if (enable) + { + base->GP_DATA_REG &= ~RTC_GP_DATA_REG_CFG0_MASK; + } + else + { + base->GP_DATA_REG |= RTC_GP_DATA_REG_CFG0_MASK; + } +} + +/*! + * @brief Select which clock to output from RTC. + * + * Select which clock to output from RTC for other modules to use inside SoC, for example, + * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. + * + * @param base IRTC peripheral base address + * @param cloOut select clock to use for output, + */ +void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut); + +/*! + * @brief Gets the IRTC Tamper status flags + * + * @param base IRTC peripheral base address + * + * @return The Tamper status value. + */ +static inline uint8_t IRTC_GetTamperStatusFlag(RTC_Type *base) +{ + return (base->TAMPER_SCR & RTC_TAMPER_SCR_TMPR_STS_MASK) >> RTC_TAMPER_SCR_TMPR_STS_SHIFT; +} + +/*! + * @brief Gets the IRTC Tamper status flags + * + * @param base IRTC peripheral base address + * + */ +static inline void IRTC_ClearTamperStatusFlag(RTC_Type *base) +{ + /* Writing '1' to this field clears the tamper status.*/ + base->TAMPER_SCR |= RTC_TAMPER_SCR_TMPR_STS_MASK; +} + +/*! + * @brief Set tamper configuration over + * + * Note that this API is neeeded after call IRTC_SetTamperParams to configure tamper events to + * notify IRTC module that tamper configuration process is over. + * + * @param base IRTC peripheral base address + * + */ +static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base) +{ + /* Set tamper configuration over.*/ + base->CTRL2 |= RTC_CTRL2_TAMP_CFG_OVER_MASK; +} + +/*! + * @name Daylight Savings Interface + * @{ + */ + +/*! + * @brief Sets the IRTC daylight savings start and stop date and time. + * + * It also enables the daylight saving bit in the IRTC control register + * + * @param base IRTC peripheral base address + * @param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime); + +/*! + * @brief Gets the IRTC daylight savings time and stores it in the given time structure. + * + * @param base IRTC peripheral base address + * @param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime); + +/*! @}*/ + +/*! + * @name Time Compensation Interface + * @{ + */ + +/*! + * @brief Enables the coarse compensation and sets the value in the IRTC compensation register. + * + * @param base IRTC peripheral base address + * @param compensationValue Compensation value is a 2's complement value. + * @param compensationInterval Compensation interval. + */ +void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8_t compensationInterval); + +/*! + * @brief Enables the fine compensation and sets the value in the IRTC compensation register. + * + * @param base The IRTC peripheral base address + * @param integralValue Compensation integral value; twos complement value of the integer part + * @param fractionValue Compensation fraction value expressed as number of clock cycles of a + * fixed 4.194304Mhz clock that have to be added. + * @param accumulateFractional Flag indicating if we want to add to previous fractional part; + * true: Add to previously accumulated fractional part, + * false: Start afresh and overwrite current value + */ +void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional); + +/*! @}*/ + +/*! + * @name Tamper Interface + * @{ + */ + +/*! + * @brief This function allows configuring the four tamper inputs. + * + * The function configures the filter properties for the three external tampers. + * It also sets up active/passive and direction of the tamper bits, which are not available + * on all platforms. + * @note This function programs the tamper filter parameters. The user must gate the 32K clock to + * the RTC before calling this function. It is assumed that the time and date are set after this + * and the tamper parameters do not require to be changed again later. + * + * @param base The IRTC peripheral base address + * @param tamperNumber The IRTC tamper input to configure + * @param tamperConfig The IRTC tamper properties + */ +void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const irtc_tamper_config_t *tamperConfig); + +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + +/*! + * @brief This function reads the tamper timestamp and returns the associated tamper pin. + * + * The tamper timestamp has month, day, hour, minutes, and seconds. Ignore the year field as this + * information is not available in the tamper queue. The user should look at the RTC_YEARMON register + * for this because the expectation is that the queue is read at least once a year. + * Return the tamper pin number associated with the timestamp. + * + * @param base The IRTC peripheral base address + * @param tamperTimestamp The tamper timestamp + * + * @return The tamper pin number + */ +uint8_t IRTC_ReadTamperQueue(RTC_Type *base, irtc_datetime_t *tamperTimestamp); + +/*! + * @brief Gets the IRTC Tamper queue full status + * + * @param base IRTC peripheral base address + * + * @retval true Tamper queue is full. + * @retval false Tamper queue is not full. + */ +static inline bool IRTC_GetTamperQueueFullStatus(RTC_Type *base) +{ + return ((0U != (base->TAMPER_SCR & RTC_TAMPER_QSCR_Q_FULL_MASK)) ? true : false); +} + +/*! + * @brief Clear the IRTC Tamper queue full status + * + * @param base IRTC peripheral base address + * + */ +static inline void IRTC_ClearTamperQueueFullStatus(RTC_Type *base) +{ + base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_CLEAR_MASK; +} +#endif /* FSL_FEATURE_RTC_HAS_TAMPER_QUEUE */ + +/*! @}*/ + +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM +/*! + * @name RTC subsystem Interface + * @{ + */ + +/*! + * @brief Enable the RTC wake-up timer. + * + * 1HZ clock out selected via call to API IRTC_ConfigClockOut in order for the subsecond + * counter to synchronize with the RTC_SECONDS counter. + * + * @param base RTC peripheral base address + * @param enable Use/Un-use the sub-second counter. + * - true: Use RTC wake-up timer at the same time. + * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. + */ +static inline void IRTC_EnableSubsecondCounter(RTC_Type *base, bool enable) +{ + if (enable) + { + base->SUBSECOND_CTRL |= RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK; + } + else + { + base->SUBSECOND_CTRL &= ~RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK; + } +} + +/*! + * @brief Read the actual RTC sub-second COUNT value. + * + * @param base RTC peripheral base address + * + * @return The actual RTC sub-second COUNT value. + */ +static inline uint32_t IRTC_GetSubsecondCount(RTC_Type *base) +{ + uint32_t a, b; + + /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ + do + { + a = base->SUBSECOND_CNT; + b = base->SUBSECOND_CNT; + } while (a != b); + + return b; +} +/*! + * @brief Set countdown value to the RTC wake timer counter register. + * + * @param base RTC peripheral base address + * @param enable1kHzClk Enable 1kHz clock source for the wake timer, else use the 32kHz clock. + * @param wakeupValue The value to be loaded into the WAKE register in wake timer counter. + */ +static inline void IRTC_SetWakeupCount(RTC_Type *base, bool enable1kHzClk, uint32_t wakeupValue) +{ + /* Config whether enable the wakeup counter */ + uint32_t writeVal; + writeVal = base->WAKE_TIMER_CTRL; + base->WAKE_TIMER_CTRL = RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK; + + if (enable1kHzClk) + { + writeVal |= RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; + } + else + { + writeVal &= ~RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; + } + + base->WAKE_TIMER_CTRL = writeVal; + /* Set the start countdown value into the RTC WAKE register */ + base->WAKE_TIMER_CNT = wakeupValue; +} + +/*! + * @brief Read the actual value from the WAKE register value in RTC wake timer. + * + * @param base RTC peripheral base address + * + * @return The actual value of the WAKE register value in wake timer counter. + */ +static inline uint32_t IRTC_GetWakeupCount(RTC_Type *base) +{ + /* Read current wake-up countdown value */ + return base->WAKE_TIMER_CNT; +} + +/*! @}*/ +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_IRTC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.c new file mode 100644 index 0000000000000000000000000000000000000000..af31f6c1842c5b00d64265954521c6bb74b17ab1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.c @@ -0,0 +1,236 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_itrc.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.itrc" +#endif + +#define b11 0x3u +#define b10 0x2u +#define b01 0x1u + +/* Value used to trigger SW Events */ +#define SW_EVENT_VAL 0x5AA55AA5u + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * Weak implementation of ITRC IRQ, should be re-defined by user when using ITRC IRQ + */ +__WEAK void ITRC0_DriverIRQHandler(void) +{ + /* ITRC generates IRQ until corresponding bit in STATUS is cleared by calling + * ITRC_ClearStatus(ITRC,((uint32_t)kITRC_Irq) + */ +} + +/*! + * brief Clear ITRC status + * + * This function clears corresponding ITRC event or action in STATUS register. + * + * param base ITRC peripheral base address + * param word 32bit word represent corresponding event/action in STATUS register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word) +{ + /* If reserved/unused bits in STATUS register are set in 'word' parameter, return kStatus_InvalidArgument */ + if ((word & ~(IN_EVENTS_MASK | OUT_ACTIONS_MASK)) != 0u) + { + return kStatus_InvalidArgument; + } + + base->STATUS |= word; + + return kStatus_Success; +} + +/*! + * brief Clear all ITRC status + * + * This clears all event and action status. + * + * param base ITRC peripheral base address + * return Status of the ITRC + */ +status_t ITRC_ClearAllStatus(ITRC_Type *base) +{ + base->STATUS |= (IN_EVENTS_MASK | OUT_ACTIONS_MASK); + + return kStatus_Success; +} + +/*! + * brief Trigger ITRC SW Event 0 + * + * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. + * + * param base ITRC peripheral base address + */ +void ITRC_SetSWEvent0(ITRC_Type *base) +{ + base->SW_EVENT0 = SW_EVENT_VAL; +} + +/*! + * brief Trigger ITRC SW Event 1 + * + * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. + * + * param base ITRC peripheral base address + */ +void ITRC_SetSWEvent1(ITRC_Type *base) +{ + base->SW_EVENT1 = SW_EVENT_VAL; +} + +/*! + * brief Set ITRC Action to Event + * + * This function sets input Event signal to corresponding output Action response signal. + * + * param base ITRC peripheral base address + * param out ITRC OUT signal action + * param in ITRC IN signal event + * param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. + * param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_SetActionToEvent( + ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable) +{ + uint32_t sel0, sel1, index, select_AND_mask; + + /* prepare values for INx_SEL0/1 bit-field according to secure techniques and register behavior + * +------------+------------+------------------+---------------------------+ + * | INx_SEL0 | INx_SEL1 | Signal selected? | Writable field? | + * +------------+------------+------------------+---------------------------+ + * | 10 | 10 | No | Yes (default after reset) | + * | 01 | 10 | Yes | Yes | + * | don't care | !="10" | Yes | No | + * | 00 or 11 | don't care | Yes | No | + * +------------+------------+------------------+---------------------------+ + */ + if ((lock == kITRC_Unlock) && (enable == kITRC_Disable)) + { + sel0 = b10; + sel1 = b10; + } + else if ((lock == kITRC_Unlock) && (enable == kITRC_Enable)) + { + sel0 = b01; + sel1 = b10; + } + else + { + sel0 = b11; + sel1 = b11; + } + + /* Compute index for INx_SEL0/1 bit-field within OUTy_SEL0/1 registers */ + index = 2u * in; + /* Prepare AND mask to set INx_SEL0 accordingly */ + select_AND_mask = ~(b11 << index); + + /* Last possible index in OUTx_SELy registers is 30 */ + if (index > 30u) + { + return kStatus_InvalidArgument; + } + + switch (out) + { + case kITRC_Irq: + base->OUT0_SEL0 = (base->OUT0_SEL0 & select_AND_mask) | (sel0 << index); + base->OUT0_SEL1 |= sel1 << index; + break; + case kITRC_CssReset: + base->OUT1_SEL0 = (base->OUT1_SEL0 & select_AND_mask) | (sel0 << index); + base->OUT1_SEL1 |= sel1 << index; + break; + + case kITRC_PufZeroize: + base->OUT2_SEL0 = (base->OUT2_SEL0 & select_AND_mask) | (sel0 << index); + base->OUT2_SEL1 |= sel1 << index; + break; + + case kITRC_RamZeroize: + base->OUT3_SEL0 = (base->OUT3_SEL0 & select_AND_mask) | (sel0 << index); + base->OUT3_SEL1 |= sel1 << index; + break; + + case kITRC_ChipReset: + base->OUT4_SEL0 = (base->OUT4_SEL0 & select_AND_mask) | (sel0 << index); + base->OUT4_SEL1 |= sel1 << index; + break; + + case kITRC_TamperOut: + base->OUT5_SEL0 = (base->OUT5_SEL0 & select_AND_mask) | (sel0 << index); + base->OUT5_SEL1 |= sel1 << index; + break; + default: + /* This case shouldn't be reached. */ + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * brief Get ITRC Status + * + * This function returns ITRC register status. + * + * param base ITRC peripheral base address + * return Value of ITRC STATUS register + */ +status_t ITRC_GetStatus(ITRC_Type *base) +{ + return base->STATUS; +} + +/*! + * brief Initialize ITRC + * + * This function initializes ITRC by enabling IRQ. + * + * param base ITRC peripheral base address + * return Status of the init operation + */ +status_t ITRC_Init(ITRC_Type *base) +{ + NVIC_EnableIRQ(ITRC0_IRQn); + + return kStatus_Success; +} + +/*! + * brief Deinitialize ITRC + * + * This function just disable ITRC IRQ. + * + * param base ITRC peripheral base address + */ +void ITRC_Deinit(ITRC_Type *base) +{ + NVIC_DisableIRQ(ITRC0_IRQn); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.h new file mode 100644 index 0000000000000000000000000000000000000000..877134aa4d9c9647799eb85c4591865400720abb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_itrc.h @@ -0,0 +1,208 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_ITRC_H_ +#define _FSL_ITRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ITRC + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines ITRC driver version 2.1.0. + * + * Change log: + * - Version 2.1.0 + * - Make SYSCON glitch platform dependent + * - Version 2.0.0 + * - initial version + */ +#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +typedef enum _itrc_input_signals +{ + kITRC_CssGlitch = 0U, + kITRC_RtcTamper = 1U, + kITRC_Cdog = 2U, + kITRC_BodVbat = 3u, + kITRC_BodVdd = 4u, + kITRC_Watchdog = 5u, + kITRC_FlashEcc = 6u, + kITRC_Ahb = 7u, + kITRC_CssErr = 8u, +#if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) + kITRC_SysconGlitch = 9u, +#endif + kITRC_Pkc = 10u, + kITRC_SwEvent1 = 14u, + kITRC_SwEvent2 = 15u +} itrc_input_signals_t; + +typedef enum _itrc_lock +{ + kITRC_Unlock = 0U, + kITRC_Lock = 1U, +} itrc_lock_t; + +typedef enum _itrc_enable +{ + kITRC_Enable = 0U, + kITRC_Disable = 1U, +} itrc_enable_t; + +typedef enum _itrc_out_signals +{ + kITRC_Irq = 16U, + kITRC_CssReset = 17U, + kITRC_PufZeroize = 18U, + kITRC_RamZeroize = 19u, + kITRC_ChipReset = 20u, + kITRC_TamperOut = 21u, +} itrc_out_signals_t; + +#if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) +#define IN_EVENTS_MASK \ + (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ + ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ + ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ + ITRC_STATUS_IN9_STATUS_MASK | ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | \ + ITRC_STATUS_IN15_STATUS_MASK) +#else +#define IN_EVENTS_MASK \ + (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ + ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ + ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ + ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | ITRC_STATUS_IN15_STATUS_MASK) +#endif /* FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH */ + +#define OUT_ACTIONS_MASK \ + (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ + ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK) + +#ifndef ITRC +#define ITRC ITRC0 +#endif + +/******************************************************************************* + * API + *******************************************************************************/ + +extern void ITRC0_DriverIRQHandler(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name ITRC Functional Operation + * @{ + */ + +/*! + * @brief Set ITRC Action to Event + * + * This function sets input Event signal to corresponding output Action response signal. + * + * @param base ITRC peripheral base address + * @param out ITRC OUT signal action + * @param in ITRC IN signal event + * @param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. + * @param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). + * @return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_SetActionToEvent( + ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable); + +/*! + * @brief Trigger ITRC SW Event 0 + * + * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. + * + * @param base ITRC peripheral base address + */ +void ITRC_SetSWEvent0(ITRC_Type *base); + +/*! + * @brief Trigger ITRC SW Event 1 + * + * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. + * + * @param base ITRC peripheral base address + */ +void ITRC_SetSWEvent1(ITRC_Type *base); + +/*! + * @brief Get ITRC Status + * + * This function returns ITRC register status. + * + * @param base ITRC peripheral base address + * @return Value of ITRC STATUS register + */ +status_t ITRC_GetStatus(ITRC_Type *base); + +/*! + * @brief Clear ITRC status + * + * This function clears corresponding ITRC event or action in STATUS register. + * + * @param base ITRC peripheral base address + * @param word 32bit word represent corresponding event/action in STATUS register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * @return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word); + +/*! + * @brief Clear All ITRC status + * + * This function clears all event and action status. + * + * @param base ITRC peripheral base address + * @return kStatus_Success if success + */ +status_t ITRC_ClearAllStatus(ITRC_Type *base); + +/*! + * @brief Initialize ITRC + * + * This function initializes ITRC by enabling IRQ. + * + * @param base ITRC peripheral base address + * @param conf ITRC configuration structure + * @return Status of the init operation + */ +status_t ITRC_Init(ITRC_Type *base); + +/*! + * @brief Deinitialize ITRC + * + * This function deinitializes ITRC by disabling IRQ. + * + * @param base ITRC peripheral base address + */ +void ITRC_Deinit(ITRC_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group itrc */ + +#endif /* _FSL_ITRC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.c new file mode 100644 index 0000000000000000000000000000000000000000..7835e6fc454d28895795b4a29d6c117309d7646d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.c @@ -0,0 +1,612 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpadc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpadc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for LPADC module. + * + * @param base LPADC peripheral base address + */ +static uint32_t LPADC_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPADC bases for each instance. */ +static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPADC clocks for each instance. */ +static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) + { + if (s_lpadcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpadcBases)); + + return instance; +} + +/*! + * brief Initializes the LPADC module. + * + * param base LPADC peripheral base address. + * param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) +{ + /* Check if the pointer is available. */ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for LPADC instance. */ + (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + LPADC_DoResetConfig(base); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + LPADC_DoResetFIFO0(base); + LPADC_DoResetFIFO1(base); +#else + LPADC_DoResetFIFO(base); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Disable the module before setting configuration. */ + LPADC_Enable(base, false); + + /* Configure the module generally. */ + if (config->enableInDozeMode) + { + base->CTRL &= ~ADC_CTRL_DOZEN_MASK; + } + else + { + base->CTRL |= ADC_CTRL_DOZEN_MASK; + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/* ADCx_CFG. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + if (config->enableInternalClock) + { + tmp32 |= ADC_CFG_ADCKEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + if (config->enableVref1LowVoltage) + { + tmp32 |= ADC_CFG_VREF1RNG_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + if (config->enableAnalogPreliminary) + { + tmp32 |= ADC_CFG_PWREN_MASK; + } + tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ + | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ + base->CFG = tmp32; + + /* ADCx_PAUSE. */ + if (config->enableConvPause) + { + base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); + } + else + { + base->PAUSE = 0U; + } + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* ADCx_FCTRL0. */ + base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); + /* ADCx_FCTRL1. */ + base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); +#else + /* ADCx_FCTRL. */ + base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Enable the module after setting configuration. */ + LPADC_Enable(base, true); +} + +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * code + * config->enableInDozeMode = true; + * config->conversionAverageMode = kLPADC_ConversionAverage1; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFO0Watermark = 0U; + * config->FIFO1Watermark = 0U; + * config->FIFOWatermark = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + config->enableInternalClock = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + config->enableVref1LowVoltage = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + config->enableInDozeMode = true; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + config->conversionAverageMode = kLPADC_ConversionAverage1; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + config->enableAnalogPreliminary = false; + config->powerUpDelay = 0x80; + config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + config->powerLevelMode = kLPADC_PowerLevelAlt1; + config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->enableConvPause = false; + config->convPauseDelay = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->FIFO0Watermark = 0U; + config->FIFO1Watermark = 0U; +#else + config->FIFOWatermark = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} + +/*! + * brief De-initializes the LPADC module. + * + * param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base) +{ + /* Disable the module. */ + LPADC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = base->RESFIFO[index]; + + if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +#else +/*! + * brief Get the result in conversion FIFO. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = base->RESFIFO; + + if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * param base LPADC peripheral base address. + * param triggerId ID for each trigger. Typically, the available value range is from 0. + * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) +{ + assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ + | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ + | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) +#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) + | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + ; + if (config->enableHardwareTrigger) + { + tmp32 |= ADC_TCTRL_HTEN_MASK; + } + + base->TCTRL[triggerId] = tmp32; +} + +/*! + * brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->targetCommandId = 0U; + config->delayPower = 0U; + config->priority = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->channelAFIFOSelect = 0U; + config->channelBFIFOSelect = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + config->enableHardwareTrigger = false; +} + +/*! + * brief Configure conversion command. + * + * param base LPADC peripheral base address. + * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) +{ + assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0; + + commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ + + /* ADCx_CMDL. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); +#else + switch (config->sampleChannelMode) /* Sample input. */ + { + case kLPADC_SampleChannelSingleEndSideB: + tmp32 |= ADC_CMDL_ABSEL_MASK; + break; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + case kLPADC_SampleChannelDiffBothSideAB: + tmp32 |= ADC_CMDL_DIFF_MASK; + break; + case kLPADC_SampleChannelDiffBothSideBA: + tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; + break; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + default: /* kLPADC_SampleChannelSingleEndSideA. */ + break; + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + base->CMD[commandId].CMDL = tmp32; + + /* ADCx_CMDH. */ + tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ + | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ + | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ + | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ + | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ +#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) + if (config->enableWaitTrigger) + { + tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ + + if (config->enableAutoChannelIncrement) + { + tmp32 |= ADC_CMDH_LWI_MASK; + } + base->CMD[commandId].CMDH = tmp32; + + /* Hardware compare settings. + * Not all Command Buffers have an associated Compare Value register. The compare function is only available on + * Command Buffers that have a corresponding Compare Value register. + */ + if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) + { + /* Check if the hardware compare feature is available for indicated command buffer. */ + assert(commandId < ADC_CV_COUNT); + + /* Set CV register. */ + base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ + } +} + +/*! + * brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + config->sampleScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + config->channelNumber = 0U; + config->chainedNextCommandNumber = 0U; /* No next command defined. */ + config->enableAutoChannelIncrement = false; + config->loopCount = 0U; + config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + config->sampleTimeMode = kLPADC_SampleTimeADCK3; + config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + config->hardwareCompareValueHigh = 0U; /* No used. */ + config->hardwareCompareValueLow = 0U; /* No used. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + config->enableWaitTrigger = false; +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * param base LPADC peripheral base address. + * param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable) +{ + LPADC_Enable(base, false); + if (enable) + { + base->CFG |= ADC_CFG_CALOFS_MASK; + } + else + { + base->CFG &= ~ADC_CFG_CALOFS_MASK; + } + LPADC_Enable(base, true); +} + +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert(0u == LPADC_GetConvResultCount(base)); + + uint32_t mLpadcCMDL; + uint32_t mLpadcCMDH; + uint32_t mLpadcTrigger; + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + /* Enable the calibration function. */ + LPADC_EnableCalibration(base, true); + + /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ + mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ + mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ + mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ + + /* Set trigger0 configuration - for software trigger. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ + + /* Do calibration. */ + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + { + } + /* The valid bits of data are bits 14:3 in the RESFIFO register. */ + LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); + /* Disable the calibration function. */ + LPADC_EnableCalibration(base, false); + + /* restore CMD and TRG registers. */ + base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ + base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ + base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * brief Do offset calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base) +{ + LPADC_EnableOffsetCalibration(base, true); + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); + + uint32_t GCCa; + uint32_t GCCb; + uint32_t GCRa; + uint32_t GCRb; + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || + (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) + { + } + + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (uint16_t)((GCCa << 16U) / + (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ + GCRb = (uint16_t)((GCCb << 16U) / + (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ + base->GCR[0] = ADC_GCR_GCALR(GCRa); + base->GCR[1] = ADC_GCR_GCALR(GCRb); + + /* Indicate the values are valid. */ + base->GCR[0] |= ADC_GCR_RDY_MASK; + base->GCR[1] |= ADC_GCR_RDY_MASK; + + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.h new file mode 100644 index 0000000000000000000000000000000000000000..cc5429d69b54dbd52f1ab4a20a2ef2f73ba4ae9f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_lpadc.h @@ -0,0 +1,928 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPADC_H_ +#define _FSL_LPADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpadc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPADC driver version 2.4.0. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Define the MACRO function to get command status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) + +/*! + * @brief Define the MACRO function to get trigger status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result + FIFO 0 than it can hold. */ + kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 0 is greater than the setting watermark level. */ + kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result + FIFO 1 than it can hold. */ + kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 1 is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF0 flag is asserted. */ + kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF1 flag is asserted. */ + kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY1 flag is asserted. */ +}; +#else +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO + than it can hold. */ + kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO + is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF flag is asserted. */ + kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY flag is asserted. */ +}; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + */ +enum _lpadc_trigger_status_flags +{ + kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ + kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ + kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ + kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ + kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ + kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ + kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ + kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ + kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ + kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ + kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ + kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ + kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ + kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ + kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ + kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ + + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ +}; +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + +/*! + * @brief Define enumeration of sample scale mode. + * + * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum + * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the + * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows + * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. + */ +typedef enum _lpadc_sample_scale_mode +{ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ + kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ +} lpadc_sample_scale_mode_t; + +/*! + * @brief Define enumeration of channel sample mode. + * + * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. + */ +typedef enum _lpadc_sample_channel_mode +{ + kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ + kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */ + kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */ +#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ + kLPADC_SampleChannelDualSingleEndBothSide = + 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ +#endif +} lpadc_sample_channel_mode_t; + +/*! + * @brief Define enumeration of hardware average selection. + * + * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to + * capture temporary results while the averaging iterations are executed. + */ +typedef enum _lpadc_hardware_average_mode +{ + kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ + kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_hardware_average_mode_t; + +/*! + * @brief Define enumeration of sample time selection. + * + * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher + * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption + * when command looping and sequencing is configured and high conversion rates are not required. + */ +typedef enum _lpadc_sample_time_mode +{ + kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ +} lpadc_sample_time_mode_t; + +/*! + * @brief Define enumeration of hardware compare mode. + * + * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting + * guides operation of the automatic compare function to optionally only store when the compare operation is true. + * When compare is enabled, the conversion result is compared to the compare values. + */ +typedef enum _lpadc_hardware_compare_mode +{ + kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ + kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ + kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ +} lpadc_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE +/*! + * @brief Define enumeration of conversion resolution mode. + * + * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to + * #lpadc_sample_channel_mode_t + */ +typedef enum _lpadc_conversion_resolution_mode +{ + kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential + 13-bit conversion with 2’s complement output. */ + kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit + conversion with 2’s complement output. */ +} lpadc_conversion_resolution_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS +/*! + * @brief Define enumeration of conversion averages mode. + * + * Configure the converion average number for auto-calibration. + */ +typedef enum _lpadc_conversion_average_mode +{ + kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ + kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_conversion_average_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/*! + * @brief Define enumeration of reference voltage source. + * + * For detail information, need to check the SoC's specification. + */ +typedef enum _lpadc_reference_voltage_mode +{ + kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ + kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ + kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ +} lpadc_reference_voltage_source_t; + +/*! + * @brief Define enumeration of power configuration. + * + * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be + * possible. Refer to the device data sheet for power and performance capabilities for each setting. + */ +typedef enum _lpadc_power_level_mode +{ + kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ + kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ + kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ + kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ +} lpadc_power_level_mode_t; + +/*! + * @brief Define enumeration of trigger priority policy. + * + * This selection controls how higher priority triggers are handled. + */ +typedef enum _lpadc_trigger_priority_policy +{ + kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started. */ + kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, + the current conversion is completed (including averaging iterations + and compare function if enabled) and stored to the result FIFO + before the higher priority trigger/command is initiated. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY + kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ +} lpadc_trigger_priority_policy_t; + +/*! + * @brief LPADC global configuration. + * + * This structure would used to keep the settings for initialization. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". + If voltage reference option1 input is above 1.8V, it should be "false". */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When + enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the + ADC will wait for the current averaging iteration/FIFO storage to complete before + acknowledging stop or wait mode entry. */ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without + startup delays(at the cost of higher DC current consumption). */ + uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered + while the ADC is active and there is a counted delay defined by this field after an + initial trigger transitions the ADC from its Idle state to allow time for the analog + circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must + result in a longer delay than the analog startup time. */ + lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for + conversions.*/ + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ + lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to + lpadc_trigger_priority_policy_mode_t. */ + bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during + command execution sequencing between LOOP iterations, between commands in a sequence, and + between conversions when command is executing in "Compare Until True" configuration. */ + uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay + is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing + function is enabled. The available value range is in 9-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* for FIFO0. */ + uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ + /* for FIFO1. */ + uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ +#else + /* for FIFO. */ + uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored + in the ADC Result FIFO is greater than the value in this field, the ready flag would be + asserted to indicate stored data has reached the programmable threshold. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} lpadc_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion command. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ + uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ + uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. + 1-15 is available, 0 is to terminate the chain after this command. */ + bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number + of times the selected channel is converted consecutively; when enabled, the + "loopCount" field defines how many consecutive channels are converted as part + of the command execution. */ + uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next + command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ + lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ + lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ + + lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ + uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ + uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be + automatically executed; when enabled, the active trigger must be asserted again before + executing this command. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} lpadc_conv_command_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion trigger. + */ +typedef struct +{ + uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated + trigger event. */ + uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. + When this field is clear, then no delay is incurred. When this field is set to a non-zero + value, the duration for the delay is 2^delayPower ADCK cycles. The available value range + is 4-bit. */ + uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same + priority level setting, the lower order trigger event has the higher priority. The lower + value for this field is for the higher priority, the available value range is 1-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ + uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the + input trigger source or not. THe software trigger is always available. */ +} lpadc_conv_trigger_config_t; + +/*! + * @brief Define the structure to keep the conversion result. + */ +typedef struct +{ + uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ + uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ + uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ + uint16_t convValue; /*!< Data result. */ +} lpadc_conv_result_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization & de-initialization. + * @{ + */ + +/*! + * @brief Initializes the LPADC module. + * + * @param base LPADC peripheral base address. + * @param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->enableInDozeMode = true; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFOWatermark = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config); + +/*! + * @brief De-initializes the LPADC module. + * + * @param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base); + +/*! + * @brief Switch on/off the LPADC module. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the module. + */ +static inline void LPADC_Enable(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_ADCEN_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_ADCEN_MASK; + } +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Do reset the conversion FIFO0. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO0(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; +} + +/*! + * @brief Do reset the conversion FIFO1. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO1(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; +} +#else +/*! + * @brief Do reset the conversion FIFO. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO_MASK; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Do reset the module's configuration. + * + * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetConfig(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RST_MASK; + base->CTRL &= ~ADC_CTRL_RST_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base LPADC peripheral base address. + * @return status flags' mask. See to #_lpadc_status_flags. + */ +static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear status flags. + * + * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. + */ +static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high + * priority trigger exception. + * + * @param base LPADC peripheral base address. + * @return The OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) +{ + return base->TSTAT; +} + +/*! + * @brief Clear trigger status flags. + * + * @param base LPADC peripheral base address. + * @param mask The mask of trigger status flags to be cleared, should be the + * OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->TSTAT = mask; +} +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE &= ~mask; +} + +/*! + * @name DMA Control + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Switch on/off the DMA trigger for FIFO0 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE0_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE0_MASK; + } +} + +/*! + * @brief Switch on/off the DMA trigger for FIFO1 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE1_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE1_MASK; + } +} +#else +/*! + * @brief Switch on/off the DMA trigger for FIFO watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE_MASK; + } +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + /* @} */ + +/*! + * @name Trigger and conversion with FIFO. + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Get the count of result kept in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param index Result FIFO index. + * @return The count of result kept in conversion FIFOn. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else +/*! + * @brief Get the count of result kept in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @return The count of result kept in conversion FIFO. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * @return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * @code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); + +/*! + * @brief Do software trigger to conversion command. + * + * @param base LPADC peripheral base address. + * @param triggerIdMask Mask value for software trigger indexes, which count from zero. + */ +static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) +{ + /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ + base->SWTRIG = triggerIdMask; +} + +/*! + * @brief Configure conversion command. + * + * @param base LPADC peripheral base address. + * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * @code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * @brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable); +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * To minimize the offset during normal operation, software should read the conversion result from + * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. + * + * @param base LPADC peripheral base address. + * @param value Setting offset value. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) +{ + base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; +} + +/*! + * @brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ + +/*! + * @brief Enable the offset calibration function. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_CALOFS_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_CALOFS_MASK; + } +} + +/*! + * @brief Do offset calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.c new file mode 100644 index 0000000000000000000000000000000000000000..703417ab886e4db8d0d27cca63a5957108e9c642 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.c @@ -0,0 +1,1700 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcan" +#endif + +/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ +#define IDEAL_DATA_SP_1 (800U) +#define IDEAL_DATA_SP_2 (750U) +#define IDEAL_DATA_SP_3 (700U) +#define IDEAL_DATA_SP_4 (625U) +#define IDEAL_NOMINAL_SP (800U) + +/* According to CiA doc 301 v4.2.0 and previous version, specified sample point postion for classic CAN. */ +#define IDEAL_SP_LOW (750U) +#define IDEAL_SP_MID (800U) +#define IDEAL_SP_HIGH (875U) +#define IDEAL_SP_FACTOR (1000U) + +#define MAX_DSJW (CAN_DBTP_DSJW_MASK >> CAN_DBTP_DSJW_SHIFT) +#define MAX_DTSEG2 (CAN_DBTP_DTSEG2_MASK >> CAN_DBTP_DTSEG2_SHIFT) +#define MAX_DTSEG1 (CAN_DBTP_DTSEG1_MASK >> CAN_DBTP_DTSEG1_SHIFT) +#define MAX_DBRP (CAN_DBTP_DBRP_MASK >> CAN_DBTP_DBRP_SHIFT) + +#define MAX_NSJW (CAN_NBTP_NSJW_MASK >> CAN_NBTP_NSJW_SHIFT) +#define MAX_NTSEG2 (CAN_NBTP_NTSEG2_MASK >> CAN_NBTP_NTSEG2_SHIFT) +#define MAX_NTSEG1 (CAN_NBTP_NTSEG1_MASK >> CAN_NBTP_NTSEG1_SHIFT) +#define MAX_NBRP (CAN_NBTP_NBRP_MASK >> CAN_NBTP_NBRP_SHIFT) + +#define DBTP_MAX_TIME_QUANTA (1U + MAX_DTSEG2 + 1U + MAX_DTSEG1 + 1U) +#define DBTP_MIN_TIME_QUANTA (3U) +#define NBTP_MAX_TIME_QUANTA (1U + MAX_NTSEG2 + 1U + MAX_NTSEG1 + 1U) +#define NBTP_MIN_TIME_QUANTA (3U) + +#define MAX_TDCOFF (CAN_TDCR_TDCO_MASK >> CAN_TDCR_TDCO_SHIFT) + +#define MAX_CANFD_BAUDRATE (8000000U) +#define MAX_CAN_BAUDRATE (1000000U) + +/*! @brief MCAN Internal State. */ +enum _mcan_state +{ + kMCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kMCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kMCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kMCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the MCAN instance from peripheral base address. + * + * @param base MCAN peripheral base address. + * @return MCAN instance. + */ +static uint32_t MCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Reset the MCAN instance. + * + * @param base MCAN peripheral base address. + */ +static void MCAN_Reset(CAN_Type *base); + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN + * + * @param baudRate The data speed in bps + * @param tqNum Number of time quantas per bit, range in 4~385 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig); + +/*! + * @brief Set Baud Rate of MCAN. + * + * This function set the baud rate of MCAN. + * + * @param base MCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRate_Bps Baud Rate in Bps. + * @param timingConfig MCAN timingConfig. + */ +static void MCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateA_Bps, + mcan_timing_config_t timingConfig); + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate + * + * @param baudRate The canfd bus data speed in bps + * @param tqNum Number of time quanta per bit, range in 3 ~ 33 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig); + +/*! + * @brief Set Baud Rate of MCAN FD. + * + * This function set the baud rate of MCAN FD. + * + * @param base MCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRateD_Bps Baud Rate in Bps. + * @param timingConfig MCAN timingConfig. + */ +static void MCAN_SetBaudRateFD(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateD_Bps, + mcan_timing_config_t timingConfig); + +#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ + +/*! + * @brief Get the element's address when read receive fifo 0. + * + * @param base MCAN peripheral base address. + * @return Address of the element in receive fifo 0. + */ +static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base); + +/*! + * @brief Get the element's address when read receive fifo 1. + * + * @param base MCAN peripheral base address. + * @return Address of the element in receive fifo 1. + */ +static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base); + +/*! + * @brief Get the element's address when read receive buffer. + * + * @param base MCAN peripheral base address. + * @param idx Number of the erceive buffer element. + * @return Address of the element in receive buffer. + */ +static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx); + +/*! + * @brief Get the element's address when read transmit buffer. + * + * @param base MCAN peripheral base address. + * @param idx Number of the transmit buffer element. + * @return Address of the element in transmit buffer. + */ +static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of MCAN handle. */ +static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT]; + +/* Array of MCAN peripheral base address. */ +static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS; + +/* Array of MCAN IRQ number. */ +static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of MCAN clock name. */ +static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) +/*! @brief Pointers to MCAN resets for each instance. */ +static const reset_ip_name_t s_mcanResets[] = MCAN_RSTS; +#endif + +/* MCAN ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static mcan_isr_t s_mcanIsr = (mcan_isr_t)DefaultISR; +#else +static mcan_isr_t s_mcanIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t MCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++) + { + if (s_mcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_mcanBases)); + + return instance; +} + +static void MCAN_Reset(CAN_Type *base) +{ + /* Set INIT bit. */ + base->CCCR |= CAN_CCCR_INIT_MASK; + /* Confirm the value has been accepted. */ + while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) + { + } + + /* Set CCE bit to have access to the protected configuration registers, + and clear some status registers. */ + base->CCCR |= CAN_CCCR_CCE_MASK; +} + +static void MCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateA_Bps, + mcan_timing_config_t timingConfig) +{ + /* MCAN timing setting formula: + * quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1); + */ + uint32_t quantum = (1U + ((uint32_t)timingConfig.seg1 + 1U) + ((uint32_t)timingConfig.seg2 + 1U)); + uint32_t preDivA = baudRateA_Bps * quantum; + + /* Assertion: Source clock should greater than baud rate * quantum. */ + assert(preDivA <= sourceClock_Hz); + + if (0U == preDivA) + { + preDivA = 1U; + } + + preDivA = (sourceClock_Hz / preDivA) - 1U; + + /* Desired baud rate is too low. */ + if (preDivA > 0x1FFU) + { + preDivA = 0x1FFU; + } + + timingConfig.preDivider = (uint16_t)preDivA; + + /* Update actual timing characteristic. */ + MCAN_SetArbitrationTimingConfig(base, &timingConfig); +} + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +static void MCAN_SetBaudRateFD(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateD_Bps, + mcan_timing_config_t timingConfig) +{ + /* MCAN timing setting formula: + * quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1); + */ + uint32_t quantum = (1U + ((uint32_t)timingConfig.dataseg1 + 1U) + ((uint32_t)timingConfig.dataseg2 + 1U)); + uint32_t preDivD = baudRateD_Bps * quantum; + + /* Assertion: Source clock should greater than baud rate * quantum. */ + assert(preDivD <= sourceClock_Hz); + + if (0U == preDivD) + { + preDivD = 1U; + } + + preDivD = (sourceClock_Hz / preDivD) - 1U; + + /* Desired baud rate is too low. */ + if (preDivD > 0x1FU) + { + preDivD = 0x1FU; + } + + timingConfig.datapreDivider = (uint16_t)preDivD; + + /* Update actual timing characteristic. */ + MCAN_SetDataTimingConfig(base, &timingConfig); +} +#endif + +/*! + * brief Initializes an MCAN instance. + * + * This function initializes the MCAN module with user-defined settings. + * This example shows how to set up the mcan_config_t parameters and how + * to call the MCAN_Init function by passing in these parameters. + * code + * mcan_config_t config; + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * MCAN_Init(CANFD0, &config, 8000000UL); + * endcode + * + * param base MCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. + */ +void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable MCAN clock. */ + CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) + /* Reset the MCAN module */ + RESET_PeripheralReset(s_mcanResets[MCAN_GetInstance(base)]); +#endif + + MCAN_Reset(base); + + if (config->enableLoopBackInt) + { + base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK; + base->TEST |= CAN_TEST_LBCK_MASK; + } + if (config->enableLoopBackExt) + { + base->CCCR |= CAN_CCCR_TEST_MASK; + base->TEST |= CAN_TEST_LBCK_MASK; + } + if (config->enableBusMon) + { + base->CCCR |= CAN_CCCR_MON_MASK; + } + /* Set baud rate of arbitration phase. */ + MCAN_SetBaudRate(base, sourceClock_Hz, config->baudRateA, config->timingConfig); + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) + if (config->enableCanfdNormal) + { + base->CCCR |= CAN_CCCR_FDOE_MASK; + } + if (config->enableCanfdSwitch) + { + /* Enable the CAN FD mode and Bit Rate Switch feature. */ + base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK; + /* Set baud rate of date phase when enable the CAN FD mode and Bit Rate Switch feature. */ + MCAN_SetBaudRateFD(base, sourceClock_Hz, config->baudRateD, config->timingConfig); + if (!config->enableLoopBackInt && !config->enableLoopBackExt) + { + /* Enable the Transceiver Delay Compensation. */ + base->DBTP |= CAN_DBTP_TDC_MASK; + /* Cleaning previous TDCO Setting. */ + base->TDCR &= ~CAN_TDCR_TDCO_MASK; + /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ + if (((uint32_t)config->timingConfig.dataseg1 + 2U) * (config->timingConfig.datapreDivider + 1U) < + MAX_TDCOFF) + { + base->TDCR |= CAN_TDCR_TDCO(((uint32_t)config->timingConfig.dataseg1 + 2U) * + (config->timingConfig.datapreDivider + 1U)); + } + else + { + /* Set the Transceiver Delay Compensation offset to max value. */ + base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); + } + } + } +#endif +} + +/*! + * brief Deinitializes an MCAN instance. + * + * This function deinitializes the MCAN module. + * + * param base MCAN peripheral base address. + */ +void MCAN_Deinit(CAN_Type *base) +{ + /* Reset all Register Contents. */ + MCAN_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable MCAN clock. */ + CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief MCAN enters normal mode. + * + * After initialization, INIT bit in CCCR register must be cleared to enter + * normal mode thus synchronizes to the CAN bus and ready for communication. + * + * param base MCAN peripheral base address. + */ +void MCAN_EnterNormalMode(CAN_Type *base) +{ + /* Reset INIT bit to enter normal mode. */ + base->CCCR &= ~CAN_CCCR_INIT_MASK; + while (0U != (base->CCCR & CAN_CCCR_INIT_MASK)) + { + } +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the MCAN configuration structure to default values. The default + * values are as follows. + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * + * param config Pointer to the MCAN configuration structure. + */ +void MCAN_GetDefaultConfig(mcan_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Initialize MCAN Module config struct with default value. */ + config->baudRateA = 500000U; + config->baudRateD = 2000000U; + config->enableCanfdNormal = false; + config->enableCanfdSwitch = false; + config->enableLoopBackInt = false; + config->enableLoopBackExt = false; + config->enableBusMon = false; + /* Default protocol timing configuration, time quantum is 16. */ + config->timingConfig.seg1 = 0xAU; + config->timingConfig.seg2 = 0x3U; + config->timingConfig.rJumpwidth = 0x3U; +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) + config->timingConfig.dataseg1 = 0xAU; + config->timingConfig.dataseg2 = 0x3U; + config->timingConfig.datarJumpwidth = 0x3U; +#endif +} + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate + * + * @param baudRate The canfd bus data speed in bps + * @param tqNum Number of time quanta per bit, range in 3 ~ 33 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp, seg1Temp; + + /* get ideal sample point. */ + if (baudRateFD <= 1000000U) + { + ideal_sp = IDEAL_DATA_SP_1; + } + else if (baudRateFD <= 2000000U) + { + ideal_sp = IDEAL_DATA_SP_2; + } + else if (baudRateFD <= 4000000U) + { + ideal_sp = IDEAL_DATA_SP_3; + } + else + { + ideal_sp = IDEAL_DATA_SP_4; + } + /* distribute time quanta. */ + pconfig->dataseg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); + + if (pconfig->dataseg2 > MAX_DTSEG2) + { + pconfig->dataseg2 = MAX_DTSEG2; + } + + seg1Temp = tqNum - pconfig->dataseg2 - 3U; + + if (seg1Temp > MAX_DTSEG1) + { + pconfig->dataseg2 = (uint8_t)(tqNum - MAX_DTSEG1 - 3U); + pconfig->dataseg1 = MAX_DTSEG1; + } + else + { + pconfig->dataseg1 = (uint8_t)seg1Temp; + } + + /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ + pconfig->datarJumpwidth = (pconfig->dataseg1 > pconfig->dataseg2) ? pconfig->dataseg2 : pconfig->dataseg1; + if (pconfig->datarJumpwidth > (uint8_t)MAX_DSJW) + { + pconfig->datarJumpwidth = (uint8_t)MAX_DSJW; + } +} + +/*! + * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The calculation is based on the recommendation of the CiA 1301 v1.0.0 document. + * + * param baudRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pconfig Pointer to the MCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool MCAN_CalculateImprovedNominalTimingValues(uint32_t baudRate, + uint32_t sourceClock_Hz, + mcan_timing_config_t *pconfig) +{ + uint32_t clk; /* the clock is tqNumb x baudRate. */ + uint32_t tqNum; /* Numbers of TQ. */ + uint32_t seg1Temp; + bool fgRet = false; + uint32_t spTemp = 1000U; + mcan_timing_config_t configTemp; + + /* Auto Improved Protocal timing for NBTP. */ + for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user + should change a divisible baud rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); + if (configTemp.preDivider > MAX_NBRP) + { + break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could + not handle it. */ + } + /* Calculates the best timing configuration under current tqNum. */ + configTemp.seg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR - 1U); + + if (configTemp.seg2 > MAX_NTSEG2) + { + configTemp.seg2 = MAX_NTSEG2; + } + + seg1Temp = tqNum - configTemp.seg2 - 3U; + + if (seg1Temp > MAX_NTSEG1) + { + configTemp.seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); + configTemp.seg1 = MAX_NTSEG1; + } + else + { + configTemp.seg1 = (uint8_t)seg1Temp; + } + + /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ + configTemp.rJumpwidth = (configTemp.seg1 > configTemp.seg2) ? configTemp.seg2 : configTemp.seg1; + if (configTemp.rJumpwidth > (uint8_t)MAX_NSJW) + { + configTemp.rJumpwidth = (uint8_t)MAX_NSJW; + } + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; + pconfig->preDivider = configTemp.preDivider; + pconfig->rJumpwidth = configTemp.rJumpwidth; + pconfig->seg1 = configTemp.seg1; + pconfig->seg2 = configTemp.seg2; + } + fgRet = true; + } + return fgRet; +} +/*! + * brief Calculates the improved timing values by specific baudrates for CANFD + * + * param baudRate The CANFD bus control speed in bps defined by user + * param baudRateFD The CANFD bus data speed in bps defined by user + * param sourceClock_Hz The Source clock data speed in bps. + * param pconfig Pointer to the MCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, + uint32_t baudRateFD, + uint32_t sourceClock_Hz, + mcan_timing_config_t *pconfig) +{ + uint32_t clk; + uint32_t tqNum; /* Numbers of TQ. */ + bool fgRet = false; + uint16_t preDividerTemp = 1U; + /* observe baud rate maximums */ + assert(baudRate <= MAX_CAN_BAUDRATE); + assert(baudRateFD <= MAX_CANFD_BAUDRATE); + /* Data phase bit rate need greater or equal to nominal phase bit rate. */ + assert(baudRate <= baudRateFD); + + if (baudRate < baudRateFD) + { + /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase + and data phase. */ + while (MCAN_CalculateImprovedNominalTimingValues(baudRate, sourceClock_Hz / preDividerTemp, pconfig)) + { + pconfig->datapreDivider = 0U; + for (tqNum = DBTP_MAX_TIME_QUANTA; tqNum >= DBTP_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRateFD * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNumbrs too large, clk x tqNumbrs has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate. */ + } + + pconfig->datapreDivider = (uint16_t)(sourceClock_Hz / clk - 1U); + + if (pconfig->datapreDivider > MAX_DBRP) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider + could not handle it. */ + } + + if (pconfig->datapreDivider < ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) + { + continue; /* try to get the same bit rate prescaler value for nominal phase and data phase. */ + } + else if (pconfig->datapreDivider == ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) + { + /* Calculates the best data phase timing configuration under current tqNum. */ + MCAN_FDGetSegments(baudRateFD, tqNum, pconfig); + fgRet = true; + break; + } + else + { + break; + } + } + + if (fgRet) + { + /* Find same bit rate prescaler (BRP) configuration in both nominal and data bit timing configurations. + */ + pconfig->preDivider = (pconfig->preDivider + 1U) * preDividerTemp - 1U; + break; + } + else + { + if ((pconfig->datapreDivider <= MAX_DBRP) && (pconfig->datapreDivider != 0U)) + { + /* Can't find same data bit rate prescaler (BRP) configuration under current nominal phase bit rate + prescaler, double the nominal phase bit rate prescaler and recalculate. */ + preDividerTemp++; + } + else + { + break; + } + } + } + } + else + { + if (MCAN_CalculateImprovedTimingValues(baudRate, sourceClock_Hz, pconfig)) + { + /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs + feature. */ + pconfig->datapreDivider = 0U; + pconfig->datarJumpwidth = 0U; + pconfig->dataseg1 = 0U; + pconfig->dataseg2 = 0U; + fgRet = true; + } + } + + return fgRet; +} + +/*! + * brief Sets the MCAN protocol data phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default data phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * param base MCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ +void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Cleaning previous Timing Setting. */ + base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->DBTP |= (CAN_DBTP_DBRP(config->datapreDivider) | CAN_DBTP_DSJW(config->datarJumpwidth) | + CAN_DBTP_DTSEG1(config->dataseg1) | CAN_DBTP_DTSEG2(config->dataseg2)); +} +#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN + * + * @param baudRate The data speed in bps + * @param tqNum Number of time quantas per bit, range in 4~385 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp, seg1Temp; + + /* get ideal sample point. */ + if (baudRate >= 1000000U) + { + ideal_sp = IDEAL_SP_LOW; + } + else if (baudRate >= 800000U) + { + ideal_sp = IDEAL_SP_MID; + } + else + { + ideal_sp = IDEAL_SP_HIGH; + } + + /* distribute time quanta. */ + pconfig->seg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); + + if (pconfig->seg2 > MAX_NTSEG2) + { + pconfig->seg2 = MAX_NTSEG2; + } + + seg1Temp = tqNum - pconfig->seg2 - 3U; + + if (seg1Temp > MAX_NTSEG1) + { + pconfig->seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); + pconfig->seg1 = MAX_NTSEG1; + } + else + { + pconfig->seg1 = (uint8_t)seg1Temp; + } + + /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ + pconfig->rJumpwidth = (pconfig->seg1 > pconfig->seg2) ? pconfig->seg2 : pconfig->seg1; + if (pconfig->rJumpwidth > (uint8_t)MAX_NSJW) + { + pconfig->rJumpwidth = (uint8_t)MAX_NSJW; + } +} + +/*! + * @brief Calculates the improved timing values by specific baudrates for classical CAN + * + * @param baudRate The classical CAN speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the MCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig) +{ + uint32_t clk; /* the clock is tqNumb x baudRate. */ + uint32_t tqNum; /* Numbers of TQ. */ + bool fgRet = false; + uint32_t spTemp = 1000U; + mcan_timing_config_t configTemp = {0}; + /* observe baud rate maximums. */ + assert(baudRate <= MAX_CAN_BAUDRATE); + + /* Auto Improved Protocal timing for NBTP. */ + for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user + should change a divisible baud rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); + if (configTemp.preDivider > MAX_NBRP) + { + break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could + not handle it. */ + } + /* Calculates the best timing configuration under current tqNum. */ + MCAN_GetSegments(baudRate, tqNum, &configTemp); + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; + pconfig->preDivider = configTemp.preDivider; + pconfig->rJumpwidth = configTemp.rJumpwidth; + pconfig->seg1 = configTemp.seg1; + pconfig->seg2 = configTemp.seg2; + } + fgRet = true; + } + return fgRet; +} + +/*! + * brief Sets the MCAN protocol arbitration phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default arbitration phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * param base MCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ +void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Cleaning previous Timing Setting. */ + base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) | + CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2)); +} + +/*! + * brief Set filter configuration. + * + * This function sets remote and non masking frames in global filter configuration, + * also the start address, list size in standard/extended ID filter configuration. + * + * param base MCAN peripheral base address. + * param config The MCAN filter configuration. + */ +void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config) +{ + /* Set global configuration of remote/nonmasking frames, set filter address and list size. */ + if (config->idFormat == kMCAN_FrameIDStandard) + { + base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame); + base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize); + } + else + { + base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame); + base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize); + } +} + +/*! + * brief Configures an MCAN receive fifo 0 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 0. + * + * param base MCAN peripheral base address. + * param config The receive fifo 0 configuration structure. + */ +void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) +{ + /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */ + base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) | + CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode); + /* Set Rx FIFO 0 data field size */ + base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize); +} + +/*! + * brief Configures an MCAN receive fifo 1 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 1. + * + * param base MCAN peripheral base address. + * param config The receive fifo 1 configuration structure. + */ +void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) +{ + /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */ + base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) | + CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode); + /* Set Rx FIFO 1 data field size */ + base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize); +} + +/*! + * brief Configures an MCAN receive buffer. + * + * This function sets start address and datafield size of the recieve buffer. + * + * param base MCAN peripheral base address. + * param config The receive buffer configuration structure. + */ +void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config) +{ + /* Set Rx Buffer start address. */ + base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT); + /* Set Rx Buffer data field size */ + base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize); +} + +/*! + * brief Configures an MCAN transmit event fifo. + * + * This function sets start address, element size, watermark of the transmit event fifo. + * + * param base MCAN peripheral base address. + * param config The transmit event fifo configuration structure. + */ +void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config) +{ + /* Set TX Event FIFO start address, element size, watermark. */ + base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) | + CAN_TXEFC_EFWM(config->watermark); +} + +/*! + * brief Configures an MCAN transmit buffer. + * + * This function sets start address, element size, fifo/queue mode and datafield + * size of the transmit buffer. + * + * param base MCAN peripheral base address. + * param config The transmit buffer configuration structure. + */ +void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config) +{ + assert((config->dedicatedSize + config->fqSize) <= 32U); + + /* Set Tx Buffer start address, size, fifo/queue mode. */ + base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) | + CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode); + /* Set Tx Buffer data field size */ + base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize); +} + +/*! + * brief Set standard message ID filter element configuration. + * + * param base MCAN peripheral base address. + * param config The MCAN filter configuration. + * param filter The MCAN standard message ID filter element configuration. + * param idx The standard message ID filter element index. + */ +void MCAN_SetSTDFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_std_filter_element_config_t *filter, + uint8_t idx) +{ + uint32_t *elementAddress = NULL; + elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U); + (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_std_filter_element_config_t)); +} + +/*! + * brief Set extended message ID filter element configuration. + * + * param base MCAN peripheral base address. + * param config The MCAN filter configuration. + * param filter The MCAN extended message ID filter element configuration. + * param idx The extended message ID filter element index. + */ +void MCAN_SetEXTFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_ext_filter_element_config_t *filter, + uint8_t idx) +{ + uint32_t *elementAddress = NULL; + elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U); + (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_ext_filter_element_config_t)); +} + +static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base) +{ + uint32_t eSize; + uint32_t eAddress; + eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + eAddress = base->RXF0C & CAN_RXF0C_F0SA_MASK; + eAddress += ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U; + return eAddress; +} + +static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base) +{ + uint32_t eSize; + uint32_t eAddress; + eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + eAddress = base->RXF1C & CAN_RXF1C_F1SA_MASK; + eAddress += ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U; + return eAddress; +} + +static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 63U); + uint32_t eSize; + eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U; +} + +static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 31U); + uint32_t eSize; + eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U; +} + +/*! + * brief Gets the Tx buffer request pending status. + * + * This function returns Tx Message Buffer transmission request pending status. + * + * param base MCAN peripheral base address. + * param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx) +{ + return (base->TXBRP & ((uint32_t)1U << idx)) >> (uint32_t)idx; +} + +/*! + * brief Gets the Tx buffer transmission occurred status. + * + * This function returns Tx Message Buffer transmission occurred status. + * + * param base MCAN peripheral base address. + * param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx) +{ + return (base->TXBTO & ((uint32_t)1U << idx)) >> (uint32_t)idx; +} + +/*! + * brief Writes an MCAN Message to the Transmit Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base MCAN peripheral base address. + * param idx The MCAN Tx Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + */ +status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(NULL != pTxFrame); + + status_t status; + uint8_t *elementAddress = NULL; + uint8_t *elementPayloadAddress = NULL; + + if (0U == MCAN_IsTransmitRequestPending(base, idx)) + { + elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx)); + elementPayloadAddress = (uint8_t *)((uint32_t)elementAddress + 8U); + + /* Write 2 words configuration field. */ + (void)memcpy(elementAddress, (const uint8_t *)pTxFrame, 8U); + /* Write data field. */ + (void)memcpy(elementPayloadAddress, pTxFrame->data, pTxFrame->size); + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Reads an MCAN Message from Rx Buffer. + * + * This function reads a CAN message from the Rx Buffer in the Message RAM. + * + * param base MCAN peripheral base address. + * param idx The MCAN Rx Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx Buffer successfully. + */ +status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + mcan_rx_buffer_frame_t *elementAddress = NULL; + uint32_t u4PayloadLength = (uint32_t)(pRxFrame->size) + 8U; + + elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx)); + (void)memcpy((void *)pRxFrame, (void *)elementAddress, u4PayloadLength); + + return kStatus_Success; +} + +/*! + * brief Reads an MCAN Message from Rx FIFO. + * + * This function reads a CAN message from the Rx FIFO in the Message RAM. + * + * param base MCAN peripheral base address. + * param fifoBlock Rx FIFO block 0 or 1. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + */ +status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) +{ + /* Assertion. */ + assert((0U == fifoBlock) || (1U == fifoBlock)); + assert(NULL != pRxFrame); + + mcan_rx_buffer_frame_t *elementAddress = NULL; + if (0U == fifoBlock) + { + elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base)); + } + else + { + elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base)); + } + (void)memcpy(pRxFrame, elementAddress, 8U); + pRxFrame->data = (uint8_t *)((uint32_t)elementAddress + 8U); + /* Acknowledge the read. */ + if (0U == fifoBlock) + { + base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT; + } + else + { + base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT; + } + return kStatus_Success; +} + +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base MCAN peripheral base pointer. + * param idx The MCAN buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame) +{ + status_t status; + + if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, pTxFrame)) + { + MCAN_TransmitAddRequest(base, idx); + + /* Wait until message sent out. */ + while (0U == MCAN_IsTransmitOccurred(base, idx)) + { + } + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base MCAN peripheral base pointer. + * param idx The MCAN buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Rx Message Buffer Successfully. + * retval kStatus_Fail - No new message. + */ +status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) +{ + assert(idx <= 63U); + + status_t status = kStatus_Success; + +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + uint32_t u4Retry = MCAN_RETRY_TIMES; +#endif + + while (!MCAN_GetRxBufferStatusFlag(base, idx)) + { +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (0U == u4Retry--) + { + status = kStatus_Fail; + } +#endif + } +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (kStatus_Success == status) +#endif + { + MCAN_ClearRxBufferStatusFlag(base, idx); + status = MCAN_ReadRxBuffer(base, idx, pRxFrame); + } + + return status; +} + +/*! + * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base MCAN peripheral base pointer. + * param fifoBlock Rx FIFO block, 0 or 1. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - No new message in Rx FIFO. + */ +status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) +{ + assert((0U == fifoBlock) || (1U == fifoBlock)); + + status_t status = kStatus_Success; + uint32_t maskCanIR; +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + uint32_t u4Retry = MCAN_RETRY_TIMES; +#endif + + maskCanIR = (0U == fifoBlock) ? CAN_IR_RF0N_MASK : CAN_IR_RF1N_MASK; + + while (0U == MCAN_GetStatusFlag(base, maskCanIR)) + { +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (0U == u4Retry--) + { + status = kStatus_Fail; + } +#endif + } + +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (kStatus_Success == status) +#endif + { + MCAN_ClearStatusFlag(base, maskCanIR); + status = MCAN_ReadRxFifo(base, fifoBlock, pRxFrame); + } + + return status; +} + +/*! + * brief Initializes the MCAN handle. + * + * This function initializes the MCAN handle, which can be used for other MCAN + * transactional APIs. Usually, for a specified MCAN instance, + * call this API once to get the initialized handle. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData) +{ + assert(NULL != handle); + + uint8_t instance; + + /* Clean MCAN transfer handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = (uint8_t)MCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_mcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_mcanIsr = MCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of MCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + MCAN_EnableInterrupts(base, 0U, + (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | + (uint32_t)kMCAN_WarningInterruptEnable); + } + else + { + MCAN_DisableInterrupts(base, (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | + (uint32_t)kMCAN_WarningInterruptEnable); + } + + /* Enable interrupts in NVIC. */ + (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0])); + (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1])); +} + +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. + * retval kStatus_Success Start Tx Buffer sending process successfully. + * retval kStatus_Fail Write Tx Buffer failed. + * retval kStatus_MCAN_TxBusy Tx Buffer is in use. + */ +status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + assert(xfer->bufferIdx <= 63U); + + status_t status; + + /* Check if Tx Buffer is idle. */ + if ((uint8_t)kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx]) + { + handle->txbufferIdx = xfer->bufferIdx; + /* Distinguish transmit type. */ + if ((uint8_t)kMCAN_FrameTypeRemote == xfer->frame->xtd) + { + handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxRemote; + + /* Register user Frame buffer to receive remote Frame. */ + handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame; + } + else + { + handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxData; + } + + if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame)) + { + /* Enable Buffer Interrupt. */ + MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx); + MCAN_EnableInterrupts(base, 0U, CAN_IE_TCE_MASK); + + MCAN_TransmitAddRequest(base, xfer->bufferIdx); + + status = kStatus_Success; + } + else + { + handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_MCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param fifoBlock Rx FIFO block, 0 or 1. + * param xfer MCAN Rx FIFO transfer structure. See the ref mcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. + * retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. + */ +status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + uint8_t fifoBlock, + mcan_handle_t *handle, + mcan_fifo_transfer_t *xfer) +{ + /* Assertion. */ + assert((0U == fifoBlock) || (1U == fifoBlock)); + assert(NULL != handle); + assert(NULL != xfer); + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kMCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kMCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = xfer->frame; + + /* Enable FIFO Interrupt. */ + if (1U == fifoBlock) + { + MCAN_EnableInterrupts(base, 0U, CAN_IE_RF1NE_MASK); + } + else + { + MCAN_EnableInterrupts(base, 0U, CAN_IE_RF0NE_MASK); + } + status = kStatus_Success; + } + else + { + status = (1U == fifoBlock) ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy; + } + + return status; +} + +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param bufferIdx The MCAN Buffer index. + */ +void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(bufferIdx <= 63U); + + /* Disable Buffer Interrupt. */ + MCAN_DisableTransmitBufferInterrupts(base, bufferIdx); + MCAN_DisableInterrupts(base, CAN_IE_TCE_MASK); + + /* Cancel send request. */ + MCAN_TransmitCancelRequest(base, bufferIdx); + + /* Un-register handle. */ + handle->bufferFrameBuf[bufferIdx] = NULL; + + handle->bufferState[bufferIdx] = (uint8_t)kMCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base MCAN peripheral base address. + * param fifoBlock MCAN Fifo block, 0 or 1. + * param handle MCAN handle pointer. + */ +void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + assert((0U == fifoBlock) || (1U == fifoBlock)); + + /* Check if Rx FIFO is enabled. */ + if (1U == fifoBlock) + { + /* Disable Rx Message FIFO Interrupts. */ + MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK); + } + else + { + MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK); + } + /* Un-register handle. */ + handle->rxFifoFrameBuf = NULL; + + handle->rxFifoState = (uint8_t)kMCAN_StateIdle; +} + +/*! + * brief MCAN IRQ handle function. + * + * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + */ +void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + status_t status = kStatus_MCAN_UnHandled; + uint32_t valueIR; + uint32_t result; + + /* Store Current MCAN Module Error and Status. */ + valueIR = base->IR; + + do + { + if (0U != (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | + (uint32_t)kMCAN_BusOffIntFlag))) + { + /* Solve error. */ + result = (uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | + (uint32_t)kMCAN_BusOffIntFlag; + status = kStatus_MCAN_ErrorStatus; + } + else if (0U != (valueIR & (uint32_t)kMCAN_TxTransmitCompleteFlag)) + { + /* Solve Tx interrupt. */ + result = (uint32_t)kMCAN_TxTransmitCompleteFlag; + status = kStatus_MCAN_TxIdle; + MCAN_TransferAbortSend(base, handle, handle->txbufferIdx); + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0NewFlag)) + { + (void)MCAN_ReadRxFifo(base, 0U, handle->rxFifoFrameBuf); + result = (uint32_t)kMCAN_RxFifo0NewFlag; + status = kStatus_MCAN_RxFifo0Idle; + MCAN_TransferAbortReceiveFifo(base, 0U, handle); + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0LostFlag)) + { + result = (uint32_t)kMCAN_RxFifo0LostFlag; + status = kStatus_MCAN_RxFifo0Lost; + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1NewFlag)) + { + (void)MCAN_ReadRxFifo(base, 1U, handle->rxFifoFrameBuf); + result = (uint32_t)kMCAN_RxFifo1NewFlag; + status = kStatus_MCAN_RxFifo1Idle; + MCAN_TransferAbortReceiveFifo(base, 1U, handle); + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1LostFlag)) + { + result = (uint32_t)kMCAN_RxFifo1LostFlag; + status = kStatus_MCAN_RxFifo0Lost; + } + else + { + /* Handle the interrupt flag unsupported in current version of MCAN driver. + * User can get these unsupported interrupt flags by callback function, + * we can clear directly in the handler to prevent endless loop. + */ + result = valueIR; + result &= ~((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | + (uint32_t)kMCAN_BusOffIntFlag | (uint32_t)kMCAN_TxTransmitCompleteFlag | + (uint32_t)kMCAN_RxFifo0NewFlag | (uint32_t)kMCAN_RxFifo0LostFlag | + (uint32_t)kMCAN_RxFifo1NewFlag | (uint32_t)kMCAN_RxFifo1LostFlag); + } + + /* Clear Error interrupt, resolved Rx FIFO, Tx Buffer IRQ and other unsupported interrupt flags. */ + MCAN_ClearStatusFlag(base, result); + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + + /* Reset return status */ + status = kStatus_MCAN_UnHandled; + + /* Store Current MCAN Module Error and Status. */ + valueIR = base->IR; + } while (0U != valueIR); +} + +#if defined(CAN0) +void CAN0_IRQ0_DriverIRQHandler(void); +void CAN0_IRQ0_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[0]); + + s_mcanIsr(CAN0, s_mcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} + +void CAN0_IRQ1_DriverIRQHandler(void); +void CAN0_IRQ1_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[0]); + + s_mcanIsr(CAN0, s_mcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN1) +void CAN1_IRQ0_DriverIRQHandler(void); +void CAN1_IRQ0_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[1]); + + s_mcanIsr(CAN1, s_mcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} + +void CAN1_IRQ1_DriverIRQHandler(void); +void CAN1_IRQ1_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[1]); + + s_mcanIsr(CAN1, s_mcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.h new file mode 100644 index 0000000000000000000000000000000000000000..88080fb907de6e70e103446d507c7ce92675010d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mcan.h @@ -0,0 +1,1032 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MCAN_H_ +#define _FSL_MCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mcan + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief MCAN driver version. */ +#define FSL_MCAN_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +#ifndef MCAN_RETRY_TIMES +/* Define to 0 by default means to retry infinitely until the flag is assert/de-assert. + * User can change the macro with their requirement by defined the MACRO. + */ +#define MCAN_RETRY_TIMES (0U) +#endif + +/*! @brief MCAN transfer status. */ +enum +{ + kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0), /*!< Tx Buffer is Busy. */ + kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1), /*!< Tx Buffer is Idle. */ + kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2), /*!< Rx Buffer is Busy. */ + kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3), /*!< Rx Buffer is Idle. */ + kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4), /*!< New message written to Rx FIFO 0. */ + kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5), /*!< Rx FIFO 0 is Idle. */ + kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6), /*!< Rx FIFO 0 fill level reached watermark. */ + kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7), /*!< Rx FIFO 0 full. */ + kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8), /*!< Rx FIFO 0 message lost. */ + kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9), /*!< New message written to Rx FIFO 1. */ + kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10), /*!< Rx FIFO 1 is Idle. */ + kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */ + kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12), /*!< Rx FIFO 1 full. */ + kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13), /*!< Rx FIFO 1 message lost. */ + kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14), /*!< Rx FIFO 0 is busy. */ + kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15), /*!< Rx FIFO 1 is busy. */ + kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16), /*!< MCAN Module Error and Status. */ + kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17), /*!< UnHadled Interrupt asserted. */ +}; + +/*! + * @brief MCAN status flags. + * + * This provides constants for the MCAN status flags for use in the MCAN functions. + * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to + * read MCAN_ErrorFlag and distinguish which error is occur using + * _mcan_error_flags enumerations. + */ +enum _mcan_flags +{ + kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK, /*!< CAN Synchronization Status. */ + kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */ + kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */ + kMCAN_BusOffIntFlag = CAN_IR_BO_MASK, /*!< Tx Error Warning Status. */ + kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK, /*!< Rx Error Warning Status. */ + kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK, /*!< Rx Error Warning Status. */ +}; + +/*! + * @brief MCAN Rx FIFO status flags. + * + * The MCAN Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. + */ +enum _mcan_rx_fifo_flags +{ + kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK, /*!< Rx FIFO 0 new message flag. */ + kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ + kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK, /*!< Rx FIFO 0 full flag. */ + kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK, /*!< Rx FIFO 0 message lost flag. */ + kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK, /*!< Rx FIFO 0 new message flag. */ + kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ + kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK, /*!< Rx FIFO 0 full flag. */ + kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK, /*!< Rx FIFO 0 message lost flag. */ +}; + +/*! + * @brief MCAN Tx status flags. + * + * The MCAN Tx Status enumerations are used to determine the status of the + * Tx Buffer/Event FIFO. + */ +enum _mcan_tx_flags +{ + kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK, /*!< Transmission completed flag. */ + kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */ + kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK, /*!< Tx Event FIFO element lost. */ + kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK, /*!< Tx Event FIFO full. */ + kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK, /*!< Tx Event FIFO fill level reached watermark. */ + kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK, /*!< Tx Handler wrote Tx Event FIFO element flag. */ + kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK, /*!< Tx FIFO empty flag. */ +}; + +/*! + * @brief MCAN interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the MCAN Module interrupt configurations. + */ +enum _mcan_interrupt_enable +{ + kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK, /*!< Bus Off interrupt. */ + kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK, /*!< Error interrupt. */ + kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */ +}; + +/*! @brief MCAN frame format. */ +typedef enum _mcan_frame_idformat +{ + kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */ + kMCAN_FrameIDExtend = 0x1U, /*!< Extend frame format attribute. */ +} mcan_frame_idformat_t; + +/*! @brief MCAN frame type. */ +typedef enum _mcan_frame_type +{ + kMCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} mcan_frame_type_t; + +/*! @brief MCAN frame datafield size. */ +typedef enum _mcan_bytes_in_datafield +{ + kMCAN_8ByteDatafield = 0x0U, /*!< 8 byte data field. */ + kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */ + kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */ + kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */ + kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */ + kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */ + kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */ + kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */ +} mcan_bytes_in_datafield_t; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief MCAN Tx Buffer structure. */ +typedef struct _mcan_tx_buffer_frame +{ + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier. */ + uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ + uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ + }; + struct + { + uint32_t : 16; + uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 + Number of data bytes 12 16 20 24 32 48 64 */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t fdf : 1; /*!< CAN FD format. */ + uint32_t : 1; /*!< Reserved. */ + uint32_t efc : 1; /*!< Event FIFO control. */ + uint32_t mm : 8; /*!< Message Marker. */ + }; + uint8_t *data; + uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ +} mcan_tx_buffer_frame_t; + +/*! @brief MCAN Rx FIFO/Buffer structure. */ +typedef struct _mcan_rx_buffer_frame +{ + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier. */ + uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ + uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ + }; + struct + { + uint32_t rxts : 16; /*!< Rx Timestamp. */ + uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 + Number of data bytes 12 16 20 24 32 48 64 */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t fdf : 1; /*!< CAN FD format. */ + uint32_t : 2; /*!< Reserved. */ + uint32_t fidx : 7; /*!< Filter Index. */ + uint32_t anmf : 1; /*!< Accepted Non-matching Frame. */ + }; + uint8_t *data; + uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ +} mcan_rx_buffer_frame_t; + +/*! @brief MCAN Rx FIFO block number. */ +typedef enum _mcan_fifo_type +{ + kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */ + kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */ +} mcan_fifo_type_t; + +/*! @brief MCAN FIFO Operation Mode. */ +typedef enum _mcan_fifo_opmode_config +{ + kMCAN_FifoBlocking = 0x0U, /*!< FIFO blocking mode. */ + kMCAN_FifoOverwrite = 0x1U, /*!< FIFO overwrite mode. */ +} mcan_fifo_opmode_config_t; + +/*! @brief MCAN Tx FIFO/Queue Mode. */ +typedef enum _mcan_txmode_config +{ + kMCAN_txFifo = 0x0U, /*!< Tx FIFO operation. */ + kMCAN_txQueue = 0x1U, /*!< Tx Queue operation. */ +} mcan_txmode_config_t; + +/*! @brief MCAN remote frames treatment. */ +typedef enum _mcan_remote_frame_config +{ + kMCAN_filterFrame = 0x0U, /*!< Filter remote frames. */ + kMCAN_rejectFrame = 0x1U, /*!< Reject all remote frames. */ +} mcan_remote_frame_config_t; + +/*! @brief MCAN non-masking frames treatment. */ +typedef enum _mcan_nonmasking_frame_config +{ + kMCAN_acceptinFifo0 = 0x0U, /*!< Accept non-masking frames in Rx FIFO 0. */ + kMCAN_acceptinFifo1 = 0x1U, /*!< Accept non-masking frames in Rx FIFO 1. */ + kMCAN_reject0 = 0x2U, /*!< Reject non-masking frames. */ + kMCAN_reject1 = 0x3U, /*!< Reject non-masking frames. */ +} mcan_nonmasking_frame_config_t; + +/*! @brief MCAN Filter Element Configuration. */ +typedef enum _mcan_fec_config +{ + kMCAN_disable = 0x0U, /*!< Disable filter element. */ + kMCAN_storeinFifo0 = 0x1U, /*!< Store in Rx FIFO 0 if filter matches. */ + kMCAN_storeinFifo1 = 0x2U, /*!< Store in Rx FIFO 1 if filter matches. */ + kMCAN_reject = 0x3U, /*!< Reject ID if filter matches. */ + kMCAN_setprio = 0x4U, /*!< Set priority if filter matches. */ + kMCAN_setpriofifo0 = 0x5U, /*!< Set priority and store in FIFO 0 if filter matches. */ + kMCAN_setpriofifo1 = 0x6U, /*!< Set priority and store in FIFO 1 if filter matches. */ + kMCAN_storeinbuffer = 0x7U, /*!< Store into Rx Buffer or as debug message. */ +} mcan_fec_config_t; + +/*! @brief MCAN Rx FIFO configuration. */ +typedef struct _mcan_rx_fifo_config +{ + uint32_t address; /*!< FIFOn start address. */ + uint32_t elementSize; /*!< FIFOn element number. */ + uint32_t watermark; /*!< FIFOn watermark level. */ + mcan_fifo_opmode_config_t opmode; /*!< FIFOn blocking/overwrite mode. */ + mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ +} mcan_rx_fifo_config_t; + +/*! @brief MCAN Rx Buffer configuration. */ +typedef struct _mcan_rx_buffer_config +{ + uint32_t address; /*!< Rx Buffer start address. */ + mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ +} mcan_rx_buffer_config_t; + +/*! @brief MCAN Tx Event FIFO configuration. */ +typedef struct _mcan_tx_fifo_config +{ + uint32_t address; /*!< Event fifo start address. */ + uint32_t elementSize; /*!< FIFOn element number. */ + uint32_t watermark; /*!< FIFOn watermark level. */ +} mcan_tx_fifo_config_t; + +/*! @brief MCAN Tx Buffer configuration. */ +typedef struct _mcan_tx_buffer_config +{ + uint32_t address; /*!< Tx Buffers Start Address. */ + uint32_t dedicatedSize; /*!< Number of Dedicated Transmit Buffers. */ + uint32_t fqSize; /*!< Transmit FIFO/Queue Size. */ + mcan_txmode_config_t mode; /*!< Tx FIFO/Queue Mode.*/ + mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ +} mcan_tx_buffer_config_t; + +/*! @brief MCAN Filter Type. */ +typedef enum _mcan_std_filter_type +{ + kMCAN_range = 0x0U, /*!< Range filter from SFID1 to SFID2. */ + kMCAN_dual = 0x1U, /*!< Dual ID filter for SFID1 or SFID2. */ + kMCAN_classic = 0x2U, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ + kMCAN_disableORrange2 = 0x3U, /*!< Filter element disabled for standard filter + or Range filter, XIDAM mask not applied for extended filter. */ +} mcan_filter_type_t; + +/*! @brief MCAN Standard Message ID Filter Element. */ +typedef struct _mcan_std_filter_element_config +{ + uint32_t sfid2 : 11; /*!< Standard Filter ID 2. */ + uint32_t : 5; /*!< Reserved. */ + uint32_t sfid1 : 11; /*!< Standard Filter ID 1. */ + uint32_t sfec : 3; /*!< Standard Filter Element Configuration. */ + uint32_t sft : 2; /*!< Standard Filter Type. */ +} mcan_std_filter_element_config_t; + +/*! @brief MCAN Extended Message ID Filter Element. */ +typedef struct _mcan_ext_filter_element_config +{ + uint32_t efid1 : 29; /*!< Extended Filter ID 1. */ + uint32_t efec : 3; /*!< Extended Filter Element Configuration. */ + uint32_t efid2 : 29; /*!< Extended Filter ID 2. */ + uint32_t : 1; /*!< Reserved. */ + uint32_t eft : 2; /*!< Extended Filter Type. */ +} mcan_ext_filter_element_config_t; + +/*! @brief MCAN Rx filter configuration. */ +typedef struct _mcan_frame_filter_config +{ + uint32_t address; /*!< Filter start address. */ + uint32_t listSize; /*!< Filter list size. */ + mcan_frame_idformat_t idFormat; /*!< Frame format. */ + mcan_remote_frame_config_t remFrame; /*!< Remote frame treatment. */ + mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */ +} mcan_frame_filter_config_t; + +/*! @brief MCAN protocol timing characteristic configuration structure. */ +typedef struct _mcan_timing_config +{ + uint16_t preDivider; /*!< Nominal Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Nominal Re-sync Jump Width. */ + uint8_t seg1; /*!< Nominal Time Segment 1. */ + uint8_t seg2; /*!< Nominal Time Segment 2. */ +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) + uint16_t datapreDivider; /*!< Data Clock Pre-scaler Division Factor. */ + uint8_t datarJumpwidth; /*!< Data Re-sync Jump Width. */ + uint8_t dataseg1; /*!< Data Time Segment 1. */ + uint8_t dataseg2; /*!< Data Time Segment 2. */ +#endif +} mcan_timing_config_t; + +/*! @brief MCAN module configuration structure. */ +typedef struct _mcan_config +{ + uint32_t baudRateA; /*!< Baud rate of Arbitration phase in bps. */ + uint32_t baudRateD; /*!< Baud rate of Data phase in bps. */ + bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */ + bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */ + bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */ + bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */ + bool enableBusMon; /*!< Enable or Disable Bus Monitoring Mode. */ + mcan_timing_config_t timingConfig; /*!< Protocol timing . */ +} mcan_config_t; + +/*! @brief MCAN Buffer transfer. */ +typedef struct _mcan_buffer_transfer +{ + mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t bufferIdx; /*!< The index of Message buffer used to transfer Message. */ +} mcan_buffer_transfer_t; + +/*! @brief MCAN Rx FIFO transfer. */ +typedef struct _mcan_fifo_transfer +{ + mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ +} mcan_fifo_transfer_t; + +/*! @brief MCAN handle structure definition. */ +typedef struct _mcan_handle mcan_handle_t; + +/*! @brief MCAN transfer callback function. + * + * The MCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of + * MCAN status register which can be used to get the working status(or error status) of MCAN module. + * If the status equals to other MCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +typedef void (*mcan_transfer_callback_t)( + CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData); + +/*! @brief MCAN handle structure. */ +struct _mcan_handle +{ + mcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< MCAN callback function parameter.*/ + mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */ + mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ + volatile uint8_t txbufferIdx; /*!< Message Buffer transfer state. */ + volatile uint8_t bufferState[64]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an MCAN instance. + * + * This function initializes the MCAN module with user-defined settings. + * This example shows how to set up the mcan_config_t parameters and how + * to call the MCAN_Init function by passing in these parameters. + * @code + * mcan_config_t config; + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * MCAN_Init(CANFD0, &config, 8000000UL); + * @endcode + * + * @param base MCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. + */ +void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes an MCAN instance. + * + * This function deinitializes the MCAN module. + * + * @param base MCAN peripheral base address. + */ +void MCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the MCAN configuration structure to default values. The default + * values are as follows. + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * + * @param config Pointer to the MCAN configuration structure. + */ +void MCAN_GetDefaultConfig(mcan_config_t *config); + +/*! + * @brief MCAN enters normal mode. + * + * After initialization, INIT bit in CCCR register must be cleared to enter + * normal mode thus synchronizes to the CAN bus and ready for communication. + * + * @param base MCAN peripheral base address. + */ +void MCAN_EnterNormalMode(CAN_Type *base); + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the MCAN Message RAM base address. + * + * This function sets the Message RAM base address. + * + * @param base MCAN peripheral base address. + * @param value Desired Message RAM base. + */ +static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value) +{ + assert(((value >= 0x20000000U) && (value <= 0x20027FFFU)) || ((value >= 0x04000000U) && (value <= 0x04007FFFU))); + + base->MRBA = CAN_MRBA_BA(value >> 16U); +} + +/*! + * @brief Gets the MCAN Message RAM base address. + * + * This function gets the Message RAM base address. + * + * @param base MCAN peripheral base address. + * @return Message RAM base address. + */ +static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base) +{ + return base->MRBA; +} + +/*! + * @brief Calculates the improved timing values by specific baudrates for classical CAN + * + * @param baudRate The classical CAN speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the MCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig); + +/*! + * @brief Sets the MCAN protocol arbitration phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default arbitration phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * @param base MCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +/*! + * @brief Calculates the improved timing values by specific baudrates for CANFD + * + * @param baudRate The CANFD bus control speed in bps defined by user + * @param baudRateFD The CANFD bus data speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. + * @param pconfig Pointer to the MCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, + uint32_t baudRateFD, + uint32_t sourceClock_Hz, + mcan_timing_config_t *pconfig); +/*! + * @brief Sets the MCAN protocol data phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default data phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * @param base MCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); +#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ + +/*! + * @brief Configures an MCAN receive fifo 0 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 0. + * + * @param base MCAN peripheral base address. + * @param config The receive fifo 0 configuration structure. + */ +void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); + +/*! + * @brief Configures an MCAN receive fifo 1 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 1. + * + * @param base MCAN peripheral base address. + * @param config The receive fifo 1 configuration structure. + */ +void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); + +/*! + * @brief Configures an MCAN receive buffer. + * + * This function sets start address and datafield size of the recieve buffer. + * + * @param base MCAN peripheral base address. + * @param config The receive buffer configuration structure. + */ +void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config); + +/*! + * @brief Configures an MCAN transmit event fifo. + * + * This function sets start address, element size, watermark of the transmit event fifo. + * + * @param base MCAN peripheral base address. + * @param config The transmit event fifo configuration structure. + */ +void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config); + +/*! + * @brief Configures an MCAN transmit buffer. + * + * This function sets start address, element size, fifo/queue mode and datafield + * size of the transmit buffer. + * + * @param base MCAN peripheral base address. + * @param config The transmit buffer configuration structure. + */ +void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config); + +/*! + * @brief Set filter configuration. + * + * This function sets remote and non masking frames in global filter configuration, + * also the start address, list size in standard/extended ID filter configuration. + * + * @param base MCAN peripheral base address. + * @param config The MCAN filter configuration. + */ +void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config); + +/*! + * @brief Set standard message ID filter element configuration. + * + * @param base MCAN peripheral base address. + * @param config The MCAN filter configuration. + * @param filter The MCAN standard message ID filter element configuration. + * @param idx The standard message ID filter element index. + */ +void MCAN_SetSTDFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_std_filter_element_config_t *filter, + uint8_t idx); + +/*! + * @brief Set extended message ID filter element configuration. + * + * @param base MCAN peripheral base address. + * @param config The MCAN filter configuration. + * @param filter The MCAN extended message ID filter element configuration. + * @param idx The extended message ID filter element index. + */ +void MCAN_SetEXTFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_ext_filter_element_config_t *filter, + uint8_t idx); + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the MCAN module interrupt flags. + * + * This function gets all MCAN interrupt status flags. + * + * @param base MCAN peripheral base address. + * @param mask The ORed MCAN interrupt mask. + * @return MCAN status flags which are ORed. + */ +static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask) +{ + return (base->IR & mask); +} + +/*! + * @brief Clears the MCAN module interrupt flags. + * + * This function clears MCAN interrupt status flags. + * + * @param base MCAN peripheral base address. + * @param mask The ORed MCAN interrupt mask. + */ +static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag, write 0 has no effect. */ + base->IR = mask; +} + +/*! + * @brief Gets the new data flag of specific Rx Buffer. + * + * This function gets new data flag of specific Rx Buffer. + * + * @param base MCAN peripheral base address. + * @param idx Rx Buffer index. + * @return Rx Buffer new data status flag. + */ +static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 63U); + + bool fgRet; + + if (idx <= 31U) + { + fgRet = (0U != (base->NDAT1 & ((uint32_t)1U << idx))); + } + else + { + fgRet = (0U != (base->NDAT2 & ((uint32_t)1U << (idx - 32U)))); + } + + return fgRet; +} + +/*! + * @brief Clears the new data flag of specific Rx Buffer. + * + * This function clears new data flag of specific Rx Buffer. + * + * @param base MCAN peripheral base address. + * @param idx Rx Buffer index. + */ +static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 63U); + + if (idx <= 31U) + { + base->NDAT1 &= ~((uint32_t)1U << idx); + } + else + { + base->NDAT2 &= ~((uint32_t)1U << (idx - 32U)); + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables MCAN interrupts according to the provided interrupt line and mask. + * + * This function enables the MCAN interrupts according to the provided interrupt line and mask. + * The mask is a logical OR of enumeration members. + * + * @param base MCAN peripheral base address. + * @param line Interrupt line number, 0 or 1. + * @param mask The interrupts to enable. + */ +static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask) +{ + base->ILE |= ((uint32_t)1U << line); + if (0U == line) + { + base->ILS &= ~mask; + } + else + { + base->ILS |= mask; + } + base->IE |= mask; +} + +/*! + * @brief Enables MCAN Tx Buffer interrupts according to the provided index. + * + * This function enables the MCAN Tx Buffer interrupts. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) +{ + base->TXBTIE |= ((uint32_t)1U << idx); +} + +/*! + * @brief Disables MCAN Tx Buffer interrupts according to the provided index. + * + * This function disables the MCAN Tx Buffer interrupts. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) +{ + base->TXBTIE &= (~((uint32_t)1U << idx)); +} + +/*! + * @brief Disables MCAN interrupts according to the provided mask. + * + * This function disables the MCAN interrupts according to the provided mask. + * The mask is a logical OR of enumeration members. + * + * @param base MCAN peripheral base address. + * @param mask The interrupts to disable. + */ +static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +{ + base->IE &= ~mask; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the Tx buffer request pending status. + * + * This function returns Tx Message Buffer transmission request pending status. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx); + +/*! + * @brief Gets the Tx buffer transmission occurred status. + * + * This function returns Tx Message Buffer transmission occurred status. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx); + +/*! + * @brief Writes an MCAN Message to the Transmit Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Tx Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + */ +status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame); + +/*! + * @brief Reads an MCAN Message from Rx Buffer. + * + * This function reads a CAN message from the Rx Buffer in the Message RAM. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Rx Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx Buffer successfully. + */ +status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); + +/*! + * @brief Reads an MCAN Message from Rx FIFO. + * + * This function reads a CAN message from the Rx FIFO in the Message RAM. + * + * @param base MCAN peripheral base address. + * @param fifoBlock Rx FIFO block 0 or 1. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + */ +status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Tx Buffer add request to send message out. + * + * This function add sending request to corresponding Tx Buffer. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx) +{ + base->TXBAR |= ((uint32_t)1U << idx); +} + +/*! + * @brief Tx Buffer cancel sending request. + * + * This function clears Tx buffer request pending bit. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx) +{ + base->TXBCR |= ((uint32_t)1U << idx); +} + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base MCAN peripheral base pointer. + * @param idx The MCAN buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base MCAN peripheral base pointer. + * @param idx The MCAN buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Rx Message Buffer Successfully. + * @retval kStatus_Fail - No new message. + */ +status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); + +/*! + * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base MCAN peripheral base pointer. + * @param fifoBlock Rx FIFO block, 0 or 1. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - No new message in Rx FIFO. + */ +status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); + +/*! + * @brief Initializes the MCAN handle. + * + * This function initializes the MCAN handle, which can be used for other MCAN + * transactional APIs. Usually, for a specified MCAN instance, + * call this API once to get the initialized handle. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void MCAN_TransferCreateHandle(CAN_Type *base, + mcan_handle_t *handle, + mcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. + * @retval kStatus_Success Start Tx Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Buffer failed. + * @retval kStatus_MCAN_TxBusy Tx Buffer is in use. + */ +status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param fifoBlock Rx FIFO block, 0 or 1. + * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. + * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. + */ +status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + uint8_t fifoBlock, + mcan_handle_t *handle, + mcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param bufferIdx The MCAN Buffer index. + */ +void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base MCAN peripheral base address. + * @param fifoBlock MCAN Fifo block, 0 or 1. + * @param handle MCAN handle pointer. + */ +void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle); + +/*! + * @brief MCAN IRQ handle function. + * + * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + */ +void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MCAN_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.c new file mode 100644 index 0000000000000000000000000000000000000000..d80e16de4165a7a68bc68257d71194d52e0700fd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mrt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mrt" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Multi-Rate timer peripheral base address + * + * @return The MRT instance + */ +static uint32_t MRT_GetInstance(MRT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to MRT bases for each instance. */ +static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to MRT clocks for each instance. */ +static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; +#else +/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t MRT_GetInstance(MRT_Type *base) +{ + uint32_t instance; + uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < mrtArrayCount; instance++) + { + if (s_mrtBases[instance] == base) + { + break; + } + } + + assert(instance < mrtArrayCount); + + return instance; +} + +/*! + * brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the MRT driver. + * + * param base Multi-Rate timer peripheral base address + * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the MRT clock */ + CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Set timer operating mode */ + base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); +#endif +} + +/*! + * brief Gate the MRT clock + * + * param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base) +{ + /* Stop all the timers */ + MRT_StopTimer(base, kMRT_Channel_0); + MRT_StopTimer(base, kMRT_Channel_1); +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) + MRT_StopTimer(base, kMRT_Channel_2); +#endif +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) + MRT_StopTimer(base, kMRT_Channel_3); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the MRT clock*/ + CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * param base Multi-Rate timer peripheral base address + * param channel Timer channel number + * param count Timer period in units of ticks + * param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t newValue = count; + if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) + { + /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ + newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; + } + + /* Update the timer interval value */ + base->CHANNEL[channel].INTVAL = newValue; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.h new file mode 100644 index 0000000000000000000000000000000000000000..7829d984e206922b7ec0d89083fc582b16f7e862 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_mrt.h @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MRT_H_ +#define _FSL_MRT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mrt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ +/*@}*/ + +/*! @brief List of MRT channels */ +typedef enum _mrt_chnl +{ + kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ + kMRT_Channel_1, /*!< MRT channel number 1 */ + kMRT_Channel_2, /*!< MRT channel number 2 */ + kMRT_Channel_3 /*!< MRT channel number 3 */ +} mrt_chnl_t; + +/*! @brief List of MRT timer modes */ +typedef enum _mrt_timer_mode +{ + kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ + kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ + kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ +} mrt_timer_mode_t; + +/*! @brief List of MRT interrupts */ +typedef enum _mrt_interrupt_enable +{ + kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ +} mrt_interrupt_enable_t; + +/*! @brief List of MRT status flags */ +typedef enum _mrt_status_flags +{ + kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ + kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ +} mrt_status_flags_t; + +/*! + * @brief MRT configuration structure + * + * This structure holds the configuration settings for the MRT peripheral. To initialize this + * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _mrt_config +{ + bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ +} mrt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the MRT driver. + * + * @param base Multi-Rate timer peripheral base address + * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config); + +/*! + * @brief Gate the MRT clock + * + * @param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base); + +/*! + * @brief Fill in the MRT config struct with the default settings + * + * The default values are: + * @code + * config->enableMultiTask = false; + * @endcode + * @param config Pointer to user's MRT config structure. + */ +static inline void MRT_GetDefaultConfig(mrt_config_t *config) +{ + assert(config != NULL); +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Use hardware status operating mode */ + config->enableMultiTask = false; +#endif +} + +/*! + * @brief Sets up an MRT channel mode. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Channel that is being configured. + * @param mode Timer mode to use for the channel. + */ +static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].CTRL; + + /* Clear old value */ + reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; + /* Add the new mode */ + reg |= (uint32_t)mode; + + base->CHANNEL[channel].CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL |= mask; +} + +/*! + * @brief Disables the selected MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL &= ~mask; +} + +/*! + * @brief Gets the enabled MRT interrupts. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the MRT status flags + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); +} + +/*! + * @brief Clears the MRT status flags. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + * @param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return base->CHANNEL[channel].TIMER; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, counts down to 0 and + * depending on the timer mode it will either load the respective start value again or stop. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. + */ +static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); + /* Write the timer interval value */ + base->CHANNEL[channel].INTVAL = count; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer from counting. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + /* Stop the timer immediately */ + base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; +} + +/*! @}*/ + +/*! + * @name Get & release channel + * @{ + */ + +/*! + * @brief Find the available channel. + * + * This function returns the lowest available channel number. + * + * @param base Multi-Rate timer peripheral base address + */ +static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) +{ + return base->IDLE_CH; +} + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) +/*! + * @brief Release the channel when the timer is using the multi-task mode. + * + * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for + * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as + * long as it is needed and release it by calling this function. This removes the need to ask for + * an available channel for every use. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].STAT; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; + reg |= MRT_CHANNEL_STAT_INUSE_MASK; + + base->CHANNEL[channel].STAT = reg; +} +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MRT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.c new file mode 100644 index 0000000000000000000000000000000000000000..fc1f96e41672b6027e21dbe749f4fa05ed02521c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.c @@ -0,0 +1,130 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_opamp.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.opamp" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t OPAMP_GetInstance(OPAMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static OPAMP_Type *const s_opampBases[] = OPAMP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to OPAMP clocks for each instance. */ +static const clock_ip_name_t s_opampClocks[] = OPAMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t OPAMP_GetInstance(OPAMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0UL; instance < ARRAY_SIZE(s_opampBases); instance++) + { + if (s_opampBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_opampBases)); + + return instance; +} + +/*! + * brief Initialize OPAMP instance. + * + * param base OPAMP peripheral base address. + * param config The pointer to opamp_config_t. + */ +void OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_opampClocks[OPAMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + tmp32 = base->OPAMP_CTR; + tmp32 &= ~(OPAMP_OPAMP_CTR_EN_MASK | OPAMP_OPAMP_CTR_MODE_MASK | OPAMP_OPAMP_CTR_BIASC_MASK | + OPAMP_OPAMP_CTR_INTREF_MASK | OPAMP_OPAMP_CTR_ADCSW_MASK | OPAMP_OPAMP_CTR_PREF_MASK | + OPAMP_OPAMP_CTR_PGAIN_MASK | OPAMP_OPAMP_CTR_NGAIN_MASK); + tmp32 |= OPAMP_OPAMP_CTR_EN(config->enable) | OPAMP_OPAMP_CTR_MODE(config->mode) | + OPAMP_OPAMP_CTR_BIASC(config->trimOption) | OPAMP_OPAMP_CTR_INTREF(config->intRefVoltage) | + OPAMP_OPAMP_CTR_ADCSW(config->enablePosADCSw) | OPAMP_OPAMP_CTR_PREF(config->posRefVoltage) | + OPAMP_OPAMP_CTR_PGAIN(config->posGain) | OPAMP_OPAMP_CTR_NGAIN(config->negGain); + base->OPAMP_CTR = tmp32; +} + +/*! + * brief De-initialize OPAMP instance. + * + * param base OPAMP peripheral base address. + */ +void OPAMP_Deinit(OPAMP_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_opampClocks[OPAMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable OPAMP instance. */ + base->OPAMP_CTR &= ~OPAMP_OPAMP_CTR_EN_MASK; +} + +/*! + * brief Get default configuration of OPAMP. + * + * code + * config->enable = false; + * config->mode = kOPAMP_LowNoiseMode; + * config->trimOption = kOPAMP_TrimOptionDefault; + * config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; + * config->enablePosADCSw = false; + * config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; + * config->posGain = kOPAMP_PosGainReserved; + * config->negGain = kOPAMP_NegGainBufferMode; + * endcode + * + * param config The pointer to opamp_config_t. + */ +void OPAMP_GetDefaultConfig(opamp_config_t *config) +{ + assert(config != NULL); + + config->enable = false; + config->mode = kOPAMP_LowNoiseMode; + config->trimOption = kOPAMP_TrimOptionDefault; + config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; + + config->enablePosADCSw = false; + config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; + config->posGain = kOPAMP_PosGainReserved; + + config->negGain = kOPAMP_NegGainBufferMode; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.h new file mode 100644 index 0000000000000000000000000000000000000000..3a3ceaa731e52da198130a342d927ce918fe89cb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_opamp.h @@ -0,0 +1,181 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_OPAMP_H_ +#define _FSL_OPAMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup opamp + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief OPAMP driver version. */ +#define FSL_OPAMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief The enumeration of OPAMP mode, including low noise mode and high speed mode. + */ +typedef enum _opamp_mode +{ + kOPAMP_LowNoiseMode = 0U, /*!< Set opamp mode as low noise mode. */ + kOPAMP_HighSpeedMode, /*!< Set opamp mode as high speed mode. */ +} opamp_mode_t; + +/*! + * @brief The enumeration of bias current trim option. + */ +typedef enum _opamp_bias_current_trim_option +{ + kOPAMP_TrimOptionDefault = 0U, /*!< Default Bias current trim option. */ + kOPAMP_TrimOptionIncreaseCurrent, /*!< Trim option selected as increase current. */ + kOPAMP_TrimOptionDecreaseCurrent, /*!< Trim option selected as decrease current. */ + kOPAMP_TrimOptionFurtherDecreaseCurrent, /*!< Trim option selected as further decrease current. */ +} opamp_bias_current_trim_option_t; + +/*! + * @brief The enumeration of internal reference voltage. + */ +typedef enum _opamp_internal_ref_voltage +{ + kOPAMP_IntRefVoltVddaDiv2 = 0U, /*!< Internal reference voltage selected as Vdda/2. */ + kOPAMP_IntRefVoltVdda3V, /*!< Internal reference voltage selected as Vdda_3V. */ + kOPAMP_IntRefVoltVssa3V, /*!< Internal reference voltage selected as Vssa_3V. */ + kOPAMP_IntRefVoltNotAllowed, /*!< Internal reference voltage not allowed. */ +} opamp_internal_ref_voltage_t; + +/*! + * @brief The enumeration of positive reference voltage. + */ +typedef enum _opamp_positive_ref_voltage +{ + kOPAMP_PosRefVoltVrefh3 = 0U, /*!< Positive part reference voltage select Vrefh3, connected from DAC output. */ + kOPAMP_PosRefVoltVrefh0 = 1U, /*!< Positive part reference voltage select Vrefh0, connected from VDDA supply. */ + kOPAMP_PosRefVoltVrefh1 = 2U, /*!< Positive part reference voltage select Vrefh1, + connected from Voltage reference output. */ + kOPAMP_PosRefVoltReserved = 3U, /*!< Positive part reference voltage reserved. */ +} opamp_positive_ref_voltage_t; + +/*! + * @brief The enumeration of positive programmable gain. + */ +typedef enum _opamp_positive_gain +{ + kOPAMP_PosGainReserved = 0U, /*!< Positive Gain reserved. */ + kOPAMP_PosGainNonInvert1X, /*!< Positive non-inverting gain application 1X. */ + kOPAMP_PosGainNonInvert2X, /*!< Positive non-inverting gain application 2X. */ + kOPAMP_PosGainNonInvert4X, /*!< Positive non-inverting gain application 4X. */ + kOPAMP_PosGainNonInvert8X, /*!< Positive non-inverting gain application 8X. */ + kOPAMP_PosGainNonInvert16X, /*!< Positive non-inverting gain application 16X. */ + kOPAMP_PosGainNonInvert33X, /*!< Positive non-inverting gain application 33X. */ + kOPAMP_PosGainNonInvert64X, /*!< Positive non-inverting gain application 64X. */ +} opamp_positive_gain_t; + +/*! + * @brief The enumeration of negative programmable gain. + */ +typedef enum _opamp_negative_gain +{ + kOPAMP_NegGainBufferMode = 0U, /*!< Negative Buffer Mode. */ + kOPAMP_NegGainInvert1X, /*!< Negative inverting gain application -1X. */ + kOPAMP_NegGainInvert2X, /*!< Negative inverting gain application -2X. */ + kOPAMP_NegGainInvert4X, /*!< Negative inverting gain application -4X. */ + kOPAMP_NegGainInvert8X, /*!< Negative inverting gain application -8X. */ + kOPAMP_NegGainInvert16X, /*!< Negative inverting gain application -16X. */ + kOPAMP_NegGainInvert33X, /*!< Negative inverting gain application -33X. */ + kOPAMP_NegGainInvert64X, /*!< Negative inverting gain application -64X. */ +} opamp_negative_gain_t; + +/*! + * @brief OPAMP configuraion, including mode, internal reference voltage, positive gain, negative gain and so on. + */ +typedef struct _opamp_config +{ + bool enable; /*!< Enable/disable OPAMP. */ + opamp_mode_t mode; /*!< Opamp mode, available values are @ref kOPAMP_LowNoiseMode and @ref kOPAMP_HighSpeedMode. */ + opamp_bias_current_trim_option_t trimOption; /*!< Bias current trim option, please refer to + @ref opamp_bias_current_trim_option_t. */ + opamp_internal_ref_voltage_t intRefVoltage; /*!< Internal reference voltage, please refer to + @ref opamp_internal_ref_voltage_t. */ + + /* Positive part configuration. */ + bool enablePosADCSw; /*!< Positive part reference voltage switch to ADC channel or not. + - \b true Positive part reference voltage switch to ADC channel. + - \b false Positive part reference voltage do not switch to ADC channel. */ + opamp_positive_ref_voltage_t posRefVoltage; /*!< Positive part reference voltage, please refer + to @ref opamp_positive_ref_voltage_t. */ + opamp_positive_gain_t posGain; /*!< Positive part programmable gain, please refer + to @ref opamp_positive_gain_t. */ + + /* Negative part configuration. */ + opamp_negative_gain_t negGain; /*!< Negative part programmable gain, please refer + to @ref opamp_negative_gain_t. */ + +} opamp_config_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize OPAMP instance. + * + * @param base OPAMP peripheral base address. + * @param config The pointer to @ref opamp_config_t. + */ +void OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config); + +/*! + * @brief De-initialize OPAMP instance. + * + * @param base OPAMP peripheral base address. + */ +void OPAMP_Deinit(OPAMP_Type *base); + +/*! + * @brief Get default configuration of OPAMP. + * + * @code + * config->enable = false; + * config->mode = kOPAMP_LowNoiseMode; + * config->trimOption = kOPAMP_TrimOptionDefault; + * config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; + * config->enablePosADCSw = false; + * config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; + * config->posGain = kOPAMP_PosGainReserved; + * config->negGain = kOPAMP_NegGainBufferMode; + * @endcode + * + * @param config The pointer to @ref opamp_config_t. + */ +void OPAMP_GetDefaultConfig(opamp_config_t *config); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_OPAMP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.c new file mode 100644 index 0000000000000000000000000000000000000000..cfa28bafa23667234a02f218454be060aa4aac1c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.c @@ -0,0 +1,395 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ostimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ostimer" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base OSTIMER peripheral base address + * + * @return The OSTIMER instance + */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/* @brief Translate the value from gray-code to decimal. */ +/* + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimal(uint64_t gray); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of OSTIMER handle. */ +static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; +/* Array of OSTIMER peripheral base address. */ +static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; +/* Array of OSTIMER IRQ number. */ +static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of OSTIMER clock name. */ +static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* OSTIMER ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; +#else +static ostimer_isr_t s_ostimerIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* @brief Function for getting the instance number of OS timer. */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) + { + if (s_ostimerBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ostimerBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) +{ + uint64_t decOut; + + SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); + SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer + __NOP(); + decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; + decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); + + return decOut; +} +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/* @brief Translate the value from gray-code to decimal. */ +/* + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +{ +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + return OSTIMER_GrayToDecimalbyCodeGray(gray); +#else + uint64_t temp = gray; + while (temp != 0U) + { + temp >>= 1U; + gray ^= temp; + } + + return gray; +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +} + +/* @brief Translate the value from decimal to gray-code. */ +static uint64_t OSTIMER_DecimalToGray(uint64_t dec) +{ + return (dec ^ (dec >> 1U)); +} + +/* @brief Enable the OSTIMER interrupt. + * + * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. + * + * @param base OSTIMER peripheral base address. + * @param enable enable/disable the IRQ and module interrupt enablement. + * - true: Disable the IRQ and module interrupt enablement. + * - false: Disable the IRQ and module interrupt enablement. + * @return none + */ +static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) +{ + assert(NULL != base); + + if (enable) + { + /* Enable the IRQ and module interrupt enablement. */ + (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; + } + else + { + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ + } +} + +/*! + * @brief Initializes an OSTIMER by turning it's clock on. + * + */ +void OSTIMER_Init(OSTIMER_Type *base) +{ + assert(NULL != base); + + uint32_t instance = OSTIMER_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + /* Enable the OSTIMER 32k clock in PMC module. */ + CLOCK_EnableOstimer32kClock(); +#endif + /* Enable clock for OSTIMER. */ + CLOCK_EnableClock(s_ostimerClock[instance]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_EnableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable clock for OSTIMER. */ + CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_DisableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) +{ + return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; +} + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) +{ + base->OSEVENT_CTRL |= mask; +} + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + uint64_t decValueTimer; +#endif + status_t status; + uint64_t tmp = count; + uint32_t instance = OSTIMER_GetInstance(base); + + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + s_ostimerIsr = OSTIMER_HandleIRQ; + s_ostimerHandle[instance] = cb; + + /* Set the match value. */ + base->MATCH_L = (uint32_t)tmp; + base->MATCH_H = (uint32_t)(tmp >> 32U); + +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Workaround-2019-12-30: + * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match + * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is + * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it + * should not be necessary to test this bit", but we found the interruption would not be reported when the delta + * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such + * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. + */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } + + /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. + * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit + * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable + * interrupt and return success; if not, we will return fail directly. + * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. + */ + decValueTimer = OSTIMER_GetCurrentTimerValue(base); + if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && + (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) + { + status = kStatus_Fail; + } + else +#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ + { + /* Enable the module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, true); + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in + * API. ) + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ + uint64_t tmp = OSTIMER_DecimalToGray(count); + + return OSTIMER_SetMatchRawValue(base, tmp, cb); +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCurrentTimerRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCaptureRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) +{ + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + if (cb != NULL) + { + cb(); + } +} + +#if defined(OSTIMER0) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(OSTIMER) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.h new file mode 100644 index 0000000000000000000000000000000000000000..c805ce3160976c5e84d51bb0188b64d5d776399d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_ostimer.h @@ -0,0 +1,204 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_OSTIMER_H_ +#define _FSL_OSTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ostimer + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief OSTIMER driver version. */ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! + * @brief OSTIMER status flags. + */ +enum _ostimer_flags +{ + kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if + the match value was reached. */ +}; + +/*! @brief ostimer callback function. */ +typedef void (*ostimer_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an OSTIMER by turning its bus clock on + * + */ +void OSTIMER_Init(OSTIMER_Type *base); + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER bus clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base); + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code + * internally.) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Get current timer raw count value from OSTIMER. + * + * This function will get a gray code type timer count value from OS timer register. + * The raw value of timer count is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of OSTIMER, gray code format. + */ +static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->EVTIMERL; + tmp |= (uint64_t)(base->EVTIMERH) << 32U; + + return tmp; +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will be formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a captured gray-code value from OSTIMER. + * The Raw value of timer capture is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of capture register, data format is gray code. + */ +static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->CAPTURE_L; + tmp |= (uint64_t)(base->CAPTURE_H) << 32U; + + return tmp; +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); + +/*! + * @brief OS timer interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in OSTIMER_SetMatchValue()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base OS timer peripheral base address. + * @param cb callback scheduled for this instance of OS timer + * @return none + */ +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.c new file mode 100644 index 0000000000000000000000000000000000000000..f658b7990df800503d89f3de76f7ac6be6135c52 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.c @@ -0,0 +1,968 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for SECPINT(s). */ +static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#else +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg = 0; + uint8_t pintcount = 0; + assert(base != NULL); + + if (base == PINT) + { + pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear SECPINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + /* Disable all bit slices for pint*/ + for (i = 0; i < pintcount; i++) + { + pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +/*! + * brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param intr Pin interrupt. + * param enable Selects detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base != NULL); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* Security PINT uses additional callback array */ + if (base == PINT) + { + s_pintCallback[intr] = callback; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + s_secpintCallback[intr] = callback; +#endif + } + + /* select level or edge sensitive */ + base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | + ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); + + /* enable rising or level interrupt */ + if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) + { + base->SIENR = 1UL << (uint32_t)intr; + } + else + { + base->CIENR = 1UL << (uint32_t)intr; + } + + /* Enable falling or select high level */ + if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) + { + base->SIENF = 1UL << (uint32_t)intr; + } + else + { + base->CIENF = 1UL << (uint32_t)intr; + } +} + +/*! + * brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param pintr Pin interrupt. + * param enable Pointer to store the detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base != NULL); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1UL << (uint32_t)pintr; + if ((base->ISEL & mask) != 0U) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if ((base->IENR & mask) != 0U) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if ((base->IENF & mask) != 0U) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + /* Security PINT uses additional callback array */ + if (base == PINT) + { + *callback = s_pintCallback[pintr]; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + *callback = s_secpintCallback[pintr]; +#endif + } +} + +/*! + * brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base != NULL); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); + + /* If end point is true, enable the bits */ + if ((uint32_t)bslice != 7UL) + { + if (cfg->end_point) + { + pmcfg |= (1UL << (uint32_t)bslice); + } + else + { + pmcfg &= ~(1UL << (uint32_t)bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_pintCallback[bslice] = cfg->callback; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_secpintCallback[bslice] = cfg->callback; + } +#endif + } +} + +/*! + * brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base != NULL); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); + + if ((uint32_t)bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; + } + + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_pintCallback[bslice]; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_secpintCallback[bslice]; + } +#endif + } +} + +/*! + * brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * param base Base address of the PINT peripheral. + * + * retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = base->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus != 0UL) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); + uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + base->IST = (1UL << (uint32_t)pintr); + } +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + uint32_t pinIntMode = 0; + uint32_t pinIntStatus = 0; + uint32_t pinIntCount = 0; + uint32_t mask = 0; + uint32_t i; + + if (base == PINT) + { + pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + for (i = 0; i < pinIntCount; i++) + { + pinIntMode = base->ISEL & (1UL << i); + pinIntStatus = base->IST & (1UL << i); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + mask |= 1UL << i; + } + } + + base->IST = mask; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + if (base == PINT) + { + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + (void)EnableIRQ(s_pintIRQ[i]); + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +} + +/*! + * brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base != NULL); + + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* Get the right security pint irq index in array */ + if (base == SECPINT) + { + pintIdx = + (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + (void)EnableIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + if (base == PINT) + { + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +} + +/*! + * brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base != NULL); + + if (base == PINT) + { + (void)DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); +#endif + } +} + +/*! + * brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + /* Cleanup */ + PINT_DisableCallback(base); + if (base == PINT) + { + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* clear SECPINT callback array */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ +} +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) +{ + uint32_t pmstatus = 0; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_secpintCallback[kPINT_SecPinInt0] != NULL) + { + s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); + } + SDK_ISR_EXIT_BARRIER; +} + +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_secpintCallback[kPINT_SecPinInt1] != NULL) + { + s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void); +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } + SDK_ISR_EXIT_BARRIER; +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void); +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + if ((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void); +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + if ((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void); +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + if ((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void); +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + if ((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void) +#else +void PIN_INT5_DriverIRQHandler(void); +void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + if ((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void) +#else +void PIN_INT6_DriverIRQHandler(void); +void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + if ((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void) +#else +void PIN_INT7_DriverIRQHandler(void); +void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + if ((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.h new file mode 100644 index 0000000000000000000000000000000000000000..d56458f3b1543a29e71bc66312439e21787e6b7f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pint.h @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PINT_H_ +#define _FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 8)) /*!< Version 2.1.8 */ +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of interrupt line supported by SECURE PINT */ +#define SEC_PINT_PIN_INT_COUNT 2U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ + kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base); + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +/*! + * @brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * @param base Base address of the peripheral. + * @param pintIdx pin index. + * + * @retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +/*! + * @brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * @param base Base address of the peripheral. + * @param pintIdx pin index. + * + * @retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_PINT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.c new file mode 100644 index 0000000000000000000000000000000000000000..4ae4f9b6874e4d25d1af589bae95a205bca7e101 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.c @@ -0,0 +1,3107 @@ +/* + * Copyright 2020, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include "fsl_common.h" +#include "fsl_power.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif + +/* NOTE: These registers are handled by the SDK. The user should not modify the source code. Changes to the source code + * can cause application failure. NXP is not responsible for any change to the code and is not obligated to provide + * support. */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/** + * @brief LDO_FLASH_NV & LDO_EFUSE_PROG voltage settings + */ +typedef enum _v_ldo_flashnv_ldo_efuse +{ + V_LDO_1P650 = 0, /*!< 1.65 V */ + V_LDO_1P700 = 1, /*!< 1.7 V */ + V_LDO_1P750 = 2, /*!< 1.75 V */ + V_LDO_1P800 = 3, /*!< 1.8 V */ + V_LDO_1P850 = 4, /*!< 1.85 V */ + V_LDO_1P900 = 5, /*!< 1.9 V */ + V_LDO_1P950 = 6, /*!< 1.95 V */ + V_LDO_2P000 = 7 /*!< 2.0 V */ +} v_ldo_flashnv_ldo_efuse_t; + +/** + * @brief Always On and Memories LDO voltage settings + */ +typedef enum _v_ao +{ + // V_AO_1P220 1.22 = 0, /*!< 1.22 V */ + V_AO_0P700 = 1, /*!< 0.7 V */ + V_AO_0P725 = 2, /*!< 0.725 V */ + V_AO_0P750 = 3, /*!< 0.75 V */ + V_AO_0P775 = 4, /*!< 0.775 V */ + V_AO_0P800 = 5, /*!< 0.8 V */ + V_AO_0P825 = 6, /*!< 0.825 V */ + V_AO_0P850 = 7, /*!< 0.85 V */ + V_AO_0P875 = 8, /*!< 0.875 V */ + V_AO_0P900 = 9, /*!< 0.9 V */ + V_AO_0P960 = 10, /*!< 0.96 V */ + V_AO_0P970 = 11, /*!< 0.97 V */ + V_AO_0P980 = 12, /*!< 0.98 V */ + V_AO_0P990 = 13, /*!< 0.99 V */ + V_AO_1P000 = 14, /*!< 1 V */ + V_AO_1P010 = 15, /*!< 1.01 V */ + V_AO_1P020 = 16, /*!< 1.02 V */ + V_AO_1P030 = 17, /*!< 1.03 V */ + V_AO_1P040 = 18, /*!< 1.04 V */ + V_AO_1P050 = 19, /*!< 1.05 V */ + V_AO_1P060 = 20, /*!< 1.06 V */ + V_AO_1P070 = 21, /*!< 1.07 V */ + V_AO_1P080 = 22, /*!< 1.08 V */ + V_AO_1P090 = 23, /*!< 1.09 V */ + V_AO_1P100 = 24, /*!< 1.1 V */ + V_AO_1P110 = 25, /*!< 1.11 V */ + V_AO_1P120 = 26, /*!< 1.12 V */ + V_AO_1P130 = 27, /*!< 1.13 V */ + V_AO_1P140 = 28, /*!< 1.14 V */ + V_AO_1P150 = 29, /*!< 1.15 V */ + V_AO_1P160 = 30, /*!< 1.16 V */ + V_AO_1P220 = 31 /*!< 1.22 V */ +} v_ao_t; + +/** + * @brief DCDC voltage settings + */ +typedef enum _v_dcdc +{ + V_DCDC_0P950 = 0, /*!< 0.95 V */ + V_DCDC_0P975 = 1, /*!< 0.975 V */ + V_DCDC_1P000 = 2, /*!< 1 V */ + V_DCDC_1P025 = 3, /*!< 1.025 V */ + V_DCDC_1P050 = 4, /*!< 1.050 V */ + V_DCDC_1P075 = 5, /*!< 1.075 V */ + V_DCDC_1P100 = 6, /*!< 1.1 V */ + V_DCDC_1P125 = 7, /*!< 1.125 V */ + V_DCDC_1P150 = 8, /*!< 1.150 V */ + V_DCDC_1P175 = 9, /*!< 1.175 V */ + V_DCDC_1P200 = 10 /*!< 1.2 V */ +} v_dcdc_t; + +/** + * @brief LDO_CORE High Power Mode voltage settings + */ +typedef enum _v_ldocore_hp +{ + V_LDOCORE_HP_1P373 = 0, /*!< 1.373 V */ + V_LDOCORE_HP_1P365 = 1, /*!< 1.365 V */ + V_LDOCORE_HP_1P359 = 2, /*!< 1.359 V */ + V_LDOCORE_HP_1P352 = 3, /*!< 1.352 V */ + V_LDOCORE_HP_1P345 = 4, /*!< 1.345 V */ + V_LDOCORE_HP_1P339 = 5, /*!< 1.339 V */ + V_LDOCORE_HP_1P332 = 6, /*!< 1.332 V */ + V_LDOCORE_HP_1P325 = 7, /*!< 1.325 V */ + V_LDOCORE_HP_1P318 = 8, /*!< 1.318 V */ + V_LDOCORE_HP_1P311 = 9, /*!< 1.311 V */ + V_LDOCORE_HP_1P305 = 10, /*!< 1.305 V */ + V_LDOCORE_HP_1P298 = 11, /*!< 1.298 V */ + V_LDOCORE_HP_1P291 = 12, /*!< 1.291 V */ + V_LDOCORE_HP_1P285 = 13, /*!< 1.285 V */ + V_LDOCORE_HP_1P278 = 14, /*!< 1.278 V */ + V_LDOCORE_HP_1P271 = 15, /*!< 1.271 V */ + V_LDOCORE_HP_1P264 = 16, /*!< 1.264 V */ + V_LDOCORE_HP_1P258 = 17, /*!< 1.258 V */ + V_LDOCORE_HP_1P251 = 18, /*!< 1.251 V */ + V_LDOCORE_HP_1P244 = 19, /*!< 1.244 V */ + V_LDOCORE_HP_1P237 = 20, /*!< 1.237 V */ + V_LDOCORE_HP_1P231 = 21, /*!< 1.231 V */ + V_LDOCORE_HP_1P224 = 22, /*!< 1.224 V */ + V_LDOCORE_HP_1P217 = 23, /*!< 1.217 V */ + V_LDOCORE_HP_1P210 = 24, /*!< 1.21 V */ + V_LDOCORE_HP_1P204 = 25, /*!< 1.204 V */ + V_LDOCORE_HP_1P197 = 26, /*!< 1.197 V */ + V_LDOCORE_HP_1P190 = 27, /*!< 1.19 V */ + V_LDOCORE_HP_1P183 = 28, /*!< 1.183 V */ + V_LDOCORE_HP_1P177 = 29, /*!< 1.177 V */ + V_LDOCORE_HP_1P169 = 30, /*!< 1.169 V */ + V_LDOCORE_HP_1P163 = 31, /*!< 1.163 V */ + V_LDOCORE_HP_1P156 = 32, /*!< 1.156 V */ + V_LDOCORE_HP_1P149 = 33, /*!< 1.149 V */ + V_LDOCORE_HP_1P143 = 34, /*!< 1.143 V */ + V_LDOCORE_HP_1P136 = 35, /*!< 1.136 V */ + V_LDOCORE_HP_1P129 = 36, /*!< 1.129 V */ + V_LDOCORE_HP_1P122 = 37, /*!< 1.122 V */ + V_LDOCORE_HP_1P116 = 38, /*!< 1.116 V */ + V_LDOCORE_HP_1P109 = 39, /*!< 1.109 V */ + V_LDOCORE_HP_1P102 = 40, /*!< 1.102 V */ + V_LDOCORE_HP_1P095 = 41, /*!< 1.095 V */ + V_LDOCORE_HP_1P088 = 42, /*!< 1.088 V */ + V_LDOCORE_HP_1P082 = 43, /*!< 1.082 V */ + V_LDOCORE_HP_1P075 = 44, /*!< 1.075 V */ + V_LDOCORE_HP_1P068 = 45, /*!< 1.068 V */ + V_LDOCORE_HP_1P062 = 46, /*!< 1.062 V */ + V_LDOCORE_HP_1P055 = 47, /*!< 1.055 V */ + V_LDOCORE_HP_1P048 = 48, /*!< 1.048 V */ + V_LDOCORE_HP_1P041 = 49, /*!< 1.041 V */ + V_LDOCORE_HP_1P034 = 50, /*!< 1.034 V */ + V_LDOCORE_HP_1P027 = 51, /*!< 1.027 V */ + V_LDOCORE_HP_1P021 = 52, /*!< 1.021 V */ + V_LDOCORE_HP_1P014 = 53, /*!< 1.014 V */ + V_LDOCORE_HP_1P007 = 54, /*!< 1.007 V */ + V_LDOCORE_HP_1P001 = 55, /*!< 1.001 V */ + V_LDOCORE_HP_0P993 = 56, /*!< 0.9937 V */ + V_LDOCORE_HP_0P987 = 57, /*!< 0.987 V */ + V_LDOCORE_HP_0P980 = 58, /*!< 0.9802 V */ + V_LDOCORE_HP_0P973 = 59, /*!< 0.9731 V */ + V_LDOCORE_HP_0P966 = 60, /*!< 0.9666 V */ + V_LDOCORE_HP_0P959 = 61, /*!< 0.9598 V */ + V_LDOCORE_HP_0P953 = 62, /*!< 0.9532 V */ + V_LDOCORE_HP_0P946 = 63, /*!< 0.946 V */ + V_LDOCORE_HP_0P939 = 64, /*!< 0.9398 V */ + V_LDOCORE_HP_0P932 = 65, /*!< 0.9327 V */ + V_LDOCORE_HP_0P926 = 66, /*!< 0.9262 V */ + V_LDOCORE_HP_0P919 = 67, /*!< 0.9199 V */ + V_LDOCORE_HP_0P913 = 68, /*!< 0.9135 V */ + V_LDOCORE_HP_0P907 = 69, /*!< 0.9071 V */ + V_LDOCORE_HP_0P901 = 70, /*!< 0.9012 V */ + V_LDOCORE_HP_0P895 = 71, /*!< 0.8953 V */ + V_LDOCORE_HP_0P889 = 72, /*!< 0.8895 V */ + V_LDOCORE_HP_0P883 = 73, /*!< 0.8837 V */ + V_LDOCORE_HP_0P877 = 74, /*!< 0.8779 V */ + V_LDOCORE_HP_0P871 = 75, /*!< 0.8719 V */ + V_LDOCORE_HP_0P865 = 76, /*!< 0.8658 V */ + V_LDOCORE_HP_0P859 = 77, /*!< 0.8596 V */ + V_LDOCORE_HP_0P853 = 78, /*!< 0.8537 V */ + V_LDOCORE_HP_0P847 = 79, /*!< 0.8474 V */ + V_LDOCORE_HP_0P841 = 80, /*!< 0.8413 V */ + V_LDOCORE_HP_0P835 = 81, /*!< 0.835 V */ + V_LDOCORE_HP_0P828 = 82, /*!< 0.8288 V */ + V_LDOCORE_HP_0P822 = 83, /*!< 0.8221 V */ + V_LDOCORE_HP_0P815 = 84, /*!< 0.8158 V */ + V_LDOCORE_HP_0P809 = 85, /*!< 0.8094 V */ + V_LDOCORE_HP_0P802 = 86, /*!< 0.8026 V */ + V_LDOCORE_HP_0P795 = 87, /*!< 0.7959 V */ + V_LDOCORE_HP_0P789 = 88, /*!< 0.7893 V */ + V_LDOCORE_HP_0P782 = 89, /*!< 0.7823 V */ + V_LDOCORE_HP_0P775 = 90, /*!< 0.7756 V */ + V_LDOCORE_HP_0P768 = 91, /*!< 0.7688 V */ + V_LDOCORE_HP_0P762 = 92, /*!< 0.7623 V */ + V_LDOCORE_HP_0P755 = 93, /*!< 0.7558 V */ + V_LDOCORE_HP_0P749 = 94, /*!< 0.749 V */ + V_LDOCORE_HP_0P742 = 95, /*!< 0.7421 V */ + V_LDOCORE_HP_0P735 = 96, /*!< 0.7354 V */ + V_LDOCORE_HP_0P728 = 97, /*!< 0.7284 V */ + V_LDOCORE_HP_0P722 = 98, /*!< 0.722 V */ + V_LDOCORE_HP_0P715 = 99 /*!< 0.715 V */ + // V_LDOCORE_HP_0P715 = 100, /*!< 0.7148 V */ + // V_LDOCORE_HP_0P715 = 101, /*!< 0.7148 V */ + // V_LDOCORE_HP_0P715 = 102, /*!< 0.7151 V */ + // V_LDOCORE_HP_0P715 = 103, /*!< 0.7147 V */ + // V_LDOCORE_HP_0P715 = 104, /*!< 0.7147 V */ + // V_LDOCORE_HP_0P715 = 105, /*!< 0.715 V */ + // V_LDOCORE_HP_0P715 = 106, /*!< 0.7147 V */ + // V_LDOCORE_HP_0P715 = 107, /*!< 0.715 V */ + // V_LDOCORE_HP_0P715 = 108, /*!< 0.7152 V */ + // V_LDOCORE_HP_0P715 = 109, /*!< 0.7148 V */ + // V_LDOCORE_HP_0P715 = 110, /*!< 0.715 V */ + // V_LDOCORE_HP_0P715 = 111, /*!< 0.7151 V */ + // V_LDOCORE_HP_0P715 = 112, /*!< 0.7153 V */ + // V_LDOCORE_HP_0P715 = 113, /*!< 0.7152 V */ + // V_LDOCORE_HP_0P715 = 114, /*!< 0.7149 V */ + // V_LDOCORE_HP_0P715 = 115, /*!< 0.7154 V */ + // V_LDOCORE_HP_0P715 = 116, /*!< 0.7152 V */ + // V_LDOCORE_HP_0P715 = 117, /*!< 0.7154 V */ + // V_LDOCORE_HP_0P715 = 118, /*!< 0.7147 V */ + // V_LDOCORE_HP_0P715 = 119, /*!< 0.7152 V */ + // V_LDOCORE_HP_0P715 = 120, /*!< 0.7149 V */ + // V_LDOCORE_HP_0P715 = 121, /*!< 0.7151 V */ + // V_LDOCORE_HP_0P715 = 122, /*!< 0.7152 V */ + // V_LDOCORE_HP_0P715 = 123, /*!< 0.7153 V */ + // V_LDOCORE_HP_0P715 = 124, /*!< 0.7149 V */ + // V_LDOCORE_HP_0P715 = 125, /*!< 0.7154 V */ + // V_LDOCORE_HP_0P715 = 126, /*!< 0.7153 V */ + // V_LDOCORE_HP_0P715 = 127, /*!< 0.7154 V */ +} v_ldocore_hp_t; + +/** + * @brief LDO_CORE Low Power Mode voltage settings + */ +typedef enum _v_ldocore_lp +{ + V_LDOCORE_LP_0P750 = 3, /*!< 0.75 V */ + V_LDOCORE_LP_0P800 = 2, /*!< 0.8 V */ + V_LDOCORE_LP_0P850 = 1, /*!< 0.85 V */ + V_LDOCORE_LP_0P900 = 0 /*!< 0.9 V */ +} v_ldocore_lp_t; + +/** + * @brief System Power Mode settings + */ +typedef enum _v_system_power_profile +{ + V_SYSTEM_POWER_PROFILE_LOW = 0UL, /*!< For system below or equal to 100 MHz */ + V_SYSTEM_POWER_PROFILE_MEDIUM = 1UL, /*!< For system frequencies in ]100 MHz - 150 MHz] */ + V_SYSTEM_POWER_PROFILE_HIGH = 2UL, /*!< For system above 150 MHz */ +} v_system_power_profile_t; + +/** + * @brief Manufacturing Process Corners + */ +typedef enum +{ + PROCESS_CORNER_SSS, /**< Slow Corner Process */ + PROCESS_CORNER_NNN, /**< Nominal Corner Process */ + PROCESS_CORNER_FFF, /**< Fast Corner Process */ + PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ +} lowpower_process_corner_enum; + +/** @brief Low Power main structure */ +typedef struct +{ + __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ + __IO uint32_t PDCTRL[2]; /*!< Power Down control : controls power of various modules + in the different Low power modes, including ROM */ + __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances + in the different Low power modes */ + __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ + __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ + __IO uint32_t WAKEUPSRC[4]; /*!< Wake up sources control for sleepcon */ + __IO uint32_t WAKEUPINT[4]; /*!< Wake up sources control for ARM */ + __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes + in case an interrupt is pending when the processor request deepsleep */ + __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER-DOWN mode */ +} LPC_LOWPOWER_T; + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) +/** + * @brief NMPA related Registers + */ +#define FLASH_NMPA_BOD_LDOCORE (*((volatile unsigned int *)(0x3FC08))) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY0 (*((volatile unsigned int *)(0x3FC18))) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY1 (*((volatile unsigned int *)(0x3FC1C))) +#define FLASH_NMPA_LDO_AO (*((volatile unsigned int *)(0x3FC24))) +#define FLASH_NMPA_LDO_MEM (*((volatile unsigned int *)(0x3FD60))) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY0 (*((volatile unsigned int *)(0x3FCB0))) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY1 (*((volatile unsigned int *)(0x3FCB4))) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY0 (*((volatile unsigned int *)(0x3FCB8))) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY1 (*((volatile unsigned int *)(0x3FCBC))) +#define FLASH_NMPA_PVT_MONITOR_0_RINGO (*((volatile unsigned int *)(0x3FCE0))) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO (*((volatile unsigned int *)(0x3FCF0))) + +/** + * @brief NMPA related masks + */ + +#define FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_SHIFT (24U) +#define FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_MASK (0xFF000000U) +#define FLASH_NMPA_LDO_AO_VADJ_ACTIVE_SHIFT (0U) +#define FLASH_NMPA_LDO_AO_VADJ_ACTIVE_MASK (0xFFU) +#endif + +/** + * @brief CSS related Registers + */ +#define CSSV2_STATUS_REG (*((volatile unsigned int *)(0x40030000))) +#define CSSV2_CTRL_REG (*((volatile unsigned int *)(0x40030004))) +#define SYSCON_CSS_CLK_CTRL_REG (*((volatile unsigned int *)(0x400009B0))) +#define SYSCON_CSS_CLK_CTRL_SET_REG (*((volatile unsigned int *)(0x400009B4))) +#define SYSCON_CSS_CLK_CTRL_CLR_REG (*((volatile unsigned int *)(0x400009B8))) + +/** + * @brief Wake-up I/O positions + */ +/*!< wake-up 0 */ +#define WAKEUPIO_0_PORT (1UL) +#define WAKEUPIO_0_PINS (1UL) +/*!< wake-up 1 */ +#define WAKEUPIO_1_PORT (0UL) +#define WAKEUPIO_1_PINS (28UL) +/*!< wake-up 2 */ +#define WAKEUPIO_2_PORT (1UL) +#define WAKEUPIO_2_PINS (18UL) +/*!< wake-up 3 */ +#define WAKEUPIO_3_PORT (1UL) +#define WAKEUPIO_3_PINS (30UL) +/*!< wake-up 4 */ +#define WAKEUPIO_4_PORT (0UL) +#define WAKEUPIO_4_PINS (26UL) + +/** + * @brief SRAM Low Power Modes + */ +#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) +#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ +#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ +#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ +#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ +#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ + +/** + * @brief SoC Low Power modes + */ +#define LOWPOWER_CFG_LPMODE_INDEX 0 +#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) +#define LOWPOWER_CFG_SELCLOCK_INDEX 2 +#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) +#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 +#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) +#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 +#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) +#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 +#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) + +#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ +#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP-SLEEP mode */ +#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER-DOWN mode */ +#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER-DOWN mode */ +#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ + +#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ +#define LOWPOWER_CFG_SELCLOCK_12MHZ \ + 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ + +#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ +#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ + 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ + +#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ + 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ + as possible -- 1.1V typical -- during low power mode) */ +#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ + 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ + as possible -- down to 0.7V -- during low power mode) */ + +/** + * @brief LDO Voltage control in Low Power Modes + */ +#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 +#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 +#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 10 +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 15 +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) + +/* CPU Retention Control*/ +#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 +#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) +#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 +#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) + +/** + * @brief SRAM Power Control Registers Code + */ +// LSDEL DSBDEL DSB LS +#define SRAM_PWR_MODE_ACT_CODE (0x6UL) // Active | 0 1 1 0 +#define SRAM_PWR_MODE_LS_CODE (0xFUL) // Light Sleep | 1 1 1 1 +#define SRAM_PWR_MODE_DS_CODE (0x8UL) // Deep Sleep | 1 0 0 0 +#define SRAM_PWR_MODE_SD_CODE (0x9UL) // Shut Down | 1 0 0 1 +#define SRAM_PWR_MODE_MPU_CODE (0xEUL) // Matrix Power Up | 1 1 1 0 +#define SRAM_PWR_MODE_FPU_CODE (0xAUL) // Full Power Up | 1 0 1 0 + +/** + * @brief System voltage setting + */ +// All 3 DCDC_POWER_PROFILE_* constants below have been updated after chip characterization on ATE +#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ + (100000000UL) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ +#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ + (135000000UL) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ +#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ + (150000000UL) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ + +/** + * @brief Manufacturing Process Parameters + */ +// All 3 PROCESS_* constants below have been updated after chip characterization on ATE +#define PROCESS_NNN_AVG_HZ (14900000UL) /* Average Ring Oscillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_STD_HZ \ + (515000UL) /* Standard Deviation Ring Oscillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_LIMITS \ + (2UL) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ + +#define PROCESS_NNN_MIN_HZ \ + (PROCESS_NNN_AVG_HZ - \ + (PROCESS_NNN_LIMITS * \ + PROCESS_NNN_STD_HZ)) /* Minimum Ring Oscillator value for Nominal (NNN) Manufacturing Process */ + +#define PROCESS_NNN_MAX_HZ \ + (PROCESS_NNN_AVG_HZ + \ + (PROCESS_NNN_LIMITS * \ + PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ + +// All 9 VOLTAGE_* constants below have been updated after chip characterization on ATE +#define VOLTAGE_SSS_LOW_MV (1075UL) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ +#define VOLTAGE_SSS_MED_MV (1175UL) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_SSS_HIG_MV (1200UL) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ + +#define VOLTAGE_NNN_LOW_MV (1025UL) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ +#define VOLTAGE_NNN_MED_MV (1100UL) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_NNN_HIG_MV (1150UL) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ + +#define VOLTAGE_FFF_LOW_MV (1025UL) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ +#define VOLTAGE_FFF_MED_MV (1100UL) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_FFF_HIG_MV (1150UL) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +/******************************************************************************* + * LOCAL FUNCTIONS PROTOTYPES + ******************************************************************************/ +static void POWER_WaitLDOCoreInit(void); +static void POWER_SRAMPowerUpDelay(void); +static void POWER_PowerCycleCpu(void); +static void POWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg); +static uint32_t POWER_WakeUpIOCtrl(uint32_t p_wakeup_io_ctrl); +static uint32_t POWER_SetLdoAoLdoMemVoltage(uint32_t p_lp_mode); +static void POWER_SetSystemPowerProfile(v_system_power_profile_t power_profile); +static void POWER_SetVoltageForProcess(v_system_power_profile_t power_profile); +static lowpower_process_corner_enum POWER_GetPartProcessCorner(void); +static void POWER_SetSystemVoltage(uint32_t system_voltage_mv); +static void POWER_SetSystemClock12MHZ(void); +static void POWER_SRAMSetRegister(power_sram_index_t sram_index, uint32_t power_mode); +static void POWER_SRAMActiveToLightSleep(power_sram_index_t sram_index); +static void POWER_SRAMActiveToDeepSleep(power_sram_index_t sram_index); +static void POWER_SRAMActiveToShutDown(power_sram_index_t sram_index); +static void POWER_SRAMLightSleepToActive(power_sram_index_t sram_index); +static void POWER_SRAMDeepSleepToActive(power_sram_index_t sram_index); +static void POWER_SRAMShutDownToActive(power_sram_index_t sram_index); + +/** + * brief SoC Power Management Controller initialization + * return power_status_t + */ +power_status_t POWER_PowerInit(void) +{ + // To speed up PMC configuration, change PMC clock from 1 MHz to 12 MHz. + // Set Power Mode to "ACTIVE" (required specially when waking up from DEEP POWER-DOWN) + PMC->CTRL = (PMC->CTRL | PMC_CTRL_SELCLOCK_MASK) & (~PMC_CTRL_LPMODE_MASK); + + // Check that no time out occured during the hardware wake-up process + if (PMC->TIMEOUTEVENTS != 0) + { + // A least 1 time-out error occured. + return kPOWER_Status_Fail; + } + + // Set up wake-up IO pad control source : IOCON ((WAKEUPIO_ENABLE = 0) + PMC->WAKEUPIOCTRL &= ~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK; + + // Set LDO_FLASHNV output voltage + PMC->LDOFLASHNV = (PMC->LDOFLASHNV & (~PMC_LDOFLASHNV_VADJ_MASK)) | PMC_LDOFLASHNV_VADJ(V_LDO_1P850); + + // Set LDO_EFUSE_PROG output voltage + PMC->LDOEFUSEPROG = (PMC->LDOEFUSEPROG & (~PMC_LDOEFUSEPROG_VADJ_MASK)) | PMC_LDOEFUSEPROG_VADJ(V_LDO_1P850); + + // Configure the voltage level of LDO CORE Low Power mode (TODO :: :: Temporarily set to 0.9V; target is 0.8 V)*/ + PMC->LDOCORE0 = (PMC->LDOCORE0 & (~PMC_LDOCORE0_LPREGREFSEL_MASK)) | PMC_LDOCORE0_LPREGREFSEL(V_LDOCORE_LP_0P900); + + // SRAM uses Voltage Scaling in all Low Power modes + PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); + + // Enable Analog References fast wake-up in case of wake-up from all low power modes and Hardware Pin reset + PMC->REFFASTWKUP = PMC->REFFASTWKUP | PMC_REFFASTWKUP_LPWKUP_MASK | PMC_REFFASTWKUP_HWWKUP_MASK; + + // Enable FRO192MHz shut-off glitch suppression. + // TODO :: :: Check the Power Consumption Impact of this setting during DEEP-SLEEP and POWER-DOWN. + // (Supposed to be 1 to 2uA in typical conditions). If the impe + // + ANACTRL->OSC_TESTBUS = 0x1; + + return kPOWER_Status_Success; +} + +/** + * brief + * return power_status_t + */ +power_status_t POWER_SetCorePowerSource(power_core_pwr_source_t pwr_source) +{ + uint32_t pmc_reg_data; + + switch (pwr_source) + { + case kPOWER_CoreSrcDCDC: + { + // Enable DCDC (1st step) + PMC->CMD = PMC_CMD_DCDCENABLE_MASK; + + // Wait until DCDC is enabled + while ((PMC->STATUSPWR & PMC_STATUSPWR_DCDCPWROK_MASK) == 0) + ; + + // Disable LDO Core Low Power Mode (2nd step) + PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; + + // Disable LDO Core High Power Mode (3rd step) + PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; + + // Check PMC Finite State Machines status + pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | + PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); + if (pmc_reg_data != (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) + { + // Error : only DCDC and LDO CORE Exponential Timer must both be enabled. + return (kPOWER_Status_Fail); + } + } + break; + + case kPOWER_CoreSrcLDOCoreHP: + { + // Enable LDO Core High Power Mode (1st step) + PMC->CMD = PMC_CMD_LDOCOREHIGHPWRENABLE_MASK; + + // Note: Once LDO_CORE High Power Mode has been enabled, + // at least 2us are required before one can reliabily sample + // the LDO Low Voltage Detectore Output. + POWER_WaitLDOCoreInit(); + + // Wait until LDO CORE High Power is enabled + while ((PMC->STATUSPWR & PMC_STATUSPWR_LDOCOREPWROK_MASK) == 0) + ; + + // Disable DCDC (2nd step) + PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; + + // Disable LDO Core Low Power Mode (3rd step) + PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; + + // Check PMC Finite State Machines status + pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | + PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); + if (pmc_reg_data != PMC_STATUS_FSMLDOCOREHPENABLE_MASK) + { + // Error : only LDO CORE High Power mode must both be enabled. + return (kPOWER_Status_Fail); + } + } + break; + + case kPOWER_CoreSrcLDOCoreLP: + { + // Enable LDO Core Low Power Mode (1st step) + PMC->CMD = PMC_CMD_LDOCORELOWPWRENABLE_MASK; + + // Disable LDO Core High Power Mode (2nd step) + PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; + + // Disable DCDC (3rd step) + PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; + + // Check PMC Finite State Machines status + pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | + PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); + if (pmc_reg_data != (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) + { + // Error : only LDO CORE Low Power mode and LDO CORE Exponential Timer must both be enabled. + return (kPOWER_Status_Fail); + } + } + break; + + case kPOWER_CoreSrcExternal: + { + // Disable LDO Core Low Power Mode (1st step) + PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; + + // Disable LDO Core High Power Mode (2nd step) + PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; + + // Disable DCDC (3rd step) + PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; + + // Check PMC Finite State Machines status + pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | + PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK); + if (pmc_reg_data != 0) + { + // Error : All power sources must be disabled. + return (kPOWER_Status_Fail); + } + } + break; + + default: // Not supported + return (kPOWER_Status_Fail); + + } // End switch (pwr_source) + + return (kPOWER_Status_Success); +} + +/** + * brief + * @param : + * return power_core_pwr_source_t + */ +power_core_pwr_source_t POWER_GetCorePowerSource(void) +{ + uint32_t reg_status, reg_statuspwr; + + reg_status = PMC->STATUS; + reg_statuspwr = PMC->STATUSPWR; + + if ((reg_statuspwr & PMC_STATUSPWR_DCDCPWROK_MASK) && (reg_status & PMC_STATUS_FSMDCDCENABLE_MASK)) + { + /* DCDC */ + return (kPOWER_CoreSrcDCDC); + } + else + { + if ((reg_statuspwr & PMC_STATUSPWR_LDOCOREPWROK_MASK) && (reg_status & PMC_STATUS_FSMLDOCOREHPENABLE_MASK)) + { + /* LDO_CORE High Power Mode */ + return (kPOWER_CoreSrcLDOCoreHP); + } + else + { + if (reg_status & PMC_STATUS_FSMLDOCORELPENABLE_MASK) + { + /* LDO_CORE Low Power Mode */ + return (kPOWER_CoreSrcLDOCoreLP); + } + else + { + /* External */ + return (kPOWER_CoreSrcExternal); + } + } + } +} + +/** + * brief + * return nothing + */ +power_status_t POWER_CorePowerSourceControl(power_core_pwr_source_t pwr_source, power_core_pwr_state_t pwr_state) +{ + switch (pwr_source) + { + case kPOWER_CoreSrcDCDC: + { + if (pwr_state == kPOWER_CorePwrEnable) + { + // Enable DCDC + PMC->CMD = PMC_CMD_DCDCENABLE_MASK; + + // Wait until DCDC is enabled + while ((PMC->STATUSPWR & PMC_STATUSPWR_DCDCPWROK_MASK) == 0) + ; + + // Check PMC Finite State Machines status + if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) == 0) + { + // Error : DCDC not enabled. + return (kPOWER_Status_Fail); + } + } + else + { + // Disable DCDC + PMC->CMD = PMC_CMD_DCDCDISABLE_MASK; + + // Check PMC Finite State Machines status + if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) != 0) + { + // Error : DCDC is enabled. + return (kPOWER_Status_Fail); + } + } + } + break; + + case kPOWER_CoreSrcLDOCoreHP: + { + if (pwr_state == kPOWER_CorePwrEnable) + { + // Enable LDO Core High Power Mode + PMC->CMD = PMC_CMD_LDOCOREHIGHPWRENABLE_MASK; + + // Note: Once LDO_CORE High Power Mode has been enabled, + // at least 2us are required before one can reliabily sample + // the LDO Low Voltage Detector Output. + POWER_WaitLDOCoreInit(); + + // Wait until LDO CORE High Power is enabled + while ((PMC->STATUSPWR & PMC_STATUSPWR_LDOCOREPWROK_MASK) == 0) + ; + + // Check PMC Finite State Machines status + if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) == 0) + { + // Error : LDO CORE High Power mode is not enabled. + return (kPOWER_Status_Fail); + } + } + else + { + // Disable LDO Core High Power Mode + PMC->CMD = PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK; + + // Check PMC Finite State Machines status + if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) != 0) + { + // Error : LDO CORE High Power mode is enabled. + return (kPOWER_Status_Fail); + } + } + } + break; + + case kPOWER_CoreSrcLDOCoreLP: + { + if (pwr_state == kPOWER_CorePwrEnable) + { + // Enable LDO Core Low Power Mode (1st step) + PMC->CMD = PMC_CMD_LDOCORELOWPWRENABLE_MASK; + + // Check PMC Finite State Machines status + if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) != + (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) + { + // Error : LDO CORE Low Power mode is not enabled. + return (kPOWER_Status_Fail); + } + } + else + { + // Disable LDO Core Low Power Mode + PMC->CMD = PMC_CMD_LDOCORELOWPWRDISABLE_MASK; + + // Check PMC Finite State Machines status + if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) != 0) + { + // Error : LDO CORE Low Power mode is enabled. + return (kPOWER_Status_Fail); + } + } + } + break; + + default: // Not supported + return (kPOWER_Status_Fail); + + } // End switch (pwr_source) + + return (kPOWER_Status_Success); +} + +/** + * brief + * return + */ +power_sram_pwr_mode_t POWER_GetSRAMPowerMode(power_sram_index_t sram_index) +{ + power_sram_pwr_mode_t pwr_mode; + uint32_t state; + uint32_t sram_ctrl_0 = PMC->SRAMCTRL0; + uint32_t sram_ctrl_1 = PMC->SRAMCTRL1; + + switch (sram_index) + { + case kPOWER_SRAM_IDX_RAM_X0: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_X0_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_00: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_00_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_01: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_01_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_02: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_02_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_03: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_03_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_10: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_10_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_20: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_20_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_30: + { + state = (sram_ctrl_0 >> PMC_SRAMCTRL0_RAM_30_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_40: + { + state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_40_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_41: + { + state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_41_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_42: + { + state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_42_LS_SHIFT) & 0xF; + break; + } + + case kPOWER_SRAM_IDX_RAM_43: + { + state = (sram_ctrl_1 >> PMC_SRAMCTRL1_RAM_43_LS_SHIFT) & 0xF; + break; + } + + default: + // Error + state = 0x6; // Active. + } + + switch (state) + { + case 0x6: + pwr_mode = kPOWER_SRAMPwrActive; + break; + + case 0xF: + pwr_mode = kPOWER_SRAMPwrLightSleep; + break; + + case 0x8: + pwr_mode = kPOWER_SRAMPwrDeepSleep; + break; + + case 0x9: + pwr_mode = kPOWER_SRAMPwrShutDown; + break; + + default: + pwr_mode = kPOWER_SRAMPwrActive; + } + + return (pwr_mode); +} + +/** + * brief + * return + */ +power_status_t POWER_SRAMPowerModeControl(power_sram_bit_t sram_inst, power_sram_pwr_mode_t pwr_mode) +{ + power_sram_pwr_mode_t current_pwr_mode; + power_sram_index_t sram_index = kPOWER_SRAM_IDX_RAM_X0; + + sram_inst = (power_sram_bit_t)((uint32_t)sram_inst & 0x3FFF); /* Only SRAM from RAM_X0 to RAM_F3 */ + while ((uint32_t)sram_inst != 0) + { + // There is a least 1 SRAM instance to be processed + if ((uint32_t)sram_inst & 0x1) + { + // Get current SRAM state + current_pwr_mode = POWER_GetSRAMPowerMode(sram_index); + + // The SRAM instance Power state must be updated + switch (current_pwr_mode) + { + case kPOWER_SRAMPwrActive: + { // Active + switch (pwr_mode) + { + case kPOWER_SRAMPwrActive: + { // Active ---> Active : there is nothing to do. + break; + } + + case kPOWER_SRAMPwrLightSleep: + { // Active ---> Light Sleep + POWER_SRAMActiveToLightSleep(sram_index); + break; + } + + case kPOWER_SRAMPwrDeepSleep: + { // Active ---> Deep Sleep + POWER_SRAMActiveToDeepSleep(sram_index); + break; + } + + case kPOWER_SRAMPwrShutDown: + { // Active ---> Shut Down + POWER_SRAMActiveToShutDown(sram_index); + break; + } + + default: + // Do nothing. + ; + } // switch( pwr_mode ) + + break; + } + + case kPOWER_SRAMPwrLightSleep: + { // Light Sleep + switch (pwr_mode) + { + case kPOWER_SRAMPwrActive: + { // Light Sleep ---> Active + POWER_SRAMLightSleepToActive(sram_index); + break; + } + + case kPOWER_SRAMPwrLightSleep: + { // Light Sleep ---> Light Sleep : there is nothing to do. + break; + } + + default: + // Light Sleep ---> Shut Down : FORBIDDEN (error) + // Light Sleep ---> Deep Sleep : FORBIDDEN (error) + return (kPOWER_Status_Fail); + } // switch( pwr_mode ) + + break; + } + + case kPOWER_SRAMPwrDeepSleep: + { // Deep Sleep + switch (pwr_mode) + { + case kPOWER_SRAMPwrActive: + { // Deep Sleep ---> Active + POWER_SRAMDeepSleepToActive(sram_index); + break; + } + + case kPOWER_SRAMPwrDeepSleep: + { // Deep Sleep ---> Deep Sleep : there is nothing to do. + break; + } + + default: + // Deep Sleep ---> Shut Down : FORBIDDEN (error) + // Deep Sleep ---> Light Sleep : FORBIDDEN (error) + return (kPOWER_Status_Fail); + } // switch( pwr_mode ) + + break; + } + + case kPOWER_SRAMPwrShutDown: + { // Shutdown + switch (pwr_mode) + { + case kPOWER_SRAMPwrActive: + { // Shutdown ---> Active + POWER_SRAMShutDownToActive(sram_index); + break; + } + + case kPOWER_SRAMPwrShutDown: + { // Shutdown ---> Shut Down : there is nothing to do. + break; + } + + default: + // Shutdown ---> Deep Sleep : FORBIDDEN (error) + // Shutdown ---> Light Sleep : FORBIDDEN (error) + return (kPOWER_Status_Fail); + } // switch( pwr_mode ) + + break; + } + + default: + // Do nothing + ; + } // switch( current_pwr_mode ) + } // if ( (uint32_t)sram_inst & 0x1 ) + + // Move to next SRAM index + sram_inst = (power_sram_bit_t)((uint32_t)sram_inst >> 1); + sram_index = (power_sram_index_t)((uint32_t)sram_index + 1); + } // while ((uint32_t)sram_inst != 0 ) + + return (kPOWER_Status_Success); +} + +/** + * @brief Configures and enters in SLEEP low power mode + * @return Nothing + */ +void POWER_EnterSleep(void) +{ + uint32_t pmsk; + pmsk = __get_PRIMASK(); /* Save CORTEX-M33 interrupt configuration */ + __disable_irq(); /* Disable all interrupts */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; /* CORTEX-M33 uses "Sleep" mode */ + __WFI(); /* CORTEX-M33 enters "Sleep" mode */ + __set_PRIMASK(pmsk); /* Restore CORTEX-M33 interrupt configuration (after wake up) */ +} + +/** + * brief PMC Deep Sleep function call + * return nothing + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd[2], + uint32_t sram_retention_ctrl, + uint32_t wakeup_interrupts[4], + uint32_t hardware_wake_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t pmc_reset_ctrl; + + /* Clear Low Power Mode configuration variable */ + memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG = LOWPOWER_CFG_LPMODE_DEEPSLEEP << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ + + /* Make sure LDO MEM & Analog references will stay powered, Shut down ROM & LDO Flash NV */ + lv_low_power_mode_cfg.PDCTRL[0] = + (~exclude_from_pd[0] & ~kPDRUNCFG_PD_LDOMEM & ~kPDRUNCFG_PD_BIAS) | kPDRUNCFG_PD_ROM | kPDRUNCFG_PD_LDOFLASHNV; + lv_low_power_mode_cfg.PDCTRL[1] = ~exclude_from_pd[1]; + + // Voltage control in DeepSleep Low Power Modes + lv_low_power_mode_cfg.VOLTAGE = POWER_SetLdoAoLdoMemVoltage(LOWPOWER_CFG_LPMODE_DEEPSLEEP); + + // SRAM retention control during DEEP-SLEEP + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl & kPOWER_SRAM_DSLP_MASK; + + /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ + if (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_DMIC | LOWPOWER_HWWAKE_SDMA0 | + LOWPOWER_HWWAKE_SDMA1 | LOWPOWER_HWWAKE_DAC)) + { + lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; + } + + // @NOTE Niobe4mini: update with new BOD reset enable management + pmc_reset_ctrl = PMC->RESETCTRL; + if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)) == + ((0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT))) + { + /* BoD CORE reset is activated, so make sure BoD Core and Biasing won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL[0] &= ~kPDRUNCFG_PD_BODCORE & ~kPDRUNCFG_PD_BIAS; + } + + if ((pmc_reset_ctrl & + (PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK)) == + ((0x1 << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT) | + (0x1 << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT))) + { + /* BoD VDDMAIN reset is activated, so make sure BoD VDDMAIN and Biasing won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL[0] &= ~kPDRUNCFG_PD_BODVDDMAIN & ~kPDRUNCFG_PD_BIAS; + } + + /* CPU Wake up & Interrupt sources control */ + lv_low_power_mode_cfg.WAKEUPSRC[0] = lv_low_power_mode_cfg.WAKEUPINT[0] = wakeup_interrupts[0]; + lv_low_power_mode_cfg.WAKEUPSRC[1] = lv_low_power_mode_cfg.WAKEUPINT[1] = wakeup_interrupts[1]; + lv_low_power_mode_cfg.WAKEUPSRC[2] = lv_low_power_mode_cfg.WAKEUPINT[2] = wakeup_interrupts[2]; + lv_low_power_mode_cfg.WAKEUPSRC[3] = lv_low_power_mode_cfg.WAKEUPINT[3] = wakeup_interrupts[3]; + + /* Enter low power mode */ + POWER_SetLowPowerMode(&lv_low_power_mode_cfg); +} + +/** + * brief PMC power Down function call + * return nothing + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd[1], + uint32_t sram_retention_ctrl, + uint32_t wakeup_interrupts[4], + uint32_t cpu_retention_addr) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + + // Clear Low Power Mode configuration variable + memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + // Configure Low Power Mode configuration variable : POWER DOWN mode + lv_low_power_mode_cfg.CFG = LOWPOWER_CFG_LPMODE_POWERDOWN << LOWPOWER_CFG_LPMODE_INDEX; + + // Only FRO32K, XTAL32K, FRO1M, COMP, BIAS and VREF can stay powered during POWERDOWN. + // LDO_MEM is enabled (because at least 1 SRAM instance will be required - for CPU state retention -) + lv_low_power_mode_cfg.PDCTRL[0] = ~(exclude_from_pd[0] | kPDRUNCFG_PD_LDOMEM); + lv_low_power_mode_cfg.PDCTRL[1] = 0xFFFFFFFF; + + // Force Bias activation if Analog Comparator is required, otherwise, disable it. + if ((lv_low_power_mode_cfg.PDCTRL[0] & kPDRUNCFG_PD_COMP) == 0) + { + // Analog Comparator is required du ring power-down: Enable Biasing + lv_low_power_mode_cfg.PDCTRL[0] = lv_low_power_mode_cfg.PDCTRL[0] & (~kPDRUNCFG_PD_BIAS); + } + else + { + // Analog Comparator is not required du ring power-down: Disable Biasing + lv_low_power_mode_cfg.PDCTRL[0] = lv_low_power_mode_cfg.PDCTRL[0] | kPDRUNCFG_PD_BIAS; + } + +// SRAM retention control during POWER-DOWN + +// Depending on where the user wants to locate the CPU state retention data, +// the associated SRAM instance will be automatically put in retention mode. +// The boundaries are defined in such a way that the area where the CPU state +// will be retained does not cross any SRAM instance boundary. +// Per hardware design, 1540 bytes are necessary to store the whole CPU state +#define RAM_00_CPU_RET_ADDR_MIN 0x20000000UL // RAM_00 start address +#define RAM_00_CPU_RET_ADDR_MAX 0x200009FCUL // RAM_00 start address + 1540 - 1 +#define RAM_01_CPU_RET_ADDR_MIN 0x20001000UL // RAM_01 start address +#define RAM_01_CPU_RET_ADDR_MAX 0x200019FCUL // RAM_01 start address + 1540 - 1 +#define RAM_02_CPU_RET_ADDR_MIN 0x20002000UL // RAM_02 start address +#define RAM_02_CPU_RET_ADDR_MAX 0x200029FCUL // RAM_02 start address + 1540 - 1 +#define RAM_03_CPU_RET_ADDR_MIN 0x20003000UL // RAM_03 start address +#define RAM_03_CPU_RET_ADDR_MAX 0x200039FCUL // RAM_03 start address + 1540 - 1 + + if ((cpu_retention_addr >= RAM_00_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_00_CPU_RET_ADDR_MAX)) + { + // Inside RAM_00 + sram_retention_ctrl |= kPOWER_SRAM_RAM_00; + } + else + { + if ((cpu_retention_addr >= RAM_01_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_01_CPU_RET_ADDR_MAX)) + { + // Inside RAM_01 + sram_retention_ctrl |= kPOWER_SRAM_RAM_01; + } + else + { + if ((cpu_retention_addr >= RAM_02_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_02_CPU_RET_ADDR_MAX)) + { + // Inside RAM_02 + sram_retention_ctrl |= kPOWER_SRAM_RAM_02; + } + else + { + if ((cpu_retention_addr >= RAM_03_CPU_RET_ADDR_MIN) && (cpu_retention_addr <= RAM_03_CPU_RET_ADDR_MAX)) + { + // Inside RAM_03 + sram_retention_ctrl |= kPOWER_SRAM_RAM_03; + } + else + { + // Error! Therefore, we locate the retention area in RAM_00 + cpu_retention_addr = 0x20000000UL; + sram_retention_ctrl |= kPOWER_SRAM_RAM_00; + } + } + } + } + + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl & kPOWER_SRAM_PDWN_MASK; + + // Voltage control in Low Power Modes + // The Memories Voltage settings below are for voltage scaling + lv_low_power_mode_cfg.VOLTAGE = POWER_SetLdoAoLdoMemVoltage(LOWPOWER_CFG_LPMODE_POWERDOWN); + + /* CPU0 retention Address */ + lv_low_power_mode_cfg.CPURETCTRL = ((cpu_retention_addr >> 1) | LOWPOWER_CPURETCTRL_ENA_MASK) & + (LOWPOWER_CPURETCTRL_MEMBASE_MASK | LOWPOWER_CPURETCTRL_ENA_MASK); + + /* CPU Wake up & Interrupt sources control */ + lv_low_power_mode_cfg.WAKEUPSRC[0] = lv_low_power_mode_cfg.WAKEUPINT[0] = + wakeup_interrupts[0] & (WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP | + WAKEUP_RTC_ALARM_WAKEUP | WAKEUP_WAKEUP_MAILBOX); + lv_low_power_mode_cfg.WAKEUPSRC[1] = lv_low_power_mode_cfg.WAKEUPINT[1] = + wakeup_interrupts[1] & WAKEUP_OS_EVENT_TIMER; + lv_low_power_mode_cfg.WAKEUPSRC[2] = lv_low_power_mode_cfg.WAKEUPINT[2] = 0UL; + lv_low_power_mode_cfg.WAKEUPSRC[3] = lv_low_power_mode_cfg.WAKEUPINT[3] = wakeup_interrupts[3] & WAKEUP_ITRC; + + /* Enter low power mode */ + POWER_SetLowPowerMode(&lv_low_power_mode_cfg); +} + +/** + * brief PMC Deep Power-Down function call + * return nothing + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd[1], + uint32_t sram_retention_ctrl, + uint32_t wakeup_interrupts[2], + uint32_t wakeup_io_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + + // Clear Low Power Mode configuration variable + memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + // Configure Low Power Mode configuration variable : DEEP POWER-DOWN mode + lv_low_power_mode_cfg.CFG = LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN << LOWPOWER_CFG_LPMODE_INDEX; + + // Note: only FRO32K, XTAL32K, FRO1M and LDO_MEM can stay powered during DEEP POWER-DOWN + lv_low_power_mode_cfg.PDCTRL[0] = ~exclude_from_pd[0]; + lv_low_power_mode_cfg.PDCTRL[1] = 0xFFFFFFFF; + + // SRAM retention control during DEEP POWER-DOWN + // RAM_X0, RAM_02 and RAM_03 excluded: they are used by ROM Boot code + sram_retention_ctrl = sram_retention_ctrl & kPOWER_SRAM_DPWD_MASK; + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + // Sanity check: if retention is required for any SRAM instance other than RAM_00, make sure LDO MEM will stay + // powered */ + if ((sram_retention_ctrl & (~kPOWER_SRAM_RAM_00)) != 0) + { + // SRAM retention is required : enable LDO_MEM + lv_low_power_mode_cfg.PDCTRL[0] &= ~kPDRUNCFG_PD_LDOMEM; + } + else + { + // No SRAM retention required : disable LDO_MEM + lv_low_power_mode_cfg.PDCTRL[0] |= kPDRUNCFG_PD_LDOMEM; + } + + // Voltage control in Low Power Modes + // The Memories Voltage settings below are for voltage scaling + lv_low_power_mode_cfg.VOLTAGE = POWER_SetLdoAoLdoMemVoltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN); + + // Wake up sources control + lv_low_power_mode_cfg.WAKEUPSRC[0] = lv_low_power_mode_cfg.WAKEUPINT[0] = + wakeup_interrupts[0] & + WAKEUP_RTC_ALARM_WAKEUP; /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP */ + lv_low_power_mode_cfg.WAKEUPSRC[1] = lv_low_power_mode_cfg.WAKEUPINT[1] = + wakeup_interrupts[1] & WAKEUP_OS_EVENT_TIMER; /* CPU Wake up sources control : only WAKEUP_OS_EVENT_TIMER */ + lv_low_power_mode_cfg.WAKEUPSRC[2] = lv_low_power_mode_cfg.WAKEUPINT[2] = 0UL; + lv_low_power_mode_cfg.WAKEUPSRC[3] = lv_low_power_mode_cfg.WAKEUPINT[3] = 0UL; + + /* Wake up I/O sources */ + lv_low_power_mode_cfg.WAKEUPIOSRC = POWER_WakeUpIOCtrl(wakeup_io_ctrl); + + /* Enter low power mode */ + POWER_SetLowPowerMode(&lv_low_power_mode_cfg); + + /*** We'll reach this point ONLY and ONLY if the DEEPPOWERDOWN has not been taken (for instance because an RTC or + * OSTIMER interrupt is pending) ***/ +} + +/** + * @brief Configures the 5 wake-up pins to wake up the part in DEEP-SLEEP and POWER-DOWN low power modes. + * @param wakeup_io_cfg_src : for all wake-up pins : indicates if the config is from IOCON or from PMC. + * @param wakeup_io_ctrl: the 5 wake-up pins configurations (see "LOWPOWER_WAKEUPIOSRC_*" #defines) + + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - To be called just before POWER_EnterDeepSleep() or POWER_EnterPowerDown(). + */ +/** + * brief PMC Deep Power-Down function call + * return nothing + */ +void POWER_SetWakeUpPins(uint32_t wakeup_io_cfg_src, uint32_t wakeup_io_ctrl) +{ + if (wakeup_io_cfg_src == LOWPOWER_WAKEUPIO_CFG_SRC_IOCON) + { + /* All wake-up pins controls are coming from IOCON */ + + wakeup_io_ctrl = wakeup_io_ctrl | LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK | + LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK | LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK | + LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK | + LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK; /* Make sure IOCON is not modified inside + POWER_WakeUpIOCtrl */ + + PMC->WAKEUPIOCTRL = POWER_WakeUpIOCtrl(wakeup_io_ctrl) & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); + } + else + { + /* All wake-up pins controls are coming from PMC */ + PMC->WAKEUPIOCTRL = POWER_WakeUpIOCtrl(wakeup_io_ctrl) | PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK; + } + + /* Release Wake up I/O reset (WAKEUPIO_RSTN = 1)*/ + PMC->WAKEUPIOCTRL |= PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK; +} + +void POWER_GetWakeUpCause(power_reset_cause_t *reset_cause, + power_boot_mode_t *boot_mode, + power_wakeup_pin_t *wakeup_pin_cause) +{ + uint32_t reset_cause_reg; + uint32_t boot_mode_reg; + uint32_t wakeupio_cause_reg; + + boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; + + switch (boot_mode_reg) + { + case 1: + /* DEEP-SLEEP */ + *boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; + break; + case 2: + /* POWER-DOWN */ + *boot_mode = kBOOT_MODE_LP_POWER_DOWN; + break; + case 3: + /* DEEP-POWER-DOWN */ + *boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; + break; + default: + /* All non Low Power Mode wake-up */ + *boot_mode = kBOOT_MODE_POWER_UP; + } + + wakeupio_cause_reg = PMC->WAKEIOCAUSE; + + if (boot_mode_reg == 0) + { + /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset: + * PMC has been reset, so wake up pin event not expected to have happened. */ + *wakeup_pin_cause = kWAKEUP_PIN_NONE; + } + else + { + switch (((wakeupio_cause_reg & PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK) >> + PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT)) + { + case 0x0: + *wakeup_pin_cause = kWAKEUP_PIN_NONE; + break; + case 0x1: + *wakeup_pin_cause = kWAKEUP_PIN_0; + break; + case 0x2: + *wakeup_pin_cause = kWAKEUP_PIN_1; + break; + case 0x4: + *wakeup_pin_cause = kWAKEUP_PIN_2; + break; + case 0x8: + *wakeup_pin_cause = kWAKEUP_PIN_3; + break; + case 0x10: + *wakeup_pin_cause = kWAKEUP_PIN_4; + break; + default: + /* Mutiple */ + *wakeup_pin_cause = kWAKEUP_PIN_MULTIPLE; + break; + } + } + + reset_cause_reg = PMC->AOREG1; + + /* + * Prioritize interrupts source with respect to how critical they are. + */ + if (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK) + { /* Code Watchdog Reset */ + *reset_cause = kRESET_CAUSE_CDOGRESET; + } + else + { + if (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK) + { /* Watchdog Timer Reset */ + *reset_cause = kRESET_CAUSE_WDTRESET; + } + else + { + if (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK) + { /* ARM System Reset */ + *reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; + } + else + { + if (boot_mode_reg != 3) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset, + DEEP-SLEEP and POWER-DOWN */ + { + /* + * Prioritise Reset causes, starting from the strongest (Power On Reset) + */ + if (reset_cause_reg & PMC_AOREG1_POR_MASK) + { /* Power On Reset */ + *reset_cause = kRESET_CAUSE_POR; + } + else + { + if (reset_cause_reg & PMC_AOREG1_BODRESET_MASK) + { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ + *reset_cause = kRESET_CAUSE_BODRESET; + } + else + { + if (reset_cause_reg & PMC_AOREG1_PADRESET_MASK) + { /* Hardware Pin Reset */ + *reset_cause = kRESET_CAUSE_PADRESET; + } + else + { + if (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK) + { /* Software triggered Reset */ + *reset_cause = kRESET_CAUSE_SWRRESET; + } + else + { /* Unknown Reset Cause (shall never occur) */ + *reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + } + } + } + } + } + else /* boot_mode_reg == 3 : DEEP-POWER-DOWN */ + { + switch (((reset_cause_reg & PMC_AOREG1_DPD_EVENTS_ORDER_MASK) >> PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT)) + { + case 1: + *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; + break; + case 2: + *reset_cause = kRESET_CAUSE_DPDRESET_RTC; + break; + case 3: + *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; + break; + case 4: + *reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; + break; + case 5: + *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; + break; + case 6: + *reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; + break; + case 7: + *reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; + break; + default: + /* Unknown Reset Cause (shall not occur) */ + *reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + break; + } + } // if ( boot_mode != 3 ) + + } // if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) + + } // if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) + + } // if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz) +{ + if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) + { + /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ + POWER_SetSystemPowerProfile(V_SYSTEM_POWER_PROFILE_LOW); + POWER_SetVoltageForProcess(V_SYSTEM_POWER_PROFILE_LOW); + } + else + { + if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) + { + /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ + POWER_SetSystemPowerProfile(V_SYSTEM_POWER_PROFILE_MEDIUM); + POWER_SetVoltageForProcess(V_SYSTEM_POWER_PROFILE_MEDIUM); + } + else + { + /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ + POWER_SetSystemPowerProfile(V_SYSTEM_POWER_PROFILE_HIGH); + POWER_SetVoltageForProcess(V_SYSTEM_POWER_PROFILE_HIGH); + } + } +} + +/** + * @brief Wait at least 2us. + * @param None + * @return Nothing + */ + +static void POWER_WaitLDOCoreInit(void) +{ + /* + * Note: Once LDO_CORE High Power Mode has been enabled, + * at least 2us are required before one can reliabily sample + * the LDO Low Voltage Detectore Output. + * The PMC clock being 12 MHz, with at least 5 dummy read + * operations, it is guaranteed by design that, whatever the + * System/CPU clock frequency (up to 200 MHz). + */ + + volatile uint32_t reg_data; + for (uint32_t i = 0; i < 5; i++) + reg_data = PMC->STATUSPWR; /* Dummy Read */ + (void)reg_data; +} + +/** + * @brief Wait at least 2us. + * @param None + * @return Nothing + */ + +static void POWER_SRAMPowerUpDelay(void) +{ + /* + * Note: Wait about 1 us + * The PMC clock being 12 MHz, with at least 3 dummy read + * operations, it is guaranteed by design that when this , + * function is called, at least 1 us will elapse, + * whatever the System/CPU clock frequency (up to 200 MHz). + */ + + volatile uint32_t reg_data; + for (uint32_t i = 0; i < 3; i++) + reg_data = PMC->STATUSPWR; /* Dummy Read */ + (void)reg_data; +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * @param None + * @return Nothing + */ + +static void POWER_PowerCycleCpu(void) +{ + /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ + POWER_SetSystemClock12MHZ(); + + /* Configure the Cortex-M33 in Deep Sleep mode */ + SCB->SCR = SCB->SCR | SCB_SCR_SLEEPDEEP_Msk; + + /* Enter in low power mode */ + __WFI(); + + /* Configure the Cortex-M33 in Active mode */ + SCB->SCR = SCB->SCR & (~SCB_SCR_SLEEPDEEP_Msk); +}; + +/** + * @brief Configures and enters in low power mode + * @param : p_lowpower_cfg + * @return Nothing + */ +static void POWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg) +{ + uint32_t i, primask, reg_data; + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable[4]; + uint32_t analog_ctrl_regs[7]; /* To store Analog Controller Registers */ + uint32_t vref_regs[4]; /* To store VREF Registers */ + uint32_t fmccr_reg; /* FMC Configuration Register */ + + /* Save FMC configuration */ + fmccr_reg = SYSCON->FMCCR; + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + // Save the configuration of the CPU interrupt enable Registers (because they are overwritten in + // POWER_SetLowPowerMode) + for (i = 0; i < 4; i++) + { + cpu0_int_enable[i] = NVIC->ISER[i]; + } + + uint32_t low_power_mode = (p_lowpower_cfg->CFG & LOWPOWER_CFG_LPMODE_MASK) >> LOWPOWER_CFG_LPMODE_INDEX; + + /* Set the Low power mode.*/ + PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_LPMODE(low_power_mode); + + /* SRAM in Retention modes */ + PMC->SRAMRETCTRL = p_lowpower_cfg->SRAMRETCTRL; + + /* Configure the voltage level of the Always On domain, Memories LDO */ + PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_PWD_MASK) & (~PMC_LDOPMU_VADJ_BOOST_PWD_MASK)) | + PMC_LDOPMU_VADJ_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_PMU_MASK) >> + LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | + PMC_LDOPMU_VADJ_BOOST_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK) >> + LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX); + + PMC->LDOMEM = (PMC->LDOMEM & (~PMC_LDOMEM_VADJ_PWD_MASK) & (~PMC_LDOMEM_VADJ_BOOST_PWD_MASK)) | + PMC_LDOMEM_VADJ_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_MEM_MASK) >> + LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | + PMC_LDOMEM_VADJ_BOOST_PWD((p_lowpower_cfg->VOLTAGE & LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK) >> + LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX); + + /* + * Enable wake up interrupt. + * Rational : we enable each interrupt (NVIC->ISER) that can wake up the CPU here (before the __disable_irq() + * below): Hence, if an interrupt was pending and not treated before (for any reason), the CPU will jump to that + * interrupt handler before trying to enter the low power mode. + * VERY IMPORTANT : Also, any interrupt set in NVIC->ISER, even though __disable_irq(), will make the CPU + * go out of the Deep Sleep mode. + */ + for (i = 0; i < 4; i++) + { + NVIC->ISER[i] = p_lowpower_cfg->WAKEUPINT[i]; /* Enable wake-up interrupt */ + SYSCON->STARTER[i] = p_lowpower_cfg->WAKEUPSRC[i]; /* Enable wake-up sources */ + } + + /* Save the configuration of the Priority Mask Register */ + primask = __get_PRIMASK(); + + switch (low_power_mode) + { + case LOWPOWER_CFG_LPMODE_DEEPSLEEP: + { + /* DEEP SLEEP power mode */ + + uint32_t bod_core_trglvl; /* BoD Core trigger level */ + uint32_t css_ctrl, syscon_css_clk_ctrl, syscon_css_clk_pclk_hclk; + uint32_t syscon_autoclkgateoverride_reg; /* AUTOCLKGATEOVERRIDE Configuration Register */ + + /* Analog Modules to be shut off */ + PMC->PDSLEEPCFG0 = p_lowpower_cfg->PDCTRL[0]; + PMC->PDSLEEPCFG1 = p_lowpower_cfg->PDCTRL[1]; + + /* Saving AUTOCLKGATEOVERRIDE register*/ + syscon_autoclkgateoverride_reg = SYSCON->AUTOCLKGATEOVERRIDE; + + /* DMA transactions with Flexcomm during DEEP SLEEP */ + SYSCON->HARDWARESLEEP = p_lowpower_cfg->HWWAKE; + /* Enable autoclockgating on SDMA0 and SDMA1 during DeepSleep*/ + SYSCON->AUTOCLKGATEOVERRIDE = + 0xC0DE0000 | (syscon_autoclkgateoverride_reg & + (~(SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK | SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK))); + + /* Make sure DEEP POWER DOWN reset is disabled */ + PMC->RESETCTRL = PMC->RESETCTRL & (~PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK); + + /* Adjust BoD Core Trip point . Currently set to 700 mV. TODO :: :: Check this value. */ + reg_data = PMC->BODCORE; + bod_core_trglvl = (reg_data & PMC_BODCORE_TRIGLVL_MASK) >> PMC_BODCORE_TRIGLVL_SHIFT; + PMC->BODCORE = (reg_data & (~PMC_BODCORE_TRIGLVL_MASK)) | PMC_BODCORE_TRIGLVL(kPOWER_BodCoreLevel700mv); + + // CSSV2 + { + syscon_css_clk_ctrl = SYSCON_CSS_CLK_CTRL_REG & (1U << 1); + + css_ctrl = 0U; + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL2 & (1U << 18); + /* Check if CSS is NOT in reset AND is clocked and enable, to avoid deadlock situations or a hardfault + */ + if (((SYSCON->PRESETCTRL2 & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (CSSV2_CTRL_REG & 0x1)) +#else + syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL[2] & (1U << 18); + /* Check if CSS is NOT in reset AND is clocked and enable, to avoid deadlock situations or a hardfault + */ + if (((SYSCON->PRESETCTRL[2] & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (CSSV2_CTRL_REG & 0x1)) +#endif + { + css_ctrl = CSSV2_CTRL_REG; + + /* Wait until CSS is in idle state (CSS_STATUS_BUSY_MASK) */ + while (CSSV2_STATUS_REG & 0x1) + ; + + /* Disable CSS */ + CSSV2_CTRL_REG = CSSV2_CTRL_REG & 0xFFFFFFFE; + + /* Swicth off i_css_clk/pclk/hclk */ + SYSCON->AHBCLKCTRLCLR[2] = (1U << 18); + } + + /* Switch off DTRNG clocks */ + SYSCON_CSS_CLK_CTRL_CLR_REG = (1U << 1); + } + + /* Disable all IRQs */ + __disable_irq(); + + /* + * - Switch PMC clock to 1 MHz, + * - Set LDO_MEM as SRAM supply source during DEEP-SLEEP, + * - Set LDO_CORE Low Power mode as Core supply source during DEEP-SLEEP, + * - Select Core Logic supply source when waking up from DEEP-SLEEP. + */ + reg_data = PMC->CTRL & (~PMC_CTRL_SELCLOCK_MASK) & (~PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK) & + (~PMC_CTRL_SELMEMSUPPLY_MASK); + if (POWER_GetCorePowerSource() == kPOWER_CoreSrcDCDC) + { + /* Core Logic is supplied by DCDC Converter when waking up from DEEP-SLEEP */ + PMC->CTRL = reg_data & (~PMC_CTRL_SELCORESUPPLYWK_MASK); + } + else + { + /* Core Logic is supplied by LDO CORE (configured in High Power mode) when waking up from DEEP-SLEEP */ + PMC->CTRL = reg_data | PMC_CTRL_SELCORESUPPLYWK_MASK; + } + + /* _WFI() */ + POWER_PowerCycleCpu(); + + /* Switch PMC clock to 12 MHz and Configure the PMC in ACTIVE mode */ + PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_SELCLOCK_MASK | + PMC_CTRL_LPMODE(LOWPOWER_CFG_LPMODE_ACTIVE); + + /* Restore BoD Core Trip point. */ + PMC->BODCORE = (PMC->BODCORE & (~PMC_BODCORE_TRIGLVL_MASK)) | PMC_BODCORE_TRIGLVL(bod_core_trglvl); + + // CSSV2 + { + /* Restore i_css_clk/pclk/hclk */ + SYSCON->AHBCLKCTRLSET[2] = syscon_css_clk_pclk_hclk; + + /* Restore DTRNG clocks */ + SYSCON_CSS_CLK_CTRL_SET_REG = syscon_css_clk_ctrl; + +/* Check if CSS is NOT in reset AND is clocked, to avoid deadlock situations */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + if (((SYSCON->PRESETCTRL2 & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (css_ctrl & 0x1)) +#else + if (((SYSCON->PRESETCTRL[2] & 0x40000U) == 0) && syscon_css_clk_pclk_hclk && (css_ctrl & 0x1)) +#endif + { + /* Restore CSS */ + CSSV2_CTRL_REG = css_ctrl; + + /* Wait until CSS is in idle state */ + while (CSSV2_STATUS_REG & 0x1) + ; + } + } + + /* Restore AUTOCLKGATEOVERRIDE register*/ + SYSCON->AUTOCLKGATEOVERRIDE = 0xC0DE0000 | syscon_autoclkgateoverride_reg; + + /* Reset Sleep Postpone configuration */ + SYSCON->HARDWARESLEEP = 0; + + break; + } + + case LOWPOWER_CFG_LPMODE_POWERDOWN: + { + uint32_t lpcac_ctrl_reg; + uint32_t vref_rst_state; + uint32_t vref_clk_state; + uint32_t syscon_ahbclk_reg_0; + uint32_t syscon_css_clk_ctrl, syscon_css_clk_pclk_hclk; + + /* POWER DOWN power mode */ + power_core_pwr_source_t core_supply_source; + + /* Only FRO32K, XTAL32K, FRO1M, COMP, BIAS, LDO_MEM and can VREF stay powered during POWERDOWN */ + PMC->PDSLEEPCFG0 = + p_lowpower_cfg->PDCTRL[0] | + (0xFFFFFFFF & (~(kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_FRO32K | kPDRUNCFG_PD_XTAL32K | kPDRUNCFG_PD_COMP | + kPDRUNCFG_PD_BIAS | kPDRUNCFG_PD_LDOMEM | kPDRUNCFG_PD_VREF))); + PMC->PDSLEEPCFG1 = p_lowpower_cfg->PDCTRL[1]; + + /* Make sure DEEP POWER DOWN reset is disabled */ + PMC->RESETCTRL = PMC->RESETCTRL & (~PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK); + +/* Enable VREF Module (reset & clock) */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + vref_rst_state = (SYSCON->PRESETCTRL3) & SYSCON_PRESETCTRL3_VREF_RST_MASK; + vref_clk_state = (SYSCON->AHBCLKCTRL3) & SYSCON_AHBCLKCTRL3_VREF_MASK; + SYSCON->PRESETCTRLCLR[3] = SYSCON_PRESETCTRL3_VREF_RST_MASK; + SYSCON->AHBCLKCTRLSET[3] = SYSCON_AHBCLKCTRL3_VREF_MASK; +#else + vref_rst_state = (*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_5))) & 0x40000UL; + vref_clk_state = (*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_9))) & 0x40000UL; + *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_7)) = 0x40000UL; + *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_10)) = 0x40000UL; +#endif + + /* Save VREF Module User Configuration ... */ + vref_regs[0] = VREF->CSR; + vref_regs[1] = VREF->UTRIM; + /* Save VREF Module Factory Trimmings ... */ + VREF->TEST_UNLOCK = 0x5AA5UL << 1; /* TEST_UNLOCK. Required before writting TRIM0 & TRIM1 */ + vref_regs[2] = VREF->TRIM0; + vref_regs[3] = VREF->TRIM1; + + /* ... then enable VREF Module isolation */ + PMC->MISCCTRL = PMC->MISCCTRL | PMC_MISCCTRL_VREF_ISO_MASK; + + // CSSV2 + { + syscon_css_clk_ctrl = SYSCON_CSS_CLK_CTRL_REG & (1U << 1); +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL2 & (1U << 18); +#else + syscon_css_clk_pclk_hclk = SYSCON->AHBCLKCTRL[2] & (1U << 18); +#endif + + /* Switch off DTRNG clocks */ + SYSCON_CSS_CLK_CTRL_CLR_REG = (1U << 1); + + /* Swicth off i_css_clk/pclk/hclk */ + SYSCON->AHBCLKCTRLCLR[2] = (1U << 18); + } + + /* CPU0 Retention */ + SYSCON->FUNCRETENTIONCTRL = + (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | p_lowpower_cfg->CPURETCTRL; + + /* Disable all IRQs */ + __disable_irq(); + + /* + * From here : + * 1 - If an interrupt that is enable occurs, the _WFI instruction will not be executed and we won't enter + * in POWER DOWN. 2 - If an interrupt that is not enable occurs, there is no consequence neither on the + * execution of the low power mode nor on the behaviour of the CPU. + */ + + /* Switch PMC clock to 1 MHz and select LDO CORE (configured in High Power mode) as Core Logic supply source + * when waking up from POWER-DOWN */ + PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_SELCLOCK_MASK)) | PMC_CTRL_SELCORESUPPLYWK_MASK; + + /* Save user Core Supply Source configuration */ + core_supply_source = POWER_GetCorePowerSource(); + + /* Store Analog Controller Registers */ + analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; + analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; + analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; + analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; + analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; + analog_ctrl_regs[5] = ANACTRL->LDO_XO32M; + analog_ctrl_regs[6] = ANACTRL->OSC_TESTBUS; + + /* Save Flash Cache settings, then disable and clear it */ + lpcac_ctrl_reg = SYSCON->LPCAC_CTRL; + SYSCON->LPCAC_CTRL = 0x3; /* dis_lpcac = '1', clr_lpcac = '1' */ + +/* Save ROM clock setting, then enable it. + * It is important to have the ROM clock running before entering + * POWER-DOWN for the following two reasons: + * 1 - In case of POWER-DOWN with CPU state retention (which is the only + * option currently offered to the user), some flip-flops that depend + on this clock need to be saved. + * 2 - In case of POWER-DOWN without CPU state retention (which is a + * hardware feature that is NOT offered to the user for the time being) + * CPU reboot cannot occur if ROM clock has been shut down. + */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + syscon_ahbclk_reg_0 = SYSCON->AHBCLKCTRL0; + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_ROM_MASK; /* Enable the clock for ROM */ +#else + syscon_ahbclk_reg_0 = SYSCON->AHBCLKCTRL[0]; + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_ROM_MASK; /* Enable the clock for ROM */ +#endif + + /* _WFI() */ + POWER_PowerCycleCpu(); + +/* Restore ROM clock setting */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + SYSCON->AHBCLKCTRL0 = syscon_ahbclk_reg_0; +#else + SYSCON->AHBCLKCTRL[0] = syscon_ahbclk_reg_0; +#endif + /* Restore Flash Cache settings */ + SYSCON->LPCAC_CTRL = lpcac_ctrl_reg; + + /* Switch PMC clock to 12 MHz and Configure the PMC in ACTIVE mode */ + PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_SELCLOCK_MASK | + PMC_CTRL_LPMODE(LOWPOWER_CFG_LPMODE_ACTIVE); + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + { + /* Restore i_css_clk/pclk/hclk */ + SYSCON->AHBCLKCTRLSET[2] = syscon_css_clk_pclk_hclk; + + /* Restore DTRNG clocks */ + SYSCON_CSS_CLK_CTRL_SET_REG = syscon_css_clk_ctrl; + } +#endif + + /* Restore Analog Controller Registers */ + ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; + ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; + ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; + ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; + ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; + ANACTRL->LDO_XO32M = analog_ctrl_regs[5]; + ANACTRL->OSC_TESTBUS = analog_ctrl_regs[6]; + + /* Restore VREF Module Factory Trimmings ... */ + VREF->TEST_UNLOCK = 0x5AA5UL << 1; /* TEST_UNLOCK. Required before writting TRIM0 & TRIM1 */ + VREF->TRIM0 = vref_regs[2]; + VREF->TRIM1 = vref_regs[3]; + /* ... then restore VREF Module User Configuration */ + VREF->CSR = vref_regs[0]; + VREF->UTRIM = vref_regs[1]; + +/* Restore VREF module reset and clock state */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + SYSCON->PRESETCTRL3 = (SYSCON->PRESETCTRL3 & (~SYSCON_PRESETCTRL3_VREF_RST_MASK)) | vref_rst_state; + SYSCON->AHBCLKCTRL3 = (SYSCON->AHBCLKCTRL3 & (~SYSCON_AHBCLKCTRL3_VREF_MASK)) | vref_clk_state; +#else + *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_5)) = + ((*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_5))) & (~0x40000UL)) | vref_rst_state; + *(uint32_t *)(((uint32_t *)SYSCON->RESERVED_9)) = + ((*(uint32_t *)(((uint32_t *)SYSCON->RESERVED_9))) & (~0x40000UL)) | vref_clk_state; +#endif + + /* Disable VREF Module isolation ... */ + PMC->MISCCTRL = PMC->MISCCTRL & (~PMC_MISCCTRL_VREF_ISO_MASK); + + /* After wake up from Power-down, the Core supply source is LDO CORE */ + /* So restore the user configuration if necessary */ + if (core_supply_source == kPOWER_CoreSrcDCDC) + { + /* Restore DCDC Converter as Core Logic supply source */ + /* NOTE: PMC must be set in ACTIVE mode first before doing this switching to DCDC */ + (void)POWER_SetCorePowerSource(kPOWER_CoreSrcDCDC); + } + + break; + } + + case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: + { + /* DEEP-POWER-DOWN power mode */ + + /* Configure wake-up by I/O : + * - Set up wake-up IO pad control source : PMC WAKEUPIOCTRL (WAKEUPIO_ENABLE = 1) + * - Reset Wake-up I/O Edge Detectors & Cause (WAKEUPIO_RSTN = 0) + */ + PMC->WAKEUPIOCTRL = p_lowpower_cfg->WAKEUPIOSRC | PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK; + + /* Release Wake up I/O reset (WAKEUPIO_RSTN = 1)*/ + PMC->WAKEUPIOCTRL |= PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK; + + /* Only FRO1M, FRO32K, XTAL32K and LDOMEM can stay powered during DEEP POWER-DOWN */ + PMC->PDSLEEPCFG0 = + p_lowpower_cfg->PDCTRL[0] | (0xFFFFFFFF & (~(kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_FRO32K | + kPDRUNCFG_PD_XTAL32K | kPDRUNCFG_PD_LDOMEM))); + PMC->PDSLEEPCFG1 = p_lowpower_cfg->PDCTRL[1]; + + /* Disable all IRQs */ + __disable_irq(); + + /* + * From here : + * 1 - If an interrupt that is enabled occurs, the _WFI instruction will not be executed and we won't enter + * in POWER DOWN. 2 - If an interrupt that is not enabled occurs, there is no consequence neither on the + * execution of the low power mode nor on the behaviour of the CPU. + */ + + /* clear all Reset causes */ + PMC->RESETCAUSE = 0xFFFFFFFF; + + /* Enable DEEP POWER-DOWN reset */ + PMC->RESETCTRL |= PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK; + + /* Switch PMC clock to 1 MHz */ + PMC->CTRL = PMC->CTRL & (~PMC_CTRL_SELCLOCK_MASK); + + /* _WFI() */ + POWER_PowerCycleCpu(); + + /*** We should never reach this point, unless the Low Power cycle has been cancelled somehow. ***/ + /* Switch PMC clock to 12 MHz and Configure the PMC in ACTIVE mode */ + PMC->CTRL = (PMC->CTRL & (~PMC_CTRL_LPMODE_MASK)) | PMC_CTRL_SELCLOCK_MASK | + PMC_CTRL_LPMODE(LOWPOWER_CFG_LPMODE_ACTIVE); + + break; + } + + default: + { + /* Error */ + } + } // End switch( low_power_mode ) + + /* Restore FMC Configuration */ + SYSCON->FMCCR = SYSCON->FMCCR | (fmccr_reg & SYSCON_FMCCR_PREFEN_MASK); + + /* + * Restore the configuration of the Priority Mask Register. + * Rational : if the interrupts were enable before entering the Low power mode, they will be re-enabled, + * if they were disabled, they will stay disabled. + */ + __set_PRIMASK(primask); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + for (i = 0; i < 4; i++) + { + NVIC->ISER[i] = cpu0_int_enable[i]; + } +} + +/** + * @brief Configures and enters in low power mode + * @param : p_lowpower_cfg + * @return Nothing + */ +static uint32_t POWER_WakeUpIOCtrl(uint32_t p_wakeup_io_ctrl) +{ + uint32_t wake_up_type; + uint32_t wakeup_io_ctrl_reg = 0; + +// Enable IOCON +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + SYSCON->PRESETCTRLCLR[0] = SYSCON_PRESETCTRL0_IOCON_RST_MASK; + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK; +#else + SYSCON->PRESETCTRLCLR[0] = SYSCON_PRESETCTRL_IOCON_RST_MASK; + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_IOCON_MASK; +#endif + + /* Configure Pull up & Pull down based on the required wake-up edge */ + + /* Wake-up I/O 0 */ + wake_up_type = + (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK)) >> + LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO0_INDEX); + if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) + { + /* Rising edge and both rising and falling edges */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_0_PORT][WAKEUPIO_0_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + } + else + { + if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) + { + /* Falling edge only */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_0_PORT][WAKEUPIO_0_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + } + else + { + /* Wake-up I/O is disabled : set pull-up/pull-down as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + } + } + } + + /* Wake-up I/O 1 */ + wake_up_type = + (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK)) >> + LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO1_INDEX); + if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) + { + /* Rising edge and both rising and falling edges */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_1_PORT][WAKEUPIO_1_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + } + else + { + if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) + { + /* Falling edge only */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_1_PORT][WAKEUPIO_1_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + } + } + } + + /* Wake-up I/O 2 */ + wake_up_type = + (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK)) >> + LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO2_INDEX); + if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) + { + /* Rising edge and both rising and falling edges */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_2_PORT][WAKEUPIO_2_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + } + else + { + if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) + { + /* Falling edge only */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_2_PORT][WAKEUPIO_2_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + } + } + } + + /* Wake-up I/O 3 */ + wake_up_type = + (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK)) >> + LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO3_INDEX); + if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) + { + /* Rising edge and both rising and falling edges */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_3_PORT][WAKEUPIO_3_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + } + else + { + if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) + { + /* Falling edge only */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_3_PORT][WAKEUPIO_3_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + } + } + } + + /* Wake-up I/O 4 */ + wake_up_type = + (p_wakeup_io_ctrl & (PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK | PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK)) >> + LOWPOWER_WAKEUPIOSRC_PIO4_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO4_INDEX); + if ((wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING) || (wake_up_type == LOWPOWER_WAKEUPIOSRC_RISING_FALLING)) + { + /* Rising edge and both rising and falling edges */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_4_PORT][WAKEUPIO_4_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); + } + } + else + { + if (wake_up_type == LOWPOWER_WAKEUPIOSRC_FALLING) + { + /* Falling edge only */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK) == 0) + { + /* Internal pull up / pull down are not disabled by the user, so use them */ + IOCON->PIO[WAKEUPIO_4_PORT][WAKEUPIO_4_PINS] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); + } + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK) != 0) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + (LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX); + } + } + } + } + + return (wakeup_io_ctrl_reg); +} + +static uint32_t POWER_SetLdoAoLdoMemVoltage(uint32_t p_lp_mode) +{ + uint32_t voltage = 0; + uint32_t ldo_ao_trim = 0; + uint32_t ldo_mem_trim = 0; + uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; + uint32_t lv_v_ldo_mem, lv_v_ldo_mem_boost; + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + ldo_ao_trim = FLASH_NMPA_LDO_AO; + ldo_mem_trim = FLASH_NMPA_LDO_MEM; +#endif + + switch (p_lp_mode) + { + case LOWPOWER_CFG_LPMODE_DEEPSLEEP: + { + if ((ldo_ao_trim & 0x80000000) != 0) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim >> 8) & 0x1F; + lv_v_ldo_pmu_boost = (ldo_ao_trim >> 13) & 0x1F; + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = V_AO_0P900; + lv_v_ldo_pmu_boost = V_AO_0P850; + } + } + break; + + case LOWPOWER_CFG_LPMODE_POWERDOWN: + { + if ((ldo_ao_trim & 0x80000000) != 0) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim >> 18) & 0x1F; + lv_v_ldo_pmu_boost = (ldo_ao_trim >> 23) & 0x1F; + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = V_AO_0P800; + lv_v_ldo_pmu_boost = V_AO_0P750; + } + } + break; + + case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: + { + if ((ldo_ao_trim & 0x80000000) != 0) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim >> 18) & 0x1F; + lv_v_ldo_pmu_boost = (ldo_ao_trim >> 23) & 0x1F; + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = V_AO_0P800; + lv_v_ldo_pmu_boost = V_AO_0P750; + } + } + break; + + default: + /* We should never reach this point */ + lv_v_ldo_pmu = V_AO_1P100; + lv_v_ldo_pmu_boost = V_AO_1P050; + } + + if ((ldo_mem_trim & 0x80000000) != 0) + { + /* Apply settings coming from Flash */ + lv_v_ldo_mem = ldo_mem_trim & 0x1F; + lv_v_ldo_mem_boost = (ldo_mem_trim >> 8) & 0x1F; + } + else + { + /* Apply default settings */ + lv_v_ldo_mem = V_AO_0P750; /* Set to 0.75V (voltage Scaling) */ + lv_v_ldo_mem_boost = V_AO_0P700; /* Set to 0.7V (voltage Scaling) */ + } + + /* The Memories Voltage settings below are for voltage scaling */ + voltage = (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | + (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | + (lv_v_ldo_mem << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | + (lv_v_ldo_mem_boost << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX); + + return (voltage); +} + +/** + * @brief Configures System Power Profile + * @param power_profile : Low/Medium/High + * @return Nothing + */ +static void POWER_SetSystemPowerProfile(v_system_power_profile_t power_profile) +{ + uint32_t dcdcTrimValue0 = 0; + uint32_t dcdcTrimValue1 = 0; + + switch (power_profile) + { + case V_SYSTEM_POWER_PROFILE_MEDIUM: + /* Medium */ + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + dcdcTrimValue0 = FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY0; + dcdcTrimValue1 = FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY1; +#endif + + if (dcdcTrimValue0 & 0x1) + { + /* DCDC Trimmings in Flash are valid */ + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; + } + else + { + /* DCDC Trimmings in Flash are not valid. + * Set a default value */ + PMC->DCDC0 = 0x0220ACF1 >> 1; + PMC->DCDC1 = 0x01D05C78; + } + + break; + + case V_SYSTEM_POWER_PROFILE_HIGH: +/* High */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + dcdcTrimValue0 = FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY0; + dcdcTrimValue1 = FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY1; +#endif + + if (dcdcTrimValue0 & 0x1) + { + /* DCDC Trimmings in Flash are valid */ + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; + } + else + { + /* DCDC Trimmings in Flash are not valid. + * Set a default value */ + PMC->DCDC0 = 0x0228ACF9 >> 1; + PMC->DCDC1 = 0x01E05C68; + } + + break; + + default: +/* Low */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + dcdcTrimValue0 = FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY0; + dcdcTrimValue1 = FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY1; +#endif + + if (dcdcTrimValue0 & 0x1) + { + /* DCDC Trimmings in Flash are valid */ + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; + } + else + { + /* DCDC Trimmings in Flash are not valid. + * Set a default value */ + PMC->DCDC0 = 0x0210CCFD >> 1; + PMC->DCDC1 = 0x01C05C98; + } + } +} + +/** + * @brief Configures System Power Profile + * @param power_profile : Low/Medium/High + * @return Nothing + */ +static void POWER_SetVoltageForProcess(v_system_power_profile_t power_profile) +{ + /* Get Sample Process Corner */ + lowpower_process_corner_enum part_process_corner = POWER_GetPartProcessCorner(); + + switch (part_process_corner) + { + case PROCESS_CORNER_SSS: + /* Slow Corner */ + { + switch (power_profile) + { + case V_SYSTEM_POWER_PROFILE_MEDIUM: + /* Medium */ + POWER_SetSystemVoltage(VOLTAGE_SSS_MED_MV); + break; + + case V_SYSTEM_POWER_PROFILE_HIGH: + /* High */ + POWER_SetSystemVoltage(VOLTAGE_SSS_HIG_MV); + break; + + default: + /* V_SYSTEM_POWER_PROFILE_LOW */ + POWER_SetSystemVoltage(VOLTAGE_SSS_LOW_MV); + } // switch(power_profile) + } + break; + + case PROCESS_CORNER_FFF: + /* Fast Corner */ + { + switch (power_profile) + { + case V_SYSTEM_POWER_PROFILE_MEDIUM: + /* Medium */ + POWER_SetSystemVoltage(VOLTAGE_FFF_MED_MV); + break; + + case V_SYSTEM_POWER_PROFILE_HIGH: + /* High */ + POWER_SetSystemVoltage(VOLTAGE_FFF_HIG_MV); + break; + + default: + /* V_SYSTEM_POWER_PROFILE_LOW */ + POWER_SetSystemVoltage(VOLTAGE_FFF_LOW_MV); + } // switch(power_profile) + } + break; + + default: + /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ + { + switch (power_profile) + { + case V_SYSTEM_POWER_PROFILE_MEDIUM: + /* Medium */ + POWER_SetSystemVoltage(VOLTAGE_NNN_MED_MV); + break; + + case V_SYSTEM_POWER_PROFILE_HIGH: + /* High */ + POWER_SetSystemVoltage(VOLTAGE_NNN_HIG_MV); + break; + + default: + /* V_SYSTEM_POWER_PROFILE_LOW */ + POWER_SetSystemVoltage(VOLTAGE_NNN_LOW_MV); + } // switch(power_profile) + } + } // switch(part_process_corner) +} + +/** + * @brief + * @param + * @return + */ +static lowpower_process_corner_enum POWER_GetPartProcessCorner(void) +{ + lowpower_process_corner_enum part_process_corner; + uint32_t pvt_ringo_hz; + uint32_t pvt_ringo_0 = 0; + uint32_t pvt_ringo_1 = 0; + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + pvt_ringo_0 = FLASH_NMPA_PVT_MONITOR_0_RINGO; + pvt_ringo_1 = FLASH_NMPA_PVT_MONITOR_1_RINGO; +#endif + + /* + * Check that the PVT Monitors Trimmings in flash are valid. + * Note : On Customer Samples, PVT Trimmings in flash will ALWAYS be valid, + * so that in the SDK, the check below could be skipped (but NOT the right shift operation) + */ + if (pvt_ringo_0 & 0x1) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_0 = pvt_ringo_0 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_0 = PROCESS_NNN_AVG_HZ; + } + + if (pvt_ringo_1 & 0x1) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_1 = pvt_ringo_1 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_1 = PROCESS_NNN_AVG_HZ; + } + + /* + * There are 2 Ring Oscillators in the System. + * We consider the worst case scenario by choosing + * the minimum of the 2 Ring Oscillators values + * as the final value to determine the Process Corner. + */ + if (pvt_ringo_1 <= pvt_ringo_0) + { + pvt_ringo_hz = pvt_ringo_1; + } + else + { + pvt_ringo_hz = pvt_ringo_0; + } + + /* + * Determine the process corner based on the value of the Ring Oscillator frequency + */ + if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) + { + /* SSS Process Corner */ + part_process_corner = PROCESS_CORNER_SSS; + } + else + { + if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) + { + /* NNN Process Corner */ + part_process_corner = PROCESS_CORNER_NNN; + } + else + { + /* FFF Process Corner */ + part_process_corner = PROCESS_CORNER_FFF; + } + } + + return (part_process_corner); +} + +/** + * @brief + * @param + * @return + */ +static void POWER_SetSystemVoltage(uint32_t system_voltage_mv) +{ + /* + * Set system voltage + */ + uint32_t lv_ldo_ao = V_AO_1P100; /* */ + uint32_t lv_ldo_ao_boost = V_AO_1P150; /* */ + uint32_t lv_dcdc = V_DCDC_1P100; /* */ + uint32_t lv_ldo_core = V_LDOCORE_HP_1P102; /* */ + + /* + * Because DCDC has less code than LD_AO, we first determine the + * optimum DCDC settings, then we find the closest possible settings + * for LDO_AO, knowing that we want both settings to be as close as possible + * (ideally, they shall be equal). + */ + + if (system_voltage_mv <= 950) + { + lv_dcdc = V_DCDC_0P950; + lv_ldo_ao = V_AO_0P960; + lv_ldo_ao_boost = V_AO_1P010; + lv_ldo_core = V_LDOCORE_HP_0P953; + } + else if (system_voltage_mv <= 975) + { + lv_dcdc = V_DCDC_0P975; + lv_ldo_ao = V_AO_0P980; + lv_ldo_ao_boost = V_AO_1P030; + lv_ldo_core = V_LDOCORE_HP_0P980; + } + else if (system_voltage_mv <= 1000) + { + lv_dcdc = V_DCDC_1P000; + lv_ldo_ao = V_AO_1P000; + lv_ldo_ao_boost = V_AO_1P050; + lv_ldo_core = V_LDOCORE_HP_1P001; + } + else if (system_voltage_mv <= 1025) + { + lv_dcdc = V_DCDC_1P025; + lv_ldo_ao = V_AO_1P030; + lv_ldo_ao_boost = V_AO_1P080; + lv_ldo_core = V_LDOCORE_HP_1P027; + } + else if (system_voltage_mv <= 1050) + { + lv_dcdc = V_DCDC_1P050; + lv_ldo_ao = V_AO_1P060; + lv_ldo_ao_boost = V_AO_1P110; + lv_ldo_core = V_LDOCORE_HP_1P055; + } + else if (system_voltage_mv <= 1075) + { + lv_dcdc = V_DCDC_1P075; + lv_ldo_ao = V_AO_1P080; + lv_ldo_ao_boost = V_AO_1P130; + lv_ldo_core = V_LDOCORE_HP_1P075; + } + else if (system_voltage_mv <= 1100) + { + lv_dcdc = V_DCDC_1P100; + lv_ldo_ao = V_AO_1P100; + lv_ldo_ao_boost = V_AO_1P150; + lv_ldo_core = V_LDOCORE_HP_1P102; + } + else if (system_voltage_mv <= 1125) + { + lv_dcdc = V_DCDC_1P125; + lv_ldo_ao = V_AO_1P130; + lv_ldo_ao_boost = V_AO_1P160; + lv_ldo_core = V_LDOCORE_HP_1P027; + } + else if (system_voltage_mv <= 1150) + { + lv_dcdc = V_DCDC_1P150; + lv_ldo_ao = V_AO_1P160; + lv_ldo_ao_boost = V_AO_1P220; + lv_ldo_core = V_LDOCORE_HP_1P156; + } + else if (system_voltage_mv <= 1175) + { + lv_dcdc = V_DCDC_1P175; + lv_ldo_ao = V_AO_1P160; + lv_ldo_ao_boost = V_AO_1P220; + lv_ldo_core = V_LDOCORE_HP_1P177; + } + else + { + lv_dcdc = V_DCDC_1P200; + lv_ldo_ao = V_AO_1P220; + lv_ldo_ao_boost = V_AO_1P220; + lv_ldo_core = V_LDOCORE_HP_1P204; + } + +/* Set up LDO Always-On voltages */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + /* Apply LDO_AO Trimmings */ + { + int8_t ldo_ao_offset; + int32_t lv_ldo_ao_signed; + + ldo_ao_offset = + (int8_t)((FLASH_NMPA_LDO_AO & FLASH_NMPA_LDO_AO_VADJ_ACTIVE_MASK) >> FLASH_NMPA_LDO_AO_VADJ_ACTIVE_SHIFT); + lv_ldo_ao_signed = (int32_t)((int32_t)lv_ldo_ao + (int32_t)ldo_ao_offset); + + if (lv_ldo_ao_signed < (int32_t)V_AO_0P960) + { + lv_ldo_ao = V_AO_0P960; + } + else + { + if (lv_ldo_ao_signed > (int32_t)V_AO_1P220) + { + lv_ldo_ao = V_AO_1P220; + } + else + { + lv_ldo_ao = (uint32_t)lv_ldo_ao_signed; + } + } + } +// Note: In ACTIVE mode, the LDO BOOST mode is always enabled. +// Therefore, the value of the "lv_ldo_ao_boost" does not really matter. +// For that reason, we do not recompuete it here. +#endif + PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | + PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); + + /* Set up DCDC voltage */ + PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); + +/* Set up LDO_CORE voltage */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + /* Apply LDO_CORE Trimmings */ + { + int8_t ldo_core_regref_offset; + int32_t lv_ldo_core_signed; + + ldo_core_regref_offset = (int8_t)((FLASH_NMPA_BOD_LDOCORE & FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_MASK) >> + FLASH_NMPA_BOD_LDOCORE_REGREF_1P8V_OFFSET_SHIFT); + lv_ldo_core_signed = (int32_t)((int32_t)lv_ldo_core + (int32_t)ldo_core_regref_offset); + + if (lv_ldo_core_signed < (int32_t)V_LDOCORE_HP_1P204) + { + lv_ldo_core = V_LDOCORE_HP_1P204; + } + else + { + if (lv_ldo_core_signed > (int32_t)V_LDOCORE_HP_0P953) + { + lv_ldo_core = V_LDOCORE_HP_0P953; + } + else + { + lv_ldo_core = (uint32_t)lv_ldo_core_signed; + } + } + } +#endif + PMC->LDOCORE0 = (PMC->LDOCORE0 & (~PMC_LDOCORE0_REGREFTRIM_MASK)) | PMC_LDOCORE0_REGREFTRIM(lv_ldo_core); +} + +/** + * brief + * return + */ +static void POWER_SRAMSetRegister(power_sram_index_t sram_index, uint32_t power_mode) +{ + switch (sram_index) + { + case kPOWER_SRAM_IDX_RAM_X0: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_00: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_00_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_00_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_01: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_01_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_01_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_02: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_02_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_02_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_03: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_03_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_03_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_10: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_10_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_10_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_20: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_20_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_20_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_30: + { + PMC->SRAMCTRL0 = (PMC->SRAMCTRL0 & (~(0xFUL << PMC_SRAMCTRL0_RAM_30_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL0_RAM_30_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_40: + { + PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_40_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL1_RAM_40_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_41: + { + PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_41_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL1_RAM_41_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_42: + { + PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_42_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL1_RAM_42_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_RAM_43: + { + PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_43_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL1_RAM_43_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_FLASHCACHE: + { + PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT); + break; + } + + case kPOWER_SRAM_IDX_FLEXSPICACHE: + { + PMC->SRAMCTRL1 = (PMC->SRAMCTRL1 & (~(0xFUL << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT))) | + (power_mode << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT); + break; + } + + default: + // Error + ; + } +} + +/** + * brief + * return + */ +static void POWER_SRAMActiveToLightSleep(power_sram_index_t sram_index) +{ + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_LS_CODE); +} + +/** + * brief + * return + */ +static void POWER_SRAMActiveToDeepSleep(power_sram_index_t sram_index) +{ + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_DS_CODE); +} + +/** + * brief + * return + */ +static void POWER_SRAMActiveToShutDown(power_sram_index_t sram_index) +{ + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_SD_CODE); +} + +/** + * brief + * return + */ +static void POWER_SRAMLightSleepToActive(power_sram_index_t sram_index) +{ + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_MPU_CODE); + // Wait at least 944.90 ns (worst case, from gf40rfnv_nxp_ehlvsram_008192x032bw4c04_mh_pt_m7) + POWER_SRAMPowerUpDelay(); // wait about 1 us + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_ACT_CODE); +} + +/** + * brief + * return + */ +static void POWER_SRAMDeepSleepToActive(power_sram_index_t sram_index) +{ + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_FPU_CODE); + // Wait at least 707.30 ns (worst case, from gf40rfnv_nxp_ehlvsram_008192x032bw4c04_mh_pt_m7) + POWER_SRAMPowerUpDelay(); // wait about 1 us + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_ACT_CODE); +} + +/** + * brief + * return + */ +static void POWER_SRAMShutDownToActive(power_sram_index_t sram_index) +{ + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_FPU_CODE); + // Wait at least 382.80 ns (worst case, from gf40rfnv_nxp_ehlvsram_008192x032bw4c04_mh_pt_m7) + POWER_SRAMPowerUpDelay(); // wait about 1 us + POWER_SRAMSetRegister(sram_index, SRAM_PWR_MODE_ACT_CODE); +} + +/** + * brief + * return + */ +static void POWER_SetSystemClock12MHZ(void) +{ + if ((SYSCON->MAINCLKSELA != 0) || (SYSCON->MAINCLKSELB != 0) || + ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) != 0)) + { + /* The System is NOT running at 12 MHz: so switch the system on 12 MHz clock */ + /* IMPORTANT NOTE : The assumption here is that before calling any Low Power API + * the system will be running at a frequency higher or equal to 12 MHz. + */ + uint32_t flash_int_enable_reg; + uint32_t num_wait_states = 1; /* Default to the maximum number of wait states */ + + /* Switch main clock to FRO12MHz ( the order of the 5 settings below is critical) */ + SYSCON->MAINCLKSELA = SYSCON_MAINCLKSELA_SEL(0); /* Main clock A source select : FRO 12 MHz clock */ + SYSCON->MAINCLKSELB = SYSCON_MAINCLKSELB_SEL(0); /* Main clock B source select : Main Clock A */ + SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); /* Main clock divided by 1 */ + +/* Adjust FMC waiting time cycles (num_wait_states) and disable PREFETCH + * NOTE : PREFETCH disable MUST BE DONE BEFORE the flash command below. + */ +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + SYSCON->FMCCR = (SYSCON->FMCCR & (~SYSCON_FMCCR_FLASHTIM_MASK) & (~SYSCON_FMCCR_PREFEN_MASK)) | + SYSCON_FMCCR_FLASHTIM(num_wait_states); + /* Adjust Flash Controller waiting time */ + flash_int_enable_reg = FLASH->INTEN; /* Save INT_ENABLE register. */ + FLASH->INTEN_CLR = 0x1F; /* Disable all interrupt */ + FLASH->INTSTAT_CLR = 0x1F; /* Clear all status flags */ +#else + SYSCON->FMCCR = (SYSCON->FMCCR & (~SYSCON_FMCCR_FMCTIM_MASK) & (~SYSCON_FMCCR_PREFEN_MASK)) | + SYSCON_FMCCR_FMCTIM(num_wait_states); + /* Adjust Flash Controller waiting time */ + flash_int_enable_reg = FLASH->INT_ENABLE; /* Save INT_ENABLE register. */ + FLASH->INT_CLR_ENABLE = 0x1F; /* Disable all interrupt */ + FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ +#endif + + FLASH->DATAW[0] = num_wait_states; + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + /* Wait until the cmd is completed (without error) */ + while (!(FLASH->INTSTAT & FLASH_INTSTAT_DONE_MASK)) + ; + FLASH->INTSTAT_CLR = 0x1F; /* Clear all status flags, then ... */ + FLASH->INTEN_SET = flash_int_enable_reg; /* ... restore INT_ENABLE register. */ +#else + /* Wait until the cmd is completed (without error) */ + while (!(FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) + ; + FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags, then ... */ + FLASH->INT_SET_ENABLE = flash_int_enable_reg; /* ... restore INT_ENABLE register. */ +#endif + + POWER_SetSystemPowerProfile( + V_SYSTEM_POWER_PROFILE_LOW); /* Align DCDC/LDO_CORE Power profile with the 12 MHz frequency */ + } + else + { + /* The System is already running at 12 MHz: so disable FMC PREFETCH feature only */ + SYSCON->FMCCR = SYSCON->FMCCR & (~SYSCON_FMCCR_PREFEN_MASK); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.h new file mode 100644 index 0000000000000000000000000000000000000000..bba93821bb750be69edefabd1003c71d777b4fd9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_power.h @@ -0,0 +1,751 @@ +/* + * Copyright 2020, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include +#include "fsl_common.h" +#include "fsl_device_registers.h" + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 1.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/** + * @brief Low Power Modes configuration + */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; + +/** + * @brief Device Reset Causes + */ +typedef enum _power_reset_cause +{ + kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ + kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ + kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ + kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ + kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ + kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ + kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ + /* Reset causes in DEEP-POWER-DOWN low power mode */ + kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 5 wake-up pins */ + kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Clock (RTC) */ + kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = + 10UL, /*!< Any of the 5 wake-up pins and RTC (the 2 events occured within 1 nano-second of each other) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = + 11UL, /*!< Any of the 5 wake-up pins and OSTIMER (the 2 events occured within 1 nano-second of each other) */ + kRESET_CAUSE_DPDRESET_RTC_OSTIMER = + 12UL, /*!< Real Time Clock or OS Event Timer (the 2 events occured within 1 nano-second of each other) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 5 wake-up pins or RTC or OS Event Timer (the 3 + events occured within 1 nano-second of each other) */ + /* Miscallenous */ + kRESET_CAUSE_NOT_RELEVANT = + 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ + kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an + application point of view. */ +} power_reset_cause_t; + +/** + * @brief Device Boot Modes + */ +typedef enum _power_boot_mode +{ + kBOOT_MODE_POWER_UP = + 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ + kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ + kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ + kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ +} power_boot_mode_t; + +/** + * @brief Device wake up pins events + */ +typedef enum _power_wakeup_pin_t +{ + kWAKEUP_PIN_NONE = 0UL, /*!< No wake up pin event */ + kWAKEUP_PIN_0 = (1UL << 0), /*!< Wake up pin 0 event */ + kWAKEUP_PIN_1 = (1UL << 1), /*!< Wake up pin 1 event */ + kWAKEUP_PIN_2 = (1UL << 2), /*!< Wake up pin 2 event */ + kWAKEUP_PIN_3 = (1UL << 3), /*!< Wake up pin 3 event */ + kWAKEUP_PIN_4 = (1UL << 4), /*!< Wake up pin 4 event */ + kWAKEUP_PIN_MULTIPLE = 0x1FUL, /*!< More than 1 wake up pins events occured (within 1 nano-second of each other) */ +} power_wakeup_pin_t; + +/** + * @brief analog components power modes control during low power modes + */ +typedef enum _power_pd_bit +{ + /* Power Down Vector 0 */ + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVDDMAIN = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTALHF = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USBFSPHY = (1UL << 11), + // kPDRUNCFG_PD_ = (1UL << 12), /*!< RESERVED */ + kPDRUNCFG_PD_COMP = (1UL << 13), + // kPDRUNCFG_PD_ = (1UL << 14), /*!< RESERVED */ + // kPDRUNCFG_PD_ = (1UL << 15), /*!< RESERVED */ + kPDRUNCFG_PD_LDOMEM = (1UL << 16), + // kPDRUNCFG_PD_ = (1UL << 17), /*!< RESERVED */ + kPDRUNCFG_PD_LDOEFUSEPROG = (1UL << 18), + // kPDRUNCFG_PD_ = (1UL << 19), /*!< RESERVED */ + kPDRUNCFG_PD_LDOXTALHF = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + // kPDRUNCFG_PD_ = (1UL << 22), /*!< RESERVED */ + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), + kPDRUNCFG_PD_HSCMP0 = (1UL << 25), + kPDRUNCFG_PD_HSCMP1 = (1UL << 26), + kPDRUNCFG_PD_HSCMP2 = (1UL << 27), + kPDRUNCFG_PD_OPAMP0 = (1UL << 28), + kPDRUNCFG_PD_OPAMP1 = (1UL << 29), + kPDRUNCFG_PD_OPAMP2 = (1UL << 30), + kPDRUNCFG_PD_VREF = (1UL << 31), + + /* Power Down Vector 1 */ + kPDRUNCFG_PD_CMPBIAS = (1UL << 0) | (1UL << 31), + kPDRUNCFG_PD_HSCMP0_DAC = (1UL << 1) | (1UL << 31), + kPDRUNCFG_PD_HSCMP1_DAC = (1UL << 2) | (1UL << 31), + kPDRUNCFG_PD_HSCMP2_DAC = (1UL << 3) | (1UL << 31), + kPDRUNCFG_PD_DAC0 = (1UL << 4) | (1UL << 31), + kPDRUNCFG_PD_DAC1 = (1UL << 5) | (1UL << 31), + kPDRUNCFG_PD_DAC2 = (1UL << 6) | (1UL << 31), + kPDRUNCFG_STOP_DAC0 = (1UL << 7) | (1UL << 31), + kPDRUNCFG_STOP_DAC1 = (1UL << 8) | (1UL << 31), + kPDRUNCFG_STOP_DAC2 = (1UL << 9) | (1UL << 31), + + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/** + * @brief SRAM instances bit masks + */ +typedef enum _power_sram_bit +{ + kPOWER_SRAM_RAM_X0 = (1UL << 0), /*!< RAM_X0 */ + kPOWER_SRAM_RAM_00 = (1UL << 1), /*!< RAM_00 */ + kPOWER_SRAM_RAM_01 = (1UL << 2), /*!< RAM_01 */ + kPOWER_SRAM_RAM_02 = (1UL << 3), /*!< RAM_02 */ + kPOWER_SRAM_RAM_03 = (1UL << 4), /*!< RAM_03 */ + kPOWER_SRAM_RAM_10 = (1UL << 5), /*!< RAM_10 */ + kPOWER_SRAM_RAM_20 = (1UL << 6), /*!< RAM_20 */ + kPOWER_SRAM_RAM_30 = (1UL << 7), /*!< RAM_30 */ + kPOWER_SRAM_RAM_40 = (1UL << 8), /*!< RAM_40 */ + kPOWER_SRAM_RAM_41 = (1UL << 9), /*!< RAM_41 */ + kPOWER_SRAM_RAM_42 = (1UL << 10), /*!< RAM_42 */ + kPOWER_SRAM_RAM_43 = (1UL << 11), /*!< RAM_43 */ + kPOWER_SRAM_FLASHCACHE = (1UL << 12), /*!< Reserved. Flash Cache SRAM instance */ + kPOWER_SRAM_FLEXSPICACHE = (1UL << 13), /*!< Reserved. FlexSPI Cache SRAM instance */ + kPOWER_SRAM_FLEXSPIH2PREG = (1UL << 14), /*!< Reserved. FlexSPI Dual Port Register Files instances */ + + kPOWER_SRAM_DSLP_MASK = 0x7FFFUL, /*!< Reserved. DEEP-SLEEP SRAM instances */ + kPOWER_SRAM_PDWN_MASK = 0xFFFUL, /*!< Reserved. POWER-DOWN SRAM instances */ + +#if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES)) + kPOWER_SRAM_DPWD_MASK = 0xFE6UL, /*!< Reserved. DEEP-POWER-DOWN SRAM instances (RAM_X0, RAM_02 and RAM_03 excluded: + they are used by ROM Boot code) */ +#else + kPOWER_SRAM_DPWD_MASK = 0xF3FUL, /*!< Reserved. DEEP-POWER-DOWN SRAM instances (RAM_20 & RAM_30 excluded).*/ +#endif + + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPOWER_SRAM_ForceUnsigned = 0x80000000U, +} power_sram_bit_t; + +/** + * @brief SRAM instances indexes + */ +typedef enum _power_sram_index +{ + kPOWER_SRAM_IDX_RAM_X0 = 0UL, /*!< RAM_X0 */ + kPOWER_SRAM_IDX_RAM_00 = 1UL, /*!< RAM_00 */ + kPOWER_SRAM_IDX_RAM_01 = 2UL, /*!< RAM_01 */ + kPOWER_SRAM_IDX_RAM_02 = 3UL, /*!< RAM_02 */ + kPOWER_SRAM_IDX_RAM_03 = 4UL, /*!< RAM_03 */ + kPOWER_SRAM_IDX_RAM_10 = 5UL, /*!< RAM_10 */ + kPOWER_SRAM_IDX_RAM_20 = 6UL, /*!< RAM_20 */ + kPOWER_SRAM_IDX_RAM_30 = 7UL, /*!< RAM_30 */ + kPOWER_SRAM_IDX_RAM_40 = 8UL, /*!< RAM_40 */ + kPOWER_SRAM_IDX_RAM_41 = 9UL, /*!< RAM_41 */ + kPOWER_SRAM_IDX_RAM_42 = 10UL, /*!< RAM_42 */ + kPOWER_SRAM_IDX_RAM_43 = 11UL, /*!< RAM_43 */ + kPOWER_SRAM_IDX_FLASHCACHE = 12UL, /*!< Reserved. Flash Cache SRAM instance */ + kPOWER_SRAM_IDX_FLEXSPICACHE = 13UL, /*!< Reserved. FlexSPI Cache SRAM instance */ + kPOWER_SRAM_IDX_FLEXSPIH2PREG = 14UL, /*!< Reserved. FlexSPI Dual Port Register Files instances */ +} power_sram_index_t; + +/*@brief SRAM Power Mode */ +typedef enum _power_sram_pwr_mode +{ + kPOWER_SRAMPwrActive = 0U, /*!< Active */ + kPOWER_SRAMPwrLightSleep = 1U, /*!< RESERVED, DO NOT USE (Light Sleep) */ + kPOWER_SRAMPwrDeepSleep = 2U, /*!< Deep Sleep : SRAM content retained */ + kPOWER_SRAMPwrShutDown = 3U, /*!< Shutdown: SRAM content lost */ +} power_sram_pwr_mode_t; + +/*@brief BOD VDDMAIN level */ +typedef enum _power_bod_vddmain_level +{ + kPOWER_BodVddmainLevel1000mv = 0, /*!< VDDMAIN Brown out detector level 1V */ + kPOWER_BodVddmainLevel1100mv = 1, /*!< VDDMAIN Brown out detector level 1.1V */ + kPOWER_BodVddmainLevel1200mv = 2, /*!< VDDMAIN Brown out detector level 1.2V */ + kPOWER_BodVddmainLevel1300mv = 3, /*!< VDDMAIN Brown out detector level 1.3V */ + kPOWER_BodVddmainLevel1400mv = 4, /*!< VDDMAIN Brown out detector level 1.4V */ + kPOWER_BodVddmainLevel1500mv = 5, /*!< VDDMAIN Brown out detector level 1.5V */ + kPOWER_BodVddmainLevel1600mv = 6, /*!< VDDMAIN Brown out detector level 1.6V */ + kPOWER_BodVddmainLevel1650mv = 7, /*!< VDDMAIN Brown out detector level 1.65V */ + kPOWER_BodVddmainLevel1700mv = 8, /*!< VDDMAIN Brown out detector level 1.7V */ + kPOWER_BodVddmainLevel1750mv = 9, /*!< VDDMAIN Brown out detector level 1.75V */ + kPOWER_BodVddmainLevel1800mv = 10, /*!< VDDMAIN Brown out detector level 1.8V */ + kPOWER_BodVddmainLevel1900mv = 11, /*!< VDDMAIN Brown out detector level 1.9V */ + kPOWER_BodVddmainLevel2000mv = 12, /*!< VDDMAIN Brown out detector level 2V */ + kPOWER_BodVddmainLevel2100mv = 13, /*!< VDDMAIN Brown out detector level 2.1V */ + kPOWER_BodVddmainLevel2200mv = 14, /*!< VDDMAIN Brown out detector level 2.2V */ + kPOWER_BodVddmainLevel2300mv = 15, /*!< VDDMAIN Brown out detector level 2.3V */ + kPOWER_BodVddmainLevel2400mv = 16, /*!< VDDMAIN Brown out detector level 2.4V */ + kPOWER_BodVddmainLevel2500mv = 17, /*!< VDDMAIN Brown out detector level 2.5V */ + kPOWER_BodVddmainLevel2600mv = 18, /*!< VDDMAIN Brown out detector level 2.6V */ + kPOWER_BodVddmainLevel2700mv = 19, /*!< VDDMAIN Brown out detector level 2.7V */ + kPOWER_BodVddmainLevel2800mv = 20, /*!< VDDMAIN Brown out detector level 2.80 V */ + kPOWER_BodVddmainLevel2900mv = 21, /*!< VDDMAIN Brown out detector level 2.9V */ + kPOWER_BodVddmainLevel3000mv = 22, /*!< VDDMAIN Brown out detector level 3.0V */ + kPOWER_BodVddmainLevel3100mv = 23, /*!< VDDMAIN Brown out detector level 3.1V */ + kPOWER_BodVddmainLevel3200mv = 24, /*!< VDDMAIN Brown out detector level 3.2V */ + kPOWER_BodVddmainLevel3300mv = 25, /*!< VDDMAIN Brown out detector level 3.3V */ +} power_bod_vddmain_level_t; + +/*@brief BOD core level */ +typedef enum _power_bod_core_level +{ + kPOWER_BodCoreLevel600mv = 0, /*!< core Brown out detector level 600mV */ + kPOWER_BodCoreLevel650mv = 1, /*!< core Brown out detector level 650mV */ + kPOWER_BodCoreLevel700mv = 2, /*!< core Brown out detector level 700mV */ + kPOWER_BodCoreLevel750mv = 3, /*!< core Brown out detector level 750mV */ + kPOWER_BodCoreLevel800mv = 4, /*!< core Brown out detector level 800mV */ + kPOWER_BodCoreLevel850mv = 5, /*!< core Brown out detector level 850mV */ + kPOWER_BodCoreLevel900mv = 6, /*!< core Brown out detector level 900mV */ + kPOWER_BodCoreLevel950mv = 7, /*!< core Brown out detector level 950mV */ +} power_bod_core_level_t; + +/*@brief BODs (VDDMAIN & Core) Hysteresis control */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; + +/*@brief Core Power Source */ +typedef enum _power_core_pwr_source +{ + kPOWER_CoreSrcDCDC = 0U, /*!< DCDC */ + kPOWER_CoreSrcLDOCoreHP = 1U, /*!< LDO Core High Power Mode */ + kPOWER_CoreSrcLDOCoreLP = 2U, /*!< LDO Core Low Power Mode (DO NOT USE : Reserved for test purposes) */ + kPOWER_CoreSrcExternal = 3U, /*!< External (DO NOT USE : Reserved for test purposes) */ +} power_core_pwr_source_t; + +/*@brief Core Regulators Power State */ +typedef enum _power_core_pwr_state +{ + kPOWER_CorePwrDisable = 0U, /*!< Disable */ + kPOWER_CorePwrEnable = 1U, /*!< Enable */ +} power_core_pwr_state_t; + +/*@brief Generic Power Library APIs Status codes */ +typedef enum _power_status +{ + kPOWER_Status_Success = 0U, /*!< OK */ + kPOWER_Status_Fail = 1U, /*!< Generic error code */ +} power_status_t; + +/** + * @brief Low Power Modes Wake up sources + */ +/* Wake up source vector 0 */ +#define WAKEUP_SYS (1UL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1UL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1UL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1UL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1UL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1UL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1UL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1UL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1UL << 8) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_MRT (1UL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1UL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1UL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1UL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1UL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1UL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1UL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1UL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1UL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1UL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1UL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1UL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1UL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC0 (1UL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_ADC1 (1UL << 23) /*!< [SLEEP, ] */ +#define WAKEUP_ACMP (1UL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_DMIC (1UL << 25) /*!< [SLEEP, ] */ +#define WAKEUP_HWVAD (1UL << 26) /*!< [SLEEP, DEEP SLEEP, ] */ +#define WAKEUP_USB0_NEEDCLK (1UL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1UL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_ALARM_WAKEUP (1UL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_EZH_ARCH_B (1UL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_WAKEUP_MAILBOX (1UL << 31) /*!< [SLEEP, DEEP SLEEP, ] */ + +/* Wake up source vector 1 */ +#define WAKEUP_GPIO_INT0_4 (1UL << 0) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1UL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1UL << 2) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1UL << 3) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1UL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1UL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1UL << 6) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_FLEXSPI (1UL << 7) /*!< [SLEEP, ] */ +// reserved (1UL << 8) +// reserved (1UL << 9) +// reserved (1UL << 10) +#define WAKEUP_CAN0_0 (1UL << 11) /*!< [SLEEP, ] */ +#define WAKEUP_CAN0_1 (1UL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_SPIFILTER (1UL << 13) /*!< [SLEEP, ] */ +// reserved (1UL << 14) +// reserved (1UL << 15) +// reserved (1UL << 16) +#define WAKEUP_SEC_HYPERVISOR_CALL (1UL << 17) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1UL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1UL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +// reserved (1UL << 20) +#define WAKEUP_SEC_VIO (1UL << 21) /*!< [SLEEP, ] */ +#define WAKEUP_CSS_IRQ0 (1UL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_PKC (1UL << 23) /*!< [SLEEP, ] */ +#define WAKEUP_PUF (1UL << 24) /*!< [SLEEP, ] */ +#define WAKEUP_PQ (1UL << 25) /*!< [SLEEP, ] */ +#define WAKEUP_SDMA1 (1UL << 26) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1UL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CODE_WDG (1UL << 28) /*!< [SLEEP, ] */ +// reserved (1UL << 29) +#define WAKEUP_I3C (1UL << 30) /*!< [SLEEP, DEEP SLEEP ] */ +// reserved (1UL << 31) + +/* Wake up source vector 2 */ +#define WAKEUP_NEUTRON (1UL << 0) /*!< [SLEEP, ] */ +#define WAKEUP_CSS_IRQ1 (1UL << 1) /*!< [SLEEP, ] */ +// reserved (1UL << 2) +#define WAKEUP_ANA_GLITCH_DETECT (1UL << 3) +// reserved (1UL << 4) +// reserved (1UL << 5) +// reserved (1UL << 6) +// reserved (1UL << 7) +// reserved (1UL << 8) +// reserved (1UL << 9) +#define WAKEUP_DAC0 (1UL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_DAC1 (1UL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_DAC2 (1UL << 12) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_HS_COMP0 (1UL << 13) /*!< [SLEEP, ] */ +#define WAKEUP_HS_COMP1 (1UL << 14) /*!< [SLEEP, ] */ +#define WAKEUP_HS_COMP2 (1UL << 15) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_CAPTURE (1UL << 16) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_FAULT (1UL << 17) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_RELOAD_ERROR (1UL << 18) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_COMPARE0 (1UL << 19) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_RELOAD0 (1UL << 20) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_COMPARE1 (1UL << 21) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_RELOAD1 (1UL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_COMPARE2 (1UL << 23) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_RELOAD2 (1UL << 24) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_COMPARE3 (1UL << 25) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM0_RELOAD3 (1UL << 26) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_CAPTURE (1UL << 27) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_FAULT (1UL << 28) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_RELOAD_ERROR (1UL << 29) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_COMPARE0 (1UL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_RELOAD0 (1UL << 31) /*!< [SLEEP, ] */ + +/* Wake up source vector 3 */ +#define WAKEUP_FLEXPWM1_COMPARE1 (1UL << 0) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_RELOAD1 (1UL << 1) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_COMPARE2 (1UL << 2) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_RELOAD2 (1UL << 3) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_COMPARE3 (1UL << 4) /*!< [SLEEP, ] */ +#define WAKEUP_FLEXPWM1_RELOAD3 (1UL << 5) /*!< [SLEEP, ] */ +#define WAKEUP_ENC0_COMPARE (1UL << 6) /*!< [SLEEP, ] */ +#define WAKEUP_ENC0_HOME (1UL << 7) /*!< [SLEEP, ] */ +#define WAKEUP_ENC0_WDG (1UL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_ENC0_IDX (1UL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_ENC1_COMPARE (1UL << 10) /*!< [SLEEP, ] */ +#define WAKEUP_ENC1_HOME (1UL << 11) /*!< [SLEEP, ] */ +#define WAKEUP_ENC1_WDG (1UL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_ENC1_IDX (1UL << 13) /*!< [SLEEP, ] */ +#define WAKEUP_ITRC (1UL << 14) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_CF_DSP24L_IRQ0 (1UL << 15) /*!< [SLEEP, ] */ +#define WAKEUP_CF_DSP24L_IRQ1 (1UL << 16) /*!< [SLEEP, ] */ +#define WAKEUP_FTM0 (1UL << 17) /*!< [SLEEP, ] */ +// reserved (1UL << 18) +// reserved (1UL << 19) +// reserved (1UL << 20) +// reserved (1UL << 21) +// reserved (1UL << 22) +// reserved (1UL << 23) +// reserved (1UL << 24) +// reserved (1UL << 25) +// reserved (1UL << 26) +// reserved (1UL << 27) +// reserved (1UL << 28) +// reserved (1UL << 29) +// reserved (1UL << 30) +// reserved (1UL << 31) + +/** + * @brief Sleep Postpone (DEEP-SLEEP) + */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS \ + (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ + peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_DMIC \ + (1UL << 2) /*!< Wake for DMIC. DMIC being busy will cause peripheral clocking to remain running until DMIC \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA0 \ + (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS or LOWPOWER_HWWAKE_DAC */ +#define LOWPOWER_HWWAKE_SDMA1 \ + (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS or LOWPOWER_HWWAKE_DAC */ +#define LOWPOWER_HWWAKE_DAC \ + (1UL << 6) /*!< Wake for DAC0, DAC1, DAC2. Any DAC0/1/2 FIFO reaching the level specified by the configuration \ + will generate an asynchronous SDMA0 request, and SDMA0 will wake up the bus \ + clock temporarily to transfer data to DAC0/1/2.*/ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ + (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ + LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0, LOWPOWER_HWWAKE_SDMA1 or LOWPOWER_HWWAKE_DAC is \ + set */ + +/** + * @brief CPU State retention (POWER-DOWN) + */ +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ + +/** + * @brief Wake up I/O sources (DEEP POWER-DOWN) + */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ +#define LOWPOWER_WAKEUPIOSRC_PIO4_INDEX 8 /*!< Pin P0(26) */ + +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ + +#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 10 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 12 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 14 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 16 /*!< Pin P1(30) */ +#define LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX 18 /*!< Pin P0(26) */ + +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */ +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */ +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */ +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */ + +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ + 20 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ + 21 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ + 22 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ + 23 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_INDEX \ + 24 /*!< Wake-up I/O 4 pull-up/down disable/enable control index */ + +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 4 pull-up/down disable/enable mask */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 25 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 26 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 27 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 28 /*!< Wake-up I/O 3 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_INDEX 29 /*!< Wake-up I/O 4 pull-up/down configuration index */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_INDEX) /*!< Wake-up I/O 4 pull-up/down mask */ + +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ + +#define LOWPOWER_WAKEUPIO_CFG_SRC_IOCON \ + 0 /*!< Wake-up pins configuration (in/out, pull up/down plain input ...) is coming from IOCON (valid for \ + DEEP-SLEEP and POWER-DOWN) */ +#define LOWPOWER_WAKEUPIO_CFG_SRC_PMC \ + 1 /*!< Wake-up pins configuration (in/out, pull up/down plain input ...) is coming from PMC and set up via \ + the second parameter (wakeup_io_ctrl) of POWER_SetWakeUpPins API (valid for DEEP-SLEEP and POWER-DOWN) */ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + if (((en & (1UL << 31)) != 0UL) && (en != (1UL << 31))) + { + /* PDRUNCFGSET1 */ + PMC->PDRUNCFGSET1 = (uint32_t)(en & ~(1UL << 31)); + } + else + { + /* PDRUNCFGSET0 */ + PMC->PDRUNCFGSET0 = (uint32_t)en; + } +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + if (((en & (1UL << 31)) != 0UL) && (en != (1UL << 31))) + { + /* PDRUNCFGCLR1 */ + PMC->PDRUNCFGCLR1 = (uint32_t)(en & ~(1UL << 31)); + } + else + { + /* PDRUNCFGCLR0 */ + PMC->PDRUNCFGCLR0 = (uint32_t)en; + } +} + +/** + * @brief SoC Power Management Controller initialization + * @return power_status_t + */ +power_status_t POWER_PowerInit(void); + +/** + * @brief Selects the core logic supply source + * @param pwr_source : Defines which regulator will be used to power the part core logic (internally) + * @return power_status_t + */ +power_status_t POWER_SetCorePowerSource(power_core_pwr_source_t pwr_source); + +/** + * @brief Returns the current core logic supply source. + * @return power_core_pwr_source_t + */ +power_core_pwr_source_t POWER_GetCorePowerSource(void); + +/** + * @brief Allows to control the state (enabled or disabled) of the core logic internal regulators (DCDC, LDO_CORE) + * @param pwr_source : Defines which regulator will be enabled or disabled + * @param pwr_state : Defines the state of the internal regulator indicated by pwr_source + * @return power_status_t + */ +power_status_t POWER_CorePowerSourceControl(power_core_pwr_source_t pwr_source, power_core_pwr_state_t pwr_state); + +/** + * @brief Allows to configure SRAM instances (low) power modes when the part is in ACTIVE mode. + * @param sram_inst : Defines the SRAM instance(s) to be configured. + * @param pwr_mode : Defines the SRAM low power mode to be applied to all SRAM instances given by sram_inst + * @return power_status_t + */ +power_status_t POWER_SRAMPowerModeControl(power_sram_bit_t sram_inst, power_sram_pwr_mode_t pwr_mode); + +/** + * @brief + * @param p_sram_index : + * @return power_sram_pwr_mode_t + */ +power_sram_pwr_mode_t POWER_GetSRAMPowerMode(power_sram_index_t sram_index); + +/** + * @brief Configures and enters in SLEEP low power mode + * @return Nothing + */ +void POWER_EnterSleep(void); + +/** + * @brief Configures and enters in DEEP-SLEEP low power mode + * @param exclude_from_pd: defines which analog peripherals shall NOT be powered down (it is a 2 x 32-bit vectors, + aligned with "pd_bit_t" definition) + * @param sram_retention_ctrl:defines which SRAM instances will be put in "retention" mode during deep-sleep (aligned + with "power_sram_bit_t" definition) + * @param wakeup_interrupts: defines which peripheral interrupts can be a wake-up source during deep-sleep (it is a 4 + x 32-bit vectors, aligned with "WAKEUP_" #defines) + * @param hardware_wake_ctrl: configure DMA services during deep-sleep without waking up entire device (see + "LOWPOWER_HWWAKE_*" #defines). + + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - CPU & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd[2], + uint32_t sram_retention_ctrl, + uint32_t wakeup_interrupts[4], + uint32_t hardware_wake_ctrl); + +/** + * @brief Configures and enters in POWERDOWN low power mode + * @param exclude_from_pd: defines which analog peripherals shall NOT be powered down (it is a 1 x 32-bit vector, + aligned with "pd_bit_t" definition) + * @param sram_retention_ctrl:defines which SRAM instances will be put in "retention" mode during power-down (aligned + with "power_sram_bit_t" definition) + * @param wakeup_interrupts: defines which peripheral interrupts can be a wake-up source during power-down (it is a 2 + x 32-bit vectors, aligned with "WAKEUP_" #defines) + * @param cpu_retention_addr: Must be: + - Word aligned (address ending by 0x0, 0x4, 0x8 and 0xC). + - Between 0x2000_0000 and 0x2000_09FC (inside RAM_00) or + - Between 0x2000_1000 and 0x2000_19FC (inside RAM_01) or + - Between 0x2000_2000 and 0x2000_29FC (inside RAM_02) or + - Between 0x2000_3000 and 0x2000_39FC (inside RAM_03) + - The CPU state will be stored in SRAM from "cpu_retention_addr" to "cpu_retention_addr + 1540". + Therefore, any data present in this area before calling the function will be lost. + + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - CPU0 & System Clock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 2 - It is the responsability of the user to make sure that SRAM instance containing the application + * software stack and variables WILL BE preserved during low power (via parameter "sram_retention_ctrl") + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd[1], + uint32_t sram_retention_ctrl, + uint32_t wakeup_interrupts[4], + uint32_t cpu_retention_addr); + +/** + * @brief Configures and enters in DEEPPOWERDOWN low power mode + * @param exclude_from_pd: defines which analog peripherals shall NOT be powered down (it is a 1 x 32-bit vector, + aligned with "pd_bit_t" definition) + * @param sram_retention_ctrl: defines which SRAM instances will be put in "retention" mode during deep power-down + (aligned with "power_sram_bit_t" definition) + * @param wakeup_interrupts: defines which peripheral interrupts can be a wake-up source during deep power-down (it is + a 2 x 32-bit vectors, aligned with "WAKEUP_" #defines) + * @param wakeup_io_ctrl: configure the 5 wake-up pins that can wake-up the part from deep power-down mode (see + "LOWPOWER_WAKEUPIOSRC_*" #defines) + + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - CPU0 & System Clock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 2 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd[1], + uint32_t sram_retention_ctrl, + uint32_t wakeup_interrupts[2], + uint32_t wakeup_io_ctrl); + +/** + * @brief Configures the 5 wake-up pins to wake up the part in DEEP-SLEEP and POWER-DOWN low power modes. + * @param wakeup_io_cfg_src : for all wake-up pins : indicates if the config is from IOCON (0) or from PMC (1). + * @param wakeup_io_ctrl: the 5 wake-up pins configurations (see "LOWPOWER_WAKEUPIOSRC_*" #defines) + + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - To be called just before POWER_EnterDeepSleep() or POWER_EnterPowerDown(). + */ +void POWER_SetWakeUpPins(uint32_t wakeup_io_cfg_src, uint32_t wakeup_io_ctrl); + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param reset_cause : the device reset cause, according to the definition of power_reset_cause_t type. + * @param boot_mode : the device boot mode, according to the definition of power_boot_mode_t type. + * @param wakeup_pin_cause: the wake-up pin sources, according to the definition of power_wakeup_pin_t type. + + * @return Nothing + * + */ +void POWER_GetWakeUpCause(power_reset_cause_t *reset_cause, + power_boot_mode_t *boot_mode, + power_wakeup_pin_t *wakeup_pin_cause); + +/** + * @brief Configures the device internal power control settings + * @param system_freq_hz: operating frequency required (in Hertz). + * @return Nothing + * + * prepare on-chip power regulators (DC-DC Converter / Core and Always-on + * Low Drop-Out regulators) to deliver the amount of power needed for the + * requested performance level, as defined by the CPU operating frequency. + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz); + +#ifdef __cplusplus +} +#endif + +#endif /* _FSL_POWER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.c new file mode 100644 index 0000000000000000000000000000000000000000..d5c457a553e79bea0774eff912700a64971c67a8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.c @@ -0,0 +1,929 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_puf_v3.h" +#include "fsl_clock.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.puf_v3" +#endif + +#define kPUF_OperationInProgress (0x0u) +#define kPUF_Enroll (0x1u) +#define kPUF_Start (0x2u) +#define kPUF_Stop (0x5u) +#define kPUF_GetKey (0x6u) +#define kPUF_Unwrap (0x7u) +#define kPUF_WrapGeneratedRandom (0x8u) +#define kPUF_Wrap (0x9u) +#define kPUF_GenerateRandom (0xfu) +#define kPUF_Test (0x1fu) +#define kPUF_Init (0x20u) +#define kPUF_Zeroize (0x2fu) +typedef uint32_t puf_last_operation_t; + +#define PUF_KEY_OPERATION_CONTEXT_TYPE (0x10 << 16) +#define PUF_CONTEXT_GENERIC_KEY_TYPE (0x0u) +#define PUF_CONTEXT_KEY_LEN_MASK (0x1fffu) + +/******************************************************************************* + * Code + ******************************************************************************/ + +static status_t puf_waitForInit(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ + while (0u == base->SR) + { + } + + /* wait if busy */ + while ((base->SR & PUF_SR_BUSY_MASK) != 0u) + { + } + + /* return status */ + if (base->SR & (PUF_SR_OK_MASK | PUF_SR_ERROR_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +static void puf_powerOn(PUF_Type *base, puf_config_t *conf) +{ + /* Power On PUF SRAM */ + base->SRAM_CFG = 0x1u; + while (0u == (PUF_SRAM_STATUS_READY_MASK & base->SRAM_STATUS)) + { + } +} + +static status_t puf_powerCycle(PUF_Type *base, puf_config_t *conf) +{ + /* Power off */ + base->SRAM_CFG = 0x0u; + + /* Reset PUF and reenable power to PUF SRAM */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); + puf_powerOn(base, conf); + + return kStatus_Success; +} + +static status_t puf_makeStatus(PUF_Type *base, puf_last_operation_t operation) +{ + uint32_t result; + status_t status = kStatus_Fail; + + if (((base->ORR & PUF_ORR_LAST_OPERATION_MASK) >> PUF_ORR_LAST_OPERATION_SHIFT) == operation) + { + result = (base->ORR & PUF_ORR_RESULT_CODE_MASK); + if ((result == kPUF_ResultOK) && (0u == (base->SR & PUF_SR_ERROR_MASK))) + { + status = kStatus_Success; + } + else + { + status = MAKE_STATUS(kStatusGroup_PUF, result); + } + } + + return status; +} + +/*! + * brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * @param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf) +{ + /* Default configuration after reset */ + conf->dataEndianness = kPUF_EndianBig; + conf->CKGATING = 0U; +} + +/*! + * brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * @param conf PUF configuration structure + * @return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, puf_config_t *conf) +{ + status_t status = kStatus_Fail; + + /* Enable PUF clock */ + CLOCK_EnableClock(kCLOCK_Puf); + /* Reset PUF */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); + + /* Set configuration from SRAM */ + base->SRAM_CFG |= PUF_SRAM_CFG_CKGATING(conf->CKGATING); + + /* Enable power to PUF SRAM */ + puf_powerOn(base, conf); + + /* Wait for peripheral to become ready */ + status = puf_waitForInit(base); + + /* In case of error or enroll & start not allowed, do power-cycle */ + if ((status != kStatus_Success) || ((PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK) != + (base->AR & (PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK)))) + { + puf_powerCycle(base, conf); + status = puf_waitForInit(base); + } + + if (kStatus_Success == status) + { + /* Set data endianness */ + base->MISC = PUF_MISC_DATA_ENDIANNESS(conf->dataEndianness); + + /* get status */ + status = puf_makeStatus(base, kPUF_Init); + } + + return status; +} + +/*! + * brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + */ +void PUF_Deinit(PUF_Type *base, puf_config_t *conf) +{ + base->SRAM_CFG = 0x0u; + + RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); + CLOCK_DisableClock(kCLOCK_Puf); +} + +/*! + * brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * @param base PUF peripheral base address + * @param[out] activationCode Word aligned address of the resulting activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize, uint8_t *score) +{ + status_t status = kStatus_Fail; + uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code buffer size is at least 996 bytes */ + if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned and valid activationCode */ + if ((0x3u & (uintptr_t)activationCode) || (activationCode == NULL)) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; + + /* check if ENROLL is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_ENROLL_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_ENROLL_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_ENROLL_MASK)) + { + } + + /* read out AC */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + temp32 = base->DOR; + if (activationCodeSize >= sizeof(uint32_t)) + { + *activationCodeAligned = temp32; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + } + } + + /* In case of success fill in score */ + if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) + { + *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Enroll); + + return status; +} + +/*! + * brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * @param base PUF peripheral base address + * @param[in] activationCode Word aligned address of the input activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param score Value of the PUF Score that was obtained during the start operation. + * return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize, uint8_t *score) +{ + status_t status = kStatus_Fail; + const uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code size is at least 996 bytes */ + if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + /* Set activationCodeSize to 996 bytes */ + activationCodeSize = PUF_ACTIVATION_CODE_SIZE; + + /* only work with aligned activationCode */ + if (0x3u & (uintptr_t)activationCode) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; + + /* check if START is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_START_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_START_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_START_MASK)) + { + } + + /* while busy send AC */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + if (activationCodeSize >= sizeof(uint32_t)) + { + temp32 = *activationCodeAligned; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + /* Send AC again */ + else + { + activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; + temp32 = *activationCodeAligned; + activationCodeAligned++; + activationCodeSize = PUF_ACTIVATION_CODE_SIZE - sizeof(uint32_t); + } + base->DIR = temp32; + } + } + + /* In case of success fill in score */ + if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) + { + *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Start); + + return status; +} + +/*! + * brief Stop PUF + * + * The Stop operation removes all key material from PUF flipflops and PUF SRAM, and sets + * PUF to the Stopped state. + * + * @param base PUF peripheral base address + * @return Status of stop operation. + */ +status_t PUF_Stop(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* check if STOP is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_STOP_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_STOP_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_STOP_MASK)) + { + } + + /* wait while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Stop); + + return status; +} + +/*! + * brief PUF Get Key + * + * The Get Key operation derives a key from the intrinsic PUF key and externally provided context. + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keyDest output destination of the derived PUF key + * @param[out] key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the derived key in bytes. + * @return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDest, uint8_t *key, size_t keySize) +{ + uint8_t idx = 0; + uint32_t *keyAligned = NULL; + uint32_t context[4] = {0}; + status_t status = kStatus_Fail; + + /* check if GET KEY is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_GET_KEY_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for key context */ + if (keyCtx == NULL) + { + return kStatus_InvalidArgument; + } + + /* check for valid key destination */ + if (((keyDest == kPUF_KeyDestRegister) && (key == NULL)) || (keyDest == kPUF_KeyDestInvalid)) + { + return kStatus_InvalidArgument; + } + + /* check for valid key size. */ + /* must be 8byte multiple */ + if (keySize & 0x7u) + { + return kStatus_InvalidArgument; + } + /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + else if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned key */ + if (0x3u & (uintptr_t)key) + { + return kStatus_InvalidArgument; + } + + keyAligned = (uint32_t *)(uintptr_t)key; + + /* fill in key context */ + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & PUF_CONTEXT_KEY_LEN_MASK); + context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; + context[2] = keyCtx->userCtx0; + context[3] = keyCtx->userCtx1; + + /* set key destination */ + base->KEY_DEST = keyDest; + + /* begin */ + base->CR = PUF_CR_GET_KEY_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_GET_KEY_MASK)) + { + } + + /* send context and read output data while busy */ + while (0 != (base->SR & PUF_SR_BUSY_MASK)) + { + if ((0 != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) + { + base->DIR = context[idx]; + idx++; + } + + if ((0 != (PUF_SR_DO_REQUEST_MASK & base->SR)) && (kPUF_KeyDestRegister == keyDest)) + { + if (keySize >= sizeof(uint32_t)) + { + *keyAligned = base->DOR; + keyAligned++; + keySize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_GetKey); + + return status; +} + +/*! + * brief PUF Wrap generated random + * + * The Wrap Generated Random operation wraps a random key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keySize Size of the key to be generated in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap generated random operation. + */ +status_t PUF_WrapGeneratedRandom( + PUF_Type *base, puf_key_ctx_t *keyCtx, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) +{ + uint8_t idx = 0; + uint32_t *keyCodeAligned = NULL; + uint32_t context[4] = {0}; + status_t status = kStatus_Fail; + + /* check if WRAP GENERATED RANDOM is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid key context and keyCode buffer */ + if ((keyCtx == NULL) || (keyCode == NULL)) + { + return kStatus_InvalidArgument; + } + + /* check for valid key size. */ + /* must be 8byte multiple */ + if (keySize & 0x7u) + { + return kStatus_InvalidArgument; + } + /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + else if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given keySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned key code */ + if (0x3u & (uintptr_t)keyCode) + { + return kStatus_InvalidArgument; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* fill in key context */ + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & 0x1FFF); + context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; + context[2] = keyCtx->userCtx0; + context[3] = keyCtx->userCtx1; + + /* begin */ + base->CR = PUF_CR_WRAP_GENERATED_RANDOM_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_WRAP_GENERATED_RANDOM_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if ((0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) + { + base->DIR = context[idx]; + idx++; + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = base->DOR; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_WrapGeneratedRandom); + + return status; +} + +/*! + * brief PUF Wrap user key + * + * The Wrap operation wraps a user defined key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct. + * @param userKey Word aligned address of input user key. + * @param userKeySize Size of the key to be wrapped in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap operation. + */ +status_t PUF_Wrap( + PUF_Type *base, puf_key_ctx_t *keyCtx, uint8_t *userKey, size_t userKeySize, uint8_t *keyCode, size_t keyCodeSize) +{ + uint8_t ctxIdx = 0; + uint32_t *userKeyAligned = NULL; + uint32_t *keyCodeAligned = NULL; + uint32_t context[4] = {0}; + status_t status = kStatus_Fail; + + /* check if WRAP is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_WRAP_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid keyCtx and keyCode pointers */ + if ((keyCtx == NULL) || (keyCode == NULL)) + { + return kStatus_InvalidArgument; + } + + /* check for valid userKey size. */ + /* must be 8byte multiple */ + if (userKeySize & 0x7u) + { + return kStatus_InvalidArgument; + } + /* if userKeySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + else if ((userKeySize > 128u) && !((userKeySize == 256u) || (userKeySize == 384u) || (userKeySize == 512u))) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given userKeySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned userKey and key code */ + if ((0x3u & (uintptr_t)userKey) || (0x3u & (uintptr_t)keyCode)) + { + return kStatus_InvalidArgument; + } + + userKeyAligned = (uint32_t *)(uintptr_t)userKey; + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* fill in key context */ + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((userKeySize * 8u) & 0x1FFF); + context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; + context[2] = keyCtx->userCtx0; + context[3] = keyCtx->userCtx1; + + /* begin */ + base->CR = PUF_CR_WRAP_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_WRAP_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + /* send context first */ + if (ctxIdx < 4u) + { + base->DIR = context[ctxIdx]; + ctxIdx++; + } + /* send userKey */ + else + { + base->DIR = *userKeyAligned; + userKeyAligned++; + } + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = base->DOR; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Wrap); + + return status; +} + +/*! + * brief PUF Unwrap user key + * + * The unwrap operation unwraps the key from a previously created Key Code (KC) + * + * @param base PUF peripheral base address + * @param keyDest output destination of the unwraped PUF key + * @param[in] keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the input keycode in bytes. + * @param key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the key to be generated in bytes. + * @return Status of unwrap operation. + */ +status_t PUF_Unwrap( + PUF_Type *base, puf_key_dest_t keyDest, uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) +{ + uint32_t *keyAligned = NULL; + uint32_t *keyCodeAligned = NULL; + status_t status = kStatus_Fail; + + /* check if UNWRAP is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_UNWRAP_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid key destination */ + if (((keyDest == kPUF_KeyDestRegister) && (key == NULL)) || (keyDest == kPUF_KeyDestInvalid)) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned key and key code */ + if ((0x3u & (uintptr_t)key) || (0x3u & (uintptr_t)keyCode)) + { + return kStatus_InvalidArgument; + } + + keyAligned = (uint32_t *)(uintptr_t)key; + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* set key destination */ + base->KEY_DEST = keyDest; + + /* begin */ + base->CR = PUF_CR_UNWRAP_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_UNWRAP_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + base->DIR = *keyCodeAligned; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + if (keySize >= sizeof(uint32_t)) + { + *keyAligned = base->DOR; + keyAligned++; + keySize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Unwrap); + + return status; +} + +/*! + * brief Generate Random + * + * The Generate Random operation outputs the requested amount of random data as specified in a + * provided context. + * + * @param base PUF peripheral base address + * @param size Size of random data to be genarated in bytes. + * @return Status of generate random operation. + */ +status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size) +{ + uint32_t context; + uint32_t *dataAligned = NULL; + status_t status = kStatus_Fail; + + if (data == NULL) + { + return kStatus_InvalidArgument; + } + + /* check if Generate random is allowed */ + if (0u == (base->AR & PUF_AR_ALLOW_GENERATE_RANDOM_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid size. */ + /* must be 8byte multiple */ + if (size & 0x7u) + { + return kStatus_InvalidArgument; + } + /* if size > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + else if ((size > 128u) && !((size == 256u) || (size == 384u) || (size == 512u))) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned data buffer */ + if (0x3u & (uintptr_t)data) + { + return kStatus_InvalidArgument; + } + + /* Configure context */ + context = ((size * 8u) & 0x1FFFu); + + dataAligned = (uint32_t *)(uintptr_t)data; + + /* begin */ + base->CR = PUF_CR_GENERATE_RANDOM_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_GENERATE_RANDOM_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + base->DIR = context; + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + *dataAligned = base->DOR; + dataAligned++; + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_GenerateRandom); + + return status; +} + +/*! + * brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to zeroized state. + * + * @param base PUF peripheral base address + * @return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* zeroize command is always allowed */ + base->CR = PUF_CR_ZEROIZE_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_ZEROIZE_MASK)) + { + } + + /* wait while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + } + + /* check status */ + if (((PUF_SR_ZEROIZED_MASK | PUF_SR_OK_MASK) == base->SR) && (0u == base->AR)) + { + status = puf_makeStatus(base, kPUF_Zeroize); + } + + return status; +} + +/*! + * brief Test PUF + * + * With the Test PUF operation, diagnostics about the PUF quality is collected and presented in a PUF + * score. + * + * @param base PUF peripheral base address + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of the test operation. + */ +status_t PUF_Test(PUF_Type *base, uint8_t *score) +{ + status_t status = kStatus_Fail; + + /* check if TEST is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_TEST_PUF_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_TEST_PUF_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_TEST_PUF_MASK)) + { + } + + /* wait while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + } + + /* In case of success fill in score */ + if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) + { + *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); + } + + /* Check status */ + status = puf_makeStatus(base, kPUF_Test); + + return status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.h new file mode 100644 index 0000000000000000000000000000000000000000..f360447f47b0ac53a3749edd92cf789d3da30bbf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_puf_v3.h @@ -0,0 +1,286 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PUF_V3_H_ +#define _PUF_V3_H_ + +#include +#include + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @addtogroup puf_v3_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief PUFv3 driver version. Version 2.0.0. + * + * Current version: 2.0.0 + * + * Change log: + * - 2.0.0 + * - Initial version. + */ +#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define kPUF_EndianLittle (0x0u) +#define kPUF_EndianBig (0x1u) +typedef uint32_t puf_endianness_t; + +#define kPUF_KeyDestRegister (0x1u) +#define kPUF_KeyDestKeyBus (0x2u) +#define kPUF_KeyDestInvalid (0x3u) +typedef uint32_t puf_key_dest_t; + +#define kPUF_KeyAllowRegister (0x1u) +#define kPUF_KeyAllowKeyBus (0x2u) +#define kPUF_KeyAllowAll (0x3u) +typedef uint32_t puf_key_scope_t; + +#define kPUF_ResultOK (0x0u) +#define kPUF_AcNotForThisProductPhase1 (0xf0u) +#define kPUF_AcNotForThisProductPhase2 (0xf1u) +#define kPUF_AcCorruptedPhase1 (0xf2u) +#define kPUF_AcCorruptedPhase2 (0xf3u) +#define kPUF_AcAuthFailedPhase1 (0xf4u) +#define kPUF_AcAuthFailedPhase2 (0xf5u) +#define kPUF_QualityVerificationFail (0xf6u) +#define kPUF_ContextIncorrect (0xf7u) +#define kPUF_DestinationNotAllowed (0xf8u) +#define kPUF_Failure (0xFFu) +typedef uint32_t puf_result_code_t; + +typedef struct +{ + puf_endianness_t dataEndianness; + uint8_t CKGATING; +} puf_config_t; + +typedef struct +{ + puf_key_scope_t keyScopeStarted; + puf_key_scope_t keyScopeEnrolled; + uint32_t userCtx0; + uint32_t userCtx1; +} puf_key_ctx_t; + +#define PUF_ACTIVATION_CODE_SIZE 996 +#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((0x34u + x) + 0x10u * (x / 0x32u)) + +enum _puf_status +{ + kStatus_PUF_OperationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 0xA5), + kStatus_PUF_AcNotForThisProductPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase1), + kStatus_PUF_AcNotForThisProductPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase2), + kStatus_PUF_AcCorruptedPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcCorruptedPhase1), + kStatus_PUF_AcCorruptedPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcCorruptedPhase2), + kStatus_PUF_AcAuthFailedPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcAuthFailedPhase1), + kStatus_PUF_NBOOT_AcAuthFailedPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcAuthFailedPhase2), + kStatus_PUF_QualityVerificationFail = MAKE_STATUS(kStatusGroup_PUF, kPUF_QualityVerificationFail), + kStatus_PUF_ContextIncorrect = MAKE_STATUS(kStatusGroup_PUF, kPUF_ContextIncorrect), + kStatus_PUF_DestinationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, kPUF_DestinationNotAllowed), + kStatus_PUF_Failure = MAKE_STATUS(kStatusGroup_PUF, kPUF_Failure), +}; + +/******************************************************************************* + * API + *******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * @param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf); + +/*! + * brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * @param conf PUF configuration structure + * @return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, puf_config_t *conf); + +/*! + * brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + */ +void PUF_Deinit(PUF_Type *base, puf_config_t *conf); + +/*! + * brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * @param base PUF peripheral base address + * @param[out] activationCode Word aligned address of the resulting activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize, uint8_t *score); + +/*! + * brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * @param base PUF peripheral base address + * @param[in] activationCode Word aligned address of the input activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param score Value of the PUF Score that was obtained during the start operation. + * return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize, uint8_t *score); + +/*! + * brief Stop PUF + * + * The Stop operation removes all key material from PUF flipflops and PUF SRAM, and sets + * PUF to the Stopped state. + * + * @param base PUF peripheral base address + * @return Status of stop operation. + */ +status_t PUF_Stop(PUF_Type *base); + +/*! + * brief PUF Get Key + * + * The Get Key operation derives a key from the intrinsic PUF key and externally provided context. + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keyDest output destination of the derived PUF key + * @param[out] key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the derived key in bytes. + * @return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDest, uint8_t *key, size_t keySize); + +/*! + * brief PUF Wrap generated random + * + * The Wrap Generated Random operation wraps a random key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keySize Size of the key to be generated in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap generated random operation. + */ +status_t PUF_WrapGeneratedRandom( + PUF_Type *base, puf_key_ctx_t *keyCtx, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); + +/*! + * brief PUF Wrap user key + * + * The Wrap operation wraps a user defined key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct. + * @param userKey Word aligned address of input user key. + * @param userKeySize Size of the key to be wrapped in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap operation. + */ +status_t PUF_Wrap( + PUF_Type *base, puf_key_ctx_t *keyCtx, uint8_t *userKey, size_t userKeySize, uint8_t *keyCode, size_t keyCodeSize); + +/*! + * brief PUF Unwrap user key + * + * The unwrap operation unwraps the key from a previously created Key Code (KC) + * + * @param base PUF peripheral base address + * @param keyDest output destination of the unwraped PUF key + * @param[in] keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the input keycode in bytes. + * @param key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the key to be generated in bytes. + * @return Status of unwrap operation. + */ +status_t PUF_Unwrap( + PUF_Type *base, puf_key_dest_t keyDest, uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); + +/*! + * brief Generate Random + * + * The Generate Random operation outputs the requested amount of random data as specified in a + * provided context. + * + * @param base PUF peripheral base address + * @param size Size of random data to be genarated in bytes. + * @return Status of generate random operation. + */ +status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size); + +/*! + * brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to zeroized state. + * + * @param base PUF peripheral base address + * @return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base); + +/*! + * brief Test PUF + * + * With the Test PUF operation, diagnostics about the PUF quality is collected and presented in a PUF + * score. + * + * @param base PUF peripheral base address + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of the test operation. + */ +status_t PUF_Test(PUF_Type *base, uint8_t *score); + +/*! + * @brief Blocks specified PUF commands + * + * This function blocks PUF commands specified by mask parameter. + * + * @param base PUF peripheral base address + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of the test operation. + */ +static inline void PUF_BlockCommand(PUF_Type *base, uint32_t mask) +{ + base->CONFIG |= mask; +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _PUF_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..d16fe3a1391b3e911e4f821c5961f95b74aca920 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.c @@ -0,0 +1,935 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pwm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pwm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t PWM_GetInstance(PWM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PWM clocks for each PWM submodule. */ +static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Complement the variable of type uint16_t as needed + * + * This function can complement the variable of type uint16_t as needed.For example, + * need to ask for the opposite of a positive integer. + * + * param value Parameters of type uint16_t + */ +static inline uint16_t PWM_GetComplementU16(uint16_t value) +{ + return (~value + 1U); +} + +static inline uint16_t dutyCycleToReloadValue(uint8_t dutyCyclePercent) +{ + /* Rounding calculations to improve the accuracy of reloadValue */ + return ((65535U * dutyCyclePercent) + 50U) / 100U; +} + +static uint32_t PWM_GetInstance(PWM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pwmBases)); + + return instance; +} + +/*! + * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the PWM driver. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param config Pointer to user's PWM config structure. + * + * return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) +{ + assert(config); + + uint16_t reg; + + /* Source clock for submodule 0 cannot be itself */ + if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + + /* Reload source select clock for submodule 0 cannot be master reload */ + if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PWM submodule clock*/ + CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Clear the fault status flags */ + base->FSTS |= PWM_FSTS_FFLAG_MASK; + + reg = base->SM[subModule].CTRL2; + + /* Setup the submodule clock-source, control source of the INIT signal, + * source of the force output signal, operation in debug & wait modes and reload source select + */ + reg &= ~(uint16_t)(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | + PWM_CTRL2_INDEP_MASK | PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); + reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | + PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | + PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); + + /* Setup PWM A & B to be independent or a complementary-pair */ + switch (config->pairOperation) + { + case kPWM_Independent: + reg |= PWM_CTRL2_INDEP_MASK; + break; + case kPWM_ComplementaryPwmA: + base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); + break; + case kPWM_ComplementaryPwmB: + base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } + base->SM[subModule].CTRL2 = reg; + + reg = base->SM[subModule].CTRL; + + /* Setup the clock prescale, load mode and frequency */ + reg &= ~(uint16_t)(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); + reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); + + /* Setup register reload logic */ + switch (config->reloadLogic) + { + case kPWM_ReloadImmediate: + reg |= PWM_CTRL_LDMOD_MASK; + break; + case kPWM_ReloadPwmHalfCycle: + reg |= PWM_CTRL_HALF_MASK; + reg &= (uint16_t)(~PWM_CTRL_FULL_MASK); + break; + case kPWM_ReloadPwmFullCycle: + reg &= (uint16_t)(~PWM_CTRL_HALF_MASK); + reg |= PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmHalfAndFullCycle: + reg |= PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + default: + assert(false); + break; + } + base->SM[subModule].CTRL = reg; + + /* Issue a Force trigger event when configured to trigger locally */ + if (config->forceTrigger == kPWM_Force_Local) + { + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); + } + + return kStatus_Success; +} + +/*! + * brief Gate the PWM submodule clock + * + * param base PWM peripheral base address + * param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) +{ + /* Stop the submodule */ + base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM submodule clock*/ + CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fill in the PWM config struct with the default settings + * + * The default values are: + * code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * endcode + * param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* PWM is paused in debug mode */ + config->enableDebugMode = false; + /* PWM is paused in wait mode */ + config->enableWait = false; + /* PWM module uses the local reload signal to reload registers */ + config->reloadSelect = kPWM_LocalReload; + /* Use the IP Bus clock as source clock for the PWM submodule */ + config->clockSource = kPWM_BusClock; + /* Clock source prescale is set to divide by 1*/ + config->prescale = kPWM_Prescale_Divide_1; + /* Local sync causes initialization */ + config->initializationControl = kPWM_Initialize_LocalSync; + /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + config->forceTrigger = kPWM_Force_Local; + /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. + * This field is not used in Immediate reload mode + */ + config->reloadFrequency = kPWM_LoadEveryOportunity; + /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ + config->reloadLogic = kPWM_ReloadImmediate; + /* PWM A & PWM B operate as 2 independent channels */ + config->pairOperation = kPWM_Independent; +} + +/*! + * brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param chnlParams Array of PWM channel parameters to configure the channel(s) + * param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM main counter clock in Hz. + * + * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(pwmFreq_Hz); + assert(numOfChnls); + assert(srcClock_Hz); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint16_t modulo = 0; + uint8_t i, polarityShift = 0, outputEnableShift = 0; + + if (numOfChnls > 2U) + { + /* Each submodule has 2 signals; PWM A & PWM B */ + return kStatus_Fail; + } + + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); + + /* Setup each PWM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U; + + /* Setup the different match registers to generate the PWM signal */ + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + if (i == 0U) + { + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + } + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL3 = (pwmHighPulse / 2U); + } + else + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL5 = (pwmHighPulse / 2U); + } + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + if (i == 0U) + { + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + } + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); + } + else + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); + } + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + if (i == 0U) + { + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + } + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + if (i == 0U) + { + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + } + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + break; + default: + assert(false); + break; + } + /* Setup register shift values based on the channel being configured. + * Also setup the deadtime value + */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + polarityShift = PWM_OCTRL_POLA_SHIFT; + outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; + base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); + } + else + { + polarityShift = PWM_OCTRL_POLB_SHIFT; + outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; + base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); + } + + /* Set PWM output fault status */ + switch (chnlParams->pwmChannel) + { + case kPWM_PwmA: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMAFS_MASK); + break; + case kPWM_PwmB: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMBFS_MASK); + break; + case kPWM_PwmX: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMXFS_MASK); + break; + default: + assert(false); + break; + } + + /* Setup signal active level */ + if ((bool)chnlParams->level == kPWM_HighTrue) + { + base->SM[subModule].OCTRL &= ~((uint16_t)1U << (uint16_t)polarityShift); + } + else + { + base->SM[subModule].OCTRL |= ((uint16_t)1U << (uint16_t)polarityShift); + } + /* Enable PWM output */ + base->OUTEN |= ((uint16_t)1U << ((uint16_t)outputEnableShift + (uint16_t)subModule)); + + /* Get the next channel parameters */ + chnlParams++; + } + + return kStatus_Success; +} + +/*! + * brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent) +{ + assert(dutyCyclePercent <= 100U); + assert((uint16_t)pwmSignal < 2U); + uint16_t reloadValue = dutyCycleToReloadValue(dutyCyclePercent); + + PWM_UpdatePwmDutycycleHighAccuracy(base, subModule, pwmSignal, currPwmMode, reloadValue); +} + +/*! + * brief Updates the PWM signal's dutycycle with 16-bit accuracy. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycleHighAccuracy( + PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle) +{ + assert((uint16_t)pwmSignal < 2U); + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint16_t modulo = 0; + + switch (currPwmMode) + { + case kPWM_SignedCenterAligned: + modulo = base->SM[subModule].VAL1 + 1U; + pulseCnt = modulo * 2U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL3 = (pwmHighPulse / 2U); + } + else + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL5 = (pwmHighPulse / 2U); + } + break; + case kPWM_CenterAligned: + pulseCnt = base->SM[subModule].VAL1 + 1U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); + } + else + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); + } + break; + case kPWM_SignedEdgeAligned: + modulo = base->SM[subModule].VAL1 + 1U; + pulseCnt = modulo * 2U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + break; + case kPWM_EdgeAligned: + pulseCnt = base->SM[subModule].VAL1 + 1U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + break; + default: + assert(false); + break; + } +} + +/*! + * brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel in the submodule to setup + * param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams) +{ + uint16_t reg = 0; + switch (pwmChannel) + { + case kPWM_PwmA: + /* Setup the capture paramters for PWM A pin */ + reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | + PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLA_ARMA_MASK; + + base->SM[subModule].CAPTCTRLA = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); + /* Setup PWM A pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmB: + /* Setup the capture paramters for PWM B pin */ + reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | + PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLB_ARMB_MASK; + + base->SM[subModule].CAPTCTRLB = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); + /* Setup PWM B pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmX: + reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | + PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLX_ARMX_MASK; + + base->SM[subModule].CAPTCTRLX = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); + /* Setup PWM X pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Sets up the PWM fault input filter. + * + * @param base PWM peripheral base address + * @param faultInputFilterParams Parameters passed in to set up the fault input filter. + */ +void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams) +{ + assert(NULL != faultInputFilterParams); + + /* When changing values for fault period from a non-zero value, first write a value of 0 to clear the filter. */ + if (0U != (base->FFILT & PWM_FFILT_FILT_PER_MASK)) + { + base->FFILT &= ~(uint16_t)(PWM_FFILT_FILT_PER_MASK); + } + + base->FFILT = (uint16_t)(PWM_FFILT_FILT_PER(faultInputFilterParams->faultFilterPeriod) | + PWM_FFILT_FILT_CNT(faultInputFilterParams->faultFilterCount) | + PWM_FFILT_GSTR(faultInputFilterParams->faultGlitchStretch ? 1U : 0U)); +} + +/*! + * brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * param base PWM peripheral base address + * param faultNum PWM fault to configure. + * param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) +{ + assert(faultParams); + uint16_t reg; + + reg = base->FCTRL; + /* Set the faults level-settting */ + if (faultParams->faultLevel) + { + reg |= ((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); + } + else + { + reg &= ~((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); + } + /* Set the fault clearing mode */ + if ((uint16_t)faultParams->faultClearingMode != 0U) + { + /* Use manual fault clearing */ + reg &= ~((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); + if (faultParams->faultClearingMode == kPWM_ManualSafety) + { + /* Use manual fault clearing with safety mode enabled */ + reg |= ((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); + } + else + { + /* Use manual fault clearing with safety mode disabled */ + reg &= ~((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); + } + } + else + { + /* Use automatic fault clearing */ + reg |= ((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); + } + base->FCTRL = reg; + + /* Set the combinational path option */ + if (faultParams->enableCombinationalPath) + { + /* Combinational path from the fault input to the PWM output is available */ + base->FCTRL2 &= ~((uint16_t)1U << (uint16_t)faultNum); + } + else + { + /* No combinational path available, only fault filter & latch signal can disable PWM output */ + base->FCTRL2 |= ((uint16_t)1U << (uint16_t)faultNum); + } + + /* Initially clear both recovery modes */ + reg = base->FSTS; + reg &= ~(((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)) | + ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum))); + /* Setup fault recovery */ + switch (faultParams->recoverMode) + { + case kPWM_NoRecovery: + break; + case kPWM_RecoverHalfCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); + break; + case kPWM_RecoverFullCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); + break; + case kPWM_RecoverHalfAndFullCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); + reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); + break; + default: + assert(false); + break; + } + base->FSTS = reg; +} + +/*! + * brief Fill in the PWM fault config struct with the default settings + * + * The default values are: + * code + * config->faultClearingMode = kPWM_Automatic; + * config->faultLevel = false; + * config->enableCombinationalPath = true; + * config->recoverMode = kPWM_NoRecovery; + * endcode + * param config Pointer to user's PWM fault config structure. + */ +void PWM_FaultDefaultConfig(pwm_fault_param_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* PWM uses automatic fault clear mode */ + config->faultClearingMode = kPWM_Automatic; + /* PWM fault level is set to logic 0 */ + config->faultLevel = false; + /* Combinational Path from fault input is enabled */ + config->enableCombinationalPath = true; + /* PWM output will stay inactive when recovering from a fault */ + config->recoverMode = kPWM_NoRecovery; +} + +/*! + * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel to configure + * param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) + +{ + uint16_t shift; + uint16_t reg; + + /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ + shift = ((uint16_t)subModule * 4U) + ((uint16_t)pwmChannel * 2U); + + /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ + reg = base->DTSRCSEL; + reg &= ~((uint16_t)0x3U << shift); + reg |= (uint16_t)((uint16_t)mode << shift); + base->DTSRCSEL = reg; +} + +/*! + * brief Enables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + /* Upper 16 bits are for related to the submodule */ + base->SM[subModule].INTEN |= ((uint16_t)mask & 0xFFFFU); + /* Fault related interrupts */ + base->FCTRL |= ((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Disables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + base->SM[subModule].INTEN &= ~((uint16_t)mask & 0xFFFFU); + base->FCTRL &= ~((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Gets the enabled PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t enabledInterrupts; + + enabledInterrupts = base->SM[subModule].INTEN; + enabledInterrupts |= (((uint32_t)base->FCTRL & PWM_FCTRL_FIE_MASK) << 16UL); + return enabledInterrupts; +} + +/*! + * brief Gets the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t statusFlags; + + statusFlags = base->SM[subModule].STS; + statusFlags |= (((uint32_t)base->FSTS & PWM_FSTS_FFLAG_MASK) << 16UL); + + return statusFlags; +} + +/*! + * brief Clears the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + uint16_t reg; + + base->SM[subModule].STS = ((uint16_t)mask & 0xFFFFU); + reg = base->FSTS; + /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared + * by writing a login one + */ + reg &= ~(uint16_t)(PWM_FSTS_FFLAG_MASK); + reg |= (uint16_t)((mask >> 16U) & PWM_FSTS_FFLAG_MASK); + base->FSTS = reg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..081abf1521c08b9d9894c7e9da6a32c7d4b3cfaa --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_pwm.h @@ -0,0 +1,987 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PWM_H_ +#define _FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ +/*@}*/ + +/*! Number of bits per submodule for software output control */ +#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 + +/*! @brief List of PWM submodules */ +typedef enum _pwm_submodule +{ + kPWM_Module_0 = 0U, /*!< Submodule 0 */ + kPWM_Module_1, /*!< Submodule 1 */ + kPWM_Module_2, /*!< Submodule 2 */ + kPWM_Module_3 /*!< Submodule 3 */ +} pwm_submodule_t; + +/*! @brief List of PWM channels in each module */ +typedef enum _pwm_channels +{ + kPWM_PwmB = 0U, + kPWM_PwmA, + kPWM_PwmX +} pwm_channels_t; + +/*! @brief List of PWM value registers */ +typedef enum _pwm_value_register +{ + kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ + kPWM_ValueRegister_1, /*!< PWM Value1 register */ + kPWM_ValueRegister_2, /*!< PWM Value2 register */ + kPWM_ValueRegister_3, /*!< PWM Value3 register */ + kPWM_ValueRegister_4, /*!< PWM Value4 register */ + kPWM_ValueRegister_5 /*!< PWM Value5 register */ +} pwm_value_register_t; + +/*! @brief List of PWM value registers mask */ +enum _pwm_value_register_mask +{ + kPWM_ValueRegisterMask_0 = (1U << 0), /*!< PWM Value0 register mask */ + kPWM_ValueRegisterMask_1 = (1U << 1), /*!< PWM Value1 register mask */ + kPWM_ValueRegisterMask_2 = (1U << 2), /*!< PWM Value2 register mask */ + kPWM_ValueRegisterMask_3 = (1U << 3), /*!< PWM Value3 register mask */ + kPWM_ValueRegisterMask_4 = (1U << 4), /*!< PWM Value4 register mask */ + kPWM_ValueRegisterMask_5 = (1U << 5) /*!< PWM Value5 register mask */ +}; + +/*! @brief PWM clock source selection.*/ +typedef enum _pwm_clock_source +{ + kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ + kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ + kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ +} pwm_clock_source_t; + +/*! @brief PWM prescaler factor selection for clock source*/ +typedef enum _pwm_clock_prescale +{ + kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ + kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ + kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ + kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ + kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ + kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ + kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ + kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ +} pwm_clock_prescale_t; + +/*! @brief Options that can trigger a PWM FORCE_OUT */ +typedef enum _pwm_force_output_trigger +{ + kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ + kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to + the state of LDOK */ + kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ + kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ + kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ + kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ + kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ +} pwm_force_output_trigger_t; + +/*! @brief PWM counter initialization options */ +typedef enum _pwm_init_source +{ + kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ + kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ + kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ + kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ +} pwm_init_source_t; + +/*! @brief PWM load frequency selection */ +typedef enum _pwm_load_frequency +{ + kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ + kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ + kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ + kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ + kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ + kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ + kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ + kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ + kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ + kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ + kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ + kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ + kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ + kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ + kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ + kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ +} pwm_load_frequency_t; + +/*! @brief List of PWM fault selections */ +typedef enum _pwm_fault_input +{ + kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ + kPWM_Fault_1, /*!< Fault 1 input pin */ + kPWM_Fault_2, /*!< Fault 2 input pin */ + kPWM_Fault_3 /*!< Fault 3 input pin */ +} pwm_fault_input_t; + +/*! @brief List of PWM fault disable mapping selections */ +typedef enum _pwm_fault_disable +{ + kPWM_FaultDisable_0 = (1U << 0), /*!< Fault 0 disable mapping */ + kPWM_FaultDisable_1 = (1U << 1), /*!< Fault 1 disable mapping */ + kPWM_FaultDisable_2 = (1U << 2), /*!< Fault 2 disable mapping */ + kPWM_FaultDisable_3 = (1U << 3) /*!< Fault 3 disable mapping */ +} pwm_fault_disable_t; + +/*! @brief List of PWM fault channels */ +typedef enum _pwm_fault_channels +{ + kPWM_faultchannel_0 = 0U, + kPWM_faultchannel_1 +} pwm_fault_channels_t; + +/*! @brief PWM capture edge select */ +typedef enum _pwm_input_capture_edge +{ + kPWM_Disable = 0U, /*!< Disabled */ + kPWM_FallingEdge, /*!< Capture on falling edge only */ + kPWM_RisingEdge, /*!< Capture on rising edge only */ + kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ +} pwm_input_capture_edge_t; + +/*! @brief PWM output options when a FORCE_OUT signal is asserted */ +typedef enum _pwm_force_signal +{ + kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ + kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ + kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ + kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ +} pwm_force_signal_t; + +/*! @brief Options available for the PWM A & B pair operation */ +typedef enum _pwm_chnl_pair_operation +{ + kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ + kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ + kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ +} pwm_chnl_pair_operation_t; + +/*! @brief Options available on how to load the buffered-registers with new values */ +typedef enum _pwm_register_reload +{ + kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ + kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ + kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ + kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ +} pwm_register_reload_t; + +/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ +typedef enum _pwm_fault_recovery_mode +{ + kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ + kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ + kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ + kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ +} pwm_fault_recovery_mode_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ + kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ + kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ + kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ + kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ + kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ + kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ + kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ + kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ + kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ + kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ + kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ + kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ + kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ + kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ + kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ + kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ + kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ + kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ + kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ + kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ + kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ + kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ + kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ + kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ + kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ + kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ + kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ + kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ + kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ + kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ + kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ + kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ + kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ + kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ + kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ +} pwm_status_flags_t; + +/*! @brief List of PWM DMA options */ +typedef enum _pwm_dma_enable +{ + kPWM_CaptureX0DMAEnable = (1U << 0), /*!< PWM capture X0 DMA */ + kPWM_CaptureX1DMAEnable = (1U << 1), /*!< PWM capture X1 DMA */ + kPWM_CaptureB0DMAEnable = (1U << 2), /*!< PWM capture B0 DMA */ + kPWM_CaptureB1DMAEnable = (1U << 3), /*!< PWM capture B1 DMA */ + kPWM_CaptureA0DMAEnable = (1U << 4), /*!< PWM capture A0 DMA */ + kPWM_CaptureA1DMAEnable = (1U << 5) /*!< PWM capture A1 DMA */ +} pwm_dma_enable_t; + +/*! @brief List of PWM capture DMA enable source select */ +typedef enum _pwm_dma_source_select +{ + kPWM_DMARequestDisable = 0U, /*!< Read DMA requests disabled */ + kPWM_DMAWatermarksEnable, /*!< Exceeding a FIFO watermark sets the DMA read request */ + kPWM_DMALocalSync, /*!< A local sync (VAL1 matches counter) sets the read DMA request */ + kPWM_DMALocalReload /*!< A local reload (STS[RF] being set) sets the read DMA request */ +} pwm_dma_source_select_t; + +/*! @brief PWM FIFO Watermark AND Control */ +typedef enum _pwm_watermark_control +{ + kPWM_FIFOWatermarksOR = 0U, /*!< Selected FIFO watermarks are OR'ed together */ + kPWM_FIFOWatermarksAND /*!< Selected FIFO watermarks are AND'ed together */ +} pwm_watermark_control_t; + +/*! @brief PWM operation mode */ +typedef enum _pwm_mode +{ + kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ + kPWM_CenterAligned, /*!< Unsigned cente-aligned */ + kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ + kPWM_EdgeAligned /*!< Unsigned edge-aligned */ +} pwm_mode_t; + +/*! @brief PWM output pulse mode, high-true or low-true */ +typedef enum _pwm_level_select +{ + kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ + kPWM_LowTrue /*!< Low level represents "on" or "active" state */ +} pwm_level_select_t; + +/*! @brief PWM output fault status */ +typedef enum _pwm_fault_state +{ + kPWM_PwmFaultState0 = + 0U, /*!< Output is forced to logic 0 state prior to consideration of output polarity control. */ + kPWM_PwmFaultState1, /*!< Output is forced to logic 1 state prior to consideration of output polarity control. */ + kPWM_PwmFaultState2, /*!< Output is tristated. */ + kPWM_PwmFaultState3 /*!< Output is tristated. */ +} pwm_fault_state_t; + +/*! @brief PWM reload source select */ +typedef enum _pwm_reload_source_select +{ + kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ + kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ +} pwm_reload_source_select_t; + +/*! @brief PWM fault clearing options */ +typedef enum _pwm_fault_clear +{ + kPWM_Automatic = 0U, /*!< Automatic fault clearing */ + kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ + kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ +} pwm_fault_clear_t; + +/*! @brief Options for submodule master control operation */ +typedef enum _pwm_module_control +{ + kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ + kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ + kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ + kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ +} pwm_module_control_t; + +/*! @brief Structure for the user to define the PWM signal characteristics */ +typedef struct _pwm_signal_param +{ + pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ + pwm_level_select_t level; /*!< PWM output active level select */ + uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ + pwm_fault_state_t faultState; /*!< PWM output fault status */ +} pwm_signal_param_t; + +/*! + * @brief PWM config structure + * + * This structure holds the configuration settings for the PWM peripheral. To initialize this + * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pwm_config +{ + bool enableDebugMode; /*!< true: PWM continues to run in debug mode; + false: PWM is paused in debug mode */ + bool enableWait; /*!< true: PWM continues to run in WAIT mode; + false: PWM is paused in WAIT mode */ + pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ + pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ + pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ + pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ + pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice + is not immediate reload */ + pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ +} pwm_config_t; + +/*! @brief Structure for the user to configure the fault input filter. */ +typedef struct _pwm_fault_input_filter_param +{ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + bool faultGlitchStretch; /*!< Fault Glitch Stretch Enable: A logic 1 means that input + fault signals will be stretched to at least 2 IPBus clock cycles */ +} pwm_fault_input_filter_param_t; + +/*! @brief Structure is used to hold the parameters to configure a PWM fault */ +typedef struct _pwm_fault_param +{ + pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ + bool faultLevel; /*!< true: Logic 1 indicates fault; + false: Logic 0 indicates fault */ + bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; + false: No combination path is available */ + pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ +} pwm_fault_param_t; + +/*! + * @brief Structure is used to hold parameters to configure the capture capability of a signal pin + */ +typedef struct _pwm_input_capture_param +{ + bool captureInputSel; /*!< true: Use the edge counter signal as source + false: Use the raw input signal from the pin as source */ + uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ + pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ + pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ + bool enableOneShotCapture; /*!< true: Use one-shot capture mode; + false: Use free-running capture mode */ + uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in + the status register will set if the word count in the FIFO + is greater than this watermark level */ +} pwm_input_capture_param_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name Module PWM output + * @{ + */ +/*! + * @brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM main counter clock in Hz. + * + * @return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Updates the PWM signal's dutycycle with 16-bit accuracy. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCycle New PWM pulse width, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycleHighAccuracy( + PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle); + +/*! @}*/ + +/*! + * @brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel in the submodule to setup + * @param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams); + +/*! + * @brief Sets up the PWM fault input filter. + * + * @param base PWM peripheral base address + * @param faultInputFilterParams Parameters passed in to set up the fault input filter. + */ +void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams); + +/*! + * @brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * @param base PWM peripheral base address + * @param faultNum PWM fault to configure. + * @param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); + +/*! + * @brief Fill in the PWM fault config struct with the default settings + * + * The default values are: + * @code + * config->faultClearingMode = kPWM_Automatic; + * config->faultLevel = false; + * config->enableCombinationalPath = true; + * config->recoverMode = kPWM_NoRecovery; + * @endcode + * @param config Pointer to user's PWM fault config structure. + */ +void PWM_FaultDefaultConfig(pwm_fault_param_t *config); + +/*! + * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_force_signal_t mode); + +/*! + * @name Interrupts Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Disables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Gets the enabled PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); + +/*! @}*/ + +/*! + * @name DMA Interface + * @{ + */ + +/*! + * @brief Capture DMA Enable Source Select. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwm_watermark_control PWM FIFO watermark and control + */ +static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, + pwm_submodule_t subModule, + pwm_watermark_control_t pwm_watermark_control) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (pwm_watermark_control == kPWM_FIFOWatermarksOR) + { + reg &= ~((uint16_t)PWM_DMAEN_FAND_MASK); + } + else + { + reg |= ((uint16_t)PWM_DMAEN_FAND_MASK); + } + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Capture DMA Enable Source Select. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwm_dma_source_select PWM capture DMA enable source select + */ +static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, + pwm_submodule_t subModule, + pwm_dma_source_select_t pwm_dma_source_select) +{ + uint16_t reg = base->SM[subModule].DMAEN; + + reg &= ~((uint16_t)PWM_DMAEN_CAPTDE_MASK); + reg |= (((uint16_t)pwm_dma_source_select << (uint16_t)PWM_DMAEN_CAPTDE_SHIFT) & (uint16_t)PWM_DMAEN_CAPTDE_MASK); + + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Enables or disables the selected PWM DMA Capture read request. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The DMA to enable or disable. This is a logical OR of members of the + * enumeration ::pwm_dma_enable_t + * @param activate true: Enable DMA read request; false: Disable DMA read request + */ +static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (activate) + { + reg |= (uint16_t)(mask); + } + else + { + reg &= ~((uint16_t)(mask)); + } + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Enables or disables the PWM DMA write request. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param activate true: Enable DMA write request; false: Disable DMA write request + */ +static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (activate) + { + reg |= ((uint16_t)PWM_DMAEN_VALDE_MASK); + } + else + { + reg &= ~((uint16_t)PWM_DMAEN_VALDE_MASK); + } + base->SM[subModule].DMAEN = reg; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Clears the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the PWM counter for a single or multiple submodules. + * + * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) +{ + base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); +} + +/*! + * @brief Stops the PWM counter for a single or multiple submodules. + * + * Clears the Run bit which resets the submodule's counter. This function can stop multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) +{ + base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); +} + +/*! @}*/ + +/*! + * @brief Enables or disables the PWM output trigger. + * + * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 + * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated + * when the counter matches VAL 1, VAL 3, or VAL 5 register. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister Value register that will activate the trigger + * @param activate true: Enable the trigger; false: Disable the trigger + */ +static inline void PWM_OutputTriggerEnable(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + bool activate) +{ + if (activate) + { + base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister); + } + else + { + base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister); + } +} + +/*! + * @brief Enables the PWM output trigger. + * + * This function allows the user to enable one or more (VAL0-5) PWM trigger. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegisterMask Value register mask that will activate one or more (VAL0-5) trigger + * enumeration ::_pwm_value_register_mask + */ +static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) +{ + base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); +} + +/*! + * @brief Disables the PWM output trigger. + * + * This function allows the user to disables one or more (VAL0-5) PWM trigger. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegisterMask Value register mask that will Deactivate one or more (VAL0-5) trigger + * enumeration ::_pwm_value_register_mask + */ +static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) +{ + base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); +} + +/*! + * @brief Sets the software control output for a pin to high or low. + * + * The user specifies which channel to modify by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param value true: Supply a logic 1, false: Supply a logic 0. + */ +static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) +{ + if (value) + { + base->SWCOUT |= + ((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); + } + else + { + base->SWCOUT &= + ~((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); + } +} + +/*! + * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules + * + * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The + * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the + * values are loaded at the next PWM reload point. + * This function can issue the load command to multiple submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of + * members of the enumeration ::pwm_module_control_t + * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit + */ +static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) +{ + if (value) + { + base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); + } + else + { + base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); + } +} + +/*! + * @brief Set PWM output fault status + * + * These bits determine the fault state for the PWM_A output in fault conditions + * and STOP mode. It may also define the output state in WAIT and DEBUG modes + * depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. + * This function can update PWM output fault status. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param faultState PWM output fault status + */ +static inline void PWM_SetPwmFaultState(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_fault_state_t faultState) +{ + uint16_t reg = base->SM[subModule].OCTRL; + switch (pwmChannel) + { + case kPWM_PwmA: + reg &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMAFS_MASK); + break; + case kPWM_PwmB: + reg &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMBFS_MASK); + break; + case kPWM_PwmX: + reg &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMXFS_MASK); + break; + default: + assert(false); + break; + } + base->SM[subModule].OCTRL = reg; +} + +/*! + * @brief Set PWM fault disable mapping + * + * Each of the four bits of this read/write field is one-to-one associated + * with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned + * off if there is a logic 1 on an FAULTx input and a 1 in the corresponding + * bit of this field. A reset sets all bits in this field. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param pwm_fault_channels PWM fault channel to configure + * @param value Fault disable mapping mask value + * enumeration ::pwm_fault_disable_t + */ +static inline void PWM_SetupFaultDisableMap(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_fault_channels_t pwm_fault_channels, + uint16_t value) +{ + uint16_t reg = base->SM[subModule].DISMAP[pwm_fault_channels]; + switch (pwmChannel) + { + case kPWM_PwmA: + reg &= ~((uint16_t)PWM_DISMAP_DIS0A_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0A_SHIFT) & (uint16_t)PWM_DISMAP_DIS0A_MASK); + break; + case kPWM_PwmB: + reg &= ~((uint16_t)PWM_DISMAP_DIS0B_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0B_SHIFT) & (uint16_t)PWM_DISMAP_DIS0B_MASK); + break; + case kPWM_PwmX: + reg &= ~((uint16_t)PWM_DISMAP_DIS0X_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0X_SHIFT) & (uint16_t)PWM_DISMAP_DIS0X_MASK); + break; + default: + assert(false); + break; + } + base->SM[subModule].DISMAP[pwm_fault_channels] = reg; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PWM_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.c new file mode 100644 index 0000000000000000000000000000000000000000..411cdf3c0483d864cde266da283949c2dfbbaaac --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + uint32_t volatile *pointPresetCtrl = &SYSCON->PRESETCTRL0; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (pointPresetCtrl[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + uint32_t volatile *pointPresetCtrl = &SYSCON->PRESETCTRL0; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (pointPresetCtrl[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.h new file mode 100644 index 0000000000000000000000000000000000000000..4363f678ed3e78b207ab87e2879bb47f3676fa4a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_reset.h @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.0. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kROM_RST_SHIFT_RSTn = (0 | (1U)), /**< ROM reset control .*/ + kSRAM_CTRL1_RST_SHIFT_RSTn = (0 | (3U)), /**< SRAM Controller 1 reset control .*/ + kSRAM_CTRL2_RST_SHIFT_RSTn = (0 | (4U)), /**< SRAM Controller 2 reset control .*/ + kSRAM_CTRL3_RST_SHIFT_RSTn = (0 | (5U)), /**< SRAM Controller 3 reset control .*/ + kSRAM_CTRL4_RST_SHIFT_RSTn = (0 | (6U)), /**< SRAM Controller 4 reset control .*/ + kFLASH_RST_SHIFT_RSTn = (0 | (7U)), /**< FLASH reset control .*/ + kFMC_RST_SHIFT_RSTn = (0 | (8U)), /**< FMC reset control .*/ + kFLEXSPI_RST_SHIFT_RSTn = (0 | (10U)), /**< FLEXSPI reset control .*/ + kMUX_RST_SHIFT_RSTn = (0 | (11U)), /**< MUX reset control .*/ + kIOCON_RST_SHIFT_RSTn = (0 | (13U)), /**< IOCON reset control .*/ + kGPIO0_RST_SHIFT_RSTn = (0 | (14U)), /**< GPIO0 reset control .*/ + kGPIO1_RST_SHIFT_RSTn = (0 | (15U)), /**< GPIO1 reset control .*/ + kGPIO2_RST_SHIFT_RSTn = (0 | (16U)), /**< GPIO2 reset control .*/ + kGPIO3_RST_SHIFT_RSTn = (0 | (17U)), /**< GPIO3 reset control .*/ + kPINT_RST_SHIFT_RSTn = (0 | (18U)), /**< PINT reset control .*/ + kGINT_RST_SHIFT_RSTn = (0 | (19U)), /**< GINT reset control .*/ + kDMA0_RST_SHIFT_RSTn = (0 | (20U)), /**< DMA0 reset control .*/ + kCRC_RST_SHIFT_RSTn = (0 | (21U)), /**< CRC reset control .*/ + kWWDT_RST_SHIFT_RSTn = (0 | (22U)), /**< WWDT reset control .*/ + kRTC_RST_SHIFT_RSTn = (0 | (23U)), /**< RTC reset control .*/ + kMAILBOX_RST_SHIFT_RSTn = (0 | (26U)), /**< MAILBOX reset control .*/ + kADC0_RST_SHIFT_RSTn = (0 | (27U)), /**< ADC0 reset control .*/ + kADC1_RST_SHIFT_RSTn = (0 | (28U)), /**< ADC1 reset control .*/ + kDAC0_RST_SHIFT_RSTn = (0 | (29U)), /**< DAC0 reset control .*/ + + kMRT_RST_SHIFT_RSTn = (0x10000 | (0U)), /**< MRT reset control .*/ + kOSTIMER_RST_SHIFT_RSTn = (0x10000 | (1U)), /**< OSTIMER reset control .*/ + kSCT_RST_SHIFT_RSTn = (0x10000 | (2U)), /**< SCT reset control .*/ + kMCAN_RST_SHIFT_RSTn = (0x10000 | (7U)), /**< MCAN reset control .*/ + kUTICK_RST_SHIFT_RSTn = (0x10000 | (10U)), /**< UTICK reset control .*/ + kFC0_RST_SHIFT_RSTn = (0x10000 | (11U)), /**< FC0 reset control .*/ + kFC1_RST_SHIFT_RSTn = (0x10000 | (12U)), /**< FC1 reset control .*/ + kFC2_RST_SHIFT_RSTn = (0x10000 | (13U)), /**< FC2 reset control .*/ + kFC3_RST_SHIFT_RSTn = (0x10000 | (14U)), /**< FC3 reset control .*/ + kFC4_RST_SHIFT_RSTn = (0x10000 | (15U)), /**< FC4 reset control .*/ + kFC5_RST_SHIFT_RSTn = (0x10000 | (16U)), /**< FC5 reset control .*/ + kFC6_RST_SHIFT_RSTn = (0x10000 | (17U)), /**< FC6 reset control .*/ + kFC7_RST_SHIFT_RSTn = (0x10000 | (18U)), /**< FC7 reset control .*/ + kDMIC_RST_SHIFT_RSTn = (0x10000 | (19U)), /**< DMIC reset control .*/ + kCTIMER2_RST_SHIFT_RSTn = (0x10000 | (22U)), /**< TIMER2 reset control .*/ + kUSB0_DEV_RST_SHIFT_RSTn = (0x10000 | (25U)), /**< USB0_DEV reset control .*/ + kCTIMER0_RST_SHIFT_RSTn = (0x10000 | (26U)), /**< TIMER0 reset control .*/ + kCTIMER1_RST_SHIFT_RSTn = (0x10000 | (27U)), /**< TIMER1 reset control .*/ + + kDMA1_RST_SHIFT_RSTn = (0x20000 | (1U)), /**< DMA1 reset control .*/ + kCMP_RST_SHIFT_RSTn = (0x20000 | (2U)), /**< CMP reset control .*/ + kFREQME_RST_SHIFT_RSTn = (0x20000 | (8U)), /**< FREQME reset control .*/ + kCDOG_RST_SHIFT_RSTn = (0x20000 | (11U)), /**< Code Watchdog reset control */ + kRNG_RST_SHIFT_RSTn = (0x20000 | (13U)), /**< RNG reset control .*/ + kSYSCTL_RST_SHIFT_RSTn = (0x20000 | (15U)), /**< SYSCTL reset control .*/ + kUSB0HMR_RST_SHIFT_RSTn = (0x20000 | (16U)), /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = (0x20000 | (17U)), /**< USB0HSL reset control */ + kCSS_RST_SHIFT_RSTn = (0x20000 | (18U)), /**< CSS reset control .*/ + kPOWERQUAD_RST_SHIFT_RSTn = (0x20000 | (19U)), /**< PowerQuad reset control .*/ + kCTIMER3_RST_SHIFT_RSTn = (0x20000 | (21U)), /**< TIMER3 reset control .*/ + kCTIMER4_RST_SHIFT_RSTn = (0x20000 | (22U)), /**< TIMER4 reset control .*/ + kPUF_RST_SHIFT_RSTn = (0x20000 | (23U)), /**< PUF reset control */ + kPKC_RST_SHIFT_RSTn = (0x20000 | (24U)), /**< PKC reset control .*/ + kANACTRL_RST_SHIFT_RSTn = (0x20000 | (27U)), /**< ANACTRL reset control .*/ + kHSLSPI_RST_SHIFT_RSTn = (0x20000 | (28U)), /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = (0x20000 | (29U)), /**< GPIO_SEC reset control .*/ + kGPIOSECINT_RST_SHIFT_RSTn = (0x20000 | (30U)), /**< GPIO secure int reset control .*/ + + kI3C0_RST_SHIFT_RSTn = (0x30000 | (0U)), /**< I3C0 reset control .*/ + kENC0_RST_SHIFT_RSTn = (0x30000 | (3U)), /**< ENC0 reset control .*/ + kENC1_RST_SHIFT_RSTn = (0x30000 | (4U)), /**< ENC1 reset control .*/ + kPWM0_RST_SHIFT_RSTn = (0x30000 | (5U)), /**< PWM0 reset control .*/ + kPWM1_RST_SHIFT_RSTn = (0x30000 | (6U)), /**< PWM1 reset control .*/ + kAOI0_RST_SHIFT_RSTn = (0x30000 | (7U)), /**< AOI0 reset control .*/ + kAOI1_RST_SHIFT_RSTn = (0x30000 | (8U)), /**< AOI1 reset control .*/ + kFTM0_RST_SHIFT_RSTn = (0x30000 | (9U)), /**< FTM0 reset control .*/ + kDAC1_RST_SHIFT_RSTn = (0x30000 | (10U)), /**< DAC1 reset control .*/ + kDAC2_RST_SHIFT_RSTn = (0x30000 | (11U)), /**< DAC2 reset control .*/ + kOPAMP0_RST_SHIFT_RSTn = (0x30000 | (12U)), /**< OPAMP0 reset control .*/ + kOPAMP1_RST_SHIFT_RSTn = (0x30000 | (13U)), /**< OPAMP1 reset control .*/ + kOPAMP2_RST_SHIFT_RSTn = (0x30000 | (14U)), /**< OPAMP2 reset control .*/ + kHSCMP0_RST_SHIFT_RSTn = (0x30000 | (15U)), /**< HSCMP0 reset control .*/ + kHSCMP1_RST_SHIFT_RSTn = (0x30000 | (16U)), /**< HSCMP1 reset control .*/ + kHSCMP2_RST_SHIFT_RSTn = (0x30000 | (17U)), /**< HSCMP2 reset control .*/ + kVREF_RST_SHIFT_RSTn = (0x30000 | (18U)), /**< VREF reset control .*/ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define MCAN_RSTS \ + { \ + kMCAN_RST_SHIFT_RSTn \ + } /* Reset bits for CAN peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn, kGPIO_SEC_INT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define CDOG_RSTS \ + { \ + kCDOG_RST_SHIFT_RSTn \ + } /* Reset bits for CDOG peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SCT_RSTS \ + { \ + kSCT_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define USB0D_RST \ + { \ + kUSB0_DEV_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define I3C_RSTS \ + { \ + kI3C0_RST_SHIFT_RSTn \ + } /* Reset bits for I3C peripheral */ +#define ENC_RSTS \ + { \ + kENC0_RST_SHIFT_RSTn, kENC1_RST_SHIFT_RSTn \ + } /* Reset bits for ENC peripheral */ +#define PWM_RSTS \ + { \ + kPWM0_RST_SHIFT_RSTn, kPWM1_RST_SHIFT_RSTn \ + } /* Reset bits for PWM peripheral */ +#define AOI_RSTS \ + { \ + kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn \ + } /* Reset bits for AOI peripheral */ +#define DAC_RSTS \ + { \ + kDAC0_RST_SHIFT_RSTn, kDAC1_RST_SHIFT_RSTn \ + } /* Reset bits for DAC peripheral */ +#define OPAMP_RSTS \ + { \ + kOPAMP0_RST_SHIFT_RSTn, kOPAMP1_RST_SHIFT_RSTn, kOPAMP2_RST_SHIFT_RSTn \ + } /* Reset bits for OPAMP peripheral */ +#define HSCMP_RSTS \ + { \ + kHSCMP0_RST_SHIFT_RSTn, kHSCMP1_RST_SHIFT_RSTn, kHSCMP2_RST_SHIFT_RSTn \ + } /* Reset bits for HSCMP peripheral */ +#define POWERQUAD_RSTS \ + { \ + kPOWERQUAD_RST_SHIFT_RSTn \ + } /* Reset bits for Powerquad peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.c new file mode 100644 index 0000000000000000000000000000000000000000..5ed3445ad582a004834f40d029964b0b943dce41 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.c @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sctimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sctimer" +#endif + +/*! @brief Typedef for interrupt handler. */ +typedef void (*sctimer_isr_t)(SCT_Type *base); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base SCTimer peripheral base address + * + * @return The SCTimer instance + */ +static uint32_t SCTIMER_GetInstance(SCT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to SCT bases for each instance. */ +static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SCT clocks for each instance. */ +static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; +#else +/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*!< @brief SCTimer event Callback function. */ +static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; + +/*!< @brief Keep track of SCTimer event number */ +static uint32_t s_currentEvent; + +/*!< @brief Keep track of SCTimer state number */ +static uint32_t s_currentState; + +/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ +static uint32_t s_currentMatch; +/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ +static uint32_t s_currentMatchhigh; + +/*! @brief Pointer to SCTimer IRQ handler */ +static sctimer_isr_t s_sctimerIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SCTIMER_GetInstance(SCT_Type *base) +{ + uint32_t instance; + uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < sctArrayCount; instance++) + { + if (s_sctBases[instance] == base) + { + break; + } + } + + assert(instance < sctArrayCount); + + return instance; +} + +/*! + * brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SCTimer driver. + * + * param base SCTimer peripheral base address + * param config Pointer to the user configuration structure. + * + * return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) +{ + assert(NULL != config); + + uint32_t i; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SCTimer clock*/ + CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail + * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ + base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | + SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); + + /* Write to the control register, keep the counters halted. */ + base->CTRL = + SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; + /* Clear the counter after changing the PRE value. */ + base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; + + if (!(config->enableCounterUnify)) + { + base->CTRL |= + SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; + base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; + } + + /* Initial state of channel output */ + base->OUTPUT = config->outInitState; + + /* Clear the global variables */ + s_currentEvent = 0U; + s_currentState = 0U; + s_currentMatch = 0U; + s_currentMatchhigh = 0U; + + /* Clear the callback array */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + { + s_eventCallback[i] = NULL; + } + + /* Save interrupt handler */ + s_sctimerIsr = SCTIMER_EventHandleIRQ; + + return kStatus_Success; +} + +/*! + * brief Gates the SCTimer clock. + * + * param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base) +{ + /* Halt the counters */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the SCTimer clock*/ + CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0U; + * config->prescale_h = 0U; + * config->outInitState = 0U; + * config->inputsync = 0xFU; + * endcode + * param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* SCT operates as a unified 32-bit counter */ + config->enableCounterUnify = true; + /* System clock clocks the entire SCT module */ + config->clockMode = kSCTIMER_System_ClockMode; + /* This is used only by certain clock modes */ + config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + /* Up count mode only for the unified counter */ + config->enableBidirection_l = false; + /* Up count mode only for Counte_H */ + config->enableBidirection_h = false; + /* Prescale factor of 1 */ + config->prescale_l = 0U; + /* Prescale factor of 1 for Counter_H*/ + config->prescale_h = 0U; + /* Clear outputs */ + config->outInitState = 0U; + /* Default value is 0xFU, it can be clear as 0 when speical conditions met. + * Condition can be clear as 0: (for all Clock Modes): + * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. + * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. + * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input + * clock for CKMODE3. + * Another condition can be clear as 0: (for CKMODE2 only) + * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. + * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. + * Default value set as 0U, input0~input3 are set as bypasses. */ + config->inputsync = 0xFU; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * param base SCTimer peripheral base address + * param pwmParams PWM parameters to configure the output + * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz SCTimer counter clock in Hz + * param event Pointer to a variable where the PWM period event number is stored + * + * return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event) +{ + assert(NULL != pwmParams); + assert(0U != srcClock_Hz); + assert(0U != pwmFreq_Hz); + assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + + /* If we do not have enough events available (this function will create two events), + * the function will return fail. + */ + status_t status = kStatus_Fail; + status_t status2; + uint32_t period, pulsePeriod = 0; + uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); + uint32_t periodEvent = 0, pulseEvent = 0; + uint32_t reg; + + if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + /* Use bi-directional mode for center-aligned PWM */ + if (mode == kSCTIMER_CenterAlignedPwm) + { + base->CTRL |= SCT_CTRL_BIDIR_L_MASK; + } + + /* Calculate PWM period match value */ + if (mode == kSCTIMER_EdgeAlignedPwm) + { + period = (sctClock / pwmFreq_Hz) - 1U; + } + else + { + period = sctClock / (pwmFreq_Hz * 2U); + } + + /* Calculate pulse width and period match value: + * For EdgeAlignedPwm, "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period - 1U" results in 100% + * dutycyle. For CenterAlignedPwm, , "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period + 2U" + * results in 100% dutycyle. + */ + + pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); + + if (pwmParams->dutyCyclePercent >= 100U) + { + if (mode == kSCTIMER_EdgeAlignedPwm) + { + pulsePeriod = period + 2U; + } + else + { + pulsePeriod = period - 1U; + } + } + + /* Schedule an event when we reach the PWM period */ + status = + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); + + /* Schedule an event when we reach the pulse width */ + status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, + &pulseEvent); + + if ((kStatus_Success == status) && (kStatus_Success == status2)) + { + /* Reset the counter when we reach the PWM period */ + SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); + + /* Return the period event to the user */ + *event = periodEvent; + + /* For high-true level */ + if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); + + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the output when we reach the PWM period */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); + /* Clear the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); + } + else + { + /* Clear the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); + reg |= (1UL << (2U * (uint32_t)pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + /* For low-true level */ + else + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); + + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Clear the output when we reach the PWM period */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); + /* Set the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); + } + else + { + /* Set the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); + reg |= (1UL << (2U * (uint32_t)pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + } + else + { + status = kStatus_Fail; + } + } + + return status; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). + * + * param base SCTimer peripheral base address + * param output The output to configure + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + * param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) + +{ + assert(dutyCyclePercent <= 100U); + assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + + uint32_t periodMatchReg, pulseMatchReg; + uint32_t pulsePeriod = 0, period; + + /* Retrieve the match register number for the PWM period */ + periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; + + /* Retrieve the match register number for the PWM pulse period */ + pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; + + period = base->MATCH[periodMatchReg]; + + /* Calculate pulse width and period match value: + * For EdgeAlignedPwm, "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period - 1U" results in 100% + * dutycyle. For CenterAlignedPwm, , "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period + 2U" + * results in 100% dutycyle. + */ + pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); + + if (dutyCyclePercent == 100U) + { + if (0U == (base->CTRL & SCT_CTRL_BIDIR_L_MASK)) + { + pulsePeriod = period + 2U; + } + else + { + pulsePeriod = period - 1U; + } + } + + /* Stop the counter before updating match register */ + SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); + + /* Update dutycycle */ + base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); + base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); + + /* Restart the counter */ + SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); +} + +/*! + * brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * param base SCTimer peripheral base address + * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * param matchValue The match value that will be programmed to a match register + * param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * param event Pointer to a variable where the new event number is stored + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event) +{ + uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); + uint32_t currentCtrlVal = (uint32_t)howToMonitor; + status_t status = kStatus_Success; + + if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + if (2U == combMode) + { + base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); + } + else + { + if ((0U == combMode) || (3U == combMode)) + { + currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); + } + + if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); + + /* Use Counter_L bits if user wants to setup the Low counter */ + base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; + base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; + base->EV[s_currentEvent].CTRL = currentCtrlVal; + + /* Increment the match register number */ + s_currentMatch++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); + + /* Use Counter_H bits if user wants to setup the High counter */ + currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); + base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHH = (uint16_t)matchValue; + base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELH = (uint16_t)matchValue; + + base->EV[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatchhigh++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Use Counter_L bits if counter is operating in 32-bit mode */ + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); + + base->MATCH[s_currentMatch] = matchValue; + base->MATCHREL[s_currentMatch] = matchValue; + base->EV[s_currentEvent].CTRL = currentCtrlVal; + + /* Increment the match register number */ + s_currentMatch++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else + { + /* The used counter must match the CONFIG[UNIFY] bit selection */ + status = kStatus_Fail; + } + } + + if (kStatus_Success == status) + { + /* Enable the event in the current state */ + base->EV[s_currentEvent].STATE = (1UL << s_currentState); + + /* Return the event number */ + *event = s_currentEvent; + + /* Increment the event number */ + s_currentEvent++; + } + } + else + { + /* An error would occur if we have hit the limit in terms of number of events created */ + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * param base SCTimer peripheral base address + * param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) +{ + /* Enable event in the current state */ + base->EV[event].STATE |= (1UL << s_currentState); +} + +/*! + * brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * param base SCTimer peripheral base address + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base) +{ + status_t status = kStatus_Success; + + /* Return an error if we have hit the limit in terms of states used */ + if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) + { + status = kStatus_Fail; + } + else + { + s_currentState++; + } + + return status; +} + +/*! + * brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * param base SCTimer peripheral base address + * + * return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base) +{ + return s_currentState; +} + +/*! + * brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * param base SCTimer peripheral base address + * param whichIO The output to toggle + * param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t reg; + + /* Set the same event to set and clear the output */ + base->OUT[whichIO].CLR |= (1UL << event); + base->OUT[whichIO].SET |= (1UL << event); + + /* Set the conflict resolution to toggle output */ + reg = base->RES; + reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); + reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); + base->RES = reg; +} + +/*! + * brief Setup capture of the counter value on trigger of a selected event + * + * param base SCTimer peripheral base address + * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * param event Event number that will trigger the capture + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event) +{ + status_t status; + + if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Set the bit to enable event */ + base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); + + /* Return the match register number */ + *captureRegister = s_currentMatch; + + /* Increase the match register number */ + s_currentMatch++; + + status = kStatus_Success; + } + else + { + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + status = kStatus_Fail; + } + } + else + { + if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Set bit to enable event */ + base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLH |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE_ACCESS16BIT.REGMODEH |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatchhigh); + + /* Return the match register number */ + *captureRegister = s_currentMatchhigh; + + /* Increase the match register number */ + s_currentMatchhigh++; + + status = kStatus_Success; + } + else + { + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + status = kStatus_Fail; + } + } + + return status; +} + +/*! + * brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * param base SCTimer peripheral base address + * param event Event number that will trigger the interrupt + * param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) +{ + s_eventCallback[event] = callback; +} + +/*! + * brief SCTimer interrupt handler. + * + * param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base) +{ + uint32_t eventFlag = SCT0->EVFLAG; + /* Only clear the flags whose interrupt field is enabled */ + uint32_t clearFlag = (eventFlag & SCT0->EVEN); + uint32_t mask = eventFlag; + uint32_t i; + + /* Invoke the callback for certain events */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + { + if ((mask & 0x1U) != 0U) + { + if (s_eventCallback[i] != NULL) + { + s_eventCallback[i](); + } + } + mask >>= 1UL; + + if (0U == mask) + { + /* All events have been handled. */ + break; + } + } + + /* Clear event interrupt flag */ + SCT0->EVFLAG = clearFlag; +} + +void SCT0_DriverIRQHandler(void); +void SCT0_DriverIRQHandler(void) +{ + s_sctimerIsr(SCT0); + SDK_ISR_EXIT_BARRIER; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.h new file mode 100644 index 0000000000000000000000000000000000000000..01ccdd9077212ace57b337f95ed83befcffc2338 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sctimer.h @@ -0,0 +1,1258 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SCTIMER_H_ +#define _FSL_SCTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) /*!< Version */ +/*@}*/ + +#ifndef SCT_EV_STATE_STATEMSKn +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) +#endif + +/*! @brief SCTimer PWM operation modes */ +typedef enum _sctimer_pwm_mode +{ + kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ +} sctimer_pwm_mode_t; + +/*! @brief SCTimer counters type. */ +typedef enum _sctimer_counter +{ + kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ + kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ + kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ +} sctimer_counter_t; + +/*! @brief List of SCTimer input pins */ +typedef enum _sctimer_input +{ + kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ + kSCTIMER_Input_1, /*!< SCTIMER input 1 */ + kSCTIMER_Input_2, /*!< SCTIMER input 2 */ + kSCTIMER_Input_3, /*!< SCTIMER input 3 */ + kSCTIMER_Input_4, /*!< SCTIMER input 4 */ + kSCTIMER_Input_5, /*!< SCTIMER input 5 */ + kSCTIMER_Input_6, /*!< SCTIMER input 6 */ + kSCTIMER_Input_7 /*!< SCTIMER input 7 */ +} sctimer_input_t; + +/*! @brief List of SCTimer output pins */ +typedef enum _sctimer_out +{ + kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ + kSCTIMER_Out_1, /*!< SCTIMER output 1 */ + kSCTIMER_Out_2, /*!< SCTIMER output 2 */ + kSCTIMER_Out_3, /*!< SCTIMER output 3 */ + kSCTIMER_Out_4, /*!< SCTIMER output 4 */ + kSCTIMER_Out_5, /*!< SCTIMER output 5 */ + kSCTIMER_Out_6, /*!< SCTIMER output 6 */ + kSCTIMER_Out_7, /*!< SCTIMER output 7 */ + kSCTIMER_Out_8, /*!< SCTIMER output 8 */ + kSCTIMER_Out_9 /*!< SCTIMER output 9 */ +} sctimer_out_t; + +/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ +typedef enum _sctimer_pwm_level_select +{ + kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ + kSCTIMER_HighTrue /*!< High true pulses */ +} sctimer_pwm_level_select_t; + +/*! @brief Options to configure a SCTimer PWM signal */ +typedef struct _sctimer_pwm_signal_param +{ + sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ + sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0 = always inactive signal (0% duty cycle) + 100 = always active signal (100% duty cycle).*/ +} sctimer_pwm_signal_param_t; + +/*! @brief SCTimer clock mode options */ +typedef enum _sctimer_clock_mode +{ + kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ + kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ + kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ + kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ +} sctimer_clock_mode_t; + +/*! @brief SCTimer clock select options */ +typedef enum _sctimer_clock_select +{ + kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ + kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ + kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ + kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ + kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ + kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ + kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ + kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ + kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ + kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ + kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ + kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ + kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ + kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ + kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ + kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ +} sctimer_clock_select_t; + +/*! + * @brief SCTimer output conflict resolution options. + * + * Specifies what action should be taken if multiple events dictate that a given output should be + * both set and cleared at the same time + */ +typedef enum _sctimer_conflict_resolution +{ + kSCTIMER_ResolveNone = 0U, /*!< No change */ + kSCTIMER_ResolveSet, /*!< Set output */ + kSCTIMER_ResolveClear, /*!< Clear output */ + kSCTIMER_ResolveToggle /*!< Toggle output */ +} sctimer_conflict_resolution_t; + +/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ +typedef enum _sctimer_event_active_direction +{ + kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ + kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ + kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ +} sctimer_event_active_direction_t; + +/*! @brief List of SCTimer event types */ +typedef enum _sctimer_event +{ + kSCTIMER_InputLowOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_MatchEventOnly = + (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) +} sctimer_event_t; + +/*! @brief SCTimer callback typedef. */ +typedef void (*sctimer_event_callback_t)(void); + +/*! @brief List of SCTimer interrupts */ +typedef enum _sctimer_interrupt_enable +{ + kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ + kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ + kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ + kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ + kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ + kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ + kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ + kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ + kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ + kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ + kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ + kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ + kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ +} sctimer_interrupt_enable_t; + +/*! @brief List of SCTimer flags */ +typedef enum _sctimer_status_flags +{ + kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ + kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ + kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ + kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ + kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ + kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ + kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ + kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ + kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ + kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ + kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ + kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ + kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ + kSCTIMER_BusErrorLFlag = + (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ + kSCTIMER_BusErrorHFlag = + (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ +} sctimer_status_flags_t; + +/*! + * @brief SCTimer configuration structure + * + * This structure holds the configuration settings for the SCTimer peripheral. To initialize this + * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _sctimer_config +{ + bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; + false: SCT operates as two 16-bit counters. + User can use the 16-bit low counter and the 16-bit high counters at the + same time; for Hardware limit, user can not use unified 32-bit counter + and any 16-bit low/high counter at the same time. */ + sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ + sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ + bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter + false: Up count mode only for the L or unified counter */ + bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter + false: Up count mode only for the H or unified counter. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ + uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t outInitState; /*!< Defines the initial output value */ + uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. + it is used to define synchronization for input N: + bit 9 = input 0 + bit 10 = input 1 + bit 11 = input 2 + bit 12 = input 3 + All other bits are reserved (bit13 ~bit 16). + How User to set the the value for the member inputsync. + IE: delay for input0, and input 1, bypasses for input 2 and input 3 + MACRO definition in user level. + \#define INPUTSYNC0 (0U) + \#define INPUTSYNC1 (1U) + \#define INPUTSYNC2 (2U) + \#define INPUTSYNC3 (3U) + User Code. + sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ +} sctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SCTimer driver. + * + * @param base SCTimer peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); + +/*! + * @brief Gates the SCTimer clock. + * + * @param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base); + +/*! + * @brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * @code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0U; + * config->prescale_h = 0U; + * config->outInitState = 0U; + * config->inputsync = 0xFU; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * @note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * @param base SCTimer peripheral base address + * @param pwmParams PWM parameters to configure the output + * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz SCTimer counter clock in Hz + * @param event Pointer to a variable where the PWM period event number is stored + * + * @return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). + * + * @param base SCTimer peripheral base address + * @param output The output to configure + * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * @param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN |= mask; +} + +/*! + * @brief Disables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN &= ~mask; +} + +/*! + * @brief Gets the enabled SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) +{ + return (base->EVEN & 0xFFFFU); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) +{ + uint32_t statusFlags = 0; + + /* Add the recorded events */ + statusFlags = (base->EVFLAG & 0xFFFFU); + + /* Add bus error flags */ + statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); + + return statusFlags; +} + +/*! + * @brief Clears the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) +{ + /* Write to the flag registers */ + base->EVFLAG = (mask & 0xFFFFU); + base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the SCTimer counter. + * + * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. + * + * @param base SCTimer peripheral base address + * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the + * enumeration ::sctimer_counter_t. + */ +static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) +{ + switch (countertoStart) + { + case (uint32_t)kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L bit when user wants to start the Low counter */ + base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_H bit when user wants to start the High counter */ + base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); + break; + + default: + /* Counter_L/Counter_H can't work together with Counter_U. */ + assert(false); + break; + } +} + +/*! + * @brief Halts the SCTimer counter. + * + * @param base SCTimer peripheral base address + * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the + * enumeration ::sctimer_counter_t. + */ +static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) +{ + switch (countertoStop) + { + case (uint32_t)kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_L bit when user wants to start the Low counter */ + base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_H bit when user wants to start the High counter */ + base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK); + break; + + default: + /* Counter_L/Counter_H can't work together with Counter_U. */ + assert(false); + break; + } +} + +/*! @}*/ + +/*! + * @name Functions to create a new event and manage the state logic + * @{ + */ + +/*! + * @brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * @param base SCTimer peripheral base address + * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * @param matchValue The match value that will be programmed to a match register + * @param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Pointer to a variable where the new event number is stored + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event); + +/*! + * @brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * @param base SCTimer peripheral base address + * @param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); + +/*! + * @brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * @param base SCTimer peripheral base address + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base); + +/*! + * @brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * @param base SCTimer peripheral base address + * + * @return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base); + +/*! + * @brief Set the counter current state. + * + * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified + * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param state The counter current state number (only support range from 0~31). + */ +static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) +{ + /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + + SCTIMER_StopTimer(base, (uint32_t)whichCounter); + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when user wants to setup the Low counter */ + base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_H bits when user wants to start the High counter */ + base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ + base->STATE = SCT_STATE_STATE_L(state); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + SCTIMER_StartTimer(base, (uint32_t)whichCounter); +} + +/*! + * @brief Get the counter current state value. + * + * The function is to get the state variable bit field of STATE register. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @return The the counter current state value. + */ +static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) +{ + uint16_t regs; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when user wants to setup the Low counter */ + regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_H bits when user wants to start the High counter */ + regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ + regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return regs; +} + +/*! @}*/ + +/*! + * @name Actions to take in response to an event + * @{ + */ + +/*! + * @brief Setup capture of the counter value on trigger of a selected event + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * @param event Event number that will trigger the capture + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event); + +/*! + * @brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * @param base SCTimer peripheral base address + * @param event Event number that will trigger the interrupt + * @param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); + +/*! + * @brief Change the load method of transition to the specified state. + * + * Change the load method of transition, it will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param event Event number that will change the method to trigger the state transition + * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. + * - true: Load the STATEV value to STATE when the event occurs to be the next state. + * - false: Add the STATEV value to STATE when the event occurs to be the next state. + */ +static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) +{ + uint32_t reg = base->EV[event].CTRL; + + if (fgLoad) + { + /* Load the STATEV value to STATE when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATELD_MASK; + } + else + { + /* Add the STATEV value to STATE when the event occurs to be the next state */ + reg &= ~SCT_EV_CTRL_STATELD_MASK; + } + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Transition to the specified state with Load method. + * + * This transition will be triggered by the event number that is passed in by the user, the method decide how to load + * the highest-numbered event occurring for that state to the STATE register. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. + * - true: Load the STATEV value to STATE when the event occurs to be the next state. + * - false: Add the STATEV value to STATE when the event occurs to be the next state. + */ +static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, + uint32_t nextState, + uint32_t event, + bool fgLoad) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); + + reg |= SCT_EV_CTRL_STATEV(nextState); + + if (fgLoad) + { + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATELD_MASK; + } + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Transition to the specified state. + * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod + * + * This transition will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + */ +static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_STATEV_MASK); + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Setup event active direction when the counters are operating in BIDIR mode. + * + * @param base SCTimer peripheral base address + * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. + * @param event Event number that need setup the active direction. + */ +static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, + sctimer_event_active_direction_t activeDirection, + uint32_t event) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); + + reg |= SCT_EV_CTRL_DIRECTION(activeDirection); + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Set the Output. + * + * This output will be set when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to set + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].SET |= (1UL << event); +} + +/*! + * @brief Clear the Output. + * + * This output will be cleared when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to clear + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].CLR |= (1UL << event); +} + +/*! + * @brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to toggle + * @param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); + +/*! + * @brief Limit the running counter. + * + * The counter is limited when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to be limited + */ +static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +/*! + * @brief Stop the running counter. + * + * The counter is stopped when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to be stopped + */ +static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +/*! + * @brief Re-start the stopped counter. + * + * The counter will re-start when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to re-start + */ +static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->START |= SCT_START_STARTMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +/*! + * @brief Halt the running counter. + * + * The counter is disabled (halted) when the event number that is passed in by the user is + * triggered. When the counter is halted, all further events are disabled. The HALT condition + * can only be removed by calling the SCTIMER_StartTimer() function. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to be halted + */ +static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) +/*! + * @brief Generate a DMA request. + * + * DMA request will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param dmaNumber The DMA request to generate + * @param event Event number that will trigger the DMA request + */ +static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) +{ + if (dmaNumber == 0U) + { + base->DMAREQ0 |= (1UL << event); + } + else + { + base->DMAREQ1 |= (1UL << event); + } +} +#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ + +/*! + * @brief Set the value of counter. + * + * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register + * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param value the counter value update to the COUNT register. + */ +static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) +{ + SCTIMER_StopTimer(base, (uint32_t)whichCounter); + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(value <= 0xFFFFU); + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; + break; + + case kSCTIMER_Counter_H: + assert(value <= 0xFFFFU); + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->COUNT &= ~SCT_COUNT_CTR_L_MASK; + base->COUNT |= SCT_COUNT_CTR_L(value); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + SCTIMER_StartTimer(base, (uint32_t)whichCounter); +} + +/*! + * @brief Get the value of counter. + * + * The function is to read the value of Count register, software can read the counter registers at any time.. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @return The value of counter selected. + */ +static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) +{ + uint32_t value; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + value = base->COUNT_ACCESS16BIT.COUNTL; + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + value = base->COUNT_ACCESS16BIT.COUNTH; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + value = base->COUNT; + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return value; +} + +/*! + * @brief Set the state mask bit field of EV_STATE register. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be set. + * @param state The state value in which the event is enabled to occur. + */ +static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); +} + +/*! + * @brief Clear the state mask bit field of EV_STATE register. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be clear. + * @param state The state value in which the event is disabled to occur. + */ +static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); +} + +/*! + * @brief Get the state mask bit field of EV_STATE register. + * + * @note This function is to check whether the event is enabled in a specific state. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be read. + * @param state The state value. + * + * @return The the state mask bit field of EV_STATE register. + * - true: The event is enable in state. + * - false: The event is disable in state. + */ +static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); +} + +/*! + * @brief SCTimer interrupt handler. + * + * @param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..456361e62042d6bf60c22c672263f0ffbfcab7e3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.c @@ -0,0 +1,1072 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" +#endif + +/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ + +#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) +#define SPI_FIFO_DEPTH(base) 4 +#else +#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) +#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ + +/* Convert transfer count to transfer bytes. dataWidth is a + * range <0,15>. Range <8,15> represents 2B transfer */ +#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) +#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) +#else +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) +#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and + * `flexcomm_spi_slave_irq_handler_t`. + */ +typedef union spi_to_flexcomm +{ + flexcomm_spi_master_irq_handler_t spi_master_handler; + flexcomm_spi_slave_irq_handler_t spi_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} spi_to_flexcomm_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief internal SPI config array */ +static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; + +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + uint32_t i; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) + { + if ((uint32_t)base == s_spiBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); + return i; +} + +/*! + * brief Set up the dummy data. + * + * param base SPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +/*! + * brief Returns the configurations. + * + * param base SPI peripheral address. + * return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base) +{ + uint32_t instance; + instance = SPI_GetInstance(base); + return &g_configs[instance]; +} + +/*! + * brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + endcode + * + * param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableLoopback = false; + config->enableMaster = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->baudRate_Bps = 500000U; + config->dataWidth = kSPI_Data8Bits; + config->sselNum = kSPI_Ssel0; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; +} + +/*! + * brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to master configuration structure + * param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; + + /* assert params */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to SPI mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + if (kStatus_Success != result) + { + return result; + } + + /* set divider */ + result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + + /* get instance number */ + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmpConfig |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmpConfig |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmpConfig |= SPI_CFG_LSBF(config->direction); + /* master mode */ + tmpConfig |= SPI_CFG_MASTER(1); + /* loopback */ + tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + g_configs[instance].sselNum = config->sselNum; + /* enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmpConfig; + + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableMaster); + return kStatus_Success; +} + +/*! + * brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + endcode + * + * param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->dataWidth = kSPI_Data8Bits; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; +} + +/*! + * brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; + + /* assert params */ + assert(!((NULL == base) || (NULL == config))); + if ((NULL == base) || (NULL == config)) + { + return kStatus_InvalidArgument; + } + /* configure flexcomm to SPI, enable clock gate */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + if (kStatus_Success != result) + { + return result; + } + + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmpConfig |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmpConfig |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmpConfig |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + /* empty and enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmpConfig; + + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableSlave); + return kStatus_Success; +} + +/*! + * brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base) +{ + /* Assert arguments */ + assert(NULL != base); + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | + SPI_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); + base->CFG &= ~(SPI_CFG_ENABLE_MASK); +} + +/*! + * brief Enables the DMA request from SPI txFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; + } +} + +/*! + * brief Enables the DMA request from SPI rxFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; + } +} + +/*! + * brief Sets the baud rate for SPI transfer. This is only used in master. + * + * param base SPI base pointer + * param baudrate_Bps baud rate needed in Hz. + * param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t tmpDiv; + + /* assert params */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* calculate baudrate, round up the result */ + tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; + if (tmpDiv > 0xFFFFU) + { + return kStatus_SPI_BaudrateNotSupport; + } + base->DIV &= ~SPI_DIV_DIVVAL_MASK; + base->DIV |= SPI_DIV_DIVVAL(tmpDiv); + return kStatus_Success; +} + +/*! + * brief Writes a data into the SPI data register. + * + * param base SPI base pointer + * param data needs to be write. + * param configFlags transfer configuration options ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) +{ + uint32_t control = 0U; + uint32_t instance; + + /* check params */ + assert(NULL != base); + /* get and check instance */ + instance = SPI_GetInstance(base); + + /* set data width */ + control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); + /* set sssel */ + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); + /* mask configFlags */ + control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); + /* control should not affect lower 16 bits */ + assert(0U == (control & 0xFFFFU)); + base->FIFOWR = data | control; +} + +/*! + * brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback Callback function. + * param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + /* check 'base' */ + assert(NULL != base); + /* check 'handle' */ + assert(NULL != handle); + + uint32_t instance; + spi_to_flexcomm_t handler; + + /* get flexcomm instance by 'base' param */ + instance = SPI_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Initialize the handle */ + if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) + { + handler.spi_master_handler = SPI_MasterTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + } + else + { + handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + } + + handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); + /* in slave mode, the sselNum is not important */ + handle->sselNum = (uint8_t)(g_configs[instance].sselNum); + handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->callback = callback; + handle->userData = userData; + + /* Enable SPI NVIC */ + (void)EnableIRQ(s_spiIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * param base SPI base pointer + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Timeout The transfer timed out and was aborted. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + uint32_t instance; + uint32_t tx_ctrl = 0U, last_ctrl = 0U; + uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; + uint32_t toReceiveCount = 0; + uint8_t *txData, *rxData; + uint32_t fifoDepth; +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif + + /* check params */ + assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + fifoDepth = SPI_FIFO_DEPTH(base); + txData = xfer->txData; + rxData = xfer->rxData; + txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; + rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; + + instance = SPI_GetInstance(base); + dataWidth = (uint32_t)(g_configs[instance].dataWidth); + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) + { + return kStatus_InvalidArgument; + } + + /* clear tx/rx errors and empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); + /* set width of data - range asserted at entry */ + tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + /* end of transfer */ + last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + /* last index of loop */ + while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) + { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif + /* if rxFIFO is not empty */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (rxRemainingBytes != 0U) + { + *(rxData++) = (uint8_t)tmp32; + rxRemainingBytes--; + /* read 16 bits at once */ + if (dataWidth > 8U) + { + *(rxData++) = (uint8_t)(tmp32 >> 8); + rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + toReceiveCount -= 1U; + } + /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) + { + /* txBuffer is not empty */ + if (txRemainingBytes != 0U) + { + tmp32 = *(txData++); + txRemainingBytes--; + /* write 16 bit at once */ + if (dataWidth > 8U) + { + tmp32 |= ((uint32_t)(*(txData++))) << 8U; + txRemainingBytes--; + } + if (txRemainingBytes == 0U) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + toReceiveCount += 1U; + } + } + /* wait if TX FIFO of previous transfer is not empty */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + /* check params */ + assert( + !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); + if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) + { + return kStatus_InvalidArgument; + } + + /* Check if SPI is busy */ + if (handle->state == (uint32_t)kStatus_SPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + /* set count */ + handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; + handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; + handle->totalByteCount = xfer->dataSize; + /* other options */ + handle->toReceiveCount = 0; + handle->configFlags = xfer->configFlags; + /* Set the SPI state to busy */ + handle->state = (uint32_t)kStatus_SPI_Busy; + /* clear FIFOs when transfer starts */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * param base SPI base pointer + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer != NULL); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer != NULL); + assert(handle != NULL); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +/*! + * brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint32_t)kStatus_SPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->rxRemainingBytes; + return kStatus_Success; +} + +/*! + * brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupt requests*/ + base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); + /* Empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + + handle->state = (uint32_t)kStatus_SPI_Idle; + handle->txRemainingBytes = 0U; + handle->rxRemainingBytes = 0U; +} + +static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) +{ + uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; + bool loopContinue; + uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); + size_t txRemainingBytes; + size_t rxRemainingBytes; + uint8_t toReceiveCount; + + /* check params */ + assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); + + fifoDepth = SPI_FIFO_DEPTH(base); + /* select slave to talk with */ + tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); + /* set width of data */ + tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + /* end of transfer */ + last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + do + { + loopContinue = false; + + /* rxFIFO is not empty */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (handle->rxRemainingBytes != 0U) + { + /* low byte must go first */ + *(handle->rxData++) = (uint8_t)tmp32; + handle->rxRemainingBytes--; + /* read 16 bits at once */ + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) + { + *(handle->rxData++) = (uint8_t)(tmp32 >> 8); + handle->rxRemainingBytes--; + } + } + + /* decrease number of data expected to receive */ + handle->toReceiveCount -= 1; + loopContinue = true; + } + + /* - txFIFO is not full + * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO + * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer + */ + txRemainingBytes = handle->txRemainingBytes; + rxRemainingBytes = handle->rxRemainingBytes; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || + (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) + { + /* txBuffer is not empty */ + if ((txRemainingBytes != 0U) && (handle->txData != NULL)) + { + /* low byte must go first */ + tmp32 = *(handle->txData++); + handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; + /* write 16 bit at once */ + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) + { + tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; + handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; + } + /* last transfer */ + if (handle->txRemainingBytes == 0U) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + /* increase number of expected data to receive */ + handle->toReceiveCount += 1; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + loopContinue = true; + } + } while (loopContinue); +} + +/*! + * brief Interrupts the handler for the SPI. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert((NULL != base) && (NULL != handle)); + size_t txRemainingBytes; + uint8_t toReceiveCount; + + /* IRQ behaviour: + * - first interrupt is triggered by empty txFIFO. The transfer function + * then tries empty rxFIFO and fill txFIFO interleaved that results to + * strategy to process as many items as possible. + * - the next IRQs can be: + * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. + * txIRQ from empty txFIFO which requires to refill txFIFO. + * - last interrupt is triggered by empty txFIFO. The last state is + * known by empty rxBuffer and txBuffer. If there is nothing to receive + * or send - both operations have been finished and interrupts can be + * disabled. + */ + + /* Data to send or read or expected to receive */ + if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) + { + /* Transmit or receive data */ + SPI_TransferHandleIRQInternal(base, handle); + /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and + * enable txIRQ to confirm when txFIFO becomes empty */ + if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) + { + base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; + } + else + { + uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); + /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, + * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) + { + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; + } + /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. + * Cannot clear rxFIFO, txFIFO might be still active */ + if (rxRemainingCount == 0U) + { + txRemainingBytes = handle->txRemainingBytes; + if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && + (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) + { + base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | + SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); + } + } + else + { + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); + } + } + } + } + else + { + /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; + base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | + SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); + /* set idle state and call user callback */ + handle->state = (uint32_t)kStatus_SPI_Idle; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, handle->state, handle->userData); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..2320e574cc91d57b5b3ad98719c0b663fbf8683d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPI_H_ +#define _FSL_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI driver version. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) +#define SPI_CTRLMASK (0xFFFF0000U) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) +#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) +#define SPI_DEASSERT_ALL (0xF0000UL) + +#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) + +#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) +#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief SPI transfer option.*/ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ +} spi_xfer_option_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief txFIFO watermark values */ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ + kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ + kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ + kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ + kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ + kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ + kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ + kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ +} spi_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ + kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ + kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ + kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ + kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ + kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ + kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ + kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ +} spi_rxfifo_watermark_t; + +/*! @brief Transfer data width */ +typedef enum _spi_data_width +{ + kSPI_Data4Bits = 3, /*!< 4 bits data width */ + kSPI_Data5Bits = 4, /*!< 5 bits data width */ + kSPI_Data6Bits = 5, /*!< 6 bits data width */ + kSPI_Data7Bits = 6, /*!< 7 bits data width */ + kSPI_Data8Bits = 7, /*!< 8 bits data width */ + kSPI_Data9Bits = 8, /*!< 9 bits data width */ + kSPI_Data10Bits = 9, /*!< 10 bits data width */ + kSPI_Data11Bits = 10, /*!< 11 bits data width */ + kSPI_Data12Bits = 11, /*!< 12 bits data width */ + kSPI_Data13Bits = 12, /*!< 13 bits data width */ + kSPI_Data14Bits = 13, /*!< 14 bits data width */ + kSPI_Data15Bits = 14, /*!< 15 bits data width */ + kSPI_Data16Bits = 15, /*!< 16 bits data width */ +} spi_data_width_t; + +/*! @brief Slave select */ +typedef enum _spi_ssel +{ + kSPI_Ssel0 = 0, /*!< Slave select 0 */ + kSPI_Ssel1 = 1, /*!< Slave select 1 */ + kSPI_Ssel2 = 2, /*!< Slave select 2 */ + kSPI_Ssel3 = 3, /*!< Slave select 3 */ +} spi_ssel_t; + +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) + kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), +#else + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), +#endif + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +} spi_slave_config_t; + +/*! @brief SPI transfer status.*/ +enum +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ + kStatus_SPI_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ + kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ +}; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ + kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_statusflags +{ + kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ + kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ + kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ + kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ +}; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ + size_t dataSize; /*!< Transfer bytes */ +} spi_transfer_t; + +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + +/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ +typedef struct _spi_config +{ + spi_data_width_t dataWidth; + spi_ssel_t sselNum; +} spi_config_t; + +/*! @brief Master handle type */ +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle type */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI slave callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ + volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count + and sent count should be the same to complete the transfer, if the sent count is + x and the received count is y, toReceiveCount is x-y. */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ + uint32_t configFlags; /*!< Additional option to control transfer */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enable or disable the SPI Master or Slave + * @param base SPI base pointer + * @param enable or disable ( true = enable, false = disable) + */ +static inline void SPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= SPI_CFG_ENABLE_MASK; + } + else + { + base->CFG &= ~SPI_CFG_ENABLE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. + */ +static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFOSTAT; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENSET = irqs; +} + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENCLR = irqs; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA request from SPI txFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable); + +/*! + * @brief Enables the DMA request from SPI rxFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ +/*! + * @brief Returns the configurations. + * + * @param base SPI peripheral address. + * @return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base); + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudrate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + * @param configFlags transfer configuration options @ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +static inline uint32_t SPI_ReadData(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFORD; +} + +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + return SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); +} + +/*! + * @brief SPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..6182f9952e1748d68701beb4e970602d00ff3ee6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" +#endif + +/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; +} + +static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) +{ + *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); + /* set width of data - range asserted at entry */ + *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); +} + +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) +{ + if (config->dataWidth > kSPI_Data8Bits) + { + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); + } + else + { + *txLastWord = xfer->txData[xfer->dataSize - 1U]; + } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); +} + +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +{ + uint32_t instance = SPI_GetInstance(base); + uint32_t dummydata = (uint32_t)s_dummyData[instance]; + dummydata |= (uint32_t)s_dummyData[instance] << 8U; + + dummy->word = dummydata; + dummy->lastWord = dummydata; + + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (~(uint32_t)kSPI_FrameAssert); +} + +/*! + * brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback User callback function called at the end of a transfer. + * param userData User data for callback. + * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + uint32_t instance; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = SPI_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set spi base to handle */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle */ + handle->state = (uint8_t)kSPI_Idle; + + /* Set handle to global state */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); + + return kStatus_Success; +} + +/*! + * brief Perform a non-blocking SPI transfer using DMA. + * + * note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + * param xfer Pointer to dma transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + assert(!((NULL == handle) || (NULL == xfer))); + + uint32_t instance; + status_t result = kStatus_Success; + spi_config_t *spi_config_p; + uint32_t address; + + if ((NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + + /* Byte size is zero. */ + if (xfer->dataSize == 0U) + { + return kStatus_InvalidArgument; + } + /* cannot get instance from base address */ + instance = SPI_GetInstance(base); + + /* Check if the device is busy */ + if (handle->state == (uint8_t)kSPI_Busy) + { + return kStatus_SPI_Busy; + } + else + { + /* Clear FIFOs before transfer. */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + + dma_transfer_config_t xferConfig = {0}; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + + handle->state = (uint8_t)kSPI_Busy; + handle->transferSize = xfer->dataSize; + + /* receive */ + SPI_EnableRxDMA(base, true); + address = (uint32_t)&base->FIFORD; + if (xfer->rxData != NULL) + { + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + } + else + { + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + } + (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + DMA_StartTransfer(handle->rxHandle); + + /* transmit */ + SPI_EnableTxDMA(base, true); + address = (uint32_t)&base->FIFOWR; + if (xfer->txData != NULL) + { + if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) + { + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + (uint32_t *)address, NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) + { + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (uint32_t *)address, NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + } + + handle->txInProgress = true; + uint32_t tmpData = 0U; + uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; + XferToFifoWR(xfer, &tmpData); + SpiConfigToFifoWR(spi_config_p, &tmpData); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmpData &= (~(uint32_t)kSPI_FrameAssert); + *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); + } + + DMA_StartTransfer(handle->txHandle); + } + + return result; +} + +/*! + * brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI base pointer + * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * param transfer A pointer to the spi_half_duplex_transfer_t structure. + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert((xfer != NULL) && (handle != NULL)); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +/*! + * brief Abort a SPI transfer using DMA. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + assert(NULL != handle); + + /* Stop tx transfer first */ + DMA_AbortTransfer(handle->txHandle); + /* Then rx transfer */ + DMA_AbortTransfer(handle->rxHandle); + + /* Set the handle state */ + handle->txInProgress = false; + handle->rxInProgress = false; + handle->state = (uint8_t)kSPI_Idle; +} + +/*! + * brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * param base SPI peripheral base address. + * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * param count A number of bytes transferred by the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); + + *count = handle->transferSize - bytes; + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..6adc6c866814372c5295a6354b72d931012cac46 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_spi_dma.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPI_DMA_H_ +#define _FSL_SPI_DMA_H_ + +#include "fsl_dma.h" +#include "fsl_spi.h" + +/*! + * @addtogroup spi_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI DMA driver version 2.1.1. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +typedef struct _spi_dma_handle spi_dma_handle_t; + +/*! @brief SPI DMA callback called at the end of transfer. */ +typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _spi_dma_handle +{ + volatile bool txInProgress; /*!< Send transfer finished */ + volatile bool rxInProgress; /*!< Receive transfer finished */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ + spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ + uint32_t state; /*!< Internal state of SPI DMA transfer */ + size_t transferSize; /*!< Bytes need to be transfer */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param xfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Initialize the SPI slave DMA handle. + * + * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferDMA(base, handle, xfer); +} + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); + +/*! + * @brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Gets the slave DMA transfer remaining bytes. + * + * This function gets the slave DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.c new file mode 100644 index 0000000000000000000000000000000000000000..1d0dd9ccf64dff5aa1695cb6db6d425c7ffd83d1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.c @@ -0,0 +1,203 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sysctl.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sysctl" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base SYSCTL peripheral base address. + * @return Instance number. + */ +static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); + +/*! + * @brief Enable SYSCTL write protect + * + * @param base SYSCTL peripheral base address. + * @param regAddr register address + * @param value value to write. + */ +static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief SYSCTL base address array name */ +static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief SYSCTL clock array name */ +static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) +{ + base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; + *regAddr = value; + base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; +} + +static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) +{ + uint8_t instance = 0; + + while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_sysctlBase)); + + return instance; +} + +/*! + * @brief SYSCTL initial + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Init(SYSCTL_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SYSCTL clock. */ + CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); +#endif +} + +/*! + * @brief SYSCTL deinit + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Deinit(SYSCTL_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SYSCTL clock. */ + CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); +#endif +} + +/*! + * @brief SYSCTL share set configure for separate signal + * + * @param base Base address of the SYSCTL peripheral + * @param flexCommIndex index of flexcomm,reference _sysctl_share_src + * @param setIndex share set for sck, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) +{ + uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; + + tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); + tempReg |= (set + 1U) << (uint32_t)signal; + + SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); +} + +/*! + * @brief SYSCTL share set configure for flexcomm + * + * @param base Base address of the SYSCTL peripheral. + * @param flexCommIndex index of flexcomm, reference _sysctl_share_src + * @param sckSet share set for sck,reference _sysctl_share_set_index + * @param wsSet share set for ws, reference _sysctl_share_set_index + * @param dataInSet share set for data in, reference _sysctl_share_set_index + * @param dataOutSet share set for data out, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetFlexcommShareSet( + SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) +{ + uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; + + tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | + SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); + tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | + SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); + + SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); +} + +/*! + * @brief SYSCTL share set source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source for this share set,reference _sysctl_share_src + * @param wsShareSrc ws source for this share set,reference _sysctl_share_src + * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src + * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, + uint32_t setIndex, + uint32_t sckShareSrc, + uint32_t wsShareSrc, + uint32_t dataInShareSrc, + uint32_t dataOutShareSrc) +{ + uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; + + /* WS,SCK,DATA IN */ + tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | + SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); + tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | + SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); + + /* data out */ + tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | + SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | + SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); + tempReg |= dataOutShareSrc; + + SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); +} + +/*! + * @brief SYSCTL sck source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src + * + */ +void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, + uint32_t setIndex, + sysctl_sharedctrlset_signal_t signal, + uint32_t shareSrc) +{ + uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; + + if (signal == kSYSCTL_SharedCtrlSignalDataOut) + { + tempReg |= 1UL << ((uint32_t)signal + shareSrc); + } + else + { + tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); + tempReg |= shareSrc << (uint32_t)signal; + } + + SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.h new file mode 100644 index 0000000000000000000000000000000000000000..0a1be88469c86e44cc8fd63c3bd89d388e61ba58 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_sysctl.h @@ -0,0 +1,186 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SYSCTL_H_ +#define _FSL_SYSCTL_H_ + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup sysctl + * @{ + */ + +/*! @file */ +/*! @file fsl_sysctl.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group sysctl driver version for SDK */ +#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ +/*@}*/ + +/*! @brief SYSCTL share set*/ +enum _sysctl_share_set_index +{ + kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ + kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ +}; + +/*! @brief SYSCTL flexcomm signal */ +typedef enum _sysctl_fcctrlsel_signal +{ + kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ + kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ + kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ +} sysctl_fcctrlsel_signal_t; + +/*! @brief SYSCTL flexcomm index*/ +enum _sysctl_share_src +{ + kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ + kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ + kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ + kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ + kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ + kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ + kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ +}; + +/*! @brief SYSCTL shared data out mask */ +enum _sysctl_dataout_mask +{ + kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ + kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ + kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ + kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ + kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ + kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ + kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ +}; + +/*! @brief SYSCTL flexcomm signal */ +typedef enum _sysctl_sharedctrlset_signal +{ + kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ + kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ + kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ +} sysctl_sharedctrlset_signal_t; +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief SYSCTL initial + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Init(SYSCTL_Type *base); + +/*! + * @brief SYSCTL deinit + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Deinit(SYSCTL_Type *base); + +/* @} */ + +/*! + * @name SYSCTL share signal configure + * @{ + */ + +/*! + * @brief SYSCTL share set configure for flexcomm + * + * @param base Base address of the SYSCTL peripheral. + * @param flexCommIndex index of flexcomm, reference _sysctl_share_src + * @param sckSet share set for sck,reference _sysctl_share_set_index + * @param wsSet share set for ws, reference _sysctl_share_set_index + * @param dataInSet share set for data in, reference _sysctl_share_set_index + * @param dataOutSet share set for data out, reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, + uint32_t flexCommIndex, + uint32_t sckSet, + uint32_t wsSet, + uint32_t dataInSet, + uint32_t dataOutSet); + +/*! + * @brief SYSCTL share set configure for separate signal + * + * @param base Base address of the SYSCTL peripheral + * @param flexCommIndex index of flexcomm,reference _sysctl_share_src + * @param signal FCCTRLSEL signal shift + * @param set share set for sck, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); + +/*! + * @brief SYSCTL share set source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source for this share set,reference _sysctl_share_src + * @param wsShareSrc ws source for this share set,reference _sysctl_share_src + * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src + * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, + uint32_t setIndex, + uint32_t sckShareSrc, + uint32_t wsShareSrc, + uint32_t dataInShareSrc, + uint32_t dataOutShareSrc); + +/*! + * @brief SYSCTL sck source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param signal FCCTRLSEL signal shift + * @param shareSrc sck source fro this share set,reference _sysctl_share_src + * + */ +void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, + uint32_t setIndex, + sysctl_sharedctrlset_signal_t signal, + uint32_t shareSrc); + +/* @} */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..1bbf23587721a4b659f480875271ca75ef6cab09 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.c @@ -0,0 +1,1160 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +/*! + * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` + */ +typedef union usart_to_flexcomm +{ + flexcomm_usart_irq_handler_t usart_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} usart_to_flexcomm_t; + +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + uint32_t i; + + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); + return i; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | + USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + if (config->enableMode32k) + { + if ((9600U % config->baudRate_Bps) == 0U) + { + base->BRG = 9600U / config->baudRate_Bps; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->enableMode32k = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; + config->enableHardwareFlowControl = false; +} + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) + { + if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1U; + } + } + else + { + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8U; osrval--) + { + brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; + if (brgval > 0xFFFFU) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated OSR and BRG value */ + baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff > ((baudrate_Bps / 100U) * 3U)) + { + return kStatus_USART_BaudrateNotSupport; + } + + /* value over range */ + if (best_brgval > 0xFFFFU) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * param base USART peripheral base address. + * param baudRate_Bps USART baudrate to be set.. + * param enableMode32k true is 32k mode, false is normal mode. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + base->CFG &= ~(USART_CFG_ENABLE_MASK); + if (enableMode32k) + { + base->CFG |= USART_CFG_MODE32K_MASK; + if ((9600U % baudRate_Bps) == 0U) + { + base->BRG = 9600U / baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + base->CFG &= ~(USART_CFG_MODE32K_MASK); + result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + base->CFG |= USART_CFG_ENABLE_MASK; + return result; +} + +/*! + * brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base USART peripheral base address. + * param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set USART 9-bit mode, disable parity. */ + temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); + temp |= (uint32_t)USART_CFG_DATALEN(0x2U); + base->CFG = temp; + } + else + { + /* Set USART to 8-bit mode. */ + base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); + base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); + } +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base USART peripheral base address. + * param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address) +{ + assert(base != NULL); + base->FIFOWR = ((uint32_t)address | 0x100UL); +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_InvalidArgument Invalid argument. + * retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + /* Check whether txFIFO is enabled */ + if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return kStatus_InvalidArgument; + } + for (; length > 0U; length--) + { + /* Loop until txFIFO get some space for new data */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) + { + return kStatus_Fail; + } + for (; length > 0U; length--) + { + /* loop until rxFIFO have some data to read */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) +#else + while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) +#endif + { + } +#if UART_RETRY_TIMES + if (waitTimes == 0U) + { + status = kStatus_USART_Timeout; + break; + } +#endif + /* check rxFIFO statusFlag */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + status = kStatus_USART_RxError; + break; + } + /* check receive statusFlag */ + statusFlag = base->STAT; + /* Clear all status flags */ + base->STAT |= statusFlag; + if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) + { + status = kStatus_USART_ParityError; + } + if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) + { + status = kStatus_USART_FramingError; + } + if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) + { + status = kStatus_USART_NoiseError; + } + + if (kStatus_Success == status) + { + *data = (uint8_t)base->FIFORD; + data++; + } + else + { + break; + } + } + return status; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + + uint32_t instance = 0; + usart_to_flexcomm_t handler; + handler.usart_master_handler = USART_TransferHandleIRQ; + + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the + * handle value. */ + uint32_t interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kUSART_TxBusy; + /* Enable transmiter interrupt and the previously disabled interrupt. */ + USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize - + ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t interruptMask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) + { + return kStatus_InvalidArgument; + } + + /* Enable address detect when address match is enabled. */ + if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) + { + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable IRQ, protect ring buffer. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kUSART_RxBusy; + } + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up + * the handle value. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); + } + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + bool sendEnabled = (handle->txDataSize != 0U); + uint8_t rxdata; + size_t tmpsize; + + /* If RX overrun. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || + (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) + { + /* Receive data */ + if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) + { + /* Clear address detect when RXFIFO has data. */ + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize != 0U) + { + rxdata = (uint8_t)base->FIFORD; + *handle->rxData = rxdata; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + if (0U == handle->rxDataSize) + { + if (NULL == handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = (uint8_t)kUSART_RxIdle; + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer != NULL) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + rxdata = (uint8_t)base->FIFORD; + handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; + /* Increase handle->rxRingBufferHead. */ + if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0U; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + + base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; + } + } + } + + /* Tx idle and the interrupt is enabled. */ + if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kUSART_TxIdle; + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + tmpsize = handle->rxDataSize; + + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) + { + base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..68467e7e2096ec417eba455bfd8f22ae52cc1586 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart.h @@ -0,0 +1,866 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the USART driver. */ +enum +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ + bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for usart interrupt handler. */ +typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * @param base USART peripheral base address. + * @param baudRate_Bps USART baudrate to be set.. + * @param enableMode32k true is 32k mode, false is normal mode. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base USART peripheral base address. + * @param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable); + +/*! + * @brief Set the USART slave address. + * + * This function configures the address for USART module that works as slave in 9-bit data mode. When the address + * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is + * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This + * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. + * To un-address a slave, just send an address frame with unmatched address. + * + * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) +{ + /* Configure match address. */ + base->ADDR = (uint32_t)address; +} + +/*! + * @brief Enable the USART match address feature. + * + * @param base USART peripheral base address. + * @param match true to enable match address, false to disable. + */ +static inline void USART_EnableMatchAddress(USART_Type *base, bool match) +{ + /* Configure match address enable bit. */ + if (match) + { + base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + else + { + base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return base->FIFOSTAT; +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENSET = mask & 0xFUL; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENCLR = mask & 0xFUL; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} + +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); +} +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return (uint8_t)base->FIFORD; +} + +/*! + * @brief Gets the rx FIFO data count. + * + * @param base USART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t USART_GetRxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base USART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t USART_GetTxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); +} + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..60c2d5284c50ee0103f1188f94ae14b2d5431d14 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.c @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_dma.h" +#include "fsl_flexcomm.h" +#include "fsl_usart_dma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/*! @brief Typedef for usart DMA interrupt handler. */ +typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); + +/*base, false); + + /* Enable tx idle interrupt */ + usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; +} + +static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) +{ + assert(handle != NULL); + assert(param != NULL); + + usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + USART_EnableRxDMA(usartPrivateHandle->base, false); + + usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; + + if (usartPrivateHandle->handle->callback != NULL) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, + usartPrivateHandle->handle->userData); + } +} + +/*! + * brief Initializes the USART handle which is used in transactional functions. + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txDmaHandle User-requested DMA handle for TX DMA transfer. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + uint32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* assign 'base' and 'handle' */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* set tx/rx 'idle' state */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ + usart_dma_to_flexcomm_t handler; + handler.usart_dma_handler = USART_TransferDMAHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + /* Enable NVIC IRQ. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + /* Configure TX. */ + if (txDmaHandle != NULL) + { + DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle != NULL) + { + DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t address = (uint32_t)&base->FIFOWR; + + /* If previous TX not finished. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + status = kStatus_USART_TxBusy; + } + else + { + handle->txState = (uint8_t)kUSART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Enable DMA request from txFIFO */ + USART_EnableTxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, + kDMA_MemoryToPeripheral, NULL); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + DMA_StartTransfer(handle->txDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t address = (uint32_t)&base->FIFORD; + + /* If previous RX not finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + status = kStatus_USART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kUSART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Enable DMA request from rxFIFO */ + USART_EnableRxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, + kDMA_PeripheralToMemory, NULL); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + DMA_StartTransfer(handle->rxDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Get the number of bytes that have been sent. + * + * This function gets the number of bytes that have been sent. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Sent bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ + handle->txState = (uint8_t)kUSART_TxIdle; + + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Invoke callback */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..901ee115e8806ddacf7fb551065f317eb087f23f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_usart_dma.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_DMA_H_ +#define _FSL_USART_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" +#include "fsl_usart.h" + +/*! + * @addtogroup usart_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART dma driver version. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_dma_handle usart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, + usart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART DMA handle + */ +struct _usart_dma_handle +{ + USART_Type *base; /*!< UART peripheral base address. */ + + usart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle which is used in transactional functions. + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been sent. + * + * This function gets the number of bytes that have been sent. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Sent bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.c new file mode 100644 index 0000000000000000000000000000000000000000..208b34cf9dfc2dc0e97789a8228da5a443b5f645 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_utick.h" +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) +#include "fsl_power.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base UTICK peripheral base address + * + * @return The UTICK instance + */ +static uint32_t UTICK_GetInstance(UTICK_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UTICK handle. */ +static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; +/* Array of UTICK peripheral base address. */ +static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; +/* Array of UTICK IRQ number. */ +static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UTICK clock name. */ +static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) +/*! @brief Pointers to UTICK resets for each instance. */ +static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; +#endif + +/* UTICK ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; +#else +static utick_isr_t s_utickIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t UTICK_GetInstance(UTICK_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) + { + if (s_utickBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_utickBases)); + + return instance; +} + +/*! + * brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * param base UTICK peripheral base address. + * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) +{ + uint32_t instance; + + /* Get instance from peripheral base address. */ + instance = UTICK_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_utickHandle[instance] = cb; +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ + !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) + EnableDeepSleepIRQ(s_utickIRQ[instance]); +#else + (void)EnableIRQ(s_utickIRQ[instance]); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ + base->CTRL = count | UTICK_CTRL_REPEAT(mode); +} + +/*! + * brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable utick clock */ + CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) + RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) + /* Power up Watchdog oscillator*/ + POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); +#endif + + s_utickIsr = UTICK_HandleIRQ; +} + +/*! + * brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base) +{ + /* Turn off utick */ + base->CTRL = 0; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable utick clock */ + CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif +} + +/*! + * brief Get Status Flags. + * + * This returns the status flag + * + * param base UTICK peripheral base address. + * return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base) +{ + return (base->STAT); +} + +/*! + * brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * param base UTICK peripheral base address. + * return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base) +{ + base->STAT = UTICK_STAT_INTR_MASK; +} + +/*! + * brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * param base UTICK peripheral base address. + * param cb callback scheduled for this instance of UTICK + * return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) +{ + UTICK_ClearStatusFlags(base); + if (cb != NULL) + { + cb(); + } +} + +#if defined(UTICK0) +void UTICK0_DriverIRQHandler(void); +void UTICK0_DriverIRQHandler(void) +{ + s_utickIsr(UTICK0, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK1) +void UTICK1_DriverIRQHandler(void); +void UTICK1_DriverIRQHandler(void) +{ + s_utickIsr(UTICK1, s_utickHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK2) +void UTICK2_DriverIRQHandler(void); +void UTICK2_DriverIRQHandler(void) +{ + s_utickIsr(UTICK2, s_utickHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.h new file mode 100644 index 0000000000000000000000000000000000000000..800cde8ce25f5efbf24bf3cefee21a4a39b8fc62 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_utick.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_UTICK_H_ +#define _FSL_UTICK_H_ + +#include "fsl_common.h" +/*! + * @addtogroup utick + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UTICK driver version 2.0.4. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief UTICK timer operational mode. */ +typedef enum _utick_mode +{ + kUTICK_Onetime = 0x0U, /*!< Trigger once*/ + kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ +} utick_mode_t; + +/*! @brief UTICK callback function. */ +typedef void (*utick_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base); + +/*! + * @brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * @param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base); +/*! + * @brief Get Status Flags. + * + * This returns the status flag + * + * @param base UTICK peripheral base address. + * @return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base); +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * @param base UTICK peripheral base address. + * @return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base); + +/*! + * @brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * @param base UTICK peripheral base address. + * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * @return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); +/*! + * @brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base UTICK peripheral base address. + * @param cb callback scheduled for this instance of UTICK + * @return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.c new file mode 100644 index 0000000000000000000000000000000000000000..d0ab8ebf3aad42d44bd41b63647601dedd02a098 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.c @@ -0,0 +1,292 @@ +/* + * Copyright 2019-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_vref.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.vref_1" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base VREF peripheral base address + * + * @return The VREF instance + */ +static uint32_t VREF_GetInstance(VREF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to VREF bases for each instance. */ +static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to VREF clocks for each instance. */ +static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t VREF_GetInstance(VREF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++) + { + if (s_vrefBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_vrefBases)); + + return instance; +} + +/*! + * brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all other VREF driver functions, read/write registers, and + * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters + * and how to call the VREF_Init function by passing in these parameters. + * code + * vref_config_t vrefConfig; + * VREF_GetDefaultConfig(VREF, &vrefConfig); + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * VREF_Init(VREF, &vrefConfig); + * endcode + * + * param base VREF peripheral address. + * param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate clock for VREF */ + CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Enable low power bandgap at first. */ + tmp32 = VREF_CSR_LPBGEN_MASK | VREF_CSR_LPBG_BUF_EN_MASK | VREF_CSR_VRSEL(config->vrefSel); + + /* Configure buffer mode. */ + switch (config->bufferMode) + { + case kVREF_ModeBandgapOnly: + break; + case kVREF_ModeLowPowerBuffer: + tmp32 |= VREF_CSR_BUF21EN_MASK; + break; + case kVREF_ModeHighPowerBuffer: + tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); + break; + default: + assert(false); + break; + } + + /* Enable internal voltage regulator */ + if (config->enableInternalVoltageRegulator) + { + /* Enable internal voltage regulator to provide the optimum VREF performance. */ + tmp32 |= VREF_CSR_REGEN_MASK | VREF_CSR_CHOPEN_MASK | VREF_CSR_ICOMPEN_MASK; + base->CSR = tmp32; + /* After enabling low power bandgap, delay 20 us. */ + SDK_DelayAtLeastUs(20U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + /* Enable high accurancy bandgap for vref output. */ + if (config->enableVrefOut) + { + base->CSR |= VREF_CSR_HCBGEN_MASK; + } + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + else + { + /* Enable high accurancy bandgap for vref output. */ + if (config->enableVrefOut) + { + tmp32 |= VREF_CSR_HCBGEN_MASK; + base->CSR = tmp32; + /* Wait until internal voltage stable */ + while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) + { + } + } + else + { + base->CSR = tmp32; + } + } +} + +/*! + * brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * This is an example. + * code + * vref_config_t vrefUserConfig; + * VREF_GetDefaultConfig(VREF, &vrefUserConfig); + * VREF_Init(VREF, &vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * endcode + * + * param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock for VREF */ + CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to default values. + * This is an example. + * code + * config->bufferMode = kVREF_ModeHighPowerBuffer; + * config->enableInternalVoltageRegulator = true; + * config->enableVrefOut = true; + * config->vrefSel = kVREF_InternalBandgap; + * endcode + * + * param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->bufferMode = kVREF_ModeHighPowerBuffer; + config->enableInternalVoltageRegulator = true; + config->enableVrefOut = true; + config->vrefSel = kVREF_InternalBandgap; +} + +/*! + * brief Sets a TRIM value for the accurate 1.0V bandgap output. + * + * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue) +{ + uint32_t tmp32 = base->UTRIM; + + tmp32 &= (~VREF_UTRIM_VREFTRIM_MASK); + tmp32 |= VREF_UTRIM_VREFTRIM(trimValue); + + base->UTRIM = tmp32; + + if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) + { + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + else + { + while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) + { + } + } +} + +/*! + * brief Sets a TRIM value for the accurate buffered VREF output. + * + * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 + * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. + * + * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the + * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). + */ +void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) +{ + uint32_t tmp32 = base->UTRIM; + + if (VREF_CSR_BUF21EN_MASK == (base->CSR & VREF_CSR_BUF21EN_MASK)) + { + tmp32 &= (~VREF_UTRIM_TRIM2V1_MASK); + tmp32 |= VREF_UTRIM_TRIM2V1(trim21Value); + } + + base->UTRIM = tmp32; + + if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) + { + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + else + { + while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) + { + } + } +} + +/*! + * brief Reads the VREF trim value.. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) + * + * param base VREF peripheral address. + * return 6-bit value of trim setting. + */ +uint8_t VREF_GetVrefTrimVal(VREF_Type *base) +{ + uint8_t trimValue; + + trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_VREFTRIM_MASK) >> VREF_UTRIM_VREFTRIM_SHIFT); + + return trimValue; +} + +/*! + * brief Reads the VREF 2.1V trim value.. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), + * + * param base VREF peripheral address. + * return 4-bit value of trim setting. + */ +uint8_t VREF_GetTrim21Val(VREF_Type *base) +{ + uint8_t trimValue; + + trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_TRIM2V1_MASK) >> VREF_UTRIM_TRIM2V1_SHIFT); + + return trimValue; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.h new file mode 100644 index 0000000000000000000000000000000000000000..51ff4bb927223b176db881f7596c7a292a8f5498 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_vref.h @@ -0,0 +1,175 @@ +/* + * Copyright 2019-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_VREF_H_ +#define _FSL_VREF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup vref + * @{ + */ + +/****************************************************************************** + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +/*@}*/ + +/*! @brief VREF buffer modes. */ +typedef enum _vref_buffer_mode +{ + kVREF_ModeBandgapOnly = 0U, /*!< Bandgap enabled/standby. */ + kVREF_ModeLowPowerBuffer = 1U, /*!< High-power buffer mode enabled */ + kVREF_ModeHighPowerBuffer = 2U /*!< Low-power buffer mode enabled */ +} vref_buffer_mode_t; + +/*! @brief Voltage reference selection. */ +typedef enum _vref_voltage_reference_sel +{ + kVREF_InternalBandgap = 0U, /*!< Internal bandgap. */ + kVREF_LowPowerBuffed1v = 1U, /*!< Low power buffered 1v. */ + kVREF_LowPowerBufferMode = 2U, /*!< Low-power buffer mode enabled. */ +} vref_voltage_reference_sel_t; + +/*! @brief The description structure for the VREF module. */ +typedef struct _vref_config +{ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ + bool enableInternalVoltageRegulator; /*!< Provide additional supply noise rejection. */ + bool enableVrefOut; /*!< Enable the VREF supply voltage on VREF_OUT. */ + vref_voltage_reference_sel_t vrefSel; /*!< Control voltage reference selection */ +} vref_config_t; + +/****************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all other VREF driver functions, read/write registers, and + * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters + * and how to call the VREF_Init function by passing in these parameters. + * @code + * vref_config_t vrefConfig; + * VREF_GetDefaultConfig(VREF, &vrefConfig); + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * VREF_Init(VREF, &vrefConfig); + * @endcode + * + * @param base VREF peripheral address. + * @param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config); + +/*! + * @brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * This is an example. + * @code + * vref_config_t vrefUserConfig; + * VREF_GetDefaultConfig(VREF, &vrefUserConfig); + * VREF_Init(VREF, &vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * @endcode + * + * @param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base); + +/*! + * @brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to default values. + * This is an example. + * @code + * config->bufferMode = kVREF_ModeHighPowerBuffer; + * config->enableInternalVoltageRegulator = true; + * config->enableVrefOut = true; + * config->vrefSel = kVREF_InternalBandgap; + * @endcode + * + * @param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config); + +/* @} */ + +/*! + * @name Trim functions + * @{ + */ + +/*! + * brief Sets a TRIM value for the accurate 1.0V bandgap output. + * + * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * brief Sets a TRIM value for the accurate buffered VREF output. + * + * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 + * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. + * + * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the + * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). + */ +void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value); + +/*! + * brief Reads the VREF trim value.. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) + * + * param base VREF peripheral address. + * return 6-bit value of trim setting. + */ +uint8_t VREF_GetVrefTrimVal(VREF_Type *base); + +/*! + * brief Reads the VREF 2.1V trim value.. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), + * + * param base VREF peripheral address. + * return 4-bit value of trim setting. + */ +uint8_t VREF_GetTrim21Val(VREF_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_VREF_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..6680148acf773a0064f88527e95829efe0761d86 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wwdt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + +#define FREQUENCY_3MHZ (3000000U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base WWDT peripheral base address + * + * @return The WWDT instance + */ +static uint32_t WWDT_GetInstance(WWDT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to WWDT bases for each instance. */ +static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to WWDT clocks for each instance. */ +static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +/*! @brief Pointers to WWDT resets for each instance. */ +static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WWDT_GetInstance(WWDT_Type *base) +{ + uint32_t instance; + uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < wwdtArrayCount; instance++) + { + if (s_wwdtBases[instance] == base) + { + break; + } + } + + assert(instance < wwdtArrayCount); + + return instance; +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * endcode + * + * param config Pointer to WWDT config structure. + * see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Enable the watch dog */ + config->enableWwdt = true; + /* Disable the watchdog timeout reset */ + config->enableWatchdogReset = false; + /* Disable the watchdog protection for updating the timeout value */ + config->enableWatchdogProtect = false; +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + /* Do not lock the watchdog oscillator */ + config->enableLockOscillator = false; +#endif + /* Windowing is not in effect */ + config->windowValue = 0xFFFFFFU; + /* Set the timeout value to the max */ + config->timeoutValue = 0xFFFFFFU; + /* No warning is provided */ + config->warningValue = 0; + /* Set clock frequency. */ + config->clockFreq_Hz = 0U; +} + +/*! + * brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * endcode + * + * param base WWDT peripheral base address + * param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) +{ + assert(NULL != config); + + uint32_t value = 0U; + uint32_t DelayUs = 0U; + uint32_t primaskValue = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the WWDT clock */ + CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the module. */ + RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it by write 1. */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; + /* Enable the watchdog reset event to affect the system in the Power Management Controller */ + PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | + WWDT_MOD_LOCK(config->enableLockOscillator); +#else + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); +#endif + /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ + if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) + { + value |= WWDT_MOD_WDINT_MASK; + } + /* Set configuration */ + primaskValue = DisableGlobalIRQ(); + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD = value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); + /* Refreshes the WWDT timer. */ + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); + /* Read counter value to wait wwdt timer start*/ + if (config->enableWwdt) + { + while (base->TV == 0xFFUL) + { + } + } + + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) + { + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(0U != config->clockFreq_Hz); + + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; + SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + base->MOD |= WWDT_MOD_WDPROTECT(1U); + } +} + +/*! + * brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the WWDT clock */ + CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} + +/*! + * brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * endcode + * param base WWDT peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) +{ + /* Clear the WDINT bit so that we don't accidentally clear it */ + uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); + + /* Clear timeout by writing a zero */ + if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) + { + reg &= ~WWDT_MOD_WDTOF_MASK; +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + } + + /* Clear warning interrupt flag by writing a one */ + if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) + { + reg |= WWDT_MOD_WDINT_MASK; + } + + base->MOD = reg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..254625349662bec6262e769e2b0ec2f645821341 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/fsl_wwdt.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_WWDT_H_ +#define _FSL_WWDT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wwdt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WWDT driver version. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WWDT configuration structure. */ +typedef struct _wwdt_config +{ + bool enableWwdt; /*!< Enables or disables WWDT */ + bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset + false: Watchdog timeout will not cause a chip reset */ + bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be + changed after counter is below warning & window values + false: Disable watchdog protect; timeout value can be changed + at any time */ +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented + Once set, this bit can only be cleared by a reset + false: Do not lock oscillator */ +#endif + uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ + uint32_t timeoutValue; /*!< Timeout value */ + uint32_t warningValue; /*!< Watchdog time counter value that will generate a + warning interrupt. Set this to 0 for no warning */ + uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ +} wwdt_config_t; + +/*! + * @brief WWDT status flags. + * + * This structure contains the WWDT status flags for use in the WWDT functions. + */ +enum _wwdt_status_flags_t +{ + kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ + kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WWDT Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * @code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * @endcode + * + * @param config Pointer to WWDT config structure. + * @see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config); + +/*! + * @brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * @code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * @endcode + * + * @param base WWDT peripheral base address + * @param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); + +/*! + * @brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * @param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base); + +/* @} */ + +/*! + * @name WWDT Functional Operation + * @{ + */ + +/*! + * @brief Enables the WWDT module. + * + * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; + * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run + * permanently. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Enable(WWDT_Type *base) +{ + base->MOD |= WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Disables the WWDT module. + * @deprecated Do not use this function. It will be deleted in next release version, for + * once the bit field of WDEN written with a 1, it can not be re-written with a 0. + * + * This function write value into WWDT_MOD register to disable the WWDT. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Disable(WWDT_Type *base) +{ + base->MOD &= ~WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Gets all WWDT status flags. + * + * This function gets all status flags. + * + * Example for getting Timeout Flag: + * @code + * uint32_t status; + * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; + * @endcode + * @param base WWDT peripheral base address + * @return The status flags. This is the logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) +{ +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + uint32_t status; + /* WDTOF is not set in case of WD reset - get info from PMC instead */ + status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); + if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) + { + status |= kWWDT_TimeoutFlag; + } + return status; +#else + return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ +} + +/*! + * @brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * @code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * @endcode + * @param base WWDT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); + +/*! + * @brief Set the WWDT warning value. + * + * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog + * interrupt. When the watchdog timer counter is no longer greater than the value defined by + * WARNINT, an interrupt will be generated after the subsequent WDCLK. + * + * @param base WWDT peripheral base address + * @param warningValue WWDT warning value. + */ +static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) +{ + base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); +} + +/*! + * @brief Set the WWDT timeout value. + * + * This function sets the timeout value. Every time a feed sequence occurs the value in the TC + * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be + * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. + * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change + * the timeout value before the watchdog counter is below the warning and window values + * will cause a watchdog reset and set the WDTOF flag. + * + * @param base WWDT peripheral base address + * @param timeoutCount WWDT timeout value, count of WWDT clock tick. + */ +static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) +{ + base->TC = WWDT_TC_COUNT(timeoutCount); +} + +/*! + * @brief Sets the WWDT window value. + * + * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. + * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog + * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer + * value) so windowing is not in effect. + * + * @param base WWDT peripheral base address + * @param windowValue WWDT window value. + */ +static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) +{ + base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); +} + +/*! + * @brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_mem_interface.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_mem_interface.h new file mode 100644 index 0000000000000000000000000000000000000000..6d99e708fc61f34ed10c9eeefaf6b4e9c9fec02c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_mem_interface.h @@ -0,0 +1,379 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MEM_INTERFACE_H_ +#define _FSL_MEM_INTERFACE_H_ + +#include "fsl_sbloader.h" +#include "fsl_common.h" + +/*! + * @addtogroup memory_interface + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Bit mask for device ID. */ +#define DEVICE_ID_MASK (0xffU) +/*! @brief Bit position of device ID. */ +#define DEVICE_ID_SHIFT 0U +/*! @brief Bit mask for group ID. */ +#define GROUP_ID_MASK (0xf00U) +/*! @brief Bit position of group ID. */ +#define GROUP_ID_SHIFT 8U + +/*! @brief Construct a memory ID from a given group ID and device ID. */ +#define MAKE_MEMORYID(group, device) \ + ((((group) << GROUP_ID_SHIFT) & GROUP_ID_MASK) | (((device) << DEVICE_ID_SHIFT) & DEVICE_ID_MASK)) +/*! @brief Get group ID from a given memory ID. */ +#define GROUPID(memoryId) (((memoryId)&GROUP_ID_MASK) >> GROUP_ID_SHIFT) + +/*! @brief Get device ID from a given memory ID. */ +#define DEVICEID(memoryId) (((memoryId)&DEVICE_ID_MASK) >> DEVICE_ID_SHIFT) + +/*! @brief Memory group definition. */ +enum +{ + kMemoryGroup_Internal = 0U, /*!< Memory belongs internal 4G memory region. */ + kMemoryGroup_External = 1U, /*!< Memory belongs external memory region. */ +}; + +/*! @brief Memory device ID definition. */ +enum +{ + /* Memory ID bitfiled definition. + | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | Reserved | INT/EXT | Type | Sub-Type | + | | 0: INT | INT: | | + | | 1: EXT | 0: NorFlash0 | 0: Internal Flash(FTFX) | + | | | | 1: QSPI | + | | | | 4: IFR | + | | | | 5: LPC FFR | + | | | | 8: SEMC | + | | | | 9: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: ExecuteOnlyRegion | 0: Internal Flash(FTFX) | + | | | | others: Unused | + | | | | | + | | | others: Unused | | + | | | | | + | | | EXT: | | + | | | 0: NandFlash | 0: SEMC | + | | | | 1: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: NorFlash/EEPROM | 0: LPSPI | + | | | | 1: LPI2C | + | | | | others: Unused | + | | | | | + | | | 2: SD/SDHC/SDXC/MMC/eMMC | 0: uSDHC SD | + | | | | 1: uSDHC MMC | + | | | | others: Unused | + | | | others: Unused | | + + INT : Internal 4G memory, including internal memory modules, and XIP external memory modules. + EXT : Non-XIP external memory modules. + */ + kMemoryInternal = MAKE_MEMORYID(kMemoryGroup_Internal, 0U), /*!< Internal memory (include all on chip memory) */ + kMemoryQuadSpi0 = MAKE_MEMORYID(kMemoryGroup_Internal, 1U), /*!< Qsuad SPI memory 0 */ + kMemoryIFR0 = + MAKE_MEMORYID(kMemoryGroup_Internal, 4U), /*!< Nonvolatile information register 0. Only used by SB loader. */ + kMemoryFFR = MAKE_MEMORYID(kMemoryGroup_Internal, 5U), /*!< LPCc040hd flash FFR region. */ + kMemorySemcNor = MAKE_MEMORYID(kMemoryGroup_Internal, 8U), /*!< SEMC Nor memory */ + kMemoryFlexSpiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 9U), /*!< Flex SPI Nor memory */ + kMemorySpifiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 0xAU), /*!< SPIFI Nor memory */ + kMemoryFlashExecuteOnly = MAKE_MEMORYID(kMemoryGroup_Internal, 0x10U), /*!< Execute-only region on internal Flash */ + + kMemorySemcNand = MAKE_MEMORYID(kMemoryGroup_External, 0U), /*!< SEMC NAND memory */ + kMemorySpiNand = MAKE_MEMORYID(kMemoryGroup_External, 1U), /*!< SPI NAND memory */ + kMemorySpiNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x10U), /*!< SPI NOR/EEPROM memory */ + kMemoryI2cNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x11U), /*!< I2C NOR/EEPROM memory */ + kMemorySDCard = MAKE_MEMORYID(kMemoryGroup_External, 0x20U), /*!< eSD, SD, SDHC, SDXC memory Card */ + kMemoryMMCCard = MAKE_MEMORYID(kMemoryGroup_External, 0x21U), /*!< MMC, eMMC memory Card */ +}; + +/*! @brief Bootloader status group numbers. + * + * @ingroup bl_core + */ +enum +{ + kStatusGroup_Bootloader = 100, /*!< Bootloader status group number (100). */ + kStatusGroup_MemoryInterface = 102, /*!< Memory interface status group number (102). */ +}; + +/*! @brief Memory interface status codes. */ +enum +{ + kStatusMemoryRangeInvalid = MAKE_STATUS(kStatusGroup_MemoryInterface, 0), + kStatusMemoryReadFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 1), + kStatusMemoryWriteFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 2), + kStatusMemoryCumulativeWrite = MAKE_STATUS(kStatusGroup_MemoryInterface, 3), + kStatusMemoryAppOverlapWithExecuteOnlyRegion = MAKE_STATUS(kStatusGroup_MemoryInterface, 4), + kStatusMemoryNotConfigured = MAKE_STATUS(kStatusGroup_MemoryInterface, 5), + kStatusMemoryAlignmentError = MAKE_STATUS(kStatusGroup_MemoryInterface, 6), + kStatusMemoryVerifyFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 7), + kStatusMemoryWriteProtected = MAKE_STATUS(kStatusGroup_MemoryInterface, 8), + kStatusMemoryAddressError = MAKE_STATUS(kStatusGroup_MemoryInterface, 9), + kStatusMemoryBlankCheckFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 10), + kStatusMemoryBlankPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 11), + kStatusMemoryProtectedPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 12), + kStatusMemoryFfrSpecRegionWriteBroken = MAKE_STATUS(kStatusGroup_MemoryInterface, 13), + kStatusMemoryUnsupportedCommand = MAKE_STATUS(kStatusGroup_MemoryInterface, 14), +}; + +/*! @brief Bootloader status codes. */ +enum +{ + kStatus_UnknownCommand = MAKE_STATUS(kStatusGroup_Bootloader, 0), + kStatus_SecurityViolation = MAKE_STATUS(kStatusGroup_Bootloader, 1), + kStatus_AbortDataPhase = MAKE_STATUS(kStatusGroup_Bootloader, 2), + kStatus_Ping = MAKE_STATUS(kStatusGroup_Bootloader, 3), + kStatus_NoResponse = MAKE_STATUS(kStatusGroup_Bootloader, 4), + kStatus_NoResponseExpected = MAKE_STATUS(kStatusGroup_Bootloader, 5), + kStatus_CommandUnsupported = MAKE_STATUS(kStatusGroup_Bootloader, 6), +}; + +/*! + * @brief Interface to memory operations. + * + * This is the main abstract interface to all memory operations. + */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer, uint32_t memoryId); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer, uint32_t memoryId); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*finalize)(void); + status_t (*erase)(uint32_t address, uint32_t length, uint32_t memoryId); +} memory_interface_t; + +/*! @brief Interface to memory operations for one region of memory. */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +//! @brief Structure of a memory map entry. +typedef struct +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +/*! @brief Structure of version property. */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief API initialization data structure */ +typedef struct kb_api_parameter_struct +{ + uint32_t allocStart; + uint32_t allocSize; +} kp_api_init_param_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void); + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx); + +/*! + * @brief Initialize memory interface. + * + * @retval #kStatus_Fail + * @retval #kStatus_Success + */ +status_t MEM_Init(api_core_context_t *coreCtx); + +/*! + * @brief Configure memory interface + * + * @param config A pointer to the storage for the driver runtime state. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport +*/ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId); + +/*! + * @brief Write memory. + * + * @param address The start address of the desired flash memory to be programmed. + For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param buffer A pointer to the source buffer of data that is to be programmed into the flash. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatus_FLASH_CompareError + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId); + +/*! + * @brief Fill memory with a word pattern. + * + * @param address The start address of the desired flash memory to be programmed. + * For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param pattern The data to be written into the specified memory area. + * + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_Success + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId); + +/*! + * @brief Flush memory. + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Flush(api_core_context_t *coreCtx); + +/*! + * @brief Erase memory. + * + * @param address The start address of the desired flash memory to be erased. + * @param length Number of bytes to be read. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatusMemoryAddressError + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + + */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId); + +/*! + * @brief Erase entire memory based on memoryId + * + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + * @retval #kStatusMemoryNotConfigured + * @retval #kStatus_InvalidArgument + */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_MEM_INTERFACE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader.h new file mode 100644 index 0000000000000000000000000000000000000000..cfcf2ceedea59390794ee1912a5d2dfaa765eb6f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader.h @@ -0,0 +1,373 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SBLOADER_H_ +#define _FSL_SBLOADER_H_ + +#include "fsl_flash.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_sbloader_v3.h" +#include "fsl_common.h" +/*! + * @addtogroup sbloader + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Determines the version of SB loader implementation (1: sb1.0; 2: sb2.0; 3.1: sb3.1) */ +#define SB_FILE_MAJOR_VERSION (3) +#define SB_FILE_MINOR_VERSION (1) + +/*! @brief Bootloader status group numbers */ +#define kStatusGroup_SBLoader (101U) + +/*! @brief Contiguous RAM region count */ +#define RAM_REGION_COUNT (2U) + +/*! @brief Contiguous FLASH region count */ +#define FLASH_REGION_COUNT (1U) + +/*! @brief Contiguous FFR region count */ +#define FFR_REGION_COUNT (1U) + +/*! @brief Memory Interface count */ +#define MEM_INTERFACE_COUNT (4U) + +/*! @brief Contiguous FLEXSPINOR meomry count */ +#define FLEXSPINOR_REGION_COUNT (1U) + +/*! @brief SB loader status codes.*/ +enum +{ + kStatusRomLdrSectionOverrun = MAKE_STATUS(kStatusGroup_SBLoader, 0), + kStatusRomLdrSignature = MAKE_STATUS(kStatusGroup_SBLoader, 1), + kStatusRomLdrSectionLength = MAKE_STATUS(kStatusGroup_SBLoader, 2), + kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3), + kStatusRomLdrEOFReached = MAKE_STATUS(kStatusGroup_SBLoader, 4), + kStatusRomLdrChecksum = MAKE_STATUS(kStatusGroup_SBLoader, 5), + kStatusRomLdrCrc32Error = MAKE_STATUS(kStatusGroup_SBLoader, 6), + kStatusRomLdrUnknownCommand = MAKE_STATUS(kStatusGroup_SBLoader, 7), + kStatusRomLdrIdNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 8), + kStatusRomLdrDataUnderrun = MAKE_STATUS(kStatusGroup_SBLoader, 9), + kStatusRomLdrJumpReturned = MAKE_STATUS(kStatusGroup_SBLoader, 10), + kStatusRomLdrCallFailed = MAKE_STATUS(kStatusGroup_SBLoader, 11), + kStatusRomLdrKeyNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 12), + kStatusRomLdrSecureOnly = MAKE_STATUS(kStatusGroup_SBLoader, 13), + kStatusRomLdrResetReturned = MAKE_STATUS(kStatusGroup_SBLoader, 14), + + kStatusRomLdrRollbackBlocked = MAKE_STATUS(kStatusGroup_SBLoader, 15), + kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16), + kStatusRomLdrUnexpectedCommand = MAKE_STATUS(kStatusGroup_SBLoader, 17), + kStatusRomLdrBadSBKEK = MAKE_STATUS(kStatusGroup_SBLoader, 18), + kStatusRomLdrPendingJumpCommand = MAKE_STATUS(kStatusGroup_SBLoader, 19), +}; + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define BYTES_PER_CHUNK 16 + +#define SB_SECTION_COUNT_MAX 8 + +/*! @brief Boot image signature in 32-bit little-endian format "PMTS" */ +#define BOOT_SIGNATURE 0x504d5453 + +/*! @brief Boot image signature in 32-bit little-endian format "ltgs" */ +#define BOOT_SIGNATURE2 0x6c746773 + +/*! @brief These define file header flags */ +#define FFLG_DISPLAY_PROGRESS 0x0001 + +/*! @brief These define section header flags */ +#define SFLG_SECTION_BOOTABLE 0x0001 + +/*! @brief These define boot command flags */ +#define CFLG_LAST_TAG 0x01 + +/*! @brief ROM_ERASE_CMD flags */ +#define ROM_ERASE_ALL_MASK 0x01 +#define ROM_ERASE_ALL_UNSECURE_MASK 0x02 + +/*! @brief ROM_JUMP_CMD flags */ +#define ROM_JUMP_SP_MASK 0x02 + +/*! @brief Memory device id shift at sb command flags */ +#define ROM_MEM_DEVICE_ID_SHIFT 0x8 + +/*! @brief Memory device id mask */ +#define ROM_MEM_DEVICE_ID_MASK 0xff00 + +/*! @brief Memory group id shift at sb command flags */ +#define ROM_MEM_GROUP_ID_SHIFT 0x4 + +/*! @brief Memory group id flags mask */ +#define ROM_MEM_GROUP_ID_MASK 0xf0 + +/*! @brief ROM_PROG_CMD flags */ +#define ROM_PROG_8BYTE_MASK 0x01 + +/*! @brief These define the boot command tags */ +#define ROM_NOP_CMD 0x00 +#define ROM_TAG_CMD 0x01 +#define ROM_LOAD_CMD 0x02 +#define ROM_FILL_CMD 0x03 +#define ROM_JUMP_CMD 0x04 +#define ROM_CALL_CMD 0x05 +#define ROM_MODE_CMD 0x06 +#define ROM_ERASE_CMD 0x07 +#define ROM_RESET_CMD 0x08 +#define ROM_MEM_ENABLE_CMD 0x09 +#define ROM_PROG_CMD 0x0a +#define ROM_FW_VER_CHK 0x0b + +#if SB_FILE_MAJOR_VERSION == 2 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V2_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V2_CMD_SET_IN_REC_MODE) +#elif SB_FILE_MAJOR_VERSION == 3 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V3_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V3_CMD_SET_IN_REC_MODE) +#endif + +/*! @brief Plugin return codes */ +#define ROM_BOOT_SECTION_ID 1 +#define ROM_BOOT_IMAGE_ID 2 + +enum _fw_version_check_option +{ + kRomLdr_FwCheckOption_SecureVersion = 0x0U, + kRomLdr_FwCheckOption_NonSecureVersion = 0x1U, +}; + +typedef uint8_t chunk_t[BYTES_PER_CHUNK]; + +/*! @brief Boot command definition */ +typedef struct _boot_cmd +{ + uint8_t checksum; /*!< 8-bit checksum over command chunk */ + uint8_t tag; /*!< command tag (identifier) */ + uint16_t flags; /*!< command flags (modifier) */ + uint32_t address; /*!< address argument */ + uint32_t count; /*!< count argument */ + uint32_t data; /*!< data argument */ +} boot_cmd_t; + +/*! @brief Definition for boot image file header chunk 1 */ +typedef struct _boot_hdr1 +{ + uint32_t hash; /*!< last 32-bits of SHA-1 hash */ + uint32_t signature; /*!< must equal "STMP" */ + uint8_t major; /*!< major file format version */ + uint8_t minor; /*!< minor file format version */ + uint16_t fileFlags; /*!< global file flags */ + uint32_t fileChunks; /*!< total chunks in the file */ +} boot_hdr1_t; + +/*! @brief Definition for boot image file header chunk 2 */ +typedef struct _boot_hdr2 +{ + uint32_t bootOffset; /*!< chunk offset to the first boot section */ + uint32_t bootSectID; /*!< section ID of the first boot section */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint16_t keyOffset; /*!< chunk offset to the key dictionary */ + uint16_t hdrChunks; /*!< number of chunks in the header */ + uint16_t sectCount; /*!< number of sections in the image */ +} boot_hdr2_t; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context ldr_Context_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_t)(ldr_Context_t *); + +/*! @brief Jump command function pointer definition. */ +typedef status_t (*pJumpFnc_t)(uint32_t); + +/*! @brief Call command function pointer definition. */ +typedef status_t (*pCallFnc_t)(uint32_t, uint32_t *); + +/*! @brief State information for the CRC32 algorithm. */ +typedef struct Crc32Data +{ + uint32_t currentCrc; /*!< Current CRC value. */ + uint32_t byteCountCrc; /*!< Number of bytes processed. */ +} crc32_data_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context +{ + pLdrFnc_t Action; /*!< pointer to loader action function */ + uint32_t fileChunks; /*!< chunks remaining in file */ + uint32_t sectChunks; /*!< chunks remaining in section */ + uint32_t bootSectChunks; /*!< number of chunks we need to complete the boot section */ + uint32_t receivedChunks; /*!< number of chunks we need to complete the boot section */ + uint16_t fileFlags; /*!< file header flags */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint32_t objectID; /*!< ID of the current boot section or image */ + crc32_data_t crc32; /*!< crc calculated over load command payload */ + uint8_t *src; /*!< source buffer address */ + chunk_t initVector; /*!< decryption initialization vector */ + chunk_t dek; /*!< chunk size DEK if the image is encrypted */ + chunk_t scratchPad; /*!< chunk size scratch pad area */ + boot_cmd_t bootCmd; /*!< current boot command */ + uint32_t skipCount; /*!< Number of chunks to skip */ + bool skipToEnd; /*!< true if skipping to end of file */ + + // extended for SB 2.0 + uint32_t nonce[4]; + uint32_t keyBlobBlock; + uint32_t keyBlobBlockCount; + uint8_t *keyBlobBuffer; + uint32_t offsetSignatureBytes; /*!< offset to signagure block header in bytesn */ + uint8_t *headerBuffer; +}; + +typedef struct soc_memory_map_struct +{ + struct + { + uint32_t start; + uint32_t end; + } ramRegions[RAM_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flashRegions[FLASH_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } ffrRegions[FFR_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flexspiNorRegions[FLEXSPINOR_REGION_COUNT]; +} soc_mem_regions_t; + +typedef struct arena_context +{ + uint32_t start; + uint32_t end; + uint32_t nextAddr; +} arena_context_t; + +/*! @brief Memory region information table */ +typedef struct mem_region +{ + uint32_t start; + uint32_t end; +} mem_region_t; + +/*! @brief Memory Attribute Structure */ +typedef struct memory_attribute_struct +{ + uint32_t memId; + uint32_t regionCount; + mem_region_t *memRegions; + void *context; +} mem_attribute_t; + +/*! @brief Memory context structure */ +typedef struct memory_context_struct +{ + status_t (*flush)(mem_attribute_t *attr); + mem_attribute_t *attr; +} mem_context_t; + +/*! @brief Memory region interface structure */ +typedef struct api_memory_region_interface +{ + status_t (*init)(mem_attribute_t *attr); +#if ROM_API_HAS_FEATURE_MEM_READ + status_t (*read)(mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf); +#endif + status_t (*write)(mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf); + status_t (*fill)(mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern); + status_t (*flush)(mem_attribute_t *attr); + status_t (*erase)(mem_attribute_t *attr, uint32_t addr, uint32_t len); + status_t (*config)(mem_attribute_t *attr, uint32_t *buf); + status_t (*erase_all)(mem_attribute_t *attr); + status_t (*alloc_ctx)(arena_context_t *ctx, mem_attribute_t *attr, void *miscParams); +} api_memory_region_interface_t; + +/*! @brief Memory entry data structure */ +typedef struct memory_map_entry +{ + mem_attribute_t *memoryAttribute; + const api_memory_region_interface_t *memoryInterface; +} api_memory_map_entry_t; + +/*! @brief The API context structure */ +typedef struct api_core_context +{ + soc_mem_regions_t memRegions; + arena_context_t arenaCtx; + flash_config_t flashConfig; + flexspi_nor_config_t flexspinorCfg; + mem_context_t memCtx; + ldr_Context_v3_t *sbloaderCtx; + nboot_context_t *nbootCtx; + uint8_t *sharedBuf; + api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT]; +} api_core_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Perform the Sbloader runtime environment initialization + * This API is used for initializing the sbloader state machine before calling + * the api_sbloader_pump. This API should be called after the iap_api_init API. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Init(api_core_context_t *ctx); + +/*! + * @brief Handle the SB data stream + * This API is used for handling the secure binary(SB3.1 format) data stream, + * which is used for image update, lifecycle advancing, etc. + * This API should be called after the iap_api_init and api_sbloader_init APIs. + + * @param ctx Pointer to IAP API core context structure. + * @param data Pointer to source data that is the sb file buffer data. + * @param length The size of the process buffer data. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_Fail API execution failed. + */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length); + +/*! + * @brief Finish the sbloader handling + * The API is used for finalizing the sbloader operations. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Finalize(api_core_context_t *ctx); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SBLOADER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader_v3.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader_v3.h new file mode 100644 index 0000000000000000000000000000000000000000..292c9ac1ac32c4b2f200f2c99ab44619a954e4e8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/fsl_sbloader_v3.h @@ -0,0 +1,271 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SBLOADER_V3_H_ +#define _FSL_SBLOADER_V3_H_ + +#include + +#include "fsl_nboot_hal.h" + +/*! @addtogroup sbloader */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define SB3_BYTES_PER_CHUNK 16 + +typedef uint8_t chunk_v3_t[SB3_BYTES_PER_CHUNK]; + +typedef struct _ldr_buf ldr_buf_t; + +struct _ldr_buf +{ + chunk_v3_t data; + uint32_t fillPosition; +}; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context_v3 ldr_Context_v3_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_v3_t)(ldr_Context_v3_t *); + +/*! @brief sb3 section definitions */ +/*! @brief section type */ +typedef enum _sectionType +{ + kSectionNone = 0, /*!< end or invalid */ + kSectionDataRange = 1, + kSectionDiffUpdate = 2, + kSectionDDRConfig = 3, + kSectionRegister = 4, +} section_type_t; + +#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) /*!< bit 0 */ +#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK (0x2u) /*!< bit 1 */ + +/*! @brief section data range structure */ +typedef struct range_header +{ + uint32_t tag; + uint32_t startAddress; + uint32_t length; + uint32_t cmd; +} sb3_data_range_header_t; + +typedef struct range_header_expansion +{ + uint32_t memoryId; + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb3_data_range_expansion_t; + +typedef struct copy_memory_expansion +{ + uint32_t destAddr; + uint32_t memoryIdFrom; + uint32_t memoryIdTo; + uint32_t pad; +} sb3_copy_memory_expansion_t; + +typedef struct copy +{ + sb3_data_range_header_t header; + sb3_copy_memory_expansion_t expansion; +} sb3_copy_memory_t; + +typedef struct load_keyblob +{ + uint32_t tag; + uint16_t offset; + uint16_t keyWrapId; + uint32_t length; + uint32_t cmd; +} sb3_load_keyblob_t; + +typedef struct fill_memory_expansion +{ + uint32_t pattern; /*!< word to be used as pattern */ + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb3_fill_memory_expansion_t; + +typedef struct fill_memory +{ + sb3_data_range_header_t header; + sb3_fill_memory_expansion_t arg; +} sb3_fill_memory_t; + +typedef struct config_memory +{ + uint32_t tag; + uint32_t memoryId; + uint32_t address; /*!< address of config blob */ + uint32_t cmd; +} sb3_config_memory_t; + +enum +{ + kFwVerChk_Id_none = 0, + kFwVerChk_Id_nonsecure = 1, + kFwVerChk_Id_secure = 2, +}; + +typedef struct fw_ver_check +{ + uint32_t tag; + uint32_t version; + uint32_t id; + uint32_t cmd; +} sb3_fw_ver_check_t; + +/*! @brief sb3 DATA section header format */ +typedef struct section_header +{ + uint32_t sectionUid; + uint32_t sectionType; + uint32_t length; + uint32_t _pad; +} sb3_section_header_t; + +/*! @brief loader command enum */ +typedef enum _loader_command_sb3 +{ + kSB3_CmdInvalid = 0, + kSB3_CmdErase = 1, + kSB3_CmdLoad = 2, + kSB3_CmdExecute = 3, + kSB3_CmdCall = 4, + kSB3_CmdProgramFuse = 5, + kSB3_CmdProgramIFR = 6, + kSB3_CmdLoadCmac = 7, + kSB3_CmdCopy = 8, + kSB3_CmdLoadHashLocking = 9, + kSB3_CmdLoadKeyBlob = 10, + kSB3_CmdConfigMem = 11, + kSB3_CmdFillMem = 12, + kSB3_CmdFwVerCheck = 13, +} sb3_cmd_t; + +/*! @brief The all of the allowed command */ +#define SBLOADER_V3_CMD_SET_ALL \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdCall) | \ + (1u << kSB3_CmdProgramFuse) | (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | \ + (1u << kSB3_CmdConfigMem) | (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) +/*! @brief The allowed command set in ISP mode */ +#define SBLOADER_V3_CMD_SET_IN_ISP_MODE \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ + (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ + (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) +/*! @brief The allowed command set in recovery mode */ +#define SBLOADER_V3_CMD_SET_IN_REC_MODE \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ + (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ + (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) + +#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(128, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX)) + +/*! @brief Memory region definition. */ +typedef struct +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image. */ + kRomLoadImage = 2, /*!< Load SB file. */ + kRomOperationCount = 3, +} kb_operation_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct +{ + uint32_t version; /*!< Should be set to #kKbootApiVersion. */ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot. */ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*!< Settings for #kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*!< Settings for #kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context_v3 +{ + pLdrFnc_v3_t Action; /*!< pointer to loader action function */ + uint32_t block_size; /*!< size of each block in bytes */ + uint32_t block_data_size; /*!< data size in bytes (NBOOT_SB3_CHUNK_SIZE_IN_BYTES) */ + uint32_t block_data_total; /*!< data max size in bytes (block_size * data_size */ + uint32_t block_buffer_size; /*!< block0 and block size */ + uint32_t block_buffer_position; + uint8_t block_buffer[MAX(NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES, + NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES)]; /*! will be used for both block0 and blockx */ + uint32_t processedBlocks; + + uint8_t data_block_offset; /*! data block offset in a block. */ + bool in_data_block; /*!< in progress of handling a data block within a block */ + uint8_t *data_block; + uint32_t data_block_position; + + bool in_data_section; /*!< in progress of handling a data section within a data block */ + uint32_t data_section_handled; + sb3_section_header_t data_section_header; + + bool in_data_range; /*!< in progress of handling a data range within a data section */ + uint32_t data_range_handled; + uint32_t data_range_gap; + sb3_data_range_header_t data_range_header; + bool has_data_range_expansion; + sb3_data_range_expansion_t data_range_expansion; + + uint32_t commandSet; /*!< support command set during sb file handling */ + + uint32_t data_position; + uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; /*!< temporary data buffer */ + + kb_options_t fromAPI; /*!< options from ROM API */ +}; + +/*! @} */ + +#endif /* _FSL_SBLOADER_V3_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/src/fsl_mem_interface.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/src/fsl_mem_interface.c new file mode 100644 index 0000000000000000000000000000000000000000..a863327e87ef3760285a3a07047c41e9880ae5ef --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/mem_interface/src/fsl_mem_interface.c @@ -0,0 +1,133 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_mem_interface.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.memInterface" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define API_INTERFACE ((api_core_interface_t *)0x1302fcb4U) + +/*! @brief IAP API Interface structure */ +typedef struct iap_api_interface_struct +{ + standard_version_t version; /*!< IAP API version number. */ + status_t (*api_init)(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + status_t (*api_deinit)(api_core_context_t *coreCtx); + status_t (*mem_init)(api_core_context_t *ctx); + const uint32_t reserved; + status_t (*mem_write)(api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId); + status_t (*mem_fill)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId); + status_t (*mem_flush)(api_core_context_t *ctx); + status_t (*mem_erase)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId); + status_t (*mem_config)(api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId); + status_t (*mem_erase_all)(api_core_context_t *ctx, uint32_t memoryId); + status_t (*sbloader_init)(api_core_context_t *ctx); + status_t (*sbloader_pump)(api_core_context_t *ctx, uint8_t *data, uint32_t length); + status_t (*sbloader_finalize)(api_core_context_t *ctx); +} api_core_interface_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void) +{ + assert(API_INTERFACE); + return API_INTERFACE->version; +} + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param) +{ + assert(API_INTERFACE); + return API_INTERFACE->api_init(coreCtx, param); +} + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx) +{ + assert(API_INTERFACE); + return API_INTERFACE->api_deinit(coreCtx); +} + +/*! @brief Intialize the memory interface of the IAP API */ +status_t MEM_Init(api_core_context_t *coreCtx) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_init(coreCtx); +} + +/*! @brief Perform the memory write operation */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_write(coreCtx, start, lengthInBytes, buf, memoryId); +} + +/*! @brief Perform the Fill operation */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_fill(coreCtx, start, lengthInBytes, pattern, memoryId); +} + +/*! @brief Perform the Memory erase operation */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_erase(coreCtx, start, lengthInBytes, memoryId); +} +/*! @brief Perform the full Memory erase operation */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_erase_all(coreCtx, memoryId); +} + +/*! @brief Perform the Memory configuration operation */ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_config(coreCtx, config, memoryId); +} + +/*! @brief Perform the Memory Flush operation */ +status_t MEM_Flush(api_core_context_t *coreCtx) +{ + assert(API_INTERFACE); + return API_INTERFACE->mem_flush(coreCtx); +} + +/*! @brief Perform the Sbloader runtime environment initialization */ +status_t Sbloader_Init(api_core_context_t *ctx) +{ + assert(API_INTERFACE); + return API_INTERFACE->sbloader_init(ctx); +} + +/*! @brief Handle the SB data stream */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length) +{ + assert(API_INTERFACE); + return API_INTERFACE->sbloader_pump(ctx, data, length); +} +/*! @brief Finish the sbloader handling */ +status_t Sbloader_Finalize(api_core_context_t *ctx) +{ + assert(API_INTERFACE); + return API_INTERFACE->sbloader_finalize(ctx); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot.h new file mode 100644 index 0000000000000000000000000000000000000000..64b50d793f1ae05c65f9f2c1a51abe3b28f770c9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot.h @@ -0,0 +1,339 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_NBOOT_H_ +#define _FSL_NBOOT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup nboot + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/** @def NXPCLHASH_WA_SIZE_MAX + * @brief Define the max workarea size required for this component + */ +#define NXPCLHASH_WA_SIZE_MAX (128U+64U) +#define NBOOT_ROOT_CERT_COUNT (4U) +#define NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL ((size_t) 32U) ///< Size of RTF appendix to hash output buffer, in bytes + +#define NBOOT_KEYINFO_WORDLEN (23U) +#define NBOOT_CONTEXT_BYTELEN (192U + NXPCLHASH_WA_SIZE_MAX) +#define NBOOT_CONTEXT_WORDLEN (NBOOT_CONTEXT_BYTELEN/sizeof(uint32_t)) +typedef int romapi_status_t; + +/*! + * @brief NBOOT type for the root key usage + * + * This type defines the NBOOT root key usage; + * any other value means the root key is not valid (treat as if revoked). + */ +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0U) +#define kNBOOT_RootKeyUsage_DebugCA (0x1U) +#define kNBOOT_RootKeyUsage_ImageCA_FwCA (0x2U) +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA (0x3U) +#define kNBOOT_RootKeyUsage_ImageKey_FwKey (0x4U) +#define kNBOOT_RootKeyUsage_ImageKey (0x5U) +#define kNBOOT_RootKeyUsage_FwKey (0x6U) +#define kNBOOT_RootKeyUsage_Unused (0x7U) +typedef uint32_t nboot_root_key_usage_t; + +/*! + * @brief NBOOT type for the root key revocation + * + * This type defines the NBOOT root key revocation; + * any other value means the root key is revoked. + */ +#define kNBOOT_RootKey_Enabled (0xAAU) +#define kNBOOT_RootKey_Revoked (0xBBU) +typedef uint32_t nboot_root_key_revocation_t; + +/*! + * @brief NBOOT type specifying the elliptic curve to be used + * + * This type defines the elliptic curve type and length + */ +#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01U) +#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02U) +typedef uint32_t nboot_root_key_type_and_length_t; + +/*! @brief Enumeration for SoC Lifecycle. */ +#define nboot_lc_nxpBlank (0xFFFF0000U) +#define nboot_lc_nxpFab (0xFFFE0001U) +#define nboot_lc_nxpDev (0xFF0300FCU) +#define nboot_lc_nxpProvisioned (0xFFFC0003U) +#define nboot_lc_oemOpen (0xFFFC0003U) +#define nboot_lc_oemSecureWorld (0xFFF80007U) +#define nboot_lc_oemClosed (0xFFF0000FU) +#define nboot_lc_oemLocked (0xFF3000CFU) +#define nboot_lc_oemFieldReturn (0xFFE0001FU) +#define nboot_lc_nxpFieldReturn (0xFF80007FU) +#define nboot_lc_shredded (0xFF0000FFU) +typedef uint32_t nboot_soc_lifecycle_t; + +/*! @brief Type for nboot status codes */ +typedef uint32_t nboot_status_t; + +/*! @brief Type for nboot protected status codes */ +typedef uint64_t nboot_status_protected_t; + +/*! + * @brief nboot status codes. + */ +enum +{ + kStatus_NBOOT_Success = 0x5A5A5A5AU, /*!< Operation completed successfully. */ + kStatus_NBOOT_Fail = 0x5A5AA5A5U, /*!< Operation failed. */ + kStatus_NBOOT_InvalidArgument = 0x5A5AA5F0U, /*!< Invalid argument passed to the function. */ + kStatus_NBOOT_RequestTimeout = 0x5A5AA5E1U, /*!< Operation timed out. */ + kStatus_NBOOT_KeyNotLoaded = 0x5A5AA5E2U, /*!< The requested key is not loaded. */ + kStatus_NBOOT_AuthFail = 0x5A5AA5E4U, /*!< Authentication failed. */ + kStatus_NBOOT_OperationNotAvaialable = 0x5A5AA5E5U, /*!< Operation not available on this HW. */ + kStatus_NBOOT_KeyNotAvailable = 0x5A5AA5E6U, /*!< Key is not avaialble. */ + kStatus_NBOOT_IvCounterOverflow = 0x5A5AA5E7U, /*!< Overflow of IV counter (PRINCE/IPED). */ + kStatus_NBOOT_SelftestFail = 0x5A5AA5E8U, /*!< FIPS self-test failure. */ + kStatus_NBOOT_InvalidDataFormat = 0x5A5AA5E9U, /*!< Invalid data format for example antipole */ + kStatus_NBOOT_IskCertUserDataTooBig = 0x5A5AA5EAU, /*!< Size of User data in ISK certificate is greater than 96 bytes */ + kStatus_NBOOT_IskCertSignatureOffsetTooSmall = 0x5A5AA5EBU, /*!< Signature offset in ISK certificate is smaller than expected */ + kStatus_NBOOT_MemcpyFail =0x5A5A845AU, /*!< Unexpected error detected during nboot_memcpy() */ +}; + +/*! @brief Data structure holding secure counter value used by nboot library */ +typedef struct _nboot_secure_counter +{ + uint32_t sc; + uint32_t scAp; +} nboot_secure_counter_t; + +/*! + * @brief NBOOT context type + * + * This type defines the NBOOT context + * + */ +typedef struct _nboot_context +{ + uint32_t totalBlocks; /*!< holds number of SB3 blocks. Initialized by nboot_sb3_load_header(). */ + uint32_t processData; /*!< flag, initialized by nboot_sb3_load_header(). + SB3 related flag set by NBOOT in case the nboot_sb3_load_block() + provides plain data to output buffer (for processing by ROM SB3 loader */ + uint32_t timeout; /*!< timeout value for css operation. In case it is 0, infinite wait is performed */ + uint32_t keyinfo[NBOOT_KEYINFO_WORDLEN]; /*!< data for NBOOT key management. */ + uint32_t context[NBOOT_CONTEXT_WORDLEN]; /*!< work area for NBOOT lib. */ + uint32_t uuid[4]; /*!< holds UUID value from NMPA */ + uint32_t prngReadyFlag; /*!< flag, used by nboot_rng_generate_lq_random() to determine whether CSS is ready to generate rnd number */ + uint32_t multipartMacBuffer[1024/sizeof(uint32_t)]; + uint32_t oemShareValidFlag; /*!< flag, used during TP to determine whether valid oemShare was set by nboot_tp_isp_gen_oem_master_share() */ + uint32_t oemShare[4]; /*!< buffer to store OEM_SHARE computed by nxpCLTrustProv_nboot_isp_gen_oem_master_share() */ + nboot_secure_counter_t secureCounter; /*!< Secure counter used by nboot */ + uint32_t rtf[NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL/sizeof(uint32_t)]; + uint32_t imageHash[48/sizeof(uint32_t)]; + uint32_t authStatus; +} nboot_context_t; + +/*! + * @brief NBOOT type for the root of trust parameters + * + * This type defines the NBOOT root of trust parameters + * + */ +typedef struct _nboot_rot_auth_parms +{ + /* trusted information originated from CFPA */ + nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM information in CFPA: ROTKH_REVOKE */ + uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */ + + /* trusted information originated from CMPA */ + uint32_t soc_rkh[12]; /*!< Provided by caller based on NVM information in CMPA: ROTKH (hash of hashes) */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */ + + uint32_t soc_numberOfRootKeys; /*!< unsigned int, between minimum = 1 and maximum = 4; */ + nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /*!< CMPA */ + nboot_root_key_type_and_length_t soc_rootKeyTypeAndLength; /*!< static selection between ECDSA P-256 or ECDSA P-384 based root keys */ + + /* trusted information originated from OTP fuses */ + nboot_soc_lifecycle_t soc_lifecycle; +} nboot_rot_auth_parms_t; + +/*! + * @brief manifest loading parameters + * + * This type defines the NBOOT SB3.1 manifest loading parameters + * + */typedef struct _nboot_sb3_load_manifest_parms +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ + uint8_t pckBlob[48]; +} nboot_sb3_load_manifest_parms_t; + +/*! + * @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. + * Shall be read from SoC trusted NVM or SoC fuses. + */ +typedef struct _nboot_img_auth_ecdsa_parms +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ +} nboot_img_auth_ecdsa_parms_t; + +/*! @brief Data structure holding input arguments for CMAC authentication */ +typedef struct _nboot_cmac_authenticate_parms +{ + uint32_t expectedMAC[4]; /*!< expected MAC result */ +} nboot_img_authenticate_cmac_parms_t; + +/*! + * @brief Boolean type for the NBOOT functions + * + * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks + */ +typedef enum _nboot_bool +{ + kNBOOT_TRUE = 0x3C5AC33CU, /*!< Value for TRUE. */ + kNBOOT_TRUE256 = 0x3C5AC35AU, /*!< Value for TRUE when P256 was used to sign the image. */ + kNBOOT_TRUE384 = 0x3C5AC3A5U, /*!< Value for TRUE when P384 was used to sign the image. */ + kNBOOT_FALSE = 0x5AA55AA5U, /*!< Value for FALSE. */ + kNBOOT_OperationAllowed = 0x3c5a33ccU, + kNBOOT_OperationDisallowed = 0x5aa5cc33U, +} nboot_bool_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief This API function is used to generate random number with specified length. + * + * @param output Pointer to random number buffer + * @param outputByteLen length of generated random number in bytes. Length has to be in range <1, 2^16> + * + * @retval #kStatus_NBOOT_InvalidArgument Invalid input parameters (Input pointers points to NULL or length is invalid) + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +status_t NBOOT_GenerateRandom(uint8_t *output, size_t outputByteLen); + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation +*/ +nboot_status_t NBOOT_ContextInit(nboot_context_t *context); + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextDeinit(nboot_context_t *context); + +/*! + * @brief Verify NBOOT SB3.1 manifest (header message) + * + * This function verifies the NBOOT SB3.1 manifest (header message), initializes + * the context and loads keys into the CSS key store so that they can be used by nboot_sb3_load_block + * function. The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. Please note that this API is intended to be used only by users who needs to split + * FW update process (loading of SB3.1 file) to partial steps to customize whole operation. + * For regular SB3.1 processing, please use API described in chapter SBloader APIs. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * @param manifest Pointer to the input manifest buffer + * @param params additional input parameters. Please refer to nboot_sb3_load_manifest_parms_t definition for details. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadManifest(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms); + +/*! + * @brief Verify NBOOT SB3.1 block + * + * This function verifies and decrypts an NBOOT SB3.1 block. Decryption is performed in-place. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * Please note that this API is intended to be used only by users who needs to split FW update process + * (loading of SB3.1 file) to partial steps to customize whole operation. For regular SB3.1 processing, + * please use API described in chapter SBloader APIs. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the input SB3.1 data block + * + * @retval #kStatus_NBOOT_Success successfully finished + * @retval #kStatus_NBOOT_Fail occured during operation +*/ + nboot_status_protected_t NBOOT_Sb3LoadBlock(nboot_context_t *context, uint32_t *block); + +/*! + * @brief This function authenticates image with asymmetric cryptography. + * The NBOOT context has to be initialized by the function nboot_context_init + * before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + * After the function returns, the value will be set to kNBOOT_TRUE when the image is authentic. + * Any other value means the authentication does not pass. + * + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Returned in all other cases. Doesn't always mean invalid image, + * it could also mean transient error caused by short time environmental conditions. +*/ +nboot_status_protected_t NBOOT_ImgAuthenticateEcdsa(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms); + +/*! + * @brief This function calculates the CMAC over the given image and compares it to the expected value. + * To be more resistant against SPA, it is recommended that imageStartAddress is word aligned. + * The NBOOT context has to be initialized by the nboot_context_init() before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + After the function returns, the value will be set to + * @param parms Pointer to a data structure in trusted memory, holding the reference MAC. + The data structure shall be correctly filled before the function call. + * + * @retval kStatus_NBOOT_Success + * @retval kStatus_NBOOT_Fail + */ +nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_NBOOT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot_hal.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot_hal.h new file mode 100644 index 0000000000000000000000000000000000000000..acd4701046b5b2beeda2d9b9b537f46860202050 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/nboot/fsl_nboot_hal.h @@ -0,0 +1,231 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_NBOOT_HAL_H_ +#define _FSL_NBOOT_HAL_H_ + +#include "fsl_nboot.h" + +/*! @addtogroup nbot_hal */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The size of the UUID. */ +#define NBOOT_UUID_SIZE_IN_WORD (4) +#define NBOOT_UUID_SIZE_IN_BYTE (NBOOT_UUID_SIZE_IN_WORD * 4) + +/*! @brief The size of the PUF activation code. */ +#define NBOOT_PUF_AC_SIZE_IN_BYTE (996) +/*! @brief The size of the PUF key code. */ +#define NBOOT_PUF_KC_SIZE_IN_BYTE (84) + +/*! @brief The size of the key store. */ +#define NBOOT_KEY_STORE_SIZE_IN_BYTE (NBOOT_PUF_AC_SIZE_IN_BYTE + 8) + +/*! @brief The size of the root of trust key table hash. */ +#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12) +#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4) + +/*! @brief The size of the blob with Key Blob. */ +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384) + +/*! @brief The mask of the value of the debug state . */ +#define NBOOT_DBG_AUTH_DBG_STATE_MASK (0x0000FFFFu) +/*! @brief The shift inverted value of the debug state. */ +#define NBOOT_DBG_AUTH_DBG_STATE_SHIFT (16) +/*! @brief The value with all debug feature disabled. */ +#define NBOOT_DBG_AUTH_DBG_STATE_ALL_DISABLED (0xFFFF0000u) + +#define NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES (48u) + +#define NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES (48u) +#define NBOOT_EC_COORDINATE_MAX_SIZE NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES + +/* SB3.1 */ +#define NBOOT_SB3_CHUNK_SIZE_IN_BYTES (256u) +#define NBOOT_SB3_BLOCK_HASH256_SIZE_IN_BYTES (32u) +#define NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES (48u) + +/*! + * @brief NBOOT type for a timestamp + * + * This type defines the NBOOT timestamp + * + */ +typedef uint32_t nboot_timestamp_t[2]; + +/*! + * @brief NBOOT SB3.1 header type + * + * This type defines the header used in the SB3.1 manifest + * + */ +typedef struct _nboot_sb3_header +{ + uint32_t magic; /*!< offset 0x00: Fixed 4-byte string of 'sbv3' without the trailing NULL */ + uint32_t formatVersion; /*!< offset 0x04: (major = 3, minor = 1); The format version determines the manifest + (block0) size. */ + uint32_t flags; /*!< offset 0x08: not defined yet, keep zero for future compatibility */ + uint32_t blockCount; /*!< offset 0x0C: Number of blocks not including the manifest (block0). */ + uint32_t + blockSize; /*!< offset 0x10: Size in bytes of data block (repeated blockCount times for SB3 data stream). */ + nboot_timestamp_t timeStamp; /*!< offset 0x14: 64-bit value used as key derivation data. */ + uint32_t firmwareVersion; /*!< offset 0x1c: Version number of the included firmware */ + uint32_t imageTotalLength; /*!< offset 0x20: Total manifest length in bytes, including signatures etc. */ + uint32_t imageType; /*!< offset 0x24: image type and flags */ + uint32_t certificateBlockOffset; /*!< offset 0x28: Offset from start of header block to the certificate block. */ + uint8_t description[16]; /*!< offset 0x32: This field provides description of the file. It is an arbitrary + string injected by the signing tool, which helps to identify the file. */ +} nboot_sb3_header_t; + +/*! + * @brief NBOOT type for the header of the certificate block + * + * This type defines the NBOOT header of the certificate block, it is part of the nboot_certificate_block_t + * + */ +typedef struct _nboot_certificate_header_block +{ + uint32_t magic; /*!< magic number. */ + uint32_t formatMajorMinorVersion; /*!< format major minor version */ + uint32_t certBlockSize; /*!< Size of the full certificate block */ +} nboot_certificate_header_block_t; + +typedef uint8_t nboot_ctrk_hash_t[NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES]; + +/*! + * @brief NBOOT type for the hash table + * + * This type defines the NBOOT hash table + * + */ +typedef struct _nboot_ctrk_hash_table +{ + nboot_ctrk_hash_t ctrkHashTable[NBOOT_ROOT_CERT_COUNT]; +} nboot_ctrk_hash_table_t; + +/*! + * @brief NBOOT type for an ECC coordinate + * + * This type defines the NBOOT ECC coordinate type + * + */ +typedef uint8_t + nboot_ecc_coordinate_t[NBOOT_EC_COORDINATE_MAX_SIZE]; /*!< ECC point coordinate, up to 384-bits. big endian. */ + +/*! + * @brief NBOOT type for an ECC point + * + * This type defines the NBOOT ECC point type + */ +typedef struct +{ + nboot_ecc_coordinate_t x; /*!< x portion of the ECDSA public key, up to 384-bits. big endian. */ + nboot_ecc_coordinate_t y; /*!< y portion of the ECDSA public key, up to 384-bits. big endian. */ +} nboot_ecdsa_public_key_t; + +/*! + * @brief NBOOT type for the root certificate block + * + * This type defines the NBOOT root certificate block, it is part of the nboot_certificate_block_t + */ +typedef struct _nboot_root_certificate_block +{ + uint32_t flags; /*!< root certificate flags */ + nboot_ctrk_hash_table_t ctrkHashTable; /*!< hash table */ + nboot_ecdsa_public_key_t rootPublicKey; /*!< root public key */ +} nboot_root_certificate_block_t; + +/*! + * @brief NBOOT type for an ECC signature + * + * This type defines the NBOOT ECC signature type + */ +typedef struct +{ + nboot_ecc_coordinate_t r; /*!< r portion of the ECDSA signature, up to 384-bits. big endian. */ + nboot_ecc_coordinate_t s; /*!< s portion of the ECDSA signature, up to 384-bits. big endian. */ +} nboot_ecdsa_signature_t; + +/*! + * @brief NBOOT type for the isk block + * + * This type defines the constant length part of an NBOOT isk block + */ +typedef struct +{ + uint32_t signatureOffset; /*!< Offset of signature in ISK block. */ + uint32_t constraints; /*!< Version number of signing certificate. */ + uint32_t iskFlags; /*!< Reserved for definiton of ISK certificate flags. */ + nboot_ecdsa_public_key_t + iskPubKey; /*!< Public key of signing certificate. Variable length; only used to determine start address*/ + nboot_ecdsa_public_key_t userData; /*!< Space for at lest one addition public key*/ + nboot_ecdsa_signature_t iskSign; /*!< ISK signature*/ +} nboot_isk_block_t; + +/*! + * @brief NBOOT type for the certificate block + * + * This type defines the constant length part of an NBOOT certificate block + */ +typedef struct _nboot_certificate_block +{ + nboot_certificate_header_block_t header; + nboot_root_certificate_block_t rootCertBlock; /*! Details of selected root certificate (root certificate which will + be used for ISK signing/SB3 header signing) */ + nboot_isk_block_t iskBlock; +} nboot_certificate_block_t; + +#define NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES \ + (sizeof(nboot_sb3_header_t) + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + sizeof(nboot_certificate_block_t) + \ + NBOOT_EC_COORDINATE_MAX_SIZE * 2) +#define NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES \ + (4 /* blockNumber */ + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + NBOOT_SB3_CHUNK_SIZE_IN_BYTES) + +/*! @brief The size of the DICE certificate. */ +#define NBOOT_DICE_CSR_SIZE_IN_WORD (36) +#define NBOOT_DICE_CSR_SIZE_IN_BYTES (NBOOT_DICE_CSR_SIZE_IN_WORD * 4) + +/*! @brief The physical address to put the DICE certificate. */ +#define NBOOT_DICE_CSR_ADDRESS (0x30000000u) + +/*! @brief The offset for the PRCINE/IPED erase region return by nboot mem checker. */ +#define NBOOT_IPED_IV_OFFSET (3U) + +#define NBOOT_IMAGE_CMAC_UPDATE_NONE (0u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX0 (1u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX1 (2u) +#define NBOOT_IMAGE_CMAC_UPDATE_BOTH (3u) +#define NBOOT_IMAGE_CMAC_UPDATE_MASK (3u) + +#define NBOOT_CMPA_CMAC_UPDATE_MASK (0x1Cu) +#define NBOOT_CMPA_CMAC_UPDATE_SHIFT (0x2u) + +#define NBOOT_CMPA_UPDATE_CMAC_PFR (0x2u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_SECURE (0x3u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_CLOSE (0x5u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_LOCKED (0x6u) + +/*! @brief Algorithm used for nboot HASH operation */ +typedef enum _nboot_hash_algo_t +{ + kHASH_Sha1 = 1, /*!< SHA_1 */ + kHASH_Sha256 = 2, /*!< SHA_256 */ + kHASH_Sha512 = 3, /*!< SHA_512 */ + kHASH_Aes = 4, /*!< AES */ + kHASH_AesIcb = 5, /*!< AES_ICB */ +} nboot_hash_algo_t; + +/*! @} */ + +#endif /*_FSL_NBOOT_HAL_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/fsl_runbootloader.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/fsl_runbootloader.h new file mode 100644 index 0000000000000000000000000000000000000000..104cfbb770cf97314f62373af6ab912fa46461fd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/fsl_runbootloader.h @@ -0,0 +1,72 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_RUN_BOOTLOADER_H_ +#define _FSL_RUN_BOOTLOADER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup runbootloader + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | + | Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | +*/ + +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure + */ +void bootloader_user_entry(void *arg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_RUN_BOOTLOADER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/src/fsl_runbootloader.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/src/fsl_runbootloader.c new file mode 100644 index 0000000000000000000000000000000000000000..1cdee52af1c723f126dacaf6e8b656b6baeeb82e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/drivers/runbootloader/src/fsl_runbootloader.c @@ -0,0 +1,147 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_runbootloader.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.runBootloader" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1302FC00U) + +/*! + * @name flash, ffr, flexspi nor flash Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); + status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +} function_command_option_t; + +/*! + * @brief Structure of version property. + * + * @ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number. */ + /* Flash driver */ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program_with_checker)(flash_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); + status_t (*flash_verify_program_with_checker)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + /*!< Flash FFR driver */ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t reserved0; + status_t reserved1; + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + status_t (*ffr_seclib_init)(flash_config_t *config, uint32_t *context); + status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_erase_non_blocking)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_get_command_state)(flash_config_t *config); +} flash_driver_interface_t; + +/*! @brief FLEXSPI Flash driver API Interface */ +typedef struct +{ + uint32_t version; + status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); + status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); + status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); + status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); + status_t (*set_clock_source)(uint32_t clockSrc); + void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); +} flexspi_nor_flash_driver_t; + +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t reserved2; /*!< reserved*/ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +void bootloader_user_entry(void *arg) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->runBootloader(arg); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/fsl_device_registers.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/fsl_device_registers.h new file mode 100644 index 0000000000000000000000000000000000000000..e0c187e378744b81a2e929d7597cad2d9694c107 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/fsl_device_registers.h @@ -0,0 +1,35 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC55S36JBD100) || defined(CPU_LPC55S36JHI48)) + +#define LPC55S36_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S36.h" +/* CPU specific feature definitions */ +#include "LPC55S36_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_flash.ld b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..bc23d2616f86c589947e1569ea02a28a61ea96ec --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_flash.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU retention for power down mode */ +RETENTION_RAMSIZE = DEFINED(__pkc__) ? 0x00004000 : (DEFINED(__power_down__) ? 0x00000604 : 0x00000000); +POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for powerquad */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0003D400 + m_data (RW) : ORIGIN = 0x20000000 + RETENTION_RAMSIZE, LENGTH = 0x0001C000 - RETENTION_RAMSIZE - POWERQUAD_RAMSIZE + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_ram.ld b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_ram.ld new file mode 100644 index 0000000000000000000000000000000000000000..c1b7ae88ac476c7be601f935837cd5dc8ba7002d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/LPC55S36_ram.ld @@ -0,0 +1,204 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU retention for power down mode */ +RETENTION_RAMSIZE = DEFINED(__pkc__) ? 0x00004000 : (DEFINED(__power_down__) ? 0x00000604 : 0x00000000); +POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x0; /* SRAM E(16K) reserved for powerquad */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20000000 + RETENTION_RAMSIZE, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x20000400 + RETENTION_RAMSIZE, LENGTH = 0x0001BC00 - RETENTION_RAMSIZE - POWERQUAD_RAMSIZE + m_data (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/startup_LPC55S36.S b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/startup_LPC55S36.S new file mode 100644 index 0000000000000000000000000000000000000000..2fa183c298dc8623c173a6afbf3b54a10e0c612d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/gcc/startup_LPC55S36.S @@ -0,0 +1,1544 @@ +/* --------------------------------------------------------------------------*/ +/* @file: startup_LPC55S36.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* LPC55S36 */ +/* @version: 1.1 */ +/* @date: 2021-8-4 */ +/* --------------------------------------------------------------------------*/ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2021 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts */ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long ADC1_IRQHandler /* ADC1 */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long DMIC_IRQHandler /* Digital microphone and DMIC subsystem */ + .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long EZH_ARCH_B0_IRQHandler /* EZH interrupt */ + .long WAKEUP_IRQHandler /* Wakeup interrupt */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + .long FlexSPI0_IRQHandler /* FlexSPI interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long Reserved58_IRQHandler /* Reserved interrupt */ + .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ + .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ + .long SPI_FILTER_IRQHandler /* SPI Filter interrupt */ + .long Reserved62_IRQHandler /* Reserved interrupt */ + .long Reserved63_IRQHandler /* Reserved interrupt */ + .long Reserved64_IRQHandler /* Reserved interrupt */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT00 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT01 interrupt */ + .long Freqme_IRQHandler /* frequency measure interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long SHA_IRQHandler /* SHA interrupt */ + .long PKC_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long POWERQUAD_IRQHandler /* PowerQuad interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* LSPI_HS interrupt */ + .long CDOG_IRQHandler /* CodeWDG interrupt */ + .long Reserved77_IRQHandler /* Reserved interrupt */ + .long I3C0_IRQHandler /* I3C interrupt */ + .long Reserved79_IRQHandler /* Reserved interrupt */ + .long Reserved80_IRQHandler /* Reserved interrupt */ + .long CSS_IRQ1_IRQHandler /* CSS_IRQ1 */ + .long Tamper_IRQHandler /* Tamper */ + .long Analog_Glitch_IRQHandler /* Analog_Glitch */ + .long Reserved84_IRQHandler /* Reserved interrupt */ + .long Reserved85_IRQHandler /* Reserved interrupt */ + .long Reserved86_IRQHandler /* Reserved interrupt */ + .long Reserved87_IRQHandler /* Reserved interrupt */ + .long Reserved88_IRQHandler /* Reserved interrupt */ + .long Reserved89_IRQHandler /* Reserved interrupt */ + .long DAC0_IRQHandler /* dac0 interrupt */ + .long DAC1_IRQHandler /* dac1 interrupt */ + .long DAC2_IRQHandler /* dac2 interrupt */ + .long HSCMP0_IRQHandler /* hscmp0 interrupt */ + .long HSCMP1_IRQHandler /* hscmp1 interrupt */ + .long HSCMP2_IRQHandler /* hscmp2 interrupt */ + .long FLEXPWM0_CAPTURE_IRQHandler /* flexpwm0_capture interrupt */ + .long FLEXPWM0_FAULT_IRQHandler /* flexpwm0_fault interrupt */ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* flexpwm0_reload_error interrupt */ + .long FLEXPWM0_COMPARE0_IRQHandler /* flexpwm0_compare0 interrupt */ + .long FLEXPWM0_RELOAD0_IRQHandler /* flexpwm0_reload0 interrupt */ + .long FLEXPWM0_COMPARE1_IRQHandler /* flexpwm0_compare1 interrupt */ + .long FLEXPWM0_RELOAD1_IRQHandler /* flexpwm0_reload1 interrupt */ + .long FLEXPWM0_COMPARE2_IRQHandler /* flexpwm0_compare2 interrupt */ + .long FLEXPWM0_RELOAD2_IRQHandler /* flexpwm0_reload2 interrupt */ + .long FLEXPWM0_COMPARE3_IRQHandler /* flexpwm0_compare3 interrupt */ + .long FLEXPWM0_RELOAD3_IRQHandler /* flexpwm0_reload3 interrupt */ + .long FLEXPWM1_CAPTURE_IRQHandler /* flexpwm1_capture interrupt */ + .long FLEXPWM1_FAULT_IRQHandler /* flexpwm1_fault interrupt */ + .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* flexpwm1_reload_error interrupt */ + .long FLEXPWM1_COMPARE0_IRQHandler /* flexpwm1_compare0 interrupt */ + .long FLEXPWM1_RELOAD0_IRQHandler /* flexpwm1_reload0 interrupt */ + .long FLEXPWM1_COMPARE1_IRQHandler /* flexpwm1_compare1 interrupt */ + .long FLEXPWM1_RELOAD1_IRQHandler /* flexpwm1_reload1 interrupt */ + .long FLEXPWM1_COMPARE2_IRQHandler /* flexpwm1_compare2 interrupt */ + .long FLEXPWM1_RELOAD2_IRQHandler /* flexpwm1_reload2 interrupt */ + .long FLEXPWM1_COMPARE3_IRQHandler /* flexpwm1_compare3 interrupt */ + .long FLEXPWM1_RELOAD3_IRQHandler /* flexpwm1_reload3 interrupt */ + .long ENC0_COMPARE_IRQHandler /* enc0_compare interrupt */ + .long ENC0_HOME_IRQHandler /* enc0_home interrupt */ + .long ENC0_WDG_IRQHandler /* enc0_wdg interrupt */ + .long ENC0_IDX_IRQHandler /* enc0_idx interrupt */ + .long ENC1_COMPARE_IRQHandler /* enc1_compare interrupt */ + .long ENC1_HOME_IRQHandler /* enc1_home interrupt */ + .long ENC1_WDG_IRQHandler /* enc1_wdg interrupt */ + .long ENC1_IDX_IRQHandler /* enc1_idx interrupt */ + .long ITRC0_IRQHandler /* itrc0 interrupt */ + .long Reserved127_IRQHandler /* Reserved interrupt */ + .long CSSV2_ERR_IRQHandler /* cssv2_err interrupt */ + .long PKC_ERR_IRQHandler /* pkc_err interrupt */ + .long Reserved130_IRQHandler /* Reserved interrupt */ + .long Reserved131_IRQHandler /* Reserved interrupt */ + .long Reserved132_IRQHandler /* Reserved interrupt */ + .long Reserved133_IRQHandler /* Reserved interrupt */ + .long FLASH_IRQHandler /* flash interrupt */ + .long RAM_PARITY_ECC_ERR_IRQHandler /* ram_parity_ecc_err interrupt */ + + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =__StackLimit + msr msplim, r0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak DMIC_IRQHandler + .type DMIC_IRQHandler, %function +DMIC_IRQHandler: + ldr r0,=DMIC_DriverIRQHandler + bx r0 + .size DMIC_IRQHandler, . - DMIC_IRQHandler + + .align 1 + .thumb_func + .weak HWVAD0_IRQHandler + .type HWVAD0_IRQHandler, %function +HWVAD0_IRQHandler: + ldr r0,=HWVAD0_DriverIRQHandler + bx r0 + .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak EZH_ARCH_B0_IRQHandler + .type EZH_ARCH_B0_IRQHandler, %function +EZH_ARCH_B0_IRQHandler: + ldr r0,=EZH_ARCH_B0_DriverIRQHandler + bx r0 + .size EZH_ARCH_B0_IRQHandler, . - EZH_ARCH_B0_IRQHandler + + .align 1 + .thumb_func + .weak WAKEUP_IRQHandler + .type WAKEUP_IRQHandler, %function +WAKEUP_IRQHandler: + ldr r0,=WAKEUP_DriverIRQHandler + bx r0 + .size WAKEUP_IRQHandler, . - WAKEUP_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak FlexSPI0_IRQHandler + .type FlexSPI0_IRQHandler, %function +FlexSPI0_IRQHandler: + ldr r0,=FlexSPI0_DriverIRQHandler + bx r0 + .size FlexSPI0_IRQHandler, . - FlexSPI0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak Reserved58_IRQHandler + .type Reserved58_IRQHandler, %function +Reserved58_IRQHandler: + ldr r0,=Reserved58_DriverIRQHandler + bx r0 + .size Reserved58_IRQHandler, . - Reserved58_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ0_IRQHandler + .type CAN0_IRQ0_IRQHandler, %function +CAN0_IRQ0_IRQHandler: + ldr r0,=CAN0_IRQ0_DriverIRQHandler + bx r0 + .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ1_IRQHandler + .type CAN0_IRQ1_IRQHandler, %function +CAN0_IRQ1_IRQHandler: + ldr r0,=CAN0_IRQ1_DriverIRQHandler + bx r0 + .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak SPI_FILTER_IRQHandler + .type SPI_FILTER_IRQHandler, %function +SPI_FILTER_IRQHandler: + ldr r0,=SPI_FILTER_DriverIRQHandler + bx r0 + .size SPI_FILTER_IRQHandler, . - SPI_FILTER_IRQHandler + + .align 1 + .thumb_func + .weak Reserved62_IRQHandler + .type Reserved62_IRQHandler, %function +Reserved62_IRQHandler: + ldr r0,=Reserved62_DriverIRQHandler + bx r0 + .size Reserved62_IRQHandler, . - Reserved62_IRQHandler + + .align 1 + .thumb_func + .weak Reserved63_IRQHandler + .type Reserved63_IRQHandler, %function +Reserved63_IRQHandler: + ldr r0,=Reserved63_DriverIRQHandler + bx r0 + .size Reserved63_IRQHandler, . - Reserved63_IRQHandler + + .align 1 + .thumb_func + .weak Reserved64_IRQHandler + .type Reserved64_IRQHandler, %function +Reserved64_IRQHandler: + ldr r0,=Reserved64_DriverIRQHandler + bx r0 + .size Reserved64_IRQHandler, . - Reserved64_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak Freqme_IRQHandler + .type Freqme_IRQHandler, %function +Freqme_IRQHandler: + ldr r0,=Freqme_DriverIRQHandler + bx r0 + .size Freqme_IRQHandler, . - Freqme_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak SHA_IRQHandler + .type SHA_IRQHandler, %function +SHA_IRQHandler: + ldr r0,=SHA_DriverIRQHandler + bx r0 + .size SHA_IRQHandler, . - SHA_IRQHandler + + .align 1 + .thumb_func + .weak PKC_IRQHandler + .type PKC_IRQHandler, %function +PKC_IRQHandler: + ldr r0,=PKC_DriverIRQHandler + bx r0 + .size PKC_IRQHandler, . - PKC_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak POWERQUAD_IRQHandler + .type POWERQUAD_IRQHandler, %function +POWERQUAD_IRQHandler: + ldr r0,=POWERQUAD_DriverIRQHandler + bx r0 + .size POWERQUAD_IRQHandler, . - POWERQUAD_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + + .align 1 + .thumb_func + .weak CDOG_IRQHandler + .type CDOG_IRQHandler, %function +CDOG_IRQHandler: + ldr r0,=CDOG_DriverIRQHandler + bx r0 + .size CDOG_IRQHandler, . - CDOG_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved79_IRQHandler + .type Reserved79_IRQHandler, %function +Reserved79_IRQHandler: + ldr r0,=Reserved79_DriverIRQHandler + bx r0 + .size Reserved79_IRQHandler, . - Reserved79_IRQHandler + + .align 1 + .thumb_func + .weak Reserved80_IRQHandler + .type Reserved80_IRQHandler, %function +Reserved80_IRQHandler: + ldr r0,=Reserved80_DriverIRQHandler + bx r0 + .size Reserved80_IRQHandler, . - Reserved80_IRQHandler + + .align 1 + .thumb_func + .weak CSS_IRQ1_IRQHandler + .type CSS_IRQ1_IRQHandler, %function +CSS_IRQ1_IRQHandler: + ldr r0,=CSS_IRQ1_DriverIRQHandler + bx r0 + .size CSS_IRQ1_IRQHandler, . - CSS_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak Tamper_IRQHandler + .type Tamper_IRQHandler, %function +Tamper_IRQHandler: + ldr r0,=Tamper_DriverIRQHandler + bx r0 + .size Tamper_IRQHandler, . - Tamper_IRQHandler + + .align 1 + .thumb_func + .weak Analog_Glitch_IRQHandler + .type Analog_Glitch_IRQHandler, %function +Analog_Glitch_IRQHandler: + ldr r0,=Analog_Glitch_DriverIRQHandler + bx r0 + .size Analog_Glitch_IRQHandler, . - Analog_Glitch_IRQHandler + + .align 1 + .thumb_func + .weak Reserved84_IRQHandler + .type Reserved84_IRQHandler, %function +Reserved84_IRQHandler: + ldr r0,=Reserved84_DriverIRQHandler + bx r0 + .size Reserved84_IRQHandler, . - Reserved84_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak Reserved87_IRQHandler + .type Reserved87_IRQHandler, %function +Reserved87_IRQHandler: + ldr r0,=Reserved87_DriverIRQHandler + bx r0 + .size Reserved87_IRQHandler, . - Reserved87_IRQHandler + + .align 1 + .thumb_func + .weak Reserved88_IRQHandler + .type Reserved88_IRQHandler, %function +Reserved88_IRQHandler: + ldr r0,=Reserved88_DriverIRQHandler + bx r0 + .size Reserved88_IRQHandler, . - Reserved88_IRQHandler + + .align 1 + .thumb_func + .weak Reserved89_IRQHandler + .type Reserved89_IRQHandler, %function +Reserved89_IRQHandler: + ldr r0,=Reserved89_DriverIRQHandler + bx r0 + .size Reserved89_IRQHandler, . - Reserved89_IRQHandler + + .align 1 + .thumb_func + .weak DAC0_IRQHandler + .type DAC0_IRQHandler, %function +DAC0_IRQHandler: + ldr r0,=DAC0_DriverIRQHandler + bx r0 + .size DAC0_IRQHandler, . - DAC0_IRQHandler + + .align 1 + .thumb_func + .weak DAC1_IRQHandler + .type DAC1_IRQHandler, %function +DAC1_IRQHandler: + ldr r0,=DAC1_DriverIRQHandler + bx r0 + .size DAC1_IRQHandler, . - DAC1_IRQHandler + + .align 1 + .thumb_func + .weak DAC2_IRQHandler + .type DAC2_IRQHandler, %function +DAC2_IRQHandler: + ldr r0,=DAC2_DriverIRQHandler + bx r0 + .size DAC2_IRQHandler, . - DAC2_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP0_IRQHandler + .type HSCMP0_IRQHandler, %function +HSCMP0_IRQHandler: + ldr r0,=HSCMP0_DriverIRQHandler + bx r0 + .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP1_IRQHandler + .type HSCMP1_IRQHandler, %function +HSCMP1_IRQHandler: + ldr r0,=HSCMP1_DriverIRQHandler + bx r0 + .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP2_IRQHandler + .type HSCMP2_IRQHandler, %function +HSCMP2_IRQHandler: + ldr r0,=HSCMP2_DriverIRQHandler + bx r0 + .size HSCMP2_IRQHandler, . - HSCMP2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_CAPTURE_IRQHandler + .type FLEXPWM0_CAPTURE_IRQHandler, %function +FLEXPWM0_CAPTURE_IRQHandler: + ldr r0,=FLEXPWM0_CAPTURE_DriverIRQHandler + bx r0 + .size FLEXPWM0_CAPTURE_IRQHandler, . - FLEXPWM0_CAPTURE_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE0_IRQHandler + .type FLEXPWM0_COMPARE0_IRQHandler, %function +FLEXPWM0_COMPARE0_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE0_IRQHandler, . - FLEXPWM0_COMPARE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD0_IRQHandler + .type FLEXPWM0_RELOAD0_IRQHandler, %function +FLEXPWM0_RELOAD0_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD0_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD0_IRQHandler, . - FLEXPWM0_RELOAD0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE1_IRQHandler + .type FLEXPWM0_COMPARE1_IRQHandler, %function +FLEXPWM0_COMPARE1_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE1_IRQHandler, . - FLEXPWM0_COMPARE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD1_IRQHandler + .type FLEXPWM0_RELOAD1_IRQHandler, %function +FLEXPWM0_RELOAD1_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD1_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD1_IRQHandler, . - FLEXPWM0_RELOAD1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE2_IRQHandler + .type FLEXPWM0_COMPARE2_IRQHandler, %function +FLEXPWM0_COMPARE2_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE2_IRQHandler, . - FLEXPWM0_COMPARE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD2_IRQHandler + .type FLEXPWM0_RELOAD2_IRQHandler, %function +FLEXPWM0_RELOAD2_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD2_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD2_IRQHandler, . - FLEXPWM0_RELOAD2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_COMPARE3_IRQHandler + .type FLEXPWM0_COMPARE3_IRQHandler, %function +FLEXPWM0_COMPARE3_IRQHandler: + ldr r0,=FLEXPWM0_COMPARE3_DriverIRQHandler + bx r0 + .size FLEXPWM0_COMPARE3_IRQHandler, . - FLEXPWM0_COMPARE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD3_IRQHandler + .type FLEXPWM0_RELOAD3_IRQHandler, %function +FLEXPWM0_RELOAD3_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD3_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD3_IRQHandler, . - FLEXPWM0_RELOAD3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_CAPTURE_IRQHandler + .type FLEXPWM1_CAPTURE_IRQHandler, %function +FLEXPWM1_CAPTURE_IRQHandler: + ldr r0,=FLEXPWM1_CAPTURE_DriverIRQHandler + bx r0 + .size FLEXPWM1_CAPTURE_IRQHandler, . - FLEXPWM1_CAPTURE_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_FAULT_IRQHandler + .type FLEXPWM1_FAULT_IRQHandler, %function +FLEXPWM1_FAULT_IRQHandler: + ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD_ERROR_IRQHandler + .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function +FLEXPWM1_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE0_IRQHandler + .type FLEXPWM1_COMPARE0_IRQHandler, %function +FLEXPWM1_COMPARE0_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE0_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE0_IRQHandler, . - FLEXPWM1_COMPARE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD0_IRQHandler + .type FLEXPWM1_RELOAD0_IRQHandler, %function +FLEXPWM1_RELOAD0_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD0_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD0_IRQHandler, . - FLEXPWM1_RELOAD0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE1_IRQHandler + .type FLEXPWM1_COMPARE1_IRQHandler, %function +FLEXPWM1_COMPARE1_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE1_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE1_IRQHandler, . - FLEXPWM1_COMPARE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD1_IRQHandler + .type FLEXPWM1_RELOAD1_IRQHandler, %function +FLEXPWM1_RELOAD1_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD1_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD1_IRQHandler, . - FLEXPWM1_RELOAD1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE2_IRQHandler + .type FLEXPWM1_COMPARE2_IRQHandler, %function +FLEXPWM1_COMPARE2_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE2_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE2_IRQHandler, . - FLEXPWM1_COMPARE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD2_IRQHandler + .type FLEXPWM1_RELOAD2_IRQHandler, %function +FLEXPWM1_RELOAD2_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD2_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD2_IRQHandler, . - FLEXPWM1_RELOAD2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_COMPARE3_IRQHandler + .type FLEXPWM1_COMPARE3_IRQHandler, %function +FLEXPWM1_COMPARE3_IRQHandler: + ldr r0,=FLEXPWM1_COMPARE3_DriverIRQHandler + bx r0 + .size FLEXPWM1_COMPARE3_IRQHandler, . - FLEXPWM1_COMPARE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD3_IRQHandler + .type FLEXPWM1_RELOAD3_IRQHandler, %function +FLEXPWM1_RELOAD3_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD3_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD3_IRQHandler, . - FLEXPWM1_RELOAD3_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_COMPARE_IRQHandler + .type ENC0_COMPARE_IRQHandler, %function +ENC0_COMPARE_IRQHandler: + ldr r0,=ENC0_COMPARE_DriverIRQHandler + bx r0 + .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_HOME_IRQHandler + .type ENC0_HOME_IRQHandler, %function +ENC0_HOME_IRQHandler: + ldr r0,=ENC0_HOME_DriverIRQHandler + bx r0 + .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_WDG_IRQHandler + .type ENC0_WDG_IRQHandler, %function +ENC0_WDG_IRQHandler: + ldr r0,=ENC0_WDG_DriverIRQHandler + bx r0 + .size ENC0_WDG_IRQHandler, . - ENC0_WDG_IRQHandler + + .align 1 + .thumb_func + .weak ENC0_IDX_IRQHandler + .type ENC0_IDX_IRQHandler, %function +ENC0_IDX_IRQHandler: + ldr r0,=ENC0_IDX_DriverIRQHandler + bx r0 + .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_COMPARE_IRQHandler + .type ENC1_COMPARE_IRQHandler, %function +ENC1_COMPARE_IRQHandler: + ldr r0,=ENC1_COMPARE_DriverIRQHandler + bx r0 + .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_HOME_IRQHandler + .type ENC1_HOME_IRQHandler, %function +ENC1_HOME_IRQHandler: + ldr r0,=ENC1_HOME_DriverIRQHandler + bx r0 + .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_WDG_IRQHandler + .type ENC1_WDG_IRQHandler, %function +ENC1_WDG_IRQHandler: + ldr r0,=ENC1_WDG_DriverIRQHandler + bx r0 + .size ENC1_WDG_IRQHandler, . - ENC1_WDG_IRQHandler + + .align 1 + .thumb_func + .weak ENC1_IDX_IRQHandler + .type ENC1_IDX_IRQHandler, %function +ENC1_IDX_IRQHandler: + ldr r0,=ENC1_IDX_DriverIRQHandler + bx r0 + .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ITRC0_IRQHandler + .type ITRC0_IRQHandler, %function +ITRC0_IRQHandler: + ldr r0,=ITRC0_DriverIRQHandler + bx r0 + .size ITRC0_IRQHandler, . - ITRC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved127_IRQHandler + .type Reserved127_IRQHandler, %function +Reserved127_IRQHandler: + ldr r0,=Reserved127_DriverIRQHandler + bx r0 + .size Reserved127_IRQHandler, . - Reserved127_IRQHandler + + .align 1 + .thumb_func + .weak CSSV2_ERR_IRQHandler + .type CSSV2_ERR_IRQHandler, %function +CSSV2_ERR_IRQHandler: + ldr r0,=CSSV2_ERR_DriverIRQHandler + bx r0 + .size CSSV2_ERR_IRQHandler, . - CSSV2_ERR_IRQHandler + + .align 1 + .thumb_func + .weak PKC_ERR_IRQHandler + .type PKC_ERR_IRQHandler, %function +PKC_ERR_IRQHandler: + ldr r0,=PKC_ERR_DriverIRQHandler + bx r0 + .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler + + .align 1 + .thumb_func + .weak Reserved130_IRQHandler + .type Reserved130_IRQHandler, %function +Reserved130_IRQHandler: + ldr r0,=Reserved130_DriverIRQHandler + bx r0 + .size Reserved130_IRQHandler, . - Reserved130_IRQHandler + + .align 1 + .thumb_func + .weak Reserved131_IRQHandler + .type Reserved131_IRQHandler, %function +Reserved131_IRQHandler: + ldr r0,=Reserved131_DriverIRQHandler + bx r0 + .size Reserved131_IRQHandler, . - Reserved131_IRQHandler + + .align 1 + .thumb_func + .weak Reserved132_IRQHandler + .type Reserved132_IRQHandler, %function +Reserved132_IRQHandler: + ldr r0,=Reserved132_DriverIRQHandler + bx r0 + .size Reserved132_IRQHandler, . - Reserved132_IRQHandler + + .align 1 + .thumb_func + .weak Reserved133_IRQHandler + .type Reserved133_IRQHandler, %function +Reserved133_IRQHandler: + ldr r0,=Reserved133_DriverIRQHandler + bx r0 + .size Reserved133_IRQHandler, . - Reserved133_IRQHandler + + .align 1 + .thumb_func + .weak FLASH_IRQHandler + .type FLASH_IRQHandler, %function +FLASH_IRQHandler: + ldr r0,=FLASH_DriverIRQHandler + bx r0 + .size FLASH_IRQHandler, . - FLASH_IRQHandler + + .align 1 + .thumb_func + .weak RAM_PARITY_ECC_ERR_IRQHandler + .type RAM_PARITY_ECC_ERR_IRQHandler, %function +RAM_PARITY_ECC_ERR_IRQHandler: + ldr r0,=RAM_PARITY_ECC_ERR_DriverIRQHandler + bx r0 + .size RAM_PARITY_ECC_ERR_IRQHandler, . - RAM_PARITY_ECC_ERR_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler GINT0_DriverIRQHandler + def_irq_handler GINT1_DriverIRQHandler + def_irq_handler PIN_INT0_DriverIRQHandler + def_irq_handler PIN_INT1_DriverIRQHandler + def_irq_handler PIN_INT2_DriverIRQHandler + def_irq_handler PIN_INT3_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler SCT0_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler FLEXCOMM0_DriverIRQHandler + def_irq_handler FLEXCOMM1_DriverIRQHandler + def_irq_handler FLEXCOMM2_DriverIRQHandler + def_irq_handler FLEXCOMM3_DriverIRQHandler + def_irq_handler FLEXCOMM4_DriverIRQHandler + def_irq_handler FLEXCOMM5_DriverIRQHandler + def_irq_handler FLEXCOMM6_DriverIRQHandler + def_irq_handler FLEXCOMM7_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler ADC1_DriverIRQHandler + def_irq_handler ACMP_DriverIRQHandler + def_irq_handler DMIC_DriverIRQHandler + def_irq_handler HWVAD0_DriverIRQHandler + def_irq_handler USB0_NEEDCLK_DriverIRQHandler + def_irq_handler USB0_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler EZH_ARCH_B0_DriverIRQHandler + def_irq_handler WAKEUP_DriverIRQHandler + def_irq_handler PIN_INT4_DriverIRQHandler + def_irq_handler PIN_INT5_DriverIRQHandler + def_irq_handler PIN_INT6_DriverIRQHandler + def_irq_handler PIN_INT7_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler FlexSPI0_DriverIRQHandler + def_irq_handler Reserved56_DriverIRQHandler + def_irq_handler Reserved57_DriverIRQHandler + def_irq_handler Reserved58_DriverIRQHandler + def_irq_handler CAN0_IRQ0_DriverIRQHandler + def_irq_handler CAN0_IRQ1_DriverIRQHandler + def_irq_handler SPI_FILTER_DriverIRQHandler + def_irq_handler Reserved62_DriverIRQHandler + def_irq_handler Reserved63_DriverIRQHandler + def_irq_handler Reserved64_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler + def_irq_handler Freqme_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler SHA_DriverIRQHandler + def_irq_handler PKC_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler POWERQUAD_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler FLEXCOMM8_DriverIRQHandler + def_irq_handler CDOG_DriverIRQHandler + def_irq_handler Reserved77_DriverIRQHandler + def_irq_handler I3C0_DriverIRQHandler + def_irq_handler Reserved79_DriverIRQHandler + def_irq_handler Reserved80_DriverIRQHandler + def_irq_handler CSS_IRQ1_DriverIRQHandler + def_irq_handler Tamper_DriverIRQHandler + def_irq_handler Analog_Glitch_DriverIRQHandler + def_irq_handler Reserved84_DriverIRQHandler + def_irq_handler Reserved85_DriverIRQHandler + def_irq_handler Reserved86_DriverIRQHandler + def_irq_handler Reserved87_DriverIRQHandler + def_irq_handler Reserved88_DriverIRQHandler + def_irq_handler Reserved89_DriverIRQHandler + def_irq_handler DAC0_DriverIRQHandler + def_irq_handler DAC1_DriverIRQHandler + def_irq_handler DAC2_DriverIRQHandler + def_irq_handler HSCMP0_DriverIRQHandler + def_irq_handler HSCMP1_DriverIRQHandler + def_irq_handler HSCMP2_DriverIRQHandler + def_irq_handler FLEXPWM0_CAPTURE_DriverIRQHandler + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM0_COMPARE0_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD0_DriverIRQHandler + def_irq_handler FLEXPWM0_COMPARE1_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD1_DriverIRQHandler + def_irq_handler FLEXPWM0_COMPARE2_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD2_DriverIRQHandler + def_irq_handler FLEXPWM0_COMPARE3_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD3_DriverIRQHandler + def_irq_handler FLEXPWM1_CAPTURE_DriverIRQHandler + def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM1_COMPARE0_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD0_DriverIRQHandler + def_irq_handler FLEXPWM1_COMPARE1_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD1_DriverIRQHandler + def_irq_handler FLEXPWM1_COMPARE2_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD2_DriverIRQHandler + def_irq_handler FLEXPWM1_COMPARE3_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD3_DriverIRQHandler + def_irq_handler ENC0_COMPARE_DriverIRQHandler + def_irq_handler ENC0_HOME_DriverIRQHandler + def_irq_handler ENC0_WDG_DriverIRQHandler + def_irq_handler ENC0_IDX_DriverIRQHandler + def_irq_handler ENC1_COMPARE_DriverIRQHandler + def_irq_handler ENC1_HOME_DriverIRQHandler + def_irq_handler ENC1_WDG_DriverIRQHandler + def_irq_handler ENC1_IDX_DriverIRQHandler + def_irq_handler ITRC0_DriverIRQHandler + def_irq_handler Reserved127_DriverIRQHandler + def_irq_handler CSSV2_ERR_DriverIRQHandler + def_irq_handler PKC_ERR_DriverIRQHandler + def_irq_handler Reserved130_DriverIRQHandler + def_irq_handler Reserved131_DriverIRQHandler + def_irq_handler Reserved132_DriverIRQHandler + def_irq_handler Reserved133_DriverIRQHandler + def_irq_handler FLASH_DriverIRQHandler + def_irq_handler RAM_PARITY_ECC_ERR_DriverIRQHandler + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_flash.icf b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_flash.icf new file mode 100644 index 0000000000000000000000000000000000000000..26a5faafe5973fcce143df196ccbf413e37c1e3e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_flash.icf @@ -0,0 +1,103 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +if (isdefinedsymbol(__pkc__)) { + define symbol retention_RAMsize = 0x00004000; /* SRAM A(16K) reserved for pkc */ +} else if (isdefinedsymbol(__power_down__)) { + define symbol retention_RAMsize = 0x00000604; /* The first 0x604 bytes reserved to CPU retention for power down mode */ +} else { + define symbol retention_RAMsize = 0x00000000; +} + +if (isdefinedsymbol(__powerquad__)) { + define symbol powerquad_RAMsize = 0x00004000; /* SRAM E(16K) reserved for powerquad */ +} else { + define symbol powerquad_RAMsize = 0x00000000; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0003D7FF; + +define symbol m_data_start = 0x20000000 + retention_RAMsize; +define symbol m_data_end = 0x2001BFFF - powerquad_RAMsize; + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04003FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_ram.icf b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_ram.icf new file mode 100644 index 0000000000000000000000000000000000000000..3c235631ab792f6361c101217b6e1fdbdf11bf11 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/LPC55S36_ram.icf @@ -0,0 +1,100 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +if (isdefinedsymbol(__pkc__)) { + define symbol retention_RAMsize = 0x00004000; /* SRAM A(16K) reserved for pkc */ +} else if (isdefinedsymbol(__power_down__)) { + define symbol retention_RAMsize = 0x00000604; /* The first 0x604 bytes reserved to CPU retention for power down mode */ +} else { + define symbol retention_RAMsize = 0x00000000; +} + +if (isdefinedsymbol(__powerquad__)) { + define symbol powerquad_RAMsize = 0x00004000; /* SRAM E(16K) reserved for powerquad */ +} else { + define symbol powerquad_RAMsize = 0x00000000; +} + +define symbol m_interrupts_start = 0x20000000 + retention_RAMsize; +define symbol m_interrupts_end = 0x200003FF + retention_RAMsize; + +define symbol m_text_start = 0x20000400 + retention_RAMsize; +define symbol m_text_end = 0x2001BFFF - powerquad_RAMsize; + +define symbol m_data_start = 0x04000000; +define symbol m_data_end = 0x04003FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/startup_LPC55S36.s b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/startup_LPC55S36.s new file mode 100644 index 0000000000000000000000000000000000000000..0672289d995d733206bc63c5a2280879abd4d633 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/iar/startup_LPC55S36.s @@ -0,0 +1,1115 @@ +;/***************************************************************************** +; * @file: startup_LPC55S36.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File +; * LPC55S36 +; * @version: 1.1 +; * @date: 2021-8-4 +; *---------------------------------------------------------------------------- +; * +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2021 NXP +; All rights reserved. +; +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD ADC1_IRQHandler ; ADC1 + DCD ACMP_IRQHandler ; ACMP interrupts + DCD DMIC_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD EZH_ARCH_B0_IRQHandler ; EZH interrupt + DCD WAKEUP_IRQHandler ; Wakeup interrupt + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts + DCD FlexSPI0_IRQHandler ; FlexSPI interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD Reserved58_IRQHandler ; Reserved interrupt + DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 + DCD SPI_FILTER_IRQHandler ; SPI Filter interrupt + DCD Reserved62_IRQHandler ; Reserved interrupt + DCD Reserved63_IRQHandler ; Reserved interrupt + DCD Reserved64_IRQHandler ; Reserved interrupt + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT00 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT01 interrupt + DCD Freqme_IRQHandler ; frequency measure interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD SHA_IRQHandler ; SHA interrupt + DCD PKC_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD POWERQUAD_IRQHandler ; PowerQuad interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; LSPI_HS interrupt + DCD CDOG_IRQHandler ; CodeWDG interrupt + DCD Reserved77_IRQHandler ; Reserved interrupt + DCD I3C0_IRQHandler ; I3C interrupt + DCD Reserved79_IRQHandler ; Reserved interrupt + DCD Reserved80_IRQHandler ; Reserved interrupt + DCD CSS_IRQ1_IRQHandler ; CSS_IRQ1 + DCD Tamper_IRQHandler ; Tamper + DCD Analog_Glitch_IRQHandler ; Analog_Glitch + DCD Reserved84_IRQHandler ; Reserved interrupt + DCD Reserved85_IRQHandler ; Reserved interrupt + DCD Reserved86_IRQHandler ; Reserved interrupt + DCD Reserved87_IRQHandler ; Reserved interrupt + DCD Reserved88_IRQHandler ; Reserved interrupt + DCD Reserved89_IRQHandler ; Reserved interrupt + DCD DAC0_IRQHandler ; dac0 interrupt + DCD DAC1_IRQHandler ; dac1 interrupt + DCD DAC2_IRQHandler ; dac2 interrupt + DCD HSCMP0_IRQHandler ; hscmp0 interrupt + DCD HSCMP1_IRQHandler ; hscmp1 interrupt + DCD HSCMP2_IRQHandler ; hscmp2 interrupt + DCD FLEXPWM0_CAPTURE_IRQHandler ; flexpwm0_capture interrupt + DCD FLEXPWM0_FAULT_IRQHandler ; flexpwm0_fault interrupt + DCD FLEXPWM0_RELOAD_ERROR_IRQHandler ; flexpwm0_reload_error interrupt + DCD FLEXPWM0_COMPARE0_IRQHandler ; flexpwm0_compare0 interrupt + DCD FLEXPWM0_RELOAD0_IRQHandler ; flexpwm0_reload0 interrupt + DCD FLEXPWM0_COMPARE1_IRQHandler ; flexpwm0_compare1 interrupt + DCD FLEXPWM0_RELOAD1_IRQHandler ; flexpwm0_reload1 interrupt + DCD FLEXPWM0_COMPARE2_IRQHandler ; flexpwm0_compare2 interrupt + DCD FLEXPWM0_RELOAD2_IRQHandler ; flexpwm0_reload2 interrupt + DCD FLEXPWM0_COMPARE3_IRQHandler ; flexpwm0_compare3 interrupt + DCD FLEXPWM0_RELOAD3_IRQHandler ; flexpwm0_reload3 interrupt + DCD FLEXPWM1_CAPTURE_IRQHandler ; flexpwm1_capture interrupt + DCD FLEXPWM1_FAULT_IRQHandler ; flexpwm1_fault interrupt + DCD FLEXPWM1_RELOAD_ERROR_IRQHandler ; flexpwm1_reload_error interrupt + DCD FLEXPWM1_COMPARE0_IRQHandler ; flexpwm1_compare0 interrupt + DCD FLEXPWM1_RELOAD0_IRQHandler ; flexpwm1_reload0 interrupt + DCD FLEXPWM1_COMPARE1_IRQHandler ; flexpwm1_compare1 interrupt + DCD FLEXPWM1_RELOAD1_IRQHandler ; flexpwm1_reload1 interrupt + DCD FLEXPWM1_COMPARE2_IRQHandler ; flexpwm1_compare2 interrupt + DCD FLEXPWM1_RELOAD2_IRQHandler ; flexpwm1_reload2 interrupt + DCD FLEXPWM1_COMPARE3_IRQHandler ; flexpwm1_compare3 interrupt + DCD FLEXPWM1_RELOAD3_IRQHandler ; flexpwm1_reload3 interrupt + DCD ENC0_COMPARE_IRQHandler ; enc0_compare interrupt + DCD ENC0_HOME_IRQHandler ; enc0_home interrupt + DCD ENC0_WDG_IRQHandler ; enc0_wdg interrupt + DCD ENC0_IDX_IRQHandler ; enc0_idx interrupt + DCD ENC1_COMPARE_IRQHandler ; enc1_compare interrupt + DCD ENC1_HOME_IRQHandler ; enc1_home interrupt + DCD ENC1_WDG_IRQHandler ; enc1_wdg interrupt + DCD ENC1_IDX_IRQHandler ; enc1_idx interrupt + DCD ITRC0_IRQHandler ; itrc0 interrupt + DCD Reserved127_IRQHandler ; Reserved interrupt + DCD CSSV2_ERR_IRQHandler ; cssv2_err interrupt + DCD PKC_ERR_IRQHandler ; pkc_err interrupt + DCD Reserved130_IRQHandler ; Reserved interrupt + DCD Reserved131_IRQHandler ; Reserved interrupt + DCD Reserved132_IRQHandler ; Reserved interrupt + DCD Reserved133_IRQHandler ; Reserved interrupt + DCD FLASH_IRQHandler ; flash interrupt + DCD RAM_PARITY_ECC_ERR_IRQHandler ; ram_parity_ecc_err interrupt +__Vectors_End + + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =sfb(CSTACK) + MSR MSPLIM, R0 + CPSIE I ; Unmask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_IRQHandler + LDR R0, =ADC0_DriverIRQHandler + BX R0 + PUBWEAK ADC1_IRQHandler + PUBWEAK ADC1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC1_IRQHandler + LDR R0, =ADC1_DriverIRQHandler + BX R0 + PUBWEAK ACMP_IRQHandler + PUBWEAK ACMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ACMP_IRQHandler + LDR R0, =ACMP_DriverIRQHandler + BX R0 + PUBWEAK DMIC_IRQHandler + PUBWEAK DMIC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC_IRQHandler + LDR R0, =DMIC_DriverIRQHandler + BX R0 + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK EZH_ARCH_B0_IRQHandler + PUBWEAK EZH_ARCH_B0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EZH_ARCH_B0_IRQHandler + LDR R0, =EZH_ARCH_B0_DriverIRQHandler + BX R0 + PUBWEAK WAKEUP_IRQHandler + PUBWEAK WAKEUP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WAKEUP_IRQHandler + LDR R0, =WAKEUP_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK OS_EVENT_IRQHandler + PUBWEAK OS_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OS_EVENT_IRQHandler + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + PUBWEAK FlexSPI0_IRQHandler + PUBWEAK FlexSPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FlexSPI0_IRQHandler + LDR R0, =FlexSPI0_DriverIRQHandler + BX R0 + PUBWEAK Reserved56_IRQHandler + PUBWEAK Reserved56_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved56_IRQHandler + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + PUBWEAK Reserved57_IRQHandler + PUBWEAK Reserved57_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved57_IRQHandler + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + PUBWEAK Reserved58_IRQHandler + PUBWEAK Reserved58_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved58_IRQHandler + LDR R0, =Reserved58_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK SPI_FILTER_IRQHandler + PUBWEAK SPI_FILTER_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI_FILTER_IRQHandler + LDR R0, =SPI_FILTER_DriverIRQHandler + BX R0 + PUBWEAK Reserved62_IRQHandler + PUBWEAK Reserved62_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved62_IRQHandler + LDR R0, =Reserved62_DriverIRQHandler + BX R0 + PUBWEAK Reserved63_IRQHandler + PUBWEAK Reserved63_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved63_IRQHandler + LDR R0, =Reserved63_DriverIRQHandler + BX R0 + PUBWEAK Reserved64_IRQHandler + PUBWEAK Reserved64_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved64_IRQHandler + LDR R0, =Reserved64_DriverIRQHandler + BX R0 + PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler + PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_HYPERVISOR_CALL_IRQHandler + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ0_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ1_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK Freqme_IRQHandler + PUBWEAK Freqme_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Freqme_IRQHandler + LDR R0, =Freqme_DriverIRQHandler + BX R0 + PUBWEAK SEC_VIO_IRQHandler + PUBWEAK SEC_VIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_VIO_IRQHandler + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + PUBWEAK PKC_IRQHandler + PUBWEAK PKC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PKC_IRQHandler + LDR R0, =PKC_DriverIRQHandler + BX R0 + PUBWEAK PUF_IRQHandler + PUBWEAK PUF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PUF_IRQHandler + LDR R0, =PUF_DriverIRQHandler + BX R0 + PUBWEAK POWERQUAD_IRQHandler + PUBWEAK POWERQUAD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +POWERQUAD_IRQHandler + LDR R0, =POWERQUAD_DriverIRQHandler + BX R0 + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + PUBWEAK CDOG_IRQHandler + PUBWEAK CDOG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CDOG_IRQHandler + LDR R0, =CDOG_DriverIRQHandler + BX R0 + PUBWEAK Reserved77_IRQHandler + PUBWEAK Reserved77_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved77_IRQHandler + LDR R0, =Reserved77_DriverIRQHandler + BX R0 + PUBWEAK I3C0_IRQHandler + PUBWEAK I3C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I3C0_IRQHandler + LDR R0, =I3C0_DriverIRQHandler + BX R0 + PUBWEAK Reserved79_IRQHandler + PUBWEAK Reserved79_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved79_IRQHandler + LDR R0, =Reserved79_DriverIRQHandler + BX R0 + PUBWEAK Reserved80_IRQHandler + PUBWEAK Reserved80_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved80_IRQHandler + LDR R0, =Reserved80_DriverIRQHandler + BX R0 + PUBWEAK CSS_IRQ1_IRQHandler + PUBWEAK CSS_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CSS_IRQ1_IRQHandler + LDR R0, =CSS_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK Tamper_IRQHandler + PUBWEAK Tamper_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Tamper_IRQHandler + LDR R0, =Tamper_DriverIRQHandler + BX R0 + PUBWEAK Analog_Glitch_IRQHandler + PUBWEAK Analog_Glitch_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Analog_Glitch_IRQHandler + LDR R0, =Analog_Glitch_DriverIRQHandler + BX R0 + PUBWEAK Reserved84_IRQHandler + PUBWEAK Reserved84_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved84_IRQHandler + LDR R0, =Reserved84_DriverIRQHandler + BX R0 + PUBWEAK Reserved85_IRQHandler + PUBWEAK Reserved85_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved85_IRQHandler + LDR R0, =Reserved85_DriverIRQHandler + BX R0 + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved86_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved86_IRQHandler + LDR R0, =Reserved86_DriverIRQHandler + BX R0 + PUBWEAK Reserved87_IRQHandler + PUBWEAK Reserved87_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved87_IRQHandler + LDR R0, =Reserved87_DriverIRQHandler + BX R0 + PUBWEAK Reserved88_IRQHandler + PUBWEAK Reserved88_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved88_IRQHandler + LDR R0, =Reserved88_DriverIRQHandler + BX R0 + PUBWEAK Reserved89_IRQHandler + PUBWEAK Reserved89_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved89_IRQHandler + LDR R0, =Reserved89_DriverIRQHandler + BX R0 + PUBWEAK DAC0_IRQHandler + PUBWEAK DAC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DAC0_IRQHandler + LDR R0, =DAC0_DriverIRQHandler + BX R0 + PUBWEAK DAC1_IRQHandler + PUBWEAK DAC1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DAC1_IRQHandler + LDR R0, =DAC1_DriverIRQHandler + BX R0 + PUBWEAK DAC2_IRQHandler + PUBWEAK DAC2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DAC2_IRQHandler + LDR R0, =DAC2_DriverIRQHandler + BX R0 + PUBWEAK HSCMP0_IRQHandler + PUBWEAK HSCMP0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HSCMP0_IRQHandler + LDR R0, =HSCMP0_DriverIRQHandler + BX R0 + PUBWEAK HSCMP1_IRQHandler + PUBWEAK HSCMP1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HSCMP1_IRQHandler + LDR R0, =HSCMP1_DriverIRQHandler + BX R0 + PUBWEAK HSCMP2_IRQHandler + PUBWEAK HSCMP2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HSCMP2_IRQHandler + LDR R0, =HSCMP2_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_CAPTURE_IRQHandler + PUBWEAK FLEXPWM0_CAPTURE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_CAPTURE_IRQHandler + LDR R0, =FLEXPWM0_CAPTURE_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_FAULT_IRQHandler + PUBWEAK FLEXPWM0_FAULT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_FAULT_IRQHandler + LDR R0, =FLEXPWM0_FAULT_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_RELOAD_ERROR_IRQHandler + PUBWEAK FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD_ERROR_IRQHandler + LDR R0, =FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_COMPARE0_IRQHandler + PUBWEAK FLEXPWM0_COMPARE0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_COMPARE0_IRQHandler + LDR R0, =FLEXPWM0_COMPARE0_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_RELOAD0_IRQHandler + PUBWEAK FLEXPWM0_RELOAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD0_IRQHandler + LDR R0, =FLEXPWM0_RELOAD0_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_COMPARE1_IRQHandler + PUBWEAK FLEXPWM0_COMPARE1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_COMPARE1_IRQHandler + LDR R0, =FLEXPWM0_COMPARE1_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_RELOAD1_IRQHandler + PUBWEAK FLEXPWM0_RELOAD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD1_IRQHandler + LDR R0, =FLEXPWM0_RELOAD1_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_COMPARE2_IRQHandler + PUBWEAK FLEXPWM0_COMPARE2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_COMPARE2_IRQHandler + LDR R0, =FLEXPWM0_COMPARE2_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_RELOAD2_IRQHandler + PUBWEAK FLEXPWM0_RELOAD2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD2_IRQHandler + LDR R0, =FLEXPWM0_RELOAD2_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_COMPARE3_IRQHandler + PUBWEAK FLEXPWM0_COMPARE3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_COMPARE3_IRQHandler + LDR R0, =FLEXPWM0_COMPARE3_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM0_RELOAD3_IRQHandler + PUBWEAK FLEXPWM0_RELOAD3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD3_IRQHandler + LDR R0, =FLEXPWM0_RELOAD3_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_CAPTURE_IRQHandler + PUBWEAK FLEXPWM1_CAPTURE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_CAPTURE_IRQHandler + LDR R0, =FLEXPWM1_CAPTURE_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_FAULT_IRQHandler + PUBWEAK FLEXPWM1_FAULT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_FAULT_IRQHandler + LDR R0, =FLEXPWM1_FAULT_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_RELOAD_ERROR_IRQHandler + PUBWEAK FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD_ERROR_IRQHandler + LDR R0, =FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_COMPARE0_IRQHandler + PUBWEAK FLEXPWM1_COMPARE0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_COMPARE0_IRQHandler + LDR R0, =FLEXPWM1_COMPARE0_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_RELOAD0_IRQHandler + PUBWEAK FLEXPWM1_RELOAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD0_IRQHandler + LDR R0, =FLEXPWM1_RELOAD0_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_COMPARE1_IRQHandler + PUBWEAK FLEXPWM1_COMPARE1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_COMPARE1_IRQHandler + LDR R0, =FLEXPWM1_COMPARE1_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_RELOAD1_IRQHandler + PUBWEAK FLEXPWM1_RELOAD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD1_IRQHandler + LDR R0, =FLEXPWM1_RELOAD1_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_COMPARE2_IRQHandler + PUBWEAK FLEXPWM1_COMPARE2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_COMPARE2_IRQHandler + LDR R0, =FLEXPWM1_COMPARE2_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_RELOAD2_IRQHandler + PUBWEAK FLEXPWM1_RELOAD2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD2_IRQHandler + LDR R0, =FLEXPWM1_RELOAD2_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_COMPARE3_IRQHandler + PUBWEAK FLEXPWM1_COMPARE3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_COMPARE3_IRQHandler + LDR R0, =FLEXPWM1_COMPARE3_DriverIRQHandler + BX R0 + PUBWEAK FLEXPWM1_RELOAD3_IRQHandler + PUBWEAK FLEXPWM1_RELOAD3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD3_IRQHandler + LDR R0, =FLEXPWM1_RELOAD3_DriverIRQHandler + BX R0 + PUBWEAK ENC0_COMPARE_IRQHandler + PUBWEAK ENC0_COMPARE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC0_COMPARE_IRQHandler + LDR R0, =ENC0_COMPARE_DriverIRQHandler + BX R0 + PUBWEAK ENC0_HOME_IRQHandler + PUBWEAK ENC0_HOME_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC0_HOME_IRQHandler + LDR R0, =ENC0_HOME_DriverIRQHandler + BX R0 + PUBWEAK ENC0_WDG_IRQHandler + PUBWEAK ENC0_WDG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC0_WDG_IRQHandler + LDR R0, =ENC0_WDG_DriverIRQHandler + BX R0 + PUBWEAK ENC0_IDX_IRQHandler + PUBWEAK ENC0_IDX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC0_IDX_IRQHandler + LDR R0, =ENC0_IDX_DriverIRQHandler + BX R0 + PUBWEAK ENC1_COMPARE_IRQHandler + PUBWEAK ENC1_COMPARE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC1_COMPARE_IRQHandler + LDR R0, =ENC1_COMPARE_DriverIRQHandler + BX R0 + PUBWEAK ENC1_HOME_IRQHandler + PUBWEAK ENC1_HOME_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC1_HOME_IRQHandler + LDR R0, =ENC1_HOME_DriverIRQHandler + BX R0 + PUBWEAK ENC1_WDG_IRQHandler + PUBWEAK ENC1_WDG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC1_WDG_IRQHandler + LDR R0, =ENC1_WDG_DriverIRQHandler + BX R0 + PUBWEAK ENC1_IDX_IRQHandler + PUBWEAK ENC1_IDX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENC1_IDX_IRQHandler + LDR R0, =ENC1_IDX_DriverIRQHandler + BX R0 + PUBWEAK ITRC0_IRQHandler + PUBWEAK ITRC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ITRC0_IRQHandler + LDR R0, =ITRC0_DriverIRQHandler + BX R0 + PUBWEAK Reserved127_IRQHandler + PUBWEAK Reserved127_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved127_IRQHandler + LDR R0, =Reserved127_DriverIRQHandler + BX R0 + PUBWEAK CSSV2_ERR_IRQHandler + PUBWEAK CSSV2_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CSSV2_ERR_IRQHandler + LDR R0, =CSSV2_ERR_DriverIRQHandler + BX R0 + PUBWEAK PKC_ERR_IRQHandler + PUBWEAK PKC_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PKC_ERR_IRQHandler + LDR R0, =PKC_ERR_DriverIRQHandler + BX R0 + PUBWEAK Reserved130_IRQHandler + PUBWEAK Reserved130_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved130_IRQHandler + LDR R0, =Reserved130_DriverIRQHandler + BX R0 + PUBWEAK Reserved131_IRQHandler + PUBWEAK Reserved131_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved131_IRQHandler + LDR R0, =Reserved131_DriverIRQHandler + BX R0 + PUBWEAK Reserved132_IRQHandler + PUBWEAK Reserved132_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved132_IRQHandler + LDR R0, =Reserved132_DriverIRQHandler + BX R0 + PUBWEAK Reserved133_IRQHandler + PUBWEAK Reserved133_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved133_IRQHandler + LDR R0, =Reserved133_DriverIRQHandler + BX R0 + PUBWEAK FLASH_IRQHandler + PUBWEAK FLASH_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLASH_IRQHandler + LDR R0, =FLASH_DriverIRQHandler + BX R0 + PUBWEAK RAM_PARITY_ECC_ERR_IRQHandler + PUBWEAK RAM_PARITY_ECC_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RAM_PARITY_ECC_ERR_IRQHandler + LDR R0, =RAM_PARITY_ECC_ERR_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +ADC1_DriverIRQHandler +ACMP_DriverIRQHandler +DMIC_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +EZH_ARCH_B0_DriverIRQHandler +WAKEUP_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +FlexSPI0_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +Reserved58_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +SPI_FILTER_DriverIRQHandler +Reserved62_DriverIRQHandler +Reserved63_DriverIRQHandler +Reserved64_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +Freqme_DriverIRQHandler +SEC_VIO_DriverIRQHandler +SHA_DriverIRQHandler +PKC_DriverIRQHandler +PUF_DriverIRQHandler +POWERQUAD_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +CDOG_DriverIRQHandler +Reserved77_DriverIRQHandler +I3C0_DriverIRQHandler +Reserved79_DriverIRQHandler +Reserved80_DriverIRQHandler +CSS_IRQ1_DriverIRQHandler +Tamper_DriverIRQHandler +Analog_Glitch_DriverIRQHandler +Reserved84_DriverIRQHandler +Reserved85_DriverIRQHandler +Reserved86_DriverIRQHandler +Reserved87_DriverIRQHandler +Reserved88_DriverIRQHandler +Reserved89_DriverIRQHandler +DAC0_DriverIRQHandler +DAC1_DriverIRQHandler +DAC2_DriverIRQHandler +HSCMP0_DriverIRQHandler +HSCMP1_DriverIRQHandler +HSCMP2_DriverIRQHandler +FLEXPWM0_CAPTURE_DriverIRQHandler +FLEXPWM0_FAULT_DriverIRQHandler +FLEXPWM0_RELOAD_ERROR_DriverIRQHandler +FLEXPWM0_COMPARE0_DriverIRQHandler +FLEXPWM0_RELOAD0_DriverIRQHandler +FLEXPWM0_COMPARE1_DriverIRQHandler +FLEXPWM0_RELOAD1_DriverIRQHandler +FLEXPWM0_COMPARE2_DriverIRQHandler +FLEXPWM0_RELOAD2_DriverIRQHandler +FLEXPWM0_COMPARE3_DriverIRQHandler +FLEXPWM0_RELOAD3_DriverIRQHandler +FLEXPWM1_CAPTURE_DriverIRQHandler +FLEXPWM1_FAULT_DriverIRQHandler +FLEXPWM1_RELOAD_ERROR_DriverIRQHandler +FLEXPWM1_COMPARE0_DriverIRQHandler +FLEXPWM1_RELOAD0_DriverIRQHandler +FLEXPWM1_COMPARE1_DriverIRQHandler +FLEXPWM1_RELOAD1_DriverIRQHandler +FLEXPWM1_COMPARE2_DriverIRQHandler +FLEXPWM1_RELOAD2_DriverIRQHandler +FLEXPWM1_COMPARE3_DriverIRQHandler +FLEXPWM1_RELOAD3_DriverIRQHandler +ENC0_COMPARE_DriverIRQHandler +ENC0_HOME_DriverIRQHandler +ENC0_WDG_DriverIRQHandler +ENC0_IDX_DriverIRQHandler +ENC1_COMPARE_DriverIRQHandler +ENC1_HOME_DriverIRQHandler +ENC1_WDG_DriverIRQHandler +ENC1_IDX_DriverIRQHandler +ITRC0_DriverIRQHandler +Reserved127_DriverIRQHandler +CSSV2_ERR_DriverIRQHandler +PKC_ERR_DriverIRQHandler +Reserved130_DriverIRQHandler +Reserved131_DriverIRQHandler +Reserved132_DriverIRQHandler +Reserved133_DriverIRQHandler +FLASH_DriverIRQHandler +RAM_PARITY_ECC_ERR_DriverIRQHandler +DefaultISR + B . + + END diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.c b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.c new file mode 100644 index 0000000000000000000000000000000000000000..ac2fee6e8934167b9ea570baa2c44066edf4f75c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210806 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-04-12) +** Initial version based on RM DraftF +** - rev. 1.1 (2021-08-04) +** Initial version based on RM DraftG +** +** ################################################################### +*/ + +/*! + * @file LPC55S36 + * @version 1.1 + * @date 2021-08-04 + * @brief Device specific configuration file for LPC55S36 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK + | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; +#endif +/* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.h b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.h new file mode 100644 index 0000000000000000000000000000000000000000..a00ade0b22ff4305aa7aeda5714fd494701b7880 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/LPC55S36/system_LPC55S36.h @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210806 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-04-12) +** Initial version based on RM DraftF +** - rev. 1.1 (2021-08-04) +** Initial version based on RM DraftG +** +** ################################################################### +*/ + +/*! + * @file LPC55S36 + * @version 1.1 + * @date 2021-08-04 + * @brief Device specific configuration file for LPC55S36 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S36_H_ +#define _SYSTEM_LPC55S36_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S36_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S36/SConscript b/bsp/lpc55sxx/Libraries/LPC55S36/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..edc35e422b755c57fef02eb093e1d63fe62d1a00 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S36/SConscript @@ -0,0 +1,51 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S36', cwd + '/LPC55S36/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] +src = Split(''' + LPC55S36/system_LPC55S36.c + ''') + +if rtconfig.PLATFORM in ['gcc']: + src += ['LPC55S36/gcc/startup_LPC55S36.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += ['LPC55S36/arm/startup_LPC55S36.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += ['LPC55S36/iar/startup_LPC55S36.s'] + +src += ['LPC55S36/drivers/fsl_anactrl.c'] +src += ['LPC55S36/drivers/fsl_clock.c'] +src += ['LPC55S36/drivers/fsl_cmp.c'] +src += ['LPC55S36/drivers/fsl_common.c'] +src += ['LPC55S36/drivers/fsl_common_arm.c'] +src += ['LPC55S36/drivers/fsl_crc.c'] +src += ['LPC55S36/drivers/fsl_ctimer.c'] +src += ['LPC55S36/drivers/fsl_flexcomm.c'] +src += ['LPC55S36/drivers/fsl_dma.c'] +src += ['LPC55S36/drivers/fsl_gint.c'] +src += ['LPC55S36/drivers/fsl_gpio.c'] +src += ['LPC55S36/drivers/fsl_i2c.c'] +src += ['LPC55S36/drivers/fsl_i2c_dma.c'] +src += ['LPC55S36/drivers/fsl_i2s.c'] +src += ['LPC55S36/drivers/fsl_i2s_dma.c'] +src += ['LPC55S36/drivers/fsl_inputmux.c'] +src += ['LPC55S36/drivers/fsl_lpadc.c'] +src += ['LPC55S36/drivers/fsl_mrt.c'] +src += ['LPC55S36/drivers/fsl_ostimer.c'] +src += ['LPC55S36/drivers/fsl_pint.c'] +src += ['LPC55S36/drivers/fsl_power.c'] +src += ['LPC55S36/drivers/fsl_reset.c'] +src += ['LPC55S36/drivers/fsl_sctimer.c'] +src += ['LPC55S36/drivers/fsl_spi.c'] +src += ['LPC55S36/drivers/fsl_spi_dma.c'] +src += ['LPC55S36/drivers/fsl_sysctl.c'] +src += ['LPC55S36/drivers/fsl_usart.c'] +src += ['LPC55S36/drivers/fsl_usart_dma.c'] +src += ['LPC55S36/drivers/fsl_utick.c'] +src += ['LPC55S36/drivers/fsl_wwdt.c'] + + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/.config b/bsp/lpc55sxx/lpc55s36_nxp_evk/.config new file mode 100644 index 0000000000000000000000000000000000000000..93b1478d24ebd51d9a0a15c29a808bc759bbe20c --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/.config @@ -0,0 +1,758 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_LPC55S6x=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40101 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set +# CONFIG_PKG_USING_BSDIFF_LIB is not set +# CONFIG_PKG_USING_PRC_DIFF is not set + +# +# RT-Thread Smart +# +# CONFIG_PKG_USING_UKERNEL is not set +# CONFIG_PKG_USING_TRACE_AGENT is not set +CONFIG_SOC_LPC55S6X_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_LPC55S6X=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_HW_UART0_BAUDRATE_9600 is not set +CONFIG_HW_UART0_BAUDRATE_115200=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_PWM is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_LED=y +CONFIG_BSP_USING_KEY=y +# CONFIG_BSP_USING_MMA8562 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/Kconfig b/bsp/lpc55sxx/lpc55s36_nxp_evk/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..91ec3bf89f46708d2ebb5d40426f613bfc2b203c --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_LPC55S36 + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../Libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/README.md b/bsp/lpc55sxx/lpc55s36_nxp_evk/README.md new file mode 100644 index 0000000000000000000000000000000000000000..ab4ecf051ebcffafec05278d36087ddf97e525cd --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/README.md @@ -0,0 +1,124 @@ +# LPC55S36-EVK 板级支持包 + +## 1. 简介(Introduction) + +LPC55S36 是由恩智浦NXP半导体推出的基于Cortex-M33内核的高性能单片机 +包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| LPC5536/LPC55S36 全系列 | +|CPU| Cortex-M33 , with FPU | +|主频| 150MHz | + +## 2. 硬件开发环境(Hardware development system) + +开发板（EVK） + +![开发板示意图](./figures/board.png) + + + +## 3. 编译说明 + +支持IDE: + +* MDK5: V5.36 +* IAR: 9.30.1 + +1) 下载源码 + +```bash + git clone https://github.com/RT-Thread/rt-thread.git +``` + +2) 配置工程并准备env + +（Linux/Mac） + +```bash + cd rt-thread/bsp/lpc55S36_evk + scons --menuconfig + source ~/.env/env.sh + pkgs --upgrade +``` + +（Windows） + +>在[RT-Thread官网][1]下载ENV工具包 + +3) 配置芯片型号 + +（Linux/Mac） + +```bash + scons --menuconfig +``` + +（Windows(ENV环境中)） + +```bash + menuconfig +``` + +在menuconfig页面配置并选择对应的芯片型号，若开发环境为MDK/IAR，则需要生成工程 + +4) 生成工程 + +IAR: + +```bash +scons --target=iar +``` + +MDK5: + +```bash +scons --target=mdk5 +``` + +## 3. 烧写及执行 + +烧写可以使用仿真器 ISP等多种方式 此处不再赘述 + +### 3.1 运行结果 + +如果编译 & 烧写无误，会在Flexcomm0串口*上看到RT-Thread的启动logo信息： + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.1 build Jul 30 2019 + 2006 - 2019 Copyright by rt-thread team +uising armclang, version: 6120001 +msh /> +``` + + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ---------- | :------: | :--------------------------: | +| UART | 支持 | UART0/2 | +| GPIO | 支持 | 自动根据芯片型号选择引脚布局 | +| SPI | 支持 | 支持High Speed SPI | +| USB Device | 不支持 | 暂不支持 | +| USB Host | 不支持 | 暂不支持 | +| Windowed WatchDog | 不支持 | 支持 | +| ADC | 不支持 | 暂不支持 | +| I2C | 支持 | 可配合MMA8562 | +| RTC | 支持 | RTC时钟自动配置 | + +## 5.进阶使用 + +此 BSP 默认只开启了串口 0 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置， 步骤如下： + +1. 在 bsp 下打开 env 工具。 +2. 输入 menuconfig 命令配置工程，配置好之后保存退出。 +3. 输入 pkgs --update 命令更新软件包。 +4. 输入 scons --target=mdk5/iar 命令重新生成工程。 + +## 6. 联系人信息 + +维护人: +alex.yang@nxp.com diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/SConscript b/bsp/lpc55sxx/lpc55s36_nxp_evk/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/SConstruct b/bsp/lpc55sxx/lpc55s36_nxp_evk/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..91e65db7a673c0d203fedc6be1e916767b8f5d7f --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/SConstruct @@ -0,0 +1,67 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# include cmsis +objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/SConscript b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..2588714bbe16b0e7790e5b867d7100c38ab7dde0 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/SConscript @@ -0,0 +1,19 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('main.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +if GetDepend('BSP_USING_SDIO'): + src += ['mnt.c'] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/main.c b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..50317bf7c9dcef4ed57da66a24886afed8eb1917 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/main.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-24 Magicoe first version + * 2020-01-10 Kevin/Karl Add PS demo + * 2020-09-21 supperthomas fix the main.c + * + */ + +#include +#include "drv_pin.h" + +/* defined the LED pin: GPIO1_IO4 */ +/* GPIO1_4 is Blue LED */ +#define LEDB_PIN GET_PINS(1, 4) + + +int main(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__clang__) + rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif + + rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT); /* Set GPIO as Output */ + while (1) + { + rt_pin_write(LEDB_PIN, PIN_HIGH); /* Set GPIO output 1 */ + rt_thread_mdelay(500); /* Delay 500mS */ + rt_pin_write(LEDB_PIN, PIN_LOW); /* Set GPIO output 0 */ + rt_thread_mdelay(500); /* Delay 500mS */ + } +} + +// end file diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/mnt.c b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..a849c04619e9923e83c20d0be72c637aa9abc9ce --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/mnt.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * sdio filesystem support + * Change Logs: + * Date Author Notes + * 2021-10-10 supperthomas first version + */ +#include "dfs_fs.h" +#include +#include + +#ifdef BSP_USING_SDIO + +/** + * @brief SDIO filesystem init + * @param void + * @retval 0: filesystem init success, -1: filesystem init failed + */ + +static int sdio_fs_init(void) +{ + int result = 0; + dfs_mount("sdcard0", "/", "elm", 0, 0); + return result; +} + +INIT_ENV_EXPORT(sdio_fs_init); + +#endif /* BSP_USING_SDIO */ diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/tfm_ps.c b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/tfm_ps.c new file mode 100644 index 0000000000000000000000000000000000000000..2c99e474026a72af6dde51a40744ac95b40b3f85 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/applications/tfm_ps.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-10 Kevin/Karl Add PS demo + * + */ + +#include +#include +#include "tfm_ns_lock.h" +#include "psa_protected_storage.h" + +#define TEST_UID_A 2U +#define ASSET_A "THEQUICKBROWNFOXJUMPSOVERALAZYDOG" +#define ASSET_A_SIZE (sizeof( ASSET_A ) - 1) +#define RESETDATA "THISIS" +#define RESETDATA_SIZE (sizeof( RESETDATA ) - 1) +#define READ_LENGTH (ASSET_A_SIZE > RESETDATA_SIZE ? \ + ASSET_A_SIZE : RESETDATA_SIZE) + +void protected_storage_demo_thread(void * parameters) +{ + psa_ps_status_t status; + const psa_ps_uid_t uid = TEST_UID_A; + const psa_ps_create_flags_t flags = PSA_PS_FLAG_NONE; + uint8_t write_data[] = ASSET_A; + const uint32_t data_length = ASSET_A_SIZE; + uint8_t rewrite_data[] = RESETDATA; + const uint32_t reset_data_length = RESETDATA_SIZE; + uint8_t get_data[READ_LENGTH]; + uint32_t counter = 0; + + tfm_ns_lock_init(); + + for ( ; ; ) + { + /* Call TF-M protected storage service and set the asset. */ + status = psa_ps_set(uid, data_length, write_data, flags); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Set Round %ld] Fail\r\n", counter); + for( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Set Round %ld] Success\r\n", counter); + + /* Read the asset. */ + status = psa_ps_get(uid, 0, data_length, get_data); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Get Round %ld] Success\r\n", counter); + + /* Check the read data. */ + if (memcmp(write_data, get_data, sizeof(write_data) - 1) != 0) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Get the wrong data\r\n", counter); + for ( ; ; ); + } + + /* Change the asset. */ + status = psa_ps_set(uid, reset_data_length, rewrite_data, flags); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Reset Round %ld] Fail\r\n", counter); + } + + rt_kprintf("[Protected Storage Asset A Reset Round %ld] Success\r\n", counter); + + /* Read the asset. */ + status = psa_ps_get(uid, 0, reset_data_length, get_data); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Get Round %ld] Success\r\n", counter); + + /* Check the read data. */ + if (memcmp(rewrite_data, get_data, sizeof(rewrite_data) - 1) != 0) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Get the wrong data\r\n", counter); + for ( ; ; ); + } + + /* Remove the asset. */ + status = psa_ps_remove(uid); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Remove Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Remove Round %ld] Success\r\n\n", counter); + + /* Wait for a second. */ + rt_thread_mdelay(1000); + counter++; + } +} + +// end file diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..c59e271e6a8e167fc1999397d4628ee324de1b8d --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig @@ -0,0 +1,224 @@ +menu "Hardware Drivers Config" + +config SOC_LPC55S36 + bool + select SOC_LPC55S36_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + select RT_USING_DMA + default n + + config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + config BSP_USING_UART + bool "Enable UART" + select RT_USING_UART + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable Flexcomm0 as UART" + default y + if BSP_USING_UART0 + choice + prompt "Select UART0 badurate" + default HW_UART0_BAUDRATE_115200 + + config HW_UART0_BAUDRATE_9600 + bool "Badurate 9600" + + config HW_UART0_BAUDRATE_115200 + bool "Badurate 115200" + endchoice + endif + + config BSP_USING_UART2 + bool "Enable Flexcomm2 as UART" + default n + if BSP_USING_UART2 + choice + prompt "Select UART2 badurate" + default HW_UART2_BAUDRATE_115200 + + config HW_UART2_BAUDRATE_9600 + bool "Badurate 9600" + + config HW_UART2_BAUDRATE_115200 + bool "Badurate 115200" + endchoice + endif + endif + + + menuconfig BSP_USING_I2C + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default y + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable Flexcomm1 I2C" + default y + if BSP_USING_I2C1 + choice + prompt "Select I2C1 badurate" + default HW_I2C1_BAUDRATE_100kHZ + + config HW_I2C1_BAUDRATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C1_BAUDRATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + + config BSP_USING_I2C4 + bool "Enable Flexcomm4 I2C" + default y + if BSP_USING_I2C4 + choice + prompt "Select I2C4 badurate" + default HW_I2C4_BAUDRATE_100kHZ + + config HW_I2C4_BAUDRATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C4_BAUDRATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + endif + + menuconfig BSP_USING_SPI + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default y + + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable Flexcomm3 as SPI" + default n + + config BSP_USING_SPI8 + bool "Enable Flexcomm8 as High Speed SPI" + default y + endif + + menuconfig BSP_USING_ADC + config BSP_USING_ADC + bool "Enable ADC Channel" + select RT_USING_ADC + default y + + if BSP_USING_ADC + config BSP_USING_ADC0_CH0 + bool "Enable ADC0 Channel0" + default y + + config BSP_USING_ADC0_CH1 + bool "Enable ADC0 Channel1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO SD Card Interface" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default y + + config BSP_USING_WDT + bool "Enable WatchDog" + select RT_USING_WDT + default n + + menuconfig BSP_USING_HWTIMER + config BSP_USING_HWTIMER + bool "Enable Timer" + select RT_USING_HWTIMER + default y + + if BSP_USING_HWTIMER + config BSP_USING_CTIMER0 + bool "Enable CIMER0" + default y + + config BSP_USING_CTIMER1 + bool "Enable CIMER1" + default n + + config BSP_USING_CTIMER3 + bool "Enable CIMER3" + default n + + config BSP_USING_CTIMER4 + bool "Enable CIMER4" + default n + endif + + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default y + + if BSP_USING_PWM + config BSP_USING_CTIMER2_MAT0 + bool "Enable CIMER2 Match0 as PWM output" + default y + + config BSP_USING_CTIMER2_MAT1 + bool "Enable CIMER2 Match1 as PWM output" + default n + + config BSP_USING_CTIMER2_MAT2 + bool "Enable CIMER2 Match2 as PWM output" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_LED + bool "Enable RGB LED" + select RT_USING_LED + default y + + config BSP_USING_KEY + bool "Enable Button " + select RT_USING_KEY + default y + + config BSP_USING_MMA8562 + bool "Enable MMA8562" + select BSP_USING_I2C4 + default y + if BSP_USING_MMA8562 + config BSP_USING_MMA8562I2C + string "the device name for 3-Axis Sensor" + default "i2c4" + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/clock_config.c b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/clock_config.c new file mode 100644 index 0000000000000000000000000000000000000000..ee61f59d2c3069fda7228ab42c02315a6fae4326 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,367 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v8.0 +processor: LPC55S36 +package_id: LPC55S36JBD100 +mcu_data: ksdk2_0 +processor_version: 0.10.0 +board: LPCXpresso55S36 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_PowerInit(); /*!< Power Management Controller initialization */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_PowerInit(); /*!< Power Management Controller initialization */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} +- {id: SYSCON.XTAL.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_PowerInit(); /*!< Power Management Controller initialization */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + CLOCK_SetupExtClocking(16000000U); /* Enable XTALHF clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_PowerInit(); /*!< Power Management Controller initialization */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupExtClocking(16000000U); /* Enable XTALHF clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockPLL1_150M ******************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL1_150M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL1_150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_PowerInit(); /*!< Power Management Controller initialization */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupExtClocking(16000000U); /* Enable XTALHF clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U), + .pllndec = SYSCON_PLL1NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(150U), + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK; +#endif +} + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/clock_config.h b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/clock_config.h new file mode 100644 index 0000000000000000000000000000000000000000..0b7e428038a1a6787e51231aaf34ba260532f459 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,172 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockPLL1_150M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL1_150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/pin_mux.c b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 0000000000000000000000000000000000000000..d76cb25c219fdd739f5e7691dd788404534994aa --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,118 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: LPC55S36 +package_id: LPC55S36JBD100 +mcu_data: ksdk2_0 +processor_version: 0.10.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '93', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/TRACEDATA2/FC6_RXD_SDA_MOSI_DATA/CMP0_OUT/SECURE_GPIO0_29/PWM0_A1/SPI_DIN/EXTTRIG_IN3, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '95', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/TRACEDATA1/CAN0_TD/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_30/PWM1_A1/AOI1_OUT0, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '56', peripheral: SWD, signal: SWO, pin_signal: PIO0_18/FC4_CTS_SDA_SSEL0/CTIMER1_MAT0/SCT0_OUT1/FC5_RXD_SDA_MOSI_DATA/SWO/SECURE_GPIO0_18/PWM1_A0/QSPI_DIN1/TRIGOUT_7/ACMP0_C, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw0: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 */ +void BOARD_InitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin18_config = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC8 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch 0 is open (disabled) */ + IOCON_PIO_ASW0_DI); + /* PORT0 PIN18 (coords: 56) is configured as SWO */ + IOCON_PinMuxSet(IOCON, 0U, 18U, port0_pin18_config); + + const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 93) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config); + + const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 95) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/pin_mux.h b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 0000000000000000000000000000000000000000..b34942bbcf54b3007d8c459bc1c0a958d1e669de --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,61 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_ASW0_DI 0x00u /*!<@brief Analog switch 0 is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC8 0x08u /*!<@brief Selects pin function 8 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/SConscript b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..5c740fb347e6139b853218259a39c51ff516f826 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/SConscript @@ -0,0 +1,16 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config/board'] +CPPDEFINES = ['DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..612dd1f159f16bae37fd586fadbceef81ccdc2f2 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/board.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2010-02-04 Magicoe ported to LPC17xx + * 2010-05-02 Aozima update CMSIS to 130 + * 2017-08-02 XiaoYang porting to LPC54608 bsp + * 2019-08-05 Magicoe porting to LPC55S69-EVK bsp + * 2020-01-01 Karl Add PKG_USING_TFM support + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "drv_uart.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial LPC55Sxx board. + */ +void rt_hw_board_init() +{ + /* Hardware Initialization */ + BOARD_InitPins(); + + CLOCK_EnableClock(kCLOCK_InputMux); + + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + + GPIO_PortInit(GPIO, 0); + GPIO_PortInit(GPIO, 1); + + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + +#ifdef PKG_USING_TFM + /* Set the Vector Table base location at 0x00020000 when RTT with TF-M*/ + SCB->VTOR = (0x00020000 & NVIC_VTOR_MASK); +#else + /* Set the Vector Table base location at 0x00000000 */ + SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); +#endif +#endif + +#ifndef PKG_USING_TFM + /* This init has finished in secure side of TF-M */ + BOARD_BootClockPLL150M(); +#endif + //BOARD_BootClockFROHF96M(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + + /*init uart device*/ + rt_hw_uart_init(); + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +/** + * This function will called when memory fault. + */ +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/board.h b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..208d73c8f3ec9be2643db73401d5ca8ab599a322 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/board.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include + +#include + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +// + +// +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_STACK$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_STACK$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +void rt_hw_board_init(void); + +#define BOARD_SDIF_BASEADDR SDIF +#define BOARD_SDIF_CLKSRC kCLOCK_SDio +#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio) +#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK +#define BOARD_SDIF_IRQ SDIO_IRQn +#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SD_CARD_DETECT_PIN 17 +#define BOARD_SD_CARD_DETECT_PORT 0 +#define BOARD_SD_CARD_DETECT_GPIO GPIO +#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD + +#define BOARD_SDIF_CD_GPIO_INIT() \ + { \ + CLOCK_EnableClock(kCLOCK_Gpio2); \ + GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \ + } +#define BOARD_SDIF_CD_STATUS() \ + GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN) + +#endif + + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.icf b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.icf new file mode 100644 index 0000000000000000000000000000000000000000..26a5faafe5973fcce143df196ccbf413e37c1e3e --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.icf @@ -0,0 +1,103 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +if (isdefinedsymbol(__pkc__)) { + define symbol retention_RAMsize = 0x00004000; /* SRAM A(16K) reserved for pkc */ +} else if (isdefinedsymbol(__power_down__)) { + define symbol retention_RAMsize = 0x00000604; /* The first 0x604 bytes reserved to CPU retention for power down mode */ +} else { + define symbol retention_RAMsize = 0x00000000; +} + +if (isdefinedsymbol(__powerquad__)) { + define symbol powerquad_RAMsize = 0x00004000; /* SRAM E(16K) reserved for powerquad */ +} else { + define symbol powerquad_RAMsize = 0x00000000; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0003D7FF; + +define symbol m_data_start = 0x20000000 + retention_RAMsize; +define symbol m_data_end = 0x2001BFFF - powerquad_RAMsize; + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04003FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.ld b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..bc23d2616f86c589947e1569ea02a28a61ea96ec --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* __pkc__ : SRAM A(16K) reserved for; pkc __power_down__ : The first 0x604 bytes reserved to CPU retention for power down mode */ +RETENTION_RAMSIZE = DEFINED(__pkc__) ? 0x00004000 : (DEFINED(__power_down__) ? 0x00000604 : 0x00000000); +POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for powerquad */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0003D400 + m_data (RW) : ORIGIN = 0x20000000 + RETENTION_RAMSIZE, LENGTH = 0x0001C000 - RETENTION_RAMSIZE - POWERQUAD_RAMSIZE + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.scf b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.scf new file mode 100644 index 0000000000000000000000000000000000000000..7e54ddd6c459431516f0e3fe726f1cee97a785fb --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/board/linker_scripts/LPC55S36_flash.scf @@ -0,0 +1,88 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S36JBD100 +** LPC55S36JHI48 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 +** Version: rev. 1.1, 2021-08-04 +** Build: b210913 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2021 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#if (defined(__pkc__)) + #define retention_RAMsize 0x00004000 /* SRAM A(16K) reserved for pkc */ +#elif (defined(__power_down__)) + #define retention_RAMsize 0x00000604 /* The first 0x604 bytes reserved to CPU retention for power down mode */ +#else + #define retention_RAMsize 0x00000000 +#endif + +#if (defined(__powerquad__)) + #define powerquad_RAMsize 0x00004000 /* SRAM E(16K) reserved for powerquad */ +#else + #define powerquad_RAMsize 0x00000000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0003D400 + +#define m_data_start 0x20000000 + retention_RAMsize +#define m_data_size 0x0001C000 - retention_RAMsize - powerquad_RAMsize + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00004000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/figures/board.png b/bsp/lpc55sxx/lpc55s36_nxp_evk/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..07b57b0e87f13d9a7167962b6ecccdd965a25afc Binary files /dev/null and b/bsp/lpc55sxx/lpc55s36_nxp_evk/figures/board.png differ diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/figures/flash.png b/bsp/lpc55sxx/lpc55s36_nxp_evk/figures/flash.png new file mode 100644 index 0000000000000000000000000000000000000000..b7dfb3b56896be1a3b255b0166ef89e3afa8bc93 Binary files /dev/null and b/bsp/lpc55sxx/lpc55s36_nxp_evk/figures/flash.png differ diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/flashdebug.ini b/bsp/lpc55sxx/lpc55s36_nxp_evk/flashdebug.ini new file mode 100644 index 0000000000000000000000000000000000000000..d328fc5a4d880362d7fd78400259cfedf1ee05f3 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/flashdebug.ini @@ -0,0 +1,11 @@ +FUNC void Setup (void) { + SP = _RDWORD(0x0); // Setup Stack Pointer + PC = _RDWORD(0x4); // Setup Program Counter + _WDWORD(0xE000ED08, 0); // Setup Vector Table Offset Register +} + +//LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +g, main \ No newline at end of file diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/project.uvoptx b/bsp/lpc55sxx/lpc55s36_nxp_evk/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..7fcae62d3c623026b7c071cc4b9f2f0e34ccfe38 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/project.uvoptx @@ -0,0 +1,1215 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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fsl_ctimer.c + 0 + 0 + + + + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx b/bsp/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..6cb573e4c6d45889bc61c09d594e23f62918bb29 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx @@ -0,0 +1,847 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc55s36 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + LPC55S36JBD100 + NXP + NXP.LPC55S36_DFP.13.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x10000000,0x03d800) IRAM2(0x20000000,0x01c000) IROM(0x03000000,0x020000) IROM2(0x13000000,0x020000) XRAM(0x04000000,0x4000) XRAM2(0x14000000,0x4000) XRAM3(0x30000000,0x01c000) XROM(0x00000000,0x03d800) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN4 -FF0LPC553XX_256 -FS00 -FL040000 -FF1LPC553XX_S_256 -FS110000000 -FL140000 -FF2LPC553XX_FLEXSPI -Fs36000000 -FL24000000 -FF3LPC553XX_FLEXSPI_S -FS318000000 -FL34000000 -FP0($$Device:LPC55S36JBD100$arm\LPC553XX_256.FLM) -FP1($$Device:LPC55S36JBD100$arm\LPC553XX_S_256.FLM) -FP2($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI.FLM) -FP3($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI_S.FLM)) + 0 + $$Device:LPC55S36JBD100$fsl_device_registers.h + + + + + + + + + + $$Device:LPC55S36JBD100$LPC55S36.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x3d800 + + + 1 + 0x3000000 + 0x20000 + + + 1 + 0x4000000 + 0x4000 + + + 1 + 0x0 + 0x3d800 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x3000000 + 0x20000 + + + 1 + 0x13000000 + 0x20000 + + + 0 + 0x4000000 + 0x4000 + + + 0 + 0x14000000 + 0x4000 + + + 0 + 0x30000000 + 0x1c000 + + + 0 + 0x10000000 + 0x3d800 + + + 0 + 0x20000000 + 0x1c000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, DEBUG + + ..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\Libraries\LPC55S36\components\codec;..\Libraries\drivers;board\MCUX_Config\board;..\Libraries\LPC55S36\LPC55S36;..\Libraries\LPC55S36\middleware\sdmmc\inc;.;..\Libraries\CMSIS\Core\Include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;board;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\poll;..\Libraries\LPC55S36\middleware\sdmmc\port;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\drivers\include;..\Libraries\LPC55S36\LPC55S36\drivers;..\..\..\components\libc\posix\io\stdio;applications;..\Libraries\drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\LPC55S36_flash.scf + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdio.c + 1 + ..\..\..\components\libc\compilers\common\cstdio.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m33\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m33\cpuport.c + + + syscall_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + + + trustzone.c + 1 + ..\..\..\libcpu\arm\cortex-m33\trustzone.c + + + + + DeviceDrivers + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + clock_config.c + 1 + board\MCUX_Config\board\clock_config.c + + + pin_mux.c + 1 + board\MCUX_Config\board\pin_mux.c + + + board.c + 1 + board\board.c + + + drv_key.c + 1 + ..\Libraries\drivers\drv_key.c + + + drv_led.c + 1 + ..\Libraries\drivers\drv_led.c + + + drv_pin.c + 1 + ..\Libraries\drivers\drv_pin.c + + + drv_uart.c + 1 + ..\Libraries\drivers\drv_uart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + fsl_usart.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_usart.c + + + fsl_i2s_dma.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_i2s_dma.c + + + fsl_pint.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_pint.c + + + fsl_clock.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_clock.c + + + fsl_power.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_power.c + + + fsl_i2c.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_i2c.c + + + fsl_reset.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_reset.c + + + fsl_usart_dma.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_usart_dma.c + + + fsl_spi.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_spi.c + + + fsl_gint.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_gint.c + + + fsl_wwdt.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_wwdt.c + + + fsl_crc.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_crc.c + + + fsl_anactrl.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_anactrl.c + + + fsl_inputmux.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_inputmux.c + + + fsl_common.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_common.c + + + fsl_utick.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_utick.c + + + startup_LPC55S36.s + 2 + ..\Libraries\LPC55S36\LPC55S36\arm\startup_LPC55S36.s + + + fsl_i2s.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_i2s.c + + + fsl_common_arm.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_common_arm.c + + + fsl_sysctl.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_sysctl.c + + + fsl_spi_dma.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_spi_dma.c + + + system_LPC55S36.c + 1 + ..\Libraries\LPC55S36\LPC55S36\system_LPC55S36.c + + + fsl_cmp.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_cmp.c + + + fsl_flexcomm.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_flexcomm.c + + + fsl_sctimer.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_sctimer.c + + + fsl_lpadc.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_lpadc.c + + + fsl_ostimer.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_ostimer.c + + + fsl_dma.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_dma.c + + + fsl_i2c_dma.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_i2c_dma.c + + + fsl_gpio.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_gpio.c + + + fsl_mrt.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_mrt.c + + + fsl_ctimer.c + 1 + ..\Libraries\LPC55S36\LPC55S36\drivers\fsl_ctimer.c + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/rtconfig.h b/bsp/lpc55sxx/lpc55s36_nxp_evk/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..ee346cfc428d4fdb90e546a10fce68a8cdb3df45 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/rtconfig.h @@ -0,0 +1,216 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_LPC55S6x + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40101 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + +/* RT-Thread Smart */ + +#define SOC_LPC55S6X_SERIES + +/* Hardware Drivers Config */ + +#define SOC_LPC55S6X + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART0 +#define HW_UART0_BAUDRATE_115200 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_LED +#define BSP_USING_KEY + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/rtconfig.py b/bsp/lpc55sxx/lpc55s36_nxp_evk/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..08e6c11d0e5fc0fc6675584ff07a4c4c26f6ef8f --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/rtconfig.py @@ -0,0 +1,162 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' +BOARD_NAME = 'lpcxpresso' +BSP_LIBRARY_TYPE = 'LPC55S36' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/LPC55S36_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./LPC55S36_flash.scf" ' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/LPC55S36_flash.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/template.uvoptx b/bsp/lpc55sxx/lpc55s36_nxp_evk/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..1e6b6338ed907a6acbaa721dbc397dda3742840f --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-lpc55s28 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN4 -FC1000 -FD20000000 -FF0LPC553XX_256 -FF1LPC553XX_S_256 -FF2LPC553XX_FLEXSPI -FF3LPC553XX_FLEXSPI_S -FL040000 -FL140000 -FL24000000 -FL34000000 -FS00 -FS110000000 -FS28000000 -FS318000000 -FP0($$Device:LPC55S36JBD100$arm\LPC553XX_256.FLM) -FP1($$Device:LPC55S36JBD100$arm\LPC553XX_S_256.FLM) -FP2($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI.FLM) -FP3($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI_S.FLM) + + + 0 + CMSIS_AGDI_V8M + UL2V8M(-S0 -C0 -P0 ) -FN4 -FC1000 -FD20000000 -FF0LPC553XX_256 -FF1LPC553XX_S_256 -FF2LPC553XX_FLEXSPI -FF3LPC553XX_FLEXSPI_S -FL040000 -FL140000 -FL24000000 -FL34000000 -FS00 -FS110000000 -FS28000000 -FS318000000 -FP0($$Device:LPC55S36JBD100$arm\LPC553XX_256.FLM) -FP1($$Device:LPC55S36JBD100$arm\LPC553XX_S_256.FLM) -FP2($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI.FLM) -FP3($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI_S.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/lpc55sxx/lpc55s36_nxp_evk/template.uvprojx b/bsp/lpc55sxx/lpc55s36_nxp_evk/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..a1e0d8442a9946152aae0291741971b37aacd5a4 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s36_nxp_evk/template.uvprojx @@ -0,0 +1,400 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc55s36 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + LPC55S36JBD100 + NXP + NXP.LPC55S36_DFP.13.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x10000000,0x03d800) IRAM2(0x20000000,0x01c000) IROM(0x03000000,0x020000) IROM2(0x13000000,0x020000) XRAM(0x04000000,0x4000) XRAM2(0x14000000,0x4000) XRAM3(0x30000000,0x01c000) XROM(0x00000000,0x03d800) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN4 -FF0LPC553XX_256 -FS00 -FL040000 -FF1LPC553XX_S_256 -FS110000000 -FL140000 -FF2LPC553XX_FLEXSPI -Fs36000000 -FL24000000 -FF3LPC553XX_FLEXSPI_S -FS318000000 -FL34000000 -FP0($$Device:LPC55S36JBD100$arm\LPC553XX_256.FLM) -FP1($$Device:LPC55S36JBD100$arm\LPC553XX_S_256.FLM) -FP2($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI.FLM) -FP3($$Device:LPC55S36JBD100$arm\LPC553XX_FLEXSPI_S.FLM)) + 0 + $$Device:LPC55S36JBD100$fsl_device_registers.h + + + + + + + + + + $$Device:LPC55S36JBD100$LPC55S36.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x3d800 + + + 1 + 0x3000000 + 0x20000 + + + 1 + 0x4000000 + 0x4000 + + + 1 + 0x0 + 0x3d800 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x3000000 + 0x20000 + + + 1 + 0x13000000 + 0x20000 + + + 0 + 0x4000000 + 0x4000 + + + 0 + 0x14000000 + 0x4000 + + + 0 + 0x30000000 + 0x1c000 + + + 0 + 0x10000000 + 0x3d800 + + + 0 + 0x20000000 + 0x1c000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_LPC55s36JBD100=1, ARM_MATH_CM33, RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\LPC55S36_flash.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/README.md b/bsp/lpc55sxx/lpc55s69_nxp_evk/README.md index a3151f0e8d4e4a0b0311e2ad854d5cf22cb4332d..2305a354053548c570311cc0e1d0594c5071397f 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/README.md +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/README.md @@ -166,51 +166,9 @@ msh /> | SDIO | 支持 | 操作SD卡 | | I2S | 不支持 | 暂不支持 | - -### 4.1 IO在板级支持包中的映射情况 - -| PIO号 | 板级包中的定义 | -| -- | -- | -| PIO0_29 | Flexcomm0 USART RXD | -| PIO0_30 | Flexcomm0 USART TXD | -| | | -| PIO0_7 | SDIO SD0_CLK | -| PIO0_8 | SDIO SD0_CMD | -| PIO0_9 | SDIO SD0_POW_EN | -| PIO0_15 | SDIO SD0_WR_PRT | -| PIO0_17 | SDIO SD0_CARD_INT | -| PIO0_24 | SDIO SD0_D(0) | -| PIO0_25 | SDIO SD0_D(1) | -| PIO0_31 | SDIO SD0_D(2) | -| PIO1_0 | SDIO SD0_D(3) | -| | | -| PIO0_26 | High Speed SPI MOSI | -| PIO1_2 | High Speed SPI SCK | -| PIO1_3 | High Speed SPI MISO | -| | | -| PIO1_4 | GPIO1_4 output LED BLUE | -| PIO1_6 | GPIO1_6 output LED RED | -| PIO1_7 | GPIO1_7 output LED GREEN | -| | | -| PIO0_27 | Flexcomm2 USART TXD mikro BUS | -| PIO1_24 | Flexcomm2 USART RXD mikro BUS | -| | | -| PIO1_20 | Flexcomm4 I2C SCL | -| PIO1_21 | Flexcomm4 I2C SDA | - -## 5. menuconfig Bsp菜单详解 - -| 选项 | 解释 | -| -- | -- | -| Device type | 选择芯片型号，修改此处需修改MDK/IAR工程为相同芯片型号 | - -*部分选项需要在RT-Thread组件菜单中开启对应的设备框架才能显示。 - ## 6. 联系人信息 维护人: -[Magicoe][2] < [magicoe@163.com][3] > -[1]: https://www.rt-thread.org/page/download.html -[2]: https://github.com/Magicoe -[3]: mailto:magicoe@163.com +* magicoe@163.com +* alex.yang@nxp.com diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project.ewd b/bsp/lpc55sxx/lpc55s69_nxp_evk/project.ewd index cdaa7944121d12c8fe65dfc92c61241e2c034838..843c1c1018dcc33b97c8f4e8b86df5d086234ae9 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/project.ewd +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project.ewd @@ -2,7 +2,7 @@ 3 - rtthread-lpc55s6x + rtthread ARM @@ -44,7 +44,7 @@