diff --git a/bsp/stm32f7-disco/SConstruct b/bsp/stm32f7-disco/SConstruct index 6ea007ee941924b77417a5df3529aa507be59645..af8f4a90b23465f6fb4cd2cce6f0fc286cca8a30 100644 --- a/bsp/stm32f7-disco/SConstruct +++ b/bsp/stm32f7-disco/SConstruct @@ -20,6 +20,7 @@ TARGET = 'rtthread-stm32f7xx.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/stm32f7-disco/applications/SConscript b/bsp/stm32f7-disco/applications/SConscript index 7e46cf27f92b72e8e31be3dfca6e26bb578711bb..7a6bbecebe740dda0fdce682b51737a0a642bdb4 100644 --- a/bsp/stm32f7-disco/applications/SConscript +++ b/bsp/stm32f7-disco/applications/SConscript @@ -3,7 +3,7 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') -CPPPATH = [cwd] +CPPPATH = [cwd, str(Dir('#'))] group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/stm32f7-disco/applications/startup.c b/bsp/stm32f7-disco/applications/startup.c index 1ac91767786295493efc6ea318a6e4580e79bf8c..628a805042092a63b532f4b7a2bd270a84ffee5d 100644 --- a/bsp/stm32f7-disco/applications/startup.c +++ b/bsp/stm32f7-disco/applications/startup.c @@ -26,6 +26,7 @@ #include #include #include "board.h" + #ifdef RT_USING_EXT_SDRAM #include "drv_sdram.h" #include "sram.h" @@ -61,8 +62,8 @@ void assert_failed(uint8_t* file, uint32_t line) while (1) {} } - #endif + /** * This function will startup RT-Thread RTOS. */ @@ -113,7 +114,7 @@ void rtthread_startup(void) int main(void) { /* disable interrupt first */ - //rt_hw_interrupt_disable(); + rt_hw_interrupt_disable(); /* startup RT-Thread RTOS */ rtthread_startup(); diff --git a/bsp/stm32f7-disco/drivers/board.c b/bsp/stm32f7-disco/drivers/board.c index 4d5c0d6164d2a7d4029f33deed76f69a020c4010..734ecf2094d5783e93d36973957e6198072a202c 100644 --- a/bsp/stm32f7-disco/drivers/board.c +++ b/bsp/stm32f7-disco/drivers/board.c @@ -69,16 +69,18 @@ static void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 25; RCC_OscInitStruct.PLL.PLLN = 400; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); + RCC_OscInitStruct.PLL.PLLQ = 8; + + ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); + if(ret != HAL_OK) + { + while(1) { ; } + } ret = HAL_PWREx_EnableOverDrive(); - if (ret != HAL_OK) { - while (1) - { - ; - } + while (1) { ; } } /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 @@ -88,7 +90,11 @@ static void SystemClock_Config(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6); + ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6); + if (ret != HAL_OK) + { + while (1) { ; } + } } /** @@ -115,18 +121,46 @@ static void CPU_CACHE_Enable(void) */ void SysTick_Handler(void) { - /* tick for HAL Library */ - HAL_IncTick(); - /* enter interrupt */ rt_interrupt_enter(); + /* tick for HAL Library */ + HAL_IncTick(); + rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); } +/* re-implementat tick interface for STM32 HAL */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RT_TICK_PER_SECOND); + + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + + /* Return function status */ + return HAL_OK; +} + +void HAL_Delay(__IO uint32_t Delay) +{ + rt_thread_delay(Delay); +} + +void HAL_SuspendTick(void) +{ + /* we should not suspend tick */ +} + +void HAL_ResumeTick(void) +{ + /* we should not resume tick */ +} + /** * This function will initial STM32 board. */ diff --git a/bsp/stm32f7-disco/drivers/drv_mpu.c b/bsp/stm32f7-disco/drivers/drv_mpu.c index 284887846e70a8573c49efd499c86230dcfe6be8..4cab4d22818388cf4953920426dace65f6831ea9 100644 --- a/bsp/stm32f7-disco/drivers/drv_mpu.c +++ b/bsp/stm32f7-disco/drivers/drv_mpu.c @@ -47,6 +47,36 @@ void mpu_init(void) HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Configure the MPU attributes as WB for SDRAM */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.BaseAddress = 0xC0000000; + MPU_InitStruct.Size = MPU_REGION_SIZE_8MB; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER1; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.SubRegionDisable = 0x00; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /* Configure the MPU attributes as none-cache for 1MB SDRAM */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.BaseAddress = 0xC0100000; + MPU_InitStruct.Size = MPU_REGION_SIZE_1MB; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER2; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.SubRegionDisable = 0x00; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Enable the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); } diff --git a/bsp/stm32f7-disco/drivers/drv_sdram.c b/bsp/stm32f7-disco/drivers/drv_sdram.c index fd61b83ae74e975e177f325b302275b2f55c7c83..4b58e21d01673880cefe09979c74d930bd8072b7 100644 --- a/bsp/stm32f7-disco/drivers/drv_sdram.c +++ b/bsp/stm32f7-disco/drivers/drv_sdram.c @@ -24,12 +24,10 @@ #include "drv_sdram.h" - static SDRAM_HandleTypeDef sdramHandle; static FMC_SDRAM_TimingTypeDef Timing; static FMC_SDRAM_CommandTypeDef Command; - /** * @brief Initializes SDRAM MSP. * @param hsdram: SDRAM handle @@ -162,8 +160,11 @@ static void SDRAM_InitializationSequence(uint32_t RefreshCount) /* Step 2: Insert 100 us minimum delay */ /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ - HAL_Delay(1); - + // HAL_Delay(1); + /* interrupt is not enable, just to delay some time. */ + for (tmpmrd = 0; tmpmrd < 0xfffff; tmpmrd ++) + ; + /* Step 3: Configure a PALL (precharge all) command */ Command.CommandMode = FMC_SDRAM_CMD_PALL; Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; @@ -361,94 +362,3 @@ void SDRAM_DMA_IRQHandler(void) { HAL_DMA_IRQHandler(sdramHandle.hdma); } - - - -#ifdef RT_USING_FINSH -#include -int sdram_test(void) -{ - uint32_t i; - volatile uint32_t *wr_ptr; - volatile uint8_t *char_wr_ptr; - volatile uint16_t *short_wr_ptr; - - /* initialize memory */ - rt_kprintf("SDRAM初始化...\r\n"); - - wr_ptr = (uint32_t *)SDRAM_DEVICE_ADDR; - char_wr_ptr = (uint8_t *)wr_ptr; - /* 进行8位数据写测试前先清除数据*/ - rt_kprintf("清除SDRAM数据...\r\n"); - for (i = 0; i < SDRAM_DEVICE_SIZE / 4; i++) - { - *wr_ptr++ = 0x00; //写入0x00 - } - - /* 8 bit write */ - rt_kprintf("写入8位数据...\r\n"); - for (i = 0; i < SDRAM_DEVICE_SIZE / 4; i++) - { - *char_wr_ptr++ = 0x11; - *char_wr_ptr++ = 0x22; - *char_wr_ptr++ = 0x33; - *char_wr_ptr++ = 0x44; - } - - /* 校验写入的数据*/ - rt_kprintf("校验数据...\r\n"); - wr_ptr = (uint32_t *)SDRAM_DEVICE_ADDR; - for (i = 0; i < SDRAM_DEVICE_SIZE / 8; i++) - { - if (*wr_ptr != 0x44332211) /* be aware of endianess */ - { - /* byte comparison failure */ - rt_kprintf("校验失败，测试完毕!\r\n"); - return 1; /* fatal error */ - } - wr_ptr++; - } - - /* byte comparison succeed. */ - rt_kprintf("继续测试16位数据写入...\r\n"); - wr_ptr = (uint32_t *)SDRAM_DEVICE_ADDR; - short_wr_ptr = (uint16_t *)wr_ptr; - - /* Clear content before 16 bit access test */ - rt_kprintf("清除SDRAM中的数据...\r\n"); - for (i = 0; i < SDRAM_DEVICE_SIZE / 4; i++) - { - *wr_ptr++ = 0; - } - - /* 16 bit write */ - rt_kprintf("写入16位数据...\r\n"); - for (i = 0; i < (SDRAM_DEVICE_SIZE / 4); i++) - { - *short_wr_ptr++ = 0x5AA5; - *short_wr_ptr++ = 0xAA55; - } - - /* Verifying */ - wr_ptr = (uint32_t *)SDRAM_DEVICE_ADDR; - - //wr_ptr -= SDRAM_BASE_ADDR/4; - for (i = 0; i < SDRAM_DEVICE_SIZE / 4; i++) - { - if (*wr_ptr != 0xAA555AA5) /* be aware of endianess */ - { - /* 16-bit half word failure */ - rt_kprintf("校验失败，测试完毕!\r\n"); - return 1; /* fatal error */ - } - wr_ptr++; - } - - /* 16-bit half word comparison succeed. */ - - rt_kprintf("校验成功，测试完毕！\r\n"); - return 0; -} - -FINSH_FUNCTION_EXPORT(sdram_test, SDRAM read write test) -#endif diff --git a/bsp/stm32f7-disco/drivers/drv_usart.c b/bsp/stm32f7-disco/drivers/drv_usart.c index 58e25ba3959a58a7cd877116730ba3adeb058a17..907849c517528eb8176f09af2442f831f75842d5 100644 --- a/bsp/stm32f7-disco/drivers/drv_usart.c +++ b/bsp/stm32f7-disco/drivers/drv_usart.c @@ -44,8 +44,6 @@ #define USART1_RX_GPIO_PORT GPIOB #define USART1_RX_AF GPIO_AF7_USART1 - - /* STM32 uart driver */ struct stm32_uart { @@ -291,13 +289,11 @@ int stm32_hw_usart_init(void) serial1.config = config; /* register UART1 device */ - rt_hw_serial_register(&serial1, - "uart1", + rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART1 */ - return 0; } INIT_BOARD_EXPORT(stm32_hw_usart_init); diff --git a/bsp/stm32f7-disco/rtconfig.py b/bsp/stm32f7-disco/rtconfig.py index 083099998b15372ff974472a2f333ca2b76896ed..18cb7b6b267157beb698f0ed4699c43de968e14b 100644 --- a/bsp/stm32f7-disco/rtconfig.py +++ b/bsp/stm32f7-disco/rtconfig.py @@ -3,10 +3,12 @@ import os # toolchains options ARCH='arm' CPU='cortex-m7' -CROSS_TOOL='keil' +CROSS_TOOL='gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') # cross_tool provides the cross compiler # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR @@ -23,7 +25,7 @@ elif CROSS_TOOL == 'iar': exit(0) if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') + EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' STM32_TYPE = 'STM32F756xx' @@ -32,6 +34,7 @@ if PLATFORM == 'gcc': # toolchains PREFIX = 'arm-none-eabi-' CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' LINK = PREFIX + 'gcc' @@ -39,6 +42,7 @@ if PLATFORM == 'gcc': SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -g -Wall -DSTM32F756xx -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_USED' @@ -52,13 +56,22 @@ if PLATFORM == 'gcc': CFLAGS += ' -O0 -gdwarf-2' AFLAGS += ' -gdwarf-2' else: - CFLAGS += ' -O2' + CFLAGS += ' -O2 -Os' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + elif PLATFORM == 'armcc': # toolchains CC = 'armcc' + CXX = 'armcc' AS = 'armasm' AR = 'armar' LINK = 'armlink' @@ -78,8 +91,9 @@ elif PLATFORM == 'armcc': CFLAGS += ' -g -O0' AFLAGS += ' -g' else: - CFLAGS += ' -O2' + CFLAGS += ' -O2 -Otime' + CXXFLAGS = CFLAGS POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' elif PLATFORM == 'iar':