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92338d50
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体验新版 GitCode,发现更多精彩内容 >>
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92338d50
编写于
12月 10, 2018
作者:
B
Bernard Xiong
提交者:
GitHub
12月 10, 2018
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差异文件
Merge pull request #2051 from SummerGGift/add_stm32_new_framework
[bsp][stm32] add more drivers for stm32 bsp
上级
fea5f2d8
892ad629
变更
72
隐藏空白更改
内联
并排
Showing
72 changed file
with
6275 addition
and
325 deletion
+6275
-325
bsp/stm32/libraries/HAL_Drivers/SConscript
bsp/stm32/libraries/HAL_Drivers/SConscript
+26
-5
bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
+64
-0
bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
+79
-0
bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
+82
-0
bsp/stm32/libraries/HAL_Drivers/drv_adc.c
bsp/stm32/libraries/HAL_Drivers/drv_adc.c
+238
-0
bsp/stm32/libraries/HAL_Drivers/drv_config.h
bsp/stm32/libraries/HAL_Drivers/drv_config.h
+3
-0
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
+23
-0
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
+185
-0
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
+312
-0
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
+277
-0
bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
+206
-0
bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
+266
-0
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+2
-1
bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
+80
-0
bsp/stm32/stm32f103-atk-nano/README.md
bsp/stm32/stm32f103-atk-nano/README.md
+5
-0
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/.mxproject
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/.mxproject
+4
-4
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
...103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
+3
-3
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c
+128
-1
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
...f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
+113
-0
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc
.../stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc
+46
-19
bsp/stm32/stm32f103-atk-nano/board/Kconfig
bsp/stm32/stm32f103-atk-nano/board/Kconfig
+36
-0
bsp/stm32/stm32f103-atk-nano/board/SConscript
bsp/stm32/stm32f103-atk-nano/board/SConscript
+1
-0
bsp/stm32/stm32f103-atk-nano/board/board.h
bsp/stm32/stm32f103-atk-nano/board/board.h
+4
-0
bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
+34
-0
bsp/stm32/stm32f103-fire-arbitrary/README.md
bsp/stm32/stm32f103-fire-arbitrary/README.md
+5
-2
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject
...2/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject
+2
-2
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
...re-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
+3
-3
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c
...2/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c
+128
-2
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
...ire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
+113
-0
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc
...f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc
+55
-32
bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig
bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig
+39
-0
bsp/stm32/stm32f103-fire-arbitrary/board/SConscript
bsp/stm32/stm32f103-fire-arbitrary/board/SConscript
+2
-1
bsp/stm32/stm32f103-fire-arbitrary/board/board.h
bsp/stm32/stm32f103-fire-arbitrary/board/board.h
+4
-0
bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
+34
-0
bsp/stm32/stm32f407-atk-explorer/README.md
bsp/stm32/stm32f407-atk-explorer/README.md
+4
-2
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject
...m32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject
+2
-2
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc
...32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc
+51
-29
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
...atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
+3
-3
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c
...m32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c
+135
-1
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
...-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
+111
-0
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
+33
-0
bsp/stm32/stm32f407-atk-explorer/board/SConscript
bsp/stm32/stm32f407-atk-explorer/board/SConscript
+2
-1
bsp/stm32/stm32f407-atk-explorer/board/board.h
bsp/stm32/stm32f407-atk-explorer/board/board.h
+6
-2
bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
+34
-0
bsp/stm32/stm32f429-atk-apollo/.config
bsp/stm32/stm32f429-atk-apollo/.config
+29
-4
bsp/stm32/stm32f429-atk-apollo/README.md
bsp/stm32/stm32f429-atk-apollo/README.md
+5
-3
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject
...stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject
+4
-4
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
...9-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
+5
-5
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc
.../stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc
+223
-60
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c
...stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c
+170
-33
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
...29-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
+278
-41
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/system_stm32f4xx.c
...429-atk-apollo/board/CubeMX_Config/Src/system_stm32f4xx.c
+761
-0
bsp/stm32/stm32f429-atk-apollo/board/Kconfig
bsp/stm32/stm32f429-atk-apollo/board/Kconfig
+39
-2
bsp/stm32/stm32f429-atk-apollo/board/SConscript
bsp/stm32/stm32f429-atk-apollo/board/SConscript
+5
-0
bsp/stm32/stm32f429-atk-apollo/board/board.h
bsp/stm32/stm32f429-atk-apollo/board/board.h
+4
-0
bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
+34
-0
bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
+65
-0
bsp/stm32/stm32f429-atk-apollo/rtconfig.h
bsp/stm32/stm32f429-atk-apollo/rtconfig.h
+9
-2
bsp/stm32/stm32f429-fire-challenger/.config
bsp/stm32/stm32f429-fire-challenger/.config
+30
-4
bsp/stm32/stm32f429-fire-challenger/README.md
bsp/stm32/stm32f429-fire-challenger/README.md
+6
-3
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/.mxproject
.../stm32f429-fire-challenger/board/CubeMX_Config/.mxproject
+4
-8
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc
...429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc
+203
-31
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
...e-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
+4
-4
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c
.../stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c
+177
-2
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
...re-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
+314
-0
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/system_stm32f4xx.c
...ire-challenger/board/CubeMX_Config/Src/system_stm32f4xx.c
+761
-0
bsp/stm32/stm32f429-fire-challenger/board/Kconfig
bsp/stm32/stm32f429-fire-challenger/board/Kconfig
+45
-2
bsp/stm32/stm32f429-fire-challenger/board/SConscript
bsp/stm32/stm32f429-fire-challenger/board/SConscript
+4
-0
bsp/stm32/stm32f429-fire-challenger/board/board.h
bsp/stm32/stm32f429-fire-challenger/board/board.h
+4
-0
bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
+34
-0
bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
+65
-0
bsp/stm32/stm32f429-fire-challenger/rtconfig.h
bsp/stm32/stm32f429-fire-challenger/rtconfig.h
+10
-2
未找到文件。
bsp/stm32/libraries/HAL_Drivers/SConscript
浏览文件 @
92338d50
...
...
@@ -29,16 +29,37 @@ if GetDepend(['RT_USING_SDCARD']):
if
GetDepend
([
'RT_USING_I2C'
,
'RT_USING_I2C_BITOPS'
]):
src
+=
[
'drv_soft_i2c.c'
]
if
GetDepend
([
'RT_USING_WDT'
]):
src
+=
[
'drv_iwg.c'
]
if
GetDepend
(
'RT_USING_LWIP'
):
src
+=
[
'drv_emac.c'
]
if
GetDepend
([
'RT_USING_ADC'
]):
src
+=
Glob
(
'drv_adc.c'
)
if
GetDepend
(
'BSP_USING_SDRAM'
):
src
+=
[
'drv_sdram.c'
]
if
GetDepend
(
'BSP_USING_ONCHIP_RTC'
):
src
+=
[
'drv_rtc.c'
]
if
GetDepend
([
'BSP_USING_ON_CHIP_FLASH'
,
'SOC_SERIES_STM32F1'
]):
src
+=
[
'drv_flash/drv_flash_f1.c'
]
if
GetDepend
([
'BSP_USING_ON_CHIP_FLASH'
,
'SOC_SERIES_STM32F4'
]):
src
+=
[
'drv_flash/drv_flash_f4.c'
]
if
GetDepend
([
'BSP_USING_ON_CHIP_FLASH'
,
'SOC_SERIES_STM32L4'
]):
src
+=
[
'drv_flash/drv_flash_l4.c'
]
if
GetDepend
([
'BSP_USING_WDT'
]):
src
+=
[
'drv_wdt.c'
]
src
+=
[
'drv_common.c'
]
path
=
[
cwd
]
path
+=
[
cwd
+
'/config'
]
path
=
[
cwd
]
path
+=
[
cwd
+
'/config'
]
if
GetDepend
(
'BSP_USING_ON_CHIP_FLASH'
):
path
+=
[
cwd
+
'/drv_flash'
]
group
=
DefineGroup
(
'Drivers'
,
src
,
depend
=
[
''
],
CPPPATH
=
path
)
...
...
bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-07 zylx first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.Instance = ADC1, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
#endif
/* ADC1_CONFIG */
#endif
/* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.Instance = ADC2, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
#endif
/* ADC2_CONFIG */
#endif
/* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.Instance = ADC3, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
}
#endif
/* ADC3_CONFIG */
#endif
/* BSP_USING_ADC3 */
#endif
/* __ADC_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-06 zylx first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.Instance = ADC1, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = DISABLE, \
.Init.EOCSelection = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 0, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.DMAContinuousRequests = DISABLE, \
}
#endif
/* ADC1_CONFIG */
#endif
/* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.Instance = ADC2, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = DISABLE, \
.Init.EOCSelection = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 0, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.DMAContinuousRequests = DISABLE, \
}
#endif
/* ADC2_CONFIG */
#endif
/* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.Instance = ADC3, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = DISABLE, \
.Init.EOCSelection = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 0, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.DMAContinuousRequests = DISABLE, \
}
#endif
/* ADC3_CONFIG */
#endif
/* BSP_USING_ADC3 */
#endif
/* __ADC_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-07 zylx first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.Instance = ADC1, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
.Init.LowPowerAutoWait = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.DMAContinuousRequests = DISABLE, \
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
}
#endif
/* ADC1_CONFIG */
#endif
/* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.Instance = ADC2, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
.Init.LowPowerAutoWait = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.DMAContinuousRequests = DISABLE, \
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
}
#endif
/* ADC2_CONFIG */
#endif
/* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.Instance = ADC3, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
.Init.LowPowerAutoWait = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.DMAContinuousRequests = DISABLE, \
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
}
#endif
/* ADC3_CONFIG */
#endif
/* BSP_USING_ADC3 */
#endif
/* __ADC_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/drv_adc.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx first version
*/
#include <board.h>
#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
#include "drv_config.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.adc"
#include <drv_log.h>
static
ADC_HandleTypeDef
adc_config
[]
=
{
#ifdef BSP_USING_ADC1
ADC1_CONFIG
,
#endif
#ifdef BSP_USING_ADC2
ADC2_CONFIG
,
#endif
#ifdef BSP_USING_ADC3
ADC3_CONFIG
,
#endif
};
struct
stm32_adc
{
ADC_HandleTypeDef
ADC_Handler
;
struct
rt_adc_device
stm32_adc_device
;
};
static
struct
stm32_adc
stm32_adc_obj
[
sizeof
(
adc_config
)
/
sizeof
(
adc_config
[
0
])];
static
rt_err_t
stm32_adc_enabled
(
struct
rt_adc_device
*
device
,
rt_uint32_t
channel
,
rt_bool_t
enabled
)
{
ADC_HandleTypeDef
*
stm32_adc_handler
=
device
->
parent
.
user_data
;
RT_ASSERT
(
device
!=
RT_NULL
);
if
(
enabled
)
{
#ifdef SOC_SERIES_STM32L4
ADC_Enable
(
stm32_adc_handler
);
#else
__HAL_ADC_ENABLE
(
stm32_adc_handler
);
#endif
}
else
{
#ifdef SOC_SERIES_STM32L4
ADC_Disable
(
stm32_adc_handler
);
#else
__HAL_ADC_DISABLE
(
stm32_adc_handler
);
#endif
}
return
RT_EOK
;
}
static
rt_uint32_t
stm32_adc_get_channel
(
rt_uint32_t
channel
)
{
rt_uint32_t
stm32_channel
=
0
;
switch
(
channel
)
{
case
0
:
stm32_channel
=
ADC_CHANNEL_0
;
break
;
case
1
:
stm32_channel
=
ADC_CHANNEL_1
;
break
;
case
2
:
stm32_channel
=
ADC_CHANNEL_2
;
break
;
case
3
:
stm32_channel
=
ADC_CHANNEL_3
;
break
;
case
4
:
stm32_channel
=
ADC_CHANNEL_4
;
break
;
case
5
:
stm32_channel
=
ADC_CHANNEL_5
;
break
;
case
6
:
stm32_channel
=
ADC_CHANNEL_6
;
break
;
case
7
:
stm32_channel
=
ADC_CHANNEL_7
;
break
;
case
8
:
stm32_channel
=
ADC_CHANNEL_8
;
break
;
case
9
:
stm32_channel
=
ADC_CHANNEL_9
;
break
;
case
10
:
stm32_channel
=
ADC_CHANNEL_10
;
break
;
case
11
:
stm32_channel
=
ADC_CHANNEL_11
;
break
;
case
12
:
stm32_channel
=
ADC_CHANNEL_12
;
break
;
case
13
:
stm32_channel
=
ADC_CHANNEL_13
;
break
;
case
14
:
stm32_channel
=
ADC_CHANNEL_14
;
break
;
case
15
:
stm32_channel
=
ADC_CHANNEL_15
;
break
;
case
16
:
stm32_channel
=
ADC_CHANNEL_16
;
break
;
case
17
:
stm32_channel
=
ADC_CHANNEL_17
;
break
;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
case
18
:
stm32_channel
=
ADC_CHANNEL_18
;
break
;
#endif
}
return
stm32_channel
;
}
static
rt_err_t
stm32_get_adc_value
(
struct
rt_adc_device
*
device
,
rt_uint32_t
channel
,
rt_uint32_t
*
value
)
{
ADC_ChannelConfTypeDef
ADC_ChanConf
;
ADC_HandleTypeDef
*
stm32_adc_handler
=
device
->
parent
.
user_data
;
RT_ASSERT
(
device
!=
RT_NULL
);
RT_ASSERT
(
value
!=
RT_NULL
);
rt_memset
(
&
ADC_ChanConf
,
0
,
sizeof
(
ADC_ChanConf
));
#if defined(SOC_SERIES_STM32F1)
if
(
channel
<=
17
)
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
if
(
channel
<=
18
)
#endif
{
/* set stm32 ADC channel */
ADC_ChanConf
.
Channel
=
stm32_adc_get_channel
(
channel
);
}
else
{
#if defined(SOC_SERIES_STM32F1)
LOG_E
(
"ADC channel must be between 0 and 17."
);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
LOG_E
(
"ADC channel must be between 0 and 18."
);
#endif
return
-
RT_ERROR
;
}
ADC_ChanConf
.
Rank
=
1
;
#if defined(SOC_SERIES_STM32F1)
ADC_ChanConf
.
SamplingTime
=
ADC_SAMPLETIME_55CYCLES_5
;
#elif defined(SOC_SERIES_STM32F4)
ADC_ChanConf
.
SamplingTime
=
ADC_SAMPLETIME_112CYCLES
;
#elif defined(SOC_SERIES_STM32L4)
ADC_ChanConf
.
SamplingTime
=
ADC_SAMPLETIME_247CYCLES_5
;
#endif
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
ADC_ChanConf
.
Offset
=
0
;
#endif
#ifdef SOC_SERIES_STM32L4
ADC_ChanConf
.
OffsetNumber
=
ADC_OFFSET_NONE
;
ADC_ChanConf
.
SingleDiff
=
LL_ADC_SINGLE_ENDED
;
#endif
HAL_ADC_ConfigChannel
(
stm32_adc_handler
,
&
ADC_ChanConf
);
/* start ADC */
HAL_ADC_Start
(
stm32_adc_handler
);
/* Wait for the ADC to convert */
HAL_ADC_PollForConversion
(
stm32_adc_handler
,
10
);
/* get ADC value */
*
value
=
(
rt_uint32_t
)
HAL_ADC_GetValue
(
stm32_adc_handler
);
return
RT_EOK
;
}
static
const
struct
rt_adc_ops
stm_adc_ops
=
{
.
enabled
=
stm32_adc_enabled
,
.
convert
=
stm32_get_adc_value
,
};
static
int
stm32_adc_init
(
void
)
{
int
result
=
RT_EOK
;
/* save adc name */
char
name_buf
[
6
]
=
{
0
};
int
i
=
0
;
for
(
i
=
0
;
i
<
sizeof
(
adc_config
)
/
sizeof
(
adc_config
[
0
]);
i
++
)
{
/* ADC init */
stm32_adc_obj
[
i
].
ADC_Handler
=
adc_config
[
i
];
if
(
HAL_ADC_Init
(
&
stm32_adc_obj
[
i
].
ADC_Handler
)
!=
HAL_OK
)
{
LOG_E
(
"ADC%d init failed"
,
i
+
1
);
result
=
-
RT_ERROR
;
}
else
{
rt_sprintf
(
name_buf
,
"adc%d"
,
i
+
1
);
/* register ADC device */
if
(
rt_hw_adc_register
(
&
stm32_adc_obj
[
i
].
stm32_adc_device
,
name_buf
,
&
stm_adc_ops
,
&
stm32_adc_obj
[
i
].
ADC_Handler
)
==
RT_EOK
)
{
LOG_D
(
"ADC%d init success"
,
i
+
1
);
}
else
{
LOG_E
(
"ADC%d register failed"
,
i
+
1
);
result
=
-
RT_ERROR
;
}
}
}
return
result
;
}
INIT_BOARD_EXPORT
(
stm32_adc_init
);
#endif
/* BSP_USING_ADC */
bsp/stm32/libraries/HAL_Drivers/drv_config.h
浏览文件 @
92338d50
...
...
@@ -17,12 +17,15 @@
#if defined(SOC_SERIES_STM32F1)
#include "f1/uart_config.h"
#include "f1/spi_config.h"
#include "f1/adc_config.h"
#elif defined(SOC_SERIES_STM32F4)
#include "f4/uart_config.h"
#include "f4/spi_config.h"
#include "f4/adc_config.h"
#elif defined(SOC_SERIES_STM32L4)
#include "l4/uart_config.h"
#include "l4/spi_config.h"
#include "l4/adc_config.h"
#endif
#endif
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
int
stm32_flash_read
(
long
offset
,
rt_uint8_t
*
buf
,
size_t
size
);
int
stm32_flash_write
(
long
offset
,
const
rt_uint8_t
*
buf
,
size_t
size
);
int
stm32_flash_erase
(
long
offset
,
size_t
size
);
#endif
/* __DRV_FLASH_H__ */
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static
uint32_t
GetPage
(
uint32_t
addr
)
{
uint32_t
page
=
0
;
page
=
RT_ALIGN_DOWN
(
addr
,
FLASH_PAGE_SIZE
);
return
page
;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int
stm32_flash_read
(
long
offset
,
rt_uint8_t
*
buf
,
size_t
size
)
{
size_t
i
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"read outrange flash size! addr is (0x%p)"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
for
(
i
=
0
;
i
<
size
;
i
++
,
buf
++
,
addr
++
)
{
*
buf
=
*
(
rt_uint8_t
*
)
addr
;
}
return
size
;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int
stm32_flash_write
(
long
offset
,
const
rt_uint8_t
*
buf
,
size_t
size
)
{
rt_err_t
result
=
RT_EOK
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
rt_uint32_t
end_addr
=
addr
+
size
;
if
(
addr
%
4
!=
0
)
{
LOG_E
(
"write addr must be 4-byte alignment"
);
return
-
RT_EINVAL
;
}
if
(
size
%
4
!=
0
)
{
LOG_E
(
"write size must be 4-byte alignment"
);
return
-
RT_EINVAL
;
}
if
((
end_addr
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"write outrange flash size! addr is (0x%p)"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
HAL_FLASH_Unlock
();
while
(
addr
<
end_addr
)
{
if
(
HAL_FLASH_Program
(
FLASH_TYPEPROGRAM_WORD
,
addr
,
*
((
rt_uint32_t
*
)
buf
))
==
HAL_OK
)
{
if
(
*
(
rt_uint32_t
*
)
addr
!=
*
(
rt_uint32_t
*
)
buf
)
{
result
=
-
RT_ERROR
;
break
;
}
addr
+=
4
;
buf
+=
4
;
}
else
{
result
=
-
RT_ERROR
;
break
;
}
}
HAL_FLASH_Lock
();
if
(
result
!=
RT_EOK
)
{
return
result
;
}
return
size
;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int
stm32_flash_erase
(
long
offset
,
size_t
size
)
{
rt_err_t
result
=
RT_EOK
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
uint32_t
PAGEError
=
0
;
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef
EraseInitStruct
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"ERROR: erase outrange flash size! addr is (0x%p)
\n
"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
HAL_FLASH_Unlock
();
/* Fill EraseInit structure*/
EraseInitStruct
.
TypeErase
=
FLASH_TYPEERASE_PAGES
;
EraseInitStruct
.
PageAddress
=
GetPage
(
addr
);
EraseInitStruct
.
NbPages
=
(
size
+
FLASH_PAGE_SIZE
-
1
)
/
FLASH_PAGE_SIZE
;
if
(
HAL_FLASHEx_Erase
(
&
EraseInitStruct
,
&
PAGEError
)
!=
HAL_OK
)
{
result
=
-
RT_ERROR
;
goto
__exit
;
}
__exit:
HAL_FLASH_Lock
();
if
(
result
!=
RT_EOK
)
{
return
result
;
}
LOG_D
(
"erase done: addr (0x%p), size %d"
,
(
void
*
)
addr
,
size
);
return
result
;
}
#if defined(PKG_USING_FAL)
const
struct
fal_flash_dev
stm32_onchip_flash
=
{
"onchip_flash"
,
STM32_FLASH_START_ADRESS
,
STM32_FLASH_SIZE
,
FLASH_PAGE_SIZE
,
{
NULL
,
stm32_flash_read
,
stm32_flash_write
,
stm32_flash_erase
}
};
#endif
#endif
/* BSP_USING_ON_CHIP_FLASH */
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/* Base address of the Flash sectors Bank 1 */
#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000)
/* Base @ of Sector 0, 16 Kbytes */
#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000)
/* Base @ of Sector 1, 16 Kbytes */
#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000)
/* Base @ of Sector 2, 16 Kbytes */
#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000)
/* Base @ of Sector 3, 16 Kbytes */
#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000)
/* Base @ of Sector 4, 64 Kbytes */
#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000)
/* Base @ of Sector 5, 128 Kbytes */
#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000)
/* Base @ of Sector 6, 128 Kbytes */
#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000)
/* Base @ of Sector 7, 128 Kbytes */
#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000)
/* Base @ of Sector 8, 128 Kbytes */
#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000)
/* Base @ of Sector 9, 128 Kbytes */
#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000)
/* Base @ of Sector 10, 128 Kbytes */
#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000)
/* Base @ of Sector 11, 128 Kbytes */
/* Base address of the Flash sectors Bank 2 */
#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000)
/* Base @ of Sector 0, 16 Kbytes */
#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000)
/* Base @ of Sector 1, 16 Kbytes */
#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000)
/* Base @ of Sector 2, 16 Kbytes */
#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000)
/* Base @ of Sector 3, 16 Kbytes */
#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000)
/* Base @ of Sector 4, 64 Kbytes */
#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000)
/* Base @ of Sector 5, 128 Kbytes */
#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000)
/* Base @ of Sector 6, 128 Kbytes */
#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000)
/* Base @ of Sector 7, 128 Kbytes */
#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000)
/* Base @ of Sector 8, 128 Kbytes */
#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000)
/* Base @ of Sector 9, 128 Kbytes */
#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000)
/* Base @ of Sector 10, 128 Kbytes */
#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000)
/* Base @ of Sector 11, 128 Kbytes */
/**
* @brief Gets the sector of a given address
* @param None
* @retval The sector of a given address
*/
static
rt_uint32_t
GetSector
(
rt_uint32_t
Address
)
{
rt_uint32_t
sector
=
0
;
if
((
Address
<
ADDR_FLASH_SECTOR_1
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_0
))
{
sector
=
FLASH_SECTOR_0
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_2
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_1
))
{
sector
=
FLASH_SECTOR_1
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_3
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_2
))
{
sector
=
FLASH_SECTOR_2
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_4
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_3
))
{
sector
=
FLASH_SECTOR_3
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_5
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_4
))
{
sector
=
FLASH_SECTOR_4
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_6
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_5
))
{
sector
=
FLASH_SECTOR_5
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_7
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_6
))
{
sector
=
FLASH_SECTOR_6
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_8
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_7
))
{
sector
=
FLASH_SECTOR_7
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_9
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_8
))
{
sector
=
FLASH_SECTOR_8
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_10
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_9
))
{
sector
=
FLASH_SECTOR_9
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_11
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_10
))
{
sector
=
FLASH_SECTOR_10
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_12
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_11
))
{
sector
=
FLASH_SECTOR_11
;
}
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
else
if
((
Address
<
ADDR_FLASH_SECTOR_13
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_12
))
{
sector
=
FLASH_SECTOR_12
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_14
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_13
))
{
sector
=
FLASH_SECTOR_13
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_15
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_14
))
{
sector
=
FLASH_SECTOR_14
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_16
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_15
))
{
sector
=
FLASH_SECTOR_15
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_17
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_16
))
{
sector
=
FLASH_SECTOR_16
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_18
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_17
))
{
sector
=
FLASH_SECTOR_17
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_19
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_18
))
{
sector
=
FLASH_SECTOR_18
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_20
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_19
))
{
sector
=
FLASH_SECTOR_19
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_21
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_20
))
{
sector
=
FLASH_SECTOR_20
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_22
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_21
))
{
sector
=
FLASH_SECTOR_21
;
}
else
if
((
Address
<
ADDR_FLASH_SECTOR_23
)
&&
(
Address
>=
ADDR_FLASH_SECTOR_22
))
{
sector
=
FLASH_SECTOR_22
;
}
else
/* (Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_23) */
{
sector
=
FLASH_SECTOR_23
;
}
#endif
return
sector
;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int
stm32_flash_read
(
long
offset
,
rt_uint8_t
*
buf
,
size_t
size
)
{
size_t
i
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"read outrange flash size! addr is (0x%p)"
,
(
void
*
)(
addr
+
size
));
return
-
1
;
}
for
(
i
=
0
;
i
<
size
;
i
++
,
buf
++
,
addr
++
)
{
*
buf
=
*
(
rt_uint8_t
*
)
addr
;
}
return
size
;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int
stm32_flash_write
(
long
offset
,
const
rt_uint8_t
*
buf
,
size_t
size
)
{
rt_err_t
result
=
RT_EOK
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
rt_uint32_t
end_addr
=
addr
+
size
;
if
((
end_addr
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"write outrange flash size! addr is (0x%p)"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
if
(
size
<
1
)
{
return
-
RT_EINVAL
;
}
HAL_FLASH_Unlock
();
__HAL_FLASH_CLEAR_FLAG
(
FLASH_FLAG_EOP
|
FLASH_FLAG_OPERR
|
FLASH_FLAG_WRPERR
|
FLASH_FLAG_PGAERR
|
FLASH_FLAG_PGSERR
);
for
(
size_t
i
=
0
;
i
<
size
;
i
++
,
addr
++
,
buf
++
)
{
/* write data to flash */
if
(
HAL_FLASH_Program
(
FLASH_TYPEPROGRAM_BYTE
,
addr
,
(
rt_uint64_t
)(
*
buf
))
==
HAL_OK
)
{
if
(
*
(
rt_uint8_t
*
)
addr
!=
*
buf
)
{
result
=
-
RT_ERROR
;
break
;
}
}
else
{
result
=
-
RT_ERROR
;
break
;
}
}
HAL_FLASH_Lock
();
if
(
result
!=
RT_EOK
)
{
return
result
;
}
return
size
;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int
stm32_flash_erase
(
long
offset
,
size_t
size
)
{
rt_err_t
result
=
RT_EOK
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
rt_uint32_t
FirstSector
=
0
,
NbOfSectors
=
0
;
rt_uint32_t
SECTORError
=
0
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"ERROR: erase outrange flash size! addr is (0x%p)
\n
"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef
EraseInitStruct
;
/* Unlock the Flash to enable the flash control register access */
HAL_FLASH_Unlock
();
/* Get the 1st sector to erase */
FirstSector
=
GetSector
(
addr
);
/* Get the number of sector to erase from 1st sector*/
NbOfSectors
=
GetSector
(
addr
+
size
)
-
FirstSector
+
1
;
/* Fill EraseInit structure*/
EraseInitStruct
.
TypeErase
=
FLASH_TYPEERASE_SECTORS
;
EraseInitStruct
.
VoltageRange
=
FLASH_VOLTAGE_RANGE_3
;
EraseInitStruct
.
Sector
=
FirstSector
;
EraseInitStruct
.
NbSectors
=
NbOfSectors
;
if
(
HAL_FLASHEx_Erase
(
&
EraseInitStruct
,
&
SECTORError
)
!=
HAL_OK
)
{
result
=
-
RT_ERROR
;
goto
__exit
;
}
__exit:
HAL_FLASH_Lock
();
if
(
result
!=
RT_EOK
)
{
return
result
;
}
LOG_D
(
"erase done: addr (0x%p), size %d"
,
(
void
*
)
addr
,
size
);
return
result
;
}
#if defined(PKG_USING_FAL)
const
struct
fal_flash_dev
stm32_onchip_flash
=
{
"onchip_flash"
,
STM32_FLASH_START_ADRESS
,
STM32_FLASH_SIZE
,
(
128
*
1024
),
{
NULL
,
stm32_flash_read
,
stm32_flash_write
,
stm32_flash_erase
}
};
#endif
#endif
/* BSP_USING_ON_CHIP_FLASH */
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static
uint32_t
GetPage
(
uint32_t
Addr
)
{
uint32_t
page
=
0
;
if
(
Addr
<
(
FLASH_BASE
+
FLASH_BANK_SIZE
))
{
/* Bank 1 */
page
=
(
Addr
-
FLASH_BASE
)
/
FLASH_PAGE_SIZE
;
}
else
{
/* Bank 2 */
page
=
(
Addr
-
(
FLASH_BASE
+
FLASH_BANK_SIZE
))
/
FLASH_PAGE_SIZE
;
}
return
page
;
}
/**
* @brief Gets the bank of a given address
* @param Addr: Address of the FLASH Memory
* @retval The bank of a given address
*/
static
uint32_t
GetBank
(
uint32_t
Addr
)
{
uint32_t
bank
=
0
;
if
(
READ_BIT
(
SYSCFG
->
MEMRMP
,
SYSCFG_MEMRMP_FB_MODE
)
==
0
)
{
/* No Bank swap */
if
(
Addr
<
(
FLASH_BASE
+
FLASH_BANK_SIZE
))
{
bank
=
FLASH_BANK_1
;
}
else
{
bank
=
FLASH_BANK_2
;
}
}
else
{
/* Bank swap */
if
(
Addr
<
(
FLASH_BASE
+
FLASH_BANK_SIZE
))
{
bank
=
FLASH_BANK_2
;
}
else
{
bank
=
FLASH_BANK_1
;
}
}
return
bank
;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int
stm32_flash_read
(
long
offset
,
rt_uint8_t
*
buf
,
size_t
size
)
{
size_t
i
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"read outrange flash size! addr is (0x%p)"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
for
(
i
=
0
;
i
<
size
;
i
++
,
buf
++
,
addr
++
)
{
*
buf
=
*
(
rt_uint8_t
*
)
addr
;
}
return
size
;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int
stm32_flash_write
(
long
offset
,
const
uint8_t
*
buf
,
size_t
size
)
{
size_t
i
,
j
;
rt_err_t
result
=
0
;
rt_uint64_t
write_data
=
0
,
temp_data
=
0
;
rt_uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"ERROR: write outrange flash size! addr is (0x%p)
\n
"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
if
(
addr
%
8
!=
0
)
{
LOG_E
(
"write addr must be 8-byte alignment"
);
return
-
RT_EINVAL
;
}
if
(
size
%
8
!=
0
)
{
LOG_E
(
"write size must be 8-byte alignment"
);
return
-
RT_EINVAL
;
}
HAL_FLASH_Unlock
();
__HAL_FLASH_CLEAR_FLAG
(
FLASH_FLAG_EOP
|
FLASH_FLAG_OPERR
|
FLASH_FLAG_WRPERR
|
FLASH_FLAG_PGAERR
|
FLASH_FLAG_PGSERR
);
if
(
size
<
1
)
{
return
-
RT_ERROR
;
}
for
(
i
=
0
;
i
<
size
;)
{
if
((
size
-
i
)
<
8
)
{
for
(
j
=
0
;
(
size
-
i
)
>
0
;
i
++
,
j
++
)
{
temp_data
=
*
buf
;
write_data
=
(
write_data
)
|
(
temp_data
<<
8
*
j
);
buf
++
;
}
}
else
{
for
(
j
=
0
;
j
<
8
;
j
++
,
i
++
)
{
temp_data
=
*
buf
;
write_data
=
(
write_data
)
|
(
temp_data
<<
8
*
j
);
buf
++
;
}
}
/* write data */
if
(
HAL_FLASH_Program
(
FLASH_TYPEPROGRAM_DOUBLEWORD
,
addr
,
write_data
)
==
HAL_OK
)
{
/* Check the written value */
if
(
*
(
uint64_t
*
)
addr
!=
write_data
)
{
LOG_E
(
"ERROR: write data != read data
\n
"
);
result
=
-
RT_ERROR
;
goto
__exit
;
}
}
else
{
result
=
-
RT_ERROR
;
goto
__exit
;
}
temp_data
=
0
;
write_data
=
0
;
addr
+=
8
;
}
__exit:
HAL_FLASH_Lock
();
if
(
result
!=
0
)
{
return
result
;
}
return
size
;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int
stm32_flash_erase
(
long
offset
,
size_t
size
)
{
rt_err_t
result
=
RT_EOK
;
uint32_t
addr
=
STM32_FLASH_START_ADRESS
+
offset
;
uint32_t
FirstPage
=
0
,
NbOfPages
=
0
,
BankNumber
=
0
;
uint32_t
PAGEError
=
0
;
if
((
addr
+
size
)
>
STM32_FLASH_END_ADDRESS
)
{
LOG_E
(
"ERROR: erase outrange flash size! addr is (0x%p)
\n
"
,
(
void
*
)(
addr
+
size
));
return
-
RT_EINVAL
;
}
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef
EraseInitStruct
;
/* Unlock the Flash to enable the flash control register access *************/
HAL_FLASH_Unlock
();
/* Clear OPTVERR bit set on virgin samples */
__HAL_FLASH_CLEAR_FLAG
(
FLASH_FLAG_OPTVERR
);
/* Get the 1st page to erase */
FirstPage
=
GetPage
(
addr
);
/* Get the number of pages to erase from 1st page */
NbOfPages
=
GetPage
(
addr
+
size
)
-
FirstPage
+
1
;
/* Get the bank */
BankNumber
=
GetBank
(
addr
);
/* Fill EraseInit structure*/
EraseInitStruct
.
TypeErase
=
FLASH_TYPEERASE_PAGES
;
EraseInitStruct
.
Banks
=
BankNumber
;
EraseInitStruct
.
Page
=
FirstPage
;
EraseInitStruct
.
NbPages
=
NbOfPages
;
if
(
HAL_FLASHEx_Erase
(
&
EraseInitStruct
,
&
PAGEError
)
!=
HAL_OK
)
{
result
=
-
RT_ERROR
;
goto
__exit
;
}
__exit:
HAL_FLASH_Lock
();
if
(
result
!=
RT_EOK
)
{
return
result
;
}
LOG_D
(
"erase done: addr (0x%p), size %d"
,
(
void
*
)
addr
,
size
);
return
size
;
}
#if defined(PKG_USING_FAL)
const
struct
fal_flash_dev
stm32_onchip_flash
=
{
"onchip_flash"
,
STM32_FLASH_START_ADRESS
,
STM32_FLASH_SIZE
,
2048
,
{
NULL
,
stm32_flash_read
,
stm32_flash_write
,
stm32_flash_erase
}
};
#endif
#endif
/* BSP_USING_ON_CHIP_FLASH */
bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-04 balanceTWK change to new framework
*/
#include "board.h"
#ifdef BSP_USING_ONCHIP_RTC
//#define DRV_DEBUG
#define LOG_TAG "drv.rtc"
#include <drv_log.h>
#define BKUP_REG_DATA 0xA5A5
static
struct
rt_device
rtc
;
static
RTC_HandleTypeDef
RTC_Handler
;
static
time_t
get_rtc_timestamp
(
void
)
{
RTC_TimeTypeDef
RTC_TimeStruct
;
RTC_DateTypeDef
RTC_DateStruct
;
struct
tm
tm_new
;
HAL_RTC_GetTime
(
&
RTC_Handler
,
&
RTC_TimeStruct
,
RTC_FORMAT_BIN
);
HAL_RTC_GetDate
(
&
RTC_Handler
,
&
RTC_DateStruct
,
RTC_FORMAT_BIN
);
tm_new
.
tm_sec
=
RTC_TimeStruct
.
Seconds
;
tm_new
.
tm_min
=
RTC_TimeStruct
.
Minutes
;
tm_new
.
tm_hour
=
RTC_TimeStruct
.
Hours
;
tm_new
.
tm_mday
=
RTC_DateStruct
.
Date
;
tm_new
.
tm_mon
=
RTC_DateStruct
.
Month
-
1
;
tm_new
.
tm_year
=
RTC_DateStruct
.
Year
+
100
;
LOG_D
(
"get rtc time."
);
return
mktime
(
&
tm_new
);
}
static
rt_err_t
set_rtc_time_stamp
(
time_t
time_stamp
)
{
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
;
RTC_TimeTypeDef
RTC_TimeStruct
;
RTC_DateTypeDef
RTC_DateStruct
;
struct
tm
*
p_tm
;
HAL_PWR_EnableBkUpAccess
();
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
);
p_tm
=
localtime
(
&
time_stamp
);
if
(
p_tm
->
tm_year
<
100
)
{
return
-
RT_ERROR
;
}
RTC_TimeStruct
.
Seconds
=
p_tm
->
tm_sec
;
RTC_TimeStruct
.
Minutes
=
p_tm
->
tm_min
;
RTC_TimeStruct
.
Hours
=
p_tm
->
tm_hour
;
RTC_DateStruct
.
Date
=
p_tm
->
tm_mday
;
RTC_DateStruct
.
Month
=
p_tm
->
tm_mon
+
1
;
RTC_DateStruct
.
Year
=
p_tm
->
tm_year
-
100
;
RTC_DateStruct
.
WeekDay
=
p_tm
->
tm_wday
+
1
;
if
(
HAL_RTC_SetTime
(
&
RTC_Handler
,
&
RTC_TimeStruct
,
RTC_FORMAT_BIN
)
!=
HAL_OK
)
{
return
-
RT_ERROR
;
}
if
(
HAL_RTC_SetDate
(
&
RTC_Handler
,
&
RTC_DateStruct
,
RTC_FORMAT_BIN
)
!=
HAL_OK
)
{
return
-
RT_ERROR
;
}
LOG_D
(
"set rtc time."
);
HAL_RTCEx_BKUPWrite
(
&
RTC_Handler
,
RTC_BKP_DR1
,
BKUP_REG_DATA
);
return
RT_EOK
;
}
static
void
rt_rtc_init
(
void
)
{
__HAL_RCC_PWR_CLK_ENABLE
();
RCC_OscInitTypeDef
RCC_OscInitStruct
;
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_NONE
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
);
}
static
rt_err_t
rt_rtc_config
(
struct
rt_device
*
dev
)
{
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
;
HAL_PWR_EnableBkUpAccess
();
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
);
RTC_Handler
.
Instance
=
RTC
;
if
(
HAL_RTCEx_BKUPRead
(
&
RTC_Handler
,
RTC_BKP_DR1
)
!=
BKUP_REG_DATA
)
{
LOG_W
(
"RTC hasn't been configured, please use <date> command to config."
);
#if defined(SOC_SERIES_STM32F1)
RTC_Handler
.
Init
.
OutPut
=
RTC_OUTPUTSOURCE_NONE
;
RTC_Handler
.
Init
.
AsynchPrediv
=
RTC_AUTO_1_SECOND
;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
RTC_Handler
.
Init
.
AsynchPrediv
=
0X7F
;
RTC_Handler
.
Init
.
SynchPrediv
=
0XFF
;
RTC_Handler
.
Init
.
HourFormat
=
RTC_HOURFORMAT_24
;
RTC_Handler
.
Init
.
OutPut
=
RTC_OUTPUT_DISABLE
;
RTC_Handler
.
Init
.
OutPutPolarity
=
RTC_OUTPUT_POLARITY_HIGH
;
RTC_Handler
.
Init
.
OutPutType
=
RTC_OUTPUT_TYPE_OPENDRAIN
;
#endif
if
(
HAL_RTC_Init
(
&
RTC_Handler
)
!=
HAL_OK
)
{
return
-
RT_ERROR
;
}
}
return
RT_EOK
;
}
static
rt_err_t
rt_rtc_control
(
rt_device_t
dev
,
int
cmd
,
void
*
args
)
{
rt_err_t
result
=
RT_EOK
;
RT_ASSERT
(
dev
!=
RT_NULL
);
switch
(
cmd
)
{
case
RT_DEVICE_CTRL_RTC_GET_TIME
:
*
(
rt_uint32_t
*
)
args
=
get_rtc_timestamp
();
LOG_D
(
"RTC: get rtc_time %x
\n
"
,
*
(
rt_uint32_t
*
)
args
());
break
;
case
RT_DEVICE_CTRL_RTC_SET_TIME
:
if
(
set_rtc_time_stamp
(
*
(
rt_uint32_t
*
)
args
))
{
result
=
-
RT_ERROR
;
}
LOG_D
(
"RTC: set rtc_time %x
\n
"
,
*
(
rt_uint32_t
*
)
args
);
break
;
}
return
result
;
}
#ifdef RT_USING_DEVICE_OPS
const
static
struct
rt_device_ops
rtc_ops
=
{
RT_NULL
,
RT_NULL
,
RT_NULL
,
RT_NULL
,
RT_NULL
,
rt_rtc_control
};
#endif
static
rt_err_t
rt_hw_rtc_register
(
rt_device_t
device
,
const
char
*
name
,
rt_uint32_t
flag
)
{
RT_ASSERT
(
device
!=
RT_NULL
);
rt_rtc_init
();
if
(
rt_rtc_config
(
device
)
!=
RT_EOK
)
{
return
-
RT_ERROR
;
}
#ifdef RT_USING_DEVICE_OPS
device
->
ops
=
&
rtc_ops
;
#else
device
->
init
=
RT_NULL
;
device
->
open
=
RT_NULL
;
device
->
close
=
RT_NULL
;
device
->
read
=
RT_NULL
;
device
->
write
=
RT_NULL
;
device
->
control
=
rt_rtc_control
;
#endif
device
->
type
=
RT_Device_Class_RTC
;
device
->
rx_indicate
=
RT_NULL
;
device
->
tx_complete
=
RT_NULL
;
device
->
user_data
=
RT_NULL
;
/* register a character device */
return
rt_device_register
(
device
,
name
,
flag
);
}
int
rt_hw_rtc_init
(
void
)
{
rt_err_t
result
;
result
=
rt_hw_rtc_register
(
&
rtc
,
"rtc"
,
RT_DEVICE_FLAG_RDWR
);
if
(
result
!=
RT_EOK
)
{
LOG_E
(
"rtc register err code: %d"
,
result
);
return
result
;
}
LOG_D
(
"rtc init success"
);
return
RT_EOK
;
}
INIT_DEVICE_EXPORT
(
rt_hw_rtc_init
);
#endif
/* BSP_USING_ONCHIP_RTC */
bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-04 zylx The first version for STM32F4xx
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef BSP_USING_SDRAM
#include <sdram_port.h>
#define DRV_DEBUG
#define LOG_TAG "drv.sdram"
#include <drv_log.h>
static
SDRAM_HandleTypeDef
hsdram1
;
static
FMC_SDRAM_CommandTypeDef
command
;
#ifdef RT_USING_MEMHEAP_AS_HEAP
static
struct
rt_memheap
system_heap
;
#endif
/**
* @brief Perform the SDRAM exernal memory inialization sequence
* @param hsdram: SDRAM handle
* @param Command: Pointer to SDRAM command structure
* @retval None
*/
static
void
SDRAM_Initialization_Sequence
(
SDRAM_HandleTypeDef
*
hsdram
,
FMC_SDRAM_CommandTypeDef
*
Command
)
{
__IO
uint32_t
tmpmrd
=
0
;
uint32_t
target_bank
=
0
;
#if SDRAM_TARGET_BANK == 1
target_bank
=
FMC_SDRAM_CMD_TARGET_BANK1
;
#else
target_bank
=
FMC_SDRAM_CMD_TARGET_BANK2
;
#endif
/* Configure a clock configuration enable command */
Command
->
CommandMode
=
FMC_SDRAM_CMD_CLK_ENABLE
;
Command
->
CommandTarget
=
target_bank
;
Command
->
AutoRefreshNumber
=
1
;
Command
->
ModeRegisterDefinition
=
0
;
/* Send the command */
HAL_SDRAM_SendCommand
(
hsdram
,
Command
,
0x1000
);
/* Insert 100 ms delay */
/* interrupt is not enable, just to delay some time. */
for
(
tmpmrd
=
0
;
tmpmrd
<
0xffffff
;
tmpmrd
++
)
;
/* Configure a PALL (precharge all) command */
Command
->
CommandMode
=
FMC_SDRAM_CMD_PALL
;
Command
->
CommandTarget
=
target_bank
;
Command
->
AutoRefreshNumber
=
1
;
Command
->
ModeRegisterDefinition
=
0
;
/* Send the command */
HAL_SDRAM_SendCommand
(
hsdram
,
Command
,
0x1000
);
/* Configure a Auto-Refresh command */
Command
->
CommandMode
=
FMC_SDRAM_CMD_AUTOREFRESH_MODE
;
Command
->
CommandTarget
=
target_bank
;
Command
->
AutoRefreshNumber
=
8
;
Command
->
ModeRegisterDefinition
=
0
;
/* Send the command */
HAL_SDRAM_SendCommand
(
hsdram
,
Command
,
0x1000
);
/* Program the external memory mode register */
#if SDRAM_DATA_WIDTH == 8
tmpmrd
=
(
uint32_t
)
SDRAM_MODEREG_BURST_LENGTH_1
|
#elif SDRAM_DATA_WIDTH == 16
tmpmrd
=
(
uint32_t
)
SDRAM_MODEREG_BURST_LENGTH_2
|
#else
tmpmrd
=
(
uint32_t
)
SDRAM_MODEREG_BURST_LENGTH_4
|
#endif
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL
|
#if SDRAM_CAS_LATENCY == 3
SDRAM_MODEREG_CAS_LATENCY_3
|
#else
SDRAM_MODEREG_CAS_LATENCY_2
|
#endif
SDRAM_MODEREG_OPERATING_MODE_STANDARD
|
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
;
Command
->
CommandMode
=
FMC_SDRAM_CMD_LOAD_MODE
;
Command
->
CommandTarget
=
target_bank
;
Command
->
AutoRefreshNumber
=
1
;
Command
->
ModeRegisterDefinition
=
tmpmrd
;
/* Send the command */
HAL_SDRAM_SendCommand
(
hsdram
,
Command
,
0x1000
);
/* Set the device refresh counter */
HAL_SDRAM_ProgramRefreshRate
(
hsdram
,
SDRAM_REFRESH_COUNT
);
}
static
int
SDRAM_Init
(
void
)
{
int
result
=
RT_EOK
;
FMC_SDRAM_TimingTypeDef
SDRAM_Timing
;
/* SDRAM device configuration */
hsdram1
.
Instance
=
FMC_SDRAM_DEVICE
;
SDRAM_Timing
.
LoadToActiveDelay
=
LOADTOACTIVEDELAY
;
SDRAM_Timing
.
ExitSelfRefreshDelay
=
EXITSELFREFRESHDELAY
;
SDRAM_Timing
.
SelfRefreshTime
=
SELFREFRESHTIME
;
SDRAM_Timing
.
RowCycleDelay
=
ROWCYCLEDELAY
;
SDRAM_Timing
.
WriteRecoveryTime
=
WRITERECOVERYTIME
;
SDRAM_Timing
.
RPDelay
=
RPDELAY
;
SDRAM_Timing
.
RCDDelay
=
RCDDELAY
;
#if SDRAM_TARGET_BANK == 1
hsdram1
.
Init
.
SDBank
=
FMC_SDRAM_BANK1
;
#else
hsdram1
.
Init
.
SDBank
=
FMC_SDRAM_BANK2
;
#endif
#if SDRAM_COLUMN_BITS == 8
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_8
;
#elif SDRAM_COLUMN_BITS == 9
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_9
;
#elif SDRAM_COLUMN_BITS == 10
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_10
;
#else
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_11
;
#endif
#if SDRAM_ROW_BITS == 11
hsdram1
.
Init
.
RowBitsNumber
=
FMC_SDRAM_ROW_BITS_NUM_11
;
#elif SDRAM_ROW_BITS == 12
hsdram1
.
Init
.
RowBitsNumber
=
FMC_SDRAM_ROW_BITS_NUM_12
;
#else
hsdram1
.
Init
.
RowBitsNumber
=
FMC_SDRAM_ROW_BITS_NUM_13
;
#endif
#if SDRAM_DATA_WIDTH == 8
hsdram1
.
Init
.
MemoryDataWidth
=
FMC_SDRAM_MEM_BUS_WIDTH_8
;
#elif SDRAM_DATA_WIDTH == 16
hsdram1
.
Init
.
MemoryDataWidth
=
FMC_SDRAM_MEM_BUS_WIDTH_16
;
#else
hsdram1
.
Init
.
MemoryDataWidth
=
FMC_SDRAM_MEM_BUS_WIDTH_32
;
#endif
hsdram1
.
Init
.
InternalBankNumber
=
FMC_SDRAM_INTERN_BANKS_NUM_4
;
#if SDRAM_CAS_LATENCY == 1
hsdram1
.
Init
.
CASLatency
=
FMC_SDRAM_CAS_LATENCY_1
;
#elif SDRAM_CAS_LATENCY == 2
hsdram1
.
Init
.
CASLatency
=
FMC_SDRAM_CAS_LATENCY_2
;
#else
hsdram1
.
Init
.
CASLatency
=
FMC_SDRAM_CAS_LATENCY_3
;
#endif
hsdram1
.
Init
.
WriteProtection
=
FMC_SDRAM_WRITE_PROTECTION_DISABLE
;
#if SDCLOCK_PERIOD == 2
hsdram1
.
Init
.
SDClockPeriod
=
FMC_SDRAM_CLOCK_PERIOD_2
;
#else
hsdram1
.
Init
.
SDClockPeriod
=
FMC_SDRAM_CLOCK_PERIOD_3
;
#endif
hsdram1
.
Init
.
ReadBurst
=
FMC_SDRAM_RBURST_ENABLE
;
#if SDRAM_RPIPE_DELAY == 0
hsdram1
.
Init
.
ReadPipeDelay
=
FMC_SDRAM_RPIPE_DELAY_0
;
#elif SDRAM_RPIPE_DELAY == 1
hsdram1
.
Init
.
ReadPipeDelay
=
FMC_SDRAM_RPIPE_DELAY_1
;
#else
hsdram1
.
Init
.
ReadPipeDelay
=
FMC_SDRAM_RPIPE_DELAY_2
;
#endif
/* Initialize the SDRAM controller */
if
(
HAL_SDRAM_Init
(
&
hsdram1
,
&
SDRAM_Timing
)
!=
HAL_OK
)
{
LOG_E
(
"SDRAM init failed!"
);
result
=
-
RT_ERROR
;
}
else
{
/* Program the SDRAM external device */
SDRAM_Initialization_Sequence
(
&
hsdram1
,
&
command
);
LOG_D
(
"sdram init success, mapped at 0x%X, size is %d bytes, data width is %d"
,
SDRAM_BANK_ADDR
,
SDRAM_SIZE
,
SDRAM_DATA_WIDTH
);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
rt_memheap_init
(
&
system_heap
,
"sdram"
,
(
void
*
)
SDRAM_BANK_ADDR
,
SDRAM_SIZE
);
#endif
}
return
result
;
}
INIT_BOARD_EXPORT
(
SDRAM_Init
);
#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
int
sdram_test
(
void
)
{
int
i
=
0
;
uint32_t
start_time
=
0
,
time_cast
=
0
;
#if SDRAM_DATA_WIDTH == 8
char
data_width
=
1
;
uint8_t
data
=
0
;
#elif SDRAM_DATA_WIDTH == 16
char
data_width
=
2
;
uint16_t
data
=
0
;
#else
char
data_width
=
4
;
uint32_t
data
=
0
;
#endif
/* write data */
LOG_D
(
"Writing the %ld bytes data, waiting...."
,
SDRAM_SIZE
);
start_time
=
rt_tick_get
();
for
(
i
=
0
;
i
<
SDRAM_SIZE
/
data_width
;
i
++
)
{
#if SDRAM_DATA_WIDTH == 8
*
(
__IO
uint8_t
*
)(
SDRAM_BANK_ADDR
+
i
*
data_width
)
=
(
uint8_t
)
0x55
;
#elif SDRAM_DATA_WIDTH == 16
*
(
__IO
uint16_t
*
)(
SDRAM_BANK_ADDR
+
i
*
data_width
)
=
(
uint16_t
)
0x5555
;
#else
*
(
__IO
uint32_t
*
)(
SDRAM_BANK_ADDR
+
i
*
data_width
)
=
(
uint32_t
)
0x55555555
;
#endif
}
time_cast
=
rt_tick_get
()
-
start_time
;
LOG_D
(
"Write data success, total time: %d.%03dS."
,
time_cast
/
RT_TICK_PER_SECOND
,
time_cast
%
RT_TICK_PER_SECOND
/
((
RT_TICK_PER_SECOND
*
1
+
999
)
/
1000
));
/* read data */
LOG_D
(
"start Reading and verifying data, waiting...."
);
for
(
i
=
0
;
i
<
SDRAM_SIZE
/
data_width
;
i
++
)
{
#if SDRAM_DATA_WIDTH == 8
data
=
*
(
__IO
uint8_t
*
)(
SDRAM_BANK_ADDR
+
i
*
data_width
);
if
(
data
!=
0x55
)
{
LOG_E
(
"SDRAM test failed!"
);
break
;
}
#elif SDRAM_DATA_WIDTH == 16
data
=
*
(
__IO
uint16_t
*
)(
SDRAM_BANK_ADDR
+
i
*
data_width
);
if
(
data
!=
0x5555
)
{
LOG_E
(
"SDRAM test failed!"
);
break
;
}
#else
data
=
*
(
__IO
uint32_t
*
)(
SDRAM_BANK_ADDR
+
i
*
data_width
);
if
(
data
!=
0x55555555
)
{
LOG_E
(
"SDRAM test failed!"
);
break
;
}
#endif
}
if
(
i
>=
SDRAM_SIZE
/
data_width
)
{
LOG_D
(
"SDRAM test success!"
);
}
return
RT_EOK
;
}
MSH_CMD_EXPORT
(
sdram_test
,
sdram
test
)
#endif
/* FINSH_USING_MSH */
#endif
/* DRV_DEBUG */
#endif
/* BSP_USING_SDRAM */
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
浏览文件 @
92338d50
...
...
@@ -124,7 +124,7 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
{
return
-
RT_ERROR
;
}
__HAL_UART_CLEAR_FLAG
(
&
(
uart
->
handle
),
UART_FLAG_TC
);
return
RT_EOK
;
}
...
...
@@ -174,6 +174,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
RT_ASSERT
(
serial
!=
RT_NULL
);
uart
=
(
struct
stm32_uart
*
)
serial
->
parent
.
user_data
;
__HAL_UART_CLEAR_FLAG
(
&
(
uart
->
handle
),
UART_FLAG_TC
);
#if defined(SOC_SERIES_STM32L4)
uart
->
handle
.
Instance
->
TDR
=
c
;
#else
...
...
bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-07 balanceTWK first version
*/
#include <board.h>
#ifdef RT_USING_WDT
//#define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <drv_log.h>
static
IWDG_HandleTypeDef
hiwdg
;
static
struct
rt_watchdog_ops
ops
;
static
rt_watchdog_t
watchdog
;
static
rt_err_t
wdt_init
(
rt_watchdog_t
*
wdt
)
{
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_32
;
hiwdg
.
Init
.
Reload
=
0x00000FFE
;
#if defined(SOC_SERIES_STM32L4)
hiwdg
.
Init
.
Window
=
0x00000FFF
;
#endif
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
LOG_E
(
"wdt init failed."
);
return
-
RT_ERROR
;
}
return
RT_EOK
;
}
static
rt_err_t
wdt_control
(
rt_watchdog_t
*
wdt
,
int
cmd
,
void
*
arg
)
{
switch
(
cmd
)
{
/* feed the watchdog */
case
RT_DEVICE_CTRL_WDT_KEEPALIVE
:
HAL_IWDG_Refresh
(
&
hiwdg
);
break
;
/* set watchdog timeout */
case
RT_DEVICE_CTRL_WDT_SET_TIMEOUT
:
hiwdg
.
Init
.
Reload
=
(
rt_uint32_t
)
arg
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
LOG_E
(
"wdg set timeout failed."
);
return
-
RT_ERROR
;
}
break
;
default:
return
-
RT_ERROR
;
}
return
RT_EOK
;
}
int
rt_wdt_init
(
void
)
{
ops
.
init
=
&
wdt_init
;
ops
.
control
=
&
wdt_control
;
watchdog
.
ops
=
&
ops
;
/* register watchdog device */
if
(
rt_hw_watchdog_register
(
&
watchdog
,
"wdt"
,
RT_DEVICE_FLAG_DEACTIVATE
,
RT_NULL
)
!=
RT_EOK
)
{
LOG_E
(
"wdt device register failed."
);
return
-
RT_ERROR
;
}
LOG_D
(
"wdt device register success."
);
return
RT_EOK
;
}
INIT_BOARD_EXPORT
(
rt_wdt_init
);
#endif
/* RT_USING_WDT */
bsp/stm32/stm32f103-atk-nano/README.md
浏览文件 @
92338d50
...
...
@@ -40,11 +40,16 @@ ATK-NANO STM32F103 是正点原子推出的一款基于 ARM Cortex-M3 内核的
| :----------------- | :----------: | :------------------------------------- |
| USB 转串口 | 支持 | 使用 UART1 |
| SPI Flash | 支持 | 使用 SPI1 |
| 电位器 | 支持 | 使用 ADC1 |
|
**片上外设**
|
**支持情况**
|
**备注**
|
| GPIO | 支持 | PA0, PA1...PD2 ---> PIN: 0, 1...63 |
| UART | 支持 | UART1/2/3 |
| SPI | 支持 | SPI1/2 |
| I2C | 支持 | 软件 I2C |
| RTC | 支持 | |
| WDT | 支持 | |
| ADC | 支持 | |
| FLASH | 支持 | 已适配
[
FAL
](
https://github.com/RT-Thread-packages/fal
)
|
|
**扩展模块**
|
**支持情况**
|
**备注**
|
| DS18B20/DHT11 | 暂不支持 | |
...
...
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/.mxproject
浏览文件 @
92338d50
[PreviousGenFiles]
HeaderPath=
E:/workspace
/BspFramework/rt-thread/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc
HeaderPath=
D:
/BspFramework/rt-thread/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc
HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h;
SourcePath=
E:/workspace
/BspFramework/rt-thread/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src
SourcePath=
D:
/BspFramework/rt-thread/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src
SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_
spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_
adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h
;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedKeilFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_
spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config//MDK-ARM/startup_stm32f103xb.s
;
SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_
adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null
;
HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc;
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
浏览文件 @
92338d50
...
...
@@ -49,7 +49,7 @@
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
...
...
@@ -63,7 +63,7 @@
/*#define HAL_I2C_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_PCCARD_MODULE_ENABLED */
...
...
@@ -71,7 +71,7 @@
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_PWR_MODULE_ENABLED */
/*#define HAL_RCC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_SDRAM_MODULE_ENABLED */
...
...
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c
浏览文件 @
92338d50
...
...
@@ -62,6 +62,12 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef
hadc1
;
IWDG_HandleTypeDef
hiwdg
;
RTC_HandleTypeDef
hrtc
;
SPI_HandleTypeDef
hspi2
;
UART_HandleTypeDef
huart1
;
...
...
@@ -76,6 +82,9 @@ void SystemClock_Config(void);
static
void
MX_GPIO_Init
(
void
);
static
void
MX_USART1_UART_Init
(
void
);
static
void
MX_SPI2_Init
(
void
);
static
void
MX_RTC_Init
(
void
);
static
void
MX_IWDG_Init
(
void
);
static
void
MX_ADC1_Init
(
void
);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
...
...
@@ -116,6 +125,9 @@ int main(void)
MX_GPIO_Init
();
MX_USART1_UART_Init
();
MX_SPI2_Init
();
MX_RTC_Init
();
MX_IWDG_Init
();
MX_ADC1_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
...
...
@@ -141,13 +153,17 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInit
=
{
0
};
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_LSI
|
RCC_OSCILLATORTYPE_HSE
|
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
HSEPredivValue
=
RCC_HSE_PREDIV_DIV1
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
RCC_OscInitStruct
.
HSIState
=
RCC_HSI_ON
;
RCC_OscInitStruct
.
LSIState
=
RCC_LSI_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLMUL
=
RCC_PLL_MUL9
;
...
...
@@ -168,6 +184,116 @@ void SystemClock_Config(void)
{
Error_Handler
();
}
PeriphClkInit
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
|
RCC_PERIPHCLK_ADC
;
PeriphClkInit
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
PeriphClkInit
.
AdcClockSelection
=
RCC_ADCPCLK2_DIV2
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInit
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_ADC1_Init
(
void
)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef
sConfig
=
{
0
};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/**Common config
*/
hadc1
.
Instance
=
ADC1
;
hadc1
.
Init
.
ScanConvMode
=
ADC_SCAN_DISABLE
;
hadc1
.
Init
.
ContinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
DiscontinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
ExternalTrigConv
=
ADC_SOFTWARE_START
;
hadc1
.
Init
.
DataAlign
=
ADC_DATAALIGN_RIGHT
;
hadc1
.
Init
.
NbrOfConversion
=
1
;
if
(
HAL_ADC_Init
(
&
hadc1
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure Regular Channel
*/
sConfig
.
Channel
=
ADC_CHANNEL_9
;
sConfig
.
Rank
=
ADC_REGULAR_RANK_1
;
sConfig
.
SamplingTime
=
ADC_SAMPLETIME_1CYCLE_5
;
if
(
HAL_ADC_ConfigChannel
(
&
hadc1
,
&
sConfig
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static
void
MX_IWDG_Init
(
void
)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_4
;
hiwdg
.
Init
.
Reload
=
4095
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static
void
MX_RTC_Init
(
void
)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/**Initialize RTC Only
*/
hrtc
.
Instance
=
RTC
;
hrtc
.
Init
.
AsynchPrediv
=
RTC_AUTO_1_SECOND
;
hrtc
.
Init
.
OutPut
=
RTC_OUTPUTSOURCE_ALARM
;
if
(
HAL_RTC_Init
(
&
hrtc
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
...
...
@@ -250,6 +376,7 @@ static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOD_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
...
...
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
浏览文件 @
92338d50
...
...
@@ -101,6 +101,119 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspInit
(
ADC_HandleTypeDef
*
hadc
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
/**ADC1 GPIO Configuration
PB1 ------> ADC1_IN9
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_1
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_ANALOG
;
HAL_GPIO_Init
(
GPIOB
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspDeInit
(
ADC_HandleTypeDef
*
hadc
)
{
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE
();
/**ADC1 GPIO Configuration
PB1 ------> ADC1_IN9
*/
HAL_GPIO_DeInit
(
GPIOB
,
GPIO_PIN_1
);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief RTC MSP Initialization
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
HAL_PWR_EnableBkUpAccess
();
/* Enable BKP CLK enable for backup registers */
__HAL_RCC_BKP_CLK_ENABLE
();
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE
();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
/**
* @brief RTC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspDeInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE
();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
...
...
bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc
浏览文件 @
92338d50
#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_9
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
ADC1.master=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F1
Mcu.IP0=NVIC
Mcu.IP1=RCC
Mcu.IP2=SPI2
Mcu.IP3=SYS
Mcu.IP4=USART1
Mcu.IPNb=5
Mcu.IP0=ADC1
Mcu.IP1=IWDG
Mcu.IP2=NVIC
Mcu.IP3=RCC
Mcu.IP4=RTC
Mcu.IP5=SPI2
Mcu.IP6=SYS
Mcu.IP7=USART1
Mcu.IPNb=8
Mcu.Name=STM32F103R(8-B)Tx
Mcu.Package=LQFP64
Mcu.Pin0=PD0-OSC_IN
Mcu.Pin1=PD1-OSC_OUT
Mcu.Pin2=PB13
Mcu.Pin3=PB14
Mcu.Pin4=PB15
Mcu.Pin5=PA9
Mcu.Pin6=PA10
Mcu.Pin7=PA13
Mcu.Pin8=PA14
Mcu.Pin9=VP_SYS_VS_Systick
Mcu.PinsNb=10
Mcu.Pin0=PC14-OSC32_IN
Mcu.Pin1=PC15-OSC32_OUT
Mcu.Pin10=PA13
Mcu.Pin11=PA14
Mcu.Pin12=VP_IWDG_VS_IWDG
Mcu.Pin13=VP_RTC_VS_RTC_Activate
Mcu.Pin14=VP_SYS_VS_Systick
Mcu.Pin2=PD0-OSC_IN
Mcu.Pin3=PD1-OSC_OUT
Mcu.Pin4=PB1
Mcu.Pin5=PB13
Mcu.Pin6=PB14
Mcu.Pin7=PB15
Mcu.Pin8=PA9
Mcu.Pin9=PA10
Mcu.PinsNb=15
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F103RBTx
...
...
@@ -45,12 +59,17 @@ PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB1.Signal=ADCx_IN9
PB13.Mode=Full_Duplex_Master
PB13.Signal=SPI2_SCK
PB14.Mode=Full_Duplex_Master
PB14.Signal=SPI2_MISO
PB15.Mode=Full_Duplex_Master
PB15.Signal=SPI2_MOSI
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PCC.Checker=false
PCC.Line=STM32F103
PCC.MCU=STM32F103R(8-B)Tx
...
...
@@ -90,7 +109,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true
,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true
RCC.ADCFreqValue=36000000
RCC.AHBFreq_Value=72000000
RCC.APB1CLKDivider=RCC_HCLK_DIV2
...
...
@@ -101,17 +120,21 @@ RCC.APB2TimFreq_Value=72000000
RCC.FCLKCortexFreq_Value=72000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=72000000
RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,
RTCClockSelection,RTCFreq_Value,
SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
RCC.MCOFreq_Value=72000000
RCC.PLLCLKFreq_Value=72000000
RCC.PLLMCOFreq_Value=36000000
RCC.PLLMUL=RCC_PLL_MUL9
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.SYSCLKFreq_VALUE=72000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.TimSysFreq_Value=72000000
RCC.USBFreq_Value=72000000
RCC.VCOOutput2Freq_Value=8000000
SH.ADCx_IN9.0=ADC1_IN9,IN9
SH.ADCx_IN9.ConfNb=1
SPI2.CalculateBaudRate=18.0 MBits/s
SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
...
...
@@ -119,6 +142,10 @@ SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualType=VM_MASTER
USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32f103-atk-nano/board/Kconfig
浏览文件 @
92338d50
...
...
@@ -24,6 +24,12 @@ menu "Onboard Peripheral Drivers"
select RT_SFUD_USING_SFDP
default n
config BSP_USING_POT
bool "Enable potentiometer"
select BSP_USING_ADC
select BSP_USING_ADC1
default n
endmenu
menu "On-chip Peripheral Drivers"
...
...
@@ -83,6 +89,36 @@ menu "On-chip Peripheral Drivers"
default 23
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f103-atk-nano/board/SConscript
浏览文件 @
92338d50
...
...
@@ -11,6 +11,7 @@ if GetDepend(['BSP_USING_SPI_FLASH']):
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
path
+=
[
cwd
+
'/ports'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
cwd
+
'/../../libraries/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xb.s'
]
...
...
bsp/stm32/stm32f103-atk-nano/board/board.h
浏览文件 @
92338d50
...
...
@@ -22,6 +22,10 @@
#define LED1_PIN GET_PIN(C, 1)
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (128 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
#define STM32_SRAM_SIZE 20
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
...
...
bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-8 zylx first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern
const
struct
fal_flash_dev
stm32_onchip_flash
;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 112 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 112* 1024 , 16 * 1024, 0}, \
}
#endif
/* FAL_PART_HAS_TABLE_CFG */
#endif
/* _FAL_CFG_H_ */
bsp/stm32/stm32f103-fire-arbitrary/README.md
浏览文件 @
92338d50
...
...
@@ -43,6 +43,7 @@
| RS232 | 支持 | 使用 UART2 |
| SPI Flash | 支持 | W25Q64 |
| 以太网 | 支持 | W5500 |
| 电位器 | 支持 | 使用 ADC1 |
| SD卡 | 即将支持 | |
| CAN | 即将支持 | |
| SDRAM | 即将支持 | |
...
...
@@ -52,12 +53,14 @@
| UART | 支持 | UART1/2/3 |
| SPI | 支持 | SPI1/2/3 |
| I2C | 支持 | 软件 I2C |
| ADC | 支持 | |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 支持 | 已适配
[
FAL
](
https://github.com/RT-Thread-packages/fal
)
|
| SDIO | 暂不支持 | 即将支持 |
| RTC | 暂不支持 | 即将支持 |
| PWM | 暂不支持 | 即将支持 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
| IWG | 暂不支持 | 即将支持 |
|
**扩展模块**
|
**支持情况**
|
**备注**
|
| 暂无 | 暂不支持 | 暂不支持 |
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject
浏览文件 @
92338d50
...
...
@@ -5,9 +5,9 @@ SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrar
SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_
spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_
adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h
;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedKeilFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_
spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio
_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;
SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_
adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc
_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;
HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc;
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
浏览文件 @
92338d50
...
...
@@ -49,7 +49,7 @@
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
...
...
@@ -63,7 +63,7 @@
/*#define HAL_I2C_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_PCCARD_MODULE_ENABLED */
...
...
@@ -71,7 +71,7 @@
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_PWR_MODULE_ENABLED */
/*#define HAL_RCC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_SDRAM_MODULE_ENABLED */
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c
浏览文件 @
92338d50
...
...
@@ -62,6 +62,12 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef
hadc1
;
IWDG_HandleTypeDef
hiwdg
;
RTC_HandleTypeDef
hrtc
;
SPI_HandleTypeDef
hspi1
;
SPI_HandleTypeDef
hspi2
;
...
...
@@ -82,6 +88,9 @@ static void MX_SPI2_Init(void);
static
void
MX_USART2_UART_Init
(
void
);
static
void
MX_SPI1_Init
(
void
);
static
void
MX_USART3_UART_Init
(
void
);
static
void
MX_ADC1_Init
(
void
);
static
void
MX_RTC_Init
(
void
);
static
void
MX_IWDG_Init
(
void
);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
...
...
@@ -125,6 +134,9 @@ int main(void)
MX_USART2_UART_Init
();
MX_SPI1_Init
();
MX_USART3_UART_Init
();
MX_ADC1_Init
();
MX_RTC_Init
();
MX_IWDG_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
...
...
@@ -150,13 +162,17 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInit
=
{
0
};
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_BYPASS
;
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_LSI
|
RCC_OSCILLATORTYPE_HSE
|
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
HSEPredivValue
=
RCC_HSE_PREDIV_DIV1
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
RCC_OscInitStruct
.
HSIState
=
RCC_HSI_ON
;
RCC_OscInitStruct
.
LSIState
=
RCC_LSI_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLMUL
=
RCC_PLL_MUL9
;
...
...
@@ -177,6 +193,116 @@ void SystemClock_Config(void)
{
Error_Handler
();
}
PeriphClkInit
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
|
RCC_PERIPHCLK_ADC
;
PeriphClkInit
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
PeriphClkInit
.
AdcClockSelection
=
RCC_ADCPCLK2_DIV6
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInit
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_ADC1_Init
(
void
)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef
sConfig
=
{
0
};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/**Common config
*/
hadc1
.
Instance
=
ADC1
;
hadc1
.
Init
.
ScanConvMode
=
ADC_SCAN_DISABLE
;
hadc1
.
Init
.
ContinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
DiscontinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
ExternalTrigConv
=
ADC_SOFTWARE_START
;
hadc1
.
Init
.
DataAlign
=
ADC_DATAALIGN_RIGHT
;
hadc1
.
Init
.
NbrOfConversion
=
1
;
if
(
HAL_ADC_Init
(
&
hadc1
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure Regular Channel
*/
sConfig
.
Channel
=
ADC_CHANNEL_11
;
sConfig
.
Rank
=
ADC_REGULAR_RANK_1
;
sConfig
.
SamplingTime
=
ADC_SAMPLETIME_1CYCLE_5
;
if
(
HAL_ADC_ConfigChannel
(
&
hadc1
,
&
sConfig
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static
void
MX_IWDG_Init
(
void
)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_4
;
hiwdg
.
Init
.
Reload
=
4095
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static
void
MX_RTC_Init
(
void
)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/**Initialize RTC Only
*/
hrtc
.
Instance
=
RTC
;
hrtc
.
Init
.
AsynchPrediv
=
RTC_AUTO_1_SECOND
;
hrtc
.
Init
.
OutPut
=
RTC_OUTPUTSOURCE_ALARM
;
if
(
HAL_RTC_Init
(
&
hrtc
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
浏览文件 @
92338d50
...
...
@@ -101,6 +101,119 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspInit
(
ADC_HandleTypeDef
*
hadc
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE
();
__HAL_RCC_GPIOC_CLK_ENABLE
();
/**ADC1 GPIO Configuration
PC1 ------> ADC1_IN11
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_1
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_ANALOG
;
HAL_GPIO_Init
(
GPIOC
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspDeInit
(
ADC_HandleTypeDef
*
hadc
)
{
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE
();
/**ADC1 GPIO Configuration
PC1 ------> ADC1_IN11
*/
HAL_GPIO_DeInit
(
GPIOC
,
GPIO_PIN_1
);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief RTC MSP Initialization
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
HAL_PWR_EnableBkUpAccess
();
/* Enable BKP CLK enable for backup registers */
__HAL_RCC_BKP_CLK_ENABLE
();
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE
();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
/**
* @brief RTC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspDeInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE
();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc
浏览文件 @
92338d50
#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_11
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
ADC1.master=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F1
Mcu.IP0=NVIC
Mcu.IP1=RCC
Mcu.IP2=SPI1
Mcu.IP3=SPI2
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IP6=USART2
Mcu.IP7=USART3
Mcu.IPNb=8
Mcu.IP0=ADC1
Mcu.IP1=IWDG
Mcu.IP10=USART3
Mcu.IP2=NVIC
Mcu.IP3=RCC
Mcu.IP4=RTC
Mcu.IP5=SPI1
Mcu.IP6=SPI2
Mcu.IP7=SYS
Mcu.IP8=USART1
Mcu.IP9=USART2
Mcu.IPNb=11
Mcu.Name=STM32F103Z(C-D-E)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PC14-OSC32_IN
Mcu.Pin1=PC15-OSC32_OUT
Mcu.Pin10=PB11
Mcu.Pin11=PB13
Mcu.Pin12=PB14
Mcu.Pin13=PB15
Mcu.Pin14=PA9
Mcu.Pin15=PA10
Mcu.Pin16=PA13
Mcu.Pin17=PA14
Mcu.Pin18=VP_SYS_VS_Systick
Mcu.Pin10=PB10
Mcu.Pin11=PB11
Mcu.Pin12=PB13
Mcu.Pin13=PB14
Mcu.Pin14=PB15
Mcu.Pin15=PA9
Mcu.Pin16=PA10
Mcu.Pin17=PA13
Mcu.Pin18=PA14
Mcu.Pin19=VP_IWDG_VS_IWDG
Mcu.Pin2=OSC_IN
Mcu.Pin20=VP_RTC_VS_RTC_Activate
Mcu.Pin21=VP_SYS_VS_Systick
Mcu.Pin3=OSC_OUT
Mcu.Pin4=P
A2
Mcu.Pin5=PA
3
Mcu.Pin6=PA
5
Mcu.Pin7=PA
6
Mcu.Pin8=PA
7
Mcu.Pin9=P
B10
Mcu.PinsNb=
19
Mcu.Pin4=P
C1
Mcu.Pin5=PA
2
Mcu.Pin6=PA
3
Mcu.Pin7=PA
5
Mcu.Pin8=PA
6
Mcu.Pin9=P
A7
Mcu.PinsNb=
22
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F103ZETx
...
...
@@ -49,9 +61,9 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
OSC_IN.Mode=HSE-External-
Clock-Source
OSC_IN.Mode=HSE-External-
Oscillator
OSC_IN.Signal=RCC_OSC_IN
OSC_OUT.Mode=HSE-External-
Clock-Source
OSC_OUT.Mode=HSE-External-
Oscillator
OSC_OUT.Signal=RCC_OSC_OUT
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
...
...
@@ -81,9 +93,11 @@ PB14.Mode=Full_Duplex_Master
PB14.Signal=SPI2_MISO
PB15.Mode=Full_Duplex_Master
PB15.Signal=SPI2_MOSI
PC14-OSC32_IN.Mode=LSE-External-Clock-Source
PC1.Locked=true
PC1.Signal=ADCx_IN11
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-
Clock-Source
PC15-OSC32_OUT.Mode=LSE-External-
Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PCC.Checker=false
PCC.Line=STM32F103
...
...
@@ -120,8 +134,9 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true
RCC.ADCFreqValue=36000000
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true
RCC.ADCFreqValue=12000000
RCC.ADCPresc=RCC_ADCPCLK2_DIV6
RCC.AHBFreq_Value=72000000
RCC.APB1CLKDivider=RCC_HCLK_DIV2
RCC.APB1Freq_Value=36000000
...
...
@@ -134,12 +149,14 @@ RCC.FamilyName=M
RCC.HCLKFreq_Value=72000000
RCC.I2S2Freq_Value=72000000
RCC.I2S3Freq_Value=72000000
RCC.IPParameters=ADCFreqValue,A
HBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual
,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
RCC.IPParameters=ADCFreqValue,A
DCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value
,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
RCC.MCOFreq_Value=72000000
RCC.PLLCLKFreq_Value=72000000
RCC.PLLMCOFreq_Value=36000000
RCC.PLLMUL=RCC_PLL_MUL9
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.SDIOFreq_Value=72000000
RCC.SDIOHCLKDiv2FreqValue=36000000
RCC.SYSCLKFreq_VALUE=72000000
...
...
@@ -147,6 +164,8 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.TimSysFreq_Value=72000000
RCC.USBFreq_Value=72000000
RCC.VCOOutput2Freq_Value=8000000
SH.ADCx_IN11.0=ADC1_IN11,IN11
SH.ADCx_IN11.ConfNb=1
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
SPI1.CalculateBaudRate=18.0 MBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
...
...
@@ -164,6 +183,10 @@ USART2.IPParameters=VirtualMode
USART2.VirtualMode=VM_ASYNC
USART3.IPParameters=VirtualMode
USART3.VirtualMode=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig
浏览文件 @
92338d50
...
...
@@ -24,6 +24,12 @@ menu "Onboard Peripheral Drivers"
select RT_SFUD_USING_SFDP
default n
config BSP_USING_POT
bool "Enable potentiometer"
select BSP_USING_ADC
select BSP_USING_ADC1
default n
config BSP_USING_EEPROM
bool "Enable I2C EEPROM (i2c1)"
select BSP_USING_I2C1
...
...
@@ -85,6 +91,10 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART RX DMA support"
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
select RT_USING_SPI
...
...
@@ -121,6 +131,35 @@ menu "On-chip Peripheral Drivers"
default 23
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
config BSP_USING_ADC3
bool "Enable ADC3"
default n
endif
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/SConscript
浏览文件 @
92338d50
...
...
@@ -12,8 +12,9 @@ if GetDepend(['BSP_USING_ETH']):
if
GetDepend
([
'BSP_USING_SPI_FLASH'
]):
src
+=
Glob
(
'ports/spi_flash_init.c'
)
path
=
[
cwd
]
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
path
+=
[
cwd
+
'/ports'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
cwd
+
'/../../libraries/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s'
]
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/board.h
浏览文件 @
92338d50
...
...
@@ -26,6 +26,10 @@
#define STM32_SRAM_SIZE 64
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (512 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#ifdef __CC_ARM
extern
int
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
...
...
bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern
const
struct
fal_flash_dev
stm32_onchip_flash
;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 496 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 496* 1024 , 16 * 1024, 0}, \
}
#endif
/* FAL_PART_HAS_TABLE_CFG */
#endif
/* _FAL_CFG_H_ */
bsp/stm32/stm32f407-atk-explorer/README.md
浏览文件 @
92338d50
...
...
@@ -49,11 +49,13 @@
| UART | 支持 | UART1/2/3/6 |
| SPI | 支持 | SPI1/2/3 |
| I2C | 支持 | 软件 I2C |
| RTC | 暂不支持 | 即将支持 |
| ADC | 支持 | |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 支持 | 已适配
[
FAL
](
https://github.com/RT-Thread-packages/fal
)
|
| PWM | 暂不支持 | 即将支持 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
| IWG | 暂不支持 | 即将支持 |
|
**扩展模块**
|
**支持情况**
|
**备注**
|
| ATK-ESP8266 模块 | 暂不支持 | 即将支持 |
...
...
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject
浏览文件 @
92338d50
...
...
@@ -5,9 +5,9 @@ SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f407-atk-explorer/
SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_
eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth
.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_
adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex
.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedKeilFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_
eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config//MDK-ARM/startup_stm32f407xx.s
;
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_
adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null
;
HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc
浏览文件 @
92338d50
#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC1.master=1
ETH.IPParameters=MediaInterface
ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=ETH
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=SPI1
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IP6=USART3
Mcu.IPNb=7
Mcu.IP0=ADC1
Mcu.IP1=ETH
Mcu.IP2=IWDG
Mcu.IP3=NVIC
Mcu.IP4=RCC
Mcu.IP5=RTC
Mcu.IP6=SPI1
Mcu.IP7=SYS
Mcu.IP8=USART1
Mcu.IP9=USART3
Mcu.IPNb=10
Mcu.Name=STM32F407Z(E-G)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PC14-OSC32_IN
Mcu.Pin1=PC15-OSC32_OUT
Mcu.Pin10=P
B10
Mcu.Pin11=PB1
1
Mcu.Pin12=P
A9
Mcu.Pin13=PA
10
Mcu.Pin14=PA1
3
Mcu.Pin15=PA1
4
Mcu.Pin16=P
G11
Mcu.Pin17=PG1
3
Mcu.Pin18=PG1
4
Mcu.Pin19=P
B3
Mcu.Pin10=P
C5
Mcu.Pin11=PB1
0
Mcu.Pin12=P
B11
Mcu.Pin13=PA
9
Mcu.Pin14=PA1
0
Mcu.Pin15=PA1
3
Mcu.Pin16=P
A14
Mcu.Pin17=PG1
1
Mcu.Pin18=PG1
3
Mcu.Pin19=P
G14
Mcu.Pin2=PH0-OSC_IN
Mcu.Pin20=PB4
Mcu.Pin21=PB5
Mcu.Pin22=VP_SYS_VS_Systick
Mcu.Pin20=PB3
Mcu.Pin21=PB4
Mcu.Pin22=PB5
Mcu.Pin23=VP_IWDG_VS_IWDG
Mcu.Pin24=VP_RTC_VS_RTC_Activate
Mcu.Pin25=VP_SYS_VS_Systick
Mcu.Pin3=PH1-OSC_OUT
Mcu.Pin4=PC1
Mcu.Pin5=PA1
Mcu.Pin6=PA2
Mcu.Pin7=PA
7
Mcu.Pin8=P
C4
Mcu.Pin9=PC
5
Mcu.PinsNb=2
3
Mcu.Pin7=PA
5
Mcu.Pin8=P
A7
Mcu.Pin9=PC
4
Mcu.PinsNb=2
6
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F407ZGTx
...
...
@@ -65,6 +77,8 @@ PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA2.Mode=RMII
PA2.Signal=ETH_MDIO
PA5.Locked=true
PA5.Signal=ADCx_IN5
PA7.Mode=RMII
PA7.Signal=ETH_CRS_DV
PA9.Mode=Asynchronous
...
...
@@ -128,7 +142,7 @@ ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=
tru
e
ProjectManager.LastFirmware=
fals
e
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
...
...
@@ -140,7 +154,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true
,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true
RCC.48MHZClocksFreq_Value=84000000
RCC.AHBFreq_Value=168000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
...
...
@@ -157,7 +171,7 @@ RCC.HCLKFreq_Value=168000000
RCC.HSE_VALUE=8000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=192000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,R
CC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,R
TCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=168000000
RCC.PLLCLKFreq_Value=168000000
...
...
@@ -165,7 +179,9 @@ RCC.PLLM=4
RCC.PLLN=168
RCC.PLLQCLKFreq_Value=84000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCFreq_Value=32000
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=4000000
RCC.SYSCLKFreq_VALUE=168000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
...
...
@@ -173,6 +189,8 @@ RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=336000000
RCC.VcooutputI2S=192000000
SH.ADCx_IN5.0=ADC1_IN5,IN5
SH.ADCx_IN5.ConfNb=1
SPI1.CalculateBaudRate=42.0 MBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
...
...
@@ -182,6 +200,10 @@ USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
USART3.IPParameters=VirtualMode
USART3.VirtualMode=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
浏览文件 @
92338d50
...
...
@@ -49,7 +49,7 @@
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
...
...
@@ -66,10 +66,10 @@
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
...
...
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c
浏览文件 @
92338d50
...
...
@@ -62,8 +62,14 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef
hadc1
;
ETH_HandleTypeDef
heth
;
IWDG_HandleTypeDef
hiwdg
;
RTC_HandleTypeDef
hrtc
;
SPI_HandleTypeDef
hspi1
;
UART_HandleTypeDef
huart1
;
...
...
@@ -81,6 +87,9 @@ static void MX_USART1_UART_Init(void);
static
void
MX_SPI1_Init
(
void
);
static
void
MX_ETH_Init
(
void
);
static
void
MX_USART3_UART_Init
(
void
);
static
void
MX_ADC1_Init
(
void
);
static
void
MX_RTC_Init
(
void
);
static
void
MX_IWDG_Init
(
void
);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
...
...
@@ -123,6 +132,9 @@ int main(void)
MX_SPI1_Init
();
MX_ETH_Init
();
MX_USART3_UART_Init
();
MX_ADC1_Init
();
MX_RTC_Init
();
MX_IWDG_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
...
...
@@ -148,6 +160,7 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
=
{
0
};
/**Configure the main internal regulator output voltage
*/
...
...
@@ -155,8 +168,11 @@ void SystemClock_Config(void)
__HAL_PWR_VOLTAGESCALING_CONFIG
(
PWR_REGULATOR_VOLTAGE_SCALE1
);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_LSI
|
RCC_OSCILLATORTYPE_HSE
|
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
RCC_OscInitStruct
.
LSIState
=
RCC_LSI_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
4
;
...
...
@@ -180,6 +196,62 @@ void SystemClock_Config(void)
{
Error_Handler
();
}
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_ADC1_Init
(
void
)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef
sConfig
=
{
0
};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/**Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1
.
Instance
=
ADC1
;
hadc1
.
Init
.
ClockPrescaler
=
ADC_CLOCK_SYNC_PCLK_DIV4
;
hadc1
.
Init
.
Resolution
=
ADC_RESOLUTION_12B
;
hadc1
.
Init
.
ScanConvMode
=
DISABLE
;
hadc1
.
Init
.
ContinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
DiscontinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
ExternalTrigConvEdge
=
ADC_EXTERNALTRIGCONVEDGE_NONE
;
hadc1
.
Init
.
ExternalTrigConv
=
ADC_SOFTWARE_START
;
hadc1
.
Init
.
DataAlign
=
ADC_DATAALIGN_RIGHT
;
hadc1
.
Init
.
NbrOfConversion
=
1
;
hadc1
.
Init
.
DMAContinuousRequests
=
DISABLE
;
hadc1
.
Init
.
EOCSelection
=
ADC_EOC_SINGLE_CONV
;
if
(
HAL_ADC_Init
(
&
hadc1
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig
.
Channel
=
ADC_CHANNEL_5
;
sConfig
.
Rank
=
1
;
sConfig
.
SamplingTime
=
ADC_SAMPLETIME_3CYCLES
;
if
(
HAL_ADC_ConfigChannel
(
&
hadc1
,
&
sConfig
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
...
...
@@ -227,6 +299,68 @@ static void MX_ETH_Init(void)
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static
void
MX_IWDG_Init
(
void
)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_4
;
hiwdg
.
Init
.
Reload
=
4095
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static
void
MX_RTC_Init
(
void
)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/**Initialize RTC Only
*/
hrtc
.
Instance
=
RTC
;
hrtc
.
Init
.
HourFormat
=
RTC_HOURFORMAT_24
;
hrtc
.
Init
.
AsynchPrediv
=
127
;
hrtc
.
Init
.
SynchPrediv
=
255
;
hrtc
.
Init
.
OutPut
=
RTC_OUTPUT_DISABLE
;
hrtc
.
Init
.
OutPutPolarity
=
RTC_OUTPUT_POLARITY_HIGH
;
hrtc
.
Init
.
OutPutType
=
RTC_OUTPUT_TYPE_OPENDRAIN
;
if
(
HAL_RTC_Init
(
&
hrtc
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
* @brief SPI1 Initialization Function
* @param None
...
...
bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
浏览文件 @
92338d50
...
...
@@ -97,6 +97,70 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspInit
(
ADC_HandleTypeDef
*
hadc
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
/**ADC1 GPIO Configuration
PA5 ------> ADC1_IN5
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_5
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_ANALOG
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
HAL_GPIO_Init
(
GPIOA
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspDeInit
(
ADC_HandleTypeDef
*
hadc
)
{
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE
();
/**ADC1 GPIO Configuration
PA5 ------> ADC1_IN5
*/
HAL_GPIO_DeInit
(
GPIOA
,
GPIO_PIN_5
);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief ETH MSP Initialization
* This function configures the hardware resources used in this example
...
...
@@ -199,6 +263,53 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
}
/**
* @brief RTC MSP Initialization
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE
();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
/**
* @brief RTC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspDeInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE
();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
...
...
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
浏览文件 @
92338d50
...
...
@@ -73,6 +73,10 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART6"
select RT_USING_SERIAL
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_UART_USING_DMA_RX
bool "Enable UART RX DMA support"
...
...
@@ -97,6 +101,24 @@ menu "On-chip Peripheral Drivers"
bool "Enable SPI DMA support"
default n
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
config BSP_USING_ADC3
bool "Enable ADC3"
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
...
...
@@ -114,6 +136,17 @@ menu "On-chip Peripheral Drivers"
default 25
endif
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f407-atk-explorer/board/SConscript
浏览文件 @
92338d50
...
...
@@ -13,8 +13,9 @@ if GetDepend(['BSP_USING_ETH']):
if
GetDepend
([
'BSP_USING_SPI_FLASH'
]):
src
+=
Glob
(
'ports/spi_flash_init.c'
)
path
=
[
cwd
]
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
path
+=
[
cwd
+
'/ports'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
cwd
+
'/../../libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'
]
...
...
bsp/stm32/stm32f407-atk-explorer/board/board.h
浏览文件 @
92338d50
...
...
@@ -22,8 +22,12 @@
#define LED1_PIN GET_PIN(F, 10)
#endif
#define STM32_SRAM_SIZE (128)
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_SRAM_SIZE (128)
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#ifdef __CC_ARM
extern
int
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
;
...
...
bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern
const
struct
fal_flash_dev
stm32_onchip_flash
;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 1008 * 1024, 0},\
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 1008* 1024 , 16 * 1024, 0}, \
}
#endif
/* FAL_PART_HAS_TABLE_CFG */
#endif
/* _FAL_CFG_H_ */
bsp/stm32/stm32f429-atk-apollo/.config
浏览文件 @
92338d50
...
...
@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX
=
8
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE
=
4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32
=
y
...
...
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND
=
1000
CONFIG_RT_USING_OVERFLOW_CHECK
=
y
CONFIG_RT_USING_HOOK
=
y
CONFIG_RT_USING_IDLE_HOOK
=
y
CONFIG_RT_IDEL_HOOK_LIST_SIZE
=
4
CONFIG_IDLE_THREAD_STACK_SIZE
=
1024
# CONFIG_RT_USING_TIMER_SOFT is not set
...
...
@@ -46,10 +48,9 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_MEMPOOL
=
y
CONFIG_RT_USING_MEMHEAP
=
y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM
=
y
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP
=
y
CONFIG_RT_USING_HEAP
=
y
#
...
...
@@ -64,6 +65,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_ARCH_ARM
=
y
CONFIG_ARCH_ARM_CORTEX_M
=
y
CONFIG_ARCH_ARM_CORTEX_M4
=
y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
...
...
@@ -113,10 +115,12 @@ CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
...
...
@@ -174,6 +178,7 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
#
# ARM CMSIS
...
...
@@ -318,6 +323,25 @@ CONFIG_RT_USING_PIN=y
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
CONFIG_SOC_FAMILY_STM32
=
y
CONFIG_SOC_SERIES_STM32F4
=
y
...
...
@@ -332,6 +356,7 @@ CONFIG_SOC_STM32F429IG=y
CONFIG_BSP_USING_USB_TO_USART
=
y
# CONFIG_BSP_USING_COM2 is not set
# CONFIG_BSP_USING_COM3 is not set
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_MPU9250 is not set
# CONFIG_BSP_USING_ETH is not set
...
...
@@ -351,5 +376,5 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_I2C1 is not set
#
#
Offboard Peripheral
Drivers
#
Board extended module
Drivers
#
bsp/stm32/stm32f429-atk-apollo/README.md
浏览文件 @
92338d50
...
...
@@ -45,20 +45,22 @@
| SPI Flash | 支持 | |
| 以太网 | 支持 | |
| MPU9250九轴传感器 | 支持 | |
| SDRAM | 支持 | |
| SD卡 | 暂不支持 | |
| CAN | 暂不支持 | |
| SDRAM | 暂不支持 | |
|
**片上外设**
|
**支持情况**
|
**备注**
|
| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
| UART | 支持 | UART1/2/3 |
| SPI | 支持 | SPI1/2/5 |
| I2C | 支持 | 软件 I2C |
| ADC | 支持 | |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 支持 | 已适配
[
FAL
](
https://github.com/RT-Thread-packages/fal
)
|
| SDIO | 暂不支持 | 即将支持 |
| RTC | 暂不支持 | 即将支持 |
| PWM | 暂不支持 | 即将支持 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
| IWG | 暂不支持 | 即将支持 |
|
**扩展模块**
|
**支持情况**
|
**备注**
|
| ATK-ESP8266 模块 | 暂不支持 | 即将支持 |
...
...
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject
浏览文件 @
92338d50
[PreviousGenFiles]
HeaderPath=
F:/eclipse_datastruct/search_null/rtt
/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc
HeaderPath=
D:
/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc
HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h;
SourcePath=
F:/eclipse_datastruct/search_null/rtt
/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src
SourcePath=
D:
/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src
SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_
eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
;
LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_
adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h
;
[]
SourceFiles=;;
[PreviousUsedKeilFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_
eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth
.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null;
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_
adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex
.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null;
HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
浏览文件 @
92338d50
...
...
@@ -49,7 +49,7 @@
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
...
...
@@ -62,18 +62,18 @@
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
...
...
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc
浏览文件 @
92338d50
#MicroXplorer Configuration settings - do not modify
ETH.IPParameters=MediaInterface,PHY_Name_RMII
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC1.master=1
ETH.IPParameters=MediaInterface
ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
ETH.PHY_Name_RMII=LAN8742A_PHY_ADDRESS
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=ETH
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=SPI5
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IPNb=6
Mcu.IP0=ADC1
Mcu.IP1=ETH
Mcu.IP2=FMC
Mcu.IP3=IWDG
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RTC
Mcu.IP7=SYS
Mcu.IP8=USART1
Mcu.IPNb=9
Mcu.Name=STM32F429I(E-G)Tx
Mcu.Package=LQFP176
Mcu.Pin0=PF7
Mcu.Pin1=PF8
Mcu.Pin10=PC5
Mcu.Pin11=PB11
Mcu.Pin12=PA9
Mcu.Pin13=PA10
Mcu.Pin14=PA13
Mcu.Pin15=PA14
Mcu.Pin16=PG13
Mcu.Pin17=PG14
Mcu.Pin18=VP_SYS_VS_Systick
Mcu.Pin2=PF9
Mcu.Pin3=PH0/OSC_IN
Mcu.Pin4=PH1/OSC_OUT
Mcu.Pin5=PC1
Mcu.Pin6=PA1
Mcu.Pin7=PA2
Mcu.Pin8=PA7
Mcu.Pin9=PC4
Mcu.PinsNb=19
Mcu.Pin0=PC14/OSC32_IN
Mcu.Pin1=PC15/OSC32_OUT
Mcu.Pin10=PC0
Mcu.Pin11=PC1
Mcu.Pin12=PC2
Mcu.Pin13=PC3
Mcu.Pin14=PA1
Mcu.Pin15=PA2
Mcu.Pin16=PA5
Mcu.Pin17=PA7
Mcu.Pin18=PC4
Mcu.Pin19=PC5
Mcu.Pin2=PF0
Mcu.Pin20=PF11
Mcu.Pin21=PF12
Mcu.Pin22=PF13
Mcu.Pin23=PF14
Mcu.Pin24=PF15
Mcu.Pin25=PG0
Mcu.Pin26=PG1
Mcu.Pin27=PE7
Mcu.Pin28=PE8
Mcu.Pin29=PE9
Mcu.Pin3=PF1
Mcu.Pin30=PE10
Mcu.Pin31=PE11
Mcu.Pin32=PE12
Mcu.Pin33=PE13
Mcu.Pin34=PE14
Mcu.Pin35=PE15
Mcu.Pin36=PB11
Mcu.Pin37=PD8
Mcu.Pin38=PD9
Mcu.Pin39=PD10
Mcu.Pin4=PF2
Mcu.Pin40=PD14
Mcu.Pin41=PD15
Mcu.Pin42=PG2
Mcu.Pin43=PG4
Mcu.Pin44=PG5
Mcu.Pin45=PG8
Mcu.Pin46=PA9
Mcu.Pin47=PA10
Mcu.Pin48=PA13
Mcu.Pin49=PA14
Mcu.Pin5=PF3
Mcu.Pin50=PD0
Mcu.Pin51=PD1
Mcu.Pin52=PG13
Mcu.Pin53=PG14
Mcu.Pin54=PG15
Mcu.Pin55=PE0
Mcu.Pin56=PE1
Mcu.Pin57=VP_IWDG_VS_IWDG
Mcu.Pin58=VP_RTC_VS_RTC_Activate
Mcu.Pin59=VP_SYS_VS_Systick
Mcu.Pin6=PF4
Mcu.Pin7=PF5
Mcu.Pin8=PH0/OSC_IN
Mcu.Pin9=PH1/OSC_OUT
Mcu.PinsNb=60
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F429IGTx
...
...
@@ -60,14 +109,24 @@ PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA2.Mode=RMII
PA2.Signal=ETH_MDIO
PA5.Signal=ADCx_IN5
PA7.Mode=RMII
PA7.Signal=ETH_CRS_DV
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB11.Mode=RMII
PB11.Signal=ETH_TX_EN
PC0.Signal=FMC_SDNWE
PC1.Mode=RMII
PC1.Signal=ETH_MDC
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.Mode=SdramChipSelect1_1
PC2.Signal=FMC_SDNE0
PC3.Mode=SdramChipSelect1_1
PC3.Signal=FMC_SDCKE0
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
...
...
@@ -80,18 +139,48 @@ PCC.Seq0=0
PCC.Series=STM32F4
PCC.Temperature=25
PCC.Vdd=null
PF7.Mode=Full_Duplex_Master
PF7.Signal=SPI5_SCK
PF8.Mode=Full_Duplex_Master
PF8.Signal=SPI5_MISO
PF9.Mode=Full_Duplex_Master
PF9.Signal=SPI5_MOSI
PD0.Signal=FMC_D2_DA2
PD1.Signal=FMC_D3_DA3
PD10.Signal=FMC_D15_DA15
PD14.Signal=FMC_D0_DA0
PD15.Signal=FMC_D1_DA1
PD8.Signal=FMC_D13_DA13
PD9.Signal=FMC_D14_DA14
PE0.Signal=FMC_NBL0
PE1.Signal=FMC_NBL1
PE10.Signal=FMC_D7_DA7
PE11.Signal=FMC_D8_DA8
PE12.Signal=FMC_D9_DA9
PE13.Signal=FMC_D10_DA10
PE14.Signal=FMC_D11_DA11
PE15.Signal=FMC_D12_DA12
PE7.Signal=FMC_D4_DA4
PE8.Signal=FMC_D5_DA5
PE9.Signal=FMC_D6_DA6
PF0.Signal=FMC_A0
PF1.Signal=FMC_A1
PF11.Signal=FMC_SDNRAS
PF12.Signal=FMC_A6
PF13.Signal=FMC_A7
PF14.Signal=FMC_A8
PF15.Signal=FMC_A9
PF2.Signal=FMC_A2
PF3.Signal=FMC_A3
PF4.Signal=FMC_A4
PF5.Signal=FMC_A5
PG0.Signal=FMC_A10
PG1.Signal=FMC_A11
PG13.Locked=true
PG13.Mode=RMII
PG13.Signal=ETH_TXD0
PG14.Locked=true
PG14.Mode=RMII
PG14.Signal=ETH_TXD1
PG15.Signal=FMC_SDNCAS
PG2.Signal=FMC_A12
PG4.Signal=FMC_A14_BA0
PG5.Signal=FMC_A15_BA1
PG8.Signal=FMC_SDCLK
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
...
...
@@ -111,7 +200,7 @@ ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=
tru
e
ProjectManager.LastFirmware=
fals
e
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
...
...
@@ -123,54 +212,128 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_
SPI5_Init-SPI5
-false-HAL-true
RCC.48MHZClocksFreq_Value=
75
000000
RCC.AHBFreq_Value=1
5
0000000
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_
FMC_Init-FMC-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_ADC1_Init-ADC1
-false-HAL-true
RCC.48MHZClocksFreq_Value=
90
000000
RCC.AHBFreq_Value=1
8
0000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=
375
00000
RCC.APB1TimFreq_Value=
75
000000
RCC.APB1Freq_Value=
450
00000
RCC.APB1TimFreq_Value=
90
000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=
75
000000
RCC.APB2TimFreq_Value=1
5
0000000
RCC.CortexFreq_Value=1
5
0000000
RCC.EthernetFreq_Value=1
5
0000000
RCC.FCLKCortexFreq_Value=1
5
0000000
RCC.APB2Freq_Value=
90
000000
RCC.APB2TimFreq_Value=1
8
0000000
RCC.CortexFreq_Value=1
8
0000000
RCC.EthernetFreq_Value=1
8
0000000
RCC.FCLKCortexFreq_Value=1
8
0000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=1
5
0000000
RCC.HCLKFreq_Value=1
8
0000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=160000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LS
E_VALUE,LS
I_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
RCC.LCDTFTFreq_Value=20416666.666666668
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=1
5
0000000
RCC.PLLCLKFreq_Value=1
5
0000000
RCC.MCO2PinFreq_Value=1
8
0000000
RCC.PLLCLKFreq_Value=1
8
0000000
RCC.PLLM=15
RCC.PLLN=
180
RCC.PLLQCLKFreq_Value=
75
000000
RCC.PLLN=
216
RCC.PLLQCLKFreq_Value=
90
000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCFreq_Value=32000
RCC.RTCHSEDivFreq_Value=12500000
RCC.SAI_AClocksFreq_Value=20416666.666666668
RCC.SAI_BClocksFreq_Value=20416666.666666668
RCC.SYSCLKFreq_VALUE=1
5
0000000
RCC.SYSCLKFreq_VALUE=1
8
0000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.VCOI2SOutputFreq_Value=320000000
RCC.VCOInputFreq_Value=1666666.6666666667
RCC.VCOOutputFreq_Value=3
0
0000000
RCC.VCOOutputFreq_Value=3
6
0000000
RCC.VCOSAIOutputFreq_Value=81666666.66666667
RCC.VCOSAIOutputFreq_ValueQ=20416666.666666668
RCC.VCOSAIOutputFreq_ValueR=40833333.333333336
RCC.VcooutputI2S=160000000
RCC.VcooutputI2SQ=160000000
SPI5.CalculateBaudRate=37.5 MBits/s
SPI5.Direction=SPI_DIRECTION_2LINES
SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI5.Mode=SPI_MODE_MASTER
SPI5.VirtualType=VM_MASTER
SH.ADCx_IN5.0=ADC1_IN5,IN5
SH.ADCx_IN5.ConfNb=1
SH.FMC_A0.0=FMC_A0,13b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,13b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,13b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,13b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A12.0=FMC_A12,13b-sda1
SH.FMC_A12.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,13b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,13b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,13b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,13b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,13b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,13b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,13b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,13b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
SH.FMC_NBL0.ConfNb=1
SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
SH.FMC_NBL1.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,13b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,13b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1
SH.FMC_SDNWE.ConfNb=1
USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c
浏览文件 @
92338d50
...
...
@@ -62,12 +62,18 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef
hadc1
;
ETH_HandleTypeDef
heth
;
SPI_HandleTypeDef
hspi5
;
IWDG_HandleTypeDef
hiwdg
;
RTC_HandleTypeDef
hrtc
;
UART_HandleTypeDef
huart1
;
SDRAM_HandleTypeDef
hsdram1
;
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
...
...
@@ -78,7 +84,10 @@ void SystemClock_Config(void);
static
void
MX_GPIO_Init
(
void
);
static
void
MX_USART1_UART_Init
(
void
);
static
void
MX_ETH_Init
(
void
);
static
void
MX_SPI5_Init
(
void
);
static
void
MX_FMC_Init
(
void
);
static
void
MX_RTC_Init
(
void
);
static
void
MX_IWDG_Init
(
void
);
static
void
MX_ADC1_Init
(
void
);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
...
...
@@ -119,7 +128,10 @@ int main(void)
MX_GPIO_Init
();
MX_USART1_UART_Init
();
MX_ETH_Init
();
MX_SPI5_Init
();
MX_FMC_Init
();
MX_RTC_Init
();
MX_IWDG_Init
();
MX_ADC1_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
...
...
@@ -145,6 +157,7 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
=
{
0
};
/**Configure the main internal regulator output voltage
*/
...
...
@@ -152,18 +165,25 @@ void SystemClock_Config(void)
__HAL_PWR_VOLTAGESCALING_CONFIG
(
PWR_REGULATOR_VOLTAGE_SCALE1
);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_
LSI
|
RCC_OSCILLATORTYPE_
HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
LSIState
=
RCC_LSI_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
15
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
180
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
216
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
4
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Activate the Over-Drive mode
*/
if
(
HAL_PWREx_EnableOverDrive
()
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
...
...
@@ -173,10 +193,66 @@ void SystemClock_Config(void)
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV4
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV2
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_5
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSI
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_ADC1_Init
(
void
)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef
sConfig
=
{
0
};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/**Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1
.
Instance
=
ADC1
;
hadc1
.
Init
.
ClockPrescaler
=
ADC_CLOCK_SYNC_PCLK_DIV4
;
hadc1
.
Init
.
Resolution
=
ADC_RESOLUTION_12B
;
hadc1
.
Init
.
ScanConvMode
=
DISABLE
;
hadc1
.
Init
.
ContinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
DiscontinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
ExternalTrigConvEdge
=
ADC_EXTERNALTRIGCONVEDGE_NONE
;
hadc1
.
Init
.
ExternalTrigConv
=
ADC_SOFTWARE_START
;
hadc1
.
Init
.
DataAlign
=
ADC_DATAALIGN_RIGHT
;
hadc1
.
Init
.
NbrOfConversion
=
1
;
hadc1
.
Init
.
DMAContinuousRequests
=
DISABLE
;
hadc1
.
Init
.
EOCSelection
=
ADC_EOC_SINGLE_CONV
;
if
(
HAL_ADC_Init
(
&
hadc1
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig
.
Channel
=
ADC_CHANNEL_5
;
sConfig
.
Rank
=
1
;
sConfig
.
SamplingTime
=
ADC_SAMPLETIME_3CYCLES
;
if
(
HAL_ADC_ConfigChannel
(
&
hadc1
,
&
sConfig
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
...
...
@@ -225,40 +301,64 @@ static void MX_ETH_Init(void)
}
/**
* @brief
SPI5
Initialization Function
* @brief
IWDG
Initialization Function
* @param None
* @retval None
*/
static
void
MX_
SPI5
_Init
(
void
)
static
void
MX_
IWDG
_Init
(
void
)
{
/* USER CODE BEGIN SPI5_Init 0 */
/* USER CODE END SPI5_Init 0 */
/* USER CODE BEGIN SPI5_Init 1 */
/* USER CODE END SPI5_Init 1 */
/* SPI5 parameter configuration*/
hspi5
.
Instance
=
SPI5
;
hspi5
.
Init
.
Mode
=
SPI_MODE_MASTER
;
hspi5
.
Init
.
Direction
=
SPI_DIRECTION_2LINES
;
hspi5
.
Init
.
DataSize
=
SPI_DATASIZE_8BIT
;
hspi5
.
Init
.
CLKPolarity
=
SPI_POLARITY_LOW
;
hspi5
.
Init
.
CLKPhase
=
SPI_PHASE_1EDGE
;
hspi5
.
Init
.
NSS
=
SPI_NSS_SOFT
;
hspi5
.
Init
.
BaudRatePrescaler
=
SPI_BAUDRATEPRESCALER_2
;
hspi5
.
Init
.
FirstBit
=
SPI_FIRSTBIT_MSB
;
hspi5
.
Init
.
TIMode
=
SPI_TIMODE_DISABLE
;
hspi5
.
Init
.
CRCCalculation
=
SPI_CRCCALCULATION_DISABLE
;
hspi5
.
Init
.
CRCPolynomial
=
10
;
if
(
HAL_SPI_Init
(
&
hspi5
)
!=
HAL_OK
)
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_4
;
hiwdg
.
Init
.
Reload
=
4095
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static
void
MX_RTC_Init
(
void
)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/**Initialize RTC Only
*/
hrtc
.
Instance
=
RTC
;
hrtc
.
Init
.
HourFormat
=
RTC_HOURFORMAT_24
;
hrtc
.
Init
.
AsynchPrediv
=
127
;
hrtc
.
Init
.
SynchPrediv
=
255
;
hrtc
.
Init
.
OutPut
=
RTC_OUTPUT_DISABLE
;
hrtc
.
Init
.
OutPutPolarity
=
RTC_OUTPUT_POLARITY_HIGH
;
hrtc
.
Init
.
OutPutType
=
RTC_OUTPUT_TYPE_OPENDRAIN
;
if
(
HAL_RTC_Init
(
&
hrtc
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN
SPI5
_Init 2 */
/* USER CODE BEGIN
RTC
_Init 2 */
/* USER CODE END
SPI5
_Init 2 */
/* USER CODE END
RTC
_Init 2 */
}
...
...
@@ -295,6 +395,41 @@ static void MX_USART1_UART_Init(void)
}
/* FMC initialization function */
static
void
MX_FMC_Init
(
void
)
{
FMC_SDRAM_TimingTypeDef
SdramTiming
;
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1
.
Instance
=
FMC_SDRAM_DEVICE
;
/* hsdram1.Init */
hsdram1
.
Init
.
SDBank
=
FMC_SDRAM_BANK1
;
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_8
;
hsdram1
.
Init
.
RowBitsNumber
=
FMC_SDRAM_ROW_BITS_NUM_13
;
hsdram1
.
Init
.
MemoryDataWidth
=
FMC_SDRAM_MEM_BUS_WIDTH_16
;
hsdram1
.
Init
.
InternalBankNumber
=
FMC_SDRAM_INTERN_BANKS_NUM_4
;
hsdram1
.
Init
.
CASLatency
=
FMC_SDRAM_CAS_LATENCY_1
;
hsdram1
.
Init
.
WriteProtection
=
FMC_SDRAM_WRITE_PROTECTION_DISABLE
;
hsdram1
.
Init
.
SDClockPeriod
=
FMC_SDRAM_CLOCK_DISABLE
;
hsdram1
.
Init
.
ReadBurst
=
FMC_SDRAM_RBURST_DISABLE
;
hsdram1
.
Init
.
ReadPipeDelay
=
FMC_SDRAM_RPIPE_DELAY_0
;
/* SdramTiming */
SdramTiming
.
LoadToActiveDelay
=
16
;
SdramTiming
.
ExitSelfRefreshDelay
=
16
;
SdramTiming
.
SelfRefreshTime
=
16
;
SdramTiming
.
RowCycleDelay
=
16
;
SdramTiming
.
WriteRecoveryTime
=
16
;
SdramTiming
.
RPDelay
=
16
;
SdramTiming
.
RCDDelay
=
16
;
if
(
HAL_SDRAM_Init
(
&
hsdram1
,
&
SdramTiming
)
!=
HAL_OK
)
{
Error_Handler
(
);
}
}
/**
* @brief GPIO Initialization Function
* @param None
...
...
@@ -304,12 +439,14 @@ static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOF_CLK_ENABLE
();
__HAL_RCC_GPIOH_CLK_ENABLE
();
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
__HAL_RCC_GPIOE_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOD_CLK_ENABLE
();
}
...
...
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
浏览文件 @
92338d50
...
...
@@ -97,6 +97,70 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspInit
(
ADC_HandleTypeDef
*
hadc
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
/**ADC1 GPIO Configuration
PA5 ------> ADC1_IN5
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_5
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_ANALOG
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
HAL_GPIO_Init
(
GPIOA
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspDeInit
(
ADC_HandleTypeDef
*
hadc
)
{
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE
();
/**ADC1 GPIO Configuration
PA5 ------> ADC1_IN5
*/
HAL_GPIO_DeInit
(
GPIOA
,
GPIO_PIN_5
);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief ETH MSP Initialization
* This function configures the hardware resources used in this example
...
...
@@ -210,71 +274,48 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
}
/**
* @brief
SPI
MSP Initialization
* @brief
RTC
MSP Initialization
* This function configures the hardware resources used in this example
* @param h
spi: SPI
handle pointer
* @param h
rtc: RTC
handle pointer
* @retval None
*/
void
HAL_
SPI_MspInit
(
SPI_HandleTypeDef
*
hspi
)
void
HAL_
RTC_MspInit
(
RTC_HandleTypeDef
*
hrtc
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
hspi
->
Instance
==
SPI5
)
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN
SPI5
_MspInit 0 */
/* USER CODE BEGIN
RTC
_MspInit 0 */
/* USER CODE END
SPI5
_MspInit 0 */
/* USER CODE END
RTC
_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI5_CLK_ENABLE
();
__HAL_RCC_GPIOF_CLK_ENABLE
();
/**SPI5 GPIO Configuration
PF7 ------> SPI5_SCK
PF8 ------> SPI5_MISO
PF9 ------> SPI5_MOSI
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_7
|
GPIO_PIN_8
|
GPIO_PIN_9
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF5_SPI5
;
HAL_GPIO_Init
(
GPIOF
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN SPI5_MspInit 1 */
__HAL_RCC_RTC_ENABLE
();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END
SPI5
_MspInit 1 */
/* USER CODE END
RTC
_MspInit 1 */
}
}
/**
* @brief
SPI
MSP De-Initialization
* @brief
RTC
MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param h
spi: SPI
handle pointer
* @param h
rtc: RTC
handle pointer
* @retval None
*/
void
HAL_
SPI_MspDeInit
(
SPI_HandleTypeDef
*
hspi
)
void
HAL_
RTC_MspDeInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
h
spi
->
Instance
==
SPI5
)
if
(
h
rtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN
SPI5
_MspDeInit 0 */
/* USER CODE BEGIN
RTC
_MspDeInit 0 */
/* USER CODE END
SPI5
_MspDeInit 0 */
/* USER CODE END
RTC
_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI5_CLK_DISABLE
();
/**SPI5 GPIO Configuration
PF7 ------> SPI5_SCK
PF8 ------> SPI5_MISO
PF9 ------> SPI5_MOSI
*/
HAL_GPIO_DeInit
(
GPIOF
,
GPIO_PIN_7
|
GPIO_PIN_8
|
GPIO_PIN_9
);
/* USER CODE BEGIN SPI5_MspDeInit 1 */
__HAL_RCC_RTC_DISABLE
();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END
SPI5
_MspDeInit 1 */
/* USER CODE END
RTC
_MspDeInit 1 */
}
}
...
...
@@ -353,6 +394,202 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
}
static
uint32_t
FMC_Initialized
=
0
;
static
void
HAL_FMC_MspInit
(
void
){
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef
GPIO_InitStruct
;
if
(
FMC_Initialized
)
{
return
;
}
FMC_Initialized
=
1
;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE
();
/** FMC GPIO Configuration
PF0 ------> FMC_A0
PF1 ------> FMC_A1
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PC0 ------> FMC_SDNWE
PC2 ------> FMC_SDNE0
PC3 ------> FMC_SDCKE0
PF11 ------> FMC_SDNRAS
PF12 ------> FMC_A6
PF13 ------> FMC_A7
PF14 ------> FMC_A8
PF15 ------> FMC_A9
PG0 ------> FMC_A10
PG1 ------> FMC_A11
PE7 ------> FMC_D4
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE10 ------> FMC_D7
PE11 ------> FMC_D8
PE12 ------> FMC_D9
PE13 ------> FMC_D10
PE14 ------> FMC_D11
PE15 ------> FMC_D12
PD8 ------> FMC_D13
PD9 ------> FMC_D14
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD15 ------> FMC_D1
PG2 ------> FMC_A12
PG4 ------> FMC_BA0
PG5 ------> FMC_BA1
PG8 ------> FMC_SDCLK
PD0 ------> FMC_D2
PD1 ------> FMC_D3
PG15 ------> FMC_SDNCAS
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_3
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOF
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_0
|
GPIO_PIN_2
|
GPIO_PIN_3
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOC
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_8
|
GPIO_PIN_15
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOG
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_7
|
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOE
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOD
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
void
HAL_SDRAM_MspInit
(
SDRAM_HandleTypeDef
*
hsdram
){
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit
();
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
static
uint32_t
FMC_DeInitialized
=
0
;
static
void
HAL_FMC_MspDeInit
(
void
){
/* USER CODE BEGIN FMC_MspDeInit 0 */
/* USER CODE END FMC_MspDeInit 0 */
if
(
FMC_DeInitialized
)
{
return
;
}
FMC_DeInitialized
=
1
;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_DISABLE
();
/** FMC GPIO Configuration
PF0 ------> FMC_A0
PF1 ------> FMC_A1
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PC0 ------> FMC_SDNWE
PC2 ------> FMC_SDNE0
PC3 ------> FMC_SDCKE0
PF11 ------> FMC_SDNRAS
PF12 ------> FMC_A6
PF13 ------> FMC_A7
PF14 ------> FMC_A8
PF15 ------> FMC_A9
PG0 ------> FMC_A10
PG1 ------> FMC_A11
PE7 ------> FMC_D4
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE10 ------> FMC_D7
PE11 ------> FMC_D8
PE12 ------> FMC_D9
PE13 ------> FMC_D10
PE14 ------> FMC_D11
PE15 ------> FMC_D12
PD8 ------> FMC_D13
PD9 ------> FMC_D14
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD15 ------> FMC_D1
PG2 ------> FMC_A12
PG4 ------> FMC_BA0
PG5 ------> FMC_BA1
PG8 ------> FMC_SDCLK
PD0 ------> FMC_D2
PD1 ------> FMC_D3
PG15 ------> FMC_SDNCAS
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
HAL_GPIO_DeInit
(
GPIOF
,
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_3
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
);
HAL_GPIO_DeInit
(
GPIOC
,
GPIO_PIN_0
|
GPIO_PIN_2
|
GPIO_PIN_3
);
HAL_GPIO_DeInit
(
GPIOG
,
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_8
|
GPIO_PIN_15
);
HAL_GPIO_DeInit
(
GPIOE
,
GPIO_PIN_7
|
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
);
HAL_GPIO_DeInit
(
GPIOD
,
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
);
/* USER CODE BEGIN FMC_MspDeInit 1 */
/* USER CODE END FMC_MspDeInit 1 */
}
void
HAL_SDRAM_MspDeInit
(
SDRAM_HandleTypeDef
*
hsdram
){
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
/* USER CODE END SDRAM_MspDeInit 0 */
HAL_FMC_MspDeInit
();
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
/* USER CODE END SDRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
...
...
bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/system_stm32f4xx.c
0 → 100644
浏览文件 @
92338d50
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000)
/*!< Default value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
/* #define DATA_IN_ExtSRAM */
#endif
/* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00
/*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t
SystemCoreClock
=
16000000
;
const
uint8_t
AHBPrescTable
[
16
]
=
{
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
,
6
,
7
,
8
,
9
};
const
uint8_t
APBPrescTable
[
8
]
=
{
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static
void
SystemInit_ExtMemCtl
(
void
);
#endif
/* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void
SystemInit
(
void
)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB
->
CPACR
|=
((
3UL
<<
10
*
2
)
|
(
3UL
<<
11
*
2
));
/* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC
->
CR
|=
(
uint32_t
)
0x00000001
;
/* Reset CFGR register */
RCC
->
CFGR
=
0x00000000
;
/* Reset HSEON, CSSON and PLLON bits */
RCC
->
CR
&=
(
uint32_t
)
0xFEF6FFFF
;
/* Reset PLLCFGR register */
RCC
->
PLLCFGR
=
0x24003010
;
/* Reset HSEBYP bit */
RCC
->
CR
&=
(
uint32_t
)
0xFFFBFFFF
;
/* Disable all interrupts */
RCC
->
CIR
=
0x00000000
;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl
();
#endif
/* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB
->
VTOR
=
SRAM_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal SRAM */
#else
SCB
->
VTOR
=
FLASH_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void
SystemCoreClockUpdate
(
void
)
{
uint32_t
tmp
=
0
,
pllvco
=
0
,
pllp
=
2
,
pllsource
=
0
,
pllm
=
2
;
/* Get SYSCLK source -------------------------------------------------------*/
tmp
=
RCC
->
CFGR
&
RCC_CFGR_SWS
;
switch
(
tmp
)
{
case
0x00
:
/* HSI used as system clock source */
SystemCoreClock
=
HSI_VALUE
;
break
;
case
0x04
:
/* HSE used as system clock source */
SystemCoreClock
=
HSE_VALUE
;
break
;
case
0x08
:
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource
=
(
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLSRC
)
>>
22
;
pllm
=
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLM
;
if
(
pllsource
!=
0
)
{
/* HSE used as PLL clock source */
pllvco
=
(
HSE_VALUE
/
pllm
)
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
6
);
}
else
{
/* HSI used as PLL clock source */
pllvco
=
(
HSI_VALUE
/
pllm
)
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
6
);
}
pllp
=
(((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLP
)
>>
16
)
+
1
)
*
2
;
SystemCoreClock
=
pllvco
/
pllp
;
break
;
default:
SystemCoreClock
=
HSI_VALUE
;
break
;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp
=
AHBPrescTable
[((
RCC
->
CFGR
&
RCC_CFGR_HPRE
)
>>
4
)];
/* HCLK frequency */
SystemCoreClock
>>=
tmp
;
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void
SystemInit_ExtMemCtl
(
void
)
{
__IO
uint32_t
tmp
=
0x00
;
register
uint32_t
tmpreg
=
0
,
timeout
=
0xFFFF
;
register
__IO
uint32_t
index
;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
RCC
->
AHB1ENR
|=
0x000001F8
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB1ENR
,
RCC_AHB1ENR_GPIOCEN
);
/* Connect PDx pins to FMC Alternate function */
GPIOD
->
AFR
[
0
]
=
0x00CCC0CC
;
GPIOD
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PDx pins in Alternate function mode */
GPIOD
->
MODER
=
0xAAAA0A8A
;
/* Configure PDx pins speed to 100 MHz */
GPIOD
->
OSPEEDR
=
0xFFFF0FCF
;
/* Configure PDx pins Output type to push-pull */
GPIOD
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOD
->
PUPDR
=
0x00000000
;
/* Connect PEx pins to FMC Alternate function */
GPIOE
->
AFR
[
0
]
=
0xC00CC0CC
;
GPIOE
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PEx pins in Alternate function mode */
GPIOE
->
MODER
=
0xAAAA828A
;
/* Configure PEx pins speed to 100 MHz */
GPIOE
->
OSPEEDR
=
0xFFFFC3CF
;
/* Configure PEx pins Output type to push-pull */
GPIOE
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PEx pins */
GPIOE
->
PUPDR
=
0x00000000
;
/* Connect PFx pins to FMC Alternate function */
GPIOF
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOF
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PFx pins in Alternate function mode */
GPIOF
->
MODER
=
0xAA800AAA
;
/* Configure PFx pins speed to 50 MHz */
GPIOF
->
OSPEEDR
=
0xAA800AAA
;
/* Configure PFx pins Output type to push-pull */
GPIOF
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PFx pins */
GPIOF
->
PUPDR
=
0x00000000
;
/* Connect PGx pins to FMC Alternate function */
GPIOG
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOG
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PGx pins in Alternate function mode */
GPIOG
->
MODER
=
0xAAAAAAAA
;
/* Configure PGx pins speed to 50 MHz */
GPIOG
->
OSPEEDR
=
0xAAAAAAAA
;
/* Configure PGx pins Output type to push-pull */
GPIOG
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PGx pins */
GPIOG
->
PUPDR
=
0x00000000
;
/* Connect PHx pins to FMC Alternate function */
GPIOH
->
AFR
[
0
]
=
0x00C0CC00
;
GPIOH
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PHx pins in Alternate function mode */
GPIOH
->
MODER
=
0xAAAA08A0
;
/* Configure PHx pins speed to 50 MHz */
GPIOH
->
OSPEEDR
=
0xAAAA08A0
;
/* Configure PHx pins Output type to push-pull */
GPIOH
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PHx pins */
GPIOH
->
PUPDR
=
0x00000000
;
/* Connect PIx pins to FMC Alternate function */
GPIOI
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOI
->
AFR
[
1
]
=
0x00000CC0
;
/* Configure PIx pins in Alternate function mode */
GPIOI
->
MODER
=
0x0028AAAA
;
/* Configure PIx pins speed to 50 MHz */
GPIOI
->
OSPEEDR
=
0x0028AAAA
;
/* Configure PIx pins Output type to push-pull */
GPIOI
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PIx pins */
GPIOI
->
PUPDR
=
0x00000000
;
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC
->
AHB3ENR
|=
0x00000001
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
FMC_Bank5_6
->
SDCR
[
0
]
=
0x000019E4
;
FMC_Bank5_6
->
SDTR
[
0
]
=
0x01115351
;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6
->
SDCMR
=
0x00000011
;
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Delay */
for
(
index
=
0
;
index
<
1000
;
index
++
);
/* PALL command */
FMC_Bank5_6
->
SDCMR
=
0x00000012
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Auto refresh command */
FMC_Bank5_6
->
SDCMR
=
0x00000073
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* MRD register program */
FMC_Bank5_6
->
SDCMR
=
0x00046014
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Set refresh count */
tmpreg
=
FMC_Bank5_6
->
SDRTR
;
FMC_Bank5_6
->
SDRTR
=
(
tmpreg
|
(
0x0000027C
<<
1
));
/* Disable write protection */
tmpreg
=
FMC_Bank5_6
->
SDCR
[
0
];
FMC_Bank5_6
->
SDCR
[
0
]
=
(
tmpreg
&
0xFFFFFDFF
);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001011
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00000201
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001091
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00110212
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F469xx || STM32F479xx */
(
void
)(
tmp
);
}
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void
SystemInit_ExtMemCtl
(
void
)
{
__IO
uint32_t
tmp
=
0x00
;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register
uint32_t
tmpreg
=
0
,
timeout
=
0xFFFF
;
register
__IO
uint32_t
index
;
#if defined(STM32F446xx)
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
clock */
RCC
->
AHB1ENR
|=
0x0000007D
;
#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC
->
AHB1ENR
|=
0x000001F8
;
#endif
/* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB1ENR
,
RCC_AHB1ENR_GPIOCEN
);
#if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */
GPIOA
->
AFR
[
0
]
|=
0xC0000000
;
GPIOA
->
AFR
[
1
]
|=
0x00000000
;
/* Configure PDx pins in Alternate function mode */
GPIOA
->
MODER
|=
0x00008000
;
/* Configure PDx pins speed to 50 MHz */
GPIOA
->
OSPEEDR
|=
0x00008000
;
/* Configure PDx pins Output type to push-pull */
GPIOA
->
OTYPER
|=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOA
->
PUPDR
|=
0x00000000
;
/* Connect PCx pins to FMC Alternate function */
GPIOC
->
AFR
[
0
]
|=
0x00CC0000
;
GPIOC
->
AFR
[
1
]
|=
0x00000000
;
/* Configure PDx pins in Alternate function mode */
GPIOC
->
MODER
|=
0x00000A00
;
/* Configure PDx pins speed to 50 MHz */
GPIOC
->
OSPEEDR
|=
0x00000A00
;
/* Configure PDx pins Output type to push-pull */
GPIOC
->
OTYPER
|=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOC
->
PUPDR
|=
0x00000000
;
#endif
/* STM32F446xx */
/* Connect PDx pins to FMC Alternate function */
GPIOD
->
AFR
[
0
]
=
0x000000CC
;
GPIOD
->
AFR
[
1
]
=
0xCC000CCC
;
/* Configure PDx pins in Alternate function mode */
GPIOD
->
MODER
=
0xA02A000A
;
/* Configure PDx pins speed to 50 MHz */
GPIOD
->
OSPEEDR
=
0xA02A000A
;
/* Configure PDx pins Output type to push-pull */
GPIOD
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOD
->
PUPDR
=
0x00000000
;
/* Connect PEx pins to FMC Alternate function */
GPIOE
->
AFR
[
0
]
=
0xC00000CC
;
GPIOE
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PEx pins in Alternate function mode */
GPIOE
->
MODER
=
0xAAAA800A
;
/* Configure PEx pins speed to 50 MHz */
GPIOE
->
OSPEEDR
=
0xAAAA800A
;
/* Configure PEx pins Output type to push-pull */
GPIOE
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PEx pins */
GPIOE
->
PUPDR
=
0x00000000
;
/* Connect PFx pins to FMC Alternate function */
GPIOF
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOF
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PFx pins in Alternate function mode */
GPIOF
->
MODER
=
0xAA800AAA
;
/* Configure PFx pins speed to 50 MHz */
GPIOF
->
OSPEEDR
=
0xAA800AAA
;
/* Configure PFx pins Output type to push-pull */
GPIOF
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PFx pins */
GPIOF
->
PUPDR
=
0x00000000
;
/* Connect PGx pins to FMC Alternate function */
GPIOG
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOG
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PGx pins in Alternate function mode */
GPIOG
->
MODER
=
0xAAAAAAAA
;
/* Configure PGx pins speed to 50 MHz */
GPIOG
->
OSPEEDR
=
0xAAAAAAAA
;
/* Configure PGx pins Output type to push-pull */
GPIOG
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PGx pins */
GPIOG
->
PUPDR
=
0x00000000
;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH
->
AFR
[
0
]
=
0x00C0CC00
;
GPIOH
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PHx pins in Alternate function mode */
GPIOH
->
MODER
=
0xAAAA08A0
;
/* Configure PHx pins speed to 50 MHz */
GPIOH
->
OSPEEDR
=
0xAAAA08A0
;
/* Configure PHx pins Output type to push-pull */
GPIOH
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PHx pins */
GPIOH
->
PUPDR
=
0x00000000
;
/* Connect PIx pins to FMC Alternate function */
GPIOI
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOI
->
AFR
[
1
]
=
0x00000CC0
;
/* Configure PIx pins in Alternate function mode */
GPIOI
->
MODER
=
0x0028AAAA
;
/* Configure PIx pins speed to 50 MHz */
GPIOI
->
OSPEEDR
=
0x0028AAAA
;
/* Configure PIx pins Output type to push-pull */
GPIOI
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PIx pins */
GPIOI
->
PUPDR
=
0x00000000
;
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC
->
AHB3ENR
|=
0x00000001
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
/* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDCR
[
0
]
=
0x00001954
;
#else
FMC_Bank5_6
->
SDCR
[
0
]
=
0x000019E4
;
#endif
/* STM32F446xx */
FMC_Bank5_6
->
SDTR
[
0
]
=
0x01115351
;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6
->
SDCMR
=
0x00000011
;
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Delay */
for
(
index
=
0
;
index
<
1000
;
index
++
);
/* PALL command */
FMC_Bank5_6
->
SDCMR
=
0x00000012
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Auto refresh command */
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDCMR
=
0x000000F3
;
#else
FMC_Bank5_6
->
SDCMR
=
0x00000073
;
#endif
/* STM32F446xx */
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* MRD register program */
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDCMR
=
0x00044014
;
#else
FMC_Bank5_6
->
SDCMR
=
0x00046014
;
#endif
/* STM32F446xx */
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Set refresh count */
tmpreg
=
FMC_Bank5_6
->
SDRTR
;
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDRTR
=
(
tmpreg
|
(
0x0000050C
<<
1
));
#else
FMC_Bank5_6
->
SDRTR
=
(
tmpreg
|
(
0x0000027C
<<
1
));
#endif
/* STM32F446xx */
/* Disable write protection */
tmpreg
=
FMC_Bank5_6
->
SDCR
[
0
];
FMC_Bank5_6
->
SDCR
[
0
]
=
(
tmpreg
&
0xFFFFFDFF
);
#endif
/* DATA_IN_ExtSDRAM */
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC
->
AHB1ENR
|=
0x00000078
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB1ENR
,
RCC_AHB1ENR_GPIODEN
);
/* Connect PDx pins to FMC Alternate function */
GPIOD
->
AFR
[
0
]
=
0x00CCC0CC
;
GPIOD
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PDx pins in Alternate function mode */
GPIOD
->
MODER
=
0xAAAA0A8A
;
/* Configure PDx pins speed to 100 MHz */
GPIOD
->
OSPEEDR
=
0xFFFF0FCF
;
/* Configure PDx pins Output type to push-pull */
GPIOD
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOD
->
PUPDR
=
0x00000000
;
/* Connect PEx pins to FMC Alternate function */
GPIOE
->
AFR
[
0
]
=
0xC00CC0CC
;
GPIOE
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PEx pins in Alternate function mode */
GPIOE
->
MODER
=
0xAAAA828A
;
/* Configure PEx pins speed to 100 MHz */
GPIOE
->
OSPEEDR
=
0xFFFFC3CF
;
/* Configure PEx pins Output type to push-pull */
GPIOE
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PEx pins */
GPIOE
->
PUPDR
=
0x00000000
;
/* Connect PFx pins to FMC Alternate function */
GPIOF
->
AFR
[
0
]
=
0x00CCCCCC
;
GPIOF
->
AFR
[
1
]
=
0xCCCC0000
;
/* Configure PFx pins in Alternate function mode */
GPIOF
->
MODER
=
0xAA000AAA
;
/* Configure PFx pins speed to 100 MHz */
GPIOF
->
OSPEEDR
=
0xFF000FFF
;
/* Configure PFx pins Output type to push-pull */
GPIOF
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PFx pins */
GPIOF
->
PUPDR
=
0x00000000
;
/* Connect PGx pins to FMC Alternate function */
GPIOG
->
AFR
[
0
]
=
0x00CCCCCC
;
GPIOG
->
AFR
[
1
]
=
0x000000C0
;
/* Configure PGx pins in Alternate function mode */
GPIOG
->
MODER
=
0x00085AAA
;
/* Configure PGx pins speed to 100 MHz */
GPIOG
->
OSPEEDR
=
0x000CAFFF
;
/* Configure PGx pins Output type to push-pull */
GPIOG
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PGx pins */
GPIOG
->
PUPDR
=
0x00000000
;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC
->
AHB3ENR
|=
0x00000001
;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001011
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00000201
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001091
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00110212
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FSMCEN
);
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1
->
BTCR
[
2
]
=
0x00001011
;
FSMC_Bank1
->
BTCR
[
3
]
=
0x00000201
;
FSMC_Bank1E
->
BWTR
[
2
]
=
0x0FFFFFFF
;
#endif
/* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
#endif
/* DATA_IN_ExtSRAM */
#endif
/* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(
void
)(
tmp
);
}
#endif
/* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f429-atk-apollo/board/Kconfig
浏览文件 @
92338d50
...
...
@@ -21,7 +21,11 @@ menu "Onboard Peripheral Drivers"
bool "Enable COM3 (uart3)"
select BSP_USING_UART3
default n
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (w25q256 spi5)"
select BSP_USING_SPI5
...
...
@@ -74,7 +78,11 @@ menu "On-chip Peripheral Drivers"
config BSP_UART_USING_DMA_RX
bool "Enable UART RX DMA support"
default y
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
select RT_USING_SPI
...
...
@@ -112,6 +120,35 @@ menu "On-chip Peripheral Drivers"
default 117
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
config BSP_USING_ADC3
bool "Enable ADC3"
default n
endif
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f429-atk-apollo/board/SConscript
浏览文件 @
92338d50
...
...
@@ -15,6 +15,11 @@ if GetDepend(['BSP_USING_SPI_FLASH']):
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
path
+=
[
cwd
+
'/ports'
]
if
GetDepend
([
'BSP_USING_SDRAM'
]):
path
+=
[
cwd
+
'/ports'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
cwd
+
'/../../libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s'
]
...
...
bsp/stm32/stm32f429-atk-apollo/board/board.h
浏览文件 @
92338d50
...
...
@@ -22,6 +22,10 @@
#define STM32_SRAM_SIZE (192)
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern
int
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
...
...
bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern
const
struct
fal_flash_dev
stm32_onchip_flash
;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 1008 * 1024, 0},\
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 1008* 1024 , 16 * 1024, 0},\
}
#endif
/* FAL_PART_HAS_TABLE_CFG */
#endif
/* _FAL_CFG_H_ */
bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 16
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 9
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 13
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 3
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 1
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_COUNT ((uint32_t)0x02AB)
#define SDRAM_SIZE ((uint32_t)0x2000000)
/* Timing configuration for W9825G6KH-6 */
/* 90 MHz of SD clock frequency (180MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 7x11.90ns */
#define EXITSELFREFRESHDELAY 8
/* TRAS: 4x11.90ns */
#define SELFREFRESHTIME 6
/* TRC: 7x11.90ns */
#define ROWCYCLEDELAY 6
/* TWR: 2 Clock cycles */
#define WRITERECOVERYTIME 2
/* TRP: 2x11.90ns */
#define RPDELAY 2
/* TRCD: 2x11.90ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif
bsp/stm32/stm32f429-atk-apollo/rtconfig.h
浏览文件 @
92338d50
...
...
@@ -13,6 +13,7 @@
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_DEBUG
...
...
@@ -29,7 +30,7 @@
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_
SMALL_MEM
#define RT_USING_
MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
...
...
@@ -153,6 +154,12 @@
/* example package: hello */
/* Privated Packages of RealThread */
/* Network Utilities */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F4
...
...
@@ -169,7 +176,7 @@
#define BSP_USING_GPIO
#define BSP_USING_UART1
/*
Offboard Peripheral
Drivers */
/*
Board extended module
Drivers */
#endif
bsp/stm32/stm32f429-fire-challenger/.config
浏览文件 @
92338d50
...
...
@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX
=
8
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE
=
4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32
=
y
...
...
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND
=
1000
CONFIG_RT_USING_OVERFLOW_CHECK
=
y
CONFIG_RT_USING_HOOK
=
y
CONFIG_RT_USING_IDLE_HOOK
=
y
CONFIG_RT_IDEL_HOOK_LIST_SIZE
=
4
CONFIG_IDLE_THREAD_STACK_SIZE
=
1024
# CONFIG_RT_USING_TIMER_SOFT is not set
...
...
@@ -44,11 +46,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL
=
y
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_MEMHEAP
=
y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM
=
y
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP
=
y
CONFIG_RT_USING_HEAP
=
y
#
...
...
@@ -63,6 +65,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_ARCH_ARM
=
y
CONFIG_ARCH_ARM_CORTEX_M
=
y
CONFIG_ARCH_ARM_CORTEX_M4
=
y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
...
...
@@ -112,10 +115,12 @@ CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
...
...
@@ -173,6 +178,7 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
#
# ARM CMSIS
...
...
@@ -317,6 +323,25 @@ CONFIG_RT_USING_PIN=y
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
CONFIG_SOC_FAMILY_STM32
=
y
CONFIG_SOC_SERIES_STM32F4
=
y
...
...
@@ -330,6 +355,7 @@ CONFIG_SOC_STM32F429IG=y
#
CONFIG_BSP_USING_USB_TO_USART
=
y
# CONFIG_BSP_USING_RS232 is not set
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_MPU6050 is not set
# CONFIG_BSP_USING_ETH is not set
...
...
@@ -349,5 +375,5 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_I2C1 is not set
#
#
Offboard Peripheral
Drivers
#
Board extended module
Drivers
#
bsp/stm32/stm32f429-fire-challenger/README.md
浏览文件 @
92338d50
...
...
@@ -42,23 +42,26 @@
| USB 转串口 | 支持 | |
| RS232 | 支持 | 与以太网有引脚冲突 |
| SPI Flash | 支持 | |
| 电位器 | 支持 | 使用 ADC1 |
| 以太网 | 支持 | |
| MPU6050六轴传感器 | 支持 | |
| SDRAM | 支持 | |
| SD卡 | 即将支持 | |
| CAN | 即将支持 | |
| SDRAM | 即将支持 | |
| EMW1062 | 暂不支持 | |
|
**片上外设**
|
**支持情况**
|
**备注**
|
| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
| UART | 支持 | UART1/2/3 |
| SPI | 支持 | SPI1/2/5 |
| I2C | 支持 | 软件 I2C |
| ADC | 支持 | |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 支持 | 已适配
[
FAL
](
https://github.com/RT-Thread-packages/fal
)
|
| SDIO | 暂不支持 | 即将支持 |
| RTC | 暂不支持 | 即将支持 |
| PWM | 暂不支持 | 即将支持 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
| IWG | 暂不支持 | 即将支持 |
|
**扩展模块**
|
**支持情况**
|
**备注**
|
| 暂无 | 暂不支持 | 暂不支持 |
...
...
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/.mxproject
浏览文件 @
92338d50
[PreviousGenFiles]
HeaderPath=
F:
/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc
HeaderPath=
E:/workspace
/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc
HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h;
SourcePath=
F:
/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src
SourcePath=
E:/workspace
/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src
SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedIarFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null;
HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedKeilFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_
eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null
;
SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_
adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config//MDK-ARM/startup_stm32f429xx.s
;
HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc
浏览文件 @
92338d50
#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_13
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC1.master=1
ETH.IPParameters=MediaInterface
ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=ETH
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=SPI5
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IPNb=6
Mcu.IP0=ADC1
Mcu.IP1=ETH
Mcu.IP2=FMC
Mcu.IP3=IWDG
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RTC
Mcu.IP7=SPI5
Mcu.IP8=SYS
Mcu.IP9=USART1
Mcu.IPNb=10
Mcu.Name=STM32F429I(E-G)Tx
Mcu.Package=LQFP176
Mcu.Pin0=PC14/OSC32_IN
Mcu.Pin1=PC15/OSC32_OUT
Mcu.Pin10=PA7
Mcu.Pin11=PC4
Mcu.Pin12=PC5
Mcu.Pin13=PB11
Mcu.Pin14=PA9
Mcu.Pin15=PA10
Mcu.Pin16=PA13
Mcu.Pin17=PA14
Mcu.Pin18=PG13
Mcu.Pin19=PG14
Mcu.Pin2=PF7
Mcu.Pin20=VP_SYS_VS_Systick
Mcu.Pin3=PF8
Mcu.Pin4=PF9
Mcu.Pin5=PH0/OSC_IN
Mcu.Pin6=PH1/OSC_OUT
Mcu.Pin7=PC1
Mcu.Pin8=PA1
Mcu.Pin9=PA2
Mcu.PinsNb=21
Mcu.Pin10=PF9
Mcu.Pin11=PH0/OSC_IN
Mcu.Pin12=PH1/OSC_OUT
Mcu.Pin13=PC0
Mcu.Pin14=PC1
Mcu.Pin15=PC3
Mcu.Pin16=PA1
Mcu.Pin17=PA2
Mcu.Pin18=PA7
Mcu.Pin19=PC4
Mcu.Pin2=PF0
Mcu.Pin20=PC5
Mcu.Pin21=PF11
Mcu.Pin22=PF12
Mcu.Pin23=PF13
Mcu.Pin24=PF14
Mcu.Pin25=PF15
Mcu.Pin26=PG0
Mcu.Pin27=PG1
Mcu.Pin28=PE7
Mcu.Pin29=PE8
Mcu.Pin3=PF1
Mcu.Pin30=PE9
Mcu.Pin31=PE10
Mcu.Pin32=PE11
Mcu.Pin33=PE12
Mcu.Pin34=PE13
Mcu.Pin35=PE14
Mcu.Pin36=PE15
Mcu.Pin37=PB11
Mcu.Pin38=PH6
Mcu.Pin39=PH7
Mcu.Pin4=PF2
Mcu.Pin40=PD8
Mcu.Pin41=PD9
Mcu.Pin42=PD10
Mcu.Pin43=PD14
Mcu.Pin44=PD15
Mcu.Pin45=PG4
Mcu.Pin46=PG5
Mcu.Pin47=PG8
Mcu.Pin48=PA9
Mcu.Pin49=PA10
Mcu.Pin5=PF3
Mcu.Pin50=PA13
Mcu.Pin51=PA14
Mcu.Pin52=PD0
Mcu.Pin53=PD1
Mcu.Pin54=PG13
Mcu.Pin55=PG14
Mcu.Pin56=PG15
Mcu.Pin57=PE0
Mcu.Pin58=PE1
Mcu.Pin59=VP_IWDG_VS_IWDG
Mcu.Pin6=PF4
Mcu.Pin60=VP_RTC_VS_RTC_Activate
Mcu.Pin61=VP_SYS_VS_Systick
Mcu.Pin7=PF5
Mcu.Pin8=PF7
Mcu.Pin9=PF8
Mcu.PinsNb=62
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F429IGTx
...
...
@@ -67,12 +118,15 @@ PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB11.Mode=RMII
PB11.Signal=ETH_TX_EN
PC0.Signal=FMC_SDNWE
PC1.Mode=RMII
PC1.Signal=ETH_MDC
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC3.Locked=true
PC3.Signal=ADCx_IN13
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
...
...
@@ -85,6 +139,35 @@ PCC.Seq0=0
PCC.Series=STM32F4
PCC.Temperature=25
PCC.Vdd=null
PD0.Signal=FMC_D2_DA2
PD1.Signal=FMC_D3_DA3
PD10.Signal=FMC_D15_DA15
PD14.Signal=FMC_D0_DA0
PD15.Signal=FMC_D1_DA1
PD8.Signal=FMC_D13_DA13
PD9.Signal=FMC_D14_DA14
PE0.Signal=FMC_NBL0
PE1.Signal=FMC_NBL1
PE10.Signal=FMC_D7_DA7
PE11.Signal=FMC_D8_DA8
PE12.Signal=FMC_D9_DA9
PE13.Signal=FMC_D10_DA10
PE14.Signal=FMC_D11_DA11
PE15.Signal=FMC_D12_DA12
PE7.Signal=FMC_D4_DA4
PE8.Signal=FMC_D5_DA5
PE9.Signal=FMC_D6_DA6
PF0.Signal=FMC_A0
PF1.Signal=FMC_A1
PF11.Signal=FMC_SDNRAS
PF12.Signal=FMC_A6
PF13.Signal=FMC_A7
PF14.Signal=FMC_A8
PF15.Signal=FMC_A9
PF2.Signal=FMC_A2
PF3.Signal=FMC_A3
PF4.Signal=FMC_A4
PF5.Signal=FMC_A5
PF7.Locked=true
PF7.Mode=Full_Duplex_Master
PF7.Signal=SPI5_SCK
...
...
@@ -93,16 +176,26 @@ PF8.Mode=Full_Duplex_Master
PF8.Signal=SPI5_MISO
PF9.Mode=Full_Duplex_Master
PF9.Signal=SPI5_MOSI
PG0.Signal=FMC_A10
PG1.Signal=FMC_A11
PG13.Locked=true
PG13.Mode=RMII
PG13.Signal=ETH_TXD0
PG14.Locked=true
PG14.Mode=RMII
PG14.Signal=ETH_TXD1
PG15.Signal=FMC_SDNCAS
PG4.Signal=FMC_A14_BA0
PG5.Signal=FMC_A15_BA1
PG8.Signal=FMC_SDCLK
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
PH1/OSC_OUT.Signal=RCC_OSC_OUT
PH6.Mode=SdramChipSelect2_1
PH6.Signal=FMC_SDNE1
PH7.Mode=SdramChipSelect2_1
PH7.Signal=FMC_SDCKE1
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
...
...
@@ -118,7 +211,7 @@ ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=
tru
e
ProjectManager.LastFirmware=
fals
e
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
...
...
@@ -130,7 +223,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_SPI5_Init-SPI5-false-HAL-true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_SPI5_Init-SPI5-false-HAL-true
,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true
RCC.48MHZClocksFreq_Value=90000000
RCC.AHBFreq_Value=180000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
...
...
@@ -147,7 +240,7 @@ RCC.HCLKFreq_Value=180000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=160000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,R
CC_RTC_Clock_Source,R
TCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
RCC.LCDTFTFreq_Value=20416666.666666668
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=180000000
...
...
@@ -156,7 +249,8 @@ RCC.PLLM=15
RCC.PLLN=216
RCC.PLLQCLKFreq_Value=90000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCFreq_Value=32000
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=12500000
RCC.SAI_AClocksFreq_Value=20416666.666666668
RCC.SAI_BClocksFreq_Value=20416666.666666668
...
...
@@ -170,6 +264,80 @@ RCC.VCOSAIOutputFreq_ValueQ=20416666.666666668
RCC.VCOSAIOutputFreq_ValueR=40833333.333333336
RCC.VcooutputI2S=160000000
RCC.VcooutputI2SQ=160000000
SH.ADCx_IN13.0=ADC1_IN13,IN13
SH.ADCx_IN13.ConfNb=1
SH.FMC_A0.0=FMC_A0,12b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,12b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,12b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,12b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,12b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,12b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,12b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,12b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,12b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,12b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,12b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,12b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
SH.FMC_NBL0.ConfNb=1
SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
SH.FMC_NBL1.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
SH.FMC_SDNWE.ConfNb=1
SPI5.CalculateBaudRate=45.0 MBits/s
SPI5.Direction=SPI_DIRECTION_2LINES
SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
...
...
@@ -177,6 +345,10 @@ SPI5.Mode=SPI_MODE_MASTER
SPI5.VirtualType=VM_MASTER
USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
浏览文件 @
92338d50
...
...
@@ -49,7 +49,7 @@
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
...
...
@@ -62,14 +62,14 @@
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
...
...
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c
浏览文件 @
92338d50
...
...
@@ -62,12 +62,20 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef
hadc1
;
ETH_HandleTypeDef
heth
;
IWDG_HandleTypeDef
hiwdg
;
RTC_HandleTypeDef
hrtc
;
SPI_HandleTypeDef
hspi5
;
UART_HandleTypeDef
huart1
;
SDRAM_HandleTypeDef
hsdram1
;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
...
...
@@ -78,6 +86,10 @@ static void MX_GPIO_Init(void);
static
void
MX_USART1_UART_Init
(
void
);
static
void
MX_ETH_Init
(
void
);
static
void
MX_SPI5_Init
(
void
);
static
void
MX_FMC_Init
(
void
);
static
void
MX_ADC1_Init
(
void
);
static
void
MX_RTC_Init
(
void
);
static
void
MX_IWDG_Init
(
void
);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
...
...
@@ -118,6 +130,10 @@ int main(void)
MX_USART1_UART_Init
();
MX_ETH_Init
();
MX_SPI5_Init
();
MX_FMC_Init
();
MX_ADC1_Init
();
MX_RTC_Init
();
MX_IWDG_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
...
...
@@ -141,6 +157,7 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
=
{
0
};
/**Configure the main internal regulator output voltage
*/
...
...
@@ -148,8 +165,11 @@ void SystemClock_Config(void)
__HAL_PWR_VOLTAGESCALING_CONFIG
(
PWR_REGULATOR_VOLTAGE_SCALE1
);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_LSI
|
RCC_OSCILLATORTYPE_HSE
|
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
RCC_OscInitStruct
.
LSIState
=
RCC_LSI_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
15
;
...
...
@@ -179,6 +199,62 @@ void SystemClock_Config(void)
{
Error_Handler
();
}
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_ADC1_Init
(
void
)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef
sConfig
=
{
0
};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/**Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1
.
Instance
=
ADC1
;
hadc1
.
Init
.
ClockPrescaler
=
ADC_CLOCK_SYNC_PCLK_DIV4
;
hadc1
.
Init
.
Resolution
=
ADC_RESOLUTION_12B
;
hadc1
.
Init
.
ScanConvMode
=
DISABLE
;
hadc1
.
Init
.
ContinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
DiscontinuousConvMode
=
DISABLE
;
hadc1
.
Init
.
ExternalTrigConvEdge
=
ADC_EXTERNALTRIGCONVEDGE_NONE
;
hadc1
.
Init
.
ExternalTrigConv
=
ADC_SOFTWARE_START
;
hadc1
.
Init
.
DataAlign
=
ADC_DATAALIGN_RIGHT
;
hadc1
.
Init
.
NbrOfConversion
=
1
;
hadc1
.
Init
.
DMAContinuousRequests
=
DISABLE
;
hadc1
.
Init
.
EOCSelection
=
ADC_EOC_SINGLE_CONV
;
if
(
HAL_ADC_Init
(
&
hadc1
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig
.
Channel
=
ADC_CHANNEL_13
;
sConfig
.
Rank
=
1
;
sConfig
.
SamplingTime
=
ADC_SAMPLETIME_3CYCLES
;
if
(
HAL_ADC_ConfigChannel
(
&
hadc1
,
&
sConfig
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
...
...
@@ -226,6 +302,68 @@ static void MX_ETH_Init(void)
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static
void
MX_IWDG_Init
(
void
)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_4
;
hiwdg
.
Init
.
Reload
=
4095
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static
void
MX_RTC_Init
(
void
)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/**Initialize RTC Only
*/
hrtc
.
Instance
=
RTC
;
hrtc
.
Init
.
HourFormat
=
RTC_HOURFORMAT_24
;
hrtc
.
Init
.
AsynchPrediv
=
127
;
hrtc
.
Init
.
SynchPrediv
=
255
;
hrtc
.
Init
.
OutPut
=
RTC_OUTPUT_DISABLE
;
hrtc
.
Init
.
OutPutPolarity
=
RTC_OUTPUT_POLARITY_HIGH
;
hrtc
.
Init
.
OutPutType
=
RTC_OUTPUT_TYPE_OPENDRAIN
;
if
(
HAL_RTC_Init
(
&
hrtc
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
* @brief SPI5 Initialization Function
* @param None
...
...
@@ -297,6 +435,41 @@ static void MX_USART1_UART_Init(void)
}
/* FMC initialization function */
static
void
MX_FMC_Init
(
void
)
{
FMC_SDRAM_TimingTypeDef
SdramTiming
;
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1
.
Instance
=
FMC_SDRAM_DEVICE
;
/* hsdram1.Init */
hsdram1
.
Init
.
SDBank
=
FMC_SDRAM_BANK2
;
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_8
;
hsdram1
.
Init
.
RowBitsNumber
=
FMC_SDRAM_ROW_BITS_NUM_12
;
hsdram1
.
Init
.
MemoryDataWidth
=
FMC_SDRAM_MEM_BUS_WIDTH_16
;
hsdram1
.
Init
.
InternalBankNumber
=
FMC_SDRAM_INTERN_BANKS_NUM_4
;
hsdram1
.
Init
.
CASLatency
=
FMC_SDRAM_CAS_LATENCY_1
;
hsdram1
.
Init
.
WriteProtection
=
FMC_SDRAM_WRITE_PROTECTION_DISABLE
;
hsdram1
.
Init
.
SDClockPeriod
=
FMC_SDRAM_CLOCK_DISABLE
;
hsdram1
.
Init
.
ReadBurst
=
FMC_SDRAM_RBURST_DISABLE
;
hsdram1
.
Init
.
ReadPipeDelay
=
FMC_SDRAM_RPIPE_DELAY_0
;
/* SdramTiming */
SdramTiming
.
LoadToActiveDelay
=
16
;
SdramTiming
.
ExitSelfRefreshDelay
=
16
;
SdramTiming
.
SelfRefreshTime
=
16
;
SdramTiming
.
RowCycleDelay
=
16
;
SdramTiming
.
WriteRecoveryTime
=
16
;
SdramTiming
.
RPDelay
=
16
;
SdramTiming
.
RCDDelay
=
16
;
if
(
HAL_SDRAM_Init
(
&
hsdram1
,
&
SdramTiming
)
!=
HAL_OK
)
{
Error_Handler
(
);
}
}
/**
* @brief GPIO Initialization Function
* @param None
...
...
@@ -310,8 +483,10 @@ static void MX_GPIO_Init(void)
__HAL_RCC_GPIOF_CLK_ENABLE
();
__HAL_RCC_GPIOH_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
__HAL_RCC_GPIOE_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOD_CLK_ENABLE
();
}
...
...
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
浏览文件 @
92338d50
...
...
@@ -97,6 +97,70 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspInit
(
ADC_HandleTypeDef
*
hadc
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE
();
__HAL_RCC_GPIOC_CLK_ENABLE
();
/**ADC1 GPIO Configuration
PC3 ------> ADC1_IN13
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_3
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_ANALOG
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
HAL_GPIO_Init
(
GPIOC
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void
HAL_ADC_MspDeInit
(
ADC_HandleTypeDef
*
hadc
)
{
if
(
hadc
->
Instance
==
ADC1
)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE
();
/**ADC1 GPIO Configuration
PC3 ------> ADC1_IN13
*/
HAL_GPIO_DeInit
(
GPIOC
,
GPIO_PIN_3
);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief ETH MSP Initialization
* This function configures the hardware resources used in this example
...
...
@@ -209,6 +273,53 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
}
/**
* @brief RTC MSP Initialization
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE
();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
/**
* @brief RTC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void
HAL_RTC_MspDeInit
(
RTC_HandleTypeDef
*
hrtc
)
{
if
(
hrtc
->
Instance
==
RTC
)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE
();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
...
...
@@ -352,6 +463,209 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
}
static
uint32_t
FMC_Initialized
=
0
;
static
void
HAL_FMC_MspInit
(
void
){
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef
GPIO_InitStruct
;
if
(
FMC_Initialized
)
{
return
;
}
FMC_Initialized
=
1
;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE
();
/** FMC GPIO Configuration
PF0 ------> FMC_A0
PF1 ------> FMC_A1
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PC0 ------> FMC_SDNWE
PF11 ------> FMC_SDNRAS
PF12 ------> FMC_A6
PF13 ------> FMC_A7
PF14 ------> FMC_A8
PF15 ------> FMC_A9
PG0 ------> FMC_A10
PG1 ------> FMC_A11
PE7 ------> FMC_D4
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE10 ------> FMC_D7
PE11 ------> FMC_D8
PE12 ------> FMC_D9
PE13 ------> FMC_D10
PE14 ------> FMC_D11
PE15 ------> FMC_D12
PH6 ------> FMC_SDNE1
PH7 ------> FMC_SDCKE1
PD8 ------> FMC_D13
PD9 ------> FMC_D14
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD15 ------> FMC_D1
PG4 ------> FMC_BA0
PG5 ------> FMC_BA1
PG8 ------> FMC_SDCLK
PD0 ------> FMC_D2
PD1 ------> FMC_D3
PG15 ------> FMC_SDNCAS
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_3
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOF
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_0
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOC
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_8
|
GPIO_PIN_15
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOG
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_7
|
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOE
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_6
|
GPIO_PIN_7
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOH
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF12_FMC
;
HAL_GPIO_Init
(
GPIOD
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
void
HAL_SDRAM_MspInit
(
SDRAM_HandleTypeDef
*
hsdram
){
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit
();
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
static
uint32_t
FMC_DeInitialized
=
0
;
static
void
HAL_FMC_MspDeInit
(
void
){
/* USER CODE BEGIN FMC_MspDeInit 0 */
/* USER CODE END FMC_MspDeInit 0 */
if
(
FMC_DeInitialized
)
{
return
;
}
FMC_DeInitialized
=
1
;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_DISABLE
();
/** FMC GPIO Configuration
PF0 ------> FMC_A0
PF1 ------> FMC_A1
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PC0 ------> FMC_SDNWE
PF11 ------> FMC_SDNRAS
PF12 ------> FMC_A6
PF13 ------> FMC_A7
PF14 ------> FMC_A8
PF15 ------> FMC_A9
PG0 ------> FMC_A10
PG1 ------> FMC_A11
PE7 ------> FMC_D4
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE10 ------> FMC_D7
PE11 ------> FMC_D8
PE12 ------> FMC_D9
PE13 ------> FMC_D10
PE14 ------> FMC_D11
PE15 ------> FMC_D12
PH6 ------> FMC_SDNE1
PH7 ------> FMC_SDCKE1
PD8 ------> FMC_D13
PD9 ------> FMC_D14
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD15 ------> FMC_D1
PG4 ------> FMC_BA0
PG5 ------> FMC_BA1
PG8 ------> FMC_SDCLK
PD0 ------> FMC_D2
PD1 ------> FMC_D3
PG15 ------> FMC_SDNCAS
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
HAL_GPIO_DeInit
(
GPIOF
,
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_3
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
);
HAL_GPIO_DeInit
(
GPIOC
,
GPIO_PIN_0
);
HAL_GPIO_DeInit
(
GPIOG
,
GPIO_PIN_0
|
GPIO_PIN_1
|
GPIO_PIN_4
|
GPIO_PIN_5
|
GPIO_PIN_8
|
GPIO_PIN_15
);
HAL_GPIO_DeInit
(
GPIOE
,
GPIO_PIN_7
|
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_11
|
GPIO_PIN_12
|
GPIO_PIN_13
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
);
HAL_GPIO_DeInit
(
GPIOH
,
GPIO_PIN_6
|
GPIO_PIN_7
);
HAL_GPIO_DeInit
(
GPIOD
,
GPIO_PIN_8
|
GPIO_PIN_9
|
GPIO_PIN_10
|
GPIO_PIN_14
|
GPIO_PIN_15
|
GPIO_PIN_0
|
GPIO_PIN_1
);
/* USER CODE BEGIN FMC_MspDeInit 1 */
/* USER CODE END FMC_MspDeInit 1 */
}
void
HAL_SDRAM_MspDeInit
(
SDRAM_HandleTypeDef
*
hsdram
){
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
/* USER CODE END SDRAM_MspDeInit 0 */
HAL_FMC_MspDeInit
();
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
/* USER CODE END SDRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
...
...
bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/system_stm32f4xx.c
0 → 100644
浏览文件 @
92338d50
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000)
/*!< Default value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
/* #define DATA_IN_ExtSRAM */
#endif
/* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00
/*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t
SystemCoreClock
=
16000000
;
const
uint8_t
AHBPrescTable
[
16
]
=
{
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
,
6
,
7
,
8
,
9
};
const
uint8_t
APBPrescTable
[
8
]
=
{
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static
void
SystemInit_ExtMemCtl
(
void
);
#endif
/* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void
SystemInit
(
void
)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB
->
CPACR
|=
((
3UL
<<
10
*
2
)
|
(
3UL
<<
11
*
2
));
/* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC
->
CR
|=
(
uint32_t
)
0x00000001
;
/* Reset CFGR register */
RCC
->
CFGR
=
0x00000000
;
/* Reset HSEON, CSSON and PLLON bits */
RCC
->
CR
&=
(
uint32_t
)
0xFEF6FFFF
;
/* Reset PLLCFGR register */
RCC
->
PLLCFGR
=
0x24003010
;
/* Reset HSEBYP bit */
RCC
->
CR
&=
(
uint32_t
)
0xFFFBFFFF
;
/* Disable all interrupts */
RCC
->
CIR
=
0x00000000
;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl
();
#endif
/* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB
->
VTOR
=
SRAM_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal SRAM */
#else
SCB
->
VTOR
=
FLASH_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void
SystemCoreClockUpdate
(
void
)
{
uint32_t
tmp
=
0
,
pllvco
=
0
,
pllp
=
2
,
pllsource
=
0
,
pllm
=
2
;
/* Get SYSCLK source -------------------------------------------------------*/
tmp
=
RCC
->
CFGR
&
RCC_CFGR_SWS
;
switch
(
tmp
)
{
case
0x00
:
/* HSI used as system clock source */
SystemCoreClock
=
HSI_VALUE
;
break
;
case
0x04
:
/* HSE used as system clock source */
SystemCoreClock
=
HSE_VALUE
;
break
;
case
0x08
:
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource
=
(
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLSRC
)
>>
22
;
pllm
=
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLM
;
if
(
pllsource
!=
0
)
{
/* HSE used as PLL clock source */
pllvco
=
(
HSE_VALUE
/
pllm
)
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
6
);
}
else
{
/* HSI used as PLL clock source */
pllvco
=
(
HSI_VALUE
/
pllm
)
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
6
);
}
pllp
=
(((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLP
)
>>
16
)
+
1
)
*
2
;
SystemCoreClock
=
pllvco
/
pllp
;
break
;
default:
SystemCoreClock
=
HSI_VALUE
;
break
;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp
=
AHBPrescTable
[((
RCC
->
CFGR
&
RCC_CFGR_HPRE
)
>>
4
)];
/* HCLK frequency */
SystemCoreClock
>>=
tmp
;
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void
SystemInit_ExtMemCtl
(
void
)
{
__IO
uint32_t
tmp
=
0x00
;
register
uint32_t
tmpreg
=
0
,
timeout
=
0xFFFF
;
register
__IO
uint32_t
index
;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
RCC
->
AHB1ENR
|=
0x000001F8
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB1ENR
,
RCC_AHB1ENR_GPIOCEN
);
/* Connect PDx pins to FMC Alternate function */
GPIOD
->
AFR
[
0
]
=
0x00CCC0CC
;
GPIOD
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PDx pins in Alternate function mode */
GPIOD
->
MODER
=
0xAAAA0A8A
;
/* Configure PDx pins speed to 100 MHz */
GPIOD
->
OSPEEDR
=
0xFFFF0FCF
;
/* Configure PDx pins Output type to push-pull */
GPIOD
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOD
->
PUPDR
=
0x00000000
;
/* Connect PEx pins to FMC Alternate function */
GPIOE
->
AFR
[
0
]
=
0xC00CC0CC
;
GPIOE
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PEx pins in Alternate function mode */
GPIOE
->
MODER
=
0xAAAA828A
;
/* Configure PEx pins speed to 100 MHz */
GPIOE
->
OSPEEDR
=
0xFFFFC3CF
;
/* Configure PEx pins Output type to push-pull */
GPIOE
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PEx pins */
GPIOE
->
PUPDR
=
0x00000000
;
/* Connect PFx pins to FMC Alternate function */
GPIOF
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOF
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PFx pins in Alternate function mode */
GPIOF
->
MODER
=
0xAA800AAA
;
/* Configure PFx pins speed to 50 MHz */
GPIOF
->
OSPEEDR
=
0xAA800AAA
;
/* Configure PFx pins Output type to push-pull */
GPIOF
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PFx pins */
GPIOF
->
PUPDR
=
0x00000000
;
/* Connect PGx pins to FMC Alternate function */
GPIOG
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOG
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PGx pins in Alternate function mode */
GPIOG
->
MODER
=
0xAAAAAAAA
;
/* Configure PGx pins speed to 50 MHz */
GPIOG
->
OSPEEDR
=
0xAAAAAAAA
;
/* Configure PGx pins Output type to push-pull */
GPIOG
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PGx pins */
GPIOG
->
PUPDR
=
0x00000000
;
/* Connect PHx pins to FMC Alternate function */
GPIOH
->
AFR
[
0
]
=
0x00C0CC00
;
GPIOH
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PHx pins in Alternate function mode */
GPIOH
->
MODER
=
0xAAAA08A0
;
/* Configure PHx pins speed to 50 MHz */
GPIOH
->
OSPEEDR
=
0xAAAA08A0
;
/* Configure PHx pins Output type to push-pull */
GPIOH
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PHx pins */
GPIOH
->
PUPDR
=
0x00000000
;
/* Connect PIx pins to FMC Alternate function */
GPIOI
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOI
->
AFR
[
1
]
=
0x00000CC0
;
/* Configure PIx pins in Alternate function mode */
GPIOI
->
MODER
=
0x0028AAAA
;
/* Configure PIx pins speed to 50 MHz */
GPIOI
->
OSPEEDR
=
0x0028AAAA
;
/* Configure PIx pins Output type to push-pull */
GPIOI
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PIx pins */
GPIOI
->
PUPDR
=
0x00000000
;
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC
->
AHB3ENR
|=
0x00000001
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
FMC_Bank5_6
->
SDCR
[
0
]
=
0x000019E4
;
FMC_Bank5_6
->
SDTR
[
0
]
=
0x01115351
;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6
->
SDCMR
=
0x00000011
;
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Delay */
for
(
index
=
0
;
index
<
1000
;
index
++
);
/* PALL command */
FMC_Bank5_6
->
SDCMR
=
0x00000012
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Auto refresh command */
FMC_Bank5_6
->
SDCMR
=
0x00000073
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* MRD register program */
FMC_Bank5_6
->
SDCMR
=
0x00046014
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Set refresh count */
tmpreg
=
FMC_Bank5_6
->
SDRTR
;
FMC_Bank5_6
->
SDRTR
=
(
tmpreg
|
(
0x0000027C
<<
1
));
/* Disable write protection */
tmpreg
=
FMC_Bank5_6
->
SDCR
[
0
];
FMC_Bank5_6
->
SDCR
[
0
]
=
(
tmpreg
&
0xFFFFFDFF
);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001011
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00000201
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001091
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00110212
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F469xx || STM32F479xx */
(
void
)(
tmp
);
}
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void
SystemInit_ExtMemCtl
(
void
)
{
__IO
uint32_t
tmp
=
0x00
;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register
uint32_t
tmpreg
=
0
,
timeout
=
0xFFFF
;
register
__IO
uint32_t
index
;
#if defined(STM32F446xx)
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
clock */
RCC
->
AHB1ENR
|=
0x0000007D
;
#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC
->
AHB1ENR
|=
0x000001F8
;
#endif
/* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB1ENR
,
RCC_AHB1ENR_GPIOCEN
);
#if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */
GPIOA
->
AFR
[
0
]
|=
0xC0000000
;
GPIOA
->
AFR
[
1
]
|=
0x00000000
;
/* Configure PDx pins in Alternate function mode */
GPIOA
->
MODER
|=
0x00008000
;
/* Configure PDx pins speed to 50 MHz */
GPIOA
->
OSPEEDR
|=
0x00008000
;
/* Configure PDx pins Output type to push-pull */
GPIOA
->
OTYPER
|=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOA
->
PUPDR
|=
0x00000000
;
/* Connect PCx pins to FMC Alternate function */
GPIOC
->
AFR
[
0
]
|=
0x00CC0000
;
GPIOC
->
AFR
[
1
]
|=
0x00000000
;
/* Configure PDx pins in Alternate function mode */
GPIOC
->
MODER
|=
0x00000A00
;
/* Configure PDx pins speed to 50 MHz */
GPIOC
->
OSPEEDR
|=
0x00000A00
;
/* Configure PDx pins Output type to push-pull */
GPIOC
->
OTYPER
|=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOC
->
PUPDR
|=
0x00000000
;
#endif
/* STM32F446xx */
/* Connect PDx pins to FMC Alternate function */
GPIOD
->
AFR
[
0
]
=
0x000000CC
;
GPIOD
->
AFR
[
1
]
=
0xCC000CCC
;
/* Configure PDx pins in Alternate function mode */
GPIOD
->
MODER
=
0xA02A000A
;
/* Configure PDx pins speed to 50 MHz */
GPIOD
->
OSPEEDR
=
0xA02A000A
;
/* Configure PDx pins Output type to push-pull */
GPIOD
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOD
->
PUPDR
=
0x00000000
;
/* Connect PEx pins to FMC Alternate function */
GPIOE
->
AFR
[
0
]
=
0xC00000CC
;
GPIOE
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PEx pins in Alternate function mode */
GPIOE
->
MODER
=
0xAAAA800A
;
/* Configure PEx pins speed to 50 MHz */
GPIOE
->
OSPEEDR
=
0xAAAA800A
;
/* Configure PEx pins Output type to push-pull */
GPIOE
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PEx pins */
GPIOE
->
PUPDR
=
0x00000000
;
/* Connect PFx pins to FMC Alternate function */
GPIOF
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOF
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PFx pins in Alternate function mode */
GPIOF
->
MODER
=
0xAA800AAA
;
/* Configure PFx pins speed to 50 MHz */
GPIOF
->
OSPEEDR
=
0xAA800AAA
;
/* Configure PFx pins Output type to push-pull */
GPIOF
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PFx pins */
GPIOF
->
PUPDR
=
0x00000000
;
/* Connect PGx pins to FMC Alternate function */
GPIOG
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOG
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PGx pins in Alternate function mode */
GPIOG
->
MODER
=
0xAAAAAAAA
;
/* Configure PGx pins speed to 50 MHz */
GPIOG
->
OSPEEDR
=
0xAAAAAAAA
;
/* Configure PGx pins Output type to push-pull */
GPIOG
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PGx pins */
GPIOG
->
PUPDR
=
0x00000000
;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH
->
AFR
[
0
]
=
0x00C0CC00
;
GPIOH
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PHx pins in Alternate function mode */
GPIOH
->
MODER
=
0xAAAA08A0
;
/* Configure PHx pins speed to 50 MHz */
GPIOH
->
OSPEEDR
=
0xAAAA08A0
;
/* Configure PHx pins Output type to push-pull */
GPIOH
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PHx pins */
GPIOH
->
PUPDR
=
0x00000000
;
/* Connect PIx pins to FMC Alternate function */
GPIOI
->
AFR
[
0
]
=
0xCCCCCCCC
;
GPIOI
->
AFR
[
1
]
=
0x00000CC0
;
/* Configure PIx pins in Alternate function mode */
GPIOI
->
MODER
=
0x0028AAAA
;
/* Configure PIx pins speed to 50 MHz */
GPIOI
->
OSPEEDR
=
0x0028AAAA
;
/* Configure PIx pins Output type to push-pull */
GPIOI
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PIx pins */
GPIOI
->
PUPDR
=
0x00000000
;
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC
->
AHB3ENR
|=
0x00000001
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
/* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDCR
[
0
]
=
0x00001954
;
#else
FMC_Bank5_6
->
SDCR
[
0
]
=
0x000019E4
;
#endif
/* STM32F446xx */
FMC_Bank5_6
->
SDTR
[
0
]
=
0x01115351
;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6
->
SDCMR
=
0x00000011
;
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Delay */
for
(
index
=
0
;
index
<
1000
;
index
++
);
/* PALL command */
FMC_Bank5_6
->
SDCMR
=
0x00000012
;
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Auto refresh command */
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDCMR
=
0x000000F3
;
#else
FMC_Bank5_6
->
SDCMR
=
0x00000073
;
#endif
/* STM32F446xx */
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* MRD register program */
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDCMR
=
0x00044014
;
#else
FMC_Bank5_6
->
SDCMR
=
0x00046014
;
#endif
/* STM32F446xx */
timeout
=
0xFFFF
;
while
((
tmpreg
!=
0
)
&&
(
timeout
--
>
0
))
{
tmpreg
=
FMC_Bank5_6
->
SDSR
&
0x00000020
;
}
/* Set refresh count */
tmpreg
=
FMC_Bank5_6
->
SDRTR
;
#if defined(STM32F446xx)
FMC_Bank5_6
->
SDRTR
=
(
tmpreg
|
(
0x0000050C
<<
1
));
#else
FMC_Bank5_6
->
SDRTR
=
(
tmpreg
|
(
0x0000027C
<<
1
));
#endif
/* STM32F446xx */
/* Disable write protection */
tmpreg
=
FMC_Bank5_6
->
SDCR
[
0
];
FMC_Bank5_6
->
SDCR
[
0
]
=
(
tmpreg
&
0xFFFFFDFF
);
#endif
/* DATA_IN_ExtSDRAM */
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC
->
AHB1ENR
|=
0x00000078
;
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB1ENR
,
RCC_AHB1ENR_GPIODEN
);
/* Connect PDx pins to FMC Alternate function */
GPIOD
->
AFR
[
0
]
=
0x00CCC0CC
;
GPIOD
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PDx pins in Alternate function mode */
GPIOD
->
MODER
=
0xAAAA0A8A
;
/* Configure PDx pins speed to 100 MHz */
GPIOD
->
OSPEEDR
=
0xFFFF0FCF
;
/* Configure PDx pins Output type to push-pull */
GPIOD
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PDx pins */
GPIOD
->
PUPDR
=
0x00000000
;
/* Connect PEx pins to FMC Alternate function */
GPIOE
->
AFR
[
0
]
=
0xC00CC0CC
;
GPIOE
->
AFR
[
1
]
=
0xCCCCCCCC
;
/* Configure PEx pins in Alternate function mode */
GPIOE
->
MODER
=
0xAAAA828A
;
/* Configure PEx pins speed to 100 MHz */
GPIOE
->
OSPEEDR
=
0xFFFFC3CF
;
/* Configure PEx pins Output type to push-pull */
GPIOE
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PEx pins */
GPIOE
->
PUPDR
=
0x00000000
;
/* Connect PFx pins to FMC Alternate function */
GPIOF
->
AFR
[
0
]
=
0x00CCCCCC
;
GPIOF
->
AFR
[
1
]
=
0xCCCC0000
;
/* Configure PFx pins in Alternate function mode */
GPIOF
->
MODER
=
0xAA000AAA
;
/* Configure PFx pins speed to 100 MHz */
GPIOF
->
OSPEEDR
=
0xFF000FFF
;
/* Configure PFx pins Output type to push-pull */
GPIOF
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PFx pins */
GPIOF
->
PUPDR
=
0x00000000
;
/* Connect PGx pins to FMC Alternate function */
GPIOG
->
AFR
[
0
]
=
0x00CCCCCC
;
GPIOG
->
AFR
[
1
]
=
0x000000C0
;
/* Configure PGx pins in Alternate function mode */
GPIOG
->
MODER
=
0x00085AAA
;
/* Configure PGx pins speed to 100 MHz */
GPIOG
->
OSPEEDR
=
0x000CAFFF
;
/* Configure PGx pins Output type to push-pull */
GPIOG
->
OTYPER
=
0x00000000
;
/* No pull-up, pull-down for PGx pins */
GPIOG
->
PUPDR
=
0x00000000
;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC
->
AHB3ENR
|=
0x00000001
;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001011
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00000201
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FMCEN
);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1
->
BTCR
[
2
]
=
0x00001091
;
FMC_Bank1
->
BTCR
[
3
]
=
0x00110212
;
FMC_Bank1E
->
BWTR
[
2
]
=
0x0fffffff
;
#endif
/* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
/* Delay after an RCC peripheral clock enabling */
tmp
=
READ_BIT
(
RCC
->
AHB3ENR
,
RCC_AHB3ENR_FSMCEN
);
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1
->
BTCR
[
2
]
=
0x00001011
;
FSMC_Bank1
->
BTCR
[
3
]
=
0x00000201
;
FSMC_Bank1E
->
BWTR
[
2
]
=
0x0FFFFFFF
;
#endif
/* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
#endif
/* DATA_IN_ExtSRAM */
#endif
/* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(
void
)(
tmp
);
}
#endif
/* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f429-fire-challenger/board/Kconfig
浏览文件 @
92338d50
...
...
@@ -16,7 +16,11 @@ menu "Onboard Peripheral Drivers"
bool "Enable RS232 (uart2 pin conflict with Ethernet)"
select BSP_USING_UART2
default n
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (W25Q128 spi5)"
select BSP_USING_SPI5
...
...
@@ -39,7 +43,13 @@ menu "Onboard Peripheral Drivers"
hex
default 0x00
endif
config BSP_USING_POT
bool "Enable potentiometer"
select BSP_USING_ADC
select BSP_USING_ADC1
default n
endmenu
menu "On-chip Peripheral Drivers"
...
...
@@ -67,6 +77,10 @@ menu "On-chip Peripheral Drivers"
config BSP_UART_USING_DMA_RX
bool "Enable UART RX DMA support"
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
...
...
@@ -87,6 +101,24 @@ menu "On-chip Peripheral Drivers"
bool "Enable SPI DMA support"
default n
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
config BSP_USING_ADC3
bool "Enable ADC3"
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
...
...
@@ -105,6 +137,17 @@ menu "On-chip Peripheral Drivers"
default 23
endif
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f429-fire-challenger/board/SConscript
浏览文件 @
92338d50
...
...
@@ -15,6 +15,10 @@ if GetDepend(['BSP_USING_SPI_FLASH']):
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
path
+=
[
cwd
+
'/ports'
]
if
GetDepend
([
'BSP_USING_SDRAM'
]):
path
+=
[
cwd
+
'/ports'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
cwd
+
'/../../libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s'
]
...
...
bsp/stm32/stm32f429-fire-challenger/board/board.h
浏览文件 @
92338d50
...
...
@@ -22,6 +22,10 @@
#define STM32_SRAM_SIZE (192)
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern
int
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
...
...
bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern
const
struct
fal_flash_dev
stm32_onchip_flash
;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 1008 * 1024, 0},\
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 1008* 1024 , 16 * 1024, 0},\
}
#endif
/* FAL_PART_HAS_TABLE_CFG */
#endif
/* _FAL_CFG_H_ */
bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
0 → 100644
浏览文件 @
92338d50
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-04 zylx The first version for STM32F4xx
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 2
/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XD0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 16
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 8
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 12
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 3
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 1
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_COUNT ((uint32_t)0x056A)
#define SDRAM_SIZE ((uint32_t)0x800000)
/* Timing configuration for IS42S16400J */
/* 90 MHz of SD clock frequency (180MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 7x11.90ns */
#define EXITSELFREFRESHDELAY 7
/* TRAS: 4x11.90ns */
#define SELFREFRESHTIME 4
/* TRC: 7x11.90ns */
#define ROWCYCLEDELAY 7
/* TWR: 2 Clock cycles */
#define WRITERECOVERYTIME 2
/* TRP: 2x11.90ns */
#define RPDELAY 2
/* TRCD: 2x11.90ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif
bsp/stm32/stm32f429-fire-challenger/rtconfig.h
浏览文件 @
92338d50
...
...
@@ -13,6 +13,7 @@
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_DEBUG
...
...
@@ -28,7 +29,8 @@
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
...
...
@@ -153,6 +155,12 @@
/* example package: hello */
/* Privated Packages of RealThread */
/* Network Utilities */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F4
...
...
@@ -169,7 +177,7 @@
#define BSP_USING_GPIO
#define BSP_USING_UART1
/*
Offboard Peripheral
Drivers */
/*
Board extended module
Drivers */
#endif
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