/***************************************************************************** * Copyright (c) 2019, Nations Technologies Inc. * * All rights reserved. * **************************************************************************** * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * - Redistributions of source code must retain the above copyright notice, * this list of conditions and the disclaimer below. * * Nations' name may not be used to endorse or promote products derived from * this software without specific prior written permission. * * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ /** * @file n32g45x.h * @author Nations * @version v1.0.3 * * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. */ #ifndef __N32G45X_H__ #define __N32G45X_H__ #ifdef __cplusplus extern "C" { #endif /** @addtogroup N32G45x_Library_Basic * @{ */ #if !defined USE_STDPERIPH_DRIVER /* * Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ #define USE_STDPERIPH_DRIVER #endif /* * In the following line adjust the value of External High Speed oscillator (HSE) used in your application Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. */ #if !defined HSE_VALUE #define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /* * In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x8000) /*!< Time out for HSE start up */ #define HSI_VALUE (8000000) /*!< Value of the Internal oscillator in Hz*/ #define __N32G45X_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */ #define __N32G45X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ #define __N32G45X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __N32G45X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ /** * @brief N32G45X Standard Peripheral Library version number */ #define __N32G45X_STDPERIPH_VERSION \ ((__N32G45X_STDPERIPH_VERSION_MAIN << 24) | (__N32G45X_STDPERIPH_VERSION_SUB1 << 16) \ | (__N32G45X_STDPERIPH_VERSION_SUB2 << 8) | (__N32G45X_STDPERIPH_VERSION_RC)) /* * Configuration of the Cortex-M4 Processor and Core Peripherals */ #ifdef N32G45X #define __MPU_PRESENT 1 /*!< N32G45X devices does not provide an MPU */ #define __FPU_PRESENT 1 /*!< FPU present */ #endif /* N32G45X */ #define __NVIC_PRIO_BITS 4 /*!< N32G45X uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** * @brief N32G45X Interrupt Number Definition */ typedef enum IRQn { /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** N32G45X specific Interrupt Numbers ********************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMPER_IRQn = 2, /*!< Tamper Interrupt */ RTC_IRQn = 3, /*!< RTC global Interrupt */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ ADC3_4_IRQn = 47, /*!< ADC3 and ADC4 global Interrupt */ RESERVE48_IRQn = 48, /*!< RESERVE */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI Line interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ QSPI_IRQn = 67, /*!< QSPI global Interrupt */ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global Interrupt */ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global Interrupt */ I2C3_EV_IRQn = 70, /*!< I2C3 Event Interrupt */ I2C3_ER_IRQn = 71, /*!< I2C3 Error Interrupt */ I2C4_EV_IRQn = 72, /*!< I2C4 Event Interrupt */ I2C4_ER_IRQn = 73, /*!< I2C4 Error Interrupt */ UART6_IRQn = 74, /*!< UART6 global Interrupt */ UART7_IRQn = 75, /*!< UART7 global Interrupt */ DMA1_Channel8_IRQn = 76, /*!< DMA1 Channel 8 global Interrupt */ DMA2_Channel8_IRQn = 77, /*!< DMA2 Channel 8 global Interrupt */ DVP_IRQn = 78, /*!< DVP global Interrupt */ SAC_IRQn = 79, /*!< SAC global Interrupt */ MMU_IRQn = 80, /*!< MMU global Interrupt */ TSC_IRQn = 81, /*!< TSC global Interrupt */ COMP_1_2_3_IRQn = 82, /*!< COMP1 & COMP2 & COMP3 global Interrupt */ COMP_4_5_6_IRQn = 83, /*!< COMP4 & COMP5 & COMP6 global Interrupt */ COMP7_IRQn = 84 /*!< COMP7 global Interrupt */ } IRQn_Type; #include "core_cm4.h" #include "system_n32g45x.h" #include #include typedef int32_t s32; typedef int16_t s16; typedef int8_t s8; typedef const int32_t sc32; /*!< Read Only */ typedef const int16_t sc16; /*!< Read Only */ typedef const int8_t sc8; /*!< Read Only */ typedef __IO int32_t vs32; typedef __IO int16_t vs16; typedef __IO int8_t vs8; typedef __I int32_t vsc32; /*!< Read Only */ typedef __I int16_t vsc16; /*!< Read Only */ typedef __I int8_t vsc8; /*!< Read Only */ typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; typedef const uint32_t uc32; /*!< Read Only */ typedef const uint16_t uc16; /*!< Read Only */ typedef const uint8_t uc8; /*!< Read Only */ typedef __IO uint32_t vu32; typedef __IO uint16_t vu16; typedef __IO uint8_t vu8; typedef __I uint32_t vuc32; /*!< Read Only */ typedef __I uint16_t vuc16; /*!< Read Only */ typedef __I uint8_t vuc8; /*!< Read Only */ typedef enum { RESET = 0, SET = !RESET } FlagStatus, INTStatus; typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus; /* N32G45X Standard Peripheral Library old definitions (maintained for legacy purpose) */ #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT #define HSE_Value HSE_VALUE #define HSI_Value HSI_VALUE /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t STS; __IO uint32_t CTRL1; __IO uint32_t CTRL2; __IO uint32_t SAMPT1; __IO uint32_t SAMPT2; __IO uint32_t JOFFSET1; __IO uint32_t JOFFSET2; __IO uint32_t JOFFSET3; __IO uint32_t JOFFSET4; __IO uint32_t WDGHIGH; __IO uint32_t WDGLOW; __IO uint32_t RSEQ1; __IO uint32_t RSEQ2; __IO uint32_t RSEQ3; __IO uint32_t JSEQ; __IO uint32_t JDAT1; __IO uint32_t JDAT2; __IO uint32_t JDAT3; __IO uint32_t JDAT4; __IO uint32_t DAT; __IO uint32_t DIFSEL; __IO uint32_t CALFACT; __IO uint32_t CTRL3; __IO uint32_t SAMPT3; } ADC_Module; /** * @brief OPAMP */ typedef struct { __IO uint32_t CS1; __IO uint32_t RES1[3]; __IO uint32_t CS2; __IO uint32_t RES2[3]; __IO uint32_t CS3; __IO uint32_t RES3[3]; __IO uint32_t CS4; __IO uint32_t RES4[3]; __IO uint32_t LOCK; } OPAMP_Module; /** * @brief COMP_Single */ typedef struct { __IO uint32_t CTRL; __IO uint32_t FILC; __IO uint32_t FILP; __IO uint32_t RES; } COMP_SingleType; /** * @brief COMP */ typedef struct { __IO uint32_t RES4[4]; COMP_SingleType Cmp[7]; __IO uint32_t WINMODE; __IO uint32_t LOCK; __IO uint32_t RES; __IO uint32_t INTEN; __IO uint32_t INTSTS; __IO uint32_t VREFSCL; } COMP_Module; /** * @brief AFEC */ typedef struct { __IO uint32_t TRIMR0; __IO uint32_t TRIMR1; __IO uint32_t TRIMR2; __IO uint32_t TRIMR3; __IO uint32_t TRIMR4; __IO uint32_t TRIMR5; __IO uint32_t TRIMR6; uint32_t RESERVED0; __IO uint32_t TESTR0; __IO uint32_t TESTR1; } AFEC_Module; /** * @brief Backup Registers */ typedef struct { uint32_t RESERVED0; __IO uint16_t DAT1; uint16_t RESERVED1; __IO uint16_t DAT2; uint16_t RESERVED2; __IO uint16_t DAT3; uint16_t RESERVED3; __IO uint16_t DAT4; uint16_t RESERVED4; __IO uint16_t DAT5; uint16_t RESERVED5; __IO uint16_t DAT6; uint16_t RESERVED6; __IO uint16_t DAT7; uint16_t RESERVED7; __IO uint16_t DAT8; uint16_t RESERVED8; __IO uint16_t DAT9; uint16_t RESERVED9; __IO uint16_t DAT10; uint16_t RESERVED10; __IO uint16_t RESERVED; uint16_t RESERVED11; __IO uint16_t CTRL; uint16_t RESERVED12; __IO uint16_t CTRLSTS; uint16_t RESERVED13[5]; __IO uint16_t DAT11; uint16_t RESERVED14; __IO uint16_t DAT12; uint16_t RESERVED15; __IO uint16_t DAT13; uint16_t RESERVED16; __IO uint16_t DAT14; uint16_t RESERVED17; __IO uint16_t DAT15; uint16_t RESERVED18; __IO uint16_t DAT16; uint16_t RESERVED19; __IO uint16_t DAT17; uint16_t RESERVED20; __IO uint16_t DAT18; uint16_t RESERVED21; __IO uint16_t DAT19; uint16_t RESERVED22; __IO uint16_t DAT20; uint16_t RESERVED23; __IO uint16_t DAT21; uint16_t RESERVED24; __IO uint16_t DAT22; uint16_t RESERVED25; __IO uint16_t DAT23; uint16_t RESERVED26; __IO uint16_t DAT24; uint16_t RESERVED27; __IO uint16_t DAT25; uint16_t RESERVED28; __IO uint16_t DAT26; uint16_t RESERVED29; __IO uint16_t DAT27; uint16_t RESERVED30; __IO uint16_t DAT28; uint16_t RESERVED31; __IO uint16_t DAT29; uint16_t RESERVED32; __IO uint16_t DAT30; uint16_t RESERVED33; __IO uint16_t DAT31; uint16_t RESERVED34; __IO uint16_t DAT32; uint16_t RESERVED35; __IO uint16_t DAT33; uint16_t RESERVED36; __IO uint16_t DAT34; uint16_t RESERVED37; __IO uint16_t DAT35; uint16_t RESERVED38; __IO uint16_t DAT36; uint16_t RESERVED39; __IO uint16_t DAT37; uint16_t RESERVED40; __IO uint16_t DAT38; uint16_t RESERVED41; __IO uint16_t DAT39; uint16_t RESERVED42; __IO uint16_t DAT40; uint16_t RESERVED43; __IO uint16_t DAT41; uint16_t RESERVED44; __IO uint16_t DAT42; uint16_t RESERVED45; } BKP_Module; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TMI; __IO uint32_t TMDT; __IO uint32_t TMDL; __IO uint32_t TMDH; } CAN_TxMailBox_Param; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RMI; __IO uint32_t RMDT; __IO uint32_t RMDL; __IO uint32_t RMDH; } CAN_FIFOMailBox_Param; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_Param; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCTRL; __IO uint32_t MSTS; __IO uint32_t TSTS; __IO uint32_t RFF0; __IO uint32_t RFF1; __IO uint32_t INTE; __IO uint32_t ESTS; __IO uint32_t BTIM; uint32_t RESERVED0[88]; CAN_TxMailBox_Param sTxMailBox[3]; CAN_FIFOMailBox_Param sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FMC; __IO uint32_t FM1; uint32_t RESERVED2; __IO uint32_t FS1; uint32_t RESERVED3; __IO uint32_t FFA1; uint32_t RESERVED4; __IO uint32_t FA1; uint32_t RESERVED5[8]; CAN_FilterRegister_Param sFilterRegister[14]; } CAN_Module; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t CRC32DAT; /*!< CRC data register */ __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/ uint8_t RESERVED0; uint16_t RESERVED1; __IO uint32_t CRC32CTRL; /*!< CRC control register */ __IO uint32_t CRC16CTRL; __IO uint8_t CRC16DAT; uint8_t RESERVED2; uint16_t RESERVED3; __IO uint16_t CRC16D; uint16_t RESERVED4; __IO uint8_t LRC; uint8_t RESERVED5; uint16_t RESERVED6; } CRC_Module; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CTRL; __IO uint32_t SOTTR; __IO uint32_t DR12CH1; __IO uint32_t DL12CH1; __IO uint32_t DR8CH1; __IO uint32_t DR12CH2; __IO uint32_t DL12CH2; __IO uint32_t DR8CH2; __IO uint32_t DR12DCH; __IO uint32_t DL12DCH; __IO uint32_t DR8DCH; __IO uint32_t DATO1; __IO uint32_t DATO2; } DAC_Module; /** * @brief USB */ typedef struct { __IO uint32_t EP0; __IO uint32_t EP1; __IO uint32_t EP2; __IO uint32_t EP3; __IO uint32_t EP4; __IO uint32_t EP5; __IO uint32_t EP6; __IO uint32_t EP7; __IO uint32_t Reserve20h; __IO uint32_t Reserve24h; __IO uint32_t Reserve28h; __IO uint32_t Reserve2Ch; __IO uint32_t Reserve30h; __IO uint32_t Reserve34h; __IO uint32_t Reserve38h; __IO uint32_t Reserve3Ch; __IO uint32_t CTRL; __IO uint32_t STS; __IO uint32_t FN; __IO uint32_t ADDR; __IO uint32_t BUFTAB; } USB_Module; /** * @brief Debug MCU */ typedef struct { __IO uint32_t ID; __IO uint32_t CTRL; } DBG_Module; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CHCFG; __IO uint32_t TXNUM; __IO uint32_t PADDR; __IO uint32_t MADDR; __IO uint32_t CHSEL; } DMA_ChannelType; typedef struct { __IO uint32_t INTSTS; __IO uint32_t INTCLR; __IO DMA_ChannelType DMA_Channel[8]; __IO uint32_t CHMAPEN; } DMA_Module; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCFG; __IO uint32_t MACFFLT; __IO uint32_t MACHASHHI; __IO uint32_t MACHASHLO; __IO uint32_t MACMIIADDR; __IO uint32_t MACMIIDAT; __IO uint32_t MACFLWCTRL; __IO uint32_t MACVLANTAG; /* 8 */ uint32_t RESERVED0[2]; __IO uint32_t MACRMTWUFRMFLT; /* 11 */ __IO uint32_t MACPMTCTRLSTS; uint32_t RESERVED1[2]; __IO uint32_t MACINTSTS; /* 15 */ __IO uint32_t MACINTMSK; __IO uint32_t MACADDR0HI; __IO uint32_t MACADDR0LO; __IO uint32_t MACADDR1HI; __IO uint32_t MACADDR1LO; __IO uint32_t MACADDR2HI; __IO uint32_t MACADDR2LO; __IO uint32_t MACADDR3HI; __IO uint32_t MACADDR3LO; /* 24 */ uint32_t RESERVED2[40]; __IO uint32_t MMCCTRL; /* 65 */ __IO uint32_t MMCRXINT; __IO uint32_t MMCTXINT; __IO uint32_t MMCRXINTMSK; __IO uint32_t MMCTXINTMSK; /* 69 */ uint32_t RESERVED3[14]; __IO uint32_t MMCTXGFASCCNT; /* 84 */ __IO uint32_t MMCTXGFAMSCCNT; uint32_t RESERVED4[5]; __IO uint32_t MMCTXGFCNT; uint32_t RESERVED5[10]; __IO uint32_t MMCRXFCECNT; __IO uint32_t MMCRXFAECNT; uint32_t RESERVED6[10]; __IO uint32_t MMCRXGUFCNT; uint32_t RESERVED7[14]; __IO uint32_t MMCRXCOINTMSK; uint32_t RESERVED8[319]; __IO uint32_t PTPTSCTRL; __IO uint32_t PTPSSINC; __IO uint32_t PTPSEC; __IO uint32_t PTPNS; __IO uint32_t PTPSECUP; __IO uint32_t PTPNSUP; __IO uint32_t PTPTSADD; __IO uint32_t PTPTTSEC; __IO uint32_t PTPTTNS; uint32_t RESERVED9[567]; __IO uint32_t DMABUSMOD; __IO uint32_t DMATXPD; __IO uint32_t DMARXPD; __IO uint32_t DMARXDLADDR; __IO uint32_t DMATXDLADDR; __IO uint32_t DMASTS; __IO uint32_t DMAOPMOD; __IO uint32_t DMAINTEN; __IO uint32_t DMAMFBOCNT; uint32_t RESERVED10[9]; __IO uint32_t DMACHTXDESC; __IO uint32_t DMACHRXDESC; __IO uint32_t DMACHTXBADDR; __IO uint32_t DMACHRXBADDR; } ETH_Module; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMASK; __IO uint32_t EMASK; __IO uint32_t RT_CFG; __IO uint32_t FT_CFG; __IO uint32_t SWIE; __IO uint32_t PEND; __IO uint32_t TSSEL; } EXTI_Module; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t AC; __IO uint32_t KEY; __IO uint32_t OPTKEY; __IO uint32_t STS; __IO uint32_t CTRL; __IO uint32_t ADD; __IO uint32_t RESERVED0; __IO uint32_t OBR; __IO uint32_t WRP; __IO uint32_t RESERVED1; __IO uint32_t RESERVED2; __IO uint32_t RDN; __IO uint32_t CAHR; } FLASH_Module; /** * @brief Option Bytes Registers */ typedef struct { __IO uint32_t USER_RDP; __IO uint32_t Data1_Data0; __IO uint32_t WRP1_WRP0; __IO uint32_t WRP3_WRP2; __IO uint32_t RDP2; } OB_Module; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t PL_CFG; __IO uint32_t PH_CFG; __IO uint32_t PID; __IO uint32_t POD; __IO uint32_t PBSC; __IO uint32_t PBC; __IO uint32_t PLOCK_CFG; uint32_t RESERVED0; __IO uint32_t DS_CFG; __IO uint32_t SR_CFG; } GPIO_Module; /** * @brief Alternate Function I/O */ typedef struct { __IO uint32_t ECTRL; __IO uint32_t RMP_CFG; __IO uint32_t EXTI_CFG[4]; uint32_t RESERVED0; uint32_t RESERVED1; __IO uint32_t RMP_CFG3; __IO uint32_t RMP_CFG4; __IO uint32_t RMP_CFG5; } AFIO_Module; /** * @brief Inter Integrated Circuit Interface */ typedef struct { __IO uint16_t CTRL1; uint16_t RESERVED0; __IO uint16_t CTRL2; uint16_t RESERVED1; __IO uint16_t OADDR1; uint16_t RESERVED2; __IO uint16_t OADDR2; uint16_t RESERVED3; __IO uint16_t DAT; uint16_t RESERVED4; __IO uint16_t STS1; uint16_t RESERVED5; __IO uint16_t STS2; uint16_t RESERVED6; __IO uint16_t CLKCTRL; uint16_t RESERVED7; __IO uint16_t TMRISE; uint16_t RESERVED8; } I2C_Module; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KEY; __IO uint32_t PREDIV; /*!< IWDG PREDIV */ __IO uint32_t RELV; __IO uint32_t STS; } IWDG_Module; /** * @brief Power Control */ typedef struct { __IO uint32_t CTRL; __IO uint32_t CTRLSTS; __IO uint32_t CTRL2; __IO uint32_t CTRL3; } PWR_Module; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CTRL; __IO uint32_t CFG; __IO uint32_t CLKINT; __IO uint32_t APB2PRST; __IO uint32_t APB1PRST; __IO uint32_t AHBPCLKEN; __IO uint32_t APB2PCLKEN; __IO uint32_t APB1PCLKEN; __IO uint32_t BDCTRL; __IO uint32_t CTRLSTS; __IO uint32_t AHBPRST; __IO uint32_t CFG2; __IO uint32_t CFG3; } RCC_Module; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */ uint32_t reserved0; /*!< Reserved */ __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */ uint32_t reserved6; /*!< RTC tamper configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */ uint32_t reserved1; /*!< Reserved Address offset: 0x50 */ uint32_t reserved2; /*!< Reserved Address offset: 0x54 */ uint32_t reserved3; /*!< Reserved Address offset: 0x58 */ uint32_t reserved4; /*!< Reserved Address offset: 0x5C */ uint32_t reserved5; /*!< Reserved Address offset: 0x60 */ __IO uint32_t TSCWKUPCTRL; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t TSCWKUPCNT; /*!< RTC backup register 6, Address offset: 0x68 */ } RTC_Module; /** * @brief SD host Interface */ typedef struct { __IO uint32_t PWRCTRL; __IO uint32_t CLKCTRL; __IO uint32_t CMDARG; __IO uint32_t CMDCTRL; __I uint32_t CMDRESP; __I uint32_t RESPONSE1; __I uint32_t RESPONSE2; __I uint32_t RESPONSE3; __I uint32_t RESPONSE4; __IO uint32_t DTIMER; __IO uint32_t DATLEN; __IO uint32_t DATCTRL; __I uint32_t DATCOUNT; __I uint32_t STS; __IO uint32_t INTCLR; __IO uint32_t INTEN; uint32_t RESERVED0[2]; __I uint32_t FIFOCOUNT; uint32_t RESERVED1[13]; __IO uint32_t DATFIFO; } SDIO_Module; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint16_t CTRL1; uint16_t RESERVED0; __IO uint16_t CTRL2; uint16_t RESERVED1; __IO uint16_t STS; uint16_t RESERVED2; __IO uint16_t DAT; uint16_t RESERVED3; __IO uint16_t CRCPOLY; uint16_t RESERVED4; __IO uint16_t CRCRDAT; uint16_t RESERVED5; __IO uint16_t CRCTDAT; uint16_t RESERVED6; __IO uint16_t I2SCFG; uint16_t RESERVED7; __IO uint16_t I2SPREDIV; uint16_t RESERVED8; } SPI_Module; /** * @brief TIM */ typedef struct { __IO uint32_t CTRL1; __IO uint32_t CTRL2; __IO uint16_t SMCTRL; uint16_t RESERVED1; __IO uint16_t DINTEN; uint16_t RESERVED2; __IO uint32_t STS; __IO uint16_t EVTGEN; uint16_t RESERVED3; __IO uint16_t CCMOD1; uint16_t RESERVED4; __IO uint16_t CCMOD2; uint16_t RESERVED5; __IO uint32_t CCEN; __IO uint16_t CNT; uint16_t RESERVED6; __IO uint16_t PSC; uint16_t RESERVED7; __IO uint16_t AR; uint16_t RESERVED8; __IO uint16_t REPCNT; uint16_t RESERVED9; __IO uint16_t CCDAT1; uint16_t RESERVED10; __IO uint16_t CCDAT2; uint16_t RESERVED11; __IO uint16_t CCDAT3; uint16_t RESERVED12; __IO uint16_t CCDAT4; uint16_t RESERVED13; __IO uint16_t BKDT; uint16_t RESERVED14; __IO uint16_t DCTRL; uint16_t RESERVED15; __IO uint16_t DADDR; uint16_t RESERVED16; uint32_t RESERVED17; __IO uint16_t CCMOD3; uint16_t RESERVED18; __IO uint16_t CCDAT5; uint16_t RESERVED19; __IO uint16_t CCDAT6; uint16_t RESERVED20; } TIM_Module; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t STS; uint16_t RESERVED0; __IO uint16_t DAT; uint16_t RESERVED1; __IO uint16_t BRCF; uint16_t RESERVED2; __IO uint16_t CTRL1; uint16_t RESERVED3; __IO uint16_t CTRL2; uint16_t RESERVED4; __IO uint16_t CTRL3; uint16_t RESERVED5; __IO uint16_t GTP; uint16_t RESERVED6; } USART_Module; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CTRL; __IO uint32_t CFG; __IO uint32_t STS; } WWDG_Module; /** * @brief QSPI */ typedef struct { __IO uint32_t CTRL0; __IO uint32_t CTRL1; __IO uint32_t EN; __IO uint32_t MW_CTRL; __IO uint32_t SLAVE_EN; __IO uint32_t BAUD; __IO uint32_t TXFT; __IO uint32_t RXFT; __IO uint32_t TXFN; __IO uint32_t RXFN; __IO uint32_t STS; __IO uint32_t IMASK; __IO uint32_t ISTS; __IO uint32_t RISTS; __IO uint32_t TXFOI_CLR; __IO uint32_t RXFOI_CLR; __IO uint32_t RXFUI_CLR; __IO uint32_t MMC_CLR; __IO uint32_t ICLR; __IO uint32_t DMA_CTRL; __IO uint32_t DMATDL_CTRL; __IO uint32_t DMARDL_CTRL; __IO uint32_t IDCODE; __IO uint32_t RESERVED; __IO uint32_t DAT0; __IO uint32_t DAT1; __IO uint32_t DAT2; __IO uint32_t DAT3; __IO uint32_t DAT4; __IO uint32_t DAT5; __IO uint32_t DAT6; __IO uint32_t DAT7; __IO uint32_t DAT8; __IO uint32_t DAT9; __IO uint32_t DAT10; __IO uint32_t DAT11; __IO uint32_t DAT12; __IO uint32_t DAT13; __IO uint32_t DAT14; __IO uint32_t DAT15; __IO uint32_t DAT16; __IO uint32_t DAT17; __IO uint32_t DAT18; __IO uint32_t DAT19; __IO uint32_t DAT20; __IO uint32_t DAT21; __IO uint32_t DAT22; __IO uint32_t DAT23; __IO uint32_t DAT24; __IO uint32_t DAT25; __IO uint32_t DAT26; __IO uint32_t DAT27; __IO uint32_t DAT28; __IO uint32_t DAT29; __IO uint32_t DAT30; __IO uint32_t DAT31; __IO uint32_t RESERVED2; /*DAT32-DAT35 is reserved*/ __IO uint32_t RESERVED3; /*DAT32-DAT35 is reserved*/ __IO uint32_t RESERVED4; /*DAT32-DAT35 is reserved*/ __IO uint32_t RESERVED5; /*DAT32-DAT35 is reserved*/ __IO uint32_t RS_DELAY; __IO uint32_t ENH_CTRL0; __IO uint32_t DDR_TXDE; __IO uint32_t XIP_MODE; __IO uint32_t XIP_INCR_TOC; __IO uint32_t XIP_WRAP_TOC; __IO uint32_t XIP_CTRL; __IO uint32_t XIP_SLAVE_EN; __IO uint32_t XIP_RXFOI_CLR; __IO uint32_t XIP_TOUT; } QSPI_Module; /** * @brief Touch Sensor Controller */ typedef struct { __IO uint32_t CTRL; __IO uint32_t CHNEN; __IO uint32_t STS; __IO uint32_t RESERVED; __IO uint32_t ANA_CTRL; __IO uint32_t ANA_SEL; __IO uint32_t RESR0; __IO uint32_t RESR1; __IO uint32_t RESR2; __IO uint32_t THRHD0; __IO uint32_t THRHD1; __IO uint32_t THRHD2; __IO uint32_t THRHD3; __IO uint32_t THRHD4; __IO uint32_t THRHD5; __IO uint32_t THRHD6; __IO uint32_t THRHD7; __IO uint32_t THRHD8; __IO uint32_t THRHD9; __IO uint32_t THRHD10; __IO uint32_t THRHD11; __IO uint32_t THRHD12; __IO uint32_t THRHD13; __IO uint32_t THRHD14; __IO uint32_t THRHD15; __IO uint32_t THRHD16; __IO uint32_t THRHD17; __IO uint32_t THRHD18; __IO uint32_t THRHD19; __IO uint32_t THRHD20; __IO uint32_t THRHD21; __IO uint32_t THRHD22; __IO uint32_t THRHD23; } TSC_Module; /** * @brief DVP */ typedef struct { __IO uint32_t CTRL; /*!< DVP control register*/ __IO uint32_t STS; /*!< DVP status register*/ __IO uint32_t INTSTS; /*!< DVP interrupt status register*/ __IO uint32_t INTEN; /*!< DVP interrupt enable register*/ __IO uint32_t MINTSTS; /*!< DVP interrupt mask status register */ __IO uint32_t WST; /*!< DVP start register */ __IO uint32_t WSIZE; /*!< DVP size register */ __IO uint32_t FIFO; /*!< DVP FIFO register */ } DVP_Module; #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */ #define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */ #define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */ #define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */ #define DBGMCU_ID_BASE ((uint32_t)0xE0042000) /*!< DBGMCU_ID Address */ #define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE (PERIPH_BASE) #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x18000) /* APB1 */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) #define AFEC_BASE (APB1PERIPH_BASE + 0x1800) #define OPAMP_BASE (APB1PERIPH_BASE + 0x2000) #define COMP_BASE (APB1PERIPH_BASE + 0x2400) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) #define TSC_BASE (APB1PERIPH_BASE + 0x3400) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) #define USART3_BASE (APB1PERIPH_BASE + 0x4800) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) #define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define USB_BASE (APB1PERIPH_BASE + 0x5C00) #define USB_CAN1_SRAM_BASE (APB1PERIPH_BASE + 0x6000) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) /* APB2 */ #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) #define USART1_BASE (APB2PERIPH_BASE + 0x3800) #define I2C3_BASE (APB2PERIPH_BASE + 0x4400) #define I2C4_BASE (APB2PERIPH_BASE + 0x4800) #define DVP_BASE (APB2PERIPH_BASE + 0x4C00) #define UART6_BASE (APB2PERIPH_BASE + 0x5000) #define UART7_BASE (APB2PERIPH_BASE + 0x5400) /* AHB */ #define SDIO_BASE (AHBPERIPH_BASE + 0x0000) #define DMA1_BASE (AHBPERIPH_BASE + 0x8000) #define DMA1_CH1_BASE (AHBPERIPH_BASE + 0x8008) #define DMA1_CH2_BASE (AHBPERIPH_BASE + 0x801C) #define DMA1_CH3_BASE (AHBPERIPH_BASE + 0x8030) #define DMA1_CH4_BASE (AHBPERIPH_BASE + 0x8044) #define DMA1_CH5_BASE (AHBPERIPH_BASE + 0x8058) #define DMA1_CH6_BASE (AHBPERIPH_BASE + 0x806C) #define DMA1_CH7_BASE (AHBPERIPH_BASE + 0x8080) #define DMA1_CH8_BASE (AHBPERIPH_BASE + 0x8094) #define DMA2_BASE (AHBPERIPH_BASE + 0x8400) #define DMA2_CH1_BASE (AHBPERIPH_BASE + 0x8408) #define DMA2_CH2_BASE (AHBPERIPH_BASE + 0x841C) #define DMA2_CH3_BASE (AHBPERIPH_BASE + 0x8430) #define DMA2_CH4_BASE (AHBPERIPH_BASE + 0x8444) #define DMA2_CH5_BASE (AHBPERIPH_BASE + 0x8458) #define DMA2_CH6_BASE (AHBPERIPH_BASE + 0x846C) #define DMA2_CH7_BASE (AHBPERIPH_BASE + 0x8480) #define DMA2_CH8_BASE (AHBPERIPH_BASE + 0x8494) #define ADC1_BASE (AHBPERIPH_BASE + 0x8800) #define ADC2_BASE (AHBPERIPH_BASE + 0x8C00) #define RCC_BASE (AHBPERIPH_BASE + 0x9000) #define ADC3_BASE (AHBPERIPH_BASE + 0x9800) #define ADC4_BASE (AHBPERIPH_BASE + 0x9C00) #define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */ #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ #define CRC_BASE (AHBPERIPH_BASE + 0xB000) #define SAC_BASE (AHBPERIPH_BASE + 0xC000) #define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400) #define MMU_BASE (AHBPERIPH_BASE + 0xCC00) #define ETH_BASE (AHBPERIPH_BASE + 0x10000) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) #define QSPI_BASE (((uint32_t)0xA0001000)) #define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ #define TIM2 ((TIM_Module*)TIM2_BASE) #define TIM3 ((TIM_Module*)TIM3_BASE) #define TIM4 ((TIM_Module*)TIM4_BASE) #define TIM5 ((TIM_Module*)TIM5_BASE) #define TIM6 ((TIM_Module*)TIM6_BASE) #define TIM7 ((TIM_Module*)TIM7_BASE) #define AFEC ((AFEC_Module*)AFEC_BASE) #define OPAMP ((OPAMP_Module*)OPAMP_BASE) #define COMP ((COMP_Module*)COMP_BASE) #define RTC ((RTC_Module*)RTC_BASE) #define WWDG ((WWDG_Module*)WWDG_BASE) #define IWDG ((IWDG_Module*)IWDG_BASE) #define TSC ((TSC_Module*)TSC_BASE) #define SPI2 ((SPI_Module*)SPI2_BASE) #define SPI3 ((SPI_Module*)SPI3_BASE) #define USART2 ((USART_Module*)USART2_BASE) #define USART3 ((USART_Module*)USART3_BASE) #define UART4 ((USART_Module*)UART4_BASE) #define UART5 ((USART_Module*)UART5_BASE) #define I2C1 ((I2C_Module*)I2C1_BASE) #define I2C2 ((I2C_Module*)I2C2_BASE) #define USB ((USB_Module*)USB_BASE) #define CAN1 ((CAN_Module*)CAN1_BASE) #define CAN2 ((CAN_Module*)CAN2_BASE) #define BKP ((BKP_Module*)BKP_BASE) #define PWR ((PWR_Module*)PWR_BASE) #define DAC ((DAC_Module*)DAC_BASE) #define AFIO ((AFIO_Module*)AFIO_BASE) #define EXTI ((EXTI_Module*)EXTI_BASE) #define GPIOA ((GPIO_Module*)GPIOA_BASE) #define GPIOB ((GPIO_Module*)GPIOB_BASE) #define GPIOC ((GPIO_Module*)GPIOC_BASE) #define GPIOD ((GPIO_Module*)GPIOD_BASE) #define GPIOE ((GPIO_Module*)GPIOE_BASE) #define GPIOF ((GPIO_Module*)GPIOF_BASE) #define GPIOG ((GPIO_Module*)GPIOG_BASE) #define TIM1 ((TIM_Module*)TIM1_BASE) #define SPI1 ((SPI_Module*)SPI1_BASE) #define TIM8 ((TIM_Module*)TIM8_BASE) #define USART1 ((USART_Module*)USART1_BASE) #define I2C3 ((I2C_Module*)I2C3_BASE) #define I2C4 ((I2C_Module*)I2C4_BASE) #define DVP ((DVP_Module*)DVP_BASE) #define UART6 ((USART_Module*)UART6_BASE) #define UART7 ((USART_Module*)UART7_BASE) #define SDIO ((SDIO_Module*)SDIO_BASE) #define DMA1 ((DMA_Module*)DMA1_BASE) #define DMA2 ((DMA_Module*)DMA2_BASE) #define DMA1_CH1 ((DMA_ChannelType*)DMA1_CH1_BASE) #define DMA1_CH2 ((DMA_ChannelType*)DMA1_CH2_BASE) #define DMA1_CH3 ((DMA_ChannelType*)DMA1_CH3_BASE) #define DMA1_CH4 ((DMA_ChannelType*)DMA1_CH4_BASE) #define DMA1_CH5 ((DMA_ChannelType*)DMA1_CH5_BASE) #define DMA1_CH6 ((DMA_ChannelType*)DMA1_CH6_BASE) #define DMA1_CH7 ((DMA_ChannelType*)DMA1_CH7_BASE) #define DMA1_CH8 ((DMA_ChannelType*)DMA1_CH8_BASE) #define DMA2_CH1 ((DMA_ChannelType*)DMA2_CH1_BASE) #define DMA2_CH2 ((DMA_ChannelType*)DMA2_CH2_BASE) #define DMA2_CH3 ((DMA_ChannelType*)DMA2_CH3_BASE) #define DMA2_CH4 ((DMA_ChannelType*)DMA2_CH4_BASE) #define DMA2_CH5 ((DMA_ChannelType*)DMA2_CH5_BASE) #define DMA2_CH6 ((DMA_ChannelType*)DMA2_CH6_BASE) #define DMA2_CH7 ((DMA_ChannelType*)DMA2_CH7_BASE) #define DMA2_CH8 ((DMA_ChannelType*)DMA2_CH8_BASE) #define ADC1 ((ADC_Module*)ADC1_BASE) #define ADC2 ((ADC_Module*)ADC2_BASE) #define RCC ((RCC_Module*)RCC_BASE) #define ADC3 ((ADC_Module*)ADC3_BASE) #define ADC4 ((ADC_Module*)ADC4_BASE) #define FLASH ((FLASH_Module*)FLASH_R_BASE) #define OB ((OB_Module*)OB_BASE) #define CRC ((CRC_Module*)CRC_BASE) #define ETH ((ETH_Module*)ETH_BASE) #define QSPI ((QSPI_Module*)QSPI_BASE) #define DBG ((DBG_Module*)DBG_BASE) /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_CRC32DAT register *********************/ #define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ /******************* Bit definition for CRC_CRC32IDAT register ********************/ #define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CRC32CTRL register ********************/ #define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */ /******************** Bit definition for CRC16_CR register ********************/ #define CRC16_CTRL_LITTLE ((uint8_t)0x02) #define CRC16_CTRL_BIG ((uint8_t)0xFD) #define CRC16_CTRL_RESET ((uint8_t)0x04) #define CRC16_CTRL_NO_RESET ((uint8_t)0xFB) /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************** Bit definition for PWR_CTRL register ********************/ #define PWR_CTRL_LPS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ #define PWR_CTRL_PDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ #define PWR_CTRL_CWKUP ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ #define PWR_CTRL_CSBVBAT ((uint16_t)0x0008) /*!< Clear Standby Flag */ #define PWR_CTRL_PVDEN ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ #define PWR_CTRL_PRS ((uint16_t)0x00E0) /*!< PRS[2:0] bits (PVD Level Selection) */ #define PWR_CTRL_PRS_0 ((uint16_t)0x0020) /*!< Bit 0 */ #define PWR_CTRL_PRS_1 ((uint16_t)0x0040) /*!< Bit 1 */ #define PWR_CTRL_PRS_2 ((uint16_t)0x0080) /*!< Bit 2 */ /*!< PVD level configuration */ #define PWR_CTRL_PRS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ #define PWR_CTRL_PRS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ #define PWR_CTRL_PRS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ #define PWR_CTRL_PRS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ #define PWR_CTRL_PRS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ #define PWR_CTRL_PRS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ #define PWR_CTRL_PRS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ #define PWR_CTRL_PRS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ #define PWR_CTRL_DBKP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ #define PWR_CTRL_MSB ((uint16_t)0x0200) /*!< Bit 9 */ /******************* Bit definition for PWR_CTRLSTS register ********************/ #define PWR_CTRLSTS_WKUPF ((uint16_t)0x0001) /*!< Wakeup Flag */ #define PWR_CTRLSTS_SBF ((uint16_t)0x0002) /*!< Standby Flag */ #define PWR_CTRLSTS_PVDO ((uint16_t)0x0004) /*!< PVD Output */ #define PWR_CTRLSTS_VBATF ((uint16_t)0x0008) /*!< VBAT Flag */ #define PWR_CTRLSTS_WKUPEN ((uint16_t)0x0100) /*!< Enable WKUP pin */ /******************* Bit definition for PWR_CTRL2 register ********************/ #define PWR_CTRL2_STOP2S ((uint16_t)0x0001) /*!< Enable STOP2 */ #define PWR_CTRL2_SR2VBRET ((uint16_t)0x0002) /*!< VBAT mode SRAM2 retention */ #define PWR_CTRL2_SR2STBRET ((uint16_t)0x0004) /*!< Standby mode SRAM2 retention */ #define PWR_CTRL2_TMPWPEN ((uint16_t)0x0008) /*!< Enable Tamper WakeUp */ #define PWR_CTRL2_LSITRIM ((uint16_t)0x01F0) /*!< config the LSI trimming value */ #define PWR_CTRL2_IWDGWPEN ((uint16_t)0x0200) /*!< Enable IWDG WakeUp */ #define PWR_CTRL2_IWDGRSTEN ((uint16_t)0x0400) /*!< Enable IWDG RST WakeUp */ /******************* Bit definition for PWR_CTRL3 register ********************/ #define PWR_CTRL3_EXMODE ((uint16_t)0x0001) /*!< BKPM Mode */ #define PWR_CTRL3_EXMODE_EXTEND ((uint16_t)0x0001) /*!< EXTEND Mode */ #define PWR_CTRL3_EXMODE_NORMAL ((uint16_t)0x0000) /*!< NORMAL Mode */ /******************************************************************************/ /* */ /* Backup registers */ /* */ /******************************************************************************/ /******************* Bit definition for BKP_DAT1 register ********************/ #define BKP_DAT1_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT2 register ********************/ #define BKP_DAT2_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT3 register ********************/ #define BKP_DAT3_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT4 register ********************/ #define BKP_DAT4_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT5 register ********************/ #define BKP_DAT5_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT6 register ********************/ #define BKP_DAT6_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT7 register ********************/ #define BKP_DAT7_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT8 register ********************/ #define BKP_DAT8_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT9 register ********************/ #define BKP_DAT9_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT10 register *******************/ #define BKP_DAT10_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT11 register *******************/ #define BKP_DAT11_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT12 register *******************/ #define BKP_DAT12_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT13 register *******************/ #define BKP_DAT13_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT14 register *******************/ #define BKP_DAT14_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT15 register *******************/ #define BKP_DAT15_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT16 register *******************/ #define BKP_DAT16_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT17 register *******************/ #define BKP_DAT17_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /****************** Bit definition for BKP_DAT18 register ********************/ #define BKP_DAT18_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT19 register *******************/ #define BKP_DAT19_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT20 register *******************/ #define BKP_DAT20_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT21 register *******************/ #define BKP_DAT21_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT22 register *******************/ #define BKP_DAT22_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT23 register *******************/ #define BKP_DAT23_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT24 register *******************/ #define BKP_DAT24_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT25 register *******************/ #define BKP_DAT25_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT26 register *******************/ #define BKP_DAT26_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT27 register *******************/ #define BKP_DAT27_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT28 register *******************/ #define BKP_DAT28_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT29 register *******************/ #define BKP_DAT29_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT30 register *******************/ #define BKP_DAT30_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT31 register *******************/ #define BKP_DAT31_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT32 register *******************/ #define BKP_DAT32_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT33 register *******************/ #define BKP_DAT33_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT34 register *******************/ #define BKP_DAT34_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT35 register *******************/ #define BKP_DAT35_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT36 register *******************/ #define BKP_DAT36_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT37 register *******************/ #define BKP_DAT37_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT38 register *******************/ #define BKP_DAT38_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT39 register *******************/ #define BKP_DAT39_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT40 register *******************/ #define BKP_DAT40_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT41 register *******************/ #define BKP_DAT41_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************* Bit definition for BKP_DAT42 register *******************/ #define BKP_DAT42_DAT ((uint16_t)0xFFFF) /*!< Backup data */ /******************** Bit definition for BKP_CTRL register ********************/ #define BKP_CTRL_TP_EN ((uint8_t)0x01) /*!< TAMPER pin enable */ #define BKP_CTRL_TP_ALEV ((uint8_t)0x02) /*!< TAMPER pin active level */ /******************* Bit definition for BKP_CTRLSTS register ********************/ #define BKP_CTRLSTS_CLRTE ((uint16_t)0x0001) /*!< Clear Tamper event */ #define BKP_CTRLSTS_CLRTINT ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ #define BKP_CTRLSTS_TPINT_EN ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ #define BKP_CTRLSTS_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ #define BKP_CTRLSTS_TINTF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ /******************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CTRL register ********************/ #define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ #define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ #define RCC_CTRL_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ #define RCC_CTRL_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ #define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */ #define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ #define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ #define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */ #define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */ #define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */ /******************* Bit definition for RCC_CFG register *******************/ /*!< SW configuration */ #define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ #define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ #define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ #define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ #define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ #define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ #define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ #define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ #define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ #define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ #define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ #define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ #define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ #define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ #define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ #define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ #define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ #define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ #define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ #define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ #define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ #define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ #define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ #define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ /*!< PLLSRC configuration */ #define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ /*!< PLLXTPRE configuration */ #define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ /*!< PLLMUL configuration */ #define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */ #define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */ #define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */ #define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */ #define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */ #define RCC_CFG_PLLSRC_HSI_DIV2 \ ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source \ */ #define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ #define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ #define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ #define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ #define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ #define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ #define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ #define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ #define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ #define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ #define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ #define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */ #define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ #define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ #define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ #define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ #define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ #define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ #define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */ #define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */ #define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */ #define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */ #define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */ #define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */ #define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */ #define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */ #define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */ #define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */ #define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */ #define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */ #define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */ #define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */ #define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */ #define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */ #define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */ /*!< USBPRES configuration */ #define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */ #define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */ #define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */ #define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ #define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */ #define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */ #define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */ /*!< MCO configuration */ #define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ #define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */ #define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ #define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ #define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ #define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ /*!< MCOPRE configuration */ #define RCC_CFG_MCOPRES \ ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by software to generate MCOPRE \ clock.) */ #define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */ #define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */ #define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */ #define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x20000000) /*!< PLL clock is divided by 2 */ #define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x30000000) /*!< PLL clock is divided by 3 */ #define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x40000000) /*!< PLL clock is divided by 4 */ #define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x50000000) /*!< PLL clock is divided by 5 */ #define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x60000000) /*!< PLL clock is divided by 6 */ #define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x70000000) /*!< PLL clock is divided by 7 */ #define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x80000000) /*!< PLL clock is divided by 8 */ #define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x90000000) /*!< PLL clock is divided by 9 */ #define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 10 */ #define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 11 */ #define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 12 */ #define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 13 */ #define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 14 */ #define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 15 */ /*!<****************** Bit definition for RCC_CLKINT register ********************/ #define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ #define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ #define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ #define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ #define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ #define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ #define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ #define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ #define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ #define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ #define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ #define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ #define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ #define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ #define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ #define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ #define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_APB2PRST register *****************/ #define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ #define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ #define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ #define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ #define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ #define RCC_APB2PRST_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ #define RCC_APB2PRST_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ #define RCC_APB2PRST_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ #define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ #define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ #define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ #define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ #define RCC_APB2PRST_DVPRST ((uint32_t)0x00010000) /*!< DVP reset */ #define RCC_APB2PRST_UART6RST ((uint32_t)0x00020000) /*!< UART6 reset */ #define RCC_APB2PRST_UART7RST ((uint32_t)0x00040000) /*!< UART7 reset */ #define RCC_APB2PRST_I2C3RST ((uint32_t)0x00080000) /*!< I2C3 reset */ #define RCC_APB2PRST_I2C4RST ((uint32_t)0x00100000) /*!< I2C4 reset */ /***************** Bit definition for RCC_APB1PRST register *****************/ #define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ #define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ #define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ #define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ #define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ #define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ #define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */ #define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ #define RCC_APB1PRST_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ #define RCC_APB1PRST_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ #define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ #define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ #define RCC_APB1PRST_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ #define RCC_APB1PRST_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ #define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ #define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ #define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ #define RCC_APB1PRST_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ #define RCC_APB1PRST_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ #define RCC_APB1PRST_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ #define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ #define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ /****************** Bit definition for RCC_AHBPCLKEN register ******************/ #define RCC_AHBPCLKEN_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ #define RCC_AHBPCLKEN_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ #define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ #define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ #define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ #define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */ #define RCC_AHBPCLKEN_SDIOEN ((uint32_t)0x00000400) /*!< SDIO clock enable */ #define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */ #define RCC_AHBPCLKEN_ADC1EN ((uint32_t)0x00001000) /*!< ADC1 clock enable */ #define RCC_AHBPCLKEN_ADC2EN ((uint32_t)0x00002000) /*!< ADC2 clock enable */ #define RCC_AHBPCLKEN_ADC3EN ((uint32_t)0x00004000) /*!< ADC3 clock enable */ #define RCC_AHBPCLKEN_ADC4EN ((uint32_t)0x00008000) /*!< ADC4 clock enable */ #define RCC_AHBPCLKEN_ETHMACEN ((uint32_t)0x00010000) /*!< ETHMAC clock enable */ #define RCC_AHBPCLKEN_QSPIEN ((uint32_t)0x00020000) /*!< QSPI clock enable */ /****************** Bit definition for RCC_APB2PCLKEN register *****************/ #define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ #define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ #define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ #define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ #define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ #define RCC_APB2PCLKEN_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ #define RCC_APB2PCLKEN_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ #define RCC_APB2PCLKEN_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ #define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ #define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ #define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ #define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ #define RCC_APB2PCLKEN_DVPEN ((uint32_t)0x00010000) /*!< DVP clock enable */ #define RCC_APB2PCLKEN_UART6EN ((uint32_t)0x00020000) /*!< UART6 clock enable */ #define RCC_APB2PCLKEN_UART7EN ((uint32_t)0x00040000) /*!< UART7 clock enable */ #define RCC_APB2PCLKEN_I2C3EN ((uint32_t)0x00080000) /*!< I2C3 clock enable */ #define RCC_APB2PCLKEN_I2C4EN ((uint32_t)0x00100000) /*!< I2C4 clock enable */ /***************** Bit definition for RCC_APB1PCLKEN register ******************/ #define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ #define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ #define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ #define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ #define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ #define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ #define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */ #define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */ #define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */ #define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ #define RCC_APB1PCLKEN_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ #define RCC_APB1PCLKEN_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ #define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ #define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ #define RCC_APB1PCLKEN_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ #define RCC_APB1PCLKEN_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ #define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ #define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ #define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ #define RCC_APB1PCLKEN_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ #define RCC_APB1PCLKEN_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ #define RCC_APB1PCLKEN_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ #define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ #define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ #define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */ /******************* Bit definition for RCC_BDCTRL register *******************/ #define RCC_BDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ #define RCC_BDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ #define RCC_BDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ #define RCC_BDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ #define RCC_BDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define RCC_BDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ /*!< RTC congiguration */ #define RCC_BDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ #define RCC_BDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ #define RCC_BDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ #define RCC_BDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ #define RCC_BDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ #define RCC_BDCTRL_BDSFTRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ /******************* Bit definition for RCC_CTRLSTS register ********************/ #define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ #define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ #define RCC_CTRLSTS_BORRSTF ((uint32_t)0x00080000) /*!< BOR reset flag */ #define RCC_CTRLSTS_RETEMCF ((uint32_t)0x00100000) /*!< RET_EMC reset flag */ #define RCC_CTRLSTS_BKPEMCF ((uint32_t)0x00200000) /*!< BKP_EMC reset flag */ #define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */ #define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */ #define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */ #define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ #define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ #define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ #define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ #define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ #define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ /******************* Bit definition for RCC_AHBPRST register ****************/ #define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */ #define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */ #define RCC_AHBRST_ADC1RST ((uint32_t)0x00001000) /*!< ADC1 reset */ #define RCC_AHBRST_ADC2RST ((uint32_t)0x00002000) /*!< ADC2 reset */ #define RCC_AHBRST_ADC3RST ((uint32_t)0x00004000) /*!< ADC3 reset */ #define RCC_AHBRST_ADC4RST ((uint32_t)0x00008000) /*!< ADC4 reset */ #define RCC_AHBRST_ETHMACRST ((uint32_t)0x00010000) /*!< ETHMAC reset */ #define RCC_AHBRST_QSPIRST ((uint32_t)0x00020000) /*!< QSPI reset */ /******************* Bit definition for RCC_CFG2 register ******************/ /*!< ADCHPRE configuration */ #define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */ #define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */ #define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */ #define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */ #define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */ #define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */ #define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */ #define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */ #define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */ #define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ #define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ /*!< ADCPLLPRES configuration */ #define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */ #define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */ #define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */ #define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */ #define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */ #define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */ #define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */ #define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */ #define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */ #define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */ #define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */ #define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */ #define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */ #define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */ #define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */ #define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */ /*!< ADC1MSEL configuration */ #define RCC_CFG2_ADC1MSEL ((uint32_t)0x00000400) /*!< ADC1M clock source select */ #define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */ #define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00000400) /*!< HSE clock selected as ADC1M input clock */ /*!< ADC1MPRE configuration */ #define RCC_CFG2_ADC1MPRES ((uint32_t)0x0000F800) /*!< ADC1MPRE[4:0] bits */ #define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ #define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ #define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ #define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ #define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ #define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */ #define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00000800) /*!< ADC1M source clock is divided by 2 */ #define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 3 */ #define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00001800) /*!< ADC1M source clock is divided by 4 */ #define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 5 */ #define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00002800) /*!< ADC1M source clock is divided by 6 */ #define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 7 */ #define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00003800) /*!< ADC1M source clock is divided by 8 */ #define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 9 */ #define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00004800) /*!< ADC1M source clock is divided by 10 */ #define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 11 */ #define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x00005800) /*!< ADC1M source clock is divided by 12 */ #define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 13 */ #define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x00006800) /*!< ADC1M source clock is divided by 14 */ #define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 15 */ #define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x00007800) /*!< ADC1M source clock is divided by 16 */ #define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 17 */ #define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00008800) /*!< ADC1M source clock is divided by 18 */ #define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 19 */ #define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00009800) /*!< ADC1M source clock is divided by 20 */ #define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 21 */ #define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x0000A800) /*!< ADC1M source clock is divided by 22 */ #define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 23 */ #define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x0000B800) /*!< ADC1M source clock is divided by 24 */ #define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 25 */ #define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x0000C800) /*!< ADC1M source clock is divided by 26 */ #define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 27 */ #define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0000D800) /*!< ADC1M source clock is divided by 28 */ #define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 29 */ #define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0000E800) /*!< ADC1M source clock is divided by 30 */ #define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 31 */ #define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0000F800) /*!< ADC1M source clock is divided by 32 */ /*!< RNGCPRE configuration */ #define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */ #define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */ #define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */ #define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */ #define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */ #define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */ #define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */ #define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */ #define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */ #define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */ #define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */ #define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */ #define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */ #define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */ #define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */ #define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */ #define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */ #define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */ #define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */ #define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */ #define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */ #define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */ #define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */ #define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */ #define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */ #define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */ #define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */ #define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */ #define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */ #define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */ #define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */ #define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */ #define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */ #define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */ /*!< TIMCLK_SEL configuration */ #define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */ #define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */ #define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */ /******************* Bit definition for RCC_CFG3 register ******************/ /*!< BORRSTEN configuration */ #define RCC_CFG3_BORRSTEN ((uint32_t)0x00000040) /*!< BOR reset enable */ #define RCC_CFG3_BORRSTEN_ENABLE ((uint32_t)0x00000040) /*!< BOR reset enable */ #define RCC_CFG3_BORRSTEN_DISABLE ((uint32_t)0x00000000) /*!< BOR reset disable */ /*!< TRNG1MPRE configuration */ #define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */ #define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ #define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ #define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ #define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ #define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ #define RCC_CFG3_TRNG1MPRES_VAL1 ((uint32_t)0x00000000) /*!< TRNG 1M source clock is divided by 2 */ #define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */ #define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */ #define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 4 */ #define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 6 */ #define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 6 */ #define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 8 */ #define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 8 */ #define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 10 */ #define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 10 */ #define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 12 */ #define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 12 */ #define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 14 */ #define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 14 */ #define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 16 */ #define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 16 */ #define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 18 */ #define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 18 */ #define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 20 */ #define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 20 */ #define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 22 */ #define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 22 */ #define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 24 */ #define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 24 */ #define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 26 */ #define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 26 */ #define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 28 */ #define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 28 */ #define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 30 */ #define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 30 */ #define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 32 */ #define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 32 */ /*!< TRNG1MSEL configuration */ #define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */ #define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */ #define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */ /*!< TRNG1MEN configuration */ #define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ #define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */ #define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ /* */ /******************************************************************************/ /******************* Bit definition for GPIO_PL_CFG register *******************/ #define GPIO_PL_CFG_PMODE ((uint32_t)0x33333333) /*!< Port x mode bits */ #define GPIO_PL_CFG_PMODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_PL_CFG_PMODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_PL_CFG_PMODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_PL_CFG_PMODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_PL_CFG_PMODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_PL_CFG_PMODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_PL_CFG_PMODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_PL_CFG_PMODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define GPIO_PL_CFG_PMODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_PL_CFG_PMODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define GPIO_PL_CFG_PMODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ #define GPIO_PL_CFG_PCFG0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_PL_CFG_PCFG0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_PL_CFG_PCFG1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_PL_CFG_PCFG2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_PL_CFG_PCFG3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_PL_CFG_PCFG4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_PL_CFG_PCFG5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_PL_CFG_PCFG6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ #define GPIO_PL_CFG_PCFG7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_PL_CFG_PCFG7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ #define GPIO_PL_CFG_PCFG7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ /******************* Bit definition for GPIO_PH_CFG register *******************/ #define GPIO_PH_CFG_PMODE ((uint32_t)0x33333333) /*!< Port x mode bits */ #define GPIO_PH_CFG_PMODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_PH_CFG_PMODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE1 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_PH_CFG_PMODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_PH_CFG_PMODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_PH_CFG_PMODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_PH_CFG_PMODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_PH_CFG_PMODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_PH_CFG_PMODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define GPIO_PH_CFG_PMODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_PH_CFG_PMODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define GPIO_PH_CFG_PMODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ #define GPIO_PH_CFG_PCFG8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_PH_CFG_PCFG8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_PH_CFG_PCFG9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_PH_CFG_PCFG10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_PH_CFG_PCFG11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_PH_CFG_PCFG12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_PH_CFG_PCFG13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_PH_CFG_PCFG14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ #define GPIO_PH_CFG_PCFG15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_PH_CFG_PCFG15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ #define GPIO_PH_CFG_PCFG15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ /*!<****************** Bit definition for GPIO_PID register *******************/ #define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ #define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ #define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ #define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ #define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ #define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ #define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ #define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ #define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ #define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ #define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ #define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ #define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ #define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ #define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ #define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ /******************* Bit definition for GPIO_POD register *******************/ #define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ #define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ #define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ #define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ #define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ #define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ #define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ #define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ #define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ #define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ #define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ #define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ #define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ #define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ #define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ #define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ /****************** Bit definition for GPIO_PBSC register *******************/ #define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ #define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ #define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ #define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ #define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ #define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ #define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ #define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ #define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ #define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ #define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ #define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ #define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ #define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ #define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ #define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ #define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ #define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ #define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ #define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ #define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ #define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ #define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ #define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ #define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ #define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ #define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ #define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ #define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ #define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ #define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ #define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ /******************* Bit definition for GPIO_PBC register *******************/ #define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ #define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ #define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ #define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ #define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ #define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ #define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ #define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ #define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ #define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ #define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ #define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ #define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ #define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ #define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ #define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ /****************** Bit definition for GPIO_PLOCK_CFG register *******************/ #define GPIO_PLOCK_CFG_PLOCK_CFG0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ #define GPIO_PLOCK_CFG_PLOCK_CFG1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ #define GPIO_PLOCK_CFG_PLOCK_CFG2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ #define GPIO_PLOCK_CFG_PLOCK_CFG3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ #define GPIO_PLOCK_CFG_PLOCK_CFG4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ #define GPIO_PLOCK_CFG_PLOCK_CFG5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ #define GPIO_PLOCK_CFG_PLOCK_CFG6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ #define GPIO_PLOCK_CFG_PLOCK_CFG7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ #define GPIO_PLOCK_CFG_PLOCK_CFG8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ #define GPIO_PLOCK_CFG_PLOCK_CFG9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ #define GPIO_PLOCK_CFG_PLOCK_CFG10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ #define GPIO_PLOCK_CFG_PLOCK_CFG11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ #define GPIO_PLOCK_CFG_PLOCK_CFG12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ #define GPIO_PLOCK_CFG_PLOCK_CFG13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ #define GPIO_PLOCK_CFG_PLOCK_CFG14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ #define GPIO_PLOCK_CFG_PLOCK_CFG15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ #define GPIO_PLOCK_CFG_PLOCKK_CFG ((uint32_t)0x00010000) /*!< Lock key */ /******************* Bit definition for GPIO_DS_CFG register *******************/ #define GPIO_DS_CFG0 ((uint16_t)0x0001) /*!< Port x Drive bit 0 */ #define GPIO_DS_CFG1 ((uint16_t)0x0002) /*!< Port x Drive bit 1 */ #define GPIO_DS_CFG2 ((uint16_t)0x0004) /*!< Port x Drive bit 2 */ #define GPIO_DS_CFG3 ((uint16_t)0x0008) /*!< Port x Drive bit 3 */ #define GPIO_DS_CFG4 ((uint16_t)0x0010) /*!< Port x Drive bit 4 */ #define GPIO_DS_CFG5 ((uint16_t)0x0020) /*!< Port x Drive bit 5 */ #define GPIO_DS_CFG6 ((uint16_t)0x0040) /*!< Port x Drive bit 6 */ #define GPIO_DS_CFG7 ((uint16_t)0x0080) /*!< Port x Drive bit 7 */ #define GPIO_DS_CFG8 ((uint16_t)0x0100) /*!< Port x Drive bit 8 */ #define GPIO_DS_CFG9 ((uint16_t)0x0200) /*!< Port x Drive bit 9 */ #define GPIO_DS_CFG10 ((uint16_t)0x0400) /*!< Port x Drive bit 10 */ #define GPIO_DS_CFG11 ((uint16_t)0x0800) /*!< Port x Drive bit 11 */ #define GPIO_DS_CFG12 ((uint16_t)0x1000) /*!< Port x Drive bit 12 */ #define GPIO_DS_CFG13 ((uint16_t)0x2000) /*!< Port x Drive bit 13 */ #define GPIO_DS_CFG14 ((uint16_t)0x4000) /*!< Port x Drive bit 14 */ #define GPIO_DS_CFG15 ((uint16_t)0x8000) /*!< Port x Drive bit 15 */ /******************* Bit definition for GPIO_SR_CFG register *******************/ #define GPIO_SR_CFG0 ((uint16_t)0x0001) /*!< Port x Turn bit 0 */ #define GPIO_SR_CFG1 ((uint16_t)0x0002) /*!< Port x Turn bit 1 */ #define GPIO_SR_CFG2 ((uint16_t)0x0004) /*!< Port x Turn bit 2 */ #define GPIO_SR_CFG3 ((uint16_t)0x0008) /*!< Port x Turn bit 3 */ #define GPIO_SR_CFG4 ((uint16_t)0x0010) /*!< Port x Turn bit 4 */ #define GPIO_SR_CFG5 ((uint16_t)0x0020) /*!< Port x Turn bit 5 */ #define GPIO_SR_CFG6 ((uint16_t)0x0040) /*!< Port x Turn bit 6 */ #define GPIO_SR_CFG7 ((uint16_t)0x0080) /*!< Port x Turn bit 7 */ #define GPIO_SR_CFG8 ((uint16_t)0x0100) /*!< Port x Turn bit 8 */ #define GPIO_SR_CFG9 ((uint16_t)0x0200) /*!< Port x Turn bit 9 */ #define GPIO_SR_CFG10 ((uint16_t)0x0400) /*!< Port x Turn bit 10 */ #define GPIO_SR_CFG11 ((uint16_t)0x0800) /*!< Port x Turn bit 11 */ #define GPIO_SR_CFG12 ((uint16_t)0x1000) /*!< Port x Turn bit 12 */ #define GPIO_SR_CFG13 ((uint16_t)0x2000) /*!< Port x Turn bit 13 */ #define GPIO_SR_CFG14 ((uint16_t)0x4000) /*!< Port x Turn bit 14 */ #define GPIO_SR_CFG15 ((uint16_t)0x8000) /*!< Port x Turn bit 15 */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for AFIO_ECTRL register *******************/ #define AFIO_ECTRL_PIN_SEL ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ #define AFIO_ECTRL_PIN_SEL_0 ((uint8_t)0x01) /*!< Bit 0 */ #define AFIO_ECTRL_PIN_SEL_1 ((uint8_t)0x02) /*!< Bit 1 */ #define AFIO_ECTRL_PIN_SEL_2 ((uint8_t)0x04) /*!< Bit 2 */ #define AFIO_ECTRL_PIN_SEL_3 ((uint8_t)0x08) /*!< Bit 3 */ /*!< PIN configuration */ #define AFIO_ECTRL_PIN_SEL_PIN0 ((uint8_t)0x00) /*!< Pin 0 selected */ #define AFIO_ECTRL_PIN_SEL_PIN1 ((uint8_t)0x01) /*!< Pin 1 selected */ #define AFIO_ECTRL_PIN_SEL_PIN2 ((uint8_t)0x02) /*!< Pin 2 selected */ #define AFIO_ECTRL_PIN_SEL_PIN3 ((uint8_t)0x03) /*!< Pin 3 selected */ #define AFIO_ECTRL_PIN_SEL_PIN4 ((uint8_t)0x04) /*!< Pin 4 selected */ #define AFIO_ECTRL_PIN_SEL_PIN5 ((uint8_t)0x05) /*!< Pin 5 selected */ #define AFIO_ECTRL_PIN_SEL_PIN6 ((uint8_t)0x06) /*!< Pin 6 selected */ #define AFIO_ECTRL_PIN_SEL_PIN7 ((uint8_t)0x07) /*!< Pin 7 selected */ #define AFIO_ECTRL_PIN_SEL_PIN8 ((uint8_t)0x08) /*!< Pin 8 selected */ #define AFIO_ECTRL_PIN_SEL_PIN9 ((uint8_t)0x09) /*!< Pin 9 selected */ #define AFIO_ECTRL_PIN_SEL_PIN10 ((uint8_t)0x0A) /*!< Pin 10 selected */ #define AFIO_ECTRL_PIN_SEL_PIN11 ((uint8_t)0x0B) /*!< Pin 11 selected */ #define AFIO_ECTRL_PIN_SEL_PIN12 ((uint8_t)0x0C) /*!< Pin 12 selected */ #define AFIO_ECTRL_PIN_SEL_PIN13 ((uint8_t)0x0D) /*!< Pin 13 selected */ #define AFIO_ECTRL_PIN_SEL_PIN14 ((uint8_t)0x0E) /*!< Pin 14 selected */ #define AFIO_ECTRL_PIN_SEL_PIN15 ((uint8_t)0x0F) /*!< Pin 15 selected */ #define AFIO_ECTRL_PORT_SEL ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ #define AFIO_ECTRL_PORT_SEL_0 ((uint8_t)0x10) /*!< Bit 0 */ #define AFIO_ECTRL_PORT_SEL_1 ((uint8_t)0x20) /*!< Bit 1 */ #define AFIO_ECTRL_PORT_SEL_2 ((uint8_t)0x40) /*!< Bit 2 */ /*!< PORT configuration */ #define AFIO_ECTRL_PORT_SEL_PA ((uint8_t)0x00) /*!< Port A selected */ #define AFIO_ECTRL_PORT_SEL_PB ((uint8_t)0x10) /*!< Port B selected */ #define AFIO_ECTRL_PORT_SEL_PC ((uint8_t)0x20) /*!< Port C selected */ #define AFIO_ECTRL_PORT_SEL_PD ((uint8_t)0x30) /*!< Port D selected */ #define AFIO_ECTRL_PORT_SEL_PE ((uint8_t)0x40) /*!< Port E selected */ #define AFIO_ECTRL_EOE ((uint8_t)0x80) /*!< Event Output Enable */ /****************** Bit definition for AFIO_RMP_CFG register *******************/ #define AFIO_RMP_CFG_SPI1_RMP_0 ((uint32_t)0x00000001) /*!< SPI1_RMP_0 remapping */ #define AFIO_RMP_CFG_I2C1_RMP ((uint32_t)0x00000002) /*!< I2C1 remapping */ #define AFIO_RMP_CFG_USART1_RMP ((uint32_t)0x00000004) /*!< USART1 remapping */ #define AFIO_RMP_CFG_USART2_RMP_0 ((uint32_t)0x00000008) /*!< USART2_RMP_0 remapping */ #define AFIO_RMP_CFG_USART3_RMP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ #define AFIO_RMP_CFG_USART3_RMP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define AFIO_RMP_CFG_USART3_RMP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ /* USART3_REMAP configuration */ #define AFIO_RMP_CFG_USART3_RMP_NONE \ ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_RMP_CFG_USART3_RMP_PART \ ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ #define AFIO_RMP_CFG_USART3_RMP_ALL \ ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ #define AFIO_RMP_CFG_TIM1_RMP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ #define AFIO_RMP_CFG_TIM1_RMP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define AFIO_RMP_CFG_TIM1_RMP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ /*!< TIM1_REMAP configuration */ #define AFIO_RMP_CFG_TIM1_RMP_NONE \ ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, \ CH2N/PB14, CH3N/PB15) */ #define AFIO_RMP_CFG_TIM1_RMP_PART \ ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, \ CH2N/PB0, CH3N/PB1) */ #define AFIO_RMP_CFG_TIM1_RMP_ALL \ ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, \ CH2N/PE10, CH3N/PE12) */ #define AFIO_RMP_CFG_TIM2_RMP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ #define AFIO_RMP_CFG_TIM2_RMP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define AFIO_RMP_CFG_TIM2_RMP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ /*!< TIM2_REMAP configuration */ #define AFIO_RMP_CFG_TIM2_RMP_NONE ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_RMP_CFG_TIM2_RMP_PART1 \ ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ #define AFIO_RMP_CFG_TIM2_RMP_PART2 \ ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ #define AFIO_RMP_CFG_TIM2_RMP_ALL \ ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) \ */ #define AFIO_RMP_CFG_TIM3_RMP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ #define AFIO_RMP_CFG_TIM3_RMP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define AFIO_RMP_CFG_TIM3_RMP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ /*!< TIM3_REMAP configuration */ #define AFIO_RMP_CFG_TIM3_RMP_NONE ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_RMP_CFG_TIM3_RMP_PART ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ #define AFIO_RMP_CFG_TIM3_RMP_ALL ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ #define AFIO_RMP_CFG_TIM4_RMP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ #define AFIO_RMP_CFG_CAN1_RMP ((uint32_t)0x00006000) /*!< CAN1_RMP[1:0] bits (CAN1 Alternate function remapping) */ #define AFIO_RMP_CFG_CAN1_RMP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ #define AFIO_RMP_CFG_CAN1_RMP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ /*!< CAN1_REMAP configuration */ #define AFIO_RMP_CFG_CAN1_RMP_RMP1 ((uint32_t)0x00000000) /*!< CAN1RX mapped to PA11, CAN1TX mapped to PA12 */ #define AFIO_RMP_CFG_CAN1_RMP_RMP2 ((uint32_t)0x00004000) /*!< CAN1RX mapped to PB8, CAN1TX mapped to PB9 */ #define AFIO_RMP_CFG_CAN1_RMP_RMP3 ((uint32_t)0x00006000) /*!< CAN1RX mapped to PD0, CAN1TX mapped to PD1 */ #define AFIO_RMP_CFG_CAN1_RMP_RMP4 ((uint32_t)0x00002000) /*!< CAN1RX mapped to PD12, CAN1TX mapped to PD13 */ #define AFIO_RMP_CFG_PD01_RMP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ #define AFIO_RMP_CFG_TIM5CH4_RMP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ #define AFIO_RMP_CFG_ADC1_ETRI_RMP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ #define AFIO_RMP_CFG_ADC1_ETRR_RMP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ #define AFIO_RMP_CFG_ADC2_ETRI_RMP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ #define AFIO_RMP_CFG_ADC2_ETRR_RMP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ #define AFIO_RMP_CFG_MII_RMII_SEL ((uint32_t)0x00800000) /*!< ETH MAC MII_RMII_SEL remapping */ /*!< SWJ_CFG configuration */ #define AFIO_RMP_CFG_SW_JTAG_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_RMP_CFG_SW_JTAG_CFG0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define AFIO_RMP_CFG_SW_JTAG_CFG1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define AFIO_RMP_CFG_SW_JTAG_CFG2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define AFIO_RMP_CFG_SW_JTAG_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_RMP_CFG_SW_JTAG_CFG_NO_NJTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST \ */ #define AFIO_RMP_CFG_SW_JTAG_CFG_SW_ENABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ #define AFIO_RMP_CFG_SW_JTAG_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ /***************** Bit definition for AFIO_EXTI_CFG1 register *****************/ #define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ #define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ #define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ #define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ #define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ #define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ #define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ #define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ #define AFIO_EXTI_CFG1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ #define AFIO_EXTI_CFG1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ #define AFIO_EXTI_CFG1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ /*!< EXTI1 configuration */ #define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ #define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ #define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ #define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ #define AFIO_EXTI_CFG1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ #define AFIO_EXTI_CFG1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ #define AFIO_EXTI_CFG1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ /*!< EXTI2 configuration */ #define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ #define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ #define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ #define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ #define AFIO_EXTI_CFG1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ #define AFIO_EXTI_CFG1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ #define AFIO_EXTI_CFG1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ /*!< EXTI3 configuration */ #define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ #define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ #define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ #define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ #define AFIO_EXTI_CFG1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ #define AFIO_EXTI_CFG1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ #define AFIO_EXTI_CFG1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ /***************** Bit definition for AFIO_EXTI_CFG2 register *****************/ #define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ #define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ #define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ #define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ #define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ #define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ #define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ #define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ #define AFIO_EXTI_CFG2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ #define AFIO_EXTI_CFG2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ #define AFIO_EXTI_CFG2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ /* EXTI5 configuration */ #define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ #define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ #define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ #define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ #define AFIO_EXTI_CFG2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ #define AFIO_EXTI_CFG2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ #define AFIO_EXTI_CFG2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ /*!< EXTI6 configuration */ #define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ #define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ #define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ #define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ #define AFIO_EXTI_CFG2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ #define AFIO_EXTI_CFG2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ #define AFIO_EXTI_CFG2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ /*!< EXTI7 configuration */ #define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ #define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ #define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ #define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ #define AFIO_EXTI_CFG2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ #define AFIO_EXTI_CFG2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ #define AFIO_EXTI_CFG2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ /***************** Bit definition for AFIO_EXTI_CFG3 register *****************/ #define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ #define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ #define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ #define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ #define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ #define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ #define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ #define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ #define AFIO_EXTI_CFG3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ #define AFIO_EXTI_CFG3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ #define AFIO_EXTI_CFG3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ /*!< EXTI9 configuration */ #define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ #define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ #define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ #define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ #define AFIO_EXTI_CFG3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ #define AFIO_EXTI_CFG3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ #define AFIO_EXTI_CFG3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ /*!< EXTI10 configuration */ #define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ #define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ #define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ #define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ #define AFIO_EXTI_CFG3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ #define AFIO_EXTI_CFG3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ #define AFIO_EXTI_CFG3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ /*!< EXTI11 configuration */ #define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ #define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ #define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ #define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ #define AFIO_EXTI_CFG3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ #define AFIO_EXTI_CFG3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ #define AFIO_EXTI_CFG3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ /***************** Bit definition for AFIO_EXTI_CFG4 register *****************/ #define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ #define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ #define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ #define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ /* EXTI12 configuration */ #define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ #define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ #define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ #define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ #define AFIO_EXTI_CFG4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ #define AFIO_EXTI_CFG4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ #define AFIO_EXTI_CFG4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ /* EXTI13 configuration */ #define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ #define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ #define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ #define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ #define AFIO_EXTI_CFG4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ #define AFIO_EXTI_CFG4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ #define AFIO_EXTI_CFG4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ /*!< EXTI14 configuration */ #define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ #define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ #define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ #define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ #define AFIO_EXTI_CFG4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ #define AFIO_EXTI_CFG4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ #define AFIO_EXTI_CFG4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ /*!< EXTI15 configuration */ #define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ #define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ #define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ #define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ #define AFIO_EXTI_CFG4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ #define AFIO_EXTI_CFG4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ #define AFIO_EXTI_CFG4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ /****************** Bit definition for AFIO_RMP_CFG3 register *******************/ #define AFIO_RMP_CFG3_SDIO_RMP ((uint32_t)0x00000001) /*!< SDIO remapping */ #define AFIO_RMP_CFG3_CAN2_RMP ((uint32_t)0x00000006) /*!