From cabdbf5bbf8faadee94d01316509ce6e1e82c56f Mon Sep 17 00:00:00 2001 From: ZYH Date: Wed, 23 Oct 2019 15:04:30 +0800 Subject: [PATCH] =?UTF-8?q?[libcpu][M7]=E4=BF=AE=E5=A4=8Dcache=E7=BC=96?= =?UTF-8?q?=E8=AF=91=E8=AD=A6=E5=91=8A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: ZYH --- libcpu/arm/cortex-m7/cpu_cache.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 4a1a9c2201..350b819c00 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -72,15 +72,15 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) { - SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); } else if (ops & RT_HW_CACHE_FLUSH) { - SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte); } else if (ops & RT_HW_CACHE_INVALIDATE) { - SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); } else { -- GitLab