From 7e2a0687491449b491c8a116c6cffcd327cde3da Mon Sep 17 00:00:00 2001 From: lishaohui Date: Thu, 31 Mar 2022 11:11:31 +0800 Subject: [PATCH] add VeriSilicon projects --- projects/VeriSilicon/imports.yml | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 projects/VeriSilicon/imports.yml diff --git a/projects/VeriSilicon/imports.yml b/projects/VeriSilicon/imports.yml new file mode 100644 index 000000000..0c4fa19e4 --- /dev/null +++ b/projects/VeriSilicon/imports.yml @@ -0,0 +1,53 @@ +--- +group: + name: 'VeriSilicon' + description: '' + projects: + - name: 'TIM-VX' + description: '' + mirrorRelease: false + topic: '' +- name: 'tensorflow' + description: '' + mirrorRelease: false + topic: '' +- name: 'tflite-vx-delegate' + description: '' + mirrorRelease: false + topic: '' +- name: 'acuitylite' + description: '' + mirrorRelease: false + topic: '' +- name: 'tvm' + description: '' + mirrorRelease: false + topic: '' +- name: 'mlcommons-inference' + description: '' + mirrorRelease: false + topic: '' +- name: 'ffmpeg' + description: '' + mirrorRelease: false + topic: '' +- name: 'acuity-models' + description: '' + mirrorRelease: false + topic: '' +- name: 'solios-x-device-plugin' + description: '' + mirrorRelease: false + topic: '' +- name: 'vpe' + description: '' + mirrorRelease: false + topic: '' +- name: 'acuity-dataset' + description: '' + mirrorRelease: false + topic: '' +- name: 'caffe' + description: '' + mirrorRelease: false + topic: '' \ No newline at end of file -- GitLab