diff --git a/Global/SynopsysVCS.gitignore b/Global/SynopsysVCS.gitignore
index 9731789665b37a25ed907b7faa32179fa18a53ec..eed2432fb787a27d0b58416a1357b9fca6e39c75 100644
--- a/Global/SynopsysVCS.gitignore
+++ b/Global/SynopsysVCS.gitignore
@@ -1,23 +1,36 @@
-# Waveforms
-*.vpd
+# Waveform formats
 *.vcd
+*.vpd
 *.evcd
+*.fsdb
 
-# Binary files
+# Default name of the simulation executable.  A different name can be 
+# specified with this switch (the associated daidir database name is 
+# also taken from here):  -o <path>/<filename>
 simv
 
-# Directories used for compilation
-csrc/
+# Generated for Verilog and VHDL top configs
 simv.daidir/
+simv.db.dir/
 
-# Log files
-*.log
+# Infrastructure necessary to co-simulate SystemC models with 
+# Verilog/VHDL models.  An alternate directory may be specified with this
+# switch:  -Mdir=<directory_path>
+csrc/
 
-# DVE, UCLI related files
-DVEfiles/
-ucli*
-*.key
+# Log file - the following switch allows to specify the file that will be
+# used to write all messages from simulation:  -l <filename>
+*.log
 
-# Coverage related files
+# Coverage results (generated with urg) and database location.  The 
+# following switch can also be used:  urg -dir <coverage_directory>.vdb
 simv.vdb/
 urgReport/
+
+# DVE and UCLI related files.
+DVEfiles/
+ucli.key
+
+# When the design is elaborated for DirectC, the following file is created
+# with declarations for C/C++ functions.
+vc_hdrs.h