diff --git a/libavcodec/arm/dsputil_neon.c b/libavcodec/arm/dsputil_neon.c index efe07e117282d19a975cbe9e9b4ee9809036cc39..6b8b41e7253cd1346e37ff4abb1271d02ba03703 100644 --- a/libavcodec/arm/dsputil_neon.c +++ b/libavcodec/arm/dsputil_neon.c @@ -173,6 +173,8 @@ void ff_int32_to_float_fmul_scalar_neon(float *dst, const int *src, float mul, int len); void ff_vector_fmul_reverse_neon(float *dst, const float *src0, const float *src1, int len); +void ff_vector_fmul_add_neon(float *dst, const float *src0, const float *src1, + const float *src2, int len); void ff_vector_clipf_neon(float *dst, const float *src, float min, float max, int len); @@ -292,6 +294,7 @@ void ff_dsputil_init_neon(DSPContext *c, AVCodecContext *avctx) c->scalarproduct_float = ff_scalarproduct_float_neon; c->int32_to_float_fmul_scalar = ff_int32_to_float_fmul_scalar_neon; c->vector_fmul_reverse = ff_vector_fmul_reverse_neon; + c->vector_fmul_add = ff_vector_fmul_add_neon; c->vector_fmul_sv_scalar[0] = ff_vector_fmul_sv_scalar_2_neon; c->vector_fmul_sv_scalar[1] = ff_vector_fmul_sv_scalar_4_neon; diff --git a/libavcodec/arm/dsputil_neon_s.S b/libavcodec/arm/dsputil_neon_s.S index 9ae7cf96cb81ff84dc960cb2ce30f8ef0c33f82d..9655f0aea616c7e42db372fddc568183dcf6076b 100644 --- a/libavcodec/arm/dsputil_neon_s.S +++ b/libavcodec/arm/dsputil_neon_s.S @@ -1076,6 +1076,33 @@ function ff_vector_fmul_reverse_neon, export=1 bx lr .endfunc +function ff_vector_fmul_add_neon, export=1 + ldr r12, [sp] + vld1.32 {q0-q1}, [r1,:128]! + vld1.32 {q8-q9}, [r2,:128]! + vld1.32 {q2-q3}, [r3,:128]! + vmul.f32 q10, q0, q8 + vmul.f32 q11, q1, q9 +1: vadd.f32 q12, q2, q10 + vadd.f32 q13, q3, q11 + pld [r1, #16] + pld [r2, #16] + pld [r3, #16] + subs r12, r12, #8 + beq 2f + vld1.32 {q0}, [r1,:128]! + vld1.32 {q8}, [r2,:128]! + vmul.f32 q10, q0, q8 + vld1.32 {q1}, [r1,:128]! + vld1.32 {q9}, [r2,:128]! + vmul.f32 q11, q1, q9 + vld1.32 {q2-q3}, [r3,:128]! + vst1.32 {q12-q13},[r0,:128]! + b 1b +2: vst1.32 {q12-q13},[r0,:128]! + bx lr + .endfunc + function ff_vector_clipf_neon, export=1 VFP vdup.32 q1, d0[1] VFP vdup.32 q0, d0[0]