drm/i915: Write zero to DPLL_MD Reg for non-SDVO output
When the output device is LVDS, maybe the pixel clock of adjusted_mode will be less than that in mode. In such case it will set the incorrect multipler factor in DPLL_MD register. So the dpll_md_reg will be reset when the output type is non-SDVO https://bugs.freedesktop.org/show_bug.cgi?id=22761Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Reviewd-by: NEric Anholt <eric@anholt.net> Signed-off-by: NEric Anholt <eric@anholt.net>
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