intel-iommu.c 104.0 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
17 18 19 20
 * Copyright (C) 2006-2008 Intel Corporation
 * Author: Ashok Raj <ashok.raj@intel.com>
 * Author: Shaohua Li <shaohua.li@intel.com>
 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
F
Fenghua Yu 已提交
21
 * Author: Fenghua Yu <fenghua.yu@intel.com>
22 23 24 25
 */

#include <linux/init.h>
#include <linux/bitmap.h>
M
mark gross 已提交
26
#include <linux/debugfs.h>
27
#include <linux/export.h>
28 29 30 31 32 33 34 35
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
M
mark gross 已提交
36
#include <linux/timer.h>
K
Kay, Allen M 已提交
37
#include <linux/iova.h>
38
#include <linux/iommu.h>
K
Kay, Allen M 已提交
39
#include <linux/intel-iommu.h>
40
#include <linux/syscore_ops.h>
41
#include <linux/tboot.h>
42
#include <linux/dmi.h>
43
#include <linux/pci-ats.h>
44
#include <asm/cacheflush.h>
45
#include <asm/iommu.h>
46

F
Fenghua Yu 已提交
47 48 49
#define ROOT_SIZE		VTD_PAGE_SIZE
#define CONTEXT_SIZE		VTD_PAGE_SIZE

50 51
#define IS_BRIDGE_HOST_DEVICE(pdev) \
			    ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
52 53
#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
54
#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
55 56 57 58 59 60 61

#define IOAPIC_RANGE_START	(0xfee00000)
#define IOAPIC_RANGE_END	(0xfeefffff)
#define IOVA_START_ADDR		(0x1000)

#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48

F
Fenghua Yu 已提交
62 63
#define MAX_AGAW_WIDTH 64

64 65 66 67 68 69 70 71
#define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)

/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
   to match. That way, we can use 'unsigned long' for PFNs with impunity. */
#define DOMAIN_MAX_PFN(gaw)	((unsigned long) min_t(uint64_t, \
				__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
#define DOMAIN_MAX_ADDR(gaw)	(((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
72

73
#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
74
#define DMA_32BIT_PFN		IOVA_PFN(DMA_BIT_MASK(32))
75
#define DMA_64BIT_PFN		IOVA_PFN(DMA_BIT_MASK(64))
M
mark gross 已提交
76

77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
/* page table handling */
#define LEVEL_STRIDE		(9)
#define LEVEL_MASK		(((u64)1 << LEVEL_STRIDE) - 1)

static inline int agaw_to_level(int agaw)
{
	return agaw + 2;
}

static inline int agaw_to_width(int agaw)
{
	return 30 + agaw * LEVEL_STRIDE;
}

static inline int width_to_agaw(int width)
{
	return (width - 30) / LEVEL_STRIDE;
}

static inline unsigned int level_to_offset_bits(int level)
{
	return (level - 1) * LEVEL_STRIDE;
}

static inline int pfn_level_offset(unsigned long pfn, int level)
{
	return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}

static inline unsigned long level_mask(int level)
{
	return -1UL << level_to_offset_bits(level);
}

static inline unsigned long level_size(int level)
{
	return 1UL << level_to_offset_bits(level);
}

static inline unsigned long align_to_level(unsigned long pfn, int level)
{
	return (pfn + level_size(level) - 1) & level_mask(level);
}
120

121 122 123 124 125
static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
	return  1 << ((lvl - 1) * LEVEL_STRIDE);
}

126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
   are never going to work. */
static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
{
	return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
}

static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
{
	return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
}
static inline unsigned long page_to_dma_pfn(struct page *pg)
{
	return mm_to_dma_pfn(page_to_pfn(pg));
}
static inline unsigned long virt_to_dma_pfn(void *p)
{
	return page_to_dma_pfn(virt_to_page(p));
}

W
Weidong Han 已提交
146 147 148
/* global iommu list, set NULL for ignored DMAR units */
static struct intel_iommu **g_iommus;

149
static void __init check_tylersburg_isoch(void);
150 151
static int rwbf_quirk;

152 153 154 155 156 157
/*
 * set to 1 to panic kernel if can't successfully enable VT-d
 * (used when kernel is launched w/ TXT)
 */
static int force_on = 0;

158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
/*
 * 0: Present
 * 1-11: Reserved
 * 12-63: Context Ptr (12 - (haw-1))
 * 64-127: Reserved
 */
struct root_entry {
	u64	val;
	u64	rsvd1;
};
#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
static inline bool root_present(struct root_entry *root)
{
	return (root->val & 1);
}
static inline void set_root_present(struct root_entry *root)
{
	root->val |= 1;
}
static inline void set_root_value(struct root_entry *root, unsigned long value)
{
	root->val |= value & VTD_PAGE_MASK;
}

static inline struct context_entry *
get_context_addr_from_root(struct root_entry *root)
{
	return (struct context_entry *)
		(root_present(root)?phys_to_virt(
		root->val & VTD_PAGE_MASK) :
		NULL);
}

191 192 193 194 195 196 197 198 199 200 201 202 203 204 205
/*
 * low 64 bits:
 * 0: present
 * 1: fault processing disable
 * 2-3: translation type
 * 12-63: address space root
 * high 64 bits:
 * 0-2: address width
 * 3-6: aval
 * 8-23: domain id
 */
struct context_entry {
	u64 lo;
	u64 hi;
};
206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250

static inline bool context_present(struct context_entry *context)
{
	return (context->lo & 1);
}
static inline void context_set_present(struct context_entry *context)
{
	context->lo |= 1;
}

static inline void context_set_fault_enable(struct context_entry *context)
{
	context->lo &= (((u64)-1) << 2) | 1;
}

static inline void context_set_translation_type(struct context_entry *context,
						unsigned long value)
{
	context->lo &= (((u64)-1) << 4) | 3;
	context->lo |= (value & 3) << 2;
}

static inline void context_set_address_root(struct context_entry *context,
					    unsigned long value)
{
	context->lo |= value & VTD_PAGE_MASK;
}

static inline void context_set_address_width(struct context_entry *context,
					     unsigned long value)
{
	context->hi |= value & 7;
}

static inline void context_set_domain_id(struct context_entry *context,
					 unsigned long value)
{
	context->hi |= (value & ((1 << 16) - 1)) << 8;
}

static inline void context_clear_entry(struct context_entry *context)
{
	context->lo = 0;
	context->hi = 0;
}
251

252 253 254 255 256
/*
 * 0: readable
 * 1: writable
 * 2-6: reserved
 * 7: super page
257 258
 * 8-10: available
 * 11: snoop behavior
259 260 261 262 263 264
 * 12-63: Host physcial address
 */
struct dma_pte {
	u64 val;
};

265 266 267 268 269 270 271 272 273 274 275 276 277 278 279
static inline void dma_clear_pte(struct dma_pte *pte)
{
	pte->val = 0;
}

static inline void dma_set_pte_readable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_READ;
}

static inline void dma_set_pte_writable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_WRITE;
}

280 281 282 283 284
static inline void dma_set_pte_snp(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_SNP;
}

285 286 287 288 289 290 291
static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
{
	pte->val = (pte->val & ~3) | (prot & 3);
}

static inline u64 dma_pte_addr(struct dma_pte *pte)
{
292 293 294 295
#ifdef CONFIG_64BIT
	return pte->val & VTD_PAGE_MASK;
#else
	/* Must have a full atomic 64-bit read */
296
	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
297
#endif
298 299
}

300
static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
301
{
302
	pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
303 304 305 306 307 308
}

static inline bool dma_pte_present(struct dma_pte *pte)
{
	return (pte->val & 3) != 0;
}
309

310 311 312 313 314
static inline bool dma_pte_superpage(struct dma_pte *pte)
{
	return (pte->val & (1 << 7));
}

315 316 317 318 319
static inline int first_pte_in_page(struct dma_pte *pte)
{
	return !((unsigned long)pte & ~VTD_PAGE_MASK);
}

320 321 322 323 324 325
/*
 * This domain is a statically identity mapping domain.
 *	1. This domain creats a static 1:1 mapping to all usable memory.
 * 	2. It maps to each iommu if successful.
 *	3. Each iommu mapps to this domain if successful.
 */
326 327
static struct dmar_domain *si_domain;
static int hw_pass_through = 1;
328

W
Weidong Han 已提交
329
/* devices under the same p2p bridge are owned in one domain */
330
#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
W
Weidong Han 已提交
331

332 333 334 335 336
/* domain represents a virtual machine, more than one devices
 * across iommus may be owned in one domain, e.g. kvm guest.
 */
#define DOMAIN_FLAG_VIRTUAL_MACHINE	(1 << 1)

337 338 339
/* si_domain contains mulitple devices */
#define DOMAIN_FLAG_STATIC_IDENTITY	(1 << 2)

340 341
struct dmar_domain {
	int	id;			/* domain id */
342
	int	nid;			/* node id */
343
	unsigned long iommu_bmp;	/* bitmap of iommus this domain uses*/
344 345 346 347 348 349 350 351 352 353

	struct list_head devices; 	/* all devices' list */
	struct iova_domain iovad;	/* iova's that belong to this domain */

	struct dma_pte	*pgd;		/* virtual address */
	int		gaw;		/* max guest address width */

	/* adjusted guest address width, 0 is level 2 30-bit */
	int		agaw;

W
Weidong Han 已提交
354
	int		flags;		/* flags to find out type of domain */
W
Weidong Han 已提交
355 356

	int		iommu_coherency;/* indicate coherency of iommu access */
357
	int		iommu_snooping; /* indicate snooping control feature*/
358
	int		iommu_count;	/* reference count of iommu */
359 360 361
	int		iommu_superpage;/* Level of superpages supported:
					   0 == 4KiB (no superpages), 1 == 2MiB,
					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
362
	spinlock_t	iommu_lock;	/* protect iommu set in domain */
363
	u64		max_addr;	/* maximum mapped address */
364 365
};

366 367 368 369
/* PCI domain-device relationship */
struct device_domain_info {
	struct list_head link;	/* link to domain siblings */
	struct list_head global; /* link to global list */
370 371
	int segment;		/* PCI domain */
	u8 bus;			/* PCI bus number */
372
	u8 devfn;		/* PCI devfn number */
373
	struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
Y
Yu Zhao 已提交
374
	struct intel_iommu *iommu; /* IOMMU used by this device */
375 376 377
	struct dmar_domain *domain; /* pointer to domain */
};

M
mark gross 已提交
378 379 380 381
static void flush_unmaps_timeout(unsigned long data);

DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);

382 383 384 385 386 387 388 389 390
#define HIGH_WATER_MARK 250
struct deferred_flush_tables {
	int next;
	struct iova *iova[HIGH_WATER_MARK];
	struct dmar_domain *domain[HIGH_WATER_MARK];
};

static struct deferred_flush_tables *deferred_flush;

M
mark gross 已提交
391 392 393 394 395 396 397 398 399
/* bitmap for indexing intel_iommus */
static int g_num_of_iommus;

static DEFINE_SPINLOCK(async_umap_flush_lock);
static LIST_HEAD(unmaps_to_do);

static int timer_on;
static long list_size;

400 401
static void domain_remove_dev_info(struct dmar_domain *domain);

402
#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
403 404 405
int dmar_disabled = 0;
#else
int dmar_disabled = 1;
406
#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
407

408
static int dmar_map_gfx = 1;
409
static int dmar_forcedac;
M
mark gross 已提交
410
static int intel_iommu_strict;
411
static int intel_iommu_superpage = 1;
412

413 414 415
int intel_iommu_gfx_mapped;
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);

416 417 418 419
#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
static LIST_HEAD(device_domain_list);

420 421
static struct iommu_ops intel_iommu_ops;

422 423 424 425 426
static int __init intel_iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;
	while (*str) {
427 428 429 430
		if (!strncmp(str, "on", 2)) {
			dmar_disabled = 0;
			printk(KERN_INFO "Intel-IOMMU: enabled\n");
		} else if (!strncmp(str, "off", 3)) {
431
			dmar_disabled = 1;
432
			printk(KERN_INFO "Intel-IOMMU: disabled\n");
433 434 435 436
		} else if (!strncmp(str, "igfx_off", 8)) {
			dmar_map_gfx = 0;
			printk(KERN_INFO
				"Intel-IOMMU: disable GFX device mapping\n");
437
		} else if (!strncmp(str, "forcedac", 8)) {
M
mark gross 已提交
438
			printk(KERN_INFO
439 440
				"Intel-IOMMU: Forcing DAC for PCI devices\n");
			dmar_forcedac = 1;
M
mark gross 已提交
441 442 443 444
		} else if (!strncmp(str, "strict", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable batched IOTLB flush\n");
			intel_iommu_strict = 1;
445 446 447 448
		} else if (!strncmp(str, "sp_off", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable supported super page\n");
			intel_iommu_superpage = 0;
449 450 451 452 453 454 455 456 457 458 459 460 461 462
		}

		str += strcspn(str, ",");
		while (*str == ',')
			str++;
	}
	return 0;
}
__setup("intel_iommu=", intel_iommu_setup);

static struct kmem_cache *iommu_domain_cache;
static struct kmem_cache *iommu_devinfo_cache;
static struct kmem_cache *iommu_iova_cache;

463
static inline void *alloc_pgtable_page(int node)
464
{
465 466
	struct page *page;
	void *vaddr = NULL;
467

468 469 470
	page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
	if (page)
		vaddr = page_address(page);
471
	return vaddr;
472 473 474 475 476 477 478 479 480
}

static inline void free_pgtable_page(void *vaddr)
{
	free_page((unsigned long)vaddr);
}

static inline void *alloc_domain_mem(void)
{
481
	return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
482 483
}

K
Kay, Allen M 已提交
484
static void free_domain_mem(void *vaddr)
485 486 487 488 489 490
{
	kmem_cache_free(iommu_domain_cache, vaddr);
}

static inline void * alloc_devinfo_mem(void)
{
491
	return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
492 493 494 495 496 497 498 499 500
}

static inline void free_devinfo_mem(void *vaddr)
{
	kmem_cache_free(iommu_devinfo_cache, vaddr);
}

struct iova *alloc_iova_mem(void)
{
501
	return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
502 503 504 505 506 507 508
}

void free_iova_mem(struct iova *iova)
{
	kmem_cache_free(iommu_iova_cache, iova);
}

W
Weidong Han 已提交
509

F
Fenghua Yu 已提交
510
static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
W
Weidong Han 已提交
511 512 513 514 515
{
	unsigned long sagaw;
	int agaw = -1;

	sagaw = cap_sagaw(iommu->cap);
F
Fenghua Yu 已提交
516
	for (agaw = width_to_agaw(max_gaw);
W
Weidong Han 已提交
517 518 519 520 521 522 523 524
	     agaw >= 0; agaw--) {
		if (test_bit(agaw, &sagaw))
			break;
	}

	return agaw;
}

F
Fenghua Yu 已提交
525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542
/*
 * Calculate max SAGAW for each iommu.
 */
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
}

/*
 * calculate agaw for each iommu.
 * "SAGAW" may be different across iommus, use a default agaw, and
 * get a supported less agaw for iommus that don't support the default agaw.
 */
int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
}

543
/* This functionin only returns single iommu in a domain */
544 545 546 547
static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
{
	int iommu_id;

548
	/* si_domain and vm domain should not get here. */
549
	BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
550
	BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
551

552 553 554 555 556 557 558
	iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
	if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
		return NULL;

	return g_iommus[iommu_id];
}

W
Weidong Han 已提交
559 560 561 562 563 564
static void domain_update_iommu_coherency(struct dmar_domain *domain)
{
	int i;

	domain->iommu_coherency = 1;

565
	for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
W
Weidong Han 已提交
566 567 568 569 570 571 572
		if (!ecap_coherent(g_iommus[i]->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
}

573 574 575 576 577 578
static void domain_update_iommu_snooping(struct dmar_domain *domain)
{
	int i;

	domain->iommu_snooping = 1;

579
	for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
580 581 582 583 584 585 586
		if (!ecap_sc_support(g_iommus[i]->ecap)) {
			domain->iommu_snooping = 0;
			break;
		}
	}
}

587 588
static void domain_update_iommu_superpage(struct dmar_domain *domain)
{
589 590 591
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	int mask = 0xf;
592 593 594 595 596 597

	if (!intel_iommu_superpage) {
		domain->iommu_superpage = 0;
		return;
	}

598 599 600
	/* set iommu_superpage to the smallest common denominator */
	for_each_active_iommu(iommu, drhd) {
		mask &= cap_super_page_val(iommu->cap);
601 602 603 604 605 606 607
		if (!mask) {
			break;
		}
	}
	domain->iommu_superpage = fls(mask);
}

608 609 610 611 612
/* Some capabilities may be different across iommus */
static void domain_update_iommu_cap(struct dmar_domain *domain)
{
	domain_update_iommu_coherency(domain);
	domain_update_iommu_snooping(domain);
613
	domain_update_iommu_superpage(domain);
614 615
}

616
static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
617 618 619 620 621 622 623
{
	struct dmar_drhd_unit *drhd = NULL;
	int i;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
624 625
		if (segment != drhd->segment)
			continue;
626

627
		for (i = 0; i < drhd->devices_cnt; i++) {
D
Dirk Hohndel 已提交
628 629
			if (drhd->devices[i] &&
			    drhd->devices[i]->bus->number == bus &&
630 631
			    drhd->devices[i]->devfn == devfn)
				return drhd->iommu;
632 633
			if (drhd->devices[i] &&
			    drhd->devices[i]->subordinate &&
634 635 636 637
			    drhd->devices[i]->subordinate->number <= bus &&
			    drhd->devices[i]->subordinate->subordinate >= bus)
				return drhd->iommu;
		}
638 639 640 641 642 643 644 645

		if (drhd->include_all)
			return drhd->iommu;
	}

	return NULL;
}

W
Weidong Han 已提交
646 647 648 649 650 651 652
static void domain_flush_cache(struct dmar_domain *domain,
			       void *addr, int size)
{
	if (!domain->iommu_coherency)
		clflush_cache_range(addr, size);
}

653 654 655 656 657 658 659 660 661 662 663 664 665
/* Gets context entry for a given bus and devfn */
static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
		u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long phy_addr;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
666 667
		context = (struct context_entry *)
				alloc_pgtable_page(iommu->node);
668 669 670 671
		if (!context) {
			spin_unlock_irqrestore(&iommu->lock, flags);
			return NULL;
		}
F
Fenghua Yu 已提交
672
		__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695
		phy_addr = virt_to_phys((void *)context);
		set_root_value(root, phy_addr);
		set_root_present(root);
		__iommu_flush_cache(iommu, root, sizeof(*root));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
	return &context[devfn];
}

static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
		ret = 0;
		goto out;
	}
696
	ret = context_present(&context[devfn]);
697 698 699 700 701 702 703 704 705 706 707 708 709 710 711
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
	return ret;
}

static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (context) {
712
		context_clear_entry(&context[devfn]);
713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741
		__iommu_flush_cache(iommu, &context[devfn], \
			sizeof(*context));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
}

static void free_context_table(struct intel_iommu *iommu)
{
	struct root_entry *root;
	int i;
	unsigned long flags;
	struct context_entry *context;

	spin_lock_irqsave(&iommu->lock, flags);
	if (!iommu->root_entry) {
		goto out;
	}
	for (i = 0; i < ROOT_ENTRY_NR; i++) {
		root = &iommu->root_entry[i];
		context = get_context_addr_from_root(root);
		if (context)
			free_pgtable_page(context);
	}
	free_pgtable_page(iommu->root_entry);
	iommu->root_entry = NULL;
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
}

742
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
743
				      unsigned long pfn, int target_level)
744
{
745
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
746 747
	struct dma_pte *parent, *pte = NULL;
	int level = agaw_to_level(domain->agaw);
748
	int offset;
749 750

	BUG_ON(!domain->pgd);
751
	BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
752 753 754 755 756
	parent = domain->pgd;

	while (level > 0) {
		void *tmp_page;

757
		offset = pfn_level_offset(pfn, level);
758
		pte = &parent[offset];
759
		if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
760 761
			break;
		if (level == target_level)
762 763
			break;

764
		if (!dma_pte_present(pte)) {
765 766
			uint64_t pteval;

767
			tmp_page = alloc_pgtable_page(domain->nid);
768

769
			if (!tmp_page)
770
				return NULL;
771

772
			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
773
			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
774 775 776 777 778 779 780
			if (cmpxchg64(&pte->val, 0ULL, pteval)) {
				/* Someone else set it while we were thinking; use theirs. */
				free_pgtable_page(tmp_page);
			} else {
				dma_pte_addr(pte);
				domain_flush_cache(domain, pte, sizeof(*pte));
			}
781
		}
782
		parent = phys_to_virt(dma_pte_addr(pte));
783 784 785 786 787 788
		level--;
	}

	return pte;
}

789

790
/* return address's pte at specific level */
791 792
static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
					 unsigned long pfn,
793
					 int level, int *large_page)
794 795 796 797 798 799 800
{
	struct dma_pte *parent, *pte = NULL;
	int total = agaw_to_level(domain->agaw);
	int offset;

	parent = domain->pgd;
	while (level <= total) {
801
		offset = pfn_level_offset(pfn, total);
802 803 804 805
		pte = &parent[offset];
		if (level == total)
			return pte;

806 807
		if (!dma_pte_present(pte)) {
			*large_page = total;
808
			break;
809 810 811 812 813 814 815
		}

		if (pte->val & DMA_PTE_LARGE_PAGE) {
			*large_page = total;
			return pte;
		}

816
		parent = phys_to_virt(dma_pte_addr(pte));
817 818 819 820 821 822
		total--;
	}
	return NULL;
}

/* clear last level pte, a tlb flush should be followed */
823
static int dma_pte_clear_range(struct dmar_domain *domain,
824 825
				unsigned long start_pfn,
				unsigned long last_pfn)
826
{
827
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
828
	unsigned int large_page = 1;
829
	struct dma_pte *first_pte, *pte;
830
	int order;
831

832
	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
833
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
834
	BUG_ON(start_pfn > last_pfn);
835

836
	/* we don't need lock here; nobody else touches the iova range */
837
	do {
838 839
		large_page = 1;
		first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
840
		if (!pte) {
841
			start_pfn = align_to_level(start_pfn + 1, large_page + 1);
842 843
			continue;
		}
844
		do {
845
			dma_clear_pte(pte);
846
			start_pfn += lvl_to_nr_pages(large_page);
847
			pte++;
848 849
		} while (start_pfn <= last_pfn && !first_pte_in_page(pte));

850 851
		domain_flush_cache(domain, first_pte,
				   (void *)pte - (void *)first_pte);
852 853

	} while (start_pfn && start_pfn <= last_pfn);
854 855 856

	order = (large_page - 1) * 9;
	return order;
857 858 859 860
}

/* free page table pages. last level pte should already be cleared */
static void dma_pte_free_pagetable(struct dmar_domain *domain,
861 862
				   unsigned long start_pfn,
				   unsigned long last_pfn)
863
{
864
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
865
	struct dma_pte *first_pte, *pte;
866 867
	int total = agaw_to_level(domain->agaw);
	int level;
868
	unsigned long tmp;
869
	int large_page = 2;
870

871 872
	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
873
	BUG_ON(start_pfn > last_pfn);
874

875
	/* We don't need lock here; nobody else touches the iova range */
876 877
	level = 2;
	while (level <= total) {
878 879
		tmp = align_to_level(start_pfn, level);

880
		/* If we can't even clear one PTE at this level, we're done */
881
		if (tmp + level_size(level) - 1 > last_pfn)
882 883
			return;

884
		do {
885 886 887 888
			large_page = level;
			first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
			if (large_page > level)
				level = large_page + 1;
889 890 891 892
			if (!pte) {
				tmp = align_to_level(tmp + 1, level + 1);
				continue;
			}
893
			do {
894 895 896 897
				if (dma_pte_present(pte)) {
					free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
					dma_clear_pte(pte);
				}
898 899
				pte++;
				tmp += level_size(level);
900 901 902
			} while (!first_pte_in_page(pte) &&
				 tmp + level_size(level) - 1 <= last_pfn);

903 904 905
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			
906
		} while (tmp && tmp + level_size(level) - 1 <= last_pfn);
907 908 909
		level++;
	}
	/* free pgd */
910
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
911 912 913 914 915 916 917 918 919 920 921
		free_pgtable_page(domain->pgd);
		domain->pgd = NULL;
	}
}

/* iommu handling */
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
{
	struct root_entry *root;
	unsigned long flags;

922
	root = (struct root_entry *)alloc_pgtable_page(iommu->node);
923 924 925
	if (!root)
		return -ENOMEM;

F
Fenghua Yu 已提交
926
	__iommu_flush_cache(iommu, root, ROOT_SIZE);
927 928 929 930 931 932 933 934 935 936 937

	spin_lock_irqsave(&iommu->lock, flags);
	iommu->root_entry = root;
	spin_unlock_irqrestore(&iommu->lock, flags);

	return 0;
}

static void iommu_set_root_entry(struct intel_iommu *iommu)
{
	void *addr;
938
	u32 sts;
939 940 941 942
	unsigned long flag;

	addr = iommu->root_entry;

943
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
944 945
	dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));

946
	writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
947 948 949

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
950
		      readl, (sts & DMA_GSTS_RTPS), sts);
951

952
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
953 954 955 956 957 958 959
}

static void iommu_flush_write_buffer(struct intel_iommu *iommu)
{
	u32 val;
	unsigned long flag;

960
	if (!rwbf_quirk && !cap_rwbf(iommu->cap))
961 962
		return;

963
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
964
	writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
965 966 967

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
968
		      readl, (!(val & DMA_GSTS_WBFS)), val);
969

970
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
971 972 973
}

/* return value determine if we need a write buffer flush */
974 975 976
static void __iommu_flush_context(struct intel_iommu *iommu,
				  u16 did, u16 source_id, u8 function_mask,
				  u64 type)
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996
{
	u64 val = 0;
	unsigned long flag;

	switch (type) {
	case DMA_CCMD_GLOBAL_INVL:
		val = DMA_CCMD_GLOBAL_INVL;
		break;
	case DMA_CCMD_DOMAIN_INVL:
		val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
		break;
	case DMA_CCMD_DEVICE_INVL:
		val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
			| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
		break;
	default:
		BUG();
	}
	val |= DMA_CCMD_ICC;

997
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
998 999 1000 1001 1002 1003
	dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

1004
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1005 1006 1007
}

/* return value determine if we need a write buffer flush */
1008 1009
static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
				u64 addr, unsigned int size_order, u64 type)
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
{
	int tlb_offset = ecap_iotlb_offset(iommu->ecap);
	u64 val = 0, val_iva = 0;
	unsigned long flag;

	switch (type) {
	case DMA_TLB_GLOBAL_FLUSH:
		/* global flush doesn't need set IVA_REG */
		val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
		break;
	case DMA_TLB_DSI_FLUSH:
		val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		break;
	case DMA_TLB_PSI_FLUSH:
		val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		/* Note: always flush non-leaf currently */
		val_iva = size_order | addr;
		break;
	default:
		BUG();
	}
	/* Note: set drain read/write */
#if 0
	/*
	 * This is probably to be super secure.. Looks like we can
	 * ignore it without any impact.
	 */
	if (cap_read_drain(iommu->cap))
		val |= DMA_TLB_READ_DRAIN;
#endif
	if (cap_write_drain(iommu->cap))
		val |= DMA_TLB_WRITE_DRAIN;

1043
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1044 1045 1046 1047 1048 1049 1050 1051 1052
	/* Note: Only uses first TLB reg currently */
	if (val_iva)
		dmar_writeq(iommu->reg + tlb_offset, val_iva);
	dmar_writeq(iommu->reg + tlb_offset + 8, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, tlb_offset + 8,
		dmar_readq, (!(val & DMA_TLB_IVT)), val);

1053
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1054 1055 1056 1057 1058 1059

	/* check IOTLB invalidation granularity */
	if (DMA_TLB_IAIG(val) == 0)
		printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
	if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
		pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
F
Fenghua Yu 已提交
1060 1061
			(unsigned long long)DMA_TLB_IIRG(type),
			(unsigned long long)DMA_TLB_IAIG(val));
1062 1063
}

Y
Yu Zhao 已提交
1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100
static struct device_domain_info *iommu_support_dev_iotlb(
	struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
{
	int found = 0;
	unsigned long flags;
	struct device_domain_info *info;
	struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);

	if (!ecap_dev_iotlb_support(iommu->ecap))
		return NULL;

	if (!iommu->qi)
		return NULL;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link)
		if (info->bus == bus && info->devfn == devfn) {
			found = 1;
			break;
		}
	spin_unlock_irqrestore(&device_domain_lock, flags);

	if (!found || !info->dev)
		return NULL;

	if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
		return NULL;

	if (!dmar_find_matched_atsr_unit(info->dev))
		return NULL;

	info->iommu = iommu;

	return info;
}

static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1101
{
Y
Yu Zhao 已提交
1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
	if (!info)
		return;

	pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
}

static void iommu_disable_dev_iotlb(struct device_domain_info *info)
{
	if (!info->dev || !pci_ats_enabled(info->dev))
		return;

	pci_disable_ats(info->dev);
}

static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
				  u64 addr, unsigned mask)
{
	u16 sid, qdep;
	unsigned long flags;
	struct device_domain_info *info;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link) {
		if (!info->dev || !pci_ats_enabled(info->dev))
			continue;

		sid = info->bus << 8 | info->devfn;
		qdep = pci_ats_queue_depth(info->dev);
		qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

1135
static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1136
				  unsigned long pfn, unsigned int pages, int map)
1137
{
1138
	unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1139
	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1140 1141 1142 1143

	BUG_ON(pages == 0);

	/*
1144 1145
	 * Fallback to domain selective flush if no PSI support or the size is
	 * too big.
1146 1147 1148
	 * PSI requires page size to be 2 ^ x, and the base address is naturally
	 * aligned to the size
	 */
1149 1150
	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
		iommu->flush.flush_iotlb(iommu, did, 0, 0,
1151
						DMA_TLB_DSI_FLUSH);
1152 1153 1154
	else
		iommu->flush.flush_iotlb(iommu, did, addr, mask,
						DMA_TLB_PSI_FLUSH);
1155 1156

	/*
1157 1158
	 * In caching mode, changes of pages from non-present to present require
	 * flush. However, device IOTLB doesn't need to be flushed in this case.
1159
	 */
1160
	if (!cap_caching_mode(iommu->cap) || !map)
Y
Yu Zhao 已提交
1161
		iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1162 1163
}

M
mark gross 已提交
1164 1165 1166 1167 1168
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
{
	u32 pmen;
	unsigned long flags;

1169
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
M
mark gross 已提交
1170 1171 1172 1173 1174 1175 1176 1177
	pmen = readl(iommu->reg + DMAR_PMEN_REG);
	pmen &= ~DMA_PMEN_EPM;
	writel(pmen, iommu->reg + DMAR_PMEN_REG);

	/* wait for the protected region status bit to clear */
	IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
		readl, !(pmen & DMA_PMEN_PRS), pmen);

1178
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
M
mark gross 已提交
1179 1180
}

1181 1182 1183 1184 1185
static int iommu_enable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flags;

1186
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
1187 1188
	iommu->gcmd |= DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1189 1190 1191

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1192
		      readl, (sts & DMA_GSTS_TES), sts);
1193

1194
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1195 1196 1197 1198 1199 1200 1201 1202
	return 0;
}

static int iommu_disable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flag;

1203
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1204 1205 1206 1207 1208
	iommu->gcmd &= ~DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1209
		      readl, (!(sts & DMA_GSTS_TES)), sts);
1210

1211
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1212 1213 1214
	return 0;
}

1215

1216 1217 1218 1219 1220 1221
static int iommu_init_domains(struct intel_iommu *iommu)
{
	unsigned long ndomains;
	unsigned long nlongs;

	ndomains = cap_ndoms(iommu->cap);
Y
Yinghai Lu 已提交
1222 1223
	pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id,
			ndomains);
1224 1225
	nlongs = BITS_TO_LONGS(ndomains);

1226 1227
	spin_lock_init(&iommu->lock);

1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253
	/* TBD: there might be 64K domains,
	 * consider other allocation for future chip
	 */
	iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
	if (!iommu->domain_ids) {
		printk(KERN_ERR "Allocating domain id array failed\n");
		return -ENOMEM;
	}
	iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
			GFP_KERNEL);
	if (!iommu->domains) {
		printk(KERN_ERR "Allocating domain array failed\n");
		return -ENOMEM;
	}

	/*
	 * if Caching mode is set, then invalid translations are tagged
	 * with domainid 0. Hence we need to pre-allocate it.
	 */
	if (cap_caching_mode(iommu->cap))
		set_bit(0, iommu->domain_ids);
	return 0;
}


static void domain_exit(struct dmar_domain *domain);
1254
static void vm_domain_exit(struct dmar_domain *domain);
1255 1256

void free_dmar_iommu(struct intel_iommu *iommu)
1257 1258 1259
{
	struct dmar_domain *domain;
	int i;
1260
	unsigned long flags;
1261

1262
	if ((iommu->domains) && (iommu->domain_ids)) {
1263
		for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274
			domain = iommu->domains[i];
			clear_bit(i, iommu->domain_ids);

			spin_lock_irqsave(&domain->iommu_lock, flags);
			if (--domain->iommu_count == 0) {
				if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
					vm_domain_exit(domain);
				else
					domain_exit(domain);
			}
			spin_unlock_irqrestore(&domain->iommu_lock, flags);
1275
		}
1276 1277 1278 1279 1280 1281
	}

	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);

	if (iommu->irq) {
1282
		irq_set_handler_data(iommu->irq, NULL);
1283 1284 1285 1286 1287 1288 1289 1290
		/* This will mask the irq */
		free_irq(iommu->irq, iommu);
		destroy_irq(iommu->irq);
	}

	kfree(iommu->domains);
	kfree(iommu->domain_ids);

W
Weidong Han 已提交
1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301
	g_iommus[iommu->seq_id] = NULL;

	/* if all iommus are freed, free g_iommus */
	for (i = 0; i < g_num_of_iommus; i++) {
		if (g_iommus[i])
			break;
	}

	if (i == g_num_of_iommus)
		kfree(g_iommus);

1302 1303 1304 1305
	/* free context mapping */
	free_context_table(iommu);
}

1306
static struct dmar_domain *alloc_domain(void)
1307 1308 1309 1310 1311 1312 1313
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

1314
	domain->nid = -1;
1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
	memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
	domain->flags = 0;

	return domain;
}

static int iommu_attach_domain(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	int num;
	unsigned long ndomains;
	unsigned long flags;

1328 1329 1330
	ndomains = cap_ndoms(iommu->cap);

	spin_lock_irqsave(&iommu->lock, flags);
1331

1332 1333 1334 1335
	num = find_first_zero_bit(iommu->domain_ids, ndomains);
	if (num >= ndomains) {
		spin_unlock_irqrestore(&iommu->lock, flags);
		printk(KERN_ERR "IOMMU: no free domain ids\n");
1336
		return -ENOMEM;
1337 1338 1339
	}

	domain->id = num;
1340
	set_bit(num, iommu->domain_ids);
1341
	set_bit(iommu->seq_id, &domain->iommu_bmp);
1342 1343 1344
	iommu->domains[num] = domain;
	spin_unlock_irqrestore(&iommu->lock, flags);

1345
	return 0;
1346 1347
}

1348 1349
static void iommu_detach_domain(struct dmar_domain *domain,
				struct intel_iommu *iommu)
1350 1351
{
	unsigned long flags;
1352 1353
	int num, ndomains;
	int found = 0;
1354

1355
	spin_lock_irqsave(&iommu->lock, flags);
1356
	ndomains = cap_ndoms(iommu->cap);
1357
	for_each_set_bit(num, iommu->domain_ids, ndomains) {
1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368
		if (iommu->domains[num] == domain) {
			found = 1;
			break;
		}
	}

	if (found) {
		clear_bit(num, iommu->domain_ids);
		clear_bit(iommu->seq_id, &domain->iommu_bmp);
		iommu->domains[num] = NULL;
	}
1369
	spin_unlock_irqrestore(&iommu->lock, flags);
1370 1371 1372
}

static struct iova_domain reserved_iova_list;
M
Mark Gross 已提交
1373
static struct lock_class_key reserved_rbtree_key;
1374

1375
static int dmar_init_reserved_ranges(void)
1376 1377 1378 1379 1380
{
	struct pci_dev *pdev = NULL;
	struct iova *iova;
	int i;

D
David Miller 已提交
1381
	init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1382

M
Mark Gross 已提交
1383 1384 1385
	lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
		&reserved_rbtree_key);

1386 1387 1388
	/* IOAPIC ranges shouldn't be accessed by DMA */
	iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
		IOVA_PFN(IOAPIC_RANGE_END));
1389
	if (!iova) {
1390
		printk(KERN_ERR "Reserve IOAPIC range failed\n");
1391 1392
		return -ENODEV;
	}
1393 1394 1395 1396 1397 1398 1399 1400 1401

	/* Reserve all PCI MMIO to avoid peer-to-peer access */
	for_each_pci_dev(pdev) {
		struct resource *r;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			r = &pdev->resource[i];
			if (!r->flags || !(r->flags & IORESOURCE_MEM))
				continue;
1402 1403 1404
			iova = reserve_iova(&reserved_iova_list,
					    IOVA_PFN(r->start),
					    IOVA_PFN(r->end));
1405
			if (!iova) {
1406
				printk(KERN_ERR "Reserve iova failed\n");
1407 1408
				return -ENODEV;
			}
1409 1410
		}
	}
1411
	return 0;
1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
}

static void domain_reserve_special_ranges(struct dmar_domain *domain)
{
	copy_reserved_iova(&reserved_iova_list, &domain->iovad);
}

static inline int guestwidth_to_adjustwidth(int gaw)
{
	int agaw;
	int r = (gaw - 12) % 9;

	if (r == 0)
		agaw = gaw;
	else
		agaw = gaw + 9 - r;
	if (agaw > 64)
		agaw = 64;
	return agaw;
}

static int domain_init(struct dmar_domain *domain, int guest_width)
{
	struct intel_iommu *iommu;
	int adjust_width, agaw;
	unsigned long sagaw;

D
David Miller 已提交
1439
	init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1440
	spin_lock_init(&domain->iommu_lock);
1441 1442 1443 1444

	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
1445
	iommu = domain_get_iommu(domain);
1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461
	if (guest_width > cap_mgaw(iommu->cap))
		guest_width = cap_mgaw(iommu->cap);
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	agaw = width_to_agaw(adjust_width);
	sagaw = cap_sagaw(iommu->cap);
	if (!test_bit(agaw, &sagaw)) {
		/* hardware doesn't support it, choose a bigger one */
		pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
		agaw = find_next_bit(&sagaw, 5, agaw);
		if (agaw >= 5)
			return -ENODEV;
	}
	domain->agaw = agaw;
	INIT_LIST_HEAD(&domain->devices);

W
Weidong Han 已提交
1462 1463 1464 1465 1466
	if (ecap_coherent(iommu->ecap))
		domain->iommu_coherency = 1;
	else
		domain->iommu_coherency = 0;

1467 1468 1469 1470 1471
	if (ecap_sc_support(iommu->ecap))
		domain->iommu_snooping = 1;
	else
		domain->iommu_snooping = 0;

1472
	domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1473
	domain->iommu_count = 1;
1474
	domain->nid = iommu->node;
1475

1476
	/* always allocate the top pgd */
1477
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1478 1479
	if (!domain->pgd)
		return -ENOMEM;
F
Fenghua Yu 已提交
1480
	__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1481 1482 1483 1484 1485
	return 0;
}

static void domain_exit(struct dmar_domain *domain)
{
1486 1487
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
1488 1489 1490 1491 1492

	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

1493 1494 1495 1496
	/* Flush any lazy unmaps that may reference this domain */
	if (!intel_iommu_strict)
		flush_unmaps_timeout(0);

1497 1498 1499 1500 1501
	domain_remove_dev_info(domain);
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

	/* clear ptes */
1502
	dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1503 1504

	/* free page tables */
1505
	dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1506

1507 1508 1509 1510
	for_each_active_iommu(iommu, drhd)
		if (test_bit(iommu->seq_id, &domain->iommu_bmp))
			iommu_detach_domain(domain, iommu);

1511 1512 1513
	free_domain_mem(domain);
}

F
Fenghua Yu 已提交
1514 1515
static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
				 u8 bus, u8 devfn, int translation)
1516 1517 1518
{
	struct context_entry *context;
	unsigned long flags;
W
Weidong Han 已提交
1519
	struct intel_iommu *iommu;
1520 1521 1522 1523 1524
	struct dma_pte *pgd;
	unsigned long num;
	unsigned long ndomains;
	int id;
	int agaw;
Y
Yu Zhao 已提交
1525
	struct device_domain_info *info = NULL;
1526 1527 1528

	pr_debug("Set context mapping for %02x:%02x.%d\n",
		bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
F
Fenghua Yu 已提交
1529

1530
	BUG_ON(!domain->pgd);
F
Fenghua Yu 已提交
1531 1532
	BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
	       translation != CONTEXT_TT_MULTI_LEVEL);
W
Weidong Han 已提交
1533

1534
	iommu = device_to_iommu(segment, bus, devfn);
W
Weidong Han 已提交
1535 1536 1537
	if (!iommu)
		return -ENODEV;

1538 1539 1540 1541
	context = device_to_context_entry(iommu, bus, devfn);
	if (!context)
		return -ENOMEM;
	spin_lock_irqsave(&iommu->lock, flags);
1542
	if (context_present(context)) {
1543 1544 1545 1546
		spin_unlock_irqrestore(&iommu->lock, flags);
		return 0;
	}

1547 1548 1549
	id = domain->id;
	pgd = domain->pgd;

1550 1551
	if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
	    domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1552 1553 1554 1555
		int found = 0;

		/* find an available domain id for this device in iommu */
		ndomains = cap_ndoms(iommu->cap);
1556
		for_each_set_bit(num, iommu->domain_ids, ndomains) {
1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578
			if (iommu->domains[num] == domain) {
				id = num;
				found = 1;
				break;
			}
		}

		if (found == 0) {
			num = find_first_zero_bit(iommu->domain_ids, ndomains);
			if (num >= ndomains) {
				spin_unlock_irqrestore(&iommu->lock, flags);
				printk(KERN_ERR "IOMMU: no free domain ids\n");
				return -EFAULT;
			}

			set_bit(num, iommu->domain_ids);
			iommu->domains[num] = domain;
			id = num;
		}

		/* Skip top levels of page tables for
		 * iommu which has less agaw than default.
1579
		 * Unnecessary for PT mode.
1580
		 */
1581 1582 1583 1584 1585 1586 1587
		if (translation != CONTEXT_TT_PASS_THROUGH) {
			for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
				pgd = phys_to_virt(dma_pte_addr(pgd));
				if (!dma_pte_present(pgd)) {
					spin_unlock_irqrestore(&iommu->lock, flags);
					return -ENOMEM;
				}
1588 1589 1590 1591 1592
			}
		}
	}

	context_set_domain_id(context, id);
F
Fenghua Yu 已提交
1593

Y
Yu Zhao 已提交
1594 1595 1596 1597 1598
	if (translation != CONTEXT_TT_PASS_THROUGH) {
		info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
		translation = info ? CONTEXT_TT_DEV_IOTLB :
				     CONTEXT_TT_MULTI_LEVEL;
	}
F
Fenghua Yu 已提交
1599 1600 1601 1602
	/*
	 * In pass through mode, AW must be programmed to indicate the largest
	 * AGAW value supported by hardware. And ASR is ignored by hardware.
	 */
Y
Yu Zhao 已提交
1603
	if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
F
Fenghua Yu 已提交
1604
		context_set_address_width(context, iommu->msagaw);
Y
Yu Zhao 已提交
1605 1606 1607 1608
	else {
		context_set_address_root(context, virt_to_phys(pgd));
		context_set_address_width(context, iommu->agaw);
	}
F
Fenghua Yu 已提交
1609 1610

	context_set_translation_type(context, translation);
1611 1612
	context_set_fault_enable(context);
	context_set_present(context);
W
Weidong Han 已提交
1613
	domain_flush_cache(domain, context, sizeof(*context));
1614

1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625
	/*
	 * It's a non-present to present mapping. If hardware doesn't cache
	 * non-present entry we only need to flush the write-buffer. If the
	 * _does_ cache non-present entries, then it does so in the special
	 * domain #0, which we have to flush:
	 */
	if (cap_caching_mode(iommu->cap)) {
		iommu->flush.flush_context(iommu, 0,
					   (((u16)bus) << 8) | devfn,
					   DMA_CCMD_MASK_NOBIT,
					   DMA_CCMD_DEVICE_INVL);
1626
		iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
1627
	} else {
1628
		iommu_flush_write_buffer(iommu);
1629
	}
Y
Yu Zhao 已提交
1630
	iommu_enable_dev_iotlb(info);
1631
	spin_unlock_irqrestore(&iommu->lock, flags);
1632 1633 1634 1635

	spin_lock_irqsave(&domain->iommu_lock, flags);
	if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
		domain->iommu_count++;
1636 1637
		if (domain->iommu_count == 1)
			domain->nid = iommu->node;
1638
		domain_update_iommu_cap(domain);
1639 1640
	}
	spin_unlock_irqrestore(&domain->iommu_lock, flags);
1641 1642 1643 1644
	return 0;
}

static int
F
Fenghua Yu 已提交
1645 1646
domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
			int translation)
1647 1648 1649 1650
{
	int ret;
	struct pci_dev *tmp, *parent;

1651
	ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
F
Fenghua Yu 已提交
1652 1653
					 pdev->bus->number, pdev->devfn,
					 translation);
1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
	if (ret)
		return ret;

	/* dependent device mapping */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	if (!tmp)
		return 0;
	/* Secondary interface's bus number and devfn 0 */
	parent = pdev->bus->self;
	while (parent != tmp) {
1664 1665 1666
		ret = domain_context_mapping_one(domain,
						 pci_domain_nr(parent->bus),
						 parent->bus->number,
F
Fenghua Yu 已提交
1667
						 parent->devfn, translation);
1668 1669 1670 1671
		if (ret)
			return ret;
		parent = parent->bus->self;
	}
1672
	if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
1673
		return domain_context_mapping_one(domain,
1674
					pci_domain_nr(tmp->subordinate),
F
Fenghua Yu 已提交
1675 1676
					tmp->subordinate->number, 0,
					translation);
1677 1678
	else /* this is a legacy PCI bridge */
		return domain_context_mapping_one(domain,
1679 1680
						  pci_domain_nr(tmp->bus),
						  tmp->bus->number,
F
Fenghua Yu 已提交
1681 1682
						  tmp->devfn,
						  translation);
1683 1684
}

W
Weidong Han 已提交
1685
static int domain_context_mapped(struct pci_dev *pdev)
1686 1687 1688
{
	int ret;
	struct pci_dev *tmp, *parent;
W
Weidong Han 已提交
1689 1690
	struct intel_iommu *iommu;

1691 1692
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
W
Weidong Han 已提交
1693 1694
	if (!iommu)
		return -ENODEV;
1695

1696
	ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1697 1698 1699 1700 1701 1702 1703 1704 1705
	if (!ret)
		return ret;
	/* dependent device mapping */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	if (!tmp)
		return ret;
	/* Secondary interface's bus number and devfn 0 */
	parent = pdev->bus->self;
	while (parent != tmp) {
1706
		ret = device_context_mapped(iommu, parent->bus->number,
1707
					    parent->devfn);
1708 1709 1710 1711
		if (!ret)
			return ret;
		parent = parent->bus->self;
	}
1712
	if (pci_is_pcie(tmp))
1713 1714
		return device_context_mapped(iommu, tmp->subordinate->number,
					     0);
1715
	else
1716 1717
		return device_context_mapped(iommu, tmp->bus->number,
					     tmp->devfn);
1718 1719
}

1720 1721 1722 1723 1724 1725 1726 1727
/* Returns a number of VTD pages, but aligned to MM page size */
static inline unsigned long aligned_nrpages(unsigned long host_addr,
					    size_t size)
{
	host_addr &= ~PAGE_MASK;
	return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
}

1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755
/* Return largest possible superpage level for a given mapping */
static inline int hardware_largepage_caps(struct dmar_domain *domain,
					  unsigned long iov_pfn,
					  unsigned long phy_pfn,
					  unsigned long pages)
{
	int support, level = 1;
	unsigned long pfnmerge;

	support = domain->iommu_superpage;

	/* To use a large page, the virtual *and* physical addresses
	   must be aligned to 2MiB/1GiB/etc. Lower bits set in either
	   of them will mean we have to use smaller pages. So just
	   merge them and check both at once. */
	pfnmerge = iov_pfn | phy_pfn;

	while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
		pages >>= VTD_STRIDE_SHIFT;
		if (!pages)
			break;
		pfnmerge >>= VTD_STRIDE_SHIFT;
		level++;
		support--;
	}
	return level;
}

1756 1757 1758
static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
			    struct scatterlist *sg, unsigned long phys_pfn,
			    unsigned long nr_pages, int prot)
1759 1760
{
	struct dma_pte *first_pte = NULL, *pte = NULL;
1761
	phys_addr_t uninitialized_var(pteval);
1762
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1763
	unsigned long sg_res;
1764 1765
	unsigned int largepage_lvl = 0;
	unsigned long lvl_pages = 0;
1766 1767 1768 1769 1770 1771 1772 1773

	BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);

	if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
		return -EINVAL;

	prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;

1774 1775 1776 1777 1778 1779 1780
	if (sg)
		sg_res = 0;
	else {
		sg_res = nr_pages + 1;
		pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
	}

1781
	while (nr_pages > 0) {
1782 1783
		uint64_t tmp;

1784
		if (!sg_res) {
1785
			sg_res = aligned_nrpages(sg->offset, sg->length);
1786 1787 1788
			sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
			sg->dma_length = sg->length;
			pteval = page_to_phys(sg_page(sg)) | prot;
1789
			phys_pfn = pteval >> VTD_PAGE_SHIFT;
1790
		}
1791

1792
		if (!pte) {
1793 1794 1795
			largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);

			first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
1796 1797
			if (!pte)
				return -ENOMEM;
1798 1799 1800 1801 1802 1803
			/* It is large page*/
			if (largepage_lvl > 1)
				pteval |= DMA_PTE_LARGE_PAGE;
			else
				pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;

1804 1805 1806 1807
		}
		/* We don't need lock here, nobody else
		 * touches the iova range
		 */
1808
		tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1809
		if (tmp) {
1810
			static int dumps = 5;
1811 1812
			printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
			       iov_pfn, tmp, (unsigned long long)pteval);
1813 1814 1815 1816 1817 1818
			if (dumps) {
				dumps--;
				debug_dma_dump_mappings(NULL);
			}
			WARN_ON(1);
		}
1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841

		lvl_pages = lvl_to_nr_pages(largepage_lvl);

		BUG_ON(nr_pages < lvl_pages);
		BUG_ON(sg_res < lvl_pages);

		nr_pages -= lvl_pages;
		iov_pfn += lvl_pages;
		phys_pfn += lvl_pages;
		pteval += lvl_pages * VTD_PAGE_SIZE;
		sg_res -= lvl_pages;

		/* If the next PTE would be the first in a new page, then we
		   need to flush the cache on the entries we've just written.
		   And then we'll need to recalculate 'pte', so clear it and
		   let it get set again in the if (!pte) block above.

		   If we're done (!nr_pages) we need to flush the cache too.

		   Also if we've been setting superpages, we may need to
		   recalculate 'pte' and switch back to smaller pages for the
		   end of the mapping, if the trailing size is not enough to
		   use another superpage (i.e. sg_res < lvl_pages). */
1842
		pte++;
1843 1844
		if (!nr_pages || first_pte_in_page(pte) ||
		    (largepage_lvl > 1 && sg_res < lvl_pages)) {
1845 1846 1847 1848
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			pte = NULL;
		}
1849 1850

		if (!sg_res && nr_pages)
1851 1852 1853 1854 1855
			sg = sg_next(sg);
	}
	return 0;
}

1856 1857 1858
static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				    struct scatterlist *sg, unsigned long nr_pages,
				    int prot)
1859
{
1860 1861
	return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
}
1862

1863 1864 1865 1866 1867
static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				     unsigned long phys_pfn, unsigned long nr_pages,
				     int prot)
{
	return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1868 1869
}

1870
static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1871
{
1872 1873
	if (!iommu)
		return;
1874 1875 1876

	clear_context_table(iommu, bus, devfn);
	iommu->flush.flush_context(iommu, 0, 0, 0,
1877
					   DMA_CCMD_GLOBAL_INVL);
1878
	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1879 1880 1881 1882 1883 1884
}

static void domain_remove_dev_info(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	unsigned long flags;
1885
	struct intel_iommu *iommu;
1886 1887 1888 1889 1890 1891 1892 1893

	spin_lock_irqsave(&device_domain_lock, flags);
	while (!list_empty(&domain->devices)) {
		info = list_entry(domain->devices.next,
			struct device_domain_info, link);
		list_del(&info->link);
		list_del(&info->global);
		if (info->dev)
1894
			info->dev->dev.archdata.iommu = NULL;
1895 1896
		spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
1897
		iommu_disable_dev_iotlb(info);
1898
		iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1899
		iommu_detach_dev(iommu, info->bus, info->devfn);
1900 1901 1902 1903 1904 1905 1906 1907 1908
		free_devinfo_mem(info);

		spin_lock_irqsave(&device_domain_lock, flags);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

/*
 * find_domain
1909
 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1910
 */
K
Kay, Allen M 已提交
1911
static struct dmar_domain *
1912 1913 1914 1915 1916
find_domain(struct pci_dev *pdev)
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
1917
	info = pdev->dev.archdata.iommu;
1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932
	if (info)
		return info->domain;
	return NULL;
}

/* domain is initialized */
static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
{
	struct dmar_domain *domain, *found = NULL;
	struct intel_iommu *iommu;
	struct dmar_drhd_unit *drhd;
	struct device_domain_info *info, *tmp;
	struct pci_dev *dev_tmp;
	unsigned long flags;
	int bus = 0, devfn = 0;
1933
	int segment;
1934
	int ret;
1935 1936 1937 1938 1939

	domain = find_domain(pdev);
	if (domain)
		return domain;

1940 1941
	segment = pci_domain_nr(pdev->bus);

1942 1943
	dev_tmp = pci_find_upstream_pcie_bridge(pdev);
	if (dev_tmp) {
1944
		if (pci_is_pcie(dev_tmp)) {
1945 1946 1947 1948 1949 1950 1951 1952
			bus = dev_tmp->subordinate->number;
			devfn = 0;
		} else {
			bus = dev_tmp->bus->number;
			devfn = dev_tmp->devfn;
		}
		spin_lock_irqsave(&device_domain_lock, flags);
		list_for_each_entry(info, &device_domain_list, global) {
1953 1954
			if (info->segment == segment &&
			    info->bus == bus && info->devfn == devfn) {
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966
				found = info->domain;
				break;
			}
		}
		spin_unlock_irqrestore(&device_domain_lock, flags);
		/* pcie-pci bridge already has a domain, uses it */
		if (found) {
			domain = found;
			goto found_domain;
		}
	}

1967 1968 1969 1970
	domain = alloc_domain();
	if (!domain)
		goto error;

1971 1972 1973 1974 1975 1976 1977 1978 1979
	/* Allocate new domain for the device */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (!drhd) {
		printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
			pci_name(pdev));
		return NULL;
	}
	iommu = drhd->iommu;

1980 1981
	ret = iommu_attach_domain(domain, iommu);
	if (ret) {
1982
		free_domain_mem(domain);
1983
		goto error;
1984
	}
1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997

	if (domain_init(domain, gaw)) {
		domain_exit(domain);
		goto error;
	}

	/* register pcie-to-pci device */
	if (dev_tmp) {
		info = alloc_devinfo_mem();
		if (!info) {
			domain_exit(domain);
			goto error;
		}
1998
		info->segment = segment;
1999 2000 2001 2002 2003
		info->bus = bus;
		info->devfn = devfn;
		info->dev = NULL;
		info->domain = domain;
		/* This domain is shared by devices under p2p bridge */
W
Weidong Han 已提交
2004
		domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2005 2006 2007 2008 2009

		/* pcie-to-pci bridge already has a domain, uses it */
		found = NULL;
		spin_lock_irqsave(&device_domain_lock, flags);
		list_for_each_entry(tmp, &device_domain_list, global) {
2010 2011
			if (tmp->segment == segment &&
			    tmp->bus == bus && tmp->devfn == devfn) {
2012 2013 2014 2015 2016
				found = tmp->domain;
				break;
			}
		}
		if (found) {
2017
			spin_unlock_irqrestore(&device_domain_lock, flags);
2018 2019 2020 2021 2022 2023
			free_devinfo_mem(info);
			domain_exit(domain);
			domain = found;
		} else {
			list_add(&info->link, &domain->devices);
			list_add(&info->global, &device_domain_list);
2024
			spin_unlock_irqrestore(&device_domain_lock, flags);
2025 2026 2027 2028 2029 2030 2031
		}
	}

found_domain:
	info = alloc_devinfo_mem();
	if (!info)
		goto error;
2032
	info->segment = segment;
2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
	info->bus = pdev->bus->number;
	info->devfn = pdev->devfn;
	info->dev = pdev;
	info->domain = domain;
	spin_lock_irqsave(&device_domain_lock, flags);
	/* somebody is fast */
	found = find_domain(pdev);
	if (found != NULL) {
		spin_unlock_irqrestore(&device_domain_lock, flags);
		if (found != domain) {
			domain_exit(domain);
			domain = found;
		}
		free_devinfo_mem(info);
		return domain;
	}
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
2051
	pdev->dev.archdata.iommu = info;
2052 2053 2054 2055 2056 2057 2058
	spin_unlock_irqrestore(&device_domain_lock, flags);
	return domain;
error:
	/* recheck it here, maybe others set it */
	return find_domain(pdev);
}

2059
static int iommu_identity_mapping;
2060 2061 2062
#define IDENTMAP_ALL		1
#define IDENTMAP_GFX		2
#define IDENTMAP_AZALIA		4
2063

2064 2065 2066
static int iommu_domain_identity_map(struct dmar_domain *domain,
				     unsigned long long start,
				     unsigned long long end)
2067
{
2068 2069 2070 2071 2072
	unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
	unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;

	if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
			  dma_to_mm_pfn(last_vpfn))) {
2073
		printk(KERN_ERR "IOMMU: reserve iova failed\n");
2074
		return -ENOMEM;
2075 2076
	}

2077 2078
	pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
		 start, end, domain->id);
2079 2080 2081 2082
	/*
	 * RMRR range might have overlap with physical memory range,
	 * clear it first
	 */
2083
	dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2084

2085 2086
	return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
				  last_vpfn - first_vpfn + 1,
2087
				  DMA_PTE_READ|DMA_PTE_WRITE);
2088 2089 2090 2091 2092 2093 2094 2095 2096
}

static int iommu_prepare_identity_map(struct pci_dev *pdev,
				      unsigned long long start,
				      unsigned long long end)
{
	struct dmar_domain *domain;
	int ret;

2097
	domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2098 2099 2100
	if (!domain)
		return -ENOMEM;

2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
	/* For _hardware_ passthrough, don't bother. But for software
	   passthrough, we do it anyway -- it may indicate a memory
	   range which is reserved in E820, so which didn't get set
	   up to start with in si_domain */
	if (domain == si_domain && hw_pass_through) {
		printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
		       pci_name(pdev), start, end);
		return 0;
	}

	printk(KERN_INFO
	       "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
	       pci_name(pdev), start, end);
2114
	
2115 2116 2117 2118 2119 2120 2121 2122 2123 2124
	if (end < start) {
		WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
			"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
			dmi_get_system_info(DMI_BIOS_VENDOR),
			dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}

2125 2126 2127 2128 2129 2130 2131 2132 2133 2134
	if (end >> agaw_to_width(domain->agaw)) {
		WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     agaw_to_width(domain->agaw),
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}
2135

2136
	ret = iommu_domain_identity_map(domain, start, end);
2137 2138 2139 2140
	if (ret)
		goto error;

	/* context entry init */
F
Fenghua Yu 已提交
2141
	ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2142 2143 2144 2145 2146 2147
	if (ret)
		goto error;

	return 0;

 error:
2148 2149 2150 2151 2152 2153 2154
	domain_exit(domain);
	return ret;
}

static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
	struct pci_dev *pdev)
{
2155
	if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2156 2157
		return 0;
	return iommu_prepare_identity_map(pdev, rmrr->base_address,
2158
		rmrr->end_address);
2159 2160
}

2161
#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2162 2163 2164 2165 2166 2167 2168 2169 2170
static inline void iommu_prepare_isa(void)
{
	struct pci_dev *pdev;
	int ret;

	pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	if (!pdev)
		return;

2171
	printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2172
	ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
2173 2174

	if (ret)
2175 2176
		printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
		       "floppy might not work\n");
2177 2178 2179 2180 2181 2182 2183

}
#else
static inline void iommu_prepare_isa(void)
{
	return;
}
2184
#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2185

2186
static int md_domain_init(struct dmar_domain *domain, int guest_width);
2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199

static int __init si_domain_work_fn(unsigned long start_pfn,
				    unsigned long end_pfn, void *datax)
{
	int *ret = datax;

	*ret = iommu_domain_identity_map(si_domain,
					 (uint64_t)start_pfn << PAGE_SHIFT,
					 (uint64_t)end_pfn << PAGE_SHIFT);
	return *ret;

}

2200
static int __init si_domain_init(int hw)
2201 2202 2203
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
2204
	int nid, ret = 0;
2205 2206 2207 2208 2209

	si_domain = alloc_domain();
	if (!si_domain)
		return -EFAULT;

2210
	pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226

	for_each_active_iommu(iommu, drhd) {
		ret = iommu_attach_domain(si_domain, iommu);
		if (ret) {
			domain_exit(si_domain);
			return -EFAULT;
		}
	}

	if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
		domain_exit(si_domain);
		return -EFAULT;
	}

	si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;

2227 2228 2229
	if (hw)
		return 0;

2230 2231 2232 2233 2234 2235
	for_each_online_node(nid) {
		work_with_active_regions(nid, si_domain_work_fn, &ret);
		if (ret)
			return ret;
	}

2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247
	return 0;
}

static void domain_remove_one_dev_info(struct dmar_domain *domain,
					  struct pci_dev *pdev);
static int identity_mapping(struct pci_dev *pdev)
{
	struct device_domain_info *info;

	if (likely(!iommu_identity_mapping))
		return 0;

2248 2249 2250
	info = pdev->dev.archdata.iommu;
	if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
		return (info->domain == si_domain);
2251 2252 2253 2254 2255

	return 0;
}

static int domain_add_dev_info(struct dmar_domain *domain,
2256 2257
			       struct pci_dev *pdev,
			       int translation)
2258 2259 2260
{
	struct device_domain_info *info;
	unsigned long flags;
2261
	int ret;
2262 2263 2264 2265 2266

	info = alloc_devinfo_mem();
	if (!info)
		return -ENOMEM;

2267 2268 2269 2270 2271 2272
	ret = domain_context_mapping(domain, pdev, translation);
	if (ret) {
		free_devinfo_mem(info);
		return ret;
	}

2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287
	info->segment = pci_domain_nr(pdev->bus);
	info->bus = pdev->bus->number;
	info->devfn = pdev->devfn;
	info->dev = pdev;
	info->domain = domain;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
	pdev->dev.archdata.iommu = info;
	spin_unlock_irqrestore(&device_domain_lock, flags);

	return 0;
}

2288 2289
static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
{
2290 2291 2292 2293 2294 2295 2296 2297
	if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
		return 1;

	if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
		return 1;

	if (!(iommu_identity_mapping & IDENTMAP_ALL))
		return 0;
2298

2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315
	/*
	 * We want to start off with all devices in the 1:1 domain, and
	 * take them out later if we find they can't access all of memory.
	 *
	 * However, we can't do this for PCI devices behind bridges,
	 * because all PCI devices behind the same bridge will end up
	 * with the same source-id on their transactions.
	 *
	 * Practically speaking, we can't change things around for these
	 * devices at run-time, because we can't be sure there'll be no
	 * DMA transactions in flight for any of their siblings.
	 * 
	 * So PCI devices (unless they're on the root bus) as well as
	 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
	 * the 1:1 domain, just in _case_ one of their siblings turns out
	 * not to be able to map all of memory.
	 */
2316
	if (!pci_is_pcie(pdev)) {
2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328
		if (!pci_is_root_bus(pdev->bus))
			return 0;
		if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
			return 0;
	} else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
		return 0;

	/* 
	 * At boot time, we don't yet know if devices will be 64-bit capable.
	 * Assume that they will -- if they turn out not to be, then we can 
	 * take them out of the 1:1 domain later.
	 */
2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341
	if (!startup) {
		/*
		 * If the device's dma_mask is less than the system's memory
		 * size then this is not a candidate for identity mapping.
		 */
		u64 dma_mask = pdev->dma_mask;

		if (pdev->dev.coherent_dma_mask &&
		    pdev->dev.coherent_dma_mask < dma_mask)
			dma_mask = pdev->dev.coherent_dma_mask;

		return dma_mask >= dma_get_required_mask(&pdev->dev);
	}
2342 2343 2344 2345

	return 1;
}

2346
static int __init iommu_prepare_static_identity_mapping(int hw)
2347 2348 2349 2350
{
	struct pci_dev *pdev = NULL;
	int ret;

2351
	ret = si_domain_init(hw);
2352 2353 2354 2355
	if (ret)
		return -EFAULT;

	for_each_pci_dev(pdev) {
2356 2357 2358
		/* Skip Host/PCI Bridge devices */
		if (IS_BRIDGE_HOST_DEVICE(pdev))
			continue;
2359
		if (iommu_should_identity_map(pdev, 1)) {
2360 2361
			printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
			       hw ? "hardware" : "software", pci_name(pdev));
2362

2363
			ret = domain_add_dev_info(si_domain, pdev,
2364
						     hw ? CONTEXT_TT_PASS_THROUGH :
2365 2366 2367 2368
						     CONTEXT_TT_MULTI_LEVEL);
			if (ret)
				return ret;
		}
2369 2370 2371 2372 2373
	}

	return 0;
}

2374
static int __init init_dmars(void)
2375 2376 2377 2378 2379
{
	struct dmar_drhd_unit *drhd;
	struct dmar_rmrr_unit *rmrr;
	struct pci_dev *pdev;
	struct intel_iommu *iommu;
2380
	int i, ret;
2381

2382 2383 2384 2385 2386 2387 2388
	/*
	 * for each drhd
	 *    allocate root
	 *    initialize and program root entry to not present
	 * endfor
	 */
	for_each_drhd_unit(drhd) {
M
mark gross 已提交
2389 2390 2391 2392 2393 2394 2395 2396
		g_num_of_iommus++;
		/*
		 * lock not needed as this is only incremented in the single
		 * threaded kernel __init code path all other access are read
		 * only
		 */
	}

W
Weidong Han 已提交
2397 2398 2399 2400 2401 2402 2403 2404
	g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
			GFP_KERNEL);
	if (!g_iommus) {
		printk(KERN_ERR "Allocating global iommu array failed\n");
		ret = -ENOMEM;
		goto error;
	}

2405 2406 2407
	deferred_flush = kzalloc(g_num_of_iommus *
		sizeof(struct deferred_flush_tables), GFP_KERNEL);
	if (!deferred_flush) {
M
mark gross 已提交
2408 2409 2410 2411 2412 2413 2414
		ret = -ENOMEM;
		goto error;
	}

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
2415 2416

		iommu = drhd->iommu;
W
Weidong Han 已提交
2417
		g_iommus[iommu->seq_id] = iommu;
2418

2419 2420 2421 2422
		ret = iommu_init_domains(iommu);
		if (ret)
			goto error;

2423 2424 2425
		/*
		 * TBD:
		 * we could share the same root & context tables
L
Lucas De Marchi 已提交
2426
		 * among all IOMMU's. Need to Split it later.
2427 2428 2429 2430 2431 2432
		 */
		ret = iommu_alloc_root_entry(iommu);
		if (ret) {
			printk(KERN_ERR "IOMMU: allocate root entry failed\n");
			goto error;
		}
F
Fenghua Yu 已提交
2433
		if (!ecap_pass_through(iommu->ecap))
2434
			hw_pass_through = 0;
2435 2436
	}

2437 2438 2439
	/*
	 * Start from the sane iommu hardware state.
	 */
2440 2441 2442 2443 2444
	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;

		iommu = drhd->iommu;
2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470

		/*
		 * If the queued invalidation is already initialized by us
		 * (for example, while enabling interrupt-remapping) then
		 * we got the things already rolling from a sane state.
		 */
		if (iommu->qi)
			continue;

		/*
		 * Clear any previous faults.
		 */
		dmar_fault(-1, iommu);
		/*
		 * Disable queued invalidation if supported and already enabled
		 * before OS handover.
		 */
		dmar_disable_qi(iommu);
	}

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;

		iommu = drhd->iommu;

2471 2472 2473 2474 2475 2476 2477
		if (dmar_enable_qi(iommu)) {
			/*
			 * Queued Invalidate not enabled, use Register Based
			 * Invalidate
			 */
			iommu->flush.flush_context = __iommu_flush_context;
			iommu->flush.flush_iotlb = __iommu_flush_iotlb;
Y
Yinghai Lu 已提交
2478
			printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
2479
			       "invalidation\n",
Y
Yinghai Lu 已提交
2480
				iommu->seq_id,
2481
			       (unsigned long long)drhd->reg_base_addr);
2482 2483 2484
		} else {
			iommu->flush.flush_context = qi_flush_context;
			iommu->flush.flush_iotlb = qi_flush_iotlb;
Y
Yinghai Lu 已提交
2485
			printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
2486
			       "invalidation\n",
Y
Yinghai Lu 已提交
2487
				iommu->seq_id,
2488
			       (unsigned long long)drhd->reg_base_addr);
2489 2490 2491
		}
	}

2492
	if (iommu_pass_through)
2493 2494
		iommu_identity_mapping |= IDENTMAP_ALL;

2495
#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2496
	iommu_identity_mapping |= IDENTMAP_GFX;
2497
#endif
2498 2499 2500

	check_tylersburg_isoch();

2501
	/*
2502 2503 2504
	 * If pass through is not set or not enabled, setup context entries for
	 * identity mappings for rmrr, gfx, and isa and may fall back to static
	 * identity mapping if iommu_identity_mapping is set.
2505
	 */
2506 2507
	if (iommu_identity_mapping) {
		ret = iommu_prepare_static_identity_mapping(hw_pass_through);
F
Fenghua Yu 已提交
2508
		if (ret) {
2509 2510
			printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
			goto error;
2511 2512 2513
		}
	}
	/*
2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525
	 * For each rmrr
	 *   for each dev attached to rmrr
	 *   do
	 *     locate drhd for dev, alloc domain for dev
	 *     allocate free domain
	 *     allocate page table entries for rmrr
	 *     if context not allocated for bus
	 *           allocate and init context
	 *           set present in root table for this bus
	 *     init context with domain, translation etc
	 *    endfor
	 * endfor
2526
	 */
2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540
	printk(KERN_INFO "IOMMU: Setting RMRR:\n");
	for_each_rmrr_units(rmrr) {
		for (i = 0; i < rmrr->devices_cnt; i++) {
			pdev = rmrr->devices[i];
			/*
			 * some BIOS lists non-exist devices in DMAR
			 * table.
			 */
			if (!pdev)
				continue;
			ret = iommu_prepare_rmrr_dev(rmrr, pdev);
			if (ret)
				printk(KERN_ERR
				       "IOMMU: mapping reserved region failed\n");
2541
		}
F
Fenghua Yu 已提交
2542
	}
2543

2544 2545
	iommu_prepare_isa();

2546 2547 2548 2549 2550 2551 2552 2553
	/*
	 * for each drhd
	 *   enable fault log
	 *   global invalidate context cache
	 *   global invalidate iotlb
	 *   enable translation
	 */
	for_each_drhd_unit(drhd) {
2554 2555 2556 2557 2558 2559 2560
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(drhd->iommu);
2561
			continue;
2562
		}
2563 2564 2565 2566
		iommu = drhd->iommu;

		iommu_flush_write_buffer(iommu);

2567 2568 2569 2570
		ret = dmar_set_interrupt(iommu);
		if (ret)
			goto error;

2571 2572
		iommu_set_root_entry(iommu);

2573
		iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2574
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
M
mark gross 已提交
2575

2576 2577 2578
		ret = iommu_enable_translation(iommu);
		if (ret)
			goto error;
2579 2580

		iommu_disable_protect_mem_regions(iommu);
2581 2582 2583 2584 2585 2586 2587 2588 2589 2590
	}

	return 0;
error:
	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
		iommu = drhd->iommu;
		free_iommu(iommu);
	}
W
Weidong Han 已提交
2591
	kfree(g_iommus);
2592 2593 2594
	return ret;
}

2595
/* This takes a number of _MM_ pages, not VTD pages */
2596 2597 2598
static struct iova *intel_alloc_iova(struct device *dev,
				     struct dmar_domain *domain,
				     unsigned long nrpages, uint64_t dma_mask)
2599 2600 2601 2602
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct iova *iova = NULL;

2603 2604 2605 2606
	/* Restrict dma_mask to the width that the iommu can handle */
	dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);

	if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2607 2608
		/*
		 * First try to allocate an io virtual address in
2609
		 * DMA_BIT_MASK(32) and if that fails then try allocating
J
Joe Perches 已提交
2610
		 * from higher range
2611
		 */
2612 2613 2614 2615 2616 2617 2618 2619 2620
		iova = alloc_iova(&domain->iovad, nrpages,
				  IOVA_PFN(DMA_BIT_MASK(32)), 1);
		if (iova)
			return iova;
	}
	iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
	if (unlikely(!iova)) {
		printk(KERN_ERR "Allocating %ld-page iova for %s failed",
		       nrpages, pci_name(pdev));
2621 2622 2623 2624 2625 2626
		return NULL;
	}

	return iova;
}

2627
static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2628 2629 2630 2631 2632 2633 2634 2635 2636
{
	struct dmar_domain *domain;
	int ret;

	domain = get_domain_for_dev(pdev,
			DEFAULT_DOMAIN_ADDRESS_WIDTH);
	if (!domain) {
		printk(KERN_ERR
			"Allocating domain for %s failed", pci_name(pdev));
A
Al Viro 已提交
2637
		return NULL;
2638 2639 2640
	}

	/* make sure context mapping is ok */
W
Weidong Han 已提交
2641
	if (unlikely(!domain_context_mapped(pdev))) {
F
Fenghua Yu 已提交
2642 2643
		ret = domain_context_mapping(domain, pdev,
					     CONTEXT_TT_MULTI_LEVEL);
2644 2645 2646 2647
		if (ret) {
			printk(KERN_ERR
				"Domain context map for %s failed",
				pci_name(pdev));
A
Al Viro 已提交
2648
			return NULL;
2649
		}
2650 2651
	}

2652 2653 2654
	return domain;
}

2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666
static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
	info = dev->dev.archdata.iommu;
	if (likely(info))
		return info->domain;

	return __get_valid_domain_for_dev(dev);
}

2667 2668 2669 2670 2671 2672
static int iommu_dummy(struct pci_dev *pdev)
{
	return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
}

/* Check if the pdev needs to go through non-identity map and unmap process.*/
2673
static int iommu_no_mapping(struct device *dev)
2674
{
2675
	struct pci_dev *pdev;
2676 2677
	int found;

2678 2679 2680 2681
	if (unlikely(dev->bus != &pci_bus_type))
		return 1;

	pdev = to_pci_dev(dev);
2682 2683 2684
	if (iommu_dummy(pdev))
		return 1;

2685
	if (!iommu_identity_mapping)
2686
		return 0;
2687 2688 2689

	found = identity_mapping(pdev);
	if (found) {
2690
		if (iommu_should_identity_map(pdev, 0))
2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706
			return 1;
		else {
			/*
			 * 32 bit DMA is removed from si_domain and fall back
			 * to non-identity mapping.
			 */
			domain_remove_one_dev_info(si_domain, pdev);
			printk(KERN_INFO "32bit %s uses non-identity mapping\n",
			       pci_name(pdev));
			return 0;
		}
	} else {
		/*
		 * In case of a detached 64 bit DMA device from vm, the device
		 * is put into si_domain for identity mapping.
		 */
2707
		if (iommu_should_identity_map(pdev, 0)) {
2708
			int ret;
2709 2710 2711 2712
			ret = domain_add_dev_info(si_domain, pdev,
						  hw_pass_through ?
						  CONTEXT_TT_PASS_THROUGH :
						  CONTEXT_TT_MULTI_LEVEL);
2713 2714 2715 2716 2717 2718 2719 2720
			if (!ret) {
				printk(KERN_INFO "64bit %s uses identity mapping\n",
				       pci_name(pdev));
				return 1;
			}
		}
	}

2721
	return 0;
2722 2723
}

2724 2725
static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
				     size_t size, int dir, u64 dma_mask)
2726 2727 2728
{
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
F
Fenghua Yu 已提交
2729
	phys_addr_t start_paddr;
2730 2731
	struct iova *iova;
	int prot = 0;
I
Ingo Molnar 已提交
2732
	int ret;
2733
	struct intel_iommu *iommu;
2734
	unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2735 2736

	BUG_ON(dir == DMA_NONE);
2737

2738
	if (iommu_no_mapping(hwdev))
I
Ingo Molnar 已提交
2739
		return paddr;
2740 2741 2742 2743 2744

	domain = get_valid_domain_for_dev(pdev);
	if (!domain)
		return 0;

2745
	iommu = domain_get_iommu(domain);
2746
	size = aligned_nrpages(paddr, size);
2747

2748
	iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
2749 2750 2751
	if (!iova)
		goto error;

2752 2753 2754 2755 2756
	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2757
			!cap_zlr(iommu->cap))
2758 2759 2760 2761
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;
	/*
I
Ingo Molnar 已提交
2762
	 * paddr - (paddr + size) might be partial page, we should map the whole
2763
	 * page.  Note: if two part of one page are separately mapped, we
I
Ingo Molnar 已提交
2764
	 * might have two guest_addr mapping to the same host paddr, but this
2765 2766
	 * is not a big problem
	 */
2767
	ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2768
				 mm_to_dma_pfn(paddr_pfn), size, prot);
2769 2770 2771
	if (ret)
		goto error;

2772 2773
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
2774
		iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
2775
	else
2776
		iommu_flush_write_buffer(iommu);
2777

2778 2779 2780
	start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
	start_paddr += paddr & ~PAGE_MASK;
	return start_paddr;
2781 2782

error:
2783 2784
	if (iova)
		__free_iova(&domain->iovad, iova);
2785
	printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
F
Fenghua Yu 已提交
2786
		pci_name(pdev), size, (unsigned long long)paddr, dir);
2787 2788 2789
	return 0;
}

2790 2791 2792 2793
static dma_addr_t intel_map_page(struct device *dev, struct page *page,
				 unsigned long offset, size_t size,
				 enum dma_data_direction dir,
				 struct dma_attrs *attrs)
2794
{
2795 2796
	return __intel_map_single(dev, page_to_phys(page) + offset, size,
				  dir, to_pci_dev(dev)->dma_mask);
2797 2798
}

M
mark gross 已提交
2799 2800
static void flush_unmaps(void)
{
2801
	int i, j;
M
mark gross 已提交
2802 2803 2804 2805 2806

	timer_on = 0;

	/* just flush them all */
	for (i = 0; i < g_num_of_iommus; i++) {
2807 2808 2809
		struct intel_iommu *iommu = g_iommus[i];
		if (!iommu)
			continue;
2810

2811 2812 2813
		if (!deferred_flush[i].next)
			continue;

2814 2815 2816
		/* In caching mode, global flushes turn emulation expensive */
		if (!cap_caching_mode(iommu->cap))
			iommu->flush.flush_iotlb(iommu, 0, 0, 0,
Y
Yu Zhao 已提交
2817
					 DMA_TLB_GLOBAL_FLUSH);
2818
		for (j = 0; j < deferred_flush[i].next; j++) {
Y
Yu Zhao 已提交
2819 2820
			unsigned long mask;
			struct iova *iova = deferred_flush[i].iova[j];
2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831
			struct dmar_domain *domain = deferred_flush[i].domain[j];

			/* On real hardware multiple invalidations are expensive */
			if (cap_caching_mode(iommu->cap))
				iommu_flush_iotlb_psi(iommu, domain->id,
				iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
			else {
				mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
				iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
						(uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
			}
Y
Yu Zhao 已提交
2832
			__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2833
		}
2834
		deferred_flush[i].next = 0;
M
mark gross 已提交
2835 2836 2837 2838 2839 2840 2841
	}

	list_size = 0;
}

static void flush_unmaps_timeout(unsigned long data)
{
2842 2843 2844
	unsigned long flags;

	spin_lock_irqsave(&async_umap_flush_lock, flags);
M
mark gross 已提交
2845
	flush_unmaps();
2846
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
M
mark gross 已提交
2847 2848 2849 2850 2851
}

static void add_unmap(struct dmar_domain *dom, struct iova *iova)
{
	unsigned long flags;
2852
	int next, iommu_id;
2853
	struct intel_iommu *iommu;
M
mark gross 已提交
2854 2855

	spin_lock_irqsave(&async_umap_flush_lock, flags);
2856 2857 2858
	if (list_size == HIGH_WATER_MARK)
		flush_unmaps();

2859 2860
	iommu = domain_get_iommu(dom);
	iommu_id = iommu->seq_id;
2861

2862 2863 2864 2865
	next = deferred_flush[iommu_id].next;
	deferred_flush[iommu_id].domain[next] = dom;
	deferred_flush[iommu_id].iova[next] = iova;
	deferred_flush[iommu_id].next++;
M
mark gross 已提交
2866 2867 2868 2869 2870 2871 2872 2873 2874

	if (!timer_on) {
		mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
		timer_on = 1;
	}
	list_size++;
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
}

2875 2876 2877
static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
			     size_t size, enum dma_data_direction dir,
			     struct dma_attrs *attrs)
2878 2879
{
	struct pci_dev *pdev = to_pci_dev(dev);
2880
	struct dmar_domain *domain;
2881
	unsigned long start_pfn, last_pfn;
2882
	struct iova *iova;
2883
	struct intel_iommu *iommu;
2884

2885
	if (iommu_no_mapping(dev))
2886
		return;
2887

2888 2889 2890
	domain = find_domain(pdev);
	BUG_ON(!domain);

2891 2892
	iommu = domain_get_iommu(domain);

2893
	iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2894 2895
	if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
		      (unsigned long long)dev_addr))
2896 2897
		return;

2898 2899
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2900

2901 2902
	pr_debug("Device %s unmapping: pfn %lx-%lx\n",
		 pci_name(pdev), start_pfn, last_pfn);
2903

2904
	/*  clear the whole page */
2905 2906
	dma_pte_clear_range(domain, start_pfn, last_pfn);

2907
	/* free page tables */
2908 2909
	dma_pte_free_pagetable(domain, start_pfn, last_pfn);

M
mark gross 已提交
2910
	if (intel_iommu_strict) {
2911
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2912
				      last_pfn - start_pfn + 1, 0);
M
mark gross 已提交
2913 2914 2915 2916 2917 2918 2919 2920 2921
		/* free iova */
		__free_iova(&domain->iovad, iova);
	} else {
		add_unmap(domain, iova);
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
2922 2923
}

2924 2925
static void *intel_alloc_coherent(struct device *hwdev, size_t size,
				  dma_addr_t *dma_handle, gfp_t flags)
2926 2927 2928 2929
{
	void *vaddr;
	int order;

F
Fenghua Yu 已提交
2930
	size = PAGE_ALIGN(size);
2931
	order = get_order(size);
2932 2933 2934 2935 2936 2937 2938 2939 2940

	if (!iommu_no_mapping(hwdev))
		flags &= ~(GFP_DMA | GFP_DMA32);
	else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
		if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
			flags |= GFP_DMA;
		else
			flags |= GFP_DMA32;
	}
2941 2942 2943 2944 2945 2946

	vaddr = (void *)__get_free_pages(flags, order);
	if (!vaddr)
		return NULL;
	memset(vaddr, 0, size);

2947 2948 2949
	*dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
					 DMA_BIDIRECTIONAL,
					 hwdev->coherent_dma_mask);
2950 2951 2952 2953 2954 2955
	if (*dma_handle)
		return vaddr;
	free_pages((unsigned long)vaddr, order);
	return NULL;
}

2956 2957
static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
				dma_addr_t dma_handle)
2958 2959 2960
{
	int order;

F
Fenghua Yu 已提交
2961
	size = PAGE_ALIGN(size);
2962 2963
	order = get_order(size);

2964
	intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
2965 2966 2967
	free_pages((unsigned long)vaddr, order);
}

2968 2969 2970
static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
			   int nelems, enum dma_data_direction dir,
			   struct dma_attrs *attrs)
2971 2972 2973
{
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
2974
	unsigned long start_pfn, last_pfn;
2975
	struct iova *iova;
2976
	struct intel_iommu *iommu;
2977

2978
	if (iommu_no_mapping(hwdev))
2979 2980 2981
		return;

	domain = find_domain(pdev);
2982 2983 2984
	BUG_ON(!domain);

	iommu = domain_get_iommu(domain);
2985

F
FUJITA Tomonori 已提交
2986
	iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2987 2988
	if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
		      (unsigned long long)sglist[0].dma_address))
2989 2990
		return;

2991 2992
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2993 2994

	/*  clear the whole page */
2995 2996
	dma_pte_clear_range(domain, start_pfn, last_pfn);

2997
	/* free page tables */
2998
	dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2999

3000 3001
	if (intel_iommu_strict) {
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
3002
				      last_pfn - start_pfn + 1, 0);
3003 3004 3005 3006 3007 3008 3009 3010 3011
		/* free iova */
		__free_iova(&domain->iovad, iova);
	} else {
		add_unmap(domain, iova);
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
3012 3013 3014
}

static int intel_nontranslate_map_sg(struct device *hddev,
F
FUJITA Tomonori 已提交
3015
	struct scatterlist *sglist, int nelems, int dir)
3016 3017
{
	int i;
F
FUJITA Tomonori 已提交
3018
	struct scatterlist *sg;
3019

F
FUJITA Tomonori 已提交
3020
	for_each_sg(sglist, sg, nelems, i) {
F
FUJITA Tomonori 已提交
3021
		BUG_ON(!sg_page(sg));
3022
		sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
F
FUJITA Tomonori 已提交
3023
		sg->dma_length = sg->length;
3024 3025 3026 3027
	}
	return nelems;
}

3028 3029
static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
			enum dma_data_direction dir, struct dma_attrs *attrs)
3030 3031 3032 3033
{
	int i;
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
3034 3035 3036 3037
	size_t size = 0;
	int prot = 0;
	struct iova *iova = NULL;
	int ret;
F
FUJITA Tomonori 已提交
3038
	struct scatterlist *sg;
3039
	unsigned long start_vpfn;
3040
	struct intel_iommu *iommu;
3041 3042

	BUG_ON(dir == DMA_NONE);
3043
	if (iommu_no_mapping(hwdev))
F
FUJITA Tomonori 已提交
3044
		return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
3045

3046 3047 3048 3049
	domain = get_valid_domain_for_dev(pdev);
	if (!domain)
		return 0;

3050 3051
	iommu = domain_get_iommu(domain);

3052
	for_each_sg(sglist, sg, nelems, i)
3053
		size += aligned_nrpages(sg->offset, sg->length);
3054

3055 3056
	iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
				pdev->dma_mask);
3057
	if (!iova) {
F
FUJITA Tomonori 已提交
3058
		sglist->dma_length = 0;
3059 3060 3061 3062 3063 3064 3065 3066
		return 0;
	}

	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3067
			!cap_zlr(iommu->cap))
3068 3069 3070 3071
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;

3072
	start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3073

3074
	ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3075 3076 3077 3078 3079 3080 3081 3082 3083 3084
	if (unlikely(ret)) {
		/*  clear the page */
		dma_pte_clear_range(domain, start_vpfn,
				    start_vpfn + size - 1);
		/* free page tables */
		dma_pte_free_pagetable(domain, start_vpfn,
				       start_vpfn + size - 1);
		/* free iova */
		__free_iova(&domain->iovad, iova);
		return 0;
3085 3086
	}

3087 3088
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3089
		iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
3090
	else
3091
		iommu_flush_write_buffer(iommu);
3092

3093 3094 3095
	return nelems;
}

3096 3097 3098 3099 3100
static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return !dma_addr;
}

3101
struct dma_map_ops intel_dma_ops = {
3102 3103 3104 3105
	.alloc_coherent = intel_alloc_coherent,
	.free_coherent = intel_free_coherent,
	.map_sg = intel_map_sg,
	.unmap_sg = intel_unmap_sg,
3106 3107
	.map_page = intel_map_page,
	.unmap_page = intel_unmap_page,
3108
	.mapping_error = intel_mapping_error,
3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192
};

static inline int iommu_domain_cache_init(void)
{
	int ret = 0;

	iommu_domain_cache = kmem_cache_create("iommu_domain",
					 sizeof(struct dmar_domain),
					 0,
					 SLAB_HWCACHE_ALIGN,

					 NULL);
	if (!iommu_domain_cache) {
		printk(KERN_ERR "Couldn't create iommu_domain cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_devinfo_cache_init(void)
{
	int ret = 0;

	iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
					 sizeof(struct device_domain_info),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_devinfo_cache) {
		printk(KERN_ERR "Couldn't create devinfo cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_iova_cache_init(void)
{
	int ret = 0;

	iommu_iova_cache = kmem_cache_create("iommu_iova",
					 sizeof(struct iova),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_iova_cache) {
		printk(KERN_ERR "Couldn't create iova cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static int __init iommu_init_mempool(void)
{
	int ret;
	ret = iommu_iova_cache_init();
	if (ret)
		return ret;

	ret = iommu_domain_cache_init();
	if (ret)
		goto domain_error;

	ret = iommu_devinfo_cache_init();
	if (!ret)
		return ret;

	kmem_cache_destroy(iommu_domain_cache);
domain_error:
	kmem_cache_destroy(iommu_iova_cache);

	return -ENOMEM;
}

static void __init iommu_exit_mempool(void)
{
	kmem_cache_destroy(iommu_devinfo_cache);
	kmem_cache_destroy(iommu_domain_cache);
	kmem_cache_destroy(iommu_iova_cache);

}

3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
{
	struct dmar_drhd_unit *drhd;
	u32 vtbar;
	int rc;

	/* We know that this device on this chipset has its own IOMMU.
	 * If we find it under a different IOMMU, then the BIOS is lying
	 * to us. Hope that the IOMMU for this device is actually
	 * disabled, and it needs no translation...
	 */
	rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
	if (rc) {
		/* "can't" happen */
		dev_info(&pdev->dev, "failed to run vt-d quirk\n");
		return;
	}
	vtbar &= 0xffff0000;

	/* we know that the this iommu should be at offset 0xa000 from vtbar */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
			    TAINT_FIRMWARE_WORKAROUND,
			    "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
		pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);

3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243
static void __init init_no_remapping_devices(void)
{
	struct dmar_drhd_unit *drhd;

	for_each_drhd_unit(drhd) {
		if (!drhd->include_all) {
			int i;
			for (i = 0; i < drhd->devices_cnt; i++)
				if (drhd->devices[i] != NULL)
					break;
			/* ignore DMAR unit if no pci devices exist */
			if (i == drhd->devices_cnt)
				drhd->ignored = 1;
		}
	}

	for_each_drhd_unit(drhd) {
		int i;
		if (drhd->ignored || drhd->include_all)
			continue;

		for (i = 0; i < drhd->devices_cnt; i++)
			if (drhd->devices[i] &&
3244
			    !IS_GFX_DEVICE(drhd->devices[i]))
3245 3246 3247 3248 3249
				break;

		if (i < drhd->devices_cnt)
			continue;

3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260
		/* This IOMMU has *only* gfx devices. Either bypass it or
		   set the gfx_mapped flag, as appropriate */
		if (dmar_map_gfx) {
			intel_iommu_gfx_mapped = 1;
		} else {
			drhd->ignored = 1;
			for (i = 0; i < drhd->devices_cnt; i++) {
				if (!drhd->devices[i])
					continue;
				drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
			}
3261 3262 3263 3264
		}
	}
}

3265 3266 3267 3268 3269 3270 3271 3272 3273 3274
#ifdef CONFIG_SUSPEND
static int init_iommu_hw(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;

	for_each_active_iommu(iommu, drhd)
		if (iommu->qi)
			dmar_reenable_qi(iommu);

3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285
	for_each_iommu(iommu, drhd) {
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(iommu);
			continue;
		}
	
3286 3287 3288 3289 3290
		iommu_flush_write_buffer(iommu);

		iommu_set_root_entry(iommu);

		iommu->flush.flush_context(iommu, 0, 0, 0,
3291
					   DMA_CCMD_GLOBAL_INVL);
3292
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3293
					 DMA_TLB_GLOBAL_FLUSH);
3294 3295
		if (iommu_enable_translation(iommu))
			return 1;
3296
		iommu_disable_protect_mem_regions(iommu);
3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308
	}

	return 0;
}

static void iommu_flush_all(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;

	for_each_active_iommu(iommu, drhd) {
		iommu->flush.flush_context(iommu, 0, 0, 0,
3309
					   DMA_CCMD_GLOBAL_INVL);
3310
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3311
					 DMA_TLB_GLOBAL_FLUSH);
3312 3313 3314
	}
}

3315
static int iommu_suspend(void)
3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	for_each_active_iommu(iommu, drhd) {
		iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
						 GFP_ATOMIC);
		if (!iommu->iommu_state)
			goto nomem;
	}

	iommu_flush_all();

	for_each_active_iommu(iommu, drhd) {
		iommu_disable_translation(iommu);

3333
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3334 3335 3336 3337 3338 3339 3340 3341 3342 3343

		iommu->iommu_state[SR_DMAR_FECTL_REG] =
			readl(iommu->reg + DMAR_FECTL_REG);
		iommu->iommu_state[SR_DMAR_FEDATA_REG] =
			readl(iommu->reg + DMAR_FEDATA_REG);
		iommu->iommu_state[SR_DMAR_FEADDR_REG] =
			readl(iommu->reg + DMAR_FEADDR_REG);
		iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
			readl(iommu->reg + DMAR_FEUADDR_REG);

3344
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3345 3346 3347 3348 3349 3350 3351 3352 3353 3354
	}
	return 0;

nomem:
	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);

	return -ENOMEM;
}

3355
static void iommu_resume(void)
3356 3357 3358 3359 3360 3361
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	if (init_iommu_hw()) {
3362 3363 3364 3365
		if (force_on)
			panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
		else
			WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3366
		return;
3367 3368 3369 3370
	}

	for_each_active_iommu(iommu, drhd) {

3371
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3372 3373 3374 3375 3376 3377 3378 3379 3380 3381

		writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
			iommu->reg + DMAR_FECTL_REG);
		writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
			iommu->reg + DMAR_FEDATA_REG);
		writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
			iommu->reg + DMAR_FEADDR_REG);
		writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
			iommu->reg + DMAR_FEUADDR_REG);

3382
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3383 3384 3385 3386 3387 3388
	}

	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);
}

3389
static struct syscore_ops iommu_syscore_ops = {
3390 3391 3392 3393
	.resume		= iommu_resume,
	.suspend	= iommu_suspend,
};

3394
static void __init init_iommu_pm_ops(void)
3395
{
3396
	register_syscore_ops(&iommu_syscore_ops);
3397 3398 3399
}

#else
3400
static inline void init_iommu_pm_ops(void) {}
3401 3402
#endif	/* CONFIG_PM */

3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547
LIST_HEAD(dmar_rmrr_units);

static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
{
	list_add(&rmrr->list, &dmar_rmrr_units);
}


int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
{
	struct acpi_dmar_reserved_memory *rmrr;
	struct dmar_rmrr_unit *rmrru;

	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
	if (!rmrru)
		return -ENOMEM;

	rmrru->hdr = header;
	rmrr = (struct acpi_dmar_reserved_memory *)header;
	rmrru->base_address = rmrr->base_address;
	rmrru->end_address = rmrr->end_address;

	dmar_register_rmrr_unit(rmrru);
	return 0;
}

static int __init
rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
{
	struct acpi_dmar_reserved_memory *rmrr;
	int ret;

	rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
	ret = dmar_parse_dev_scope((void *)(rmrr + 1),
		((void *)rmrr) + rmrr->header.length,
		&rmrru->devices_cnt, &rmrru->devices, rmrr->segment);

	if (ret || (rmrru->devices_cnt == 0)) {
		list_del(&rmrru->list);
		kfree(rmrru);
	}
	return ret;
}

static LIST_HEAD(dmar_atsr_units);

int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
	if (!atsru)
		return -ENOMEM;

	atsru->hdr = hdr;
	atsru->include_all = atsr->flags & 0x1;

	list_add(&atsru->list, &dmar_atsr_units);

	return 0;
}

static int __init atsr_parse_dev(struct dmar_atsr_unit *atsru)
{
	int rc;
	struct acpi_dmar_atsr *atsr;

	if (atsru->include_all)
		return 0;

	atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
	rc = dmar_parse_dev_scope((void *)(atsr + 1),
				(void *)atsr + atsr->header.length,
				&atsru->devices_cnt, &atsru->devices,
				atsr->segment);
	if (rc || !atsru->devices_cnt) {
		list_del(&atsru->list);
		kfree(atsru);
	}

	return rc;
}

int dmar_find_matched_atsr_unit(struct pci_dev *dev)
{
	int i;
	struct pci_bus *bus;
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	dev = pci_physfn(dev);

	list_for_each_entry(atsru, &dmar_atsr_units, list) {
		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (atsr->segment == pci_domain_nr(dev->bus))
			goto found;
	}

	return 0;

found:
	for (bus = dev->bus; bus; bus = bus->parent) {
		struct pci_dev *bridge = bus->self;

		if (!bridge || !pci_is_pcie(bridge) ||
		    bridge->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
			return 0;

		if (bridge->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
			for (i = 0; i < atsru->devices_cnt; i++)
				if (atsru->devices[i] == bridge)
					return 1;
			break;
		}
	}

	if (atsru->include_all)
		return 1;

	return 0;
}

int dmar_parse_rmrr_atsr_dev(void)
{
	struct dmar_rmrr_unit *rmrr, *rmrr_n;
	struct dmar_atsr_unit *atsr, *atsr_n;
	int ret = 0;

	list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
		ret = rmrr_parse_dev(rmrr);
		if (ret)
			return ret;
	}

	list_for_each_entry_safe(atsr, atsr_n, &dmar_atsr_units, list) {
		ret = atsr_parse_dev(atsr);
		if (ret)
			return ret;
	}

	return ret;
}

F
Fenghua Yu 已提交
3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560
/*
 * Here we only respond to action of unbound device from driver.
 *
 * Added device is not attached to its DMAR domain here yet. That will happen
 * when mapping the device to iova.
 */
static int device_notifier(struct notifier_block *nb,
				  unsigned long action, void *data)
{
	struct device *dev = data;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct dmar_domain *domain;

3561 3562 3563
	if (iommu_no_mapping(dev))
		return 0;

F
Fenghua Yu 已提交
3564 3565 3566 3567
	domain = find_domain(pdev);
	if (!domain)
		return 0;

3568
	if (action == BUS_NOTIFY_UNBOUND_DRIVER && !iommu_pass_through) {
F
Fenghua Yu 已提交
3569 3570
		domain_remove_one_dev_info(domain, pdev);

3571 3572 3573 3574 3575 3576
		if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
		    !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
		    list_empty(&domain->devices))
			domain_exit(domain);
	}

F
Fenghua Yu 已提交
3577 3578 3579 3580 3581 3582 3583
	return 0;
}

static struct notifier_block device_nb = {
	.notifier_call = device_notifier,
};

3584 3585 3586 3587
int __init intel_iommu_init(void)
{
	int ret = 0;

3588 3589 3590 3591 3592 3593
	/* VT-d is required for a TXT/tboot launch, so enforce that */
	force_on = tboot_force_iommu();

	if (dmar_table_init()) {
		if (force_on)
			panic("tboot: Failed to initialize DMAR table\n");
3594
		return 	-ENODEV;
3595
	}
3596

3597
	if (dmar_dev_scope_init() < 0) {
3598 3599
		if (force_on)
			panic("tboot: Failed to initialize DMAR device scope\n");
3600
		return 	-ENODEV;
3601
	}
3602

3603
	if (no_iommu || dmar_disabled)
3604 3605
		return -ENODEV;

3606 3607 3608 3609 3610 3611
	if (iommu_init_mempool()) {
		if (force_on)
			panic("tboot: Failed to initialize iommu memory\n");
		return 	-ENODEV;
	}

3612 3613 3614 3615 3616 3617
	if (list_empty(&dmar_rmrr_units))
		printk(KERN_INFO "DMAR: No RMRR found\n");

	if (list_empty(&dmar_atsr_units))
		printk(KERN_INFO "DMAR: No ATSR found\n");

3618 3619 3620 3621 3622
	if (dmar_init_reserved_ranges()) {
		if (force_on)
			panic("tboot: Failed to reserve iommu ranges\n");
		return 	-ENODEV;
	}
3623 3624 3625

	init_no_remapping_devices();

3626
	ret = init_dmars();
3627
	if (ret) {
3628 3629
		if (force_on)
			panic("tboot: Failed to initialize DMARs\n");
3630 3631 3632 3633 3634 3635 3636 3637
		printk(KERN_ERR "IOMMU: dmar init failed\n");
		put_iova_domain(&reserved_iova_list);
		iommu_exit_mempool();
		return ret;
	}
	printk(KERN_INFO
	"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");

M
mark gross 已提交
3638
	init_timer(&unmap_timer);
3639 3640 3641
#ifdef CONFIG_SWIOTLB
	swiotlb = 0;
#endif
3642
	dma_ops = &intel_dma_ops;
F
Fenghua Yu 已提交
3643

3644
	init_iommu_pm_ops();
3645

3646
	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
3647

F
Fenghua Yu 已提交
3648 3649
	bus_register_notifier(&pci_bus_type, &device_nb);

3650 3651
	return 0;
}
3652

3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667
static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
					   struct pci_dev *pdev)
{
	struct pci_dev *tmp, *parent;

	if (!iommu || !pdev)
		return;

	/* dependent device detach */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	/* Secondary interface's bus number and devfn 0 */
	if (tmp) {
		parent = pdev->bus->self;
		while (parent != tmp) {
			iommu_detach_dev(iommu, parent->bus->number,
3668
					 parent->devfn);
3669 3670
			parent = parent->bus->self;
		}
3671
		if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3672 3673 3674
			iommu_detach_dev(iommu,
				tmp->subordinate->number, 0);
		else /* this is a legacy PCI bridge */
3675 3676
			iommu_detach_dev(iommu, tmp->bus->number,
					 tmp->devfn);
3677 3678 3679
	}
}

3680
static void domain_remove_one_dev_info(struct dmar_domain *domain,
3681 3682 3683 3684 3685 3686 3687 3688
					  struct pci_dev *pdev)
{
	struct device_domain_info *info;
	struct intel_iommu *iommu;
	unsigned long flags;
	int found = 0;
	struct list_head *entry, *tmp;

3689 3690
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
3691 3692 3693 3694 3695 3696
	if (!iommu)
		return;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_safe(entry, tmp, &domain->devices) {
		info = list_entry(entry, struct device_domain_info, link);
3697 3698
		if (info->segment == pci_domain_nr(pdev->bus) &&
		    info->bus == pdev->bus->number &&
3699 3700 3701 3702 3703 3704 3705
		    info->devfn == pdev->devfn) {
			list_del(&info->link);
			list_del(&info->global);
			if (info->dev)
				info->dev->dev.archdata.iommu = NULL;
			spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
3706
			iommu_disable_dev_iotlb(info);
3707
			iommu_detach_dev(iommu, info->bus, info->devfn);
3708
			iommu_detach_dependent_devices(iommu, pdev);
3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722
			free_devinfo_mem(info);

			spin_lock_irqsave(&device_domain_lock, flags);

			if (found)
				break;
			else
				continue;
		}

		/* if there is no other devices under the same iommu
		 * owned by this domain, clear this iommu in iommu_bmp
		 * update iommu count and coherency
		 */
3723 3724
		if (iommu == device_to_iommu(info->segment, info->bus,
					    info->devfn))
3725 3726 3727
			found = 1;
	}

3728 3729
	spin_unlock_irqrestore(&device_domain_lock, flags);

3730 3731 3732 3733 3734
	if (found == 0) {
		unsigned long tmp_flags;
		spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
		clear_bit(iommu->seq_id, &domain->iommu_bmp);
		domain->iommu_count--;
3735
		domain_update_iommu_cap(domain);
3736
		spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3737

3738 3739 3740 3741 3742 3743 3744
		if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
		    !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
			spin_lock_irqsave(&iommu->lock, tmp_flags);
			clear_bit(domain->id, iommu->domain_ids);
			iommu->domains[domain->id] = NULL;
			spin_unlock_irqrestore(&iommu->lock, tmp_flags);
		}
3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764
	}
}

static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	struct intel_iommu *iommu;
	unsigned long flags1, flags2;

	spin_lock_irqsave(&device_domain_lock, flags1);
	while (!list_empty(&domain->devices)) {
		info = list_entry(domain->devices.next,
			struct device_domain_info, link);
		list_del(&info->link);
		list_del(&info->global);
		if (info->dev)
			info->dev->dev.archdata.iommu = NULL;

		spin_unlock_irqrestore(&device_domain_lock, flags1);

Y
Yu Zhao 已提交
3765
		iommu_disable_dev_iotlb(info);
3766
		iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3767
		iommu_detach_dev(iommu, info->bus, info->devfn);
3768
		iommu_detach_dependent_devices(iommu, info->dev);
3769 3770

		/* clear this iommu in iommu_bmp, update iommu count
3771
		 * and capabilities
3772 3773 3774 3775 3776
		 */
		spin_lock_irqsave(&domain->iommu_lock, flags2);
		if (test_and_clear_bit(iommu->seq_id,
				       &domain->iommu_bmp)) {
			domain->iommu_count--;
3777
			domain_update_iommu_cap(domain);
3778 3779 3780 3781 3782 3783 3784 3785 3786
		}
		spin_unlock_irqrestore(&domain->iommu_lock, flags2);

		free_devinfo_mem(info);
		spin_lock_irqsave(&device_domain_lock, flags1);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags1);
}

3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798
/* domain id for virtual machine, it won't be set in context */
static unsigned long vm_domid;

static struct dmar_domain *iommu_alloc_vm_domain(void)
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

	domain->id = vm_domid++;
3799
	domain->nid = -1;
3800 3801 3802 3803 3804 3805
	memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
	domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;

	return domain;
}

3806
static int md_domain_init(struct dmar_domain *domain, int guest_width)
3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823
{
	int adjust_width;

	init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
	spin_lock_init(&domain->iommu_lock);

	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	domain->agaw = width_to_agaw(adjust_width);

	INIT_LIST_HEAD(&domain->devices);

	domain->iommu_count = 0;
	domain->iommu_coherency = 0;
3824
	domain->iommu_snooping = 0;
3825
	domain->iommu_superpage = 0;
3826
	domain->max_addr = 0;
3827
	domain->nid = -1;
3828 3829

	/* always allocate the top pgd */
3830
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850
	if (!domain->pgd)
		return -ENOMEM;
	domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
	return 0;
}

static void iommu_free_vm_domain(struct dmar_domain *domain)
{
	unsigned long flags;
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	unsigned long i;
	unsigned long ndomains;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
		iommu = drhd->iommu;

		ndomains = cap_ndoms(iommu->cap);
3851
		for_each_set_bit(i, iommu->domain_ids, ndomains) {
3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873
			if (iommu->domains[i] == domain) {
				spin_lock_irqsave(&iommu->lock, flags);
				clear_bit(i, iommu->domain_ids);
				iommu->domains[i] = NULL;
				spin_unlock_irqrestore(&iommu->lock, flags);
				break;
			}
		}
	}
}

static void vm_domain_exit(struct dmar_domain *domain)
{
	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

	vm_domain_remove_all_dev_info(domain);
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

	/* clear ptes */
3874
	dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3875 3876

	/* free page tables */
3877
	dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3878 3879 3880 3881 3882

	iommu_free_vm_domain(domain);
	free_domain_mem(domain);
}

3883
static int intel_iommu_domain_init(struct iommu_domain *domain)
K
Kay, Allen M 已提交
3884
{
3885
	struct dmar_domain *dmar_domain;
K
Kay, Allen M 已提交
3886

3887 3888
	dmar_domain = iommu_alloc_vm_domain();
	if (!dmar_domain) {
K
Kay, Allen M 已提交
3889
		printk(KERN_ERR
3890 3891
			"intel_iommu_domain_init: dmar_domain == NULL\n");
		return -ENOMEM;
K
Kay, Allen M 已提交
3892
	}
3893
	if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
K
Kay, Allen M 已提交
3894
		printk(KERN_ERR
3895 3896 3897
			"intel_iommu_domain_init() failed\n");
		vm_domain_exit(dmar_domain);
		return -ENOMEM;
K
Kay, Allen M 已提交
3898
	}
3899
	domain_update_iommu_cap(dmar_domain);
3900
	domain->priv = dmar_domain;
3901

3902
	return 0;
K
Kay, Allen M 已提交
3903 3904
}

3905
static void intel_iommu_domain_destroy(struct iommu_domain *domain)
K
Kay, Allen M 已提交
3906
{
3907 3908 3909 3910
	struct dmar_domain *dmar_domain = domain->priv;

	domain->priv = NULL;
	vm_domain_exit(dmar_domain);
K
Kay, Allen M 已提交
3911 3912
}

3913 3914
static int intel_iommu_attach_device(struct iommu_domain *domain,
				     struct device *dev)
K
Kay, Allen M 已提交
3915
{
3916 3917
	struct dmar_domain *dmar_domain = domain->priv;
	struct pci_dev *pdev = to_pci_dev(dev);
3918 3919
	struct intel_iommu *iommu;
	int addr_width;
3920 3921 3922 3923 3924 3925 3926

	/* normally pdev is not mapped */
	if (unlikely(domain_context_mapped(pdev))) {
		struct dmar_domain *old_domain;

		old_domain = find_domain(pdev);
		if (old_domain) {
3927 3928 3929
			if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
			    dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
				domain_remove_one_dev_info(old_domain, pdev);
3930 3931 3932 3933 3934
			else
				domain_remove_dev_info(old_domain);
		}
	}

3935 3936
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
3937 3938 3939 3940 3941
	if (!iommu)
		return -ENODEV;

	/* check if this iommu agaw is sufficient for max mapped address */
	addr_width = agaw_to_width(iommu->agaw);
3942 3943 3944 3945 3946
	if (addr_width > cap_mgaw(iommu->cap))
		addr_width = cap_mgaw(iommu->cap);

	if (dmar_domain->max_addr > (1LL << addr_width)) {
		printk(KERN_ERR "%s: iommu width (%d) is not "
3947
		       "sufficient for the mapped address (%llx)\n",
3948
		       __func__, addr_width, dmar_domain->max_addr);
3949 3950
		return -EFAULT;
	}
3951 3952 3953 3954 3955 3956 3957 3958 3959 3960
	dmar_domain->gaw = addr_width;

	/*
	 * Knock out extra levels of page tables if necessary
	 */
	while (iommu->agaw < dmar_domain->agaw) {
		struct dma_pte *pte;

		pte = dmar_domain->pgd;
		if (dma_pte_present(pte)) {
3961 3962
			dmar_domain->pgd = (struct dma_pte *)
				phys_to_virt(dma_pte_addr(pte));
3963
			free_pgtable_page(pte);
3964 3965 3966
		}
		dmar_domain->agaw--;
	}
3967

3968
	return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
K
Kay, Allen M 已提交
3969 3970
}

3971 3972
static void intel_iommu_detach_device(struct iommu_domain *domain,
				      struct device *dev)
K
Kay, Allen M 已提交
3973
{
3974 3975 3976
	struct dmar_domain *dmar_domain = domain->priv;
	struct pci_dev *pdev = to_pci_dev(dev);

3977
	domain_remove_one_dev_info(dmar_domain, pdev);
3978
}
3979

3980 3981 3982
static int intel_iommu_map(struct iommu_domain *domain,
			   unsigned long iova, phys_addr_t hpa,
			   int gfp_order, int iommu_prot)
3983
{
3984
	struct dmar_domain *dmar_domain = domain->priv;
3985
	u64 max_addr;
3986
	int prot = 0;
3987
	size_t size;
3988
	int ret;
3989

3990 3991 3992 3993
	if (iommu_prot & IOMMU_READ)
		prot |= DMA_PTE_READ;
	if (iommu_prot & IOMMU_WRITE)
		prot |= DMA_PTE_WRITE;
3994 3995
	if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
		prot |= DMA_PTE_SNP;
3996

3997
	size     = PAGE_SIZE << gfp_order;
3998
	max_addr = iova + size;
3999
	if (dmar_domain->max_addr < max_addr) {
4000 4001 4002
		u64 end;

		/* check if minimum agaw is sufficient for mapped address */
4003
		end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4004
		if (end < max_addr) {
4005
			printk(KERN_ERR "%s: iommu width (%d) is not "
4006
			       "sufficient for the mapped address (%llx)\n",
4007
			       __func__, dmar_domain->gaw, max_addr);
4008 4009
			return -EFAULT;
		}
4010
		dmar_domain->max_addr = max_addr;
4011
	}
4012 4013
	/* Round up size to next multiple of PAGE_SIZE, if it and
	   the low bits of hpa would take us onto the next page */
4014
	size = aligned_nrpages(hpa, size);
4015 4016
	ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
				 hpa >> VTD_PAGE_SHIFT, size, prot);
4017
	return ret;
K
Kay, Allen M 已提交
4018 4019
}

4020 4021
static int intel_iommu_unmap(struct iommu_domain *domain,
			     unsigned long iova, int gfp_order)
K
Kay, Allen M 已提交
4022
{
4023
	struct dmar_domain *dmar_domain = domain->priv;
4024
	size_t size = PAGE_SIZE << gfp_order;
4025
	int order;
4026

4027
	order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
4028
			    (iova + size - 1) >> VTD_PAGE_SHIFT);
4029

4030 4031
	if (dmar_domain->max_addr == iova + size)
		dmar_domain->max_addr = iova;
4032

4033
	return order;
K
Kay, Allen M 已提交
4034 4035
}

4036 4037
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
					    unsigned long iova)
K
Kay, Allen M 已提交
4038
{
4039
	struct dmar_domain *dmar_domain = domain->priv;
K
Kay, Allen M 已提交
4040
	struct dma_pte *pte;
4041
	u64 phys = 0;
K
Kay, Allen M 已提交
4042

4043
	pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
K
Kay, Allen M 已提交
4044
	if (pte)
4045
		phys = dma_pte_addr(pte);
K
Kay, Allen M 已提交
4046

4047
	return phys;
K
Kay, Allen M 已提交
4048
}
4049

S
Sheng Yang 已提交
4050 4051 4052 4053 4054 4055 4056
static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
				      unsigned long cap)
{
	struct dmar_domain *dmar_domain = domain->priv;

	if (cap == IOMMU_CAP_CACHE_COHERENCY)
		return dmar_domain->iommu_snooping;
4057 4058
	if (cap == IOMMU_CAP_INTR_REMAP)
		return intr_remapping_enabled;
S
Sheng Yang 已提交
4059 4060 4061 4062

	return 0;
}

4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107
/*
 * Group numbers are arbitrary.  Device with the same group number
 * indicate the iommu cannot differentiate between them.  To avoid
 * tracking used groups we just use the seg|bus|devfn of the lowest
 * level we're able to differentiate devices
 */
static int intel_iommu_device_group(struct device *dev, unsigned int *groupid)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct pci_dev *bridge;
	union {
		struct {
			u8 devfn;
			u8 bus;
			u16 segment;
		} pci;
		u32 group;
	} id;

	if (iommu_no_mapping(dev))
		return -ENODEV;

	id.pci.segment = pci_domain_nr(pdev->bus);
	id.pci.bus = pdev->bus->number;
	id.pci.devfn = pdev->devfn;

	if (!device_to_iommu(id.pci.segment, id.pci.bus, id.pci.devfn))
		return -ENODEV;

	bridge = pci_find_upstream_pcie_bridge(pdev);
	if (bridge) {
		if (pci_is_pcie(bridge)) {
			id.pci.bus = bridge->subordinate->number;
			id.pci.devfn = 0;
		} else {
			id.pci.bus = bridge->bus->number;
			id.pci.devfn = bridge->devfn;
		}
	}

	*groupid = id.group;

	return 0;
}

4108 4109 4110 4111 4112
static struct iommu_ops intel_iommu_ops = {
	.domain_init	= intel_iommu_domain_init,
	.domain_destroy = intel_iommu_domain_destroy,
	.attach_dev	= intel_iommu_attach_device,
	.detach_dev	= intel_iommu_detach_device,
4113 4114
	.map		= intel_iommu_map,
	.unmap		= intel_iommu_unmap,
4115
	.iova_to_phys	= intel_iommu_iova_to_phys,
S
Sheng Yang 已提交
4116
	.domain_has_cap = intel_iommu_domain_has_cap,
4117
	.device_group	= intel_iommu_device_group,
4118
};
4119 4120 4121 4122 4123 4124 4125 4126 4127

static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
{
	/*
	 * Mobile 4 Series Chipset neglects to set RWBF capability,
	 * but needs it:
	 */
	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
	rwbf_quirk = 1;
4128 4129 4130 4131 4132 4133

	/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
	if (dev->revision == 0x07) {
		printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
		dmar_map_gfx = 0;
	}
4134 4135 4136
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4137

4138 4139 4140 4141 4142 4143 4144 4145 4146 4147
#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK	(0xf << 8)
#define GGC_MEMORY_SIZE_NONE	(0x0 << 8)
#define GGC_MEMORY_SIZE_1M	(0x1 << 8)
#define GGC_MEMORY_SIZE_2M	(0x3 << 8)
#define GGC_MEMORY_VT_ENABLED	(0x8 << 8)
#define GGC_MEMORY_SIZE_2M_VT	(0x9 << 8)
#define GGC_MEMORY_SIZE_3M_VT	(0xa << 8)
#define GGC_MEMORY_SIZE_4M_VT	(0xb << 8)

4148 4149 4150 4151
static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
{
	unsigned short ggc;

4152
	if (pci_read_config_word(dev, GGC, &ggc))
4153 4154
		return;

4155
	if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
4156 4157
		printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
		dmar_map_gfx = 0;
4158 4159 4160 4161 4162
	} else if (dmar_map_gfx) {
		/* we have to ensure the gfx device is idle before we flush */
		printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
		intel_iommu_strict = 1;
       }
4163 4164 4165 4166 4167 4168
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);

4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225
/* On Tylersburg chipsets, some BIOSes have been known to enable the
   ISOCH DMAR unit for the Azalia sound device, but not give it any
   TLB entries, which causes it to deadlock. Check for that.  We do
   this in a function called from init_dmars(), instead of in a PCI
   quirk, because we don't want to print the obnoxious "BIOS broken"
   message if VT-d is actually disabled.
*/
static void __init check_tylersburg_isoch(void)
{
	struct pci_dev *pdev;
	uint32_t vtisochctrl;

	/* If there's no Azalia in the system anyway, forget it. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
	if (!pdev)
		return;
	pci_dev_put(pdev);

	/* System Management Registers. Might be hidden, in which case
	   we can't do the sanity check. But that's OK, because the
	   known-broken BIOSes _don't_ actually hide it, so far. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
	if (!pdev)
		return;

	if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
		pci_dev_put(pdev);
		return;
	}

	pci_dev_put(pdev);

	/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
	if (vtisochctrl & 1)
		return;

	/* Drop all bits other than the number of TLB entries */
	vtisochctrl &= 0x1c;

	/* If we have the recommended number of TLB entries (16), fine. */
	if (vtisochctrl == 0x10)
		return;

	/* Zero TLB entries? You get to ride the short bus to school. */
	if (!vtisochctrl) {
		WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		iommu_identity_mapping |= IDENTMAP_AZALIA;
		return;
	}
	
	printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
	       vtisochctrl);
}