From 70517048e29867399b5d93a863292b5c51414cc3 Mon Sep 17 00:00:00 2001
From: mackie100 <37126690+mackie100@users.noreply.github.com>
Date: Wed, 15 Dec 2021 19:35:58 +0100
Subject: [PATCH] Updated some descriptions

---
 English Localization (en)/Internal/Localizable.strings | 4 ++--
 French Localization (fr)/Internal/Localizable.strings  | 4 ++--
 Korean Localization (ko)/Internal/Localizable.strings  | 4 ++--
 Polish Localization (pl)/Internal/Localizable.strings  | 4 ++--
 Russian Localization (ru)/Internal/Localizable.strings | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/English Localization (en)/Internal/Localizable.strings b/English Localization (en)/Internal/Localizable.strings
index e42c1800..d354fcf0 100644
--- a/English Localization (en)/Internal/Localizable.strings	
+++ b/English Localization (en)/Internal/Localizable.strings	
@@ -1038,7 +1038,7 @@
 
 /* Emulate */
 /* 7Jq-Yr-TQY */
-"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\nCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\nCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0906EB): \nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00 \nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0906EB):\nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
+"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations. Be warned that one is required to set the correct frequency vectors matching the installed CPU.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\n\tCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\n\tCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\n\tCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0A0655): \n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 \n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0A0655):\n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
 
 /* WQz-t0-GJT */
 "TT_Cpuid1Mask" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Bit mask of active bits in Cpuid1Data. \n\nWhen each Cpuid1Mask bit is set to 0, the original CPU bit is used, otherwise set bits take the value of Cpuid1Data.";
@@ -1113,7 +1113,7 @@
 /* 6Mq-wE-cHt */
 "TT_PowerTimeoutKernelPanic" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.15 (not required for older)\nDescription: Disables kernel panic on setPowerState timeout.\nAn additional security measure was added to macOS Catalina (10.15) causing kernel panic on power change timeout for Apple drivers. Sometimes it may cause issues on misconfigured hardware, notably digital audio, which sometimes fails to wake up. For debug kernels setpowerstate_panic=0 boot argument should be used, which is otherwise equivalent to this quirk.";
 
-"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8\nDescription: Provides current CPU info to the kernel.\n\nThis quirk currently provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation.\n\nNote: These patches currently target Microsoft Hyper-V and may need to be extended for other purposes.";
+"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8 (10.14)\nDescription: Provides current CPU info to the kernel.\n\nThis quirk works differently depending on the CPU:\n• For Microsoft Hyper-V it provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation (10.8+).\n\n• For Intel CPUs it adds support for asymmetrical SMP systems (e.g. Intel Alder Lake) by patching core count to thread count along with the supplemental required changes (10.14+).";
 
 /* yhV-cY-frg */
 "TT_ThirdPartyDrives" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.6 (not required for older)\nDescription: Apply vendor patches to IOAHCIBlockStorage.kext to enable native features for third-party drives, such as TRIM on SSDs or hibernation support on 10.15 and newer.\nNote: This option may be avoided on user preference. NVMe SSDs are compatible without the change. For AHCI SSDs on modern macOS version there is a dedicated built-in utility called trimforce. Starting from 10.15 this utility creates EnableTRIM variable in APPLE_BOOT_VARIABLE_GUID namespace with 01 00 00 00 value.";
diff --git a/French Localization (fr)/Internal/Localizable.strings b/French Localization (fr)/Internal/Localizable.strings
index 8ce789eb..8e48ce88 100644
--- a/French Localization (fr)/Internal/Localizable.strings	
+++ b/French Localization (fr)/Internal/Localizable.strings	
@@ -1038,7 +1038,7 @@
 
 /* Emulate */
 /* 7Jq-Yr-TQY */
-"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\nCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\nCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0906EB): \nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00 \nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0906EB):\nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
+"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations. Be warned that one is required to set the correct frequency vectors matching the installed CPU.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\n\tCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\n\tCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\n\tCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0A0655): \n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 \n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0A0655):\n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
 
 /* WQz-t0-GJT */
 "TT_Cpuid1Mask" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Bit mask of active bits in Cpuid1Data. \n\nWhen each Cpuid1Mask bit is set to 0, the original CPU bit is used, otherwise set bits take the value of Cpuid1Data.";
@@ -1113,7 +1113,7 @@
 /* 6Mq-wE-cHt */
 "TT_PowerTimeoutKernelPanic" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.15 (not required for older)\nDescription: Disables kernel panic on setPowerState timeout.\nAn additional security measure was added to macOS Catalina (10.15) causing kernel panic on power change timeout for Apple drivers. Sometimes it may cause issues on misconfigured hardware, notably digital audio, which sometimes fails to wake up. For debug kernels setpowerstate_panic=0 boot argument should be used, which is otherwise equivalent to this quirk.";
 
-"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8\nDescription: Provides current CPU info to the kernel.\n\nThis quirk currently provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation.\n\nNote: These patches currently target Microsoft Hyper-V and may need to be extended for other purposes.";
+"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8 (10.14)\nDescription: Provides current CPU info to the kernel.\n\nThis quirk works differently depending on the CPU:\n• For Microsoft Hyper-V it provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation (10.8+).\n\n• For Intel CPUs it adds support for asymmetrical SMP systems (e.g. Intel Alder Lake) by patching core count to thread count along with the supplemental required changes (10.14+).";
 
 /* yhV-cY-frg */
 "TT_ThirdPartyDrives" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.6 (not required for older)\nDescription: Apply vendor patches to IOAHCIBlockStorage.kext to enable native features for third-party drives, such as TRIM on SSDs or hibernation support on 10.15 and newer.\nNote: This option may be avoided on user preference. NVMe SSDs are compatible without the change. For AHCI SSDs on modern macOS version there is a dedicated built-in utility called trimforce. Starting from 10.15 this utility creates EnableTRIM variable in APPLE_BOOT_VARIABLE_GUID namespace with 01 00 00 00 value.";
diff --git a/Korean Localization (ko)/Internal/Localizable.strings b/Korean Localization (ko)/Internal/Localizable.strings
index 38115477..6770b2d4 100644
--- a/Korean Localization (ko)/Internal/Localizable.strings	
+++ b/Korean Localization (ko)/Internal/Localizable.strings	
@@ -1038,7 +1038,7 @@
 
 /* Emulate */
 /* 7Jq-Yr-TQY */
-"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\nCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\nCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0906EB): \nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00 \nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0906EB):\nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
+"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations. Be warned that one is required to set the correct frequency vectors matching the installed CPU.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\n\tCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\n\tCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\n\tCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0A0655): \n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 \n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0A0655):\n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
 
 /* WQz-t0-GJT */
 "TT_Cpuid1Mask" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Bit mask of active bits in Cpuid1Data. \n\nWhen each Cpuid1Mask bit is set to 0, the original CPU bit is used, otherwise set bits take the value of Cpuid1Data.";
@@ -1113,7 +1113,7 @@
 /* 6Mq-wE-cHt */
 "TT_PowerTimeoutKernelPanic" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.15 (not required for older)\nDescription: Disables kernel panic on setPowerState timeout.\nAn additional security measure was added to macOS Catalina (10.15) causing kernel panic on power change timeout for Apple drivers. Sometimes it may cause issues on misconfigured hardware, notably digital audio, which sometimes fails to wake up. For debug kernels setpowerstate_panic=0 boot argument should be used, which is otherwise equivalent to this quirk.";
 
-"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8\nDescription: Provides current CPU info to the kernel.\n\nThis quirk currently provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation.\n\nNote: These patches currently target Microsoft Hyper-V and may need to be extended for other purposes.";
+"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8 (10.14)\nDescription: Provides current CPU info to the kernel.\n\nThis quirk works differently depending on the CPU:\n• For Microsoft Hyper-V it provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation (10.8+).\n\n• For Intel CPUs it adds support for asymmetrical SMP systems (e.g. Intel Alder Lake) by patching core count to thread count along with the supplemental required changes (10.14+).";
 
 /* yhV-cY-frg */
 "TT_ThirdPartyDrives" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.6 (not required for older)\nDescription: Apply vendor patches to IOAHCIBlockStorage.kext to enable native features for third-party drives, such as TRIM on SSDs or hibernation support on 10.15 and newer.\nNote: This option may be avoided on user preference. NVMe SSDs are compatible without the change. For AHCI SSDs on modern macOS version there is a dedicated built-in utility called trimforce. Starting from 10.15 this utility creates EnableTRIM variable in APPLE_BOOT_VARIABLE_GUID namespace with 01 00 00 00 value.";
diff --git a/Polish Localization (pl)/Internal/Localizable.strings b/Polish Localization (pl)/Internal/Localizable.strings
index 6b97aa2d..8346d990 100644
--- a/Polish Localization (pl)/Internal/Localizable.strings	
+++ b/Polish Localization (pl)/Internal/Localizable.strings	
@@ -1038,7 +1038,7 @@
 
 /* Emulate */
 /* 7Jq-Yr-TQY */
-"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\nCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\nCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0906EB): \nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00 \nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0906EB):\nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
+"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations. Be warned that one is required to set the correct frequency vectors matching the installed CPU.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\n\tCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\n\tCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\n\tCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0A0655): \n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 \n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0A0655):\n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
 
 /* WQz-t0-GJT */
 "TT_Cpuid1Mask" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Bit mask of active bits in Cpuid1Data. \n\nWhen each Cpuid1Mask bit is set to 0, the original CPU bit is used, otherwise set bits take the value of Cpuid1Data.";
@@ -1113,7 +1113,7 @@
 /* 6Mq-wE-cHt */
 "TT_PowerTimeoutKernelPanic" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.15 (not required for older)\nDescription: Disables kernel panic on setPowerState timeout.\nAn additional security measure was added to macOS Catalina (10.15) causing kernel panic on power change timeout for Apple drivers. Sometimes it may cause issues on misconfigured hardware, notably digital audio, which sometimes fails to wake up. For debug kernels setpowerstate_panic=0 boot argument should be used, which is otherwise equivalent to this quirk.";
 
-"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8\nDescription: Provides current CPU info to the kernel.\n\nThis quirk currently provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation.\n\nNote: These patches currently target Microsoft Hyper-V and may need to be extended for other purposes.";
+"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8 (10.14)\nDescription: Provides current CPU info to the kernel.\n\nThis quirk works differently depending on the CPU:\n• For Microsoft Hyper-V it provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation (10.8+).\n\n• For Intel CPUs it adds support for asymmetrical SMP systems (e.g. Intel Alder Lake) by patching core count to thread count along with the supplemental required changes (10.14+).";
 
 /* yhV-cY-frg */
 "TT_ThirdPartyDrives" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.6 (not required for older)\nDescription: Apply vendor patches to IOAHCIBlockStorage.kext to enable native features for third-party drives, such as TRIM on SSDs or hibernation support on 10.15 and newer.\nNote: This option may be avoided on user preference. NVMe SSDs are compatible without the change. For AHCI SSDs on modern macOS version there is a dedicated built-in utility called trimforce. Starting from 10.15 this utility creates EnableTRIM variable in APPLE_BOOT_VARIABLE_GUID namespace with 01 00 00 00 value.";
diff --git a/Russian Localization (ru)/Internal/Localizable.strings b/Russian Localization (ru)/Internal/Localizable.strings
index 1a7fe2fc..d6ee876e 100644
--- a/Russian Localization (ru)/Internal/Localizable.strings	
+++ b/Russian Localization (ru)/Internal/Localizable.strings	
@@ -1038,7 +1038,7 @@
 
 /* Emulate */
 /* 7Jq-Yr-TQY */
-"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\nCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\nCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0906EB): \nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00 \nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\nCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0906EB):\nCpuid1Data: EB 06 09 00 00 00 00 00 00 00 00 00 00 00 00 00\nCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
+"TT_Cpuid1Data" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Sequence of EAX, EBX, ECX, EDX values to replace CPUID (1) call in XNU kernel.\n\nThis property primarily meets three requirements:\n• Enabling support for an unsupported CPU model . (e.g. Intel Pentium).\n• Enabling support for a CPU model that is not yet supported by a specific version of macOS (typically old versions).\n• Enabling XCPM support for an unsupported CPU variant.\n\nNote 1: It may also be the case that the CPU model is supported but there is no power management supported (e.g. virtual machines). In this case, MinKernel and MaxKernel can be set to restrict CPU virtualisation and dummy power management patches to the particular macOS kernel version.\n\nNote 2: Only the value of EAX, which represents the exact CPUID, typically needs to be accounted for and remaining bytes should left as zeroes. The byte order is Little Endian. For example, C3 06 03 00 stands for CPUID 0x0306C3 (Haswell).\n\nNote 3: For XCPM support it is recommended to use the following combinations. Be warned that one is required to set the correct frequency vectors matching the installed CPU.\n• Haswell-E (0x0306F2) to Haswell (0x0306C3):\n\tCpuid1Data: C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Broadwell-E (0x0406F1) to Broadwell (0x0306D4):\n\tCpuid1Data: D4 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Comet Lake U62 (0x0A0660) to Comet Lake U42 (0x0806EC):\n\tCpuid1Data: EC 06 08 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Rocket Lake (0x0A0670) to Comet Lake (0x0A0655): \n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 \n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n• Alder Lake (0x090672) to Comet Lake (0x0A0655):\n\tCpuid1Data: 55 06 0A 00 00 00 00 00 00 00 00 00 00 00 00 00\n\tCpuid1Mask: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00\n\nNote 4: Note that the following configurations are unsupported by XCPM (at least out of the box):\n• Consumer Ivy Bridge (0x0306A9) as Apple disabled XCPM for Ivy Bridge and recommends legacy power management for these CPUs. You will need to manually patch _xcpm_bootstrap to force should manually be patched to enforce XCPM on these CPUs instead of using this option.\n• Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.";
 
 /* WQz-t0-GJT */
 "TT_Cpuid1Mask" = "Type: plist data, 16 bytes\nFailsafe: All zero\nDescription: Bit mask of active bits in Cpuid1Data. \n\nWhen each Cpuid1Mask bit is set to 0, the original CPU bit is used, otherwise set bits take the value of Cpuid1Data.";
@@ -1113,7 +1113,7 @@
 /* 6Mq-wE-cHt */
 "TT_PowerTimeoutKernelPanic" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.15 (not required for older)\nDescription: Disables kernel panic on setPowerState timeout.\nAn additional security measure was added to macOS Catalina (10.15) causing kernel panic on power change timeout for Apple drivers. Sometimes it may cause issues on misconfigured hardware, notably digital audio, which sometimes fails to wake up. For debug kernels setpowerstate_panic=0 boot argument should be used, which is otherwise equivalent to this quirk.";
 
-"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8\nDescription: Provides current CPU info to the kernel.\n\nThis quirk currently provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation.\n\nNote: These patches currently target Microsoft Hyper-V and may need to be extended for other purposes.";
+"TT_ProvideCurrentCpuInfo" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.8 (10.14)\nDescription: Provides current CPU info to the kernel.\n\nThis quirk works differently depending on the CPU:\n• For Microsoft Hyper-V it provides the correct TSC and FSB values to the kernel, as well as disables CPU topology validation (10.8+).\n\n• For Intel CPUs it adds support for asymmetrical SMP systems (e.g. Intel Alder Lake) by patching core count to thread count along with the supplemental required changes (10.14+).";
 
 /* yhV-cY-frg */
 "TT_ThirdPartyDrives" = "Type: plist boolean\nFailsafe: false\nRequirement: 10.6 (not required for older)\nDescription: Apply vendor patches to IOAHCIBlockStorage.kext to enable native features for third-party drives, such as TRIM on SSDs or hibernation support on 10.15 and newer.\nNote: This option may be avoided on user preference. NVMe SSDs are compatible without the change. For AHCI SSDs on modern macOS version there is a dedicated built-in utility called trimforce. Starting from 10.15 this utility creates EnableTRIM variable in APPLE_BOOT_VARIABLE_GUID namespace with 01 00 00 00 value.";
-- 
GitLab