diff --git a/.travis.yml b/.travis.yml
index 085b1c351d80f69cb6757e36a994ecc86557f469..b26d4c8fc529d6db7e9c957d3879d2e3e5f63667 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -22,6 +22,7 @@ script:
env:
- RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
- RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm'
+ - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
# - RTT_BSP='bf533' # no scons
diff --git a/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/ASM9260T.ddf b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/ASM9260T.ddf
new file mode 100644
index 0000000000000000000000000000000000000000..0745f83db54e0327715c1146671fae2599ef102a
--- /dev/null
+++ b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/ASM9260T.ddf
@@ -0,0 +1,44 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;; Name may be almost anything
+;; AdrSpace must be Memory
+;; StartAdr start of memory block
+;; EndAdr end of memory block
+;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;; Name AdrSpace StartAdr EndAdr AccType Width
+;Memory = SYSC0 Memory 0xFFFFE800 0xFFFFF9FF W
+;Memory = SYSC1 Memory 0xFFFFFC00 0xFFFFFD7F W
+;Memory = ROM Memory 0x00100000 0x00107FFF R
+;Memory = BootMem Memory 0x00000000 0x000FFFFF R
+;Memory = RAM0 Memory 0x00200000 0x00200FFF RW
+;Memory = Periph Memory 0xFFFA0000 0xFFFE3FFF W
+;Memory = USBH Memory 0x00500000 0x00503FFF W
+;Memory = RAM1 Memory 0x00300000 0x00300FFF RW
+;Memory = ExtDev Memory 0x10000000 0x8FFFFFFF RW
+
+Memory = EMI_MEM Memory 0x00000000 0x3FFFFFFF RW
+Memory = RAM Memory 0x40000000 0x40001FFF RW
+Memory = AHB Memory 0x50000000 0x501FFFFF W
+Memory = APB Memory 0x80000000 0x800BFFFF W
+Memory = DMA0 Memory 0x80100000 0x8010FFFF W
+Memory = DMA1 Memory 0x80200000 0x8020FFFF W
+Memory = USB0 Memory 0x80300000 0x8030FFFF W
+Memory = USB1 Memory 0x80400000 0x8040FFFF W
+Memory = MAC Memory 0x80500000 0x8050FFFF W
+Memory = NAND Memory 0x80600000 0x8060FFFF W
+Memory = EMI_REG Memory 0x80700000 0x8070FFFF W
+Memory = LCD Memory 0x80800000 0x8080FFFF W
+Memory = SPI_FLASH Memory 0xF0000000 0xF7FFFFFF RW
+Memory = ROM Memory 0xFFFF0000 0xFFFFFFFF R
+
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ioASM9260T.ddf
diff --git a/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/ioASM9260T.ddf b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/ioASM9260T.ddf
new file mode 100644
index 0000000000000000000000000000000000000000..0d09ae140b06f6af5c0dea0ffb1450473aa30f8d
--- /dev/null
+++ b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/ioASM9260T.ddf
@@ -0,0 +1,272 @@
+; ----------------------------------------------------------------------------
+; Arda Technologies CO. Ltd. 2007-2015
+; ----------------------------------------------------------------------------
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ARDA "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL ARDA BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ----------------------------------------------------------------------------
+; File Name : ASM9260T.ddf
+; Object : ASM9260T definitions
+; Generated : Arda SW Application Group 29/04/2015
+;
+; ----------------------------------------------------------------------------
+
+[Sfr]
+
+; ========== Register definition for SYS peripheral ==========
+sfr = "PRESETCTRL0", "Memory", 0x80040000, 4, base=16
+sfr = "PRESETCTRL1", "Memory", 0x80040010, 4, base=16
+sfr = "AHBCLKCTRL0", "Memory", 0x80040020, 4, base=16
+sfr = "AHBCLKCTRL0.GPIO", "Memory", 0x80040020, 4, base=16, bitRange=4
+sfr = "AHBCLKCTRL0.IOCONFIG", "Memory", 0x80040020, 4, base=16, bitRange=25
+sfr = "AHBCLKCTRL1", "Memory", 0x80040030, 4, base=16
+sfr = "AHBCLKCTRL1.TIMER0", "Memory", 0x80040030, 4, base=16, bitRange=4
+sfr = "AHBCLKCTRL1.IRQ", "Memory", 0x80040030, 4, base=16, bitRange=8
+sfr = "SYSPLLCTRL", "Memory", 0x80040100, 4, base=16
+sfr = "SYSRSTSTAT", "Memory", 0x80040110, 4, base=16
+sfr = "MAINCLKSEL", "Memory", 0x80040120, 4, base=16
+sfr = "MAINCLKUEN", "Memory", 0x80040124, 4, base=16
+sfr = "UARTCLKSEL", "Memory", 0x80040128, 4, base=16
+sfr = "UARTCLKUEN", "Memory", 0x8004012C, 4, base=16
+sfr = "CPUCLKDIV", "Memory", 0x8004017C, 4, base=16
+sfr = "SYSAHBCLKDIV", "Memory", 0x80040180, 4, base=16
+sfr = "UART0CLKDIV", "Memory", 0x80040198, 4, base=16
+sfr = "UART1CLKDIV", "Memory", 0x8004019C, 4, base=16
+sfr = "UART2CLKDIV", "Memory", 0x800401A0, 4, base=16
+sfr = "UART3CLKDIV", "Memory", 0x800401A4, 4, base=16
+sfr = "UART4CLKDIV", "Memory", 0x800401A8, 4, base=16
+sfr = "UART5CLKDIV", "Memory", 0x800401AC, 4, base=16
+sfr = "UART6CLKDIV", "Memory", 0x800401B0, 4, base=16
+sfr = "UART7CLKDIV", "Memory", 0x800401B4, 4, base=16
+sfr = "UART8CLKDIV", "Memory", 0x800401B8, 4, base=16
+sfr = "UART9CLKDIV", "Memory", 0x800401BC, 4, base=16
+sfr = "DEVICEID", "Memory", 0x80040400, 4, base=16
+sfr = "PCON", "Memory", 0x80040500, 4, base=16
+;-----------------ICOLL---------------------------------------------------------
+sfr = "HW_ICOLL_VECTOR", "Memory", 0x80054000, 4, base=16
+sfr = "HW_ICOLL_LEVELACK", "Memory", 0x80054010, 4, base=16
+sfr = "HW_ICOLL_CTRL", "Memory", 0x80054020, 4, base=16
+sfr = "HW_ICOLL_CTRL.BYPASS_FSM", "Memory", 0x80054020, 4, base=16, bitRange=20
+sfr = "HW_ICOLL_CTRL.NO_NESTING", "Memory", 0x80054020, 4, base=16, bitRange=19
+sfr = "HW_ICOLL_CTRL.RSE_MODE", "Memory", 0x80054020, 4, base=16, bitRange=18
+sfr = "HW_ICOLL_CTRL.IRQ_FINAL_ENABLE", "Memory", 0x80054020, 4, base=16, bitRange=16
+sfr = "HW_ICOLL_STAT", "Memory", 0x80054030, 4, base=16
+sfr = "HW_ICOLL_STAT.vector_number", "Memory", 0x80054030, 4, base=16, bitRange=0-5
+sfr = "HW_ICOLL_RAW0", "Memory", 0x80054040, 4, base=16
+sfr = "HW_ICOLL_RAW0.UART3_IRQ", "Memory", 0x80054040, 4, base=16, bitRange=18
+sfr = "HW_ICOLL_RAW0.TIMER0_IRQ", "Memory", 0x80054040, 4, base=16, bitRange=29
+sfr = "HW_ICOLL_RAW1", "Memory", 0x80054050, 4, base=16
+sfr = "HW_ICOLL_PRIORITY0", "Memory", 0x80054060, 4, base=16
+sfr = "HW_ICOLL_PRIORITY1", "Memory", 0x80054070, 4, base=16
+sfr = "HW_ICOLL_PRIORITY2", "Memory", 0x80054080, 4, base=16
+sfr = "HW_ICOLL_PRIORITY3", "Memory", 0x80054090, 4, base=16
+sfr = "HW_ICOLL_PRIORITY4", "Memory", 0x800540A0, 4, base=16
+sfr = "HW_ICOLL_PRIORITY5", "Memory", 0x800540B0, 4, base=16
+sfr = "HW_ICOLL_PRIORITY6", "Memory", 0x800540C0, 4, base=16
+sfr = "HW_ICOLL_PRIORITY7", "Memory", 0x800540D0, 4, base=16
+sfr = "HW_ICOLL_PRIORITY8", "Memory", 0x800540E0, 4, base=16
+sfr = "HW_ICOLL_PRIORITY9", "Memory", 0x800540F0, 4, base=16
+sfr = "HW_ICOLL_PRIORITY10", "Memory", 0x80054100, 4, base=16
+sfr = "HW_ICOLL_PRIORITY11", "Memory", 0x80054110, 4, base=16
+sfr = "HW_ICOLL_PRIORITY12", "Memory", 0x80054120, 4, base=16
+sfr = "HW_ICOLL_PRIORITY13", "Memory", 0x80054130, 4, base=16
+sfr = "HW_ICOLL_PRIORITY14", "Memory", 0x80054140, 4, base=16
+sfr = "HW_ICOLL_PRIORITY15", "Memory", 0x80054150, 4, base=16
+sfr = "HW_ICOLL_VBASE", "Memory", 0x80054160, 4, base=16
+sfr = "HW_ICOLL_DEBUG", "Memory", 0x80054170, 4, base=16
+sfr = "HW_ICOLL_DBGREAD0", "Memory", 0x80054180, 4, base=16
+sfr = "HW_ICOLL_DBGREAD1", "Memory", 0x80054190, 4, base=16
+sfr = "HW_ICOLL_DBGFLAG", "Memory", 0x800541A0, 4, base=16
+sfr = "HW_ICOLL_DBGREQUEST0", "Memory", 0x800541B0, 4, base=16
+sfr = "HW_ICOLL_DBGREQUEST1", "Memory", 0x800541C0, 4, base=16
+sfr = "HW_ICOLL_CLEAR0", "Memory", 0x800541D0, 4, base=16
+sfr = "HW_ICOLL_CLEAR0.UART3_IRQ", "Memory", 0x800541D0, 4, base=16, bitRange=18
+sfr = "HW_ICOLL_CLEAR0.TIMER0_IRQ", "Memory", 0x800541D0, 4, base=16, bitRange=29
+sfr = "HW_ICOLL_CLEAR1", "Memory", 0x800541E0, 4, base=16
+sfr = "HW_ICOLL_UNDEF_VECTOR", "Memory", 0x800541F0, 4, base=16
+
+;---------------------TIMER0----------------------------------------------
+sfr = "HW_TIMER0_IR", "Memory", 0x80088000, 4, base=16
+sfr = "HW_TIMER0_IR.MR0_INT", "Memory", 0x80088000, 4, base=16, bitRange=0
+sfr = "HW_TIMER0_IR.MR1_INT", "Memory", 0x80088000, 4, base=16, bitRange=1
+sfr = "HW_TIMER0_IR.MR2_INT", "Memory", 0x80088000, 4, base=16, bitRange=2
+sfr = "HW_TIMER0_IR.MR3_INT", "Memory", 0x80088000, 4, base=16, bitRange=3
+sfr = "HW_TIMER0_IR.CR0_INT", "Memory", 0x80088000, 4, base=16, bitRange=4
+sfr = "HW_TIMER0_TCR", "Memory", 0x80088010, 4, base=16
+sfr = "HW_TIMER0_TCR.CEN0", "Memory", 0x80088010, 4, base=16, bitRange=0
+sfr = "HW_TIMER0_TCR.CEN1", "Memory", 0x80088010, 4, base=16, bitRange=1
+sfr = "HW_TIMER0_TCR.CEN2", "Memory", 0x80088010, 4, base=16, bitRange=2
+sfr = "HW_TIMER0_TCR.CEN3", "Memory", 0x80088010, 4, base=16, bitRange=3
+sfr = "HW_TIMER0_TCR.CRST0", "Memory", 0x80088010, 4, base=16, bitRange=4
+sfr = "HW_TIMER0_TCR.CRST1", "Memory", 0x80088010, 4, base=16, bitRange=5
+sfr = "HW_TIMER0_TCR.CRST2", "Memory", 0x80088010, 4, base=16, bitRange=6
+sfr = "HW_TIMER0_TCR.CRST3", "Memory", 0x80088010, 4, base=16, bitRange=7
+sfr = "HW_TIMER0_DIR", "Memory", 0x80088020, 4, base=16
+sfr = "HW_TIMER0_DIR.DIR0", "Memory", 0x80088020, 4, base=16, bitRange=0-1
+sfr = "HW_TIMER0_DIR.DIR1", "Memory", 0x80088020, 4, base=16, bitRange=4-5
+sfr = "HW_TIMER0_DIR.DIR2", "Memory", 0x80088020, 4, base=16, bitRange=8-9
+sfr = "HW_TIMER0_DIR.DIR3", "Memory", 0x80088020, 4, base=16, bitRange=12-13
+sfr = "HW_TIMER0_TC0", "Memory", 0x80088030, 4, base=16
+sfr = "HW_TIMER0_TC1", "Memory", 0x80088040, 4, base=16
+sfr = "HW_TIMER0_TC2", "Memory", 0x80088050, 4, base=16
+sfr = "HW_TIMER0_TC3", "Memory", 0x80088060, 4, base=16
+sfr = "HW_TIMER0_PR", "Memory", 0x80088070, 4, base=16
+sfr = "HW_TIMER0_PC", "Memory", 0x80088080, 4, base=16
+sfr = "HW_TIMER0_MCR", "Memory", 0x80088090, 4, base=16
+sfr = "HW_TIMER0_MCR.MR0INT", "Memory", 0x80088090, 4, base=16, bitRange=0
+sfr = "HW_TIMER0_MCR.MR0RST", "Memory", 0x80088090, 4, base=16, bitRange=1
+sfr = "HW_TIMER0_MCR.MR0STOP", "Memory", 0x80088090, 4, base=16, bitRange=2
+sfr = "HW_TIMER0_MCR.MR1INT", "Memory", 0x80088090, 4, base=16, bitRange=3
+sfr = "HW_TIMER0_MCR.MR1RST", "Memory", 0x80088090, 4, base=16, bitRange=4
+sfr = "HW_TIMER0_MCR.MR1STOP", "Memory", 0x80088090, 4, base=16, bitRange=5
+sfr = "HW_TIMER0_MCR.MR2INT", "Memory", 0x80088090, 4, base=16, bitRange=6
+sfr = "HW_TIMER0_MCR.MR2RST", "Memory", 0x80088090, 4, base=16, bitRange=7
+sfr = "HW_TIMER0_MCR.MR2STOP", "Memory", 0x80088090, 4, base=16, bitRange=8
+sfr = "HW_TIMER0_MCR.MR3INT", "Memory", 0x80088090, 4, base=16, bitRange=9
+sfr = "HW_TIMER0_MCR.MR3RST", "Memory", 0x80088090, 4, base=16, bitRange=10
+sfr = "HW_TIMER0_MCR.MR3STOP", "Memory", 0x80088090, 4, base=16, bitRange=11
+sfr = "HW_TIMER0_MR0", "Memory", 0x800880a0, 4, base=16
+sfr = "HW_TIMER0_MR1", "Memory", 0x800880b0, 4, base=16
+sfr = "HW_TIMER0_MR2", "Memory", 0x800880C0, 4, base=16
+sfr = "HW_TIMER0_MR3", "Memory", 0x800880D0, 4, base=16
+sfr = "HW_TIMER0_CCR", "Memory", 0x800880E0, 4, base=16
+sfr = "HW_TIMER0_CCR.CAP0RE", "Memory", 0x800880E0, 4, base=16, bitRange=0
+sfr = "HW_TIMER0_CCR.CAP0FE", "Memory", 0x800880E0, 4, base=16, bitRange=1
+sfr = "HW_TIMER0_CCR.CAP0I", "Memory", 0x800880E0, 4, base=16, bitRange=2
+sfr = "HW_TIMER0_CR0", "Memory", 0x800880F0, 4, base=16
+sfr = "HW_TIMER0_CR1", "Memory", 0x80088100, 4, base=16
+sfr = "HW_TIMER0_CR2", "Memory", 0x80088110, 4, base=16
+sfr = "HW_TIMER0_CR3", "Memory", 0x80088120, 4, base=16
+sfr = "HW_TIMER0_EMR", "Memory", 0x80088130, 4, base=16
+sfr = "HW_TIMER0_PWMTH0", "Memory", 0x80088140, 4, base=16
+sfr = "HW_TIMER0_PWMTH1", "Memory", 0x80088150, 4, base=16
+sfr = "HW_TIMER0_PWMTH2", "Memory", 0x80088160, 4, base=16
+sfr = "HW_TIMER0_PWMTH3", "Memory", 0x80088170, 4, base=16
+sfr = "HW_TIMER0_CTCR", "Memory", 0x80088180, 4, base=16
+sfr = "HW_TIMER0_PWMC", "Memory", 0x80088190, 4, base=16
+
+;---------------------UART3-------------------------------------------------------
+sfr = "HW_USART3_CTRL0", "Memory", 0x8000C000, 4, base=16
+sfr = "HW_USART3_CTRL0.XFER_COUNT", "Memory", 0x8000C000, 4, base=16, bitRange=0-15
+sfr = "HW_USART3_CTRL0.RXTIMEOUT", "Memory", 0x8000C000, 4, base=16, bitRange=16-23
+sfr = "HW_USART3_CTRL0.RXTO_ENABLE", "Memory", 0x8000C000, 4, base=16, bitRange=24
+sfr = "HW_USART3_CTRL0.RX_SOURCE", "Memory", 0x8000C000, 4, base=16, bitRange=25
+sfr = "HW_USART3_CTRL0.RUN", "Memory", 0x8000C000, 4, base=16, bitRange=28
+sfr = "HW_USART3_CTRL0.CLKGATE", "Memory", 0x8000C000, 4, base=16, bitRange=30
+sfr = "HW_USART3_CTRL0.SOFTRST", "Memory", 0x8000C000, 4, base=16, bitRange=31
+sfr = "HW_USART3_CTRL1", "Memory", 0x8000C010, 4, base=16
+sfr = "HW_USART3_CTRL1.XFER_COUNT", "Memory", 0x8000C010, 4, base=16, bitRange=0-15
+sfr = "HW_USART3_CTRL1.RUN", "Memory", 0x8000C010, 4, base=16, bitRange=28
+sfr = "HW_USART3_CTRL2", "Memory", 0x8000C020, 4, base=16
+sfr = "HW_USART3_CTRL2.USARTEN", "Memory", 0x8000C020, 4, base=16, bitRange=0
+sfr = "HW_USART3_CTRL2.SIREN", "Memory", 0x8000C020, 4, base=16, bitRange=1
+sfr = "HW_USART3_CTRL2.SIRLP", "Memory", 0x8000C020, 4, base=16, bitRange=2
+sfr = "HW_USART3_CTRL2.LBE", "Memory", 0x8000C020, 4, base=16, bitRange=7
+sfr = "HW_USART3_CTRL2.TXE", "Memory", 0x8000C020, 4, base=16, bitRange=8
+sfr = "HW_USART3_CTRL2.RXE", "Memory", 0x8000C020, 4, base=16, bitRange=9
+sfr = "HW_USART3_CTRL2.DTR", "Memory", 0x8000C020, 4, base=16, bitRange=10
+sfr = "HW_USART3_CTRL2.RTS", "Memory", 0x8000C020, 4, base=16, bitRange=11
+sfr = "HW_USART3_CTRL2.OUT1", "Memory", 0x8000C020, 4, base=16, bitRange=12
+sfr = "HW_USART3_CTRL2.OUT2", "Memory", 0x8000C020, 4, base=16, bitRange=13
+sfr = "HW_USART3_CTRL2.RTSEM", "Memory", 0x8000C020, 4, base=16, bitRange=14
+sfr = "HW_USART3_CTRL2.CTSEN", "Memory", 0x8000C020, 4, base=16, bitRange=15
+sfr = "HW_USART3_CTRL2.TXIFLSEL", "Memory", 0x8000C020, 4, base=16, bitRange=16-18
+sfr = "HW_USART3_CTRL2.RXIFLSEL", "Memory", 0x8000C020, 4, base=16, bitRange=20-22
+sfr = "HW_USART3_CTRL2.RXDMAE", "Memory", 0x8000C020, 4, base=16, bitRange=24
+sfr = "HW_USART3_CTRL2.TXDMAE", "Memory", 0x8000C020, 4, base=16, bitRange=25
+sfr = "HW_USART3_CTRL2.DMAONERROR", "Memory", 0x8000C020, 4, base=16, bitRange=26
+
+sfr = "HW_USART3_LINECTRL", "Memory", 0x8000C030, 4, base=16
+sfr = "HW_USART3_LINECTRL.BRK", "Memory", 0x8000C030, 4, base=16, bitRange=0
+sfr = "HW_USART3_LINECTRL.PEN", "Memory", 0x8000C030, 4, base=16, bitRange=1
+sfr = "HW_USART3_LINECTRL.EPS", "Memory", 0x8000C030, 4, base=16, bitRange=2
+sfr = "HW_USART3_LINECTRL.STP2", "Memory", 0x8000C030, 4, base=16, bitRange=3
+sfr = "HW_USART3_LINECTRL.FEN", "Memory", 0x8000C030, 4, base=16, bitRange=4
+sfr = "HW_USART3_LINECTRL.WLEN", "Memory", 0x8000C030, 4, base=16, bitRange=5:6
+sfr = "HW_USART3_LINECTRL.SPS", "Memory", 0x8000C030, 4, base=16, bitRange=7
+sfr = "HW_USART3_LINECTRL.BAUD_DIVFRA", "Memory", 0x8000C030, 4, base=16, bitRange=8-13
+sfr = "HW_USART3_LINECTRL.BAUD_DIVINT", "Memory", 0x8000C030, 4, base=16, bitRange=16-31
+sfr = "HW_USART3_INTR", "Memory", 0x8000C040, 4, base=16
+sfr = "HW_USART3_INTR.RXIS", "Memory", 0x8000C040, 4, base=16, bitRange=4
+sfr = "HW_USART3_INTR.TXIS", "Memory", 0x8000C040, 4, base=16, bitRange=5
+sfr = "HW_USART3_INTR.RTIS", "Memory", 0x8000C040, 4, base=16, bitRange=6
+sfr = "HW_USART3_INTR.RXIEN", "Memory", 0x8000C040, 4, base=16, bitRange=20
+sfr = "HW_USART3_INTR.TXIEN", "Memory", 0x8000C040, 4, base=16, bitRange=21
+sfr = "HW_USART3_INTR.RTIEN", "Memory", 0x8000C040, 4, base=16, bitRange=22
+sfr = "HW_USART3_DATA", "Memory", 0x8000C050, 4, base=16
+sfr = "HW_USART3_STAT", "Memory", 0x8000C060, 4, base=16
+sfr = "HW_USART3_STAT.RXOUNT", "Memory", 0x8000C060, 4, base=16, bitRange=0-15
+sfr = "HW_USART3_STAT.OEER", "Memory", 0x8000C060, 4, base=16, bitRange=19
+sfr = "HW_USART3_STAT.RXBYTE_INVOID", "Memory", 0x8000C060, 4, base=16, bitRange=20-23
+sfr = "HW_USART3_STAT.RXFE", "Memory", 0x8000C060, 4, base=16, bitRange=24
+sfr = "HW_USART3_STAT.TXFF", "Memory", 0x8000C060, 4, base=16, bitRange=25
+sfr = "HW_USART3_STAT.RXFF", "Memory", 0x8000C060, 4, base=16, bitRange=26
+sfr = "HW_USART3_STAT.TXFE", "Memory", 0x8000C060, 4, base=16, bitRange=27
+sfr = "HW_USART3_STAT.BUSY", "Memory", 0x8000C060, 4, base=16, bitRange=29
+sfr = "HW_USART3_STAT.HISPEED", "Memory", 0x8000C060, 4, base=16, bitRange=30
+sfr = "HW_USART3_STAT.PRESENT", "Memory", 0x8000C060, 4, base=16, bitRange=31
+sfr = "HW_USART3_DEBUG", "Memory", 0x8000C070, 4, base=16
+sfr = "HW_USART3_ILPR", "Memory", 0x8000C080, 4, base=16
+sfr = "HW_USART3_RS485CTRL", "Memory", 0x8000C090, 4, base=16
+sfr = "HW_USART3_RS485ADRMATCH", "Memory", 0x8000C0A0, 4, base=16
+sfr = "HW_USART3_RS485DLY", "Memory", 0x8000C0B0, 4, base=16
+sfr = "HW_USART3_AUTOBAUD", "Memory", 0x8000C0C0, 4, base=16
+sfr = "HW_USART3_CTRL3", "Memory", 0x8000C0D0, 4, base=16
+sfr = "HW_USART3_ISO7816CTRL", "Memory", 0x8000C0E0, 4, base=16
+sfr = "HW_USART3_ISO7816ERRCNT", "Memory", 0x8000C0F0, 4, base=16
+sfr = "HW_USART3_ISO7816STAT", "Memory", 0x8000C100, 4, base=16
+;----------------------GPIO--------------------------------------------------------------------
+sfr = "HW_GPIO_DATA0", "Memory", 0x50000000, 4, base=16
+sfr = "HW_GPIO_DATA1", "Memory", 0x50010000, 4, base=16
+sfr = "HW_GPIO_DATA2", "Memory", 0x50020000, 4, base=16
+sfr = "HW_GPIO_DATA3", "Memory", 0x50030000, 4, base=16
+sfr = "HW_GPIO_DIR0", "Memory", 0x50008000, 4, base=16
+sfr = "HW_GPIO_DIR1", "Memory", 0x50018000, 4, base=16
+sfr = "HW_GPIO_DIR2", "Memory", 0x50028000, 4, base=16
+sfr = "HW_GPIO_DIR3", "Memory", 0x50038000, 4, base=16
+sfr = "HW_GPIO_IS0", "Memory", 0x50008010, 4, base=16
+sfr = "HW_GPIO_IS1", "Memory", 0x50018010, 4, base=16
+sfr = "HW_GPIO_IS2", "Memory", 0x50028010, 4, base=16
+sfr = "HW_GPIO_IS3", "Memory", 0x50038010, 4, base=16
+sfr = "HW_GPIO_IBE0", "Memory", 0x50008020, 4, base=16
+sfr = "HW_GPIO_IBE1", "Memory", 0x50018020, 4, base=16
+sfr = "HW_GPIO_IBE2", "Memory", 0x50028020, 4, base=16
+sfr = "HW_GPIO_IBE3", "Memory", 0x50038020, 4, base=16
+sfr = "HW_GPIO_IEV0", "Memory", 0x50008030, 4, base=16
+sfr = "HW_GPIO_IEV1", "Memory", 0x50018030, 4, base=16
+sfr = "HW_GPIO_IEV2", "Memory", 0x50028030, 4, base=16
+sfr = "HW_GPIO_IEV3", "Memory", 0x50038030, 4, base=16
+sfr = "HW_GPIO_IE0", "Memory", 0x50008040, 4, base=16
+sfr = "HW_GPIO_IE1", "Memory", 0x50018040, 4, base=16
+sfr = "HW_GPIO_IE2", "Memory", 0x50028040, 4, base=16
+sfr = "HW_GPIO_IE3", "Memory", 0x50038040, 4, base=16
+sfr = "HW_GPIO_IRS0", "Memory", 0x50008050, 4, base=16
+sfr = "HW_GPIO_IRS1", "Memory", 0x50018050, 4, base=16
+sfr = "HW_GPIO_IRS2", "Memory", 0x50028050, 4, base=16
+sfr = "HW_GPIO_IRS3", "Memory", 0x50038050, 4, base=16
+sfr = "HW_GPIO_MIS0", "Memory", 0x50008060, 4, base=16
+sfr = "HW_GPIO_MIS1", "Memory", 0x50018060, 4, base=16
+sfr = "HW_GPIO_MIS2", "Memory", 0x50028060, 4, base=16
+sfr = "HW_GPIO_MIS3", "Memory", 0x50038060, 4, base=16
+sfr = "HW_GPIO_IC0", "Memory", 0x50008070, 4, base=16
+sfr = "HW_GPIO_IC1", "Memory", 0x50018070, 4, base=16
+sfr = "HW_GPIO_IC2", "Memory", 0x50028070, 4, base=16
+sfr = "HW_GPIO_IC3", "Memory", 0x50038070, 4, base=16
+sfr = "HW_GPIO_DATAMASK0", "Memory", 0x50008080, 4, base=16
+sfr = "HW_GPIO_DATAMASK1", "Memory", 0x50018080, 4, base=16
+sfr = "HW_GPIO_DATAMASK2", "Memory", 0x50028080, 4, base=16
+sfr = "HW_GPIO_DATAMASK3", "Memory", 0x50038080, 4, base=16
+
+[SfrGroupInfo]
+group = "SYS", "PRESETCTRL0", "PRESETCTRL1", "AHBCLKCTRL0", "AHBCLKCTRL1", "SYSPLLCTRL", "SYSRSTSTAT", "MAINCLKSEL","MAINCLKUEN", "UARTCLKSEL", "UARTCLKUEN", "CPUCLKDIV", "SYSAHBCLKDIV", "UART0CLKDIV", "UART1CLKDIV", "UART2CLKDIV", "UART3CLKDIV", "UART4CLKDIV", "UART5CLKDIV", "UART6CLKDIV", "UART7CLKDIV", "UART8CLKDIV", "UART9CLKDIV", "DEVICEID","PCON"
+group = "ICOLL", "HW_ICOLL_VECTOR", "HW_ICOLL_LEVELACK", "HW_ICOLL_CTRL", "HW_ICOLL_STAT", "HW_ICOLL_RAW0", "HW_ICOLL_RAW1", "HW_ICOLL_PRIORITY0", "HW_ICOLL_PRIORITY1", "HW_ICOLL_PRIORITY2", "HW_ICOLL_PRIORITY3", "HW_ICOLL_PRIORITY4", "HW_ICOLL_PRIORITY5", "HW_ICOLL_PRIORITY6", "HW_ICOLL_PRIORITY7", "HW_ICOLL_PRIORITY8", "HW_ICOLL_PRIORITY9", "HW_ICOLL_PRIORITY10", "HW_ICOLL_PRIORITY11", "HW_ICOLL_PRIORITY12", "HW_ICOLL_PRIORITY13", "HW_ICOLL_PRIORITY14", "HW_ICOLL_PRIORITY15", "HW_ICOLL_VBASE", "HW_ICOLL_DEBUG", "HW_ICOLL_DBGREAD0", "HW_ICOLL_DBGREAD1", "HW_ICOLL_DBGFLAG", "HW_ICOLL_DBGREQUEST0", "HW_ICOLL_DBGREQUEST1", "HW_ICOLL_CLEAR0", "HW_ICOLL_CLEAR1", "HW_ICOLL_UNDEF_VECTOR",
+group = "TIMER0", "HW_TIMER0_IR","HW_TIMER0_TCR","HW_TIMER0_DIR","HW_TIMER0_TC0","HW_TIMER0_TC1","HW_TIMER0_TC2","HW_TIMER0_TC3","HW_TIMER0_PR","HW_TIMER0_PC","HW_TIMER0_MCR","HW_TIMER0_MR0","HW_TIMER0_MR1","HW_TIMER0_MR2","HW_TIMER0_MR3","HW_TIMER0_CCR","HW_TIMER0_CR0","HW_TIMER0_CR1","HW_TIMER0_CR2","HW_TIMER0_CR3","HW_TIMER0_EMR","HW_TIMER0_PWMTH0","HW_TIMER0_PWMTH1","HW_TIMER0_PWMTH2","HW_TIMER0_PWMTH3","HW_TIMER0_CTCR","HW_TIMER0_PWMC"
+group = "USART3", "HW_USART3_CTRL0", "HW_USART3_CTRL1", "HW_USART3_CTRL2", "HW_USART3_LINECTRL", "HW_USART3_INTR", "HW_USART3_DATA", "HW_USART3_STAT", "HW_USART3_DEBUG", "HW_USART3_ILPR", "HW_USART3_RS485CTRL", "HW_USART3_RS485ADRMATCH", "HW_USART3_RS485DLY", "HW_USART3_AUTOBAUD", "HW_USART3_CTRL3", "HW_USART3_ISO7816CTRL", "HW_USART3_ISO7816ERRCNT", "HW_USART3_ISO7816STAT"
+group = "GPIO","HW_GPIO_DATA0" ,"HW_GPIO_DATA1" ,"HW_GPIO_DATA2" ,"HW_GPIO_DATA3" ,"HW_GPIO_DIR0" ,"HW_GPIO_DIR1" ,"HW_GPIO_DIR2" ,"HW_GPIO_DIR3" ,"HW_GPIO_IS0" ,"HW_GPIO_IS1" ,"HW_GPIO_IS2" ,"HW_GPIO_IS3" ,"HW_GPIO_IBE0" ,"HW_GPIO_IBE1" ,"HW_GPIO_IBE2" ,"HW_GPIO_IBE3" ,"HW_GPIO_IEV0" ,"HW_GPIO_IEV1" ,"HW_GPIO_IEV2" ,"HW_GPIO_IEV3" ,"HW_GPIO_IE0" ,"HW_GPIO_IE1" ,"HW_GPIO_IE2" ,"HW_GPIO_IE3" ,"HW_GPIO_IRS0" ,"HW_GPIO_IRS1" ,"HW_GPIO_IRS2" ,"HW_GPIO_IRS3" ,"HW_GPIO_MIS0" ,"HW_GPIO_MIS1" ,"HW_GPIO_MIS2" ,"HW_GPIO_MIS3" ,"HW_GPIO_IC0" ,"HW_GPIO_IC1" ,"HW_GPIO_IC2" ,"HW_GPIO_IC3" ,"HW_GPIO_DATAMASK0" ,"HW_GPIO_DATAMASK1" ,"HW_GPIO_DATAMASK2" ,"HW_GPIO_DATAMASK3"
\ No newline at end of file
diff --git a/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/devices/AlphaScale/ASM9260T.i79 b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/devices/AlphaScale/ASM9260T.i79
new file mode 100644
index 0000000000000000000000000000000000000000..5537e20b36ae41b6b1db7f17db1c857855f1cbe0
--- /dev/null
+++ b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/devices/AlphaScale/ASM9260T.i79
@@ -0,0 +1,43 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+//Chip name
+name=ASM9260T
+
+//What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+//Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+//Does the chip support the arm instruction set? (true(default), false)
+armsupport=true
+
+//Does the chip have an FPU coprocessor?
+//(VFPv1,VFPv2,VFP9-S,None(default)
+fpu=None
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=true
+RTCK=false
+SWD=false
+SWO_TraceD0=false
+
+[CORE]
+//Name of the ARM processor core
+name=ARM926EJ-S
+
+[DDF FILE]
+//Name of the ddf file
+name=AlphaScale\ASM9260T.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\AlphaScale\sam9260t\sam9260t_sdram.icf
+
+[FLASH LOADER]
+name=$TOOLKIT_DIR$\config\flashloader\
+
+
+
diff --git a/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/devices/AlphaScale/ASM9260T.menu b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/devices/AlphaScale/ASM9260T.menu
new file mode 100644
index 0000000000000000000000000000000000000000..ce695615023a76529f935164bff6fb27d518e964
--- /dev/null
+++ b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/devices/AlphaScale/ASM9260T.menu
@@ -0,0 +1,7 @@
+
+
+ ASM9260T
+ AlphaScale ASM9260T
+ $CUR_DIR$\ASM9260T.i79
+
+
diff --git a/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/linker/AlphaScale/sam9260t/sam9260t_sdram.icf b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/linker/AlphaScale/sam9260t/sam9260t_sdram.icf
new file mode 100644
index 0000000000000000000000000000000000000000..d2dee61b293baef9048017390dc171c75002bc2b
--- /dev/null
+++ b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/linker/AlphaScale/sam9260t/sam9260t_sdram.icf
@@ -0,0 +1,59 @@
+//------------------------------------------------------------------------------
+// Linker scatter for running in external SDRAM on the ASM9260T
+// By ArdaFu 2015-04-29
+//------------------------------------------------------------------------------
+
+//
+// Define a memory region that covers the entire 4 GB addressible space of the
+// processor.
+//
+define memory mem with size = 4G;
+
+//
+// Define a region for the on-chip flash. size = 2MB
+//
+define region FLASH = mem:[from 0x20000000 to 0x201FFFFF];
+
+//
+// Define a region for the on-chip SRAM. size = 30MB
+//
+define region SRAM = mem:[from 0x20200000 to 0x21FFFFFF];
+
+//
+// Indicate that the read/write values should be initialized by copying from
+// flash.
+//
+initialize by copy { readwrite };
+
+//
+// Indicate that the noinit values should be left alone. This includes the
+// stack, which if initialized will destroy the return address from the
+// initialization code, causing the processor to branch to zero and fault.
+//
+do not initialize { section .noinit };
+
+//
+// Place the interrupt vectors at the start of flash.
+//
+place at start of FLASH { readonly section .intvec };
+
+//
+// Place the remainder of the read-only items into flash.
+//
+place in FLASH { readonly };
+
+//
+// Place the RAM vector table at the start of SRAM.
+//
+place at start of SRAM { section VTABLE };
+
+//
+// Place all read/write items into SRAM.
+//
+place in SRAM { readwrite};
+//
+// RT-thread symbols
+//
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
diff --git a/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/readme b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/readme
new file mode 100644
index 0000000000000000000000000000000000000000..22280eadee3ff7d3d659943283ffe1940476a5b4
--- /dev/null
+++ b/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/readme
@@ -0,0 +1,7 @@
+How to use:
+(By ArdaFu 2015-04-29)
+
+1. Copy %arm% folder to &IAR EWARM% folder
+2. Restart your IDE.
+3. Select AlphaScale ASM9260T at project options-> General Options -> Target-> Device.
+4. Start debug :).
diff --git a/bsp/asm9260t/SConscript b/bsp/asm9260t/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8
--- /dev/null
+++ b/bsp/asm9260t/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/asm9260t/SConstruct b/bsp/asm9260t/SConstruct
new file mode 100644
index 0000000000000000000000000000000000000000..98b5712caf864a3e337df0e335ce8901f1e4e3f6
--- /dev/null
+++ b/bsp/asm9260t/SConstruct
@@ -0,0 +1,38 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+if GetDepend('RT_USING_WEBSERVER'):
+ objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
+
+if GetDepend('RT_USING_RTGUI'):
+ objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
+
+# libc testsuite
+#objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/asm9260t/applications/SConscript b/bsp/asm9260t/applications/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..01eb940dfb35f92c503a78b0b49a4354590f9f3a
--- /dev/null
+++ b/bsp/asm9260t/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/asm9260t/applications/application.c b/bsp/asm9260t/applications/application.c
new file mode 100644
index 0000000000000000000000000000000000000000..7c6484e4f04cf4d20342cfa915280a0e92fb8aa2
--- /dev/null
+++ b/bsp/asm9260t/applications/application.c
@@ -0,0 +1,76 @@
+/*
+ * File : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
+ */
+
+#include
+#include
+
+void rt_init_thread_entry(void* parameter)
+{
+ /* Initialization RT-Thread Components */
+ rt_components_init();
+}
+
+#ifdef RT_USING_LED
+#include "led.h"
+
+void rt_led_thread_entry(void* parameter)
+{
+ rt_uint8_t cnt = 0;
+ led_init();
+ while(1)
+ {
+ /* light on leds for one second */
+ rt_thread_delay(40);
+ cnt++;
+ if(cnt & 0x01)
+ led_on(1);
+ else
+ led_off(1);
+ }
+}
+
+static void start_led_thread(void)
+{
+ rt_thread_t led_thread;
+ led_thread = rt_thread_create("led", rt_led_thread_entry, RT_NULL, 512,
+ (RT_THREAD_PRIORITY_MAX / 8 * 5), 20);
+ if(led_thread != RT_NULL)
+ rt_thread_startup(led_thread);
+}
+#endif
+
+int rt_application_init()
+{
+ rt_thread_t init_thread;
+ init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
+ (RT_THREAD_PRIORITY_MAX / 8 * 2), 20);
+ if(init_thread != RT_NULL)
+ rt_thread_startup(init_thread);
+
+#ifdef RT_USING_LED
+ start_led_thread();
+#endif
+ return 0;
+}
diff --git a/bsp/asm9260t/applications/startup.c b/bsp/asm9260t/applications/startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..af038a98190a44a1579ac609f9fb3c9365385792
--- /dev/null
+++ b/bsp/asm9260t/applications/startup.c
@@ -0,0 +1,90 @@
+/*
+ * File : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ * 2015-04-21 ArdaFu Using init componment module
+ * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
+ */
+
+#include
+#include
+#include "board.h"
+
+extern void rt_application_init(void);
+
+#if defined(__CC_ARM)
+extern int Image$$ER_ZI$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
+#elif(defined(__GNUC__))
+extern unsigned char __bss_end__;
+#define HEAP_BEGIN (&__bss_end__)
+#elif(defined(__ICCARM__))
+#pragma section = ".noinit"
+#define HEAP_BEGIN (__section_end(".noinit"))
+#endif
+
+#define HEAP_END (0x22000000)
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+static void rtthread_startup(void)
+{
+ /* initialize board */
+ rt_hw_board_init();
+
+ /* show version */
+ rt_show_version();
+
+#ifdef RT_USING_HEAP
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+ /* initialize scheduler system */
+ rt_system_scheduler_init();
+ /* initialize system timer*/
+ rt_system_timer_init();
+ /* initialize application */
+ rt_application_init();
+
+ /* initialize timer thread */
+ rt_system_timer_thread_init();
+
+ /* initialize idle thread */
+ rt_thread_idle_init();
+
+ /* start scheduler */
+ rt_system_scheduler_start();
+
+ /* never reach here */
+ return;
+}
+
+int main(void)
+{
+ /* disable interrupt first */
+ rt_hw_interrupt_disable();
+
+ /* startup RT-Thread RTOS */
+ rtthread_startup();
+
+ return 0;
+}
diff --git a/bsp/asm9260t/drivers/SConscript b/bsp/asm9260t/drivers/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..d36885bbd00f565890f83cc56bd83eddffa5e684
--- /dev/null
+++ b/bsp/asm9260t/drivers/SConscript
@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drvers.
+src = Split("""
+board.c
+usart.c
+""")
+
+# add Ethernet drvers.
+if GetDepend('RT_USING_LED'):
+ src += ['led.c']
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/asm9260t/drivers/board.c b/bsp/asm9260t/drivers/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..f3fc53c51abcad62b3bf497acd5492a725fbd54d
--- /dev/null
+++ b/bsp/asm9260t/drivers/board.c
@@ -0,0 +1,90 @@
+/*
+ * File : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ * 2015-05-02 ArdaFu Port from AT91SAM9260 BSP
+ */
+
+#include
+#include
+#include
+#include "board.h"
+#include
+#include "interrupt.h"
+
+extern void rt_hw_interrupt_init(void);
+extern void rt_hw_clock_init(void);
+extern void rt_hw_uart_init(void);
+
+static struct mem_desc hw_mem_desc[] =
+{
+ { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },/* None cached for 4G memory */
+// visual start, visual end, phy start , props
+ { 0x00000000, 0x000FFFFF, 0x20000000, RW_CB }, /* ISR Vector table */
+ { 0x00200000, 0x00001FFF, 0x40000000, RW_CB }, /* 8K cached SRAM 0/1 */
+ { 0x20000000, 0x21FFFFFF, 0x20000000, RW_CB }, /* 32M cached SDRAM */
+ { 0x90000000, 0x90001FFF, 0x40000000, RW_NCNB },/* 4K SRAM0 + 4k SRAM1 */
+ { 0xA0000000, 0xA1FFFFFF, 0x20000000, RW_NCNB },/* 32M none-cached SDRAM */
+};
+
+/**
+ * This function will handle rtos timer
+ */
+static void rt_systick_handler(int vector, void *param)
+{
+ uint32_t ir = inl(HW_TIMER0_IR);
+ if (ir & 1UL)
+ rt_tick_increase();
+ outl(ir, REG_SET(HW_TIMER0_IR));
+}
+
+/**
+ * This function will init pit for system ticks
+ */
+static void rt_hw_timer_init()
+{
+ hw_timer0_init();
+ /* install interrupt handler */
+ rt_hw_interrupt_install(INT_TIMER0, rt_systick_handler, RT_NULL, "SysTick");
+ rt_hw_interrupt_umask(INT_TIMER0);
+
+}
+
+/**
+ * This function will init at91sam9260 board
+ */
+void rt_hw_board_init(void)
+{
+ /* initialize mmu */
+ rt_hw_mmu_init(hw_mem_desc, sizeof(hw_mem_desc)/sizeof(hw_mem_desc[0]));
+ /* initialize hardware interrupt */
+ rt_hw_interrupt_init();
+
+ /* initialize the system clock */
+ //rt_hw_clock_init(); //set each pll etc.
+
+ /* initialize uart */
+ rt_hw_uart_init();
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+ /* initialize timer0 */
+ rt_hw_timer_init();
+}
diff --git a/bsp/asm9260t/drivers/board.h b/bsp/asm9260t/drivers/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..e525509a183f99cd0deb56a3543ab7ae23f0caad
--- /dev/null
+++ b/bsp/asm9260t/drivers/board.h
@@ -0,0 +1,32 @@
+/*
+ * File : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/asm9260t/drivers/led.c b/bsp/asm9260t/drivers/led.c
new file mode 100644
index 0000000000000000000000000000000000000000..e2d6d7a79d47d05b0991ef505bba97e2581399ad
--- /dev/null
+++ b/bsp/asm9260t/drivers/led.c
@@ -0,0 +1,47 @@
+/*
+ * File : led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+
+#include
+#include
+#include "led.h"
+#include "gpio.h"
+
+//ASM9260T EVK pin 16-7 LED0, 0: ON, 1 : OFF
+void led_init(void)
+{
+ // enable IOCONFIG GPIO
+ outl(((1UL<<25) | (1UL<<4)) , REG_SET(HW_AHBCLKCTRL0));
+ HW_SetPinMux(16,7,0);
+ HW_GpioSetDir(16,7,1);
+}
+
+void led_on(int num)
+{
+ HW_GpioClrVal(16, 7 );
+}
+
+void led_off(int num)
+{
+ HW_GpioSetVal(16, 7 );
+}
diff --git a/bsp/asm9260t/drivers/led.h b/bsp/asm9260t/drivers/led.h
new file mode 100644
index 0000000000000000000000000000000000000000..f2967bc92d333f5a2c23af7dfc793c2993b5ad74
--- /dev/null
+++ b/bsp/asm9260t/drivers/led.h
@@ -0,0 +1,32 @@
+/*
+ * File : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ */
+
+#ifndef __LED_H__
+#define __LED_H__
+
+void led_init(void);
+void led_on(int num);
+void led_off(int num);
+
+#endif
diff --git a/bsp/asm9260t/drivers/usart.c b/bsp/asm9260t/drivers/usart.c
new file mode 100644
index 0000000000000000000000000000000000000000..617e526afc69ebd807dd29addc9efe8c09e34d05
--- /dev/null
+++ b/bsp/asm9260t/drivers/usart.c
@@ -0,0 +1,247 @@
+/*
+ * File : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ * 2013-07-21 weety using serial component
+ * 2015-05-02 ArdaFu Port from AT91SAM9260 BSP
+ */
+
+#include
+#include
+#include
+#include "interrupt.h"
+#include
+#include "gpio.h"
+
+#include "uart.h"
+
+typedef struct
+{
+ HW_USART_TypeDef *port;
+ int irq;
+} asm_uart_t;
+
+
+/**
+ * This function will handle serial
+ */
+void rt_asm_usart_handler(int vector, void *param)
+{
+ rt_uint32_t status;
+ asm_uart_t *uart;
+ rt_device_t dev = (rt_device_t)param;
+ uart = (asm_uart_t *)dev->user_data;
+ status = uart->port->INTR[R_VAL];
+
+ if(!(status & (ASM_UART_INTR_RXIS | ASM_UART_INTR_RTIS)))
+ return;
+ uart->port->INTR[R_CLR] = ASM_UART_INTR_RXIS|ASM_UART_INTR_RTIS;
+ //rt_interrupt_enter();
+ rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+ //rt_interrupt_leave();
+
+}
+
+
+/**
+* UART device in RT-Thread
+*/
+static rt_err_t asm_usart_configure(struct rt_serial_device *serial,
+ struct serial_configure *cfg)
+{
+ asm_uart_t *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+ uart = (asm_uart_t *)serial->parent.user_data;
+
+ Hw_UartDisable(uart->port);
+
+ Hw_UartReset(uart->port);
+
+ Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits,
+ cfg->stop_bits, cfg->parity);
+
+ Hw_UartEnable(uart->port);
+
+ return RT_EOK;
+}
+
+static rt_err_t asm_usart_control(struct rt_serial_device *serial,
+ int cmd, void *arg)
+{
+ asm_uart_t* uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (asm_uart_t *)serial->parent.user_data;
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ /* disable rx irq */
+ rt_hw_interrupt_mask(uart->irq);
+ break;
+ case RT_DEVICE_CTRL_SET_INT:
+ /* enable rx irq */
+ rt_hw_interrupt_umask(uart->irq);
+ break;
+ }
+
+ return RT_EOK;
+}
+
+
+static int asm_usart_putc(struct rt_serial_device *serial, char c)
+{
+ //rt_uint32_t level;
+ asm_uart_t *uart = serial->parent.user_data;
+
+ while ((uart->port->STAT[R_VAL] & ASM_UART_STAT_TXFF));
+ uart->port->DATA[R_VAL] = c;
+
+ return 1;
+}
+
+static int asm_usart_getc(struct rt_serial_device *serial)
+{
+ asm_uart_t *uart = serial->parent.user_data;
+
+ if (uart->port->STAT[R_VAL] & ASM_UART_STAT_RXFE)
+ return -1;
+ return uart->port->DATA[R_VAL] & 0xff;
+}
+
+static const struct rt_uart_ops asm_usart_ops =
+{
+ asm_usart_configure,
+ asm_usart_control,
+ asm_usart_putc,
+ asm_usart_getc,
+};
+
+
+#if defined(RT_USING_UART0)
+static struct rt_serial_device serial0;
+asm_uart_t uart0 =
+{
+ USART0,
+ INT_UART0
+};
+#endif
+
+#if defined(RT_USING_UART3)
+static struct rt_serial_device serial3;
+asm_uart_t uart3 =
+{
+ USART3,
+ INT_UART3
+};
+#endif
+
+#if defined(RT_USING_UART4)
+static struct rt_serial_device serial4;
+asm_uart_t uart4 =
+{
+ USART4,
+ INT_UART4
+};
+#endif
+
+//USART0 PINS TX=GP14_0:5 , RX=GP14_1:5
+//USART3 PINS TX=GP8_6:2 , RX=GP8_7:2
+//USART4 PINS TX=GP3_0:2 , RX=GP3_1:2
+
+void asm_usart_gpio_init(void)
+{
+ // enable IOCONFIG GPIO
+ outl(((1UL<<25) | (1UL<<4)) ,REG_SET(HW_AHBCLKCTRL0));
+#ifdef RT_USING_UART0
+ HW_SetPinMux(14, 0, 5);
+ HW_SetPinMux(14, 1, 5);
+#endif
+
+#ifdef RT_USING_UART3
+ HW_SetPinMux(8, 6, 2);
+ HW_SetPinMux(8, 7, 2);
+#endif
+
+#ifdef RT_USING_UART4
+ HW_SetPinMux(3, 0, 2);
+ HW_SetPinMux(3, 1, 2);
+#endif
+}
+
+void asm_serial_config_set_default(struct rt_serial_device* serial)
+{
+ serial->ops = &asm_usart_ops;
+
+ serial->config.baud_rate = BAUD_RATE_115200;
+ serial->config.bit_order = BIT_ORDER_LSB;
+ serial->config.data_bits = DATA_BITS_8;
+ serial->config.parity = PARITY_NONE;
+ serial->config.stop_bits = STOP_BITS_1;
+ serial->config.invert = NRZ_NORMAL;
+ serial->config.bufsz = RT_SERIAL_RB_BUFSZ;
+}
+#define DRV_REG_OPS (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM)
+/**
+ * This function will handle init uart
+ */
+int rt_hw_uart_init(void)
+{
+ asm_usart_gpio_init();
+
+#if defined(RT_USING_UART0)
+ Hw_UartInit(0);
+ asm_serial_config_set_default(&serial0);
+
+ /* register uart device */
+ rt_hw_serial_register(&serial0, "uart0", DRV_REG_OPS, &uart0);
+ rt_hw_interrupt_install(uart0.irq, rt_asm_usart_handler,
+ (void *)&(serial0.parent), "UART0");
+ rt_hw_interrupt_umask(uart0.irq);
+#endif
+
+#if defined(RT_USING_UART3)
+ Hw_UartInit(3);
+ asm_serial_config_set_default(&serial3);
+
+ /* register uart device */
+ rt_hw_serial_register(&serial3, "uart3", DRV_REG_OPS, &uart3);
+ rt_hw_interrupt_install(uart3.irq, rt_asm_usart_handler,
+ (void *)&(serial3.parent), "UART3");
+ rt_hw_interrupt_umask(uart3.irq);
+#endif
+
+#if defined(RT_USING_UART4)
+ Hw_UartInit(4);
+ asm_serial_config_set_default(&serial4);
+
+ /* register uart device */
+ rt_hw_serial_register(&serial4, "uart4", DRV_REG_OPS, &uart4);
+ rt_hw_interrupt_install(uart4.irq, rt_asm_usart_handler,
+ (void *)&(serial4.parent), "UART4");
+ rt_hw_interrupt_umask(uart4.irq);
+#endif
+
+ return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/asm9260t/jlink/asm9260t.gdb b/bsp/asm9260t/jlink/asm9260t.gdb
new file mode 100644
index 0000000000000000000000000000000000000000..4edde54a8a160f3be531ad257d6caa0c07800da6
--- /dev/null
+++ b/bsp/asm9260t/jlink/asm9260t.gdb
@@ -0,0 +1,71 @@
+#------------------------------------------------
+# SDRAM initialization script for the ASM9260T
+#------------------------------------------------
+
+define __setup_PLL
+ echo "Enabling PLL for CPU" \n
+
+ # outl(1<<2, REG_SET(HW_AHBCLKCTRL0));
+ set *0x80040024 = 0x00000004
+ # outl(1<<8, REG_SET(HW_AHBCLKCTRL1));
+ set *0x80040034 = 0x00000100
+ # outl(3<<9, REG_SET(HW_AHBCLKCTRL0));
+ set *0x80040024 = 0x00000600
+ # outl(inl(HW_PDRUNCFG)&0xFFFFFFFA, HW_PDRUNCFG);
+ set *0x80040238 = 0x00000770
+ # outl(2, HW_CPUCLKDIV);
+ set *0x8004017C = 0x00000002
+ # outl(2, HW_SYSAHBCLKDIV);
+ set *0x80040180 = 0x00000002
+ # outl(480, HW_SYSPLLCTRL);
+ set *0x80040100 = 0x000001E0
+ # __delay(50)
+ set $i = 0
+ while $i != 500
+ set $i += 1
+ end
+ # outl(1, HW_MAINCLKSEL);
+ set *0x80040120 = 0x00000001
+ # outl(0, HW_MAINCLKUEN);
+ set *0x80040124 = 0x00000000
+ # outl(1, HW_MAINCLKUEN);
+ set *0x80040124 = 0x00000001
+end
+
+define __setup_SDRAM
+ echo "Enabling on-chip SDRAM" \n
+
+ # outl((1<<6), REG_SET(HW_AHBCLKCTRL0));
+ set *0x80040024 = 0x00000040
+ # outl(0x00001188, HW_EMI_SCONR);
+ set *0x80700000 = 0x00001188
+ # outl(0x000a0500, HW_EMI_CTRL);
+ set *0x8004034c = 0x000a0500
+ # outl(0x20000000, HW_EMI_SCSLR2_LOW);
+ set *0x8070001c = 0x20000000
+ # outl(0x0000000c, HW_EMI_SMSKR2);
+ set *0x8070005c = 0x0000000c
+ # outl(0x024996d9, HW_EMI_STMG0R);
+ set *0x80700004 = 0x024996d9
+ # outl(0x00542b4f, HW_EMI_SMTMGR_SET0);
+ set *0x80700094 = 0x00542b4f
+ # outl(0x00003288, HW_EMI_SCTLR);
+ set *0x8070000c = 0x00003288
+end
+
+# Step1: Connect to the J-Link gdb server
+define reset
+ #target remote localhost:2331
+ monitor reset
+
+ # Step2: Reset peripheral (RSTC_CR)
+ echo "------- Prepare for debug ASM9260T -------" \n
+ __setup_PLL
+ __setup_SDRAM
+
+ # Step3: Load file(eg. getting-started project)
+ load
+
+ mon reg pc=0x20000000
+ #info reg
+end
\ No newline at end of file
diff --git a/bsp/asm9260t/jlink/asm9260t.ini b/bsp/asm9260t/jlink/asm9260t.ini
new file mode 100644
index 0000000000000000000000000000000000000000..0ed621004e4a8689b126dc05f5897917e5d314c5
--- /dev/null
+++ b/bsp/asm9260t/jlink/asm9260t.ini
@@ -0,0 +1,61 @@
+//------------------------------------------------
+// SDRAM initialization script for the ASM9260T
+//------------------------------------------------
+
+FUNC void __setup_PLL()
+{
+ printf( "Enabling PLL for CPU\n");
+
+ // outl(1<<2, REG_SET(HW_AHBCLKCTRL0));
+ _WDWORD(0x80040024, 0x00000004);
+ // outl(1<<8, REG_SET(HW_AHBCLKCTRL1));
+ _WDWORD(0x80040034, 0x00000100);
+ // outl(3<<9, REG_SET(HW_AHBCLKCTRL0));
+ _WDWORD(0x80040024, 0x00000600);
+ // outl(inl(HW_PDRUNCFG)&0xFFFFFFFA, HW_PDRUNCFG);
+ _WDWORD(0x80040238, 0x00000770);
+ // outl(2, HW_CPUCLKDIV);
+ _WDWORD(0x8004017C, 0x00000002);
+ // outl(2, HW_SYSAHBCLKDIV);
+ _WDWORD(0x80040180, 0x00000002);
+ // outl(480, HW_SYSPLLCTRL);
+ _WDWORD(0x80040100, 0x000001E0);
+ _sleep_(500);
+ // outl(1, HW_MAINCLKSEL);
+ _WDWORD(0x80040120, 0x00000001);
+ // outl(0, HW_MAINCLKUEN);
+ _WDWORD(0x80040124, 0x00000000);
+ // outl(1, HW_MAINCLKUEN);
+ _WDWORD(0x80040124, 0x00000001);
+}
+
+
+FUNC void __setup_SDRAM()
+{
+ printf( "Enabling on-chip SDRAM\n");
+
+ // outl((1<<6), REG_SET(HW_AHBCLKCTRL0));
+ _WDWORD(0x80040024, 0x00000040);
+ // outl(0x00001188, HW_EMI_SCONR);
+ _WDWORD(0x80700000, 0x00001188);
+ // outl(0x000a0500, HW_EMI_CTRL);
+ _WDWORD(0x8004034c, 0x000a0500);
+ // outl(0x20000000, HW_EMI_SCSLR2_LOW);
+ _WDWORD(0x8070001c, 0x20000000);
+ // outl(0x0000000c, HW_EMI_SMSKR2);
+ _WDWORD(0x8070005c, 0x0000000c);
+ // outl(0x024996d9, HW_EMI_STMG0R);
+ _WDWORD(0x80700004, 0x024996d9);
+ // outl(0x00542b4f, HW_EMI_SMTMGR_SET0);
+ _WDWORD(0x80700094, 0x00542b4f);
+ // outl(0x00003288, HW_EMI_SCTLR);
+ _WDWORD(0x8070000c, 0x00003288);
+}
+
+printf( "------- Prepare for debug ASM9260T -------");
+__setup_PLL();
+__setup_SDRAM();
+DEBUG_CLOCK = 2000000;
+LOAD Objects\\template.axf INCREMENTAL
+PC = 0x20000000;
+g,main
\ No newline at end of file
diff --git a/bsp/asm9260t/jlink/asm9260t.mac b/bsp/asm9260t/jlink/asm9260t.mac
new file mode 100644
index 0000000000000000000000000000000000000000..0a80f05cc334b0a4cf386999e31801eacf43c971
--- /dev/null
+++ b/bsp/asm9260t/jlink/asm9260t.mac
@@ -0,0 +1,59 @@
+//------------------------------------------------
+// SDRAM initialization script for the ASM9260T
+//------------------------------------------------
+
+__setup_PLL()
+{
+ __message "Enabling PLL for CPU\n";
+
+ // outl(1<<2, REG_SET(HW_AHBCLKCTRL0));
+ __writeMemory32(0x00000004, 0x80040024, "Memory");
+ // outl(1<<8, REG_SET(HW_AHBCLKCTRL1));
+ __writeMemory32(0x00000100, 0x80040034, "Memory");
+ // outl(3<<9, REG_SET(HW_AHBCLKCTRL0));
+ __writeMemory32(0x00000600, 0x80040024, "Memory");
+ // outl(inl(HW_PDRUNCFG)&0xFFFFFFFA, HW_PDRUNCFG);
+ __writeMemory32(0x00000770, 0x80040238, "Memory");
+ // outl(2, HW_CPUCLKDIV);
+ __writeMemory32(0x00000002, 0x8004017C, "Memory");
+ // outl(2, HW_SYSAHBCLKDIV);
+ __writeMemory32(0x00000002, 0x80040180, "Memory");
+ // outl(480, HW_SYSPLLCTRL);
+ __writeMemory32(0x000001E0, 0x80040100, "Memory");
+ __delay(50);
+ // outl(1, HW_MAINCLKSEL);
+ __writeMemory32(0x00000001, 0x80040120, "Memory");
+ // outl(0, HW_MAINCLKUEN);
+ __writeMemory32(0x00000000, 0x80040124, "Memory");
+ // outl(1, HW_MAINCLKUEN);
+ __writeMemory32(0x00000001, 0x80040124, "Memory");
+}
+
+__setup_SDRAM()
+{
+ __message "Enabling on-chip SDRAM\n";
+
+ // outl((1<<6), REG_SET(HW_AHBCLKCTRL0));
+ __writeMemory32(0x00000040, 0x80040024, "Memory");
+ // outl(0x00001188, HW_EMI_SCONR);
+ __writeMemory32(0x00001188, 0x80700000, "Memory");
+ // outl(0x000a0500, HW_EMI_CTRL);
+ __writeMemory32(0x000a0500, 0x8004034c, "Memory");
+ // outl(0x20000000, HW_EMI_SCSLR2_LOW);
+ __writeMemory32(0x20000000, 0x8070001c, "Memory");
+ // outl(0x0000000c, HW_EMI_SMSKR2);
+ __writeMemory32(0x0000000c, 0x8070005c, "Memory");
+ // outl(0x024996d9, HW_EMI_STMG0R);
+ __writeMemory32(0x024996d9, 0x80700004, "Memory");
+ // outl(0x00542b4f, HW_EMI_SMTMGR_SET0);
+ __writeMemory32(0x00542b4f, 0x80700094, "Memory");
+ // outl(0x00003288, HW_EMI_SCTLR);
+ __writeMemory32(0x00003288, 0x8070000c, "Memory");
+}
+
+execUserPreload()
+{
+ __message "------- Prepare for debug ASM9260T -------";
+ __setup_PLL();
+ __setup_SDRAM();
+}
diff --git a/bsp/asm9260t/link_scripts/sdram.icf b/bsp/asm9260t/link_scripts/sdram.icf
new file mode 100644
index 0000000000000000000000000000000000000000..f6fe642bee0b93c69e6436d61f8d2453210ddfa8
--- /dev/null
+++ b/bsp/asm9260t/link_scripts/sdram.icf
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+// Linker scatter for running in external SDRAM on the AT91SAM9260
+//------------------------------------------------------------------------------
+
+//
+// Define a memory region that covers the entire 4 GB addressible space of the
+// processor.
+//
+define memory mem with size = 4G;
+
+//
+// Define a region for the on-chip flash. size = 2MB
+//
+define region FLASH = mem:[from 0x20000000 to 0x201FFFFF];
+
+//
+// Define a region for the on-chip SRAM. size = 30MB
+//
+define region SRAM = mem:[from 0x20200000 to 0x21FFFFFF];
+
+//
+// Indicate that the read/write values should be initialized by copying from
+// flash.
+//
+initialize by copy { readwrite };
+
+//
+// Indicate that the noinit values should be left alone. This includes the
+// stack, which if initialized will destroy the return address from the
+// initialization code, causing the processor to branch to zero and fault.
+//
+do not initialize { section .noinit };
+
+//
+// Place the interrupt vectors at the start of flash.
+//
+place at start of FLASH { readonly section .intvec };
+
+//
+// Place the remainder of the read-only items into flash.
+//
+place in FLASH { readonly };
+
+//
+// Place the RAM vector table at the start of SRAM.
+//
+place at start of SRAM { section VTABLE };
+
+//
+// Place all read/write items into SRAM.
+//
+place in SRAM { readwrite};
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
diff --git a/bsp/asm9260t/link_scripts/sdram.ld b/bsp/asm9260t/link_scripts/sdram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..258881b082fe49ac591a643f2f8220f831ff6e43
--- /dev/null
+++ b/bsp/asm9260t/link_scripts/sdram.ld
@@ -0,0 +1,90 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+SECTIONS
+{
+ . = 0x20000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.init)
+ *(.text)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ /* section information for modules */
+ . = ALIGN(4);
+ __rtmsymtab_start = .;
+ KEEP(*(RTMSymTab))
+ __rtmsymtab_end = .;
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
+
+ . = ALIGN(4);
+ .ctors :
+ {
+ PROVIDE(__ctors_start__ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(__ctors_end__ = .);
+ }
+
+ .dtors :
+ {
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+ }
+
+ . = ALIGN(4);
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+ }
+
+ . = ALIGN(4);
+ .nobss : { *(.nobss) }
+
+ . = ALIGN(4);
+ __bss_start__ = .;
+ .bss : { *(.bss)}
+ __bss_end__ = .;
+
+ /* stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+
+ _end = .;
+}
diff --git a/bsp/asm9260t/link_scripts/sdram.scat b/bsp/asm9260t/link_scripts/sdram.scat
new file mode 100644
index 0000000000000000000000000000000000000000..71f8bcec825699559f09e39d3eec7259b80fd822
--- /dev/null
+++ b/bsp/asm9260t/link_scripts/sdram.scat
@@ -0,0 +1,27 @@
+;*------------------------------------------------------------------------------
+;* Linker scatter for running in external SDRAM on the ASM9260T
+;*----------------------------------------------------------------------------*/
+
+Load_region 0x20000000 0x00200000
+{
+
+ Fixed_region 0x20000000
+ {
+ * (RESET +First)
+ .ANY (+RO +RW)
+ }
+
+ ARM_LIB_HEAP +0 EMPTY 0x1000
+ {
+ }
+
+ ARM_LIB_STACK +0 EMPTY 0x1000
+ {
+ }
+
+ ; Application ZI data (.bss)
+ ER_ZI +0
+ {
+ * (+ZI)
+ }
+}
diff --git a/bsp/asm9260t/platform/SConscript b/bsp/asm9260t/platform/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..5df4a5fc63598c7611f7f1ed61c0c0f8c790b627
--- /dev/null
+++ b/bsp/asm9260t/platform/SConscript
@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+
+# The set of source files associated with this SConscript file.
+src = Glob('*.c')
+
+group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
diff --git a/bsp/asm9260t/platform/asm9260t.h b/bsp/asm9260t/platform/asm9260t.h
new file mode 100644
index 0000000000000000000000000000000000000000..440375ce9ae1014f219f1e0b265298618a3bcce0
--- /dev/null
+++ b/bsp/asm9260t/platform/asm9260t.h
@@ -0,0 +1,670 @@
+#ifndef __ASM9260T_REGS_H__
+#define __ASM9260T_REGS_H__
+////////////////////////////////////////////////////////////////////////////////
+
+typedef volatile unsigned char *VP8;
+typedef volatile unsigned short *VP16;
+typedef volatile unsigned long *VP32;
+
+#define __I volatile const /*!< Defines 'read only' permissions */
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+#define outb(v, r) do{*((VP8)(r))=(v);}while(0)
+#define outw(v, r) do{*((VP16)(r))=(v);}while(0)
+#define outl(v, r) do{*((VP32)(r))=(v);}while(0)
+
+#define inb(r) (*((VP8)(r)))
+#define inw(r) (*((VP16)(r)))
+#define inl(r) (*((VP32)(r)))
+
+#define REG_VAL(r) (((unsigned long)(r))+0x00)
+#define REG_SET(r) (((unsigned long)(r))+0x04)
+#define REG_CLR(r) (((unsigned long)(r))+0x08)
+#define REG_TOG(r) (((unsigned long)(r))+0x0C)
+
+////////////////////////////////////////////////////////////////////////////////
+// SYSTEM CONFIG
+#define HW_PRESETCTRL0 0x80040000
+#define HW_PRESETCTRL1 0x80040010
+#define HW_AHBCLKCTRL0 0x80040020
+#define HW_AHBCLKCTRL1 0x80040030
+#define HW_SYSTCKCAL 0x80040040
+#define HW_SYSPLLCTRL 0x80040100
+#define HW_SYSPLLSTAT 0x80040104
+#define HW_SYSRSTSTAT 0x80040110
+#define HW_MAINCLKSEL 0x80040120
+#define HW_MAINCLKUEN 0x80040124
+#define HW_UARTCLKSEL 0x80040128
+#define HW_UARTCLKUEN 0x8004012C
+#define HW_I2S0CLKSEL 0x80040130
+#define HW_I2S0CLKUEN 0x80040134
+#define HW_I2S1CLKSEL 0x80040138
+#define HW_I2S1CLKUEN 0x8004013C
+#define HW_USBCLKSEL 0x80040140
+#define HW_USBCLKUEN 0x80040144
+#define HW_WDTCLKSEL 0x80040160
+#define HW_WDTCLKUEN 0x80040164
+#define HW_OUTCLKSEL 0x80040170
+#define HW_OUTCLKUEN 0x80040174
+#define HW_CPUCLKDIV 0x8004017C
+#define HW_SYSAHBCLKDIV 0x80040180
+#define HW_I2S1_MCLKDIV 0x80040188
+#define HW_I2S1_SCLKDIV 0x8004018C
+#define HW_I2S0_MCLKDIV 0x80040190
+#define HW_I2S0_SCLKDIV 0x80040194
+#define HW_UART0CLKDIV 0x80040198
+#define HW_UART1CLKDIV 0x8004019C
+#define HW_UART2CLKDIV 0x800401A0
+#define HW_UART3CLKDIV 0x800401A4
+#define HW_UART4CLKDIV 0x800401A8
+#define HW_UART5CLKDIV 0x800401AC
+#define HW_UART6CLKDIV 0x800401B0
+#define HW_UART7CLKDIV 0x800401B4
+#define HW_UART8CLKDIV 0x800401B8
+#define HW_UART9CLKDIV 0x800401BC
+#define HW_SPI0CLKDIV 0x800401C0
+#define HW_SPI1CLKDIV 0x800401C4
+#define HW_QUADSPI0CLKDIV 0x800401C8
+#define HW_SSP0CLKDIV 0x800401D0
+#define HW_NANDCLKDIV 0x800401D4
+#define HW_TRACECLKDIV 0x800401E0
+#define HW_CAMMCLKDIV 0x800401E8
+#define HW_WDTCLKDIV 0x800401EC
+#define HW_USBCLKDIV 0x800401F0
+#define HW_OUTCLKDIV 0x800401F4
+#define HW_MACCLKDIV 0x800401F8
+#define HW_LCDCLKDIV 0x800401FC
+#define HW_ADCCLKDIV 0x80040200
+#define HW_PDRUNCFG 0x80040238
+#define HW_MATRIXPRI0 0x80040300
+#define HW_MATRIXPRI1 0x80040304
+#define HW_MATRIXPRI2 0x80040308
+#define HW_MATRIXPRI3 0x8004030C
+#define HW_MATRIXPRI4 0x80040310
+#define HW_MATRIXPRI5 0x80040314
+#define HW_MATRIXPRI6 0x80040318
+#define HW_MATRIXPRI7 0x8004031C
+#define HW_MATRIXPRI8 0x80040320
+#define HW_MATRIXPRI9 0x80040324
+#define HW_MATRIXPRI10 0x80040328
+#define HW_MATRIXPRI11 0x8004032C
+#define HW_MATRIXPRI12 0x80040330
+#define HW_MATRIXPRI13 0x80040334
+#define HW_MATRIXPRI14 0x80040338
+#define HW_MATRIXPRI15 0x8004033C
+#define HW_EMI_CTRL 0x8004034C
+#define HW_RISC_CTRL 0x80040350
+#define HW_DMA_CTRL 0x80040354
+#define HW_MACPHY_SEL 0x80040360
+#define HW_USB_CTRL 0x80040368
+#define HW_ANA_CTRL 0x80040370
+#define HW_USB0_TEST 0x80040380
+#define HW_USB1_TEST 0x80040390
+#define HW_USB0_RSTPARA 0x800403A0
+#define HW_USB1_RSTPARA 0x800403B0
+#define HW_DEVICEID 0x80040400
+#define HW_PCON_ADDR 0x80040500
+
+////////////////////////////////////////////////////////////////////////////////
+// EMI
+#define HW_EMI_SCONR 0x80700000
+#define HW_EMI_STMG0R 0x80700004
+#define HW_EMI_STMG1R 0x80700008
+#define HW_EMI_SCTLR 0x8070000C
+#define HW_EMI_SREFR 0x80700010
+#define HW_EMI_SCSLR0_LOW 0x80700014
+#define HW_EMI_SCSLR1_LOW 0x80700018
+#define HW_EMI_SCSLR2_LOW 0x8070001c
+#define HW_EMI_SCSLR3_LOW 0x80700020
+#define HW_EMI_SCSLR4_LOW 0x80700024
+#define HW_EMI_SCSLR5_LOW 0x80700028
+#define HW_EMI_SCSLR6_LOW 0x8070002c
+#define HW_EMI_SCSLR7_LOW 0x80700030
+
+#define HW_EMI_SMSKR0 0x80700054
+#define HW_EMI_SMSKR1 0x80700058
+#define HW_EMI_SMSKR2 0x8070005c
+#define HW_EMI_SMSKR3 0x80700060
+#define HW_EMI_SMSKR4 0x80700064
+#define HW_EMI_SMSKR5 0x80700068
+#define HW_EMI_SMSKR6 0x8070006c
+#define HW_EMI_SMSKR7 0x80700070
+
+#define HW_EMI_CSALIAS0_LOW 0x80700074
+#define HW_EMI_CSALIAS1_LOW 0x80700078
+
+#define HW_EMI_CSREMAP0_LOW 0x80700084
+#define HW_EMI_CSREMAP1_LOW 0x80700088
+
+#define HW_EMI_SMTMGR_SET0 0x80700094
+#define HW_EMI_SMTMGR_SET1 0x80700098
+#define HW_EMI_SMTMGR_SET2 0x8070009c
+
+#define HW_EMI_FLASH_TRPDR 0x807000a0
+#define HW_EMI_SMCTLR 0x807000a4
+#define HW_EMI_EXN_MODE_REG 0x807000ac
+
+////////////////////////////////////////////////////////////////////////////////
+// IOCON
+#define HW_IOCON_PIO_BASE 0x80044000
+#define HW_IOCON_SCKLOC 0x800442c0
+#define HW_IOCON(port,pin) (HW_IOCON_PIO_BASE|(((port)<<5)|((pin)<<2)))
+
+////////////////////////////////////////////////////////////////////////////////
+// GPIO
+#define HW_GPIO_DATA_BASE 0x50000000
+
+#define HW_GPIO_DMA_CTRL 0x50000010
+#define HW_GPIO_DMA_DATA 0x50000020
+#define HW_GPIO_DMA_PADCTRL0 0x50000030
+#define HW_GPIO_DMA_PADCTRL1 0x50000040
+#define HW_GPIO_DMA_PADCTRL2 0x50000050
+#define HW_GPIO_DMA_PADCTRL3 0x50000060
+#define HW_GPIO_DMA_CTRL1 0x50000070
+#define HW_GPIO_DMA_CTRL2 0x50000080
+#define HW_GPIO_DMA_CTRL3 0x50000090
+#define HW_GPIO_DMA_CTRL4 0x500000a0
+
+#define HW_GPIO_DATA0 0x50000000
+#define HW_GPIO_DATA1 0x50010000
+#define HW_GPIO_DATA2 0x50020000
+#define HW_GPIO_DATA3 0x50030000
+#define HW_GPIO_DATA4 0x50040000
+
+#define HW_GPIO_DIR0 0x50008000
+#define HW_GPIO_DIR1 0x50018000
+#define HW_GPIO_DIR2 0x50028000
+#define HW_GPIO_DIR3 0x50038000
+#define HW_GPIO_DIR4 0x50048000
+
+#define HW_GPIO_IS0 0x50008010
+#define HW_GPIO_IS1 0x50018010
+#define HW_GPIO_IS2 0x50028010
+#define HW_GPIO_IS3 0x50038010
+#define HW_GPIO_IS4 0x50048010
+
+#define HW_GPIO_IBE0 0x50008020
+#define HW_GPIO_IBE1 0x50018020
+#define HW_GPIO_IBE2 0x50028020
+#define HW_GPIO_IBE3 0x50038020
+#define HW_GPIO_IBE4 0x50048020
+
+#define HW_GPIO_IEV0 0x50008030
+#define HW_GPIO_IEV1 0x50018030
+#define HW_GPIO_IEV2 0x50028030
+#define HW_GPIO_IEV3 0x50038030
+#define HW_GPIO_IEV4 0x50048030
+
+#define HW_GPIO_IE0 0x50008040
+#define HW_GPIO_IE1 0x50018040
+#define HW_GPIO_IE2 0x50028040
+#define HW_GPIO_IE3 0x50038040
+#define HW_GPIO_IE4 0x50048040
+
+#define HW_GPIO_RIS0 0x50008050
+#define HW_GPIO_RIS1 0x50018050
+#define HW_GPIO_RIS2 0x50028050
+#define HW_GPIO_RIS3 0x50038050
+#define HW_GPIO_RIS4 0x50048050
+
+#define HW_GPIO_MIS0 0x50008060
+#define HW_GPIO_MIS1 0x50018060
+#define HW_GPIO_MIS2 0x50028060
+#define HW_GPIO_MIS3 0x50038060
+#define HW_GPIO_MIS4 0x50048060
+
+#define HW_GPIO_IC0 0x50008070
+#define HW_GPIO_IC1 0x50018070
+#define HW_GPIO_IC2 0x50028070
+#define HW_GPIO_IC3 0x50038070
+#define HW_GPIO_IC4 0x50048070
+
+#define HW_GPIO_DATAMASK0 0x50008080
+#define HW_GPIO_DATAMASK1 0x50018080
+#define HW_GPIO_DATAMASK2 0x50028080
+#define HW_GPIO_DATAMASK3 0x50038080
+#define HW_GPIO_DATAMASK4 0x50048080
+
+////////////////////////////////////////////////////////////////////////////////
+// Quad-SPI0
+#define QSPI0_BASE_ADDRESS 0x80068000
+#define HW_QSPI0_CTRL0 0x80068000
+#define HW_QSPI0_CTRL1 0x80068010
+#define HW_QSPI0_CMD 0x80068020
+#define HW_QSPI0_TIMING 0x80068030
+#define HW_QSPI0_DATA 0x80068040
+#define HW_QSPI0_STATUS 0x80068050
+#define HW_QSPI0_DEBUG0 0x80068060
+#define HW_QSPI0_XFER 0x80068070
+
+/////////////////////////////////////////////////////////
+//DMA0
+#define HW_DMA0_SAR0 0x80100000
+#define HW_DMA0_DAR0 0x80100008
+#define HW_DMA0_LLP0 0x80100010
+#define HW_DMA0_CTL0 0x80100018
+#define HW_DMA0_SSTAT0 0x80100020
+#define HW_DMA0_DSTAT0 0x80100028
+#define HW_DMA0_SSTATAR0 0x80100030
+#define HW_DMA0_DSTATAR0 0x80100038
+#define HW_DMA0_CFG0 0x80100040
+#define HW_DMA0_SGR0 0x80100048
+#define HW_DMA0_DSR0 0x80100050
+
+#define HW_DMA0_SAR1 0x80100058
+#define HW_DMA0_DAR1 0x80100060
+#define HW_DMA0_LLP1 0x80100068
+#define HW_DMA0_CTL1 0x80100070
+#define HW_DMA0_SSTAT1 0x80100078
+#define HW_DMA0_DSTAT1 0x80100080
+#define HW_DMA0_SSTATAR1 0x80100088
+#define HW_DMA0_DSTATAR1 0x80100090
+#define HW_DMA0_CFG1 0x80100098
+#define HW_DMA0_SGR1 0x801000a0
+#define HW_DMA0_DSR1 0x801000a8
+
+#define HW_DMA0_SAR2 0x801000b0
+#define HW_DMA0_DAR2 0x801000b8
+#define HW_DMA0_LLP2 0x801000c0
+#define HW_DMA0_CTL2 0x801000c8
+#define HW_DMA0_SSTAT2 0x801000d0
+#define HW_DMA0_DSTAT2 0x801000d8
+#define HW_DMA0_SSTATAR2 0x801000e0
+#define HW_DMA0_DSTATAR2 0x801000e8
+#define HW_DMA0_CFG2 0x801000f0
+#define HW_DMA0_SGR2 0x801000f8
+#define HW_DMA0_DSR2 0x80100100
+
+#define HW_DMA0_SAR3 0x80100108
+#define HW_DMA0_DAR3 0x80100110
+#define HW_DMA0_LLP3 0x80100118
+#define HW_DMA0_CTL3 0x80100120
+#define HW_DMA0_SSTAT3 0x80100128
+#define HW_DMA0_DSTAT3 0x80100130
+#define HW_DMA0_SSTATAR3 0x80100138
+#define HW_DMA0_DSTATAR3 0x80100140
+#define HW_DMA0_CFG3 0x80100148
+#define HW_DMA0_SGR3 0x80100150
+#define HW_DMA0_DSR3 0x80100158
+
+#define HW_DMA0_SAR4 0x80100160
+#define HW_DMA0_DAR4 0x80100168
+#define HW_DMA0_LLP4 0x80100170
+#define HW_DMA0_CTL4 0x80100178
+#define HW_DMA0_SSTAT4 0x80100180
+#define HW_DMA0_DSTAT4 0x80100188
+#define HW_DMA0_SSTATAR4 0x80100190
+#define HW_DMA0_DSTATAR4 0x80100198
+#define HW_DMA0_CFG4 0x801001a0
+#define HW_DMA0_SGR4 0x801001a8
+#define HW_DMA0_DSR4 0x801001b0
+
+#define HW_DMA0_SAR5 0x801001b8
+#define HW_DMA0_DAR5 0x801001c0
+#define HW_DMA0_LLP5 0x801001c8
+#define HW_DMA0_CTL5 0x801001d0
+#define HW_DMA0_SSTAT5 0x801001d8
+#define HW_DMA0_DSTAT5 0x801001e0
+#define HW_DMA0_SSTATAR5 0x801001e8
+#define HW_DMA0_DSTATAR5 0x801001f0
+#define HW_DMA0_CFG5 0x801001f8
+#define HW_DMA0_SGR5 0x80100200
+#define HW_DMA0_DSR5 0x80100208
+
+#define HW_DMA0_SAR6 0x80100210
+#define HW_DMA0_DAR6 0x80100218
+#define HW_DMA0_LLP6 0x80100220
+#define HW_DMA0_CTL6 0x80100228
+#define HW_DMA0_SSTAT6 0x80100230
+#define HW_DMA0_DSTAT6 0x80100238
+#define HW_DMA0_SSTATAR6 0x80100240
+#define HW_DMA0_DSTATAR6 0x80100248
+#define HW_DMA0_CFG6 0x80100250
+#define HW_DMA0_SGR6 0x80100258
+#define HW_DMA0_DSR6 0x80100260
+
+#define HW_DMA0_SAR7 0x80100268
+#define HW_DMA0_DAR7 0x80100270
+#define HW_DMA0_LLP7 0x80100278
+#define HW_DMA0_CTL7 0x80100280
+#define HW_DMA0_SSTAT7 0x80100288
+#define HW_DMA0_DSTAT7 0x80100290
+#define HW_DMA0_SSTATAR7 0x80100298
+#define HW_DMA0_DSTATAR7 0x801002a0
+#define HW_DMA0_CFG7 0x801002a8
+#define HW_DMA0_SGR7 0x801002b0
+#define HW_DMA0_DSR7 0x801002b8
+
+#define HW_DMA0_RawTFR 0x801002c0
+#define HW_DMA0_RawBLOCK 0x801002c8
+#define HW_DMA0_RawSRCTRAN 0x801002d0
+#define HW_DMA0_RawDSTTRAN 0x801002d8
+#define HW_DMA0_RawERR 0x801002e0
+
+#define HW_DMA0_StatusTFR 0x801002e8
+#define HW_DMA0_StatusBLOCK 0x801002f0
+#define HW_DMA0_StatusSRCTRAN 0x801002f8
+#define HW_DMA0_StatusDSTTRAN 0x80100300
+#define HW_DMA0_StatusERR 0x80100308
+
+#define HW_DMA0_MaskTFR 0x80100310
+#define HW_DMA0_MaskBLOCK 0x80100318
+#define HW_DMA0_MaskSRCTRAN 0x80100320
+#define HW_DMA0_MaskDSTTRAN 0x80100328
+#define HW_DMA0_MaskERR 0x80100330
+
+#define HW_DMA0_ClearTFR 0x80100338
+#define HW_DMA0_ClearBLOCK 0x80100340
+#define HW_DMA0_ClearSRCTRAN 0x80100348
+#define HW_DMA0_ClearDSTTRAN 0x80100350
+#define HW_DMA0_ClearERR 0x80100358
+
+#define HW_DMA0_STATUSINT 0x80100360
+
+#define HW_DMA0_ReqSrcReg 0x80100368
+#define HW_DMA0_ReqDstReg 0x80100370
+#define HW_DMA0_SglReqSrcReg 0x80100378
+#define HW_DMA0_SglReqDstReg 0x80100380
+#define HW_DMA0_LstSrcReg 0x80100388
+#define HW_DMA0_LstDstReg 0x80100390
+
+#define HW_DMA0_DMACFGREG 0x80100398
+#define HW_DMA0_CHENREG 0x801003a0
+
+////////////////////////////////////////////////////////////////////////////////
+// DMA1
+#define HW_DMA1_SAR0 0x80200000
+#define HW_DMA1_DAR0 0x80200008
+#define HW_DMA1_LLP0 0x80200010
+#define HW_DMA1_CTL0 0x80200018
+#define HW_DMA1_SSTAT0 0x80200020
+#define HW_DMA1_DSTAT0 0x80200028
+#define HW_DMA1_SSTATAR0 0x80200030
+#define HW_DMA1_DSTATAR0 0x80200038
+#define HW_DMA1_CFG0 0x80200040
+#define HW_DMA1_SGR0 0x80200048
+#define HW_DMA1_DSR0 0x80200050
+
+#define HW_DMA1_SAR1 0x80200058
+#define HW_DMA1_DAR1 0x80200060
+#define HW_DMA1_LLP1 0x80200068
+#define HW_DMA1_CTL1 0x80200070
+#define HW_DMA1_SSTAT1 0x80200078
+#define HW_DMA1_DSTAT1 0x80200080
+#define HW_DMA1_SSTATAR1 0x80200088
+#define HW_DMA1_DSTATAR1 0x80200090
+#define HW_DMA1_CFG1 0x80200098
+#define HW_DMA1_SGR1 0x802000a0
+#define HW_DMA1_DSR1 0x802000a8
+
+#define HW_DMA1_SAR2 0x802000b0
+#define HW_DMA1_DAR2 0x802000b8
+#define HW_DMA1_LLP2 0x802000c0
+#define HW_DMA1_CTL2 0x802000c8
+#define HW_DMA1_SSTAT2 0x802000d0
+#define HW_DMA1_DSTAT2 0x802000d8
+#define HW_DMA1_SSTATAR2 0x802000e0
+#define HW_DMA1_DSTATAR2 0x802000e8
+#define HW_DMA1_CFG2 0x802000f0
+#define HW_DMA1_SGR2 0x802000f8
+#define HW_DMA1_DSR2 0x80200100
+
+#define HW_DMA1_SAR3 0x80200108
+#define HW_DMA1_DAR3 0x80200110
+#define HW_DMA1_LLP3 0x80200118
+#define HW_DMA1_CTL3 0x80200120
+#define HW_DMA1_SSTAT3 0x80200128
+#define HW_DMA1_DSTAT3 0x80200130
+#define HW_DMA1_SSTATAR3 0x80200138
+#define HW_DMA1_DSTATAR3 0x80200140
+#define HW_DMA1_CFG3 0x80200148
+#define HW_DMA1_SGR3 0x80200150
+#define HW_DMA1_DSR3 0x80200158
+
+#define HW_DMA1_SAR4 0x80200160
+#define HW_DMA1_DAR4 0x80200168
+#define HW_DMA1_LLP4 0x80200170
+#define HW_DMA1_CTL4 0x80200178
+#define HW_DMA1_SSTAT4 0x80200180
+#define HW_DMA1_DSTAT4 0x80200188
+#define HW_DMA1_SSTATAR4 0x80200190
+#define HW_DMA1_DSTATAR4 0x80200198
+#define HW_DMA1_CFG4 0x802001a0
+#define HW_DMA1_SGR4 0x802001a8
+#define HW_DMA1_DSR4 0x802001b0
+
+#define HW_DMA1_SAR5 0x802001b8
+#define HW_DMA1_DAR5 0x802001c0
+#define HW_DMA1_LLP5 0x802001c8
+#define HW_DMA1_CTL5 0x802001d0
+#define HW_DMA1_SSTAT5 0x802001d8
+#define HW_DMA1_DSTAT5 0x802001e0
+#define HW_DMA1_SSTATAR5 0x802001e8
+#define HW_DMA1_DSTATAR5 0x802001f0
+#define HW_DMA1_CFG5 0x802001f8
+#define HW_DMA1_SGR5 0x80200200
+#define HW_DMA1_DSR5 0x80200208
+
+#define HW_DMA1_SAR6 0x80200210
+#define HW_DMA1_DAR6 0x80200218
+#define HW_DMA1_LLP6 0x80200220
+#define HW_DMA1_CTL6 0x80200228
+#define HW_DMA1_SSTAT6 0x80200230
+#define HW_DMA1_DSTAT6 0x80200238
+#define HW_DMA1_SSTATAR6 0x80200240
+#define HW_DMA1_DSTATAR6 0x80200248
+#define HW_DMA1_CFG6 0x80200250
+#define HW_DMA1_SGR6 0x80200258
+#define HW_DMA1_DSR6 0x80200260
+
+#define HW_DMA1_SAR7 0x80200268
+#define HW_DMA1_DAR7 0x80200270
+#define HW_DMA1_LLP7 0x80200278
+#define HW_DMA1_CTL7 0x80200280
+#define HW_DMA1_SSTAT7 0x80200288
+#define HW_DMA1_DSTAT7 0x80200290
+#define HW_DMA1_SSTATAR7 0x80200298
+#define HW_DMA1_DSTATAR7 0x802002a0
+#define HW_DMA1_CFG7 0x802002a8
+#define HW_DMA1_SGR7 0x802002b0
+#define HW_DMA1_DSR7 0x802002b8
+
+#define HW_DMA1_RawTFR 0x802002c0
+#define HW_DMA1_RawBLOCK 0x802002c8
+#define HW_DMA1_RawSRCTRAN 0x802002d0
+#define HW_DMA1_RawDSTTRAN 0x802002d8
+#define HW_DMA1_RawERR 0x802002e0
+
+#define HW_DMA1_StatusTFR 0x802002e8
+#define HW_DMA1_StatusBLOCK 0x802002f0
+#define HW_DMA1_StatusSRCTRAN 0x802002f8
+#define HW_DMA1_StatusDSTTRAN 0x80200300
+#define HW_DMA1_StatusERR 0x80200308
+
+#define HW_DMA1_MaskTFR 0x80200310
+#define HW_DMA1_MaskBLOCK 0x80200318
+#define HW_DMA1_MaskSRCTRAN 0x80200320
+#define HW_DMA1_MaskDSTTRAN 0x80200328
+#define HW_DMA1_MaskERR 0x80200330
+
+#define HW_DMA1_ClearTFR 0x80200338
+#define HW_DMA1_ClearBLOCK 0x80200340
+#define HW_DMA1_ClearSRCTRAN 0x80200348
+#define HW_DMA1_ClearDSTTRAN 0x80200350
+#define HW_DMA1_ClearERR 0x80200358
+
+#define HW_DMA1_STATUSINT 0x80200360
+
+#define HW_DMA1_ReqSrcReg 0x80200368
+#define HW_DMA1_ReqDstReg 0x80200370
+#define HW_DMA1_SglReqSrcReg 0x80200378
+#define HW_DMA1_SglReqDstReg 0x80200380
+#define HW_DMA1_LstSrcReg 0x80200388
+#define HW_DMA1_LstDstReg 0x80200390
+
+#define HW_DMA1_DMACFGREG 0x80200398
+#define HW_DMA1_CHENREG 0x802003a0
+
+////////////////////////////////////////////////////////////////////////////////
+// ICOLL
+#define HW_ICOLL_VECTOR 0x80054000
+#define HW_ICOLL_LEVELACK 0x80054010
+#define HW_ICOLL_CTRL 0x80054020
+#define HW_ICOLL_STAT 0x80054030
+#define HW_ICOLL_RAW0 0x80054040
+#define HW_ICOLL_RAW1 0x80054050
+#define HW_ICOLL_PRIORITY0 0x80054060
+#define HW_ICOLL_PRIORITY1 0x80054070
+#define HW_ICOLL_PRIORITY2 0x80054080
+#define HW_ICOLL_PRIORITY3 0x80054090
+#define HW_ICOLL_PRIORITY4 0x800540A0
+#define HW_ICOLL_PRIORITY5 0x800540B0
+#define HW_ICOLL_PRIORITY6 0x800540C0
+#define HW_ICOLL_PRIORITY7 0x800540D0
+#define HW_ICOLL_PRIORITY8 0x800540E0
+#define HW_ICOLL_PRIORITY9 0x800540F0
+#define HW_ICOLL_PRIORITY10 0x80054100
+#define HW_ICOLL_PRIORITY11 0x80054110
+#define HW_ICOLL_PRIORITY12 0x80054120
+#define HW_ICOLL_PRIORITY13 0x80054130
+#define HW_ICOLL_PRIORITY14 0x80054140
+#define HW_ICOLL_PRIORITY15 0x80054150
+#define HW_ICOLL_VBASE 0x80054160
+#define HW_ICOLL_DEBUG 0x80054170
+#define HW_ICOLL_DBGREAD0 0x80054180
+#define HW_ICOLL_DBGREAD1 0x80054190
+#define HW_ICOLL_DBGFLAG 0x800541A0
+#define HW_ICOLL_DBGREQUEST0 0x800541B0
+#define HW_ICOLL_DBGREQUEST1 0x800541C0
+#define HW_ICOLL_CLEAR0 0x800541D0
+#define HW_ICOLL_CLEAR1 0x800541E0
+#define HW_ICOLL_UNDEF_VECTOR 0x800541F0
+
+////////////////////////////////////////////////////////////////////////////////
+// TIMER0
+#define HW_TIMER0_IR 0x80088000
+#define HW_TIMER0_TCR 0x80088010
+#define HW_TIMER0_DIR 0x80088020
+#define HW_TIMER0_TC0 0x80088030
+#define HW_TIMER0_TC1 0x80088040
+#define HW_TIMER0_TC2 0x80088050
+#define HW_TIMER0_TC3 0x80088060
+#define HW_TIMER0_PR 0x80088070
+#define HW_TIMER0_PC 0x80088080
+#define HW_TIMER0_MCR 0x80088090
+#define HW_TIMER0_MR0 0x800880a0
+#define HW_TIMER0_MR1 0x800880b0
+#define HW_TIMER0_MR2 0x800880C0
+#define HW_TIMER0_MR3 0x800880D0
+#define HW_TIMER0_CCR 0x800880E0
+#define HW_TIMER0_CR0 0x800880F0
+#define HW_TIMER0_CR1 0x80088100
+#define HW_TIMER0_CR2 0x80088110
+#define HW_TIMER0_CR3 0x80088120
+#define HW_TIMER0_EMR 0x80088130
+#define HW_TIMER0_PWMTH0 0x80088140
+#define HW_TIMER0_PWMTH1 0x80088150
+#define HW_TIMER0_PWMTH2 0x80088160
+#define HW_TIMER0_PWMTH3 0x80088170
+#define HW_TIMER0_CTCR 0x80088180
+#define HW_TIMER0_PWMC 0x80088190
+
+////////////////////////////////////////////////////////////////////////////////
+// USART
+
+typedef struct {
+ __IO unsigned long CTRL0[4];
+ __IO unsigned long CTRL1[4];
+ __IO unsigned long CTRL2[4];
+ __IO unsigned long LINECTRL[4];
+ __IO unsigned long INTR[4];
+ __IO unsigned long DATA[4];
+ __IO unsigned long STAT[4];
+ __I unsigned long DEBUG[4];
+ __IO unsigned long ILPR[4];
+ __IO unsigned long RS485CTRL[4];
+ __IO unsigned long RS485ADRMATCH[4];
+ __IO unsigned long RS485DLY[4];
+ __IO unsigned long AUTOBAUD[4];
+ __IO unsigned long CTRL3[4];
+} ASM_USART_TypeDef;
+
+#define UART0_BASE 0x80000000
+#define UART1_BASE 0x80004000
+#define UART2_BASE 0x80008000
+#define UART3_BASE 0x8000C000
+#define UART4_BASE 0x80010000
+#define UART5_BASE 0x80014000
+#define UART6_BASE 0x80018000
+#define UART7_BASE 0x8001C000
+#define UART8_BASE 0x80020000
+#define UART9_BASE 0x80024000
+
+////////////////////////////////////////////////////////////////////////////////
+// MAC
+#define HW_ETH_BASE_ADDR 0x80500000
+#define HW_ETH_MACCR (HW_ETH_BASE_ADDR + 0x0000)
+#define HW_ETH_MACFFR (HW_ETH_BASE_ADDR + 0x0004)
+#define HW_ETH_MACHTHR (HW_ETH_BASE_ADDR + 0x0008)
+#define HW_ETH_MACHTLR (HW_ETH_BASE_ADDR + 0x000C)
+#define HW_ETH_MACMIIAR (HW_ETH_BASE_ADDR + 0x0010)
+#define HW_ETH_MACMIIDR (HW_ETH_BASE_ADDR + 0x0014)
+#define HW_ETH_MACFCR (HW_ETH_BASE_ADDR + 0x0018)
+#define HW_ETH_MACVLANTR (HW_ETH_BASE_ADDR + 0x001C)
+#define HW_ETH_MACVR (HW_ETH_BASE_ADDR + 0x0020)
+#define HW_ETH_MACRWUFFR (HW_ETH_BASE_ADDR + 0x0028)
+#define HW_ETH_MACPMTCSR (HW_ETH_BASE_ADDR + 0x002C)
+#define HW_ETH_MACDBGR (HW_ETH_BASE_ADDR + 0x0034)
+#define HW_ETH_MACISR (HW_ETH_BASE_ADDR + 0x0038)
+#define HW_ETH_MACIMR (HW_ETH_BASE_ADDR + 0x003C)
+#define HW_ETH_MACA0HR (HW_ETH_BASE_ADDR + 0x0040)
+#define HW_ETH_MACA0LR (HW_ETH_BASE_ADDR + 0x0044)
+#define HW_ETH_MACA1HR (HW_ETH_BASE_ADDR + 0x0048)
+#define HW_ETH_MACA1LR (HW_ETH_BASE_ADDR + 0x004C)
+#define HW_ETH_MACA2HR (HW_ETH_BASE_ADDR + 0x0050)
+#define HW_ETH_MACA2LR (HW_ETH_BASE_ADDR + 0x0054)
+#define HW_ETH_MACA3HR (HW_ETH_BASE_ADDR + 0x0058)
+#define HW_ETH_MACA3LR (HW_ETH_BASE_ADDR + 0x005C)
+#define HW_ETH_MACA4HR (HW_ETH_BASE_ADDR + 0x0060)
+#define HW_ETH_MACA4LR (HW_ETH_BASE_ADDR + 0x0064)
+#define HW_ETH_MMCCR (HW_ETH_BASE_ADDR + 0x0100)
+#define HW_ETH_MMCRIR (HW_ETH_BASE_ADDR + 0x0104)
+#define HW_ETH_MMCTIR (HW_ETH_BASE_ADDR + 0x0108)
+#define HW_ETH_MMCRIMR (HW_ETH_BASE_ADDR + 0x010C)
+#define HW_ETH_MMCTIMR (HW_ETH_BASE_ADDR + 0x0110)
+#define HW_ETH_MMCTGFSCCR (HW_ETH_BASE_ADDR + 0x014C)
+#define HW_ETH_MMCTGFMSCCR (HW_ETH_BASE_ADDR + 0x0150)
+#define HW_ETH_MMCTGFCR (HW_ETH_BASE_ADDR + 0x0168)
+#define HW_ETH_MMCRFCECR (HW_ETH_BASE_ADDR + 0x0194)
+#define HW_ETH_MMCRFAECR (HW_ETH_BASE_ADDR + 0x0198)
+#define HW_ETH_MMCRGUFCR (HW_ETH_BASE_ADDR + 0x01C4)
+#define HW_ETH_PTPTSCR (HW_ETH_BASE_ADDR + 0x0700)
+#define HW_ETH_PTPSSIR (HW_ETH_BASE_ADDR + 0x0704)
+#define HW_ETH_PTPTSHR (HW_ETH_BASE_ADDR + 0x0708)
+#define HW_ETH_PTPTSLR (HW_ETH_BASE_ADDR + 0x070C)
+#define HW_ETH_PTPTSHUR (HW_ETH_BASE_ADDR + 0x0710)
+#define HW_ETH_PTPTSLUR (HW_ETH_BASE_ADDR + 0x0714)
+#define HW_ETH_PTPTSAR (HW_ETH_BASE_ADDR + 0x0718)
+#define HW_ETH_PTPTTHR (HW_ETH_BASE_ADDR + 0x071C)
+#define HW_ETH_PTPTTLR (HW_ETH_BASE_ADDR + 0x0720)
+#define HW_ETH_PTPTSSR (HW_ETH_BASE_ADDR + 0x0728)
+#define HW_ETH_PTPPPSCR (HW_ETH_BASE_ADDR + 0x072C)
+#define HW_ETH_DMABMR (HW_ETH_BASE_ADDR + 0x1000)
+#define HW_ETH_DMATPDR (HW_ETH_BASE_ADDR + 0x1004)
+#define HW_ETH_DMARPDR (HW_ETH_BASE_ADDR + 0x1008)
+#define HW_ETH_DMARDLAR (HW_ETH_BASE_ADDR + 0x100C)
+#define HW_ETH_DMATDLAR (HW_ETH_BASE_ADDR + 0x1010)
+#define HW_ETH_DMASR (HW_ETH_BASE_ADDR + 0x1014)
+#define HW_ETH_DMAOMR (HW_ETH_BASE_ADDR + 0x1018)
+#define HW_ETH_DMAIER (HW_ETH_BASE_ADDR + 0x101C)
+#define HW_ETH_DMAMFBOCR (HW_ETH_BASE_ADDR + 0x1020)
+#define HW_ETH_DMARSWTR (HW_ETH_BASE_ADDR + 0x1024)
+#define HW_ETH_DMACHTDR (HW_ETH_BASE_ADDR + 0x1048)
+#define HW_ETH_DMACHRDR (HW_ETH_BASE_ADDR + 0x104C)
+#define HW_ETH_DMACHTBAR (HW_ETH_BASE_ADDR + 0x1050)
+#define HW_ETH_DMACHRBAR (HW_ETH_BASE_ADDR + 0x1054)
+
+////////////////////////////////////////////////////////////////////////////////
+#endif /* __ASM9260T_REGS_H__ */
+
diff --git a/bsp/asm9260t/platform/gpio.c b/bsp/asm9260t/platform/gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a341dcdf57b27f73e889fe47c85c15eb52e74a3
--- /dev/null
+++ b/bsp/asm9260t/platform/gpio.c
@@ -0,0 +1,62 @@
+/*
+ * File : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+
+#include "asm9260t.h"
+#include "rtthread.h"
+
+void HW_SetPinMux(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t mux_type)
+{
+ rt_uint32_t addr = HW_IOCON(port, pin);
+ rt_uint32_t val = inl(addr); // read origin value
+
+ val &= ~7UL; // clear MUX field
+ val |= mux_type; // set MUX field with new value
+
+ outl(val ,addr); // Set new value
+}
+
+void HW_GpioSetDir(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t isOut)
+{
+ rt_uint32_t addr = HW_GPIO_DATA_BASE | ((port>>2)<<16) | 0x8000;
+ rt_uint32_t val;
+ addr = isOut? REG_SET(addr) : REG_CLR(addr);
+ val = (1 << ((port%4)*8+pin));
+ outl(val, addr);
+}
+
+void HW_GpioSetVal(rt_uint8_t port, rt_uint8_t pin)
+{
+ rt_uint32_t addr, val;
+ addr = REG_SET(HW_GPIO_DATA_BASE | ((port>>2)<<16));
+ val = (1 << ((port%4)*8+pin));
+ outl(val, addr);
+}
+
+void HW_GpioClrVal(rt_uint8_t port, rt_uint8_t pin)
+{
+ rt_uint32_t addr, val;
+ addr = REG_CLR(HW_GPIO_DATA_BASE | ((port>>2)<<16));
+ val = (1 << ((port%4)*8+pin));
+ outl(val, addr);
+}
diff --git a/bsp/asm9260t/platform/gpio.h b/bsp/asm9260t/platform/gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..26fccff47767aef72f8404547febe0ae09389b1f
--- /dev/null
+++ b/bsp/asm9260t/platform/gpio.h
@@ -0,0 +1,31 @@
+/*
+ * File : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+extern void HW_SetPinMux(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t mux_type);
+extern void HW_GpioSetDir(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t isOut);
+extern void HW_GpioSetVal(rt_uint8_t port, rt_uint8_t pin);
+extern void HW_GpioClrVal(rt_uint8_t port, rt_uint8_t pin);
+#endif
diff --git a/bsp/asm9260t/platform/interrupt.c b/bsp/asm9260t/platform/interrupt.c
new file mode 100644
index 0000000000000000000000000000000000000000..20b8b62e00585b3788a25bb11f10163e9429b1a3
--- /dev/null
+++ b/bsp/asm9260t/platform/interrupt.c
@@ -0,0 +1,221 @@
+/*
+ * File : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
+ */
+
+#include
+#include "asm9260t.h"
+#include "interrupt.h"
+
+#define MAX_HANDLERS (64)
+
+extern rt_uint32_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+
+/* --------------------------------------------------------------------
+ * Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 3 = highest).
+ */
+static rt_uint32_t default_irq_priority[MAX_HANDLERS/4] =
+{
+ 0x00000000UL, /* INT3 - INT0 */
+ 0x00000000UL, /* INT7 - INT4 */
+ 0x00000000UL, /* INT11 - INT8 */
+ 0x02000000UL, /* INT15 - INT12 */
+ 0x02020202UL, /* INT19 - INT16 */
+ 0x02020202UL, /* INT23 - INT20 */
+ 0x00000002UL, /* INT27 - INT24 */
+ 0x01010100UL, /* INT31 - INT28 */
+ 0x00000001UL, /* INT35 - INT32 */
+ 0x00000000UL, /* INT39 - INT36 */
+ 0x00000000UL, /* INT43 - INT40 */
+ 0x00000000UL, /* INT47 - INT44 */
+ 0x00000000UL, /* INT51 - INT48 */
+ 0x00000000UL, /* INT55 - INT52 */
+ 0x00000000UL, /* INT59 - INT56 */
+ 0x00000000UL, /* INT63 - INT60 */
+};
+
+
+void rt_hw_interrupt_mask(int irq);
+void rt_hw_interrupt_umask(int irq);
+
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
+{
+ rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
+ return RT_NULL;
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+ register rt_uint32_t idx;
+ /* Initialize the ICOLL interrupt controller */
+ outl((1<<8), REG_SET(HW_AHBCLKCTRL1)); // Enable ICOLL clock
+ outl((1<<8), REG_CLR(HW_PRESETCTRL1)); // Reset ICOLL start
+ outl((1<<8), REG_SET(HW_PRESETCTRL1)); // Reset ICOLL stop
+
+ for(idx = 0; idx < (MAX_HANDLERS/4); idx++)
+ {
+ rt_uint32_t reg = (HW_ICOLL_PRIORITY0 + 0x10*idx);
+ outl(default_irq_priority[idx], REG_VAL(reg));
+ }
+
+ /* init exceptions table */
+ for(idx=0; idx < MAX_HANDLERS; idx++)
+ {
+ irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+ irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+ rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+ irq_desc[idx].counter = 0;
+#endif
+ }
+
+ /* init interrupt nest, and context in thread sp */
+ rt_interrupt_nest = 0;
+ rt_interrupt_from_thread = 0;
+ rt_interrupt_to_thread = 0;
+ rt_thread_switch_interrupt_flag = 0;
+
+ outl(0x00000000, REG_CLR(HW_ICOLL_VBASE)); //todo: fix this bug
+
+ outl(0x00020000, REG_CLR(HW_ICOLL_CTRL)); // Clear CTRL REG
+ outl(0x00050000, REG_SET(HW_ICOLL_CTRL));
+ outl(0x00000004, HW_ICOLL_UNDEF_VECTOR);
+ outl(~0UL, REG_CLR(HW_ICOLL_CLEAR0));
+ outl(~0UL, REG_CLR(HW_ICOLL_CLEAR1));
+}
+
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int irq)
+{
+ rt_uint32_t reg = HW_ICOLL_PRIORITY0 + ((irq & 0x3CUL) << 2);
+ rt_uint32_t bit = 4UL << ((irq & 3UL)<<3);
+ outl(bit, REG_CLR(reg));
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int irq)
+{
+ rt_uint32_t reg = HW_ICOLL_PRIORITY0 + ((irq & 0x3CUL) << 2);
+ rt_uint32_t bit = 4UL << ((irq & 3UL)<<3);
+ outl(bit, REG_SET(reg));
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param handler the interrupt service routine to be installed
+ * @param param the interrupt service function parameter
+ * @param name the interrupt name
+ * @return old handler
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+ void *param, char *name)
+{
+ rt_isr_handler_t old_handler = RT_NULL;
+
+ if(vector < MAX_HANDLERS)
+ {
+ old_handler = irq_desc[vector].handler;
+ if (handler != RT_NULL)
+ {
+ irq_desc[vector].handler = (rt_isr_handler_t)handler;
+ irq_desc[vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+ rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+ irq_desc[vector].counter = 0;
+#endif
+ }
+ }
+
+ return old_handler;
+}
+
+
+
+rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
+{
+ //volatile rt_uint32_t irqstat;
+ rt_uint32_t id;
+ /* AIC need this dummy read */
+ inl(HW_ICOLL_VECTOR);
+ /* get irq number */
+ id = inl(HW_ICOLL_STAT);
+ /* clear pending register */
+ //irqstat = inl(HW_ICOLL_VECTOR);
+ return id;
+}
+
+void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
+{
+ rt_uint32_t reg = HW_ICOLL_PRIORITY0 + ((id & 0x3CUL) << 2);
+ rt_uint32_t level = 1UL << (0x3 & (inl(REG_VAL(reg)) >>((id & 3UL)<<3)));
+
+ if(id & 0x20)
+ outl((1UL<<(id&0x1F)), REG_SET(HW_ICOLL_CLEAR1));
+ else
+ outl((1UL<
+FINSH_FUNCTION_EXPORT(list_irq, list system irq);
+
+#endif
diff --git a/bsp/asm9260t/platform/interrupt.h b/bsp/asm9260t/platform/interrupt.h
new file mode 100644
index 0000000000000000000000000000000000000000..85aa48f3713a0d82a03782910e6109a88b25e170
--- /dev/null
+++ b/bsp/asm9260t/platform/interrupt.h
@@ -0,0 +1,97 @@
+/*
+ * File : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#define INT_IRQ 0x00
+#define INT_FIQ 0x01
+
+
+// IRQ Source
+#define INT_ARM_COMMRX 0
+#define INT_ARM_COMMTX 1
+#define INT_RTC 2
+#define INT_GPIO0 3
+#define INT_GPIO1 4
+#define INT_GPIO2 5
+#define INT_GPIO3 6
+#define INT_GPIO4_IIS1 7
+#define INT_USB0 8
+#define INT_USB1 9
+#define INT_USB0_DMA 10
+#define INT_USB1_DMA 11
+#define INT_MAC 12
+#define INT_MAC_PMT 13
+#define INT_NAND 14
+#define INT_UART0 15
+#define INT_UART1 16
+#define INT_UART2 17
+#define INT_UART3 18
+#define INT_UART4 19
+#define INT_UART5 20
+#define INT_UART6 21
+#define INT_UART7 22
+#define INT_UART8 23
+#define INT_UART9 24
+#define INT_I2S0 25
+#define INT_I2C0 26
+#define INT_I2C1 27
+#define INT_CAMIF 28
+#define INT_TIMER0 29
+#define INT_TIMER1 30
+#define INT_TIMER2 31
+#define INT_TIMER3 32
+#define INT_ADC0 33
+#define INT_DAC0 34
+#define INT_USB0_RESUME_HOSTDISCONNECT 35
+#define INT_USB0_VBUSVALID 36
+#define INT_USB1_RESUME_HOSTDISCONNECT 37
+#define INT_USB1_VBUSVALID 38
+#define INT_DMA0_CH0 39
+#define INT_DMA0_CH1 40
+#define INT_DMA0_CH2 41
+#define INT_DMA0_CH3 42
+#define INT_DMA0_CH4 43
+#define INT_DMA0_CH5 44
+#define INT_DMA0_CH6 45
+#define INT_DMA0_CH7 46
+#define INT_DMA1_CH0 47
+#define INT_DMA1_CH1 48
+#define INT_DMA1_CH2 49
+#define INT_DMA1_CH3 50
+#define INT_DMA1_CH4 51
+#define INT_DMA1_CH5 52
+#define INT_DMA1_CH6 53
+#define INT_DMA1_CH7 54
+#define INT_WATCHDOG 55
+#define INT_CAN0 56
+#define INT_CAN1 57
+#define INT_QEI 58
+#define INT_MCPWM 59
+#define INT_SPI0 60
+#define INT_SPI1 61
+#define INT_QUADSPI0 62
+#define INT_SSP0 63
+
+#endif
diff --git a/bsp/asm9260t/platform/reset.c b/bsp/asm9260t/platform/reset.c
new file mode 100644
index 0000000000000000000000000000000000000000..2f5adc62312bb61239e03a37888d483137c55e8e
--- /dev/null
+++ b/bsp/asm9260t/platform/reset.c
@@ -0,0 +1,37 @@
+/*
+ * File : reset.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety modified from mini2440
+ * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
+ */
+
+#include
+
+void machine_reset(void)
+{
+
+}
+
+void machine_shutdown(void)
+{
+
+}
+
diff --git a/bsp/asm9260t/platform/rt_low_level_gcc.inc b/bsp/asm9260t/platform/rt_low_level_gcc.inc
new file mode 100644
index 0000000000000000000000000000000000000000..c6edd3787ccc5d21cacdee921878b1a8e8c7aae3
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_gcc.inc
@@ -0,0 +1,31 @@
+/*
+ * File : rt_low_level_gcc.inc
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+
+/*--------- Stack size of CPU modes ------------------------------------------*/
+.equ UND_STK_SIZE, 2048
+.equ SVC_STK_SIZE, 4096
+.equ ABT_STK_SIZE, 2048
+.equ IRQ_STK_SIZE, 4096
+.equ FIQ_STK_SIZE, 4096
+.equ SYS_STK_SIZE, 2048
diff --git a/bsp/asm9260t/platform/rt_low_level_iar.inc b/bsp/asm9260t/platform/rt_low_level_iar.inc
new file mode 100644
index 0000000000000000000000000000000000000000..3046253d0727168c37e47eb96dd3cc357187befa
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_iar.inc
@@ -0,0 +1,31 @@
+/*
+ * File : rt_low_level_iar.inc
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+
+/*-------- Stack size of CPU modes -------------------------------------------*/
+#define UND_STK_SIZE 512
+#define SVC_STK_SIZE 4096
+#define ABT_STK_SIZE 512
+#define IRQ_STK_SIZE 1024
+#define FIQ_STK_SIZE 1024
+#define SYS_STK_SIZE 512
diff --git a/bsp/asm9260t/platform/rt_low_level_init.c b/bsp/asm9260t/platform/rt_low_level_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..926c1af6fa87677c4c1dc49c06a68f0cb0f81e34
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_init.c
@@ -0,0 +1,30 @@
+/*
+ * File : rt_low_level_init.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
+ */
+
+void rt_low_level_init(void)
+{
+
+}
+
diff --git a/bsp/asm9260t/platform/rt_low_level_keil.inc b/bsp/asm9260t/platform/rt_low_level_keil.inc
new file mode 100644
index 0000000000000000000000000000000000000000..c3cde15ded56bb7220c4bc68572c85216c04462d
--- /dev/null
+++ b/bsp/asm9260t/platform/rt_low_level_keil.inc
@@ -0,0 +1,32 @@
+;/*
+; * File : rt_low_level_keil.inc
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+; *
+; * This program is free software; you can redistribute it and/or modify
+; * it under the terms of the GNU General Public License as published by
+; * the Free Software Foundation; either version 2 of the License, or
+; * (at your option) any later version.
+; *
+; * This program is distributed in the hope that it will be useful,
+; * but WITHOUT ANY WARRANTY; without even the implied warranty of
+; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; * GNU General Public License for more details.
+; *
+; * You should have received a copy of the GNU General Public License along
+; * with this program; if not, write to the Free Software Foundation, Inc.,
+; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2015-04-14 ArdaFu first version
+; */
+
+;/*-------- Stack size of CPU modes ------------------------------------------*/
+UND_STK_SIZE EQU 512
+SVC_STK_SIZE EQU 4096
+ABT_STK_SIZE EQU 512
+IRQ_STK_SIZE EQU 1024
+FIQ_STK_SIZE EQU 1024
+SYS_STK_SIZE EQU 512
+ END
diff --git a/bsp/asm9260t/platform/system_clock.c b/bsp/asm9260t/platform/system_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..e51cf7c892f3cc18d239751e4a85191abee55df8
--- /dev/null
+++ b/bsp/asm9260t/platform/system_clock.c
@@ -0,0 +1,303 @@
+/*
+ * File : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-01-13 weety first version
+ */
+
+#include
+
+/*
+static rt_list_t clocks;
+
+struct clk {
+ char name[32];
+ rt_uint32_t rate_hz;
+ struct clk *parent;
+ rt_list_t node;
+};
+
+static struct clk clk32k = {
+ "clk32k",
+ AT91_SLOW_CLOCK,
+ RT_NULL,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk main_clk = {
+ "main",
+ 0,
+ RT_NULL,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk plla = {
+ "plla",
+ 0,
+ RT_NULL,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk mck = {
+ "mck",
+ 0,
+ RT_NULL,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk uhpck = {
+ "uhpck",
+ 0,
+ RT_NULL,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk pllb = {
+ "pllb",
+ 0,
+ &main_clk,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk udpck = {
+ "udpck",
+ 0,
+ &pllb,
+ {RT_NULL, RT_NULL},
+};
+
+static struct clk *const standard_pmc_clocks[] = {
+ // four primary clocks
+ &clk32k,
+ &main_clk,
+ &plla,
+
+ // MCK
+ &mck
+};
+
+// clocks cannot be de-registered no refcounting necessary
+struct clk *clk_get(const char *id)
+{
+ struct clk *clk;
+ rt_list_t *list;
+
+ for (list = (&clocks)->next; list != &clocks; list = list->next)
+ {
+ clk = (struct clk *)rt_list_entry(list, struct clk, node);
+ if (rt_strcmp(id, clk->name) == 0)
+ return clk;
+ }
+
+ return RT_NULL;
+}
+
+rt_uint32_t clk_get_rate(struct clk *clk)
+{
+ rt_uint32_t rate;
+
+ for (;;) {
+ rate = clk->rate_hz;
+ if (rate || !clk->parent)
+ break;
+ clk = clk->parent;
+ }
+ return rate;
+}
+
+static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
+{
+ unsigned mul, div;
+
+ div = reg & 0xff;
+ mul = (reg >> 16) & 0x7ff;
+ if (div && mul) {
+ freq /= div;
+ freq *= mul + 1;
+ } else
+ freq = 0;
+
+ return freq;
+}
+
+static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
+{
+ unsigned i, div = 0, mul = 0, diff = 1 << 30;
+ unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+ //PLL output max 240 MHz (or 180 MHz per errata)
+ if (out_freq > 240000000)
+ goto fail;
+
+ for (i = 1; i < 256; i++) {
+ int diff1;
+ unsigned input, mul1;
+
+ //
+ // PLL input between 1MHz and 32MHz per spec, but lower
+ // frequences seem necessary in some cases so allow 100K.
+ // Warning: some newer products need 2MHz min.
+ //
+ input = main_freq / i;
+ if (input < 100000)
+ continue;
+ if (input > 32000000)
+ continue;
+
+ mul1 = out_freq / input;
+ if (mul1 > 2048)
+ continue;
+ if (mul1 < 2)
+ goto fail;
+
+ diff1 = out_freq - input * mul1;
+ if (diff1 < 0)
+ diff1 = -diff1;
+ if (diff > diff1) {
+ diff = diff1;
+ div = i;
+ mul = mul1;
+ if (diff == 0)
+ break;
+ }
+ }
+ if (i == 256 && diff > (out_freq >> 5))
+ goto fail;
+ return ret | ((mul - 1) << 16) | div;
+fail:
+ return 0;
+}
+
+static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
+{
+ if (pll == &pllb && (reg & AT91_PMC_USB96M))
+ return freq / 2;
+ else
+ return freq;
+}
+
+
+// PLLB generated USB full speed clock init
+static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
+{
+ rt_uint32_t at91_pllb_usb_init;
+ //
+ // USB clock init: choose 48 MHz PLLB value,
+ // disable 48MHz clock during usb peripheral suspend.
+ //
+ // REVISIT: assumes MCK doesn't derive from PLLB!
+ //
+ uhpck.parent = &pllb;
+
+ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+ pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+
+ at91_sys_write(AT91_CKGR_PLLBR, 0);
+
+ udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+ uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+}
+
+static struct clk *at91_css_to_clk(unsigned long css)
+{
+ switch (css) {
+ case AT91_PMC_CSS_SLOW:
+ return &clk32k;
+ case AT91_PMC_CSS_MAIN:
+ return &main_clk;
+ case AT91_PMC_CSS_PLLA:
+ return &plla;
+ case AT91_PMC_CSS_PLLB:
+ return &pllb;
+ }
+
+ return RT_NULL;
+}
+
+#define false 0
+#define true 1
+int at91_clock_init(rt_uint32_t main_clock)
+{
+ unsigned tmp, freq, mckr;
+ int i;
+ int pll_overclock = false;
+
+ //
+ // When the bootloader initialized the main oscillator correctly,
+ // there's no problem using the cycle counter. But if it didn't,
+ // or when using oscillator bypass mode, we must be told the speed
+ // of the main clock.
+ //
+ if (!main_clock) {
+ do {
+ tmp = at91_sys_read(AT91_CKGR_MCFR);
+ } while (!(tmp & AT91_PMC_MAINRDY));
+ main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+ }
+ main_clk.rate_hz = main_clock;
+
+ // report if PLLA is more than mildly overclocked
+ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+ if (plla.rate_hz > 209000000)
+ pll_overclock = true;
+ if (pll_overclock)
+ ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+
+ at91_pllb_usbfs_clock_init(main_clock);
+
+ //
+ // MCK and CPU derive from one of those primary clocks.
+ // For now, assume this parentage won't change.
+ //
+ mckr = at91_sys_read(AT91_PMC_MCKR);
+ mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+ freq = mck.parent->rate_hz;
+ freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale
+
+ mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv
+
+ // Register the PMC's standard clocks
+ rt_list_init(&clocks);
+ for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+ rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+ rt_list_insert_after(&clocks, &pllb.node);
+ rt_list_insert_after(&clocks, &uhpck.node);
+ rt_list_insert_after(&clocks, &udpck.node);
+
+ // MCK and CPU clock are "always on"
+ //clk_enable(&mck);
+
+ //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+ // freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+ // (unsigned) main_clock / 1000000,
+ // ((unsigned) main_clock % 1000000) / 1000); //cause blocked
+
+ return 0;
+}
+*/
+
+ // @brief System Clock Configuration
+
+void rt_hw_clock_init(void)
+{
+ //at91_clock_init(18432000);
+}
+
diff --git a/bsp/asm9260t/platform/timer0.c b/bsp/asm9260t/platform/timer0.c
new file mode 100644
index 0000000000000000000000000000000000000000..cccbed9e574a839e2e943420d2f63e899a720fd6
--- /dev/null
+++ b/bsp/asm9260t/platform/timer0.c
@@ -0,0 +1,55 @@
+/*
+ * File : timer0.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-29 ArdaFu first version
+ */
+
+#include "timer0.h"
+#include "asm9260t.h"
+#include "rtthread.h"
+void hw_timer0_init(void)
+{
+ uint32_t pclk;
+
+ // enable timer0's clock, reset timer0
+ outl((1<<4), REG_SET(HW_AHBCLKCTRL1));
+ outl((1<<4), REG_CLR(HW_PRESETCTRL1));
+ outl((1<<4), REG_SET(HW_PRESETCTRL1));
+
+ outl((1<<0), REG_CLR(HW_TIMER0_TCR));
+
+ outl((3<<0), REG_CLR(HW_TIMER0_CTCR));
+
+ outl((3<<0), REG_CLR(HW_TIMER0_DIR));
+
+ outl(0, REG_CLR(HW_TIMER0_PR));
+ outl(0, REG_CLR(HW_TIMER0_PC));
+
+ outl((7<<0), REG_CLR(HW_TIMER0_MCR));
+ outl((3<<0), REG_SET(HW_TIMER0_MCR));
+
+ pclk = (inl(HW_SYSPLLCTRL)&0x1FF)*1000000u/4u;
+ outl(pclk/RT_TICK_PER_SECOND, HW_TIMER0_MR0);
+
+ outl((1<<4), REG_SET(HW_TIMER0_TCR));
+ outl((1<<4), REG_CLR(HW_TIMER0_TCR));
+ outl((1<<0), REG_SET(HW_TIMER0_TCR));
+}
diff --git a/bsp/asm9260t/platform/timer0.h b/bsp/asm9260t/platform/timer0.h
new file mode 100644
index 0000000000000000000000000000000000000000..338ef05816fded842c5f2e2c024da1dfbb894ee7
--- /dev/null
+++ b/bsp/asm9260t/platform/timer0.h
@@ -0,0 +1,34 @@
+/*
+ * File : timer0.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-29 ArdaFu first version
+ */
+
+#ifndef __HW_TIMER0_H__
+#define __HW_TIMER0_H__
+////////////////////////////////////////////////////////////////////////////////
+#include "stdint.h"
+
+extern void hw_timer0_init(void);
+
+////////////////////////////////////////////////////////////////////////////////
+#endif /* __HW_TIMER0_H__ */
+
diff --git a/bsp/asm9260t/platform/uart.c b/bsp/asm9260t/platform/uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f39ef9c1158799c15e3e5038873856d69a8041d
--- /dev/null
+++ b/bsp/asm9260t/platform/uart.c
@@ -0,0 +1,112 @@
+/*
+ * File : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2015-04-14 ArdaFu first version
+ */
+
+#include "asm9260t.h"
+#include "rtthread.h"
+#include "uart.h"
+
+void Hw_UartDisable(HW_USART_TypeDef* uartBase)
+{
+ uartBase->INTR[R_CLR] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_TXIEN | ASM_UART_INTR_RTIS;
+ uartBase->CTRL2[R_CLR] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE;
+}
+
+void Hw_UartEnable(HW_USART_TypeDef* uartBase)
+{
+ uartBase->CTRL2[R_CLR] = 0x0000C000UL; //clear CTSEN and RTSEN
+ uartBase->CTRL2[R_SET] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE | ASM_UART_CTRL2_USARTEN;
+ uartBase->INTR[R_SET] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_RTIEN;
+}
+
+void Hw_UartReset(HW_USART_TypeDef* uartBase)
+{
+ uartBase->CTRL0[R_CLR] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
+ uartBase->CTRL0[R_SET] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
+}
+
+void Hw_UartConfig(HW_USART_TypeDef* uartBase,int baudRate, int dataBits, int stopBits,int parity)
+{
+ rt_uint32_t mode = ASM_UART_LINECTRL_FEN;
+
+ switch (dataBits)
+ {
+ case 8:
+ mode |= ASM_UART_LINECTRL_WLEN8;
+ break;
+ case 7:
+ mode |= ASM_UART_LINECTRL_WLEN7;
+ break;
+ case 6:
+ mode |= ASM_UART_LINECTRL_WLEN6;
+ break;
+ case 5:
+ mode |= ASM_UART_LINECTRL_WLEN5;
+ break;
+ default:
+ mode |= ASM_UART_LINECTRL_WLEN8;
+ break;
+ }
+
+ switch (stopBits)
+ {
+ case 2:
+ mode |= ASM_UART_LINECTRL_STP2;
+ break;
+ case 1:
+ default:
+ break;
+ }
+
+ switch (parity)
+ {
+ case 1:
+ mode |= ASM_UART_LINECTRL_PEN;
+ break;
+ case 2:
+ mode |= ASM_UART_LINECTRL_PEN | ASM_UART_LINECTRL_EPS;
+ break;
+ case 0:
+ default:
+ break;
+ }
+ //16bit nBaudDivint
+ mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVINT_MASK) << 10;
+ //6bit nNaudDivfrac
+ mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVFRAC_MASK) << 8;
+
+
+ uartBase->LINECTRL[R_VAL] = mode;
+}
+
+void Hw_UartInit(int index)
+{
+ // uart0 = bit11, uart9 = bit20
+ int ctrl_bit = index + 11;
+ outl(1UL<
+
+
+ 2
+
+ Debug
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 22
+ 1
+ 1
+
+
+
+
+
+
+
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+
+ ICCARM
+ 2
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+ 0
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+ CUSTOM
+ 3
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+ BICOMP
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+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 1
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 22
+ 1
+ 0
+
+
+
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+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 31
+ 1
+ 0
+
+
+
+
+
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+
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+
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+
+
+ AARM
+ 2
+
+ 9
+ 1
+ 0
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 16
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+ IARCHIVE
+ 0
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+ 0
+ 1
+ 0
+
+
+
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+ BILINK
+ 0
+
+
+
+
+
+
diff --git a/bsp/asm9260t/template.eww b/bsp/asm9260t/template.eww
new file mode 100644
index 0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028
--- /dev/null
+++ b/bsp/asm9260t/template.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\template.ewp
+
+
+
+
+
diff --git a/bsp/asm9260t/template.uvopt b/bsp/asm9260t/template.uvopt
new file mode 100644
index 0000000000000000000000000000000000000000..68b788c6b03eae253881696b9da00c758d566247
--- /dev/null
+++ b/bsp/asm9260t/template.uvopt
@@ -0,0 +1,175 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rtthread
+ 0x4
+ ARM-ADS
+
+ 18432000
+
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Listings\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 16
+
+
+ 0
+ Datasheet
+ DATASHTS\ATMEL\AT91SAM9260_DS.PDF
+
+
+ 1
+ Summary
+ DATASHTS\ATMEL\AT91SAM9260_DC.PDF
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 0
+ 1
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+ 1
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+ 1
+ 1
+ 0
+ 0
+ 5
+
+
+
+
+
+
+
+
+
+ .\jlink\at91sam9260.ini
+ Segger\JLTAgdi.dll
+
+
+
+ 0
+ JLTAgdi
+ -O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0
+
+
+ 0
+ UL2ARM
+ -UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
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+ 0
+ 0
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+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
diff --git a/bsp/asm9260t/template.uvproj b/bsp/asm9260t/template.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..2e357d9fdf723445249893949033662d4988cdce
--- /dev/null
+++ b/bsp/asm9260t/template.uvproj
@@ -0,0 +1,408 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rtthread
+ 0x4
+ ARM-ADS
+
+
+ AT91SAM9260
+ Atmel
+ IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S)
+
+ "STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code")
+ UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)
+ 4210
+ AT91SAM9260.H
+
+
+
+
+
+
+
+
+
+
+ 0
+ 0
+
+
+
+ Atmel\SAM9260\
+ Atmel\SAM9260\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ template
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\Listings\
+ 1
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+ 0
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+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARM.DLL
+ -cAT91SAM9260
+ DARMATS9.DLL
+ -p91SAM9260
+ SARM.DLL
+
+ TARMATS9.DLL
+ -p91SAM9260
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
+
+ 0
+ 5
+
+
+
+
+
+
+
+
+
+
+
+
+ .\jlink\at91sam9260.ini
+ Segger\JLTAgdi.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 4096
+
+ 1
+ BIN\UL2ARM.DLL
+ "" ()
+ .\jlink\at91sam9260.ini
+
+
+
+ 0
+
+
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+ 1
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ ARM926EJ-S
+
+ 0
+ 0
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+ 1
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+ 0
+ 1
+ 0
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+ 0
+ 0
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+ 1
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+ 0x800000
+
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+ 1
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+
+ 1
+ 0x0
+ 0x0
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+ 1
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+ 0x8000
+
+
+ 1
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+ 0
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+ 0x1800000
+
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+
+
+
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+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x20000000
+ 0x20800000
+
+ .\at91sam9260_ram.scat
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c
index 0d15781c6123d19e41d848cb8c07f0025dd4ed88..014290c61e4b058ffc6d59286bd97ab42f4ce091 100644
--- a/bsp/at91sam9260/platform/interrupt.c
+++ b/bsp/at91sam9260/platform/interrupt.c
@@ -146,7 +146,7 @@ void at91_aic_init(rt_uint32_t *priority)
*/
for (i = 0; i < AIC_IRQS; i++) {
/* Put irq number in Source Vector Register: */
- at91_sys_write(AT91_AIC_SVR(i), i);
+ at91_sys_write(AT91_AIC_SVR(i), i); // no-used
/* Active Low interrupt, with the specified priority */
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
//AT91_AIC_SRCTYPE_FALLING
@@ -201,12 +201,11 @@ static void at91_gpio_irq_init()
*/
void rt_hw_interrupt_init(void)
{
- rt_int32_t i;
register rt_uint32_t idx;
rt_uint32_t *priority = at91sam9260_default_irq_priority;
- at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
- | (1 << AT91SAM9260_ID_IRQ2);
+ at91_extern_irq = (1UL << AT91SAM9260_ID_IRQ0) | (1UL << AT91SAM9260_ID_IRQ1)
+ | (1UL << AT91SAM9260_ID_IRQ2);
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
@@ -341,7 +340,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
/*@}*/
-
+/*
static int at91_aic_set_type(unsigned irq, unsigned type)
{
unsigned int smr, srctype;
@@ -354,13 +353,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
srctype = AT91_AIC_SRCTYPE_RISING;
break;
case IRQ_TYPE_LEVEL_LOW:
- if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
+ // only supported on external interrupts
+ if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))
srctype = AT91_AIC_SRCTYPE_LOW;
else
return -1;
break;
case IRQ_TYPE_EDGE_FALLING:
- if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
+ // only supported on external interrupts
+ if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))
srctype = AT91_AIC_SRCTYPE_FALLING;
else
return -1;
@@ -373,54 +374,36 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
return 0;
}
-
-rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq, rt_uint32_t* id)
+*/
+rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
{
- rt_uint32_t irqstat;
+ //volatile rt_uint32_t irqstat;
+ rt_uint32_t id;
if (fiq_irq == INT_FIQ)
- {
- *id = 0;
- }
- else //IRQ
- {
- /* get irq number */
- *id = (rt_uint32_t)at91_sys_read(AT91_AIC_IVR);
- /* clear pending register */
- irqstat = (rt_uint32_t)at91_sys_read(AT91_AIC_ISR);
- }
+ return 0;
- return irqstat;
+ //IRQ
+ /* AIC need this dummy read */
+ at91_sys_read(AT91_AIC_IVR);
+ /* clear pending register */
+ id = at91_sys_read(AT91_AIC_ISR);
+
+ return id;
}
-void rt_hw_interrupt_ack(rt_uint32_t fiq_irq)
+void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
{
+ /* new FIQ generation */
if (fiq_irq == INT_FIQ)
- {
- /* new FIQ generation */
+ return;
- }
- else
- {
- // EIOCR must be write any value after interrupt,
+ /* new IRQ generation */
+ // EIOCR must be write any value after interrupt,
// or else can't response next interrupt
- /* new IRQ generation */
- at91_sys_write(AT91_AIC_EOICR, 0x55555555);
- }
+ at91_sys_write(AT91_AIC_EOICR, 0x0);
}
-
-
-
-
-
-
-
-
-
-
-
-
#ifdef RT_USING_FINSH
void list_irq(void)
{
diff --git a/bsp/at91sam9260/platform/interrupt.h b/bsp/at91sam9260/platform/interrupt.h
index 36111c4a8c55394c9d3691da1af0fbd460049163..7780e7a3a880270355298536baefd2ffd3504586 100644
--- a/bsp/at91sam9260/platform/interrupt.h
+++ b/bsp/at91sam9260/platform/interrupt.h
@@ -1,17 +1,26 @@
/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
- * 2013-07-06 Bernard first version
+ * 2015-04-14 ArdaFu first version
*/
-
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
@@ -19,7 +28,4 @@
#define INT_FIQ 0x01
-rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq, rt_uint32_t* id);
-void rt_hw_interrupt_ack(rt_uint32_t fiq_irq);
-
#endif
diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c
index 77816a2aa6aa6e1460566ea2f9bce4384cdf22dc..726f22a557aae177ace1bd7e8f825ac10754d8f2 100644
--- a/libcpu/arm/arm926/trap.c
+++ b/libcpu/arm/arm926/trap.c
@@ -25,8 +25,9 @@
#include
#include
-#include
+#define INT_IRQ 0x00
+#define INT_FIQ 0x01
extern struct rt_thread *rt_current_thread;
#ifdef RT_USING_FINSH
@@ -171,24 +172,18 @@ void rt_hw_trap_resv(struct rt_hw_register *regs)
rt_hw_cpu_shutdown();
}
-
-
+extern struct rt_irq_desc irq_desc[];
+extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
+extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
+
void rt_hw_trap_irq()
{
rt_isr_handler_t isr_func;
- rt_uint32_t irqstat;
rt_uint32_t irq;
void *param;
- extern struct rt_irq_desc irq_desc[];
/* get irq number */
- irqstat = rt_hw_interrupt_get_active(INT_IRQ, &irq);
- if (irqstat == 0)
- {
- rt_kprintf("No interrupt occur\n");
- rt_hw_interrupt_ack(INT_IRQ);
- return;
- }
+ irq = rt_hw_interrupt_get_active(INT_IRQ);
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
@@ -197,26 +192,20 @@ void rt_hw_trap_irq()
/* turn to interrupt service routine */
isr_func(irq, param);
- rt_hw_interrupt_ack(INT_IRQ);
+ rt_hw_interrupt_ack(INT_IRQ, irq);
+#ifdef RT_USING_INTERRUPT_INFO
irq_desc[irq].counter ++;
+#endif
}
void rt_hw_trap_fiq()
{
rt_isr_handler_t isr_func;
- rt_uint32_t irqstat;
rt_uint32_t irq;
void *param;
- extern struct rt_irq_desc irq_desc[];
/* get irq number */
- irqstat = rt_hw_interrupt_get_active(INT_FIQ, &irq);
- if (irqstat == 0)
- {
- rt_kprintf("No interrupt occur\n");
- rt_hw_interrupt_ack(INT_FIQ);
- return;
- }
+ irq = rt_hw_interrupt_get_active(INT_FIQ);
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
@@ -225,6 +214,8 @@ void rt_hw_trap_fiq()
/* turn to interrupt service routine */
isr_func(irq, param);
- rt_hw_interrupt_ack(INT_FIQ);
+ rt_hw_interrupt_ack(INT_FIQ, irq);
+#ifdef RT_USING_INTERRUPT_INFO
irq_desc[irq].counter ++;
+#endif
}